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reserve/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak5
2020-06-09 15:54:49 +08:00

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if {[file exists gate_work]} {
vdel -lib gate_work -all
}
vlib gate_work
vmap work gate_work
vlog -vlog01compat -work work +incdir+. {dpwm_8_1200mv_85c_slow.vo}
vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v}
vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb
add wave *
view structure
view signals
run -all