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reserve/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak3
2020-06-09 15:54:49 +08:00

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if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip {F:/Code/FPGA/reserve/dpwm/ip/my_pll.v}
vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db {F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll.v}
vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_tb.v}
vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v}
vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_tb
add wave *
view structure
view signals
run -all