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reserve/timer_pwm/db/timer_pwm.sta.qmsg
sansi fef5d7bde7 first commit
2020-06-09 15:54:49 +08:00

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1541231012664 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541231012677 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 03 15:43:32 2018 " "Processing started: Sat Nov 03 15:43:32 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541231012677 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1541231012677 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta timer_pwm -c timer_pwm " "Command: quartus_sta timer_pwm -c timer_pwm" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1541231012677 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #2" { } { } 0 0 "qsta_default_script.tcl version: #2" 0 0 "Timing Analyzer" 0 0 1541231012855 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1541231013072 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1541231013072 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013140 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013140 ""}
{ "Info" "ISTA_SDC_FOUND" "timer_pwm.out.sdc " "Reading SDC File: 'timer_pwm.out.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1541231013317 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "timer_pwm.out.sdc 41 clk_tim port " "Ignored filter at timer_pwm.out.sdc(41): clk_tim could not be matched with a port" { } { { "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" "" { Text "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" 41 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1541231013319 ""}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock timer_pwm.out.sdc 41 Argument <targets> is an empty collection " "Ignored create_clock at timer_pwm.out.sdc(41): Argument <targets> is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name \{clk_tim\} -period 3.000 -waveform \{ 0.000 1.500 \} \[get_ports \{clk_tim\}\] " "create_clock -name \{clk_tim\} -period 3.000 -waveform \{ 0.000 1.500 \} \[get_ports \{clk_tim\}\]" { } { { "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" "" { Text "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" 41 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1541231013320 ""} } { { "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" "" { Text "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" 41 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1541231013320 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "generated clocks \"derive_pll_clocks -create_base_clocks\" " "No user constrained generated clocks found in the design. Calling \"derive_pll_clocks -create_base_clocks\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013322 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_clock -period 20.000 -waveform \{0.000 10.000\} -name clk clk " "create_clock -period 20.000 -waveform \{0.000 10.000\} -name clk clk" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1541231013323 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{my_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 4 -duty_cycle 50.00 -name \{my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{my_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 4 -duty_cycle 50.00 -name \{my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1541231013323 ""} } { } 0 332110 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541231013323 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013323 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1541231013323 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1541231013324 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541231013324 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1541231013325 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1541231013335 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.652 " "Worst-case setup slack is 0.652" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013351 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013351 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.652 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.652 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013351 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013351 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.762 " "Worst-case hold slack is 0.762" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013354 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013354 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.762 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.762 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013354 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013354 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541231013357 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541231013361 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 2.222 " "Worst-case minimum pulse width slack is 2.222" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013364 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013364 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.222 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.222 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013364 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.934 0.000 clk " " 9.934 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013364 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013364 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1541231013389 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1541231013411 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1541231013607 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541231013665 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.953 " "Worst-case setup slack is 0.953" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013675 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013675 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.953 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.953 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013675 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013675 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.705 " "Worst-case hold slack is 0.705" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013679 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013679 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.705 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.705 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013679 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013679 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541231013682 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541231013686 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 2.220 " "Worst-case minimum pulse width slack is 2.220" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.220 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.220 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.943 0.000 clk " " 9.943 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013689 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013689 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1541231013717 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541231013843 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 3.141 " "Worst-case setup slack is 3.141" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013848 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013848 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.141 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.141 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013848 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013848 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.304 " "Worst-case hold slack is 0.304" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013856 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013856 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.304 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.304 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013856 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013856 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541231013861 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541231013865 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 2.298 " "Worst-case minimum pulse width slack is 2.298" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013868 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013868 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.298 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.298 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013868 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.594 0.000 clk " " 9.594 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013868 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013868 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1541231014280 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1541231014281 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4774 " "Peak virtual memory: 4774 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541231014337 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 03 15:43:34 2018 " "Processing ended: Sat Nov 03 15:43:34 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541231014337 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541231014337 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541231014337 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1541231014337 ""}
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