53 lines
32 KiB
Plaintext
53 lines
32 KiB
Plaintext
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1544266265102 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1544266265103 ""}
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{ "Info" "IMPP_MPP_USER_DEVICE" "dpwm_shake EP4CE10F17C8 " "Selected device EP4CE10F17C8 for design \"dpwm_shake\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1544266265143 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1544266265222 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1544266265222 ""}
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{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated\|wire_pll1_clk\[0\] 49 10 0 0 " "Implementing clock multiplication of 49, clock division of 10, and phase shift of 0 degrees (0 ps) for pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pwm_pll_altpll.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v" 50 -1 0 } } { "" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 78 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1544266265280 ""} } { { "db/pwm_pll_altpll.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v" 50 -1 0 } } { "" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 78 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1544266265280 ""}
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{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1544266265377 ""}
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{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C8 " "Device EP4CE6F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1544266265609 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Device EP4CE15F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1544266265609 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Device EP4CE22F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1544266265609 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1544266265609 ""}
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{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 205 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1544266265627 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 207 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1544266265627 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 209 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1544266265627 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 211 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1544266265627 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 213 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1544266265627 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1544266265627 ""}
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{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1544266265632 ""}
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{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "17 17 " "No exact pin location assignment(s) for 17 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1544266265920 ""}
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{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "The Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "The Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1544266266161 ""}
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{ "Info" "ISTA_SDC_FOUND" "dpwm_shake.out.sdc " "Reading SDC File: 'dpwm_shake.out.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1544266266162 ""}
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{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "dpwm_shake:dpwm_shake\|cnt\[0\] " "Node: dpwm_shake:dpwm_shake\|cnt\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch dpwm_shake:dpwm_shake\|pwm_out dpwm_shake:dpwm_shake\|cnt\[0\] " "Latch dpwm_shake:dpwm_shake\|pwm_out is being clocked by dpwm_shake:dpwm_shake\|cnt\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1544266266165 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1544266266165 "|dpwm_top|dpwm_shake:dpwm_shake|cnt[0]"}
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{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000 " "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1544266266166 ""} } { } 0 332056 "%1!s!" 0 0 "Fitter" 0 -1 1544266266166 ""}
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{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "clk_0 (Rise) clk_0 (Rise) setup and hold " "From clk_0 (Rise) to clk_0 (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1544266266167 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1544266266167 ""}
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{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1544266266168 ""}
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{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1544266266168 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1544266266168 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 4.500 clk_0 " " 4.500 clk_0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1544266266168 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1544266266168 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1) " "Automatically promoted node pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} } { { "db/pwm_pll_altpll.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v" 92 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 78 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1544266266185 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rst_all " "Destination node rst_all" { } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v" 21 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 99 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~0 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~0" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 156 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~1 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~1" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 157 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|shakenum~2 " "Destination node dpwm_shake:dpwm_shake\|shakenum~2" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 25 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 165 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~2 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~2" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 166 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~3 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~3" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 167 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~4 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~4" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 168 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~5 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~5" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 169 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~6 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~6" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 170 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~7 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~7" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 171 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Design Software" 0 -1 1544266266185 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1544266266185 ""} } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v" 12 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 182 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1544266266185 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_all " "Automatically promoted node rst_all " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1544266266186 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|shakenum~0 " "Destination node dpwm_shake:dpwm_shake\|shakenum~0" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 25 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 158 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266186 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|shakenum~1 " "Destination node dpwm_shake:dpwm_shake\|shakenum~1" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 25 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 164 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266186 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1544266266186 ""} } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v" 21 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 99 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1544266266186 ""}
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{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1544266266392 ""}
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{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1544266266392 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1544266266393 ""}
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{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1544266266393 ""}
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{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1544266266394 ""}
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{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1544266266394 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1544266266394 ""}
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{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1544266266394 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1544266266395 ""}
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{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1544266266395 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1544266266395 ""}
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{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "15 unused 2.5V 13 2 0 " "Number of I/O pins in group: 15 (unused VREF, 2.5V VCCIO, 13 input, 2 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1544266266397 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1544266266397 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1544266266397 ""}
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{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 12 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 18 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 18 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 26 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 27 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 27 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 25 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 25 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 13 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 26 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 26 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1544266266398 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1544266266398 ""}
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{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544266266420 ""}
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{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1544266266433 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1544266266965 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544266267020 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1544266267038 ""}
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{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1544266267805 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544266267805 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1544266268067 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11" { } { { "loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11"} { { 12 { 0 ""} 0 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1544266268527 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1544266268527 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1544266268752 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1544266268752 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1544266268752 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544266268755 ""}
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{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.16 " "Total time spent on timing analysis during the Fitter is 0.16 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1544266268892 ""}
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{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1544266268899 ""}
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{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1544266269038 ""}
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{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1544266269038 ""}
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{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1544266269184 ""}
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{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544266269558 ""}
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{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/Code/FPGA/reserve/dpwm_shake/output_files/dpwm_shake.fit.smsg " "Generated suppressed messages file F:/Code/FPGA/reserve/dpwm_shake/output_files/dpwm_shake.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1544266269897 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 9 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5560 " "Peak virtual memory: 5560 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544266270259 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 08 18:51:10 2018 " "Processing ended: Sat Dec 08 18:51:10 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544266270259 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544266270259 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544266270259 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1544266270259 ""}
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