200 lines
5.0 KiB
Plaintext
200 lines
5.0 KiB
Plaintext
|dpwm_top
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clk => clk.IN2
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rst_n => rst_all.IN1
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rst_n => areset.IN1
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control[0] => control[0].IN1
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control[1] => control[1].IN1
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control[2] => control[2].IN1
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control[3] => control[3].IN1
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control[4] => control[4].IN1
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control[5] => control[5].IN1
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control[6] => control[6].IN1
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control[7] => control[7].IN1
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control[8] => control[8].IN1
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control[9] => control[9].IN1
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control[10] => control[10].IN1
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control[11] => control[11].IN1
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control[12] => control[12].IN1
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pwm_out << dpwm_shake:dpwm_shake.pwm_out
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pwm_out_n << dpwm_shake:dpwm_shake.pwm_out_n
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|dpwm_top|pwm_pll:pwm_pll
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areset => areset.IN1
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inclk0 => sub_wire1[0].IN1
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c0 <= altpll:altpll_component.clk
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locked <= altpll:altpll_component.locked
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|dpwm_top|pwm_pll:pwm_pll|altpll:altpll_component
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inclk[0] => pwm_pll_altpll:auto_generated.inclk[0]
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inclk[1] => pwm_pll_altpll:auto_generated.inclk[1]
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fbin => ~NO_FANOUT~
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pllena => ~NO_FANOUT~
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clkswitch => ~NO_FANOUT~
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areset => pwm_pll_altpll:auto_generated.areset
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pfdena => ~NO_FANOUT~
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clkena[0] => ~NO_FANOUT~
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clkena[1] => ~NO_FANOUT~
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clkena[2] => ~NO_FANOUT~
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clkena[3] => ~NO_FANOUT~
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clkena[4] => ~NO_FANOUT~
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clkena[5] => ~NO_FANOUT~
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extclkena[0] => ~NO_FANOUT~
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extclkena[1] => ~NO_FANOUT~
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extclkena[2] => ~NO_FANOUT~
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extclkena[3] => ~NO_FANOUT~
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scanclk => ~NO_FANOUT~
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scanclkena => ~NO_FANOUT~
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scanaclr => ~NO_FANOUT~
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scanread => ~NO_FANOUT~
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scanwrite => ~NO_FANOUT~
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scandata => ~NO_FANOUT~
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phasecounterselect[0] => ~NO_FANOUT~
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phasecounterselect[1] => ~NO_FANOUT~
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phasecounterselect[2] => ~NO_FANOUT~
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phasecounterselect[3] => ~NO_FANOUT~
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phaseupdown => ~NO_FANOUT~
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phasestep => ~NO_FANOUT~
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configupdate => ~NO_FANOUT~
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fbmimicbidir <> <GND>
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clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
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clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
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clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
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clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
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clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
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extclk[0] <= <GND>
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extclk[1] <= <GND>
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extclk[2] <= <GND>
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extclk[3] <= <GND>
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clkbad[0] <= <GND>
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clkbad[1] <= <GND>
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enable1 <= <GND>
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enable0 <= <GND>
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activeclock <= <GND>
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clkloss <= <GND>
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locked <= pwm_pll_altpll:auto_generated.locked
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scandataout <= <GND>
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scandone <= <GND>
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sclkout0 <= <GND>
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sclkout1 <= <GND>
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phasedone <= <GND>
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vcooverrange <= <GND>
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vcounderrange <= <GND>
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fbout <= <GND>
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fref <= <GND>
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icdrclk <= <GND>
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|dpwm_top|pwm_pll:pwm_pll|altpll:altpll_component|pwm_pll_altpll:auto_generated
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areset => pll_lock_sync.ACLR
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areset => pll1.ARESET
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clk[0] <= pll1.CLK
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clk[1] <= pll1.CLK1
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clk[2] <= pll1.CLK2
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clk[3] <= pll1.CLK3
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clk[4] <= pll1.CLK4
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inclk[0] => pll1.CLK
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inclk[1] => pll1.CLK1
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locked <= locked.DB_MAX_OUTPUT_PORT_TYPE
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|dpwm_top|dpwm_shake:dpwm_shake
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clk => ~NO_FANOUT~
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clk_0 => shakenum[0].CLK
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clk_0 => shakenum[1].CLK
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clk_0 => shakenum[2].CLK
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clk_0 => shakenum[3].CLK
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clk_0 => new_duty[0].CLK
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clk_0 => new_duty[1].CLK
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clk_0 => new_duty[2].CLK
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clk_0 => new_duty[3].CLK
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clk_0 => new_duty[4].CLK
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clk_0 => new_duty[5].CLK
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clk_0 => new_duty[6].CLK
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clk_0 => new_duty[7].CLK
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clk_0 => new_duty[8].CLK
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clk_0 => new_duty[9].CLK
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clk_0 => new_duty[10].CLK
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clk_0 => shake_count[0].CLK
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clk_0 => shake_count[1].CLK
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clk_0 => cnt[0].CLK
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clk_0 => cnt[1].CLK
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clk_0 => cnt[2].CLK
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clk_0 => cnt[3].CLK
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clk_0 => cnt[4].CLK
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clk_0 => cnt[5].CLK
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clk_0 => cnt[6].CLK
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clk_0 => cnt[7].CLK
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clk_0 => cnt[8].CLK
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clk_0 => cnt[9].CLK
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clk_0 => cnt[10].CLK
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clk_0 => shake_ctr[0].CLK
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clk_0 => shake_ctr[1].CLK
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clk_0 => cat_duty[0].CLK
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clk_0 => cat_duty[1].CLK
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clk_0 => cat_duty[2].CLK
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clk_0 => cat_duty[3].CLK
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clk_0 => cat_duty[4].CLK
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clk_0 => cat_duty[5].CLK
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clk_0 => cat_duty[6].CLK
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clk_0 => cat_duty[7].CLK
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clk_0 => cat_duty[8].CLK
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clk_0 => cat_duty[9].CLK
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clk_0 => cat_duty[10].CLK
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clk_0 => cat_duty[11].CLK
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rst_n => cat_duty.OUTPUTSELECT
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rst_n => cat_duty.OUTPUTSELECT
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rst_n => cat_duty.OUTPUTSELECT
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rst_n => cat_duty.OUTPUTSELECT
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rst_n => cat_duty.OUTPUTSELECT
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rst_n => cat_duty.OUTPUTSELECT
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rst_n => cat_duty.OUTPUTSELECT
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rst_n => cat_duty.OUTPUTSELECT
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rst_n => cat_duty.OUTPUTSELECT
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rst_n => cat_duty.OUTPUTSELECT
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rst_n => cat_duty.OUTPUTSELECT
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rst_n => shake_ctr.OUTPUTSELECT
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rst_n => shake_ctr.OUTPUTSELECT
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rst_n => cnt[0].ACLR
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rst_n => cnt[1].ACLR
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rst_n => cnt[2].ACLR
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rst_n => cnt[3].ACLR
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rst_n => cnt[4].ACLR
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rst_n => cnt[5].ACLR
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rst_n => cnt[6].ACLR
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rst_n => cnt[7].ACLR
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rst_n => cnt[8].ACLR
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rst_n => cnt[9].ACLR
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rst_n => cnt[10].ACLR
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rst_n => shakenum.OUTPUTSELECT
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rst_n => shakenum.OUTPUTSELECT
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rst_n => shakenum.OUTPUTSELECT
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rst_n => shake_count[0].ACLR
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rst_n => shake_count[1].ACLR
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control[0] => shake_ctr.DATAA
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control[1] => shake_ctr.DATAA
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control[2] => cat_duty.DATAA
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control[3] => cat_duty.DATAA
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control[4] => cat_duty.DATAA
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control[5] => cat_duty.DATAA
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control[6] => cat_duty.DATAA
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control[7] => cat_duty.DATAA
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control[8] => cat_duty.DATAA
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control[9] => cat_duty.DATAA
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control[10] => cat_duty.DATAA
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control[11] => cat_duty.DATAA
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control[12] => cat_duty.DATAA
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dead_zone[0] => ~NO_FANOUT~
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dead_zone[1] => ~NO_FANOUT~
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dead_zone[2] => ~NO_FANOUT~
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dead_zone[3] => ~NO_FANOUT~
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dead_zone[4] => ~NO_FANOUT~
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dead_zone[5] => ~NO_FANOUT~
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dead_zone[6] => ~NO_FANOUT~
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dead_zone[7] => ~NO_FANOUT~
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pwm_out <= pwm_out$latch.DB_MAX_OUTPUT_PORT_TYPE
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pwm_out_n <= pwm_out$latch.DB_MAX_OUTPUT_PORT_TYPE
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