44 lines
20 KiB
Plaintext
44 lines
20 KiB
Plaintext
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544266274661 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544266274675 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 08 18:51:14 2018 " "Processing started: Sat Dec 08 18:51:14 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544266274675 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1544266274675 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta dpwm_shake -c dpwm_shake " "Command: quartus_sta dpwm_shake -c dpwm_shake" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1544266274675 ""}
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{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1544266274878 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1544266275089 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1544266275089 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275170 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275171 ""}
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{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "The Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "The Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Timing Analyzer" 0 -1 1544266275346 ""}
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{ "Info" "ISTA_SDC_FOUND" "dpwm_shake.out.sdc " "Reading SDC File: 'dpwm_shake.out.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1544266275361 ""}
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{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "dpwm_shake:dpwm_shake\|cnt\[0\] " "Node: dpwm_shake:dpwm_shake\|cnt\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch dpwm_shake:dpwm_shake\|pwm_out dpwm_shake:dpwm_shake\|cnt\[0\] " "Latch dpwm_shake:dpwm_shake\|pwm_out is being clocked by dpwm_shake:dpwm_shake\|cnt\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1544266275366 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1544266275366 "|dpwm_top|dpwm_shake:dpwm_shake|cnt[0]"}
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{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000 " "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1544266275367 ""} } { } 0 332056 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1544266275367 ""}
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{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "clk_0 (Rise) clk_0 (Rise) setup and hold " "From clk_0 (Rise) to clk_0 (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1544266275367 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1544266275367 ""}
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{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1544266275368 ""}
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{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1544266275377 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.467 " "Worst-case setup slack is 0.467" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.467 0.000 clk_0 " " 0.467 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275403 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275403 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.452 " "Worst-case hold slack is 0.452" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275406 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275406 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.452 0.000 clk_0 " " 0.452 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275406 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275406 ""}
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{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544266275410 ""}
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{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544266275413 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.945 " "Worst-case minimum pulse width slack is 1.945" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.945 0.000 clk_0 " " 1.945 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275415 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275415 ""}
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{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1544266275452 ""}
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{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1544266275474 ""}
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{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1544266275704 ""}
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{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "dpwm_shake:dpwm_shake\|cnt\[0\] " "Node: dpwm_shake:dpwm_shake\|cnt\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch dpwm_shake:dpwm_shake\|pwm_out dpwm_shake:dpwm_shake\|cnt\[0\] " "Latch dpwm_shake:dpwm_shake\|pwm_out is being clocked by dpwm_shake:dpwm_shake\|cnt\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1544266275763 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1544266275763 "|dpwm_top|dpwm_shake:dpwm_shake|cnt[0]"}
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{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000 " "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1544266275764 ""} } { } 0 332056 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1544266275764 ""}
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{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "clk_0 (Rise) clk_0 (Rise) setup and hold " "From clk_0 (Rise) to clk_0 (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1544266275764 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1544266275764 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.812 " "Worst-case setup slack is 0.812" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275774 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275774 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.812 0.000 clk_0 " " 0.812 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275774 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275774 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.401 " "Worst-case hold slack is 0.401" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.401 0.000 clk_0 " " 0.401 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275779 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275779 ""}
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{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544266275783 ""}
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{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544266275787 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.920 " "Worst-case minimum pulse width slack is 1.920" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275790 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275790 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.920 0.000 clk_0 " " 1.920 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275790 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275790 ""}
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{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1544266275818 ""}
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{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "dpwm_shake:dpwm_shake\|cnt\[0\] " "Node: dpwm_shake:dpwm_shake\|cnt\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch dpwm_shake:dpwm_shake\|pwm_out dpwm_shake:dpwm_shake\|cnt\[0\] " "Latch dpwm_shake:dpwm_shake\|pwm_out is being clocked by dpwm_shake:dpwm_shake\|cnt\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1544266275941 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1544266275941 "|dpwm_top|dpwm_shake:dpwm_shake|cnt[0]"}
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{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000 " "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1544266275941 ""} } { } 0 332056 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1544266275941 ""}
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{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "clk_0 (Rise) clk_0 (Rise) setup and hold " "From clk_0 (Rise) to clk_0 (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1544266275941 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1544266275941 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "setup 2.748 " "Worst-case setup slack is 2.748" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275945 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275945 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.748 0.000 clk_0 " " 2.748 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275945 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275945 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.186 " "Worst-case hold slack is 0.186" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275949 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275949 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 clk_0 " " 0.186 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275949 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275949 ""}
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{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544266275954 ""}
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{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544266275957 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 2.025 " "Worst-case minimum pulse width slack is 2.025" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.025 0.000 clk_0 " " 2.025 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275960 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275960 ""}
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{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1544266276369 ""}
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{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1544266276379 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 17 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4776 " "Peak virtual memory: 4776 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544266276427 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 08 18:51:16 2018 " "Processing ended: Sat Dec 08 18:51:16 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544266276427 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544266276427 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544266276427 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1544266276427 ""}
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