32 lines
1.4 KiB
Plaintext
32 lines
1.4 KiB
Plaintext
--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=16 ONE_INPUT_IS_CONSTANT="YES" dataa datab result
|
|
--VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END
|
|
|
|
|
|
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
|
|
-- Your use of Intel Corporation's design tools, logic functions
|
|
-- and other software and tools, and its AMPP partner logic
|
|
-- functions, and any output files from any of the foregoing
|
|
-- (including device programming or simulation files), and any
|
|
-- associated documentation or information are expressly subject
|
|
-- to the terms and conditions of the Intel Program License
|
|
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
-- the Intel FPGA IP License Agreement, or other applicable license
|
|
-- agreement, including, without limitation, that your use is for
|
|
-- the sole purpose of programming logic devices manufactured by
|
|
-- Intel and sold by Intel or its authorized distributors. Please
|
|
-- refer to the applicable agreement for further details.
|
|
|
|
|
|
|
|
--synthesis_resources = lut 16
|
|
SUBDESIGN add_sub_pgh
|
|
(
|
|
dataa[15..0] : input;
|
|
datab[15..0] : input;
|
|
result[15..0] : output;
|
|
)
|
|
BEGIN
|
|
result[] = dataa[] + datab[];
|
|
END;
|
|
--VALID FILE
|