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reserve/spwm/db/spwm.map.qmsg
sansi fef5d7bde7 first commit
2020-06-09 15:54:49 +08:00

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544446499185 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544446499197 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 10 20:54:59 2018 " "Processing started: Mon Dec 10 20:54:59 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544446499197 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446499197 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spwm -c spwm " "Command: quartus_map --read_settings_files=on --write_settings_files=off spwm -c spwm" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446499198 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1544446499818 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1544446499818 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/spwm.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/spwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 spwm " "Found entity 1: spwm" { } { { "rtl/spwm.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/spwm.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446512746 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446512746 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testbench/spwm_tb.v 1 1 " "Found 1 design units, including 1 entities, in source file testbench/spwm_tb.v" { { "Info" "ISGN_ENTITY_NAME" "1 spwm_tb " "Found entity 1: spwm_tb" { } { { "testbench/spwm_tb.v" "" { Text "F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446512750 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446512750 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spwm_sin.v 1 1 " "Found 1 design units, including 1 entities, in source file spwm_sin.v" { { "Info" "ISGN_ENTITY_NAME" "1 spwm_sin " "Found entity 1: spwm_sin" { } { { "spwm_sin.v" "" { Text "F:/Code/FPGA/reserve/spwm/spwm_sin.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446512755 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446512755 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/modulation.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/modulation.v" { { "Info" "ISGN_ENTITY_NAME" "1 modulation " "Found entity 1: modulation" { } { { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446512758 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446512758 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "spwm " "Elaborating entity \"spwm\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1544446512939 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spwm_sin spwm_sin:spwm_sin " "Elaborating entity \"spwm_sin\" for hierarchy \"spwm_sin:spwm_sin\"" { } { { "rtl/spwm.v" "spwm_sin" { Text "F:/Code/FPGA/reserve/spwm/rtl/spwm.v" 70 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446512949 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram spwm_sin:spwm_sin\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"spwm_sin:spwm_sin\|altsyncram:altsyncram_component\"" { } { { "spwm_sin.v" "altsyncram_component" { Text "F:/Code/FPGA/reserve/spwm/spwm_sin.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513024 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "spwm_sin:spwm_sin\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"spwm_sin:spwm_sin\|altsyncram:altsyncram_component\"" { } { { "spwm_sin.v" "" { Text "F:/Code/FPGA/reserve/spwm/spwm_sin.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513030 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "spwm_sin:spwm_sin\|altsyncram:altsyncram_component " "Instantiated megafunction \"spwm_sin:spwm_sin\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file sin9bit_1024.mif " "Parameter \"init_file\" = \"sin9bit_1024.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 9 " "Parameter \"width_a\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} } { { "spwm_sin.v" "" { Text "F:/Code/FPGA/reserve/spwm/spwm_sin.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1544446513030 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sl91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_sl91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sl91 " "Found entity 1: altsyncram_sl91" { } { { "db/altsyncram_sl91.tdf" "" { Text "F:/Code/FPGA/reserve/spwm/db/altsyncram_sl91.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446513104 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446513104 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sl91 spwm_sin:spwm_sin\|altsyncram:altsyncram_component\|altsyncram_sl91:auto_generated " "Elaborating entity \"altsyncram_sl91\" for hierarchy \"spwm_sin:spwm_sin\|altsyncram:altsyncram_component\|altsyncram_sl91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513104 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "modulation modulation:modulation " "Elaborating entity \"modulation\" for hierarchy \"modulation:modulation\"" { } { { "rtl/spwm.v" "modulation" { Text "F:/Code/FPGA/reserve/spwm/rtl/spwm.v" 78 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513112 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "modulation:modulation\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"modulation:modulation\|Mult0\"" { } { { "rtl/modulation.v" "Mult0" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1544446513379 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1544446513379 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513453 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "modulation:modulation\|lpm_mult:Mult0 " "Instantiated megafunction \"modulation:modulation\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 9 " "Parameter \"LPM_WIDTHA\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 8 " "Parameter \"LPM_WIDTHB\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 17 " "Parameter \"LPM_WIDTHP\" = \"17\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 17 " "Parameter \"LPM_WIDTHR\" = \"17\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} } { { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1544446513453 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "lpm_mult.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 308 5 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513524 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "multcore.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513569 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "mpar_add.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513632 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lgh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_lgh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lgh " "Found entity 1: add_sub_lgh" { } { { "db/add_sub_lgh.tdf" "" { Text "F:/Code/FPGA/reserve/spwm/db/add_sub_lgh.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446513702 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446513702 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "mpar_add.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513708 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "mpar_add.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513721 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_pgh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_pgh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_pgh " "Found entity 1: add_sub_pgh" { } { { "db/add_sub_pgh.tdf" "" { Text "F:/Code/FPGA/reserve/spwm/db/add_sub_pgh.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446513789 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446513789 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|altshift:external_latency_ffs modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "lpm_mult.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 351 4 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513836 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1544446514266 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1544446514868 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446514868 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "148 " "Implemented 148 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1544446514936 ""} { "Info" "ICUT_CUT_TM_OPINS" "19 " "Implemented 19 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1544446514936 ""} { "Info" "ICUT_CUT_TM_LCELLS" "92 " "Implemented 92 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1544446514936 ""} { "Info" "ICUT_CUT_TM_RAMS" "9 " "Implemented 9 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1544446514936 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1544446514936 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4804 " "Peak virtual memory: 4804 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544446514956 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 20:55:14 2018 " "Processing ended: Mon Dec 10 20:55:14 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544446514956 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544446514956 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544446514956 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446514956 ""}
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