140 lines
7.4 KiB
Plaintext
140 lines
7.4 KiB
Plaintext
# Reading D:/intelFPGA/18.0/modelsim_ase/tcl/vsim/pref.tcl
|
||
# do timer_pwm_run_msim_gate_verilog.do
|
||
# if {[file exists gate_work]} {
|
||
# vdel -lib gate_work -all
|
||
# }
|
||
# vlib gate_work
|
||
# vmap work gate_work
|
||
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016
|
||
# vmap work gate_work
|
||
# Copying D:/intelFPGA/18.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
|
||
# Modifying modelsim.ini
|
||
#
|
||
# vlog -vlog01compat -work work +incdir+. {timer_pwm_8_1200mv_85c_slow.vo}
|
||
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
|
||
# Start time: 18:16:33 on Nov 03,2018
|
||
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+." timer_pwm_8_1200mv_85c_slow.vo
|
||
# -- Compiling module timer_pwm_top
|
||
#
|
||
# Top level modules:
|
||
# timer_pwm_top
|
||
# End time: 18:16:33 on Nov 03,2018, Elapsed time: 0:00:00
|
||
# Errors: 0, Warnings: 0
|
||
#
|
||
# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/testbench {F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v}
|
||
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
|
||
# Start time: 18:16:35 on Nov 03,2018
|
||
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/timer_pwm/testbench" F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v
|
||
# -- Compiling module timer_pwm_top_tb
|
||
#
|
||
# Top level modules:
|
||
# timer_pwm_top_tb
|
||
# End time: 18:16:35 on Nov 03,2018, Elapsed time: 0:00:00
|
||
# Errors: 0, Warnings: 0
|
||
#
|
||
# vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" timer_pwm_top_tb
|
||
# vsim -t 1ps "+transport_int_delays" "+transport_path_delays" -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs=""+acc"" timer_pwm_top_tb
|
||
# Start time: 18:16:36 on Nov 03,2018
|
||
# Loading work.timer_pwm_top_tb
|
||
# Loading work.timer_pwm_top
|
||
# Loading cycloneive_ver.cycloneive_io_obuf
|
||
# Loading cycloneive_ver.cycloneive_io_ibuf
|
||
# Loading cycloneive_ver.cycloneive_clkctrl
|
||
# Loading cycloneive_ver.cycloneive_mux41
|
||
# Loading cycloneive_ver.cycloneive_ena_reg
|
||
# Loading cycloneive_ver.cycloneive_pll
|
||
# Loading cycloneive_ver.cycloneive_m_cntr
|
||
# Loading cycloneive_ver.cycloneive_n_cntr
|
||
# Loading cycloneive_ver.cycloneive_scale_cntr
|
||
# Loading cycloneive_ver.cycloneive_lcell_comb
|
||
# Loading altera_ver.dffeas
|
||
# SDF 10.5b Compiler 2016.10 Oct 5 2016
|
||
#
|
||
# Loading instances from timer_pwm_8_1200mv_85c_v_slow.sdo
|
||
# Loading altera_ver.PRIM_GDFF_LOW
|
||
# Loading timing data from timer_pwm_8_1200mv_85c_v_slow.sdo
|
||
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
|
||
# Time: 0 ps Iteration: 0 Instance: /timer_pwm_top_tb File: F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v
|
||
#
|
||
# add wave *
|
||
# view structure
|
||
# .main_pane.structure.interior.cs.body.struct
|
||
# view signals
|
||
# .main_pane.objects.interior.cs.body.tree
|
||
# run -all
|
||
# Note : Cycloneive PLL self reset due to loss of lock
|
||
# Time: 0 Instance: timer_pwm_top_tb.timer_pwm_top.\my_pll|altpll_component|auto_generated|pll1
|
||
# Note : Cycloneive PLL was reset
|
||
# Time: 1535 Instance: timer_pwm_top_tb.timer_pwm_top.\my_pll|altpll_component|auto_generated|pll1
|
||
# Note : Cycloneive PLL locked to incoming clock
|
||
# Time: 4083102 Instance: timer_pwm_top_tb.timer_pwm_top.\my_pll|altpll_component|auto_generated|pll1
|
||
# ** Note: $stop : F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v(46)
|
||
# Time: 84002 ns Iteration: 0 Instance: /timer_pwm_top_tb
|
||
# Break in Module timer_pwm_top_tb at F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v line 46
|
||
vlog -vlog01compat -work work +incdir+. F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo
|
||
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
|
||
# Start time: 18:17:35 on Nov 03,2018
|
||
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+." F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo
|
||
# -- Compiling module timer_pwm_top
|
||
#
|
||
# Top level modules:
|
||
# timer_pwm_top
|
||
# End time: 18:17:35 on Nov 03,2018, Elapsed time: 0:00:00
|
||
# Errors: 0, Warnings: 0
|
||
vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/testbench F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v
|
||
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
|
||
# Start time: 18:17:36 on Nov 03,2018
|
||
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/timer_pwm/testbench" F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v
|
||
# -- Compiling module timer_pwm_top_tb
|
||
#
|
||
# Top level modules:
|
||
# timer_pwm_top_tb
|
||
# End time: 18:17:36 on Nov 03,2018, Elapsed time: 0:00:00
|
||
# Errors: 0, Warnings: 0
|
||
vlog -vlog01compat -work work +incdir+. F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo
|
||
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
|
||
# Start time: 18:17:37 on Nov 03,2018
|
||
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+." F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo
|
||
# -- Compiling module timer_pwm_top
|
||
#
|
||
# Top level modules:
|
||
# timer_pwm_top
|
||
# End time: 18:17:37 on Nov 03,2018, Elapsed time: 0:00:00
|
||
# Errors: 0, Warnings: 0
|
||
vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/testbench F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v
|
||
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
|
||
# Start time: 18:17:37 on Nov 03,2018
|
||
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/timer_pwm/testbench" F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v
|
||
# -- Compiling module timer_pwm_top_tb
|
||
#
|
||
# Top level modules:
|
||
# timer_pwm_top_tb
|
||
# End time: 18:17:37 on Nov 03,2018, Elapsed time: 0:00:00
|
||
# Errors: 0, Warnings: 0
|
||
restart
|
||
# Loading work.timer_pwm_top_tb
|
||
# Loading work.timer_pwm_top
|
||
# SDF 10.5b Compiler 2016.10 Oct 5 2016
|
||
#
|
||
# Loading instances from timer_pwm_8_1200mv_85c_v_slow.sdo
|
||
# ** Warning: (vsim-3015) F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v(20): [PCDPC] - Port size (8) does not match connection size (2) for port 'tim_ch'. The port definition is at: F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo(37).
|
||
# Time: 0 ps Iteration: 0 Instance: /timer_pwm_top_tb/timer_pwm_top File: F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo
|
||
# Loading timing data from timer_pwm_8_1200mv_85c_v_slow.sdo
|
||
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
|
||
# Time: 0 ps Iteration: 0 Instance: /timer_pwm_top_tb File: F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v
|
||
run -all
|
||
# GetModuleFileName: <20>Ҳ<EFBFBD><D2B2><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>ģ<EFBFBD>顣
|
||
#
|
||
#
|
||
# Note : Cycloneive PLL self reset due to loss of lock
|
||
# Time: 0 Instance: timer_pwm_top_tb.timer_pwm_top.\my_pll|altpll_component|auto_generated|pll1
|
||
# Note : Cycloneive PLL was reset
|
||
# Time: 1535 Instance: timer_pwm_top_tb.timer_pwm_top.\my_pll|altpll_component|auto_generated|pll1
|
||
# Note : Cycloneive PLL locked to incoming clock
|
||
# Time: 4083102 Instance: timer_pwm_top_tb.timer_pwm_top.\my_pll|altpll_component|auto_generated|pll1
|
||
# ** Note: $stop : F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v(46)
|
||
# Time: 84002 ns Iteration: 0 Instance: /timer_pwm_top_tb
|
||
# Break in Module timer_pwm_top_tb at F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v line 46
|
||
# End time: 19:35:19 on Nov 03,2018, Elapsed time: 1:18:43
|
||
# Errors: 0, Warnings: 1
|