60 lines
949 B
Verilog
60 lines
949 B
Verilog
module timer_pwm(
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clk_tim,
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rst_n,
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tim_cr,
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tim_arr,
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tim_ccr1,
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tim_ch
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);
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input clk_tim;
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input rst_n;
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input [15:0] tim_arr;
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input [31:0] tim_cr;
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input [15:0] tim_ccr1;
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output reg [1:0] tim_ch;//[7:0] {...tim_ch1,tim_ch1n}
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reg [31:0] r_tim_cr;
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reg [15:0] r_tim_cnt;
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reg [15:0] r_tim_psc;
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reg [15:0] r_tim_arr;
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reg [15:0] r_tim_ccr1;
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reg [15:0] cnt; //整个定时器的计数值
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always @ (posedge clk_tim)//tim_ch,tim_chn
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if(cnt == 0)
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tim_ch[1:0] <= 2'b10;
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else if(cnt == r_tim_ccr1)
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tim_ch[1:0] <= 2'b01;
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always @ (posedge clk_tim or negedge rst_n)
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if(!rst_n)
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cnt <= 16'd0;
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else if(cnt >= r_tim_arr)
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cnt <= 16'd0;
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else
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cnt <= cnt + 1'b1;
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always @ (posedge clk_tim or negedge rst_n)
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if(!rst_n) begin
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r_tim_arr <= 16'd0;
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r_tim_ccr1 <= 16'd0;
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r_tim_cr <= 32'd0;
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end
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else
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begin
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r_tim_arr <= tim_arr;
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r_tim_cr <= tim_cr;
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r_tim_ccr1 <= tim_ccr1;
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end
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endmodule
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