23 lines
1001 B
Plaintext
23 lines
1001 B
Plaintext
Info: Start Nativelink Simulation process
|
|
|
|
========= EDA Simulation Settings =====================
|
|
|
|
Sim Mode : Gate
|
|
Family : cycloneive
|
|
Quartus root : d:/intelfpga/18.0/quartus/bin64/
|
|
Quartus sim root : d:/intelfpga/18.0/quartus/eda/sim_lib
|
|
Simulation Tool : modelsim-altera
|
|
Simulation Language : verilog
|
|
Simulation Mode : GUI
|
|
Sim Output File : timer_pwm_8_1200mv_85c_slow.vo
|
|
Sim SDF File : timer_pwm_8_1200mv_85c_v_slow.sdo
|
|
Sim dir : simulation\modelsim
|
|
|
|
=======================================================
|
|
|
|
Info: Starting NativeLink simulation with ModelSim-Altera software
|
|
Sourced NativeLink script d:/intelfpga/18.0/quartus/common/tcl/internal/nativelink/modelsim.tcl
|
|
Warning: File timer_pwm_run_msim_gate_verilog.do already exists - backing up current file as timer_pwm_run_msim_gate_verilog.do.bak2
|
|
Info: Spawning ModelSim-Altera Simulation software
|
|
Info: NativeLink simulation flow was successful
|