riffa/fpga/xilinx/Makefile

# ----------------------------------------------------------------------
# Copyright (c) 2016, The Regents of the University of California All
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# ----------------------------------------------------------------------
#-----------------------------------------------------------------------
# Filename:            Makefile
# Version:             1.0
# Description:         Vendor-level makefile for building all boards
# Author:              Dustin Richmond (@darichmond)
#-----------------------------------------------------------------------
VENDOR:=xilinx
ULTRASCALE:=NetFPGA adm7V3 vc709 
CLASSIC:=vc707 zc706 ac701 kc705
BOARDS:=$(CLASSIC) $(ULTRASCALE)
CURRENT_PATH := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
.DEFAULT_GOAL=all

RIFFA_ROOT_PATH=$(CURRENT_PATH)/../../
RIFFA_HDL_PATH=$(CURRENT_PATH)/../riffa_hdl
include $(RIFFA_ROOT_PATH)/release.mk
include $(RIFFA_ROOT_PATH)/fpga/fpga.mk

all $(VENDOR): $(BOARDS)

classic:$(CLASSIC)
ultrascale:$(ULTRASCALE)

$(CLASSIC) $(ULTRASCALE)::
	$(MAKE) -C $@ $(MAKECMDGOALS) VENDOR_PATH=$(CURRENT_PATH) VENDOR=$(VENDOR) RIFFA_ROOT_PATH=$(RIFFA_ROOT_PATH)

.PHONY:clean $(BOARDS) classic all clobber
clean clobber: $(BOARDS)
	rm -rf *.log *.jou .Xil *~