riffa/fpga/riffa_hdl/rotate.v

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//----------------------------------------------------------------------------
// Filename:			rotate.v
// Version:				1.00
// Verilog Standard:	Verilog-2001
// Description:			A simple module to perform to rotate the input data
// Author:				Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module rotate
    #(
      parameter C_DIRECTION = "LEFT",
      parameter C_WIDTH = 4
      )
    (
     input [C_WIDTH-1:0]        WR_DATA,
     input [clog2s(C_WIDTH)-1:0] WR_SHIFTAMT,
     output [C_WIDTH-1:0]       RD_DATA
     );

    wire [2*C_WIDTH-1:0]        wPreShiftR;
    wire [2*C_WIDTH-1:0]        wPreShiftL;

    wire [2*C_WIDTH-1:0]        wShiftR;
    wire [2*C_WIDTH-1:0]        wShiftL;

    assign wPreShiftL = {WR_DATA,WR_DATA};
    assign wPreShiftR = {WR_DATA,WR_DATA};

    assign wShiftL = wPreShiftL << WR_SHIFTAMT;
    assign wShiftR = wPreShiftR >> WR_SHIFTAMT;

    generate
        if(C_DIRECTION == "LEFT") begin
            assign RD_DATA = wShiftL[2*C_WIDTH-1:C_WIDTH];
        end else if (C_DIRECTION == "RIGHT") begin
            assign RD_DATA = wShiftR[C_WIDTH-1:0];
        end
    endgenerate
endmodule