mirror of
https://github.com/KastnerRG/riffa.git
synced 2025-01-30 23:02:54 +08:00
Adding graceful reset logic to the RIFFA core.
This commit is contained in:
Dustin Richmond
parent
924d52e6ab
commit
1254f44441
@ -36,8 +36,7 @@
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`include "riffa.vh"
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`timescale 1ns/1ns
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module riffa
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#(
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parameter C_PCI_DATA_WIDTH = 128,
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#(parameter C_PCI_DATA_WIDTH = 128,
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parameter C_NUM_CHNL = 12,
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parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes)
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parameter C_TAG_WIDTH = 5, // Number of outstanding requests
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@ -46,10 +45,11 @@ module riffa
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parameter C_FPGA_ID = 0,// A value from 0 to 255 uniquely identifying this RIFFA design
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parameter C_DEPTH_PACKETS = 10
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)
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(
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input CLK,
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input RST_IN,
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(input CLK,
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input RST_BUS,
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output RST_OUT,
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input DONE_TXC_RST,
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input DONE_TXR_RST,
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// Interface: RXC Engine
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input [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
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@ -276,26 +276,25 @@ module riffa
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wire wTxEngRdReqSent;
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wire wRxEngRdComplete;
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wire wCoreReset;
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wire wRstLogic;
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wire [31:0] wCPciDataWidth;
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wire [31:0] wCFpgaId;
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reg [31:0] wCFpgaId;
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reg [4:0] rWideRst;
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reg rRst;
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genvar i;
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assign RST_OUT = wRstLogic;
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assign wRstLogic = wCoreSettingsReady;
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assign wRxEngRdComplete = RXC_DATA_END_FLAG & RXC_DATA_VALID &
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(RXC_META_LENGTH >= RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:2]);// TODO: Retime (if possible)
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assign wCoreSettings = {1'd0, wCFpgaId, wCPciDataWidth[8:5],
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CONFIG_MAX_PAYLOAD_SIZE, CONFIG_MAX_READ_REQUEST_SIZE,
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CONFIG_LINK_RATE[1:0], CONFIG_LINK_WIDTH, CONFIG_BUS_MASTER_ENABLE,
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C_NUM_CHNL[3:0]};
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assign RST_OUT = wCoreReset;
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// Interface: TXC Engine
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assign TXC_DATA = wTxcData;
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@ -303,8 +302,8 @@ module riffa
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assign TXC_DATA_START_OFFSET = wTxcDataStartOffset;
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assign TXC_DATA_END_FLAG = wTxcDataEndFlag;
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assign TXC_DATA_END_OFFSET = wTxcDataEndOffset;
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assign TXC_DATA_VALID = wTxcDataValid & ~wCoreReset;
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assign wTxcDataReady = TXC_DATA_READY & ~wCoreReset;
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assign TXC_DATA_VALID = wTxcDataValid & ~wRstLogic & DONE_TXC_RST;
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assign wTxcDataReady = TXC_DATA_READY & ~wRstLogic & DONE_TXC_RST;
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assign TXC_META_FDWBE = wTxcMetaFdwbe;
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assign TXC_META_LDWBE = wTxcMetaLdwbe;
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@ -317,8 +316,8 @@ module riffa
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assign TXC_META_TC = wTxcMetaTc;
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assign TXC_META_ATTR = wTxcMetaAttr;
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assign TXC_META_EP = wTxcMetaEp;
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assign TXC_META_VALID = wTxcMetaValid & ~wCoreReset;
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assign wTxcMetaReady = TXC_META_READY & ~wCoreReset;
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assign TXC_META_VALID = wTxcMetaValid & ~wRstLogic & DONE_TXC_RST;
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assign wTxcMetaReady = TXC_META_READY & ~wRstLogic & DONE_TXC_RST;
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/* Workaround for a bug reported by the NetFPGA group, where the parameter
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/* C_PCI_DATA_WIDTH cannot be directly assigned to a wire. */
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@ -353,21 +352,9 @@ module riffa
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end else if ((C_FPGA_ID & 1) != 1) begin
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wCFpgaId[0] = 1;
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end
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end
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endgenerate
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resetter
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#(// Parameters
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.C_RST_COUNT (5),
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.C_RST_USE_SHREG (1)
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/*AUTOINSTPARAM*/)
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core_reset_inst
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(// Outputs
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.RST_OUT (wCoreReset),
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN)
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/*AUTOINST*/);
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/* The purpose of these two hold modules is to safely reset the TX path and
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still respond to the core status request (which causes a RIFFA reset). We
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could wait until after the completion has been transmitted, but we have no
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@ -393,7 +380,7 @@ module riffa
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wTxcMetaByteCount, wTxcMetaTag,
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wTxcMetaRequesterId, wTxcMetaTc,
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wTxcMetaAttr, wTxcMetaEp}),
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.RD_DATA_VALID (wTxcDataValid),
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.RD_DATA_VALID (wTxcMetaValid),
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// Inputs
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.WR_DATA ({_wTxcMetaFdwbe, _wTxcMetaLdwbe,
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_wTxcMetaAddr, _wTxcMetaType,
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@ -401,12 +388,12 @@ module riffa
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_wTxcMetaByteCount, _wTxcMetaTag,
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_wTxcMetaRequesterId, _wTxcMetaTc,
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_wTxcMetaAttr, _wTxcMetaEp}),
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.WR_DATA_VALID (_wTxcDataValid),
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.RD_DATA_READY (wTxcDataReady ),
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.WR_DATA_VALID (_wTxcMetaValid),
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.RD_DATA_READY (wTxcMetaReady),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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.CLK (CLK),
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.RST_IN (RST_IN));
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pipeline
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#(// Parameters
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@ -427,22 +414,19 @@ module riffa
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_wTxcDataStartOffset, _wTxcDataEndFlag,
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_wTxcDataEndOffset}),
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.WR_DATA_VALID (_wTxcDataValid),
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.RD_DATA_READY (wTxcDataReady & ~wCoreReset),
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.RD_DATA_READY (wTxcDataReady),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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.CLK (CLK),
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.RST_IN (RST_IN));
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reorder_queue
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#(
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.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
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.C_NUM_CHNL(C_NUM_CHNL),
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.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),
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.C_TAG_WIDTH(C_TAG_WIDTH)
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)
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#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
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.C_NUM_CHNL(C_NUM_CHNL),
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.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),
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.C_TAG_WIDTH(C_TAG_WIDTH))
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reorderQueue
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(
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.RST (wCoreReset),
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(.RST (wRstLogic),
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.VALID (RXC_DATA_VALID),
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.DATA_START_FLAG (RXC_DATA_START_FLAG),
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.DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
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@ -504,17 +488,7 @@ module riffa
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.CHNL_TX_DONE_READY (wChnlTxDoneReady),
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.CHNL_RX_DONE_READY (wChnlRxDoneReady),
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.CHNL_NAME_READY (wChnlNameReady), // TODO: Could do this on a per-channel basis
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// Inputs
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// Read Data
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.CORE_SETTINGS (wCoreSettings),
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.CHNL_TX_REQLEN (wChnlTxReqLen),
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.CHNL_TX_OFFLAST (wChnlTxOfflast),
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.CHNL_TX_DONELEN (wChnlTxDoneLen),
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.CHNL_RX_DONELEN (wChnlRxDoneLen),
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.INTR_VECTOR (wIntrVector),
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.RST_IN (wCoreReset),
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/*AUTOINST*/
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// Outputs
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// TXC Engine Interface
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.TXC_DATA_VALID (_wTxcDataValid),
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.TXC_DATA (_wTxcData[C_PCI_DATA_WIDTH-1:0]),
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.TXC_DATA_START_FLAG (_wTxcDataStartFlag),
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@ -534,6 +508,18 @@ module riffa
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.TXC_META_ATTR (_wTxcMetaAttr[`SIG_ATTR_W-1:0]),
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.TXC_META_EP (_wTxcMetaEp),
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// Inputs
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// Read Data
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.CORE_SETTINGS (wCoreSettings),
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.CHNL_TX_REQLEN (wChnlTxReqLen),
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.CHNL_TX_OFFLAST (wChnlTxOfflast),
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.CHNL_TX_DONELEN (wChnlTxDoneLen),
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.CHNL_RX_DONELEN (wChnlRxDoneLen),
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.INTR_VECTOR (wIntrVector),
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.RST_IN (wRstLogic),
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.TXC_DATA_READY (_wTxcDataReady),
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.TXC_META_READY (_wTxcMetaReady),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RXR_DATA (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
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.RXR_DATA_VALID (RXR_DATA_VALID),
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@ -550,19 +536,16 @@ module riffa
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.RXR_META_ADDR (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
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.RXR_META_BAR_DECODED (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
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.RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
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.RXR_META_LENGTH (RXR_META_LENGTH[`SIG_LEN_W-1:0]),
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.TXC_DATA_READY (TXC_DATA_READY),
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.TXC_META_READY (TXC_META_READY));
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.RXR_META_LENGTH (RXR_META_LENGTH[`SIG_LEN_W-1:0]));
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// Track receive buffer flow control credits (header & Data)
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recv_credit_flow_ctrl rc_fc
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(
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// Outputs
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(// Outputs
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.RXBUF_SPACE_AVAIL (wRxBufSpaceAvail),
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// Inputs
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.RX_ENG_RD_DONE (wRxEngRdComplete),
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.TX_ENG_RD_REQ_SENT (wTxEngRdReqSent),
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.RST (wCoreReset),
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.RST (wRstLogic),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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@ -572,12 +555,10 @@ module riffa
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.CONFIG_CPL_BOUNDARY_SEL (CONFIG_CPL_BOUNDARY_SEL));
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// Connect the interrupt vector and controller.
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interrupt
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#(
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.C_NUM_CHNL (C_NUM_CHNL)
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)
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#(.C_NUM_CHNL (C_NUM_CHNL))
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intr
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(// Inputs
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.RST (wCoreReset),
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.RST (wRstLogic),
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.RX_SG_BUF_RECVD (wChnlSgRxBufRecvd),
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.RX_TXN_DONE (wChnlRxDone),
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.TX_TXN (wChnlTxRequest),
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@ -616,7 +597,7 @@ module riffa
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.INT_TAG_VALID (wInternalTagValid),
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.TX_ENG_RD_REQ_SENT (wTxEngRdReqSent),
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// Inputs
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.RST_IN (wCoreReset),
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.RST_IN (wRstLogic),
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.WR_REQ (wTxEngWrReq[C_NUM_CHNL-1:0]),
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.WR_ADDR (wTxEngWrAddr[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
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.WR_LEN (wTxEngWrLen[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
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@ -663,7 +644,7 @@ module riffa
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)
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channel
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(
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.RST(wCoreReset),
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.RST(wRstLogic),
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.CLK(CLK),
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.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
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.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
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