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Fixing more backwards compatibility issues

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Had to remove some method calls
This commit is contained in:
Dustin Richmond 2016-06-29 16:39:16 -07:00
parent 64cd40f0b6
commit 1d228c190d
1 changed files with 17 additions and 47 deletions
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32
driver/linux/riffa_driver.c
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@ -181,7 +181,7 @@ unsigned long long __udivdi3(unsigned long long num, unsigned long long den)
/**
* Code used to set ETB and RCB, but not available before 3.0, or incorrectly
* defined before 3.7. As it is peppered throughout the clean up code, it's just
* easier to copy the declarations verbatim here than a bunch of conditionals
* easier to copy the declarations (not verbatim) here than a bunch of conditionals
* everywhere else.
*/
@ -193,7 +193,6 @@ int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
if (pos & 1)
return -EINVAL;
if (pcie_capability_reg_implemented(dev, pos)) {
ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
/*
* Reset *val to 0 if pci_read_config_word() fails, it may
@ -203,21 +202,6 @@ int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
if (ret)
*val = 0;
return ret;
}
/*
* For Functions that do not implement the Slot Capabilities,
* Slot Status, and Slot Control registers, these spaces must
* be hardwired to 0b, with the exception of the Presence Detect
* State bit in the Slot Status register of Downstream Ports,
* which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
*/
if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
*val = PCI_EXP_SLTSTA_PDS;
}
return 0;
}
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
@ -228,7 +212,6 @@ int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
if (pos & 3)
return -EINVAL;
if (pcie_capability_reg_implemented(dev, pos)) {
ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
/*
* Reset *val to 0 if pci_read_config_dword() fails, it may
@ -238,14 +221,7 @@ int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
if (ret)
*val = 0;
return ret;
}
if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
*val = PCI_EXP_SLTSTA_PDS;
}
return 0;
}
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
@ -253,9 +229,6 @@ int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
if (pos & 1)
return -EINVAL;
if (!pcie_capability_reg_implemented(dev, pos))
return 0;
return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
}
@ -264,9 +237,6 @@ int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
if (pos & 3)
return -EINVAL;
if (!pcie_capability_reg_implemented(dev, pos))
return 0;
return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
}
#endif