FPGA/riffa
1
0
Fork 0
mirror of https://github.com/KastnerRG/riffa.git synced 2025-01-30 23:02:54 +08:00
Code Issues Projects Releases Wiki Activity

Pull changes from devel/2.2.2

Browse Source
This commit is contained in:
Adrien Prost-Boucle 2016-08-10 14:09:15 +02:00
commit 1f8a9efd77
9 changed files with 532 additions and 533 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

90
driver/linux/riffa_driver.c
View File

@ -55,6 +55,7 @@
#include <linux/rwsem.h> #include <linux/rwsem.h>
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
#include <linux/pagemap.h> #include <linux/pagemap.h>
#include <linux/slab.h>
#include <asm/uaccess.h> #include <asm/uaccess.h>
#include <asm/div64.h> #include <asm/div64.h>
#include "riffa_driver.h" #include "riffa_driver.h"
@ -156,58 +157,93 @@ unsigned long long __udivdi3(unsigned long long num, unsigned long long den)
} }
#endif #endif
#if LINUX_VERSION_CODE <= KERNEL_VERSION(3,6,11)
// These are not defined in the 2.x.y kernels, so just define them
#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,39)
#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x100
#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x200
#else
/** /**
* Used to set ETB and RCB, but not available before 3.7. As it is peppered * These are badly named in pre-3.6.11 kernel versions. We COULD do the same
* throughout the clean up code, it's just easier to define empty implementations * check as above, however (annoyingly) linux for tegra (based on post-3.6.11)
* here than a bunch of conditionals everywhere else. * picked up the header file from some pre-3.6.11 version, so we'll just make
* our code ugly and handle the check here:
*/ */
#ifndef PCI_EXP_DEVCTL
#define PCI_EXP_DEVCTL 0
#endif
#ifndef PCI_EXP_DEVCTL_EXT_TAG
#define PCI_EXP_DEVCTL_EXT_TAG 0
#endif
#ifndef PCI_EXP_DEVCTL_RELAX_EN
#define PCI_EXP_DEVCTL_RELAX_EN 0
#endif
#ifndef PCI_EXP_DEVCTL2
#define PCI_EXP_DEVCTL2 0
#endif
#ifndef PCI_EXP_DEVCTL2_IDO_REQ_EN #ifndef PCI_EXP_DEVCTL2_IDO_REQ_EN
#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0 #define PCI_EXP_DEVCTL2_IDO_REQ_EN PCI_EXP_IDO_REQ_EN
#endif #endif
#ifndef PCI_EXP_DEVCTL2_IDO_CMP_EN #ifndef PCI_EXP_DEVCTL2_IDO_CMP_EN
#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0 #define PCI_EXP_DEVCTL2_IDO_CMP_EN PCI_EXP_IDO_CMP_EN
#endif #endif
#ifndef PCI_EXP_DEVCTL
#define PCI_EXP_DEVCTL 0
#endif
#ifndef PCI_EXP_LNKCTL_RCB
#define PCI_EXP_LNKCTL_RCB 0
#endif #endif
#if LINUX_VERSION_CODE <= KERNEL_VERSION(3,6,11)
/**
* Code used to set ETB and RCB, but not available before 3.0, or incorrectly
* defined before 3.7. As it is peppered throughout the clean up code, it's just
* easier to copy the declarations (not verbatim) here than a bunch of conditionals
* everywhere else.
*/
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
{ {
return 0; int ret;
*val = 0;
if (pos & 1)
return -EINVAL;
ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
/*
* Reset *val to 0 if pci_read_config_word() fails, it may
* have been written as 0xFFFF if hardware error happens
* during pci_read_config_word().
*/
if (ret)
*val = 0;
return ret;
} }
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val) int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
{ {
return 0; int ret;
*val = 0;
if (pos & 3)
return -EINVAL;
ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
/*
* Reset *val to 0 if pci_read_config_dword() fails, it may
* have been written as 0xFFFFFFFF if hardware error happens
* during pci_read_config_dword().
*/
if (ret)
*val = 0;
return ret;
} }
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
{ {
return 0; if (pos & 1)
return -EINVAL;
return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
} }
int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val) int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
{ {
return 0; if (pos & 3)
return -EINVAL;
return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
} }
#endif #endif
/////////////////////////////////////////////////////// ///////////////////////////////////////////////////////
// INTERRUPT HANDLER // INTERRUPT HANDLER
/////////////////////////////////////////////////////// ///////////////////////////////////////////////////////

14
driver/windows/README.txt
View File

@ -4,9 +4,15 @@ To build the Windows driver:
version 7600.16385.1). version 7600.16385.1).
2) Open a DDK command window environment for Windows 7 (which ever version 2) Open a DDK command window environment for Windows 7 (which ever version
you're targeting). you're targeting).
3) Move to the directory containing this README.txt and run: build -ceZ 3) Move to the directory containing this README.txt and run build -ceZ
4) The driver should be built and ready in the output directory along with a 4) The driver should be built and ready in the output directory along with a
Windows 7 catalog file and the coinstaller DLLs. Windows 7 catalog file and the coinstaller DLLs.
5) To build the installer you will need to build the driver using the DDK for
each architecture (x86/x64). If you want both setup.exe and setup_dbg.exe
executables, you will run the build command FOUR TIMES before step 6.
6) To build the setup.exe file, run the win7install.bat script from the DDK
unchecked/free command window. To build the setup_dbg.exe file, run the
script from the checked command window.
A few notes: A few notes:
@ -15,7 +21,11 @@ A few notes:
process will attempt to sign the catalog file with the UCSD certificate. You process will attempt to sign the catalog file with the UCSD certificate. You
don't have that, so you won't get a signed driver simply by building. You'll don't have that, so you won't get a signed driver simply by building. You'll
need to get a certificate from a certificate authority that is capable of need to get a certificate from a certificate authority that is capable of
cross-certificate kernel driver signing. See this page for more details: cross-certificate kernel driver signing to authenticate yourself (.pfx),
and the cross-signing certificate from that authority (.crt file available
from link). These should both be added to the windows certificate list and
and copied into the root folder for the windows driver (same location as this
README.txt file). See this page for more details:
http://msdn.microsoft.com/en-us/windows/hardware/gg487315.aspx http://msdn.microsoft.com/en-us/windows/hardware/gg487315.aspx
- Debugging on Windows is difficult because there exists no kernel log file. - Debugging on Windows is difficult because there exists no kernel log file.

17
driver/windows/install/install.bat
View File

@ -1,4 +1,4 @@
@echo off @echo on
rmdir /s /q build rmdir /s /q build
md build md build
@ -14,12 +14,21 @@ xcopy /E /H /K /I /Y ..\..\..\c_c++\windows .\build\c_c++
xcopy /E /H /K /I /Y ..\..\..\java .\build\java xcopy /E /H /K /I /Y ..\..\..\java .\build\java
xcopy /E /H /K /I /Y ..\..\..\python .\build\python xcopy /E /H /K /I /Y ..\..\..\python .\build\python
xcopy /E /H /K /I /Y ..\..\..\matlab .\build\matlab xcopy /E /H /K /I /Y ..\..\..\matlab .\build\matlab
echo "%3"
if "%3" == "chk" ( if "%3" == "chk" (
"c:\program files\inno setup 5\iscc.exe" /dDebug="1" /o.\build .\build\win7.iss md .\build.\tmp_dbg
"c:\program files (x86)\inno setup 5\iscc.exe" /dDebug="1" /o.\build\tmp_dbg .\build\win7.iss
signtool sign /v /ac "..\GlobalSign Root CA.crt" /s my /n "University of California, San Diego" /t http://timestamp.verisign.com/scripts/timestamp.dll .\build\tmp_dbg\setup.exe
move .\build\tmp_dbg\setup.exe .\setup_dbg.exe
rmdir /s /q .\build\tmp_dbg\
) else ( ) else (
"c:\program files\inno setup 5\iscc.exe" /o.\build .\build\win7.iss md .\build\tmp
"c:\program files (x86)\inno setup 5\iscc.exe" /o.\build\tmp\ .\build\win7.iss
signtool sign /v /ac "..\GlobalSign Root CA.crt" /s my /n "University of California, San Diego" /t http://timestamp.verisign.com/scripts/timestamp.dll .\build\tmp\setup.exe
move .\build\tmp\setup.exe .\setup.exe
rmdir /s /q .\build\tmp\
) )
signtool sign /v /s my /n "University of California, San Diego" /t http://timestamp.verisign.com/scripts/timestamp.dll .\build\setup.exe

2
driver/windows/install/win7.iss
View File

@ -13,7 +13,7 @@
[Setup] [Setup]
AppName=RIFFA AppName=RIFFA
AppVersion=2.0 AppVersion=2.2.1
AppPublisher=University of California, San Diego AppPublisher=University of California, San Diego
AppPublisherURL=https://sites.google.com/a/eng.ucsd.edu/matt-jacobsen/riffa AppPublisherURL=https://sites.google.com/a/eng.ucsd.edu/matt-jacobsen/riffa
AppCopyright=Copyright (C) 2016 The Regents of the University of California. All Rights Reserved. AppCopyright=Copyright (C) 2016 The Regents of the University of California. All Rights Reserved.

4
driver/windows/sys/makefile.inc
View File

@ -22,7 +22,7 @@ POST:
inf2cat /driver:$(OBJ_PATH)\$(O) /os:7_x64 inf2cat /driver:$(OBJ_PATH)\$(O) /os:7_x64
! endif ! endif
! endif ! endif
signtool sign /v /ac "$(_INX)\GlobalSign Root CA.crt" /s my /n "University of California, San Diego" /t http://timestamp.verisign.com/scripts/timestamp.dll $(OBJ_PATH)\$(O)\$(INF_NAME).cat signtool sign /v /ac "$(_INX)\..\GlobalSign Root CA.crt" /s my /n "University of California, San Diego" /t http://timestamp.verisign.com/scripts/timestamp.dll $(OBJ_PATH)\$(O)\$(INF_NAME).cat
signtool sign /v /ac "$(_INX)\GlobalSign Root CA.crt" /s my /n "University of California, San Diego" /t http://timestamp.verisign.com/scripts/timestamp.dll $(OBJ_PATH)\$(O)\$(INF_NAME).sys signtool sign /v /ac "$(_INX)\..\GlobalSign Root CA.crt" /s my /n "University of California, San Diego" /t http://timestamp.verisign.com/scripts/timestamp.dll $(OBJ_PATH)\$(O)\$(INF_NAME).sys

304
fpga/riffa_hdl/tx_port_channel_gate_128.v
View File

@ -33,189 +33,169 @@
// DAMAGE. // DAMAGE.
// ---------------------------------------------------------------------- // ----------------------------------------------------------------------
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// Filename: tx_port_channel_gate_128.v // Filename: tx_port_channel_gate_128.v
// Version: 1.00.a // Version: 1.00.a
// Verilog Standard: Verilog-2001 // Verilog Standard: Verilog-2001
// Description: Captures transaction open/close events as well as data // Description: Captures transaction open/close events as well as data
// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can // and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can
// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When // only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When
// CHNL_TX drops, the channel closes (until the next transaction -- signaled by // CHNL_TX drops, the channel closes (until the next transaction -- signaled by
// CHNL_TX going up again). // CHNL_TX going up again).
// Author: Matt Jacobsen // Author: Matt Jacobsen
// History: @mattj: Version 2.0 // History: @mattj: Version 2.0
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
`define S_TXPORTGATE128_IDLE 2'b00 `define S_TXPORTGATE128_IDLE 2'b00
`define S_TXPORTGATE128_OPENING 2'b01 `define S_TXPORTGATE128_OPENING 2'b01
`define S_TXPORTGATE128_OPEN 2'b10 `define S_TXPORTGATE128_OPEN 2'b10
`define S_TXPORTGATE128_CLOSED 2'b11 `define S_TXPORTGATE128_CLOSED 2'b11
`timescale 1ns/1ns `timescale 1ns/1ns
module tx_port_channel_gate_128 #( module tx_port_channel_gate_128
parameter C_DATA_WIDTH = 9'd128, #(parameter C_DATA_WIDTH = 9'd128,
// Local parameters // Local parameters
parameter C_FIFO_DEPTH = 8, parameter C_FIFO_DEPTH = 8,
parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1 parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH + 1)
) (input RST,
(
input RST,
input RD_CLK, // FIFO read clock input RD_CLK, // FIFO read clock
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data
output RD_EMPTY, // FIFO is empty output RD_EMPTY, // FIFO is empty
input RD_EN, // FIFO read enable input RD_EN, // FIFO read enable
input CHNL_CLK, // Channel write clock input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words) input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved output CHNL_TX_DATA_REN); // Channel write data has been recieved
);
(* syn_encoding = "user" *) (* syn_encoding = "user" *)
(* fsm_encoding = "user" *) (* fsm_encoding = "user" *)
reg [1:0] rState=`S_TXPORTGATE128_IDLE, _rState=`S_TXPORTGATE128_IDLE; reg [1:0] rState=`S_TXPORTGATE128_IDLE, _rState=`S_TXPORTGATE128_IDLE;
reg rFifoWen=0, _rFifoWen=0; reg rFifoWen=0, _rFifoWen=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0; reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0;
wire wFifoFull; wire wFifoFull;
reg rChnlTx=0, _rChnlTx=0; reg rChnlTx=0, _rChnlTx=0;
reg rChnlLast=0, _rChnlLast=0; reg rChnlLast=0, _rChnlLast=0;
reg [31:0] rChnlLen=0, _rChnlLen=0; reg [31:0] rChnlLen=0, _rChnlLen=0;
reg [30:0] rChnlOff=0, _rChnlOff=0; reg [30:0] rChnlOff=0, _rChnlOff=0;
reg rAck=0, _rAck=0; reg rAck=0, _rAck=0;
reg rPause=0, _rPause=0; reg rPause=0, _rPause=0;
reg rClosed=0, _rClosed=0; reg rClosed=0, _rClosed=0;
reg rOpen=0, _rOpen=0;
assign CHNL_TX_ACK = rAck;
assign CHNL_TX_DATA_REN = (rOpen & !wFifoFull); // S_TXPORTGATE128_OPEN
assign CHNL_TX_ACK = rAck; // Buffer the input signals that come from outside the tx_port.
assign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE128_OPEN always @ (posedge CHNL_CLK) begin
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
rChnlLast <= #1 _rChnlLast;
rChnlLen <= #1 _rChnlLen;
rChnlOff <= #1 _rChnlOff;
end
always @ (*) begin
_rChnlTx = CHNL_TX;
_rChnlLast = CHNL_TX_LAST;
_rChnlLen = CHNL_TX_LEN;
_rChnlOff = CHNL_TX_OFF;
end
// Buffer the input signals that come from outside the tx_port. // FIFO for temporarily storing data from the channel.
always @ (posedge CHNL_CLK) begin (* RAM_STYLE="DISTRIBUTED" *)
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx); async_fifo
rChnlLast <= #1 _rChnlLast; #(.C_WIDTH(C_FIFO_DATA_WIDTH),
rChnlLen <= #1 _rChnlLen; .C_DEPTH(C_FIFO_DEPTH))
rChnlOff <= #1 _rChnlOff; fifo
end (.WR_CLK(CHNL_CLK),
.WR_RST(RST),
.WR_EN(rFifoWen),
.WR_DATA(rFifoData),
.WR_FULL(wFifoFull),
.RD_CLK(RD_CLK),
.RD_RST(RST),
.RD_EN(RD_EN),
.RD_DATA(RD_DATA),
.RD_EMPTY(RD_EMPTY));
always @ (*) begin // Pass the transaction open event, transaction data, and the transaction
_rChnlTx = CHNL_TX; // close event through to the RD_CLK domain via the async_fifo.
_rChnlLast = CHNL_TX_LAST; always @ (posedge CHNL_CLK) begin
_rChnlLen = CHNL_TX_LEN; rState <= #1 (RST ? `S_TXPORTGATE128_IDLE : _rState);
_rChnlOff = CHNL_TX_OFF; rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
end rFifoData <= #1 _rFifoData;
rAck <= #1 (RST ? 1'd0 : _rAck);
rPause <= #1 (RST ? 1'd0 : _rPause);
rClosed <= #1 (RST ? 1'd0 : _rClosed);
rOpen <= #1 (RST ? 1'd0 : _rOpen);
end
always @ (*) begin
_rState = rState;
_rFifoWen = rFifoWen;
_rFifoData = rFifoData;
_rPause = rPause;
_rAck = rAck;
_rClosed = rClosed;
_rOpen = rOpen;
case (rState)
// FIFO for temporarily storing data from the channel. `S_TXPORTGATE128_IDLE: begin // Write the len, off, last
(* RAM_STYLE="DISTRIBUTED" *) _rPause = 0;
async_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo ( _rClosed = 0;
.WR_CLK(CHNL_CLK), _rOpen = 0;
.WR_RST(RST), if (!wFifoFull) begin
.WR_EN(rFifoWen), _rAck = rChnlTx;
.WR_DATA(rFifoData), _rFifoWen = rChnlTx;
.WR_FULL(wFifoFull), _rFifoData = {1'd1, 64'd0, rChnlLen, rChnlOff, rChnlLast};
.RD_CLK(RD_CLK), if (rChnlTx)
.RD_RST(RST), _rState = `S_TXPORTGATE128_OPENING;
.RD_EN(RD_EN), end
.RD_DATA(RD_DATA), end
.RD_EMPTY(RD_EMPTY)
);
`S_TXPORTGATE128_OPENING: begin // Write the len, off, last (again)
_rAck = 0;
// rClosed catches a transfer that opens and subsequently closes
// without writing data
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE128_CLOSED;
else begin
_rState = `S_TXPORTGATE128_OPEN;
_rOpen = CHNL_TX & rChnlTx;
end
end
end
// Pass the transaction open event, transaction data, and the transaction `S_TXPORTGATE128_OPEN: begin // Copy channel data into the FIFO
// close event through to the RD_CLK domain via the async_fifo. if (!wFifoFull) begin
always @ (posedge CHNL_CLK) begin // CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
rState <= #1 (RST ? `S_TXPORTGATE128_IDLE : _rState); // but the VALID+REN model seem to make this difficult.
rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen); _rFifoWen = CHNL_TX_DATA_VALID;
rFifoData <= #1 _rFifoData; _rFifoData = {1'd0, CHNL_TX_DATA};
rAck <= #1 (RST ? 1'd0 : _rAck); end
rPause <= #1 (RST ? 1'd0 : _rPause); if (!rChnlTx)
rClosed <= #1 (RST ? 1'd0 : _rClosed); _rState = `S_TXPORTGATE128_CLOSED;
end _rOpen = CHNL_TX & rChnlTx;
end
always @ (*) begin `S_TXPORTGATE128_CLOSED: begin // Write the end marker (twice)
_rState = rState; if (!wFifoFull) begin
_rFifoWen = rFifoWen; _rPause = 1;
_rFifoData = rFifoData; _rFifoWen = 1;
_rPause = rPause; _rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
_rAck = rAck; if (rPause)
_rClosed = rClosed; _rState = `S_TXPORTGATE128_IDLE;
case (rState) end
end
`S_TXPORTGATE128_IDLE: begin // Write the len, off, last endcase
_rPause = 0; end
_rClosed = 0;
if (!wFifoFull) begin
_rAck = rChnlTx;
_rFifoWen = rChnlTx;
_rFifoData = {1'd1, 64'd0, rChnlLen, rChnlOff, rChnlLast};
if (rChnlTx)
_rState = `S_TXPORTGATE128_OPENING;
end
end
`S_TXPORTGATE128_OPENING: begin // Write the len, off, last (again)
_rAck = 0;
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE128_CLOSED;
else
_rState = `S_TXPORTGATE128_OPEN;
end
end
`S_TXPORTGATE128_OPEN: begin // Copy channel data into the FIFO
if (!wFifoFull) begin
_rFifoWen = CHNL_TX_DATA_VALID; // CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
_rFifoData = {1'd0, CHNL_TX_DATA}; // but the VALID+REN model seem to make this difficult.
end
if (!rChnlTx)
_rState = `S_TXPORTGATE128_CLOSED;
end
`S_TXPORTGATE128_CLOSED: begin // Write the end marker (twice)
if (!wFifoFull) begin
_rPause = 1;
_rFifoWen = 1;
_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
if (rPause)
_rState = `S_TXPORTGATE128_IDLE;
end
end
endcase
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CHNL_CLK),
.CONTROL(wControl0),
.TRIG0({4'd0, wFifoFull, CHNL_TX, rState}),
.DATA({313'd0,
rChnlOff, // 31
rChnlLen, // 32
rChnlLast, // 1
rChnlTx, // 1
CHNL_TX_OFF, // 31
CHNL_TX_LEN, // 32
CHNL_TX_LAST, // 1
CHNL_TX, // 1
wFifoFull, // 1
rFifoData, // 65
rFifoWen, // 1
rState}) // 2
);
*/
endmodule endmodule

307
fpga/riffa_hdl/tx_port_channel_gate_32.v
View File

@ -33,191 +33,172 @@
// DAMAGE. // DAMAGE.
// ---------------------------------------------------------------------- // ----------------------------------------------------------------------
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// Filename: tx_port_channel_gate_32.v // Filename: tx_port_channel_gate_32.v
// Version: 1.00.a // Version: 1.00.a
// Verilog Standard: Verilog-2001 // Verilog Standard: Verilog-2001
// Description: Captures transaction open/close events as well as data // Description: Captures transaction open/close events as well as data
// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can // and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can
// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When // only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When
// CHNL_TX drops, the channel closes (until the next transaction -- signaled by // CHNL_TX drops, the channel closes (until the next transaction -- signaled by
// CHNL_TX going up again). // CHNL_TX going up again).
// Author: Matt Jacobsen // Author: Matt Jacobsen
// History: @mattj: Version 2.0 // History: @mattj: Version 2.0
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
`define S_TXPORTGATE32_IDLE 2'b00 `define S_TXPORTGATE32_IDLE 2'b00
`define S_TXPORTGATE32_OPENING 2'b01 `define S_TXPORTGATE32_OPENING 2'b01
`define S_TXPORTGATE32_OPEN 2'b10 `define S_TXPORTGATE32_OPEN 2'b10
`define S_TXPORTGATE32_CLOSED 2'b11 `define S_TXPORTGATE32_CLOSED 2'b11
`timescale 1ns/1ns `timescale 1ns/1ns
module tx_port_channel_gate_32 #( module tx_port_channel_gate_32
parameter C_DATA_WIDTH = 9'd32, #(parameter C_DATA_WIDTH = 9'd32,
// Local parameters // Local parameters
parameter C_FIFO_DEPTH = 8, parameter C_FIFO_DEPTH = 8,
parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1 parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH + 1)
) (input RST,
(
input RST,
input RD_CLK, // FIFO read clock input RD_CLK, // FIFO read clock
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data
output RD_EMPTY, // FIFO is empty output RD_EMPTY, // FIFO is empty
input RD_EN, // FIFO read enable input RD_EN, // FIFO read enable
input CHNL_CLK, // Channel write clock input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words) input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved output CHNL_TX_DATA_REN); // Channel write data has been recieved
);
(* syn_encoding = "user" *) (* syn_encoding = "user" *)
(* fsm_encoding = "user" *) (* fsm_encoding = "user" *)
reg [1:0] rState=`S_TXPORTGATE32_IDLE, _rState=`S_TXPORTGATE32_IDLE; reg [1:0] rState=`S_TXPORTGATE32_IDLE, _rState=`S_TXPORTGATE32_IDLE;
reg rFifoWen=0, _rFifoWen=0; reg rFifoWen=0, _rFifoWen=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0; reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0;
wire wFifoFull; wire wFifoFull;
reg rChnlTx=0, _rChnlTx=0; reg rChnlTx=0, _rChnlTx=0;
reg rChnlLast=0, _rChnlLast=0; reg rChnlLast=0, _rChnlLast=0;
reg [31:0] rChnlLen=0, _rChnlLen=0; reg [31:0] rChnlLen=0, _rChnlLen=0;
reg [30:0] rChnlOff=0, _rChnlOff=0; reg [30:0] rChnlOff=0, _rChnlOff=0;
reg rAck=0, _rAck=0; reg rAck=0, _rAck=0;
reg rPause=0, _rPause=0; reg rPause=0, _rPause=0;
reg rClosed=0, _rClosed=0; reg rClosed=0, _rClosed=0;
reg rOpen=0, _rOpen=0;
assign CHNL_TX_ACK = rAck;
assign CHNL_TX_DATA_REN = (rOpen & !wFifoFull); // S_TXPORTGATE32_OPEN
assign CHNL_TX_ACK = rAck; // Buffer the input signals that come from outside the tx_port.
assign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE32_OPEN always @ (posedge CHNL_CLK) begin
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
rChnlLast <= #1 _rChnlLast;
rChnlLen <= #1 _rChnlLen;
rChnlOff <= #1 _rChnlOff;
end
always @ (*) begin
_rChnlTx = CHNL_TX;
_rChnlLast = CHNL_TX_LAST;
_rChnlLen = CHNL_TX_LEN;
_rChnlOff = CHNL_TX_OFF;
end
// Buffer the input signals that come from outside the tx_port. // FIFO for temporarily storing data from the channel.
always @ (posedge CHNL_CLK) begin (* RAM_STYLE="DISTRIBUTED" *)
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx); async_fifo
rChnlLast <= #1 _rChnlLast; #(.C_WIDTH(C_FIFO_DATA_WIDTH),
rChnlLen <= #1 _rChnlLen; .C_DEPTH(C_FIFO_DEPTH))
rChnlOff <= #1 _rChnlOff; fifo
end (.WR_CLK(CHNL_CLK),
.WR_RST(RST),
.WR_EN(rFifoWen),
.WR_DATA(rFifoData),
.WR_FULL(wFifoFull),
.RD_CLK(RD_CLK),
.RD_RST(RST),
.RD_EN(RD_EN),
.RD_DATA(RD_DATA),
.RD_EMPTY(RD_EMPTY));
always @ (*) begin // Pass the transaction open event, transaction data, and the transaction
_rChnlTx = CHNL_TX; // close event through to the RD_CLK domain via the async_fifo.
_rChnlLast = CHNL_TX_LAST; always @ (posedge CHNL_CLK) begin
_rChnlLen = CHNL_TX_LEN; rState <= #1 (RST ? `S_TXPORTGATE32_IDLE : _rState);
_rChnlOff = CHNL_TX_OFF; rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
end rFifoData <= #1 _rFifoData;
rAck <= #1 (RST ? 1'd0 : _rAck);
rPause <= #1 (RST ? 1'd0 : _rPause);
rClosed <= #1 (RST ? 1'd0 : _rClosed);
rOpen <= #1 (RST ? 1'd0 : _rOpen);
end
always @ (*) begin
_rState = rState;
_rFifoWen = rFifoWen;
_rFifoData = rFifoData;
_rPause = rPause;
_rAck = rAck;
_rClosed = rClosed;
_rOpen = rOpen;
case (rState)
// FIFO for temporarily storing data from the channel. `S_TXPORTGATE32_IDLE: begin // Write the len
(* RAM_STYLE="DISTRIBUTED" *) _rPause = 0;
async_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo ( _rClosed = 0;
.WR_CLK(CHNL_CLK), _rOpen = 0;
.WR_RST(RST), if (!wFifoFull) begin
.WR_EN(rFifoWen), _rFifoWen = rChnlTx;
.WR_DATA(rFifoData), _rFifoData = {1'd1, rChnlLen};
.WR_FULL(wFifoFull), if (rChnlTx)
.RD_CLK(RD_CLK), _rState = `S_TXPORTGATE32_OPENING;
.RD_RST(RST), end
.RD_EN(RD_EN), end
.RD_DATA(RD_DATA),
.RD_EMPTY(RD_EMPTY)
);
`S_TXPORTGATE32_OPENING: begin // Write the off, last
// rClosed catches a transfer that opens and subsequently closes
// without writing data
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
_rAck = rChnlTx;
_rFifoData = {1'd1, rChnlOff, rChnlLast};
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE32_CLOSED;
else begin
_rState = `S_TXPORTGATE32_OPEN;
_rOpen = CHNL_TX & rChnlTx;
end
end
end
// Pass the transaction open event, transaction data, and the transaction `S_TXPORTGATE32_OPEN: begin // Copy channel data into the FIFO
// close event through to the RD_CLK domain via the async_fifo. _rAck = 0;
always @ (posedge CHNL_CLK) begin if (!wFifoFull) begin
rState <= #1 (RST ? `S_TXPORTGATE32_IDLE : _rState); // CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen); // but the VALID+REN model seem to make this difficult.
rFifoData <= #1 _rFifoData; _rFifoWen = CHNL_TX_DATA_VALID;
rAck <= #1 (RST ? 1'd0 : _rAck); _rFifoData = {1'd0, CHNL_TX_DATA};
rPause <= #1 (RST ? 1'd0 : _rPause); end
rClosed <= #1 (RST ? 1'd0 : _rClosed); if (!rChnlTx)
end _rState = `S_TXPORTGATE32_CLOSED;
_rOpen = CHNL_TX & rChnlTx;
end
always @ (*) begin `S_TXPORTGATE32_CLOSED: begin // Write the end marker (twice)
_rState = rState; _rAck = 0;
_rFifoWen = rFifoWen; if (!wFifoFull) begin
_rFifoData = rFifoData; _rPause = 1;
_rPause = rPause; _rFifoWen = 1;
_rAck = rAck; _rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
_rClosed = rClosed; if (rPause)
case (rState) _rState = `S_TXPORTGATE32_IDLE;
end
end
`S_TXPORTGATE32_IDLE: begin // Write the len endcase
_rPause = 0;
_rClosed = 0;
if (!wFifoFull) begin
_rFifoWen = rChnlTx;
_rFifoData = {1'd1, rChnlLen};
if (rChnlTx)
_rState = `S_TXPORTGATE32_OPENING;
end
end
`S_TXPORTGATE32_OPENING: begin // Write the off, last end
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
_rAck = rChnlTx;
_rFifoData = {1'd1, rChnlOff, rChnlLast};
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE32_CLOSED;
else
_rState = `S_TXPORTGATE32_OPEN;
end
end
`S_TXPORTGATE32_OPEN: begin // Copy channel data into the FIFO
_rAck = 0;
if (!wFifoFull) begin
_rFifoWen = CHNL_TX_DATA_VALID; // CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
_rFifoData = {1'd0, CHNL_TX_DATA}; // but the VALID+REN model seem to make this difficult.
end
if (!rChnlTx)
_rState = `S_TXPORTGATE32_CLOSED;
end
`S_TXPORTGATE32_CLOSED: begin // Write the end marker (twice)
_rAck = 0;
if (!wFifoFull) begin
_rPause = 1;
_rFifoWen = 1;
_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
if (rPause)
_rState = `S_TXPORTGATE32_IDLE;
end
end
endcase
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CHNL_CLK),
.CONTROL(wControl0),
.TRIG0({4'd0, wFifoFull, CHNL_TX, rState}),
.DATA({313'd0,
rChnlOff, // 31
rChnlLen, // 32
rChnlLast, // 1
rChnlTx, // 1
CHNL_TX_OFF, // 31
CHNL_TX_LEN, // 32
CHNL_TX_LAST, // 1
CHNL_TX, // 1
wFifoFull, // 1
rFifoData, // 65
rFifoWen, // 1
rState}) // 2
);
*/
endmodule endmodule

304
fpga/riffa_hdl/tx_port_channel_gate_64.v
View File

@ -33,189 +33,169 @@
// DAMAGE. // DAMAGE.
// ---------------------------------------------------------------------- // ----------------------------------------------------------------------
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// Filename: tx_port_channel_gate_64.v // Filename: tx_port_channel_gate_64.v
// Version: 1.00.a // Version: 1.00.a
// Verilog Standard: Verilog-2001 // Verilog Standard: Verilog-2001
// Description: Captures transaction open/close events as well as data // Description: Captures transaction open/close events as well as data
// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can // and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can
// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When // only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When
// CHNL_TX drops, the channel closes (until the next transaction -- signaled by // CHNL_TX drops, the channel closes (until the next transaction -- signaled by
// CHNL_TX going up again). // CHNL_TX going up again).
// Author: Matt Jacobsen // Author: Matt Jacobsen
// History: @mattj: Version 2.0 // History: @mattj: Version 2.0
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
`define S_TXPORTGATE64_IDLE 2'b00 `define S_TXPORTGATE64_IDLE 2'b00
`define S_TXPORTGATE64_OPENING 2'b01 `define S_TXPORTGATE64_OPENING 2'b01
`define S_TXPORTGATE64_OPEN 2'b10 `define S_TXPORTGATE64_OPEN 2'b10
`define S_TXPORTGATE64_CLOSED 2'b11 `define S_TXPORTGATE64_CLOSED 2'b11
`timescale 1ns/1ns `timescale 1ns/1ns
module tx_port_channel_gate_64 #( module tx_port_channel_gate_64
parameter C_DATA_WIDTH = 9'd64, #(parameter C_DATA_WIDTH = 9'd64,
// Local parameters // Local parameters
parameter C_FIFO_DEPTH = 8, parameter C_FIFO_DEPTH = 8,
parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1 parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH + 1)
) (input RST,
(
input RST,
input RD_CLK, // FIFO read clock input RD_CLK, // FIFO read clock
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data
output RD_EMPTY, // FIFO is empty output RD_EMPTY, // FIFO is empty
input RD_EN, // FIFO read enable input RD_EN, // FIFO read enable
input CHNL_CLK, // Channel write clock input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words) input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved output CHNL_TX_DATA_REN); // Channel write data has been recieved
);
(* syn_encoding = "user" *) (* syn_encoding = "user" *)
(* fsm_encoding = "user" *) (* fsm_encoding = "user" *)
reg [1:0] rState=`S_TXPORTGATE64_IDLE, _rState=`S_TXPORTGATE64_IDLE; reg [1:0] rState=`S_TXPORTGATE64_IDLE, _rState=`S_TXPORTGATE64_IDLE;
reg rFifoWen=0, _rFifoWen=0; reg rFifoWen=0, _rFifoWen=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0; reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0;
wire wFifoFull; wire wFifoFull;
reg rChnlTx=0, _rChnlTx=0; reg rChnlTx=0, _rChnlTx=0;
reg rChnlLast=0, _rChnlLast=0; reg rChnlLast=0, _rChnlLast=0;
reg [31:0] rChnlLen=0, _rChnlLen=0; reg [31:0] rChnlLen=0, _rChnlLen=0;
reg [30:0] rChnlOff=0, _rChnlOff=0; reg [30:0] rChnlOff=0, _rChnlOff=0;
reg rAck=0, _rAck=0; reg rAck=0, _rAck=0;
reg rPause=0, _rPause=0; reg rPause=0, _rPause=0;
reg rClosed=0, _rClosed=0; reg rClosed=0, _rClosed=0;
reg rOpen=0, _rOpen=0;
assign CHNL_TX_ACK = rAck;
assign CHNL_TX_DATA_REN = (rOpen & !wFifoFull); // S_TXPORTGATE128_OPEN
assign CHNL_TX_ACK = rAck; // Buffer the input signals that come from outside the tx_port.
assign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE64_OPEN always @ (posedge CHNL_CLK) begin
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
rChnlLast <= #1 _rChnlLast;
rChnlLen <= #1 _rChnlLen;
rChnlOff <= #1 _rChnlOff;
end
always @ (*) begin
_rChnlTx = CHNL_TX;
_rChnlLast = CHNL_TX_LAST;
_rChnlLen = CHNL_TX_LEN;
_rChnlOff = CHNL_TX_OFF;
end
// Buffer the input signals that come from outside the tx_port. // FIFO for temporarily storing data from the channel.
always @ (posedge CHNL_CLK) begin (* RAM_STYLE="DISTRIBUTED" *)
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx); async_fifo
rChnlLast <= #1 _rChnlLast; #(.C_WIDTH(C_FIFO_DATA_WIDTH),
rChnlLen <= #1 _rChnlLen; .C_DEPTH(C_FIFO_DEPTH))
rChnlOff <= #1 _rChnlOff; fifo
end (.WR_CLK(CHNL_CLK),
.WR_RST(RST),
.WR_EN(rFifoWen),
.WR_DATA(rFifoData),
.WR_FULL(wFifoFull),
.RD_CLK(RD_CLK),
.RD_RST(RST),
.RD_EN(RD_EN),
.RD_DATA(RD_DATA),
.RD_EMPTY(RD_EMPTY));
always @ (*) begin // Pass the transaction open event, transaction data, and the transaction
_rChnlTx = CHNL_TX; // close event through to the RD_CLK domain via the async_fifo.
_rChnlLast = CHNL_TX_LAST; always @ (posedge CHNL_CLK) begin
_rChnlLen = CHNL_TX_LEN; rState <= #1 (RST ? `S_TXPORTGATE64_IDLE : _rState);
_rChnlOff = CHNL_TX_OFF; rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
end rFifoData <= #1 _rFifoData;
rAck <= #1 (RST ? 1'd0 : _rAck);
rPause <= #1 (RST ? 1'd0 : _rPause);
rClosed <= #1 (RST ? 1'd0 : _rClosed);
rOpen <= #1 (RST ? 1'd0 : _rOpen);
end
always @ (*) begin
_rState = rState;
_rFifoWen = rFifoWen;
_rFifoData = rFifoData;
_rPause = rPause;
_rAck = rAck;
_rClosed = rClosed;
_rOpen = rOpen;
case (rState)
// FIFO for temporarily storing data from the channel. `S_TXPORTGATE64_IDLE: begin // Write the len, off, last
(* RAM_STYLE="DISTRIBUTED" *) _rPause = 0;
async_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo ( _rClosed = 0;
.WR_CLK(CHNL_CLK), _rOpen = 0;
.WR_RST(RST), if (!wFifoFull) begin
.WR_EN(rFifoWen), _rAck = rChnlTx;
.WR_DATA(rFifoData), _rFifoWen = rChnlTx;
.WR_FULL(wFifoFull), _rFifoData = {1'd1, rChnlLen, rChnlOff, rChnlLast};
.RD_CLK(RD_CLK), if (rChnlTx)
.RD_RST(RST), _rState = `S_TXPORTGATE64_OPENING;
.RD_EN(RD_EN), end
.RD_DATA(RD_DATA), end
.RD_EMPTY(RD_EMPTY)
);
`S_TXPORTGATE64_OPENING: begin // Write the len, off, last (again)
_rAck = 0;
// rClosed catches a transfer that opens and subsequently closes
// without writing data
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE64_CLOSED;
else begin
_rState = `S_TXPORTGATE64_OPEN;
_rOpen = CHNL_TX & rChnlTx;
end
end
end
// Pass the transaction open event, transaction data, and the transaction `S_TXPORTGATE64_OPEN: begin // Copy channel data into the FIFO
// close event through to the RD_CLK domain via the async_fifo. if (!wFifoFull) begin
always @ (posedge CHNL_CLK) begin // CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
rState <= #1 (RST ? `S_TXPORTGATE64_IDLE : _rState); // but the VALID+REN model seem to make this difficult.
rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen); _rFifoWen = CHNL_TX_DATA_VALID;
rFifoData <= #1 _rFifoData; _rFifoData = {1'd0, CHNL_TX_DATA};
rAck <= #1 (RST ? 1'd0 : _rAck); end
rPause <= #1 (RST ? 1'd0 : _rPause); if (!rChnlTx)
rClosed <= #1 (RST ? 1'd0 : _rClosed); _rState = `S_TXPORTGATE64_CLOSED;
end _rOpen = CHNL_TX & rChnlTx;
end
always @ (*) begin `S_TXPORTGATE64_CLOSED: begin // Write the end marker (twice)
_rState = rState; if (!wFifoFull) begin
_rFifoWen = rFifoWen; _rPause = 1;
_rFifoData = rFifoData; _rFifoWen = 1;
_rPause = rPause; _rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
_rAck = rAck; if (rPause)
_rClosed = rClosed; _rState = `S_TXPORTGATE64_IDLE;
case (rState) end
end
`S_TXPORTGATE64_IDLE: begin // Write the len, off, last endcase
_rPause = 0; end
_rClosed = 0;
if (!wFifoFull) begin
_rAck = rChnlTx;
_rFifoWen = rChnlTx;
_rFifoData = {1'd1, rChnlLen, rChnlOff, rChnlLast};
if (rChnlTx)
_rState = `S_TXPORTGATE64_OPENING;
end
end
`S_TXPORTGATE64_OPENING: begin // Write the len, off, last (again)
_rAck = 0;
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE64_CLOSED;
else
_rState = `S_TXPORTGATE64_OPEN;
end
end
`S_TXPORTGATE64_OPEN: begin // Copy channel data into the FIFO
if (!wFifoFull) begin
_rFifoWen = CHNL_TX_DATA_VALID; // CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
_rFifoData = {1'd0, CHNL_TX_DATA}; // but the VALID+REN model seem to make this difficult.
end
if (!rChnlTx)
_rState = `S_TXPORTGATE64_CLOSED;
end
`S_TXPORTGATE64_CLOSED: begin // Write the end marker (twice)
if (!wFifoFull) begin
_rPause = 1;
_rFifoWen = 1;
_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
if (rPause)
_rState = `S_TXPORTGATE64_IDLE;
end
end
endcase
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CHNL_CLK),
.CONTROL(wControl0),
.TRIG0({4'd0, wFifoFull, CHNL_TX, rState}),
.DATA({313'd0,
rChnlOff, // 31
rChnlLen, // 32
rChnlLast, // 1
rChnlTx, // 1
CHNL_TX_OFF, // 31
CHNL_TX_LEN, // 32
CHNL_TX_LAST, // 1
CHNL_TX, // 1
wFifoFull, // 1
rFifoData, // 65
rFifoWen, // 1
rState}) // 2
);
*/
endmodule endmodule

5
python/riffa.py
View File

@ -48,6 +48,9 @@ if platform.system() == "Linux":
else: else:
libriffa = ctypes.CDLL("riffa.dll") libriffa = ctypes.CDLL("riffa.dll")
libriffa.fpga_recv.argtypes = [ctypes.c_void_p, ctypes.c_int, ctypes.c_void_p, ctypes.c_int, ctypes.c_longlong]
libriffa.fpga_send.argtypes = [ctypes.c_void_p, ctypes.c_int, ctypes.c_void_p, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_longlong]
class FpgaInfoList(ctypes.Structure): class FpgaInfoList(ctypes.Structure):
_fields_ = [("num_fpgas", ctypes.c_int), _fields_ = [("num_fpgas", ctypes.c_int),
("id", ctypes.c_int * NUM_FPGAS), ("id", ctypes.c_int * NUM_FPGAS),
@ -156,7 +159,7 @@ def fpga_recv(fd, chnl, data, timeout):
ctypes.pythonapi.PyObject_AsReadBuffer(obj, ctypes.byref(a), ctypes.byref(l)) ctypes.pythonapi.PyObject_AsReadBuffer(obj, ctypes.byref(a), ctypes.byref(l))
ptr = a.value ptr = a.value
datalen = l.value datalen = l.value
return libriffa.fpga_recv(fd, chnl, ptr, datalen/4, timeout) return libriffa.fpga_recv(fd, chnl, ptr, datalen//4, timeout)
# Resets the state of the FPGA and all transfers across all channels. This is # Resets the state of the FPGA and all transfers across all channels. This is