diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/bit/VC709_Gen1x8If64.bit b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/bit/VC709_Gen1x8If64_CLK.bit similarity index 100% rename from fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/bit/VC709_Gen1x8If64.bit rename to fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/bit/VC709_Gen1x8If64_CLK.bit diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/constr/VC709_Gen1x8If64.xdc b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/constr/VC709_Gen1x8If64_CLK.xdc similarity index 99% rename from fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/constr/VC709_Gen1x8If64.xdc rename to fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/constr/VC709_Gen1x8If64_CLK.xdc index 958153f..79401ca 100644 --- a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/constr/VC709_Gen1x8If64.xdc +++ b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/constr/VC709_Gen1x8If64_CLK.xdc @@ -33,7 +33,7 @@ # DAMAGE. # ---------------------------------------------------------------------- #---------------------------------------------------------------------------- -# Filename: VC709_Top.xdc +# Filename: VC709_Gen1x8If64_CLK.xdc # Version: 1.00.a # Verilog Standard: Verilog-2001 # Description: Xilinx Design Constraints for the VC709 board. diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/hdl/VC709_Gen1x8If64.v b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/hdl/VC709_Gen1x8If64_CLK.v similarity index 100% rename from fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/hdl/VC709_Gen1x8If64.v rename to fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/hdl/VC709_Gen1x8If64_CLK.v diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/prj/VC709_Gen1x8If64.xpr b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/prj/VC709_Gen1x8If64_CLK.xpr similarity index 97% rename from fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/prj/VC709_Gen1x8If64.xpr rename to fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/prj/VC709_Gen1x8If64_CLK.xpr index d366bc4..c9a2474 100644 --- a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/prj/VC709_Gen1x8If64.xpr +++ b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/prj/VC709_Gen1x8If64_CLK.xpr @@ -3,7 +3,7 @@ - + @@ -691,7 +691,7 @@ - + @@ -706,14 +706,14 @@ - + - @@ -790,35 +790,31 @@ - + - - + - - + - - + - - + @@ -831,7 +827,6 @@ - diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/bit/VC709_Gen2x8If128.bit b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/bit/VC709_Gen2x8If128_CLK.bit similarity index 100% rename from fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/bit/VC709_Gen2x8If128.bit rename to fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/bit/VC709_Gen2x8If128_CLK.bit diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/constr/VC709_Gen2x8If128.xdc b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/constr/VC709_Gen2x8If128_CLK.xdc similarity index 99% rename from fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/constr/VC709_Gen2x8If128.xdc rename to fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/constr/VC709_Gen2x8If128_CLK.xdc index e1109d2..6e20f0f 100644 --- a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/constr/VC709_Gen2x8If128.xdc +++ b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/constr/VC709_Gen2x8If128_CLK.xdc @@ -33,7 +33,7 @@ # DAMAGE. # ---------------------------------------------------------------------- #---------------------------------------------------------------------------- -# Filename: VC709_Top.xdc +# Filename: VC709_Gen2x8If128_CLK.xdc # Version: 1.00.a # Verilog Standard: Verilog-2001 # Description: Xilinx Design Constraints for the VC709 board. diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/hdl/VC709_Gen2x8If128.v b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/hdl/VC709_Gen2x8If128_CLK.v similarity index 100% rename from fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/hdl/VC709_Gen2x8If128.v rename to fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/hdl/VC709_Gen2x8If128_CLK.v diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/clk_250MIn_1/clk_250MIn_1.xci b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/clk_250MIn_1/clk_250MIn_1.xci index e2c02a3..14f7946 100644 --- a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/clk_250MIn_1/clk_250MIn_1.xci +++ b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/clk_250MIn_1/clk_250MIn_1.xci @@ -19,61 +19,61 @@ clkfb_out clkfb_out_p clkfb_stopped - 40.0 + 100.0 100.0 BUFG 50.0 - 5.000 + 100.000 0.000 50.000 - 5 + 100.000 0.000 1 BUFG - 50.0 - 10.000 + 50.000 + 100.000 0.000 50.000 - 10 + 100.000 0.000 1 - 1 + 0 BUFG - 50.0 - 24.800 + 50.000 + 100.000 0.000 50.000 - 25 + 100.000 0.000 1 - 1 + 0 BUFG - 50.0 - 51.667 + 50.000 + 100.000 0.000 50.000 - 50 + 100.000 0.000 1 - 1 + 0 BUFG - 50.0 - 77.500 + 50.000 + 100.000 0.000 50.000 - 75 + 100.000 0.000 1 - 1 + 0 BUFG - 50.0 - 103.333 + 50.000 + 100.000 0.000 50.000 100.000 0.000 1 - 1 + 0 BUFG 50.000 100.000 @@ -85,12 +85,12 @@ 0 VCO clk_in_sel - riffa_5_clk - riffa_10_clk - riffa_25_clk - riffa_50_clk - riffa_75_clk - riffa_100_clk + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 clk_out7 CLK_VALID NA @@ -105,41 +105,41 @@ FDBK_AUTO 0 Input Clock Freq (MHz) Input Jitter (UI) - __primary_____________250____________0.010 + __primary_________100.000____________0.010 no_secondary_input_clock input_clk_stopped 0 Units_MHz No_Jitter - clk_locked + locked OPTIMIZED - 62.000 + 10.000 0.000 FALSE - 4.0 + 10.0 10.0 - 124.000 + 10.000 0.500 0.000 FALSE - 62 + 1 0.500 0.000 FALSE - 25 + 1 0.500 0.000 FALSE - 12 + 1 0.500 0.000 FALSE FALSE - 8 + 1 0.500 0.000 FALSE - 6 + 1 0.500 0.000 FALSE @@ -149,20 +149,20 @@ FALSE FALSE ZHOLD - 25 + 1 None 0.010 0.010 FALSE - 6 + 1 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - CLK_OUT1_____5.000______0.000______50.0______943.594____894.366 - CLK_OUT2____10.000______0.000______50.0______855.836____894.366 - CLK_OUT3____24.800______0.000______50.0______752.191____894.366 - CLK_OUT4____51.667______0.000______50.0______678.319____894.366 - CLK_OUT5____77.500______0.000______50.0______641.055____894.366 - CLK_OUT6___103.333______0.000______50.0______615.875____894.366 + CLK_OUT1___100.000______0.000______50.0______130.958_____98.575 + no_CLK_OUT2_output + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output no_CLK_OUT7_output 0 0 @@ -195,10 +195,10 @@ No notes 0.010 power_down - user_clk + clk_in1 MMCM AUTO - 250 + 100.000 0.010 10.000 Single_ended_clock_capable_pin @@ -207,7 +207,7 @@ psen psincdec 0 - clk_rst + reset 100.000 0.010 10.000 @@ -233,13 +233,13 @@ 1 0 0 - 0 + 1 0 0 0 0 0 - 0 + 1 0 0 0 @@ -255,58 +255,58 @@ clkfb_out clkfb_out_p clkfb_stopped - 40.0 + 100.0 0.010 100.0 0.010 BUFG - 943.594 - 894.366 + 130.958 + 98.575 50.000 - 5 + 100.000 0.000 1 true BUFG - 855.836 - 894.366 + 0.0 + 0.0 50.000 - 10 + 100.000 0.000 1 - true + false BUFG - 752.191 - 894.366 + 0.0 + 0.0 50.000 - 25 + 100.000 0.000 1 - true + false BUFG - 678.319 - 894.366 + 0.0 + 0.0 50.000 - 50 + 100.000 0.000 1 - true + false BUFG - 641.055 - 894.366 + 0.0 + 0.0 50.000 - 75 + 100.000 0.000 1 - true + false BUFG - 615.875 - 894.366 + 0.0 + 0.0 50.000 100.000 0.000 1 - true + false BUFG 0.0 0.0 @@ -319,17 +319,17 @@ Custom Custom clk_in_sel - riffa_5_clk + clk_out1 false - riffa_10_clk + clk_out2 false - riffa_25_clk + clk_out3 false - riffa_50_clk + clk_out4 false - riffa_75_clk + clk_out5 false - riffa_100_clk + clk_out6 false clk_out7 false @@ -355,35 +355,35 @@ Units_UI UI No_Jitter - clk_locked + locked OPTIMIZED - 62.000 + 10.000 0.000 false - 4.0 + 10.0 10.0 - 124.000 + 10.000 0.500 0.000 false - 62 + 1 0.500 0.000 false - 25 + 1 0.500 0.000 false - 12 + 1 0.500 0.000 false false - 8 + 1 0.500 0.000 false - 6 + 1 0.500 0.000 false @@ -393,12 +393,12 @@ false false ZHOLD - 25 + 1 None 0.010 0.010 false - 6 + 1 false false false @@ -431,10 +431,10 @@ None 0.010 power_down - user_clk + clk_in1 MMCM mmcm_adv - 250 + 100.000 0.010 10.000 Single_ended_clock_capable_pin @@ -444,7 +444,7 @@ psincdec REL_PRIMARY Custom - clk_rst + reset ACTIVE_HIGH 100.000 0.010 @@ -466,13 +466,13 @@ true false false - false + true false false false false false - false + true false false false @@ -499,61 +499,16 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/clk_250MIn_2/clk_250MIn_2.xci b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/clk_250MIn_2/clk_250MIn_2.xci index a8dadc0..5279cbf 100644 --- a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/clk_250MIn_2/clk_250MIn_2.xci +++ b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/clk_250MIn_2/clk_250MIn_2.xci @@ -23,36 +23,36 @@ 100.0 BUFG 50.0 - 250.000 + 125.000 0.000 50.000 - 250 + 125 0.000 1 BUFG 50.0 - 250.000 + 150.000 0.000 50.000 - 250 + 150 0.000 1 1 BUFG 50.0 - 250.000 + 187.500 0.000 50.000 - 250 + 175 0.000 1 1 BUFG 50.0 - 250.000 + 187.500 0.000 50.000 - 250 + 200 0.000 1 1 @@ -61,7 +61,7 @@ 250.000 0.000 50.000 - 250 + 225 0.000 1 1 @@ -111,18 +111,18 @@ 0 Units_MHz No_Jitter - clk_locked + locked OPTIMIZED - 4.000 + 3.000 0.000 FALSE 4.0 10.0 - 4.000 + 6.000 0.500 0.000 FALSE - 4 + 5 0.500 0.000 FALSE @@ -135,11 +135,11 @@ 0.000 FALSE FALSE - 4 + 3 0.500 0.000 FALSE - 4 + 3 0.500 0.000 FALSE @@ -157,12 +157,12 @@ 6 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - CLK_OUT1___250.000______0.000______50.0_______89.528_____85.928 - CLK_OUT2___250.000______0.000______50.0_______89.528_____85.928 - CLK_OUT3___250.000______0.000______50.0_______89.528_____85.928 - CLK_OUT4___250.000______0.000______50.0_______89.528_____85.928 - CLK_OUT5___250.000______0.000______50.0_______89.528_____85.928 - CLK_OUT6___250.000______0.000______50.0_______89.528_____85.928 + CLK_OUT1___125.000______0.000______50.0______100.001_____92.989 + CLK_OUT2___150.000______0.000______50.0_______96.482_____92.989 + CLK_OUT3___187.500______0.000______50.0_______92.345_____92.989 + CLK_OUT4___187.500______0.000______50.0_______92.345_____92.989 + CLK_OUT5___250.000______0.000______50.0_______87.277_____92.989 + CLK_OUT6___250.000______0.000______50.0_______87.277_____92.989 no_CLK_OUT7_output 0 0 @@ -196,7 +196,7 @@ 0.010 power_down user_clk - PLL + MMCM AUTO 250 0.010 @@ -207,7 +207,7 @@ psen psincdec 0 - clk_rst + reset 100.000 0.010 10.000 @@ -237,7 +237,7 @@ 0 0 0 - 0 + 1 0 0 0 @@ -260,56 +260,56 @@ 100.0 0.010 BUFG - 89.528 - 85.928 + 100.001 + 92.989 50.000 - 250 + 125 0.000 1 true BUFG - 89.528 - 85.928 + 96.482 + 92.989 50.000 - 250 + 150 0.000 1 true BUFG - 89.528 - 85.928 + 92.345 + 92.989 50.000 - 250 + 175 0.000 1 true BUFG - 89.528 - 85.928 + 92.345 + 92.989 50.000 - 250 + 200 0.000 1 true BUFG - 89.528 - 85.928 + 87.277 + 92.989 50.000 - 250 + 225 0.000 1 true BUFG - 89.528 - 85.928 + 87.277 + 92.989 50.000 250 0.000 1 true BUFG - 0.0 - 0.0 + 105.821 + 92.989 50.000 100.000 0.000 @@ -355,18 +355,18 @@ Units_UI UI No_Jitter - clk_locked + locked OPTIMIZED - 4 + 3.000 0.000 false 4.0 10.0 - 4 + 6.000 0.500 0.000 false - 4 + 5 0.500 0.000 false @@ -379,11 +379,11 @@ 0.000 false false - 4 + 3 0.500 0.000 false - 4 + 3 0.500 0.000 false @@ -432,7 +432,7 @@ 0.010 power_down user_clk - PLL + MMCM mmcm_adv 250 0.010 @@ -444,7 +444,7 @@ psincdec REL_PRIMARY Custom - clk_rst + reset ACTIVE_HIGH 100.000 0.010 @@ -470,7 +470,7 @@ false false false - false + true false false false @@ -500,45 +500,38 @@ - - - - - - - - + + + - - @@ -547,19 +540,12 @@ - + - - - - - - - @@ -567,3 +553,4 @@ + diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/prj/VC709_Gen2x8If128.xpr b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/prj/VC709_Gen2x8If128_CLK.xpr similarity index 89% rename from fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/prj/VC709_Gen2x8If128.xpr rename to fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/prj/VC709_Gen2x8If128_CLK.xpr index 15632e3..2f678db 100644 --- a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/prj/VC709_Gen2x8If128.xpr +++ b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/prj/VC709_Gen2x8If128_CLK.xpr @@ -3,7 +3,7 @@ - + @@ -663,6 +663,20 @@ + + + + + + + + + + + + + + @@ -677,7 +691,7 @@ - + @@ -692,14 +706,14 @@ - + - @@ -726,32 +740,6 @@ @@ -775,35 +763,19 @@ - + - - + - - - - - - - - - - - - - - - - + @@ -816,7 +788,6 @@ - @@ -832,33 +803,5 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - -