diff --git a/c_c++/linux/x64/test_apps/asyncutil.sh b/c_c++/linux/x64/test_apps/asyncutil.sh new file mode 100755 index 0000000..63112f1 --- /dev/null +++ b/c_c++/linux/x64/test_apps/asyncutil.sh @@ -0,0 +1,60 @@ +#!/bin/bash +# ---------------------------------------------------------------------- +# Copyright (c) 2016, The Regents of the University of California All +# rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# +# * Neither the name of The Regents of the University of California +# nor the names of its contributors may be used to endorse or +# promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE +# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +# DAMAGE. +# ---------------------------------------------------------------------- + +PATH=$PATH:./ +RESULT_PATH=./results/ + +if [ "$#" -lt 2 ]; then + echo "usage: $0 " + exit +fi + +for i in {0..11} +do + testutil 1 $1 + + # Run full bandwidth test + testutil 2 $1 $i 1048576 | tee $RESULT_PATH/$2_C$i\_bw.txt + + # Run RX Sweep Test + testutil 3 $1 $i 2048 | tee $RESULT_PATH/$2_C$i\_rx.txt + + # Run TX Sweep Test + testutil 4 $1 $i 2048 | tee $RESULT_PATH/$2_C$i\_tx.txt + +done + + diff --git a/fpga/altera/de5/DE5QGen1x8If64_CLK/Makefile b/fpga/altera/de5/DE5QGen1x8If64_CLK/Makefile new file mode 100644 index 0000000..c7c66f2 --- /dev/null +++ b/fpga/altera/de5/DE5QGen1x8If64_CLK/Makefile @@ -0,0 +1,63 @@ +# ---------------------------------------------------------------------- +# Copyright (c) 2016, The Regents of the University of California All +# rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# +# * Neither the name of The Regents of the University of California +# nor the names of its contributors may be used to endorse or +# promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE +# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +# DAMAGE. +# ---------------------------------------------------------------------- +#----------------------------------------------------------------------- +# Filename: Makefile +# Version: 1.0 +# Description: Project-level makefile for building an example project +# Author: Dustin Richmond (@darichmond) +#----------------------------------------------------------------------- +# This make file expects the following variables to be set: +# RIFFA_HDL_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory. +# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to +# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory +WIDTH=64 +TYPE=classic +CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))) +PROJECT=$(shell basename $(CURRENT_PATH)) + +ifndef RIFFA_HDL_PATH + RIFFA_HDL_PATH:=../../../riffa_hdl +endif +ifndef BOARD_PATH + BOARD_PATH:=.. +endif +ifndef JOBS + JOBS=1 +endif +include $(RIFFA_HDL_PATH)/riffa.mk +include $(BOARD_PATH)/board.mk + +PROJECT_IP+=ip/QSysDE5QGen1x8If64.qsys +RELEASE_IP+=ip/QSysDE5QGen1x8If64.qsys diff --git a/fpga/altera/de5/DE5QGen1x8If64_CLK/bit/DE5QGen1x8If64.sof b/fpga/altera/de5/DE5QGen1x8If64_CLK/bit/DE5QGen1x8If64.sof new file mode 100644 index 0000000..c4598ab Binary files /dev/null and b/fpga/altera/de5/DE5QGen1x8If64_CLK/bit/DE5QGen1x8If64.sof differ diff --git a/fpga/altera/de5/DE5QGen1x8If64_CLK/constr/DE5QGen1x8If64.sdc b/fpga/altera/de5/DE5QGen1x8If64_CLK/constr/DE5QGen1x8If64.sdc new file mode 100644 index 0000000..0fd76ec --- /dev/null +++ b/fpga/altera/de5/DE5QGen1x8If64_CLK/constr/DE5QGen1x8If64.sdc @@ -0,0 +1,110 @@ +# ---------------------------------------------------------------------- +# Copyright (c) 2016, The Regents of the University of California All +# rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# +# * Neither the name of The Regents of the University of California +# nor the names of its contributors may be used to endorse or +# promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE +# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +# DAMAGE. +# ---------------------------------------------------------------------- +#---------------------------------------------------------------------------- +# Filename: DE5Gen1x8If64.sdc (Qsys) +# Version: 1.00.a +# Verilog Standard: Verilog-2001 +# Description: Synopsys Design Constraints for the DE5 board. +# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input +# Author: Dustin Richmond (@darichmond) +#----------------------------------------------------------------------------- +create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}] +create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}] +create_clock -name riffa_5_clk -period 200 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_10_clk -period 100 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_25_clk -period 40 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_50_clk -period 20 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_75_clk -period 13.3 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_100_clk -period 10 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_125_clk -period 8 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_150_clk -period 6.66 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_175_clk -period 6 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[8].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_200_clk -period 5.33 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[9].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_225_clk -period 4.66 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[10].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_250_clk -period 4 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[11].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name user_clk -period 4 [get_pins {pcie_system_inst|pciegen1x8if64|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout}] +set_clock_groups -asynchronous -group {user_clk} -group {riffa_5_clk} -group {riffa_10_clk} -group {riffa_25_clk} -group {riffa_50_clk} -group {riffa_75_clk} -group {riffa_100_clk} -group {riffa_125_clk} -group {riffa_150_clk} -group {riffa_175_clk} -group {riffa_200_clk} -group {riffa_225_clk} -group {riffa_250_clk} + +################################################################################ +# 13.1 Workround for http://www.altera.com/support/kdb/solutions/rd12162013_581.html?GSA_pos=1&WT.oss_r=1&WT.oss=adce_off_r +################################################################################ + +# set_false_path -to [get_registers *|*.adce_off_r[0]] +# set_false_path -to [get_registers *|*.adce_on_rr[0]] +# set_false_path -to [get_registers *|reset_sync_pldclk_r[*]] + +################################################################################ +# End Workround +################################################################################ + +derive_pll_clocks -create_base_clocks +derive_clock_uncertainty + +################################################################################ +# Imports from Example Design (altera/13.1/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/) +################################################################################ + +###################################################################### +# HIP Soft reset controller SDC constraints (Gen 3 only) +set_false_path -to [get_registers *altpcie_rs_serdes|fifo_err_sync_r[0]] +set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*] + +# HIP testin pins SDC constraints +set_false_path -from [get_pins -compatibility_mode *hip_ctrl*] + +###################################################################### +# Constraints for CV SIG asynchonous logic +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|test_out[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqout[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqber[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_lf[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_fs[*]}] + diff --git a/fpga/altera/de5/DE5QGen1x8If64_CLK/hdl/DE5QGen1x8If64.v b/fpga/altera/de5/DE5QGen1x8If64_CLK/hdl/DE5QGen1x8If64.v new file mode 100644 index 0000000..f110b33 --- /dev/null +++ b/fpga/altera/de5/DE5QGen1x8If64_CLK/hdl/DE5QGen1x8If64.v @@ -0,0 +1,668 @@ +// ---------------------------------------------------------------------- +// Copyright (c) 2016, The Regents of the University of California All +// rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above +// copyright notice, this list of conditions and the following +// disclaimer in the documentation and/or other materials provided +// with the distribution. +// +// * Neither the name of The Regents of the University of California +// nor the names of its contributors may be used to endorse or +// promote products derived from this software without specific +// prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE +// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +// DAMAGE. +// ---------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// Filename: DE5QGen1x8If64.v +// Version: +// Verilog Standard: Verilog-2001 +// Description: Top level module for RIFFA 2.2 reference design for the +// the Altera Stratix V Avalong Streaming Interface to PCI +// Express module and the Terasic DE5 Development Board. +// Author: Dustin Richmond (@darichmond) +//----------------------------------------------------------------------------- +`include "functions.vh" +`include "riffa.vh" +`include "altera.vh" +`timescale 1ps / 1ps +module DE5QGen1x8If64 + #(// Number of RIFFA Channels + parameter C_NUM_CHNL = 12, + // Number of PCIe Lanes + parameter C_NUM_LANES = 8, + // Settings from Quartus IP Library + parameter C_PCI_DATA_WIDTH = 64, + parameter C_MAX_PAYLOAD_BYTES = 256, + parameter C_LOG_NUM_TAGS = 5 + ) + ( + // ----------LEDs---------- + output [7:0] LED, + + // ----------PCIE---------- + input PCIE_RESET_N, + input PCIE_REFCLK, + + // ----------PCIE Serial RX---------- + input [C_NUM_LANES-1:0] PCIE_RX_IN, + + // ----------PCIE Serial TX---------- + output [C_NUM_LANES-1:0] PCIE_TX_OUT, + + // ----------Oscillators---------- + input OSC_BANK3D_50MHZ + ); + + wire npor; + wire pin_perst; + + // ----------TL Config interface---------- + wire [3:0] tl_cfg_add; + wire [31:0] tl_cfg_ctl; + wire [52:0] tl_cfg_sts; + + // ----------Rx/TX Interfaces---------- + wire [0:0] rx_st_sop; + wire [0:0] rx_st_eop; + wire [0:0] rx_st_err; + wire [0:0] rx_st_valid; + wire rx_st_ready; + wire [C_PCI_DATA_WIDTH-1:0] rx_st_data; + wire [0:0] rx_st_empty; + + wire [0:0] tx_st_sop; + wire [0:0] tx_st_eop; + wire [0:0] tx_st_err; + wire [0:0] tx_st_valid; + wire tx_st_ready; + wire [C_PCI_DATA_WIDTH-1:0] tx_st_data; + wire [0:0] tx_st_empty; + + // ----------Clocks & Locks---------- + wire pld_clk; + wire coreclkout_hip; + wire refclk; + wire pld_core_ready; + wire reset_status; + wire serdes_pll_locked; + wire riffa_5_clk; + wire riffa_10_clk; + wire riffa_25_clk; + wire riffa_50_clk; + wire riffa_75_clk; + wire riffa_100_clk; + wire riffa_125_clk; + wire riffa_150_clk; + wire riffa_175_clk; + wire riffa_200_clk; + wire riffa_225_clk; + wire riffa_250_clk; + + // ----------Interrupt Interfaces---------- + wire app_msi_req; + wire app_msi_ack; + + // ----------Reconfiguration Controller signals---------- + wire mgmt_clk_clk; + wire mgmt_rst_reset; + + // ----------Reconfiguration Driver Signals---------- + wire reconfig_xcvr_clk; + wire reconfig_xcvr_rst; + + wire [7:0] rx_in; + wire [7:0] tx_out; + + // ------------Status Interface------------ + wire derr_cor_ext_rcv; + wire derr_cor_ext_rpl; + wire derr_rpl; + wire dlup; + wire dlup_exit; + wire ev128ns; + wire ev1us; + wire hotrst_exit; + wire [3:0] int_status; + wire l2_exit; + wire [3:0] lane_act; + wire [4:0] ltssmstate; + wire rx_par_err; + wire [1:0] tx_par_err; + wire cfg_par_err; + wire [7:0] ko_cpl_spc_header; + wire [11:0] ko_cpl_spc_data; + + // ----------Clocks---------- + assign pld_clk = coreclkout_hip; + assign mgmt_clk_clk = PCIE_REFCLK; + assign reconfig_xcvr_clk = PCIE_REFCLK; + assign refclk = PCIE_REFCLK; + assign pld_core_ready = serdes_pll_locked; + + // ----------Resets---------- + assign reconfig_xcvr_rst = 1'b0; + assign mgmt_rst_reset = 1'b0; + assign pin_perst = PCIE_RESET_N; + assign npor = PCIE_RESET_N; + + // ----------LED's---------- + assign LED[7:0] = 8'hff; + QSysDE5QGen1x8If64 + pcie_system_inst + ( + // Outputs + .rx_st_startofpacket (rx_st_sop[0:0]), + .rx_st_endofpacket (rx_st_eop[0:0]), + .rx_st_valid (rx_st_valid[0:0]), + .rx_st_data (rx_st_data[63:0]), + .tx_st_ready (tx_st_ready), + .pciehip_reset_status (reset_status), + .pciehip_serdes_pll_locked (serdes_pll_locked), + .pciecfg_tl_cfg_add (tl_cfg_add[3:0]), + .pciecfg_tl_cfg_ctl (tl_cfg_ctl[31:0]), + .pciecfg_tl_cfg_sts (tl_cfg_sts[52:0]), + .pciecoreclk_clk (coreclkout_hip), + .pcieserial_tx_out0 (PCIE_TX_OUT[0]), + .pcieserial_tx_out1 (PCIE_TX_OUT[1]), + .pcieserial_tx_out2 (PCIE_TX_OUT[2]), + .pcieserial_tx_out3 (PCIE_TX_OUT[3]), + .pcieserial_tx_out4 (PCIE_TX_OUT[4]), + .pcieserial_tx_out5 (PCIE_TX_OUT[5]), + .pcieserial_tx_out6 (PCIE_TX_OUT[6]), + .pcieserial_tx_out7 (PCIE_TX_OUT[7]), + .pciemsi_app_int_ack (app_int_ack), + .pciemsi_app_msi_ack (app_msi_ack), + .pciestat_derr_cor_ext_rcv (derr_cor_ext_rcv), + .pciestat_derr_cor_ext_rpl (derr_cor_ext_rpl), + .pciestat_derr_rpl (derr_rpl), + .pciestat_dlup (dlup), + .pciestat_dlup_exit (dlup_exit), + .pciestat_ev128ns (ev128ns), + .pciestat_ev1us (ev1us), + .pciestat_hotrst_exit (hotrst_exit), + .pciestat_int_status (int_status), + .pciestat_l2_exit (l2_exit), + .pciestat_lane_act (lane_act), + .pciestat_ltssmstate (ltssmstate), + .pciestat_rx_par_err (rx_par_err), + .pciestat_tx_par_err (tx_par_err), + .pciestat_cfg_par_err (cfg_par_err), + .pciestat_ko_cpl_spc_header (ko_cpl_spc_header), + .pciestat_ko_cpl_spc_data (ko_cpl_spc_data), + .riffa_5_clk (riffa_5_clk), + .riffa_10_clk (riffa_10_clk), + .riffa_25_clk (riffa_25_clk), + .riffa_50_clk (riffa_50_clk), + .riffa_75_clk (riffa_75_clk), + .riffa_100_clk (riffa_100_clk), + .riffa_125_clk (riffa_125_clk), + .riffa_150_clk (riffa_150_clk), + .riffa_175_clk (riffa_175_clk), + .riffa_200_clk (riffa_200_clk), + .riffa_225_clk (riffa_225_clk), + .riffa_250_clk (riffa_250_clk), + // Inputs + .rx_st_ready (rx_st_ready), + .tx_st_startofpacket (tx_st_sop[0:0]), + .tx_st_endofpacket (tx_st_eop[0:0]), + .tx_st_valid (tx_st_valid[0:0]), + .tx_st_data (tx_st_data[63:0]), + .pciehip_pld_core_ready (pld_core_ready), + .pcienpor_npor (npor), + .pcienpor_pin_perst (pin_perst), + .pcierefclk_clk (refclk), + .reconfigrefclk_clk (reconfig_xcvr_clk), + .pciepld_clk (pld_clk), + .reconfigrst_reset (reconfig_xcvr_rst), + .mgmtrst_reset (mgmt_rst_reset), + .mgmtclk_clk (mgmt_clk_clk), + .reconfigpldclk_clk (pld_clk), + .pcieserial_rx_in0 (PCIE_RX_IN[0]), + .pcieserial_rx_in1 (PCIE_RX_IN[1]), + .pcieserial_rx_in2 (PCIE_RX_IN[2]), + .pcieserial_rx_in3 (PCIE_RX_IN[3]), + .pcieserial_rx_in4 (PCIE_RX_IN[4]), + .pcieserial_rx_in5 (PCIE_RX_IN[5]), + .pcieserial_rx_in6 (PCIE_RX_IN[6]), + .pcieserial_rx_in7 (PCIE_RX_IN[7]), + .pciemsi_app_msi_req (app_msi_req), + .drvstat_derr_cor_ext_rcv (derr_cor_ext_rcv), + .drvstat_derr_cor_ext_rpl (derr_cor_ext_rpl), + .drvstat_derr_rpl (derr_rpl), + .drvstat_dlup (dlup), + .drvstat_dlup_exit (dlup_exit), + .drvstat_ev128ns (ev128ns), + .drvstat_ev1us (ev1us), + .drvstat_hotrst_exit (hotrst_exit), + .drvstat_int_status (int_status), + .drvstat_l2_exit (l2_exit), + .drvstat_lane_act (lane_act), + .drvstat_ltssmstate (ltssmstate), + .drvstat_rx_par_err (rx_par_err), + .drvstat_tx_par_err (tx_par_err), + .drvstat_cfg_par_err (cfg_par_err), + .drvstat_ko_cpl_spc_header (ko_cpl_spc_header), + .drvstat_ko_cpl_spc_data (ko_cpl_spc_data), + .pllrefclk_clk (OSC_BANK3D_50MHZ), + .pllrst_reset_n (1'b1)); + + // -------------------- END ALTERA IP INSTANTIATION -------------------- + // -------------------- BEGIN RIFFA INSTANTAION -------------------- + + // RIFFA channel interface + wire rst_out; + wire [C_NUM_CHNL-1:0] chnl_rx_clk; + wire [C_NUM_CHNL-1:0] chnl_rx; + wire [C_NUM_CHNL-1:0] chnl_rx_ack; + wire [C_NUM_CHNL-1:0] chnl_rx_last; + wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len; + wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off; + wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data; + wire [C_NUM_CHNL-1:0] chnl_rx_data_valid; + wire [C_NUM_CHNL-1:0] chnl_rx_data_ren; + + wire [C_NUM_CHNL-1:0] chnl_tx_clk; + wire [C_NUM_CHNL-1:0] chnl_tx; + wire [C_NUM_CHNL-1:0] chnl_tx_ack; + wire [C_NUM_CHNL-1:0] chnl_tx_last; + wire [(C_NUM_CHNL*32)-1:0] chnl_tx_len; + wire [(C_NUM_CHNL*31)-1:0] chnl_tx_off; + wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data; + wire [C_NUM_CHNL-1:0] chnl_tx_data_valid; + wire [C_NUM_CHNL-1:0] chnl_tx_data_ren; + + wire chnl_reset; + wire chnl_clk; + wire riffa_reset; + wire riffa_clk; + assign riffa_reset = reset_status; + assign riffa_clk = pld_clk; + assign chnl_clk = pld_clk; + assign chnl_reset = rst_out; + + riffa_wrapper_de5 + #(/*AUTOINSTPARAM*/ + // Parameters + .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), + .C_NUM_CHNL (C_NUM_CHNL), + .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), + .C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES)) + riffa + ( + // Outputs + .RX_ST_READY (rx_st_ready), + .TX_ST_DATA (tx_st_data[C_PCI_DATA_WIDTH-1:0]), + .TX_ST_VALID (tx_st_valid[0:0]), + .TX_ST_EOP (tx_st_eop[0:0]), + .TX_ST_SOP (tx_st_sop[0:0]), + .TX_ST_EMPTY (tx_st_empty[0:0]), + .APP_MSI_REQ (app_msi_req), + .RST_OUT (rst_out), + .CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]), + .CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]), + .CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), + .CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), + .CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), + .CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]), + .CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]), + .CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]), + // Inputs + .RX_ST_DATA (rx_st_data[C_PCI_DATA_WIDTH-1:0]), + .RX_ST_EOP (rx_st_eop[0:0]), + .RX_ST_SOP (rx_st_sop[0:0]), + .RX_ST_VALID (rx_st_valid[0:0]), + .RX_ST_EMPTY (rx_st_empty[0:0]), + .TX_ST_READY (tx_st_ready), + .TL_CFG_CTL (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]), + .TL_CFG_ADD (tl_cfg_add[`SIG_CFG_ADD_W-1:0]), + .TL_CFG_STS (tl_cfg_sts[`SIG_CFG_STS_W-1:0]), + .KO_CPL_SPC_HEADER (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]), + .KO_CPL_SPC_DATA (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]), + .APP_MSI_ACK (app_msi_ack), + .PLD_CLK (pld_clk), + .RESET_STATUS (reset_status), + .CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]), + .CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]), + .CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]), + .CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]), + .CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]), + .CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]), + .CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), + .CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), + .CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), + .CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])); + + // -------------------- END RIFFA INSTANTAION -------------------- + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_5mhz + (.CLK(riffa_5_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[0]), + .CHNL_RX(chnl_rx[0]), + .CHNL_RX_ACK(chnl_rx_ack[0]), + .CHNL_RX_LAST(chnl_rx_last[0]), + .CHNL_RX_LEN(chnl_rx_len[32*0 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*0 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[0]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[0]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[0]), + .CHNL_TX(chnl_tx[0]), + .CHNL_TX_ACK(chnl_tx_ack[0]), + .CHNL_TX_LAST(chnl_tx_last[0]), + .CHNL_TX_LEN(chnl_tx_len[32*0 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*0 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[0]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[0])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_10mhz + (.CLK(riffa_10_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[1]), + .CHNL_RX(chnl_rx[1]), + .CHNL_RX_ACK(chnl_rx_ack[1]), + .CHNL_RX_LAST(chnl_rx_last[1]), + .CHNL_RX_LEN(chnl_rx_len[32*1 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*1 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[1]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[1]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[1]), + .CHNL_TX(chnl_tx[1]), + .CHNL_TX_ACK(chnl_tx_ack[1]), + .CHNL_TX_LAST(chnl_tx_last[1]), + .CHNL_TX_LEN(chnl_tx_len[32*1 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*1 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[1]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[1])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_25mhz + (.CLK(riffa_25_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[2]), + .CHNL_RX(chnl_rx[2]), + .CHNL_RX_ACK(chnl_rx_ack[2]), + .CHNL_RX_LAST(chnl_rx_last[2]), + .CHNL_RX_LEN(chnl_rx_len[32*2 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*2 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[2]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[2]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[2]), + .CHNL_TX(chnl_tx[2]), + .CHNL_TX_ACK(chnl_tx_ack[2]), + .CHNL_TX_LAST(chnl_tx_last[2]), + .CHNL_TX_LEN(chnl_tx_len[32*2 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*2 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[2]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[2])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_50mhz + (.CLK(riffa_50_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[3]), + .CHNL_RX(chnl_rx[3]), + .CHNL_RX_ACK(chnl_rx_ack[3]), + .CHNL_RX_LAST(chnl_rx_last[3]), + .CHNL_RX_LEN(chnl_rx_len[32*3 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*3 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[3]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[3]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[3]), + .CHNL_TX(chnl_tx[3]), + .CHNL_TX_ACK(chnl_tx_ack[3]), + .CHNL_TX_LAST(chnl_tx_last[3]), + .CHNL_TX_LEN(chnl_tx_len[32*3 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*3 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[3]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[3])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_75mhz + (.CLK(riffa_75_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[4]), + .CHNL_RX(chnl_rx[4]), + .CHNL_RX_ACK(chnl_rx_ack[4]), + .CHNL_RX_LAST(chnl_rx_last[4]), + .CHNL_RX_LEN(chnl_rx_len[32*4 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*4 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[4]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[4]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[4]), + .CHNL_TX(chnl_tx[4]), + .CHNL_TX_ACK(chnl_tx_ack[4]), + .CHNL_TX_LAST(chnl_tx_last[4]), + .CHNL_TX_LEN(chnl_tx_len[32*4 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*4 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[4]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[4])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_100mhz + (.CLK(riffa_100_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[5]), + .CHNL_RX(chnl_rx[5]), + .CHNL_RX_ACK(chnl_rx_ack[5]), + .CHNL_RX_LAST(chnl_rx_last[5]), + .CHNL_RX_LEN(chnl_rx_len[32*5 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*5 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[5]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[5]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[5]), + .CHNL_TX(chnl_tx[5]), + .CHNL_TX_ACK(chnl_tx_ack[5]), + .CHNL_TX_LAST(chnl_tx_last[5]), + .CHNL_TX_LEN(chnl_tx_len[32*5 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*5 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[5]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[5])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_125mhz + (.CLK(riffa_125_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[6]), + .CHNL_RX(chnl_rx[6]), + .CHNL_RX_ACK(chnl_rx_ack[6]), + .CHNL_RX_LAST(chnl_rx_last[6]), + .CHNL_RX_LEN(chnl_rx_len[32*6 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*6 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[6]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[6]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[6]), + .CHNL_TX(chnl_tx[6]), + .CHNL_TX_ACK(chnl_tx_ack[6]), + .CHNL_TX_LAST(chnl_tx_last[6]), + .CHNL_TX_LEN(chnl_tx_len[32*6 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*6 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[6]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[6])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_150mhz + (.CLK(riffa_150_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[7]), + .CHNL_RX(chnl_rx[7]), + .CHNL_RX_ACK(chnl_rx_ack[7]), + .CHNL_RX_LAST(chnl_rx_last[7]), + .CHNL_RX_LEN(chnl_rx_len[32*7 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*7 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[7]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[7]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[7]), + .CHNL_TX(chnl_tx[7]), + .CHNL_TX_ACK(chnl_tx_ack[7]), + .CHNL_TX_LAST(chnl_tx_last[7]), + .CHNL_TX_LEN(chnl_tx_len[32*7 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*7 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[7]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[7])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_175mhz + (.CLK(riffa_175_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[8]), + .CHNL_RX(chnl_rx[8]), + .CHNL_RX_ACK(chnl_rx_ack[8]), + .CHNL_RX_LAST(chnl_rx_last[8]), + .CHNL_RX_LEN(chnl_rx_len[32*8 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*8 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[8]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[8]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[8]), + .CHNL_TX(chnl_tx[8]), + .CHNL_TX_ACK(chnl_tx_ack[8]), + .CHNL_TX_LAST(chnl_tx_last[8]), + .CHNL_TX_LEN(chnl_tx_len[32*8 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*8 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[8]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[8])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_200mhz + (.CLK(riffa_200_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[9]), + .CHNL_RX(chnl_rx[9]), + .CHNL_RX_ACK(chnl_rx_ack[9]), + .CHNL_RX_LAST(chnl_rx_last[9]), + .CHNL_RX_LEN(chnl_rx_len[32*9 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*9 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[9]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[9]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[9]), + .CHNL_TX(chnl_tx[9]), + .CHNL_TX_ACK(chnl_tx_ack[9]), + .CHNL_TX_LAST(chnl_tx_last[9]), + .CHNL_TX_LEN(chnl_tx_len[32*9 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*9 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[9]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[9])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_225mhz + (.CLK(riffa_225_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[10]), + .CHNL_RX(chnl_rx[10]), + .CHNL_RX_ACK(chnl_rx_ack[10]), + .CHNL_RX_LAST(chnl_rx_last[10]), + .CHNL_RX_LEN(chnl_rx_len[32*10 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*10 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[10]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[10]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[10]), + .CHNL_TX(chnl_tx[10]), + .CHNL_TX_ACK(chnl_tx_ack[10]), + .CHNL_TX_LAST(chnl_tx_last[10]), + .CHNL_TX_LEN(chnl_tx_len[32*10 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*10 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[10]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[10])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_250mhz + (.CLK(riffa_250_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[11]), + .CHNL_RX(chnl_rx[11]), + .CHNL_RX_ACK(chnl_rx_ack[11]), + .CHNL_RX_LAST(chnl_rx_last[11]), + .CHNL_RX_LEN(chnl_rx_len[32*11 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*11 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[11]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[11]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[11]), + .CHNL_TX(chnl_tx[11]), + .CHNL_TX_ACK(chnl_tx_ack[11]), + .CHNL_TX_LAST(chnl_tx_last[11]), + .CHNL_TX_LEN(chnl_tx_len[32*11 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*11 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[11]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[11])); + +endmodule diff --git a/fpga/altera/de5/DE5QGen1x8If64_CLK/ip/QSysDE5QGen1x8If64.qsys b/fpga/altera/de5/DE5QGen1x8If64_CLK/ip/QSysDE5QGen1x8If64.qsys new file mode 100644 index 0000000..4004126 --- /dev/null +++ b/fpga/altera/de5/DE5QGen1x8If64_CLK/ip/QSysDE5QGen1x8If64.qsys @@ -0,0 +1,883 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + g3_coeff_10_nxtber_less + + g3_coeff_10_nxtber_more + + + + + + + g3_coeff_11_nxtber_less + + g3_coeff_11_nxtber_more + + + + + + + g3_coeff_12_nxtber_less + + g3_coeff_12_nxtber_more + + + + + + + g3_coeff_13_nxtber_less + + g3_coeff_13_nxtber_more + + + + + + + g3_coeff_14_nxtber_less + + g3_coeff_14_nxtber_more + + + + + + + g3_coeff_15_nxtber_less + + g3_coeff_15_nxtber_more + + + + + + + g3_coeff_16_nxtber_less + + g3_coeff_16_nxtber_more + + + + + + + g3_coeff_17_nxtber_less + + g3_coeff_17_nxtber_more + + + + + + + g3_coeff_18_nxtber_less + + g3_coeff_18_nxtber_more + + + + + + + g3_coeff_19_nxtber_less + + g3_coeff_19_nxtber_more + + + + + + + g3_coeff_1_nxtber_less + + g3_coeff_1_nxtber_more + + + + + + + g3_coeff_20_nxtber_less + + g3_coeff_20_nxtber_more + + + + + + + g3_coeff_21_nxtber_less + + g3_coeff_21_nxtber_more + + + + + + + g3_coeff_22_nxtber_less + + g3_coeff_22_nxtber_more + + + + + + + g3_coeff_23_nxtber_less + + g3_coeff_23_nxtber_more + + + + + + + g3_coeff_24_nxtber_less + + g3_coeff_24_nxtber_more + + + + + + + g3_coeff_2_nxtber_less + + g3_coeff_2_nxtber_more + + + + + + + g3_coeff_3_nxtber_less + + g3_coeff_3_nxtber_more + + + + + + + g3_coeff_4_nxtber_less + + g3_coeff_4_nxtber_more + + + + + + + g3_coeff_5_nxtber_less + + g3_coeff_5_nxtber_more + + + + + + + g3_coeff_6_nxtber_less + + g3_coeff_6_nxtber_more + + + + + + + g3_coeff_7_nxtber_less + + g3_coeff_7_nxtber_more + + + + + + + g3_coeff_8_nxtber_less + + g3_coeff_8_nxtber_more + + + + + + + g3_coeff_9_nxtber_less + + g3_coeff_9_nxtber_more + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Create an adjpllin signal to connect with an upstream PLL + + + + + + + + + + + + + + + + + + + + + + + + Automatic Switchover + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/altera/de5/DE5QGen1x8If64_CLK/prj/DE5QGen1x8If64.qpf b/fpga/altera/de5/DE5QGen1x8If64_CLK/prj/DE5QGen1x8If64.qpf new file mode 100644 index 0000000..315115b --- /dev/null +++ b/fpga/altera/de5/DE5QGen1x8If64_CLK/prj/DE5QGen1x8If64.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Full Version +# Date created = 16:27:01 June 09, 2014 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "16:27:01 June 09, 2014" + +# Revisions + +PROJECT_REVISION = "DE5QGen1x8If64" diff --git a/fpga/altera/de5/DE5QGen1x8If64_CLK/prj/DE5QGen1x8If64.qsf b/fpga/altera/de5/DE5QGen1x8If64_CLK/prj/DE5QGen1x8If64.qsf new file mode 100644 index 0000000..c344760 --- /dev/null +++ b/fpga/altera/de5/DE5QGen1x8If64_CLK/prj/DE5QGen1x8If64.qsf @@ -0,0 +1,469 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Full Version +# Date created = 11:03:06 March 21, 2014 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# DE5QGen1x8If64_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Stratix V" +set_global_assignment -name DEVICE 5SGXEA7N2F45C2 +set_global_assignment -name TOP_LEVEL_ENTITY DE5QGen1x8If64 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06 MARCH 21, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/ +################################################################################ +# Timing SDC Files +################################################################################ + +################################################################################ +# PCIE Connections +################################################################################ +# PCIe clk (100 MHz) +set_location_assignment PIN_AK38 -to PCIE_REFCLK +set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK + +set_location_assignment PIN_AK39 -to "PCIE_REFCLK(n)" +set_instance_assignment -name IO_STANDARD HCSL -to "PCIE_REFCLK(n)" + +set_location_assignment PIN_AU33 -to PCIE_RESET_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_RESET_N + +################################################################################ +#PCIE Pins +################################################################################ +# Settings from SV PCIE User Guide (AV-ST) +# 100 Ohm Termination +# 1.5V PCML +# XCVR_VCCR_VCCT_VOLTAGE 0_9V (GEN 1/2 CMU) +# XCVR_VCCA_VOLTAGE 2_5V (GEN 1/2 CMU) +# We use CMU PLL's (http://www.altera.com/literature/hb/stratix-v/stx5_52003.pdf) + +################################################################################ +#PCIE RX_IN 0 +################################################################################ + +set_location_assignment PIN_BB43 -to PCIE_RX_IN[0] +set_location_assignment PIN_BB44 -to "PCIE_RX_IN[0](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[0] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[0] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[0] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[0](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[0](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[0](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[0](n)" + +################################################################################ +#PCIE RX_IN 1 +################################################################################ + +set_location_assignment PIN_BA41 -to PCIE_RX_IN[1] +set_location_assignment PIN_BA42 -to "PCIE_RX_IN[1](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[1] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[1] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[1] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[1](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[1](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[1](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[1](n)" + +################################################################################ +#PCIE RX_IN 2 +################################################################################ + +set_location_assignment PIN_AW41 -to PCIE_RX_IN[2] +set_location_assignment PIN_AW42 -to "PCIE_RX_IN[2](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[2] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[2] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[2] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[2](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[2](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[2](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[2](n)" + +################################################################################ +#PCIE RX_IN 3 +################################################################################ + +set_location_assignment PIN_AY43 -to PCIE_RX_IN[3] +set_location_assignment PIN_AY44 -to "PCIE_RX_IN[3](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[3] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[3] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[3] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[3](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[3](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[3](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[3](n)" + +################################################################################ +#PCIE RX_IN 4 +################################################################################ + +set_location_assignment PIN_AT43 -to PCIE_RX_IN[4] +set_location_assignment PIN_AT44 -to "PCIE_RX_IN[4](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[4] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[4] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[4] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[4] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[4](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[4](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[4](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[4](n)" + +################################################################################ +#PCIE RX_IN 5 +################################################################################ + +set_location_assignment PIN_AP43 -to PCIE_RX_IN[5] +set_location_assignment PIN_AP44 -to "PCIE_RX_IN[5](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[5] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[5] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[5] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[5] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[5](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[5](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[5](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[5](n)" + +################################################################################ +#PCIE RX_IN 6 +################################################################################ + +set_location_assignment PIN_AM43 -to PCIE_RX_IN[6] +set_location_assignment PIN_AM44 -to "PCIE_RX_IN[6](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[6] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[6] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[6] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[6] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[6](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[6](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[6](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[6](n)" + +################################################################################ +#PCIE RX_IN 7 +################################################################################ + +set_location_assignment PIN_AK43 -to PCIE_RX_IN[7] +set_location_assignment PIN_AK44 -to "PCIE_RX_IN[7](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[7] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[7] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[7] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[7] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[7](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[7](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[7](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[7](n)" + +################################################################################ +#PCIE TX_OUT 0 +################################################################################ +set_location_assignment PIN_AY39 -to PCIE_TX_OUT[0] +set_location_assignment PIN_AY40 -to "PCIE_TX_OUT[0](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[0] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[0] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[0] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[0](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[0](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[0](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[0](n)" + +################################################################################ +#PCIE TX_OUT 1 +################################################################################ +set_location_assignment PIN_AV39 -to PCIE_TX_OUT[1] +set_location_assignment PIN_AV40 -to "PCIE_TX_OUT[1](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[1] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[1] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[1] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[1](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[1](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[1](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[1](n)" + +################################################################################ +#PCIE TX_OUT 2 +################################################################################ +set_location_assignment PIN_AT39 -to PCIE_TX_OUT[2] +set_location_assignment PIN_AT40 -to "PCIE_TX_OUT[2](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[2] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[2] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[2] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[2](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[2](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[2](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[2](n)" + +################################################################################ +#PCIE TX_OUT 3 +################################################################################ +set_location_assignment PIN_AU41 -to PCIE_TX_OUT[3] +set_location_assignment PIN_AU42 -to "PCIE_TX_OUT[3](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[3] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[3] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[3] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[3](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[3](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[3](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[3](n)" + +################################################################################ +#PCIE TX_OUT 4 +################################################################################ +set_location_assignment PIN_AN41 -to PCIE_TX_OUT[4] +set_location_assignment PIN_AN42 -to "PCIE_TX_OUT[4](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[4] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[4] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[4] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[4] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[4](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[4](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[4](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[4](n)" + +################################################################################ +#PCIE TX_OUT 5 +################################################################################ +set_location_assignment PIN_AL41 -to PCIE_TX_OUT[5] +set_location_assignment PIN_AL42 -to "PCIE_TX_OUT[5](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[5] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[5] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[5] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[5] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[5](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[5](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[5](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[5](n)" + +################################################################################ +#PCIE TX_OUT 6 +################################################################################ +set_location_assignment PIN_AJ41 -to PCIE_TX_OUT[6] +set_location_assignment PIN_AJ42 -to "PCIE_TX_OUT[6](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[6] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[6] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[6] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[6] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[6](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[6](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[6](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[6](n)" + +################################################################################ +#PCIE TX_OUT 7 +################################################################################ + +set_location_assignment PIN_AG41 -to PCIE_TX_OUT[7] +set_location_assignment PIN_AG42 -to "PCIE_TX_OUT[7](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[7] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[7] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[7] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[7] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[7](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[7](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[7](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[7](n)" + +################################################################################ +# LED's +################################################################################ +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7] + +set_location_assignment PIN_AW37 -to LED[0] +set_location_assignment PIN_AV37 -to LED[1] +set_location_assignment PIN_BB36 -to LED[2] +set_location_assignment PIN_BB39 -to LED[3] +set_location_assignment PIN_AH15 -to LED[4] +set_location_assignment PIN_AH13 -to LED[5] +set_location_assignment PIN_AJ13 -to LED[6] +set_location_assignment PIN_AJ14 -to LED[7] + +################################################################################ +# OSCILLATORS +################################################################################ + +set_location_assignment PIN_BC28 -to OSC_BANK3D_50MHZ +set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_BANK3D_50MHZ + +################################################################################ +# End Custom Instantiations +################################################################################ + +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF + +set_global_assignment -name SEARCH_PATH ../../../../riffa_hdl +set_global_assignment -name SDC_FILE ../constr/DE5QGen1x8If64.sdc +set_global_assignment -name QSYS_FILE ../ip/QSysDE5QGen1x8If64.qsys +set_global_assignment -name VERILOG_FILE ../hdl/DE5QGen1x8If64.v +set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_extender.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_controller.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ohtb.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/fpga/altera/de5/DE5QGen2x8If128_CLK/Makefile b/fpga/altera/de5/DE5QGen2x8If128_CLK/Makefile new file mode 100644 index 0000000..ef4dbc6 --- /dev/null +++ b/fpga/altera/de5/DE5QGen2x8If128_CLK/Makefile @@ -0,0 +1,63 @@ +# ---------------------------------------------------------------------- +# Copyright (c) 2016, The Regents of the University of California All +# rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# +# * Neither the name of The Regents of the University of California +# nor the names of its contributors may be used to endorse or +# promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE +# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +# DAMAGE. +# ---------------------------------------------------------------------- +#----------------------------------------------------------------------- +# Filename: Makefile +# Version: 1.0 +# Description: Project-level makefile for building an example project +# Author: Dustin Richmond (@darichmond) +#----------------------------------------------------------------------- +# This make file expects the following variables to be set: +# RIFFA_HDL_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory. +# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to +# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory +WIDTH=128 +TYPE=classic +CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))) +PROJECT=$(shell basename $(CURRENT_PATH)) + +ifndef RIFFA_HDL_PATH + RIFFA_HDL_PATH:=../../../riffa_hdl +endif +ifndef BOARD_PATH + BOARD_PATH:=.. +endif +ifndef JOBS + JOBS=1 +endif +include $(RIFFA_HDL_PATH)/riffa.mk +include $(BOARD_PATH)/board.mk + +PROJECT_IP+=ip/QSysDE5QGen2x8If128.qsys +RELEASE_IP+=ip/QSysDE5QGen2x8If128.qsys diff --git a/fpga/altera/de5/DE5QGen2x8If128_CLK/bit/DE5QGen2x8If128.sof b/fpga/altera/de5/DE5QGen2x8If128_CLK/bit/DE5QGen2x8If128.sof new file mode 100644 index 0000000..a8e4aab Binary files /dev/null and b/fpga/altera/de5/DE5QGen2x8If128_CLK/bit/DE5QGen2x8If128.sof differ diff --git a/fpga/altera/de5/DE5QGen2x8If128_CLK/constr/DE5QGen2x8If128.sdc b/fpga/altera/de5/DE5QGen2x8If128_CLK/constr/DE5QGen2x8If128.sdc new file mode 100644 index 0000000..11e1562 --- /dev/null +++ b/fpga/altera/de5/DE5QGen2x8If128_CLK/constr/DE5QGen2x8If128.sdc @@ -0,0 +1,110 @@ +# ---------------------------------------------------------------------- +# Copyright (c) 2016, The Regents of the University of California All +# rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# +# * Neither the name of The Regents of the University of California +# nor the names of its contributors may be used to endorse or +# promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE +# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +# DAMAGE. +# ---------------------------------------------------------------------- +#---------------------------------------------------------------------------- +# Filename: DE5QGen2x8If128.sdc (Qsys) +# Version: 1.00.a +# Verilog Standard: Verilog-2001 +# Description: Synopsys Design Constraints for the DE5 board. +# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input +# Author: Dustin Richmond (@darichmond) +#----------------------------------------------------------------------------- +create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}] +create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}] +create_clock -name riffa_5_clk -period 200 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_10_clk -period 100 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_25_clk -period 40 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_50_clk -period 20 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_75_clk -period 13.3 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_100_clk -period 10 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_125_clk -period 8 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_150_clk -period 6.66 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_175_clk -period 6 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[8].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_200_clk -period 5.33 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[9].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_225_clk -period 4.66 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[10].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name riffa_250_clk -period 4 [get_pins {pcie_system_inst|pll_0|altera_pll_i|general[11].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_clock -name user_clk -period 4 [get_pins {pcie_system_inst|pciegen2x8if128|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout}] +set_clock_groups -asynchronous -group {user_clk} -group {riffa_5_clk} -group {riffa_10_clk} -group {riffa_25_clk} -group {riffa_50_clk} -group {riffa_75_clk} -group {riffa_100_clk} -group {riffa_125_clk} -group {riffa_150_clk} -group {riffa_175_clk} -group {riffa_200_clk} -group {riffa_225_clk} -group {riffa_250_clk} + +################################################################################ +# 13.1 Workround for http://www.altera.com/support/kdb/solutions/rd12162013_581.html?GSA_pos=1&WT.oss_r=1&WT.oss=adce_off_r +################################################################################ + +set_false_path -to [get_registers *|*.adce_off_r[0]] +set_false_path -to [get_registers *|*.adce_on_rr[0]] +set_false_path -to [get_registers *|reset_sync_pldclk_r[*]] + +################################################################################ +# End Workround +################################################################################ + +derive_pll_clocks -create_base_clocks +derive_clock_uncertainty + +################################################################################ +# Imports from Example Design (altera/13.1/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/) +################################################################################ + +###################################################################### +# HIP Soft reset controller SDC constraints +set_false_path -to [get_registers *altpcie_rs_serdes|fifo_err_sync_r[0]] +set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*] + +# HIP testin pins SDC constraints +set_false_path -from [get_pins -compatibility_mode *hip_ctrl*] + +###################################################################### +# Constraints for CV SIG asynchonous logic +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}] + + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|test_out[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqout[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqber[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_lf[*]}] + +set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_fs[*]}] \ No newline at end of file diff --git a/fpga/altera/de5/DE5QGen2x8If128_CLK/hdl/DE5QGen2x8If128.v b/fpga/altera/de5/DE5QGen2x8If128_CLK/hdl/DE5QGen2x8If128.v new file mode 100644 index 0000000..bf32f0b --- /dev/null +++ b/fpga/altera/de5/DE5QGen2x8If128_CLK/hdl/DE5QGen2x8If128.v @@ -0,0 +1,666 @@ +// ---------------------------------------------------------------------- +// Copyright (c) 2016, The Regents of the University of California All +// rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above +// copyright notice, this list of conditions and the following +// disclaimer in the documentation and/or other materials provided +// with the distribution. +// +// * Neither the name of The Regents of the University of California +// nor the names of its contributors may be used to endorse or +// promote products derived from this software without specific +// prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE +// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +// DAMAGE. +// ---------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// Filename: DE5QGen2x8If128.v +// Version: +// Verilog Standard: Verilog-2001 +// Description: Top level module for RIFFA 2.2 reference design for the +// the Altera Stratix V Avalong Streaming Interface to PCI +// Express module and the Terasic DE5 Development Board. +// Author: Dustin Richmond (@darichmond) +//----------------------------------------------------------------------------- +`include "functions.vh" +`include "riffa.vh" +`include "altera.vh" +`timescale 1ps / 1ps +module DE5QGen2x8If128 + #(// Number of RIFFA Channels + parameter C_NUM_CHNL = 12, + // Number of PCIe Lanes + parameter C_NUM_LANES = 8, + // Settings from Quartus IP Library + parameter C_PCI_DATA_WIDTH = 128, + parameter C_MAX_PAYLOAD_BYTES = 256, + parameter C_LOG_NUM_TAGS = 5 + ) + ( + // ----------LEDs---------- + output [7:0] LED, + + // ----------PCIE---------- + input PCIE_RESET_N, + input PCIE_REFCLK, + + // ----------PCIE Serial RX---------- + input [C_NUM_LANES-1:0] PCIE_RX_IN, + + // ----------PCIE Serial TX---------- + output [C_NUM_LANES-1:0] PCIE_TX_OUT, + + // ----------Oscillators---------- + input OSC_BANK3D_50MHZ + ); + + wire npor; + wire pin_perst; + + // ----------TL Config interface---------- + wire [3:0] tl_cfg_add; + wire [31:0] tl_cfg_ctl; + wire [52:0] tl_cfg_sts; + + // ----------Rx/TX Interfaces---------- + wire [0:0] rx_st_sop; + wire [0:0] rx_st_eop; + wire [0:0] rx_st_err; + wire [0:0] rx_st_valid; + wire [0:0] rx_st_empty; + wire rx_st_ready; + wire [C_PCI_DATA_WIDTH-1:0] rx_st_data; + + wire [0:0] tx_st_sop; + wire [0:0] tx_st_eop; + wire [0:0] tx_st_err; + wire [0:0] tx_st_valid; + wire tx_st_ready; + wire [C_PCI_DATA_WIDTH-1:0] tx_st_data; + wire [0:0] tx_st_empty; + + // ----------Clocks & Locks---------- + wire pld_clk; + wire coreclkout_hip; + wire refclk; + wire pld_core_ready; + wire reset_status; + wire serdes_pll_locked; + wire riffa_5_clk; + wire riffa_10_clk; + wire riffa_25_clk; + wire riffa_50_clk; + wire riffa_75_clk; + wire riffa_100_clk; + wire riffa_125_clk; + wire riffa_150_clk; + wire riffa_175_clk; + wire riffa_200_clk; + wire riffa_225_clk; + wire riffa_250_clk; + + // ----------Interrupt Interfaces---------- + wire app_msi_req; + wire app_msi_ack; + + // ----------Reconfiguration Controller signals---------- + wire mgmt_clk_clk; + wire mgmt_rst_reset; + + // ----------Reconfiguration Driver Signals---------- + wire reconfig_xcvr_clk; + wire reconfig_xcvr_rst; + + wire [7:0] rx_in; + wire [7:0] tx_out; + + // ------------Status Interface------------ + wire derr_cor_ext_rcv; + wire derr_cor_ext_rpl; + wire derr_rpl; + wire dlup; + wire dlup_exit; + wire ev128ns; + wire ev1us; + wire hotrst_exit; + wire [3:0] int_status; + wire l2_exit; + wire [3:0] lane_act; + wire [4:0] ltssmstate; + wire rx_par_err; + wire [1:0] tx_par_err; + wire cfg_par_err; + wire [7:0] ko_cpl_spc_header; + wire [11:0] ko_cpl_spc_data; + + // ----------Clocks---------- + assign pld_clk = coreclkout_hip; + assign mgmt_clk_clk = PCIE_REFCLK; + assign reconfig_xcvr_clk = PCIE_REFCLK; + assign refclk = PCIE_REFCLK; + assign pld_core_ready = serdes_pll_locked; + + // ----------Resets---------- + assign reconfig_xcvr_rst = 1'b0; + assign mgmt_rst_reset = 1'b0; + assign pin_perst = PCIE_RESET_N; + assign npor = PCIE_RESET_N; + + // ----------LED's---------- + assign LED[7:0] = 8'hff; + + // -------------------- BEGIN ALTERA IP INSTANTIATION --------------------// + QSysDE5QGen2x8If128 + pcie_system_inst + ( + // Outputs + .rx_st_startofpacket (rx_st_sop[0:0]), + .rx_st_endofpacket (rx_st_eop[0:0]), + .rx_st_valid (rx_st_valid[0:0]), + .rx_st_empty (rx_st_empty[0:0]), + .rx_st_data (rx_st_data[127:0]), + .tx_st_ready (tx_st_ready), + .pciehip_reset_status (reset_status), + .pciehip_serdes_pll_locked (serdes_pll_locked), + .pciecfg_tl_cfg_add (tl_cfg_add[3:0]), + .pciecfg_tl_cfg_ctl (tl_cfg_ctl[31:0]), + .pciecfg_tl_cfg_sts (tl_cfg_sts[52:0]), + .pciecoreclk_clk (coreclkout_hip), + .pcieserial_tx_out0 (PCIE_TX_OUT[0]), + .pcieserial_tx_out1 (PCIE_TX_OUT[1]), + .pcieserial_tx_out2 (PCIE_TX_OUT[2]), + .pcieserial_tx_out3 (PCIE_TX_OUT[3]), + .pcieserial_tx_out4 (PCIE_TX_OUT[4]), + .pcieserial_tx_out5 (PCIE_TX_OUT[5]), + .pcieserial_tx_out6 (PCIE_TX_OUT[6]), + .pcieserial_tx_out7 (PCIE_TX_OUT[7]), + .pciemsi_app_msi_ack (app_msi_ack), + .pciestat_derr_cor_ext_rcv (derr_cor_ext_rcv), + .pciestat_derr_cor_ext_rpl (derr_cor_ext_rpl), + .pciestat_derr_rpl (derr_rpl), + .pciestat_dlup (dlup), + .pciestat_dlup_exit (dlup_exit), + .pciestat_ev128ns (ev128ns), + .pciestat_ev1us (ev1us), + .pciestat_hotrst_exit (hotrst_exit), + .pciestat_int_status (int_status), + .pciestat_l2_exit (l2_exit), + .pciestat_lane_act (lane_act), + .pciestat_ltssmstate (ltssmstate), + .pciestat_rx_par_err (rx_par_err), + .pciestat_tx_par_err (tx_par_err), + .pciestat_cfg_par_err (cfg_par_err), + .pciestat_ko_cpl_spc_header (ko_cpl_spc_header), + .pciestat_ko_cpl_spc_data (ko_cpl_spc_data), + .riffa_5_clk (riffa_5_clk), + .riffa_10_clk (riffa_10_clk), + .riffa_25_clk (riffa_25_clk), + .riffa_50_clk (riffa_50_clk), + .riffa_75_clk (riffa_75_clk), + .riffa_100_clk (riffa_100_clk), + .riffa_125_clk (riffa_125_clk), + .riffa_150_clk (riffa_150_clk), + .riffa_175_clk (riffa_175_clk), + .riffa_200_clk (riffa_200_clk), + .riffa_225_clk (riffa_225_clk), + .riffa_250_clk (riffa_250_clk), + // Inputs + .rx_st_ready (rx_st_ready), + .tx_st_startofpacket (tx_st_sop[0:0]), + .tx_st_endofpacket (tx_st_eop[0:0]), + .tx_st_valid (tx_st_valid[0:0]), + .tx_st_empty (tx_st_empty[0:0]), + .tx_st_data (tx_st_data[127:0]), + .pciehip_pld_core_ready (pld_core_ready), + .pcienpor_npor (npor), + .pcienpor_pin_perst (pin_perst), + .pcierefclk_clk (refclk), + .reconfigrefclk_clk (reconfig_xcvr_clk), + .pciepld_clk (pld_clk), + .reconfigrst_reset (reconfig_xcvr_rst), + .mgmtrst_reset (mgmt_rst_reset), + .mgmtclk_clk (mgmt_clk_clk), + .reconfigpldclk_clk (pld_clk), + .pcieserial_rx_in0 (PCIE_RX_IN[0]), + .pcieserial_rx_in1 (PCIE_RX_IN[1]), + .pcieserial_rx_in2 (PCIE_RX_IN[2]), + .pcieserial_rx_in3 (PCIE_RX_IN[3]), + .pcieserial_rx_in4 (PCIE_RX_IN[4]), + .pcieserial_rx_in5 (PCIE_RX_IN[5]), + .pcieserial_rx_in6 (PCIE_RX_IN[6]), + .pcieserial_rx_in7 (PCIE_RX_IN[7]), + .pciemsi_app_msi_req (app_msi_req), + .drvstat_derr_cor_ext_rcv (derr_cor_ext_rcv), + .drvstat_derr_cor_ext_rpl (derr_cor_ext_rpl), + .drvstat_derr_rpl (derr_rpl), + .drvstat_dlup (dlup), + .drvstat_dlup_exit (dlup_exit), + .drvstat_ev128ns (ev128ns), + .drvstat_ev1us (ev1us), + .drvstat_hotrst_exit (hotrst_exit), + .drvstat_int_status (int_status), + .drvstat_l2_exit (l2_exit), + .drvstat_lane_act (lane_act), + .drvstat_ltssmstate (ltssmstate), + .drvstat_rx_par_err (rx_par_err), + .drvstat_tx_par_err (tx_par_err), + .drvstat_cfg_par_err (cfg_par_err), + .drvstat_ko_cpl_spc_header (ko_cpl_spc_header), + .drvstat_ko_cpl_spc_data (ko_cpl_spc_data), + .pllrefclk_clk (OSC_BANK3D_50MHZ), + .pllrst_reset_n (1'b1)); + + // -------------------- END ALTERA IP INSTANTIATION -------------------- + // -------------------- BEGIN RIFFA INSTANTAION -------------------- + + // RIFFA channel interface + wire rst_out; + wire [C_NUM_CHNL-1:0] chnl_rx_clk; + wire [C_NUM_CHNL-1:0] chnl_rx; + wire [C_NUM_CHNL-1:0] chnl_rx_ack; + wire [C_NUM_CHNL-1:0] chnl_rx_last; + wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len; + wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off; + wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data; + wire [C_NUM_CHNL-1:0] chnl_rx_data_valid; + wire [C_NUM_CHNL-1:0] chnl_rx_data_ren; + + wire [C_NUM_CHNL-1:0] chnl_tx_clk; + wire [C_NUM_CHNL-1:0] chnl_tx; + wire [C_NUM_CHNL-1:0] chnl_tx_ack; + wire [C_NUM_CHNL-1:0] chnl_tx_last; + wire [(C_NUM_CHNL*32)-1:0] chnl_tx_len; + wire [(C_NUM_CHNL*31)-1:0] chnl_tx_off; + wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data; + wire [C_NUM_CHNL-1:0] chnl_tx_data_valid; + wire [C_NUM_CHNL-1:0] chnl_tx_data_ren; + + wire chnl_reset; + wire chnl_clk; + assign chnl_clk = pld_clk; + assign chnl_reset = rst_out; + + riffa_wrapper_de5 + #(/*AUTOINSTPARAM*/ + // Parameters + .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), + .C_NUM_CHNL (C_NUM_CHNL), + .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), + .C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES)) + riffa + (// Outputs + .RX_ST_READY (rx_st_ready), + .TX_ST_DATA (tx_st_data[C_PCI_DATA_WIDTH-1:0]), + .TX_ST_VALID (tx_st_valid[0:0]), + .TX_ST_EOP (tx_st_eop[0:0]), + .TX_ST_SOP (tx_st_sop[0:0]), + .TX_ST_EMPTY (tx_st_empty[0:0]), + .APP_MSI_REQ (app_msi_req), + .RST_OUT (rst_out), + .CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]), + .CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]), + .CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), + .CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), + .CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), + .CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]), + .CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]), + .CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]), + // Inputs + .RX_ST_DATA (rx_st_data[C_PCI_DATA_WIDTH-1:0]), + .RX_ST_EOP (rx_st_eop[0:0]), + .RX_ST_SOP (rx_st_sop[0:0]), + .RX_ST_VALID (rx_st_valid[0:0]), + .RX_ST_EMPTY (rx_st_empty[0:0]), + .TX_ST_READY (tx_st_ready), + .TL_CFG_CTL (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]), + .TL_CFG_ADD (tl_cfg_add[`SIG_CFG_ADD_W-1:0]), + .TL_CFG_STS (tl_cfg_sts[`SIG_CFG_STS_W-1:0]), + .KO_CPL_SPC_HEADER (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]), + .KO_CPL_SPC_DATA (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]), + .APP_MSI_ACK (app_msi_ack), + .PLD_CLK (pld_clk), + .RESET_STATUS (reset_status), + .CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]), + .CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]), + .CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]), + .CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]), + .CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]), + .CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]), + .CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), + .CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), + .CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), + .CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])); + + // -------------------- END RIFFA INSTANTAION -------------------- + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_5mhz + (.CLK(riffa_5_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[0]), + .CHNL_RX(chnl_rx[0]), + .CHNL_RX_ACK(chnl_rx_ack[0]), + .CHNL_RX_LAST(chnl_rx_last[0]), + .CHNL_RX_LEN(chnl_rx_len[32*0 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*0 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[0]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[0]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[0]), + .CHNL_TX(chnl_tx[0]), + .CHNL_TX_ACK(chnl_tx_ack[0]), + .CHNL_TX_LAST(chnl_tx_last[0]), + .CHNL_TX_LEN(chnl_tx_len[32*0 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*0 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[0]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[0])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_10mhz + (.CLK(riffa_10_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[1]), + .CHNL_RX(chnl_rx[1]), + .CHNL_RX_ACK(chnl_rx_ack[1]), + .CHNL_RX_LAST(chnl_rx_last[1]), + .CHNL_RX_LEN(chnl_rx_len[32*1 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*1 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[1]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[1]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[1]), + .CHNL_TX(chnl_tx[1]), + .CHNL_TX_ACK(chnl_tx_ack[1]), + .CHNL_TX_LAST(chnl_tx_last[1]), + .CHNL_TX_LEN(chnl_tx_len[32*1 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*1 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[1]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[1])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_25mhz + (.CLK(riffa_25_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[2]), + .CHNL_RX(chnl_rx[2]), + .CHNL_RX_ACK(chnl_rx_ack[2]), + .CHNL_RX_LAST(chnl_rx_last[2]), + .CHNL_RX_LEN(chnl_rx_len[32*2 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*2 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[2]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[2]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[2]), + .CHNL_TX(chnl_tx[2]), + .CHNL_TX_ACK(chnl_tx_ack[2]), + .CHNL_TX_LAST(chnl_tx_last[2]), + .CHNL_TX_LEN(chnl_tx_len[32*2 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*2 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[2]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[2])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_50mhz + (.CLK(riffa_50_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[3]), + .CHNL_RX(chnl_rx[3]), + .CHNL_RX_ACK(chnl_rx_ack[3]), + .CHNL_RX_LAST(chnl_rx_last[3]), + .CHNL_RX_LEN(chnl_rx_len[32*3 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*3 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[3]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[3]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[3]), + .CHNL_TX(chnl_tx[3]), + .CHNL_TX_ACK(chnl_tx_ack[3]), + .CHNL_TX_LAST(chnl_tx_last[3]), + .CHNL_TX_LEN(chnl_tx_len[32*3 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*3 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[3]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[3])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_75mhz + (.CLK(riffa_75_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[4]), + .CHNL_RX(chnl_rx[4]), + .CHNL_RX_ACK(chnl_rx_ack[4]), + .CHNL_RX_LAST(chnl_rx_last[4]), + .CHNL_RX_LEN(chnl_rx_len[32*4 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*4 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[4]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[4]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[4]), + .CHNL_TX(chnl_tx[4]), + .CHNL_TX_ACK(chnl_tx_ack[4]), + .CHNL_TX_LAST(chnl_tx_last[4]), + .CHNL_TX_LEN(chnl_tx_len[32*4 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*4 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[4]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[4])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_100mhz + (.CLK(riffa_100_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[5]), + .CHNL_RX(chnl_rx[5]), + .CHNL_RX_ACK(chnl_rx_ack[5]), + .CHNL_RX_LAST(chnl_rx_last[5]), + .CHNL_RX_LEN(chnl_rx_len[32*5 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*5 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[5]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[5]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[5]), + .CHNL_TX(chnl_tx[5]), + .CHNL_TX_ACK(chnl_tx_ack[5]), + .CHNL_TX_LAST(chnl_tx_last[5]), + .CHNL_TX_LEN(chnl_tx_len[32*5 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*5 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[5]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[5])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_125mhz + (.CLK(riffa_125_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[6]), + .CHNL_RX(chnl_rx[6]), + .CHNL_RX_ACK(chnl_rx_ack[6]), + .CHNL_RX_LAST(chnl_rx_last[6]), + .CHNL_RX_LEN(chnl_rx_len[32*6 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*6 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[6]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[6]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[6]), + .CHNL_TX(chnl_tx[6]), + .CHNL_TX_ACK(chnl_tx_ack[6]), + .CHNL_TX_LAST(chnl_tx_last[6]), + .CHNL_TX_LEN(chnl_tx_len[32*6 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*6 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[6]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[6])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_150mhz + (.CLK(riffa_150_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[7]), + .CHNL_RX(chnl_rx[7]), + .CHNL_RX_ACK(chnl_rx_ack[7]), + .CHNL_RX_LAST(chnl_rx_last[7]), + .CHNL_RX_LEN(chnl_rx_len[32*7 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*7 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[7]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[7]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[7]), + .CHNL_TX(chnl_tx[7]), + .CHNL_TX_ACK(chnl_tx_ack[7]), + .CHNL_TX_LAST(chnl_tx_last[7]), + .CHNL_TX_LEN(chnl_tx_len[32*7 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*7 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[7]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[7])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_175mhz + (.CLK(riffa_175_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[8]), + .CHNL_RX(chnl_rx[8]), + .CHNL_RX_ACK(chnl_rx_ack[8]), + .CHNL_RX_LAST(chnl_rx_last[8]), + .CHNL_RX_LEN(chnl_rx_len[32*8 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*8 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[8]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[8]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[8]), + .CHNL_TX(chnl_tx[8]), + .CHNL_TX_ACK(chnl_tx_ack[8]), + .CHNL_TX_LAST(chnl_tx_last[8]), + .CHNL_TX_LEN(chnl_tx_len[32*8 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*8 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[8]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[8])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_200mhz + (.CLK(riffa_200_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[9]), + .CHNL_RX(chnl_rx[9]), + .CHNL_RX_ACK(chnl_rx_ack[9]), + .CHNL_RX_LAST(chnl_rx_last[9]), + .CHNL_RX_LEN(chnl_rx_len[32*9 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*9 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[9]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[9]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[9]), + .CHNL_TX(chnl_tx[9]), + .CHNL_TX_ACK(chnl_tx_ack[9]), + .CHNL_TX_LAST(chnl_tx_last[9]), + .CHNL_TX_LEN(chnl_tx_len[32*9 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*9 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[9]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[9])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_225mhz + (.CLK(riffa_225_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[10]), + .CHNL_RX(chnl_rx[10]), + .CHNL_RX_ACK(chnl_rx_ack[10]), + .CHNL_RX_LAST(chnl_rx_last[10]), + .CHNL_RX_LEN(chnl_rx_len[32*10 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*10 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[10]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[10]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[10]), + .CHNL_TX(chnl_tx[10]), + .CHNL_TX_ACK(chnl_tx_ack[10]), + .CHNL_TX_LAST(chnl_tx_last[10]), + .CHNL_TX_LEN(chnl_tx_len[32*10 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*10 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[10]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[10])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_250mhz + (.CLK(riffa_250_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[11]), + .CHNL_RX(chnl_rx[11]), + .CHNL_RX_ACK(chnl_rx_ack[11]), + .CHNL_RX_LAST(chnl_rx_last[11]), + .CHNL_RX_LEN(chnl_rx_len[32*11 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*11 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[11]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[11]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[11]), + .CHNL_TX(chnl_tx[11]), + .CHNL_TX_ACK(chnl_tx_ack[11]), + .CHNL_TX_LAST(chnl_tx_last[11]), + .CHNL_TX_LEN(chnl_tx_len[32*11 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*11 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[11]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[11])); + +endmodule diff --git a/fpga/altera/de5/DE5QGen2x8If128_CLK/ip/QSysDE5QGen2x8If128.qsys b/fpga/altera/de5/DE5QGen2x8If128_CLK/ip/QSysDE5QGen2x8If128.qsys new file mode 100644 index 0000000..6373bad --- /dev/null +++ b/fpga/altera/de5/DE5QGen2x8If128_CLK/ip/QSysDE5QGen2x8If128.qsys @@ -0,0 +1,883 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + g3_coeff_10_nxtber_less + + g3_coeff_10_nxtber_more + + + + + + + g3_coeff_11_nxtber_less + + g3_coeff_11_nxtber_more + + + + + + + g3_coeff_12_nxtber_less + + g3_coeff_12_nxtber_more + + + + + + + g3_coeff_13_nxtber_less + + g3_coeff_13_nxtber_more + + + + + + + g3_coeff_14_nxtber_less + + g3_coeff_14_nxtber_more + + + + + + + g3_coeff_15_nxtber_less + + g3_coeff_15_nxtber_more + + + + + + + g3_coeff_16_nxtber_less + + g3_coeff_16_nxtber_more + + + + + + + g3_coeff_17_nxtber_less + + g3_coeff_17_nxtber_more + + + + + + + g3_coeff_18_nxtber_less + + g3_coeff_18_nxtber_more + + + + + + + g3_coeff_19_nxtber_less + + g3_coeff_19_nxtber_more + + + + + + + g3_coeff_1_nxtber_less + + g3_coeff_1_nxtber_more + + + + + + + g3_coeff_20_nxtber_less + + g3_coeff_20_nxtber_more + + + + + + + g3_coeff_21_nxtber_less + + g3_coeff_21_nxtber_more + + + + + + + g3_coeff_22_nxtber_less + + g3_coeff_22_nxtber_more + + + + + + + g3_coeff_23_nxtber_less + + g3_coeff_23_nxtber_more + + + + + + + g3_coeff_24_nxtber_less + + g3_coeff_24_nxtber_more + + + + + + + g3_coeff_2_nxtber_less + + g3_coeff_2_nxtber_more + + + + + + + g3_coeff_3_nxtber_less + + g3_coeff_3_nxtber_more + + + + + + + g3_coeff_4_nxtber_less + + g3_coeff_4_nxtber_more + + + + + + + g3_coeff_5_nxtber_less + + g3_coeff_5_nxtber_more + + + + + + + g3_coeff_6_nxtber_less + + g3_coeff_6_nxtber_more + + + + + + + g3_coeff_7_nxtber_less + + g3_coeff_7_nxtber_more + + + + + + + g3_coeff_8_nxtber_less + + g3_coeff_8_nxtber_more + + + + + + + g3_coeff_9_nxtber_less + + g3_coeff_9_nxtber_more + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Create an adjpllin signal to connect with an upstream PLL + + + + + + + + + + + + + + + + + + + + + + + + Automatic Switchover + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/altera/de5/DE5QGen2x8If128_CLK/prj/DE5QGen2x8If128.qpf b/fpga/altera/de5/DE5QGen2x8If128_CLK/prj/DE5QGen2x8If128.qpf new file mode 100644 index 0000000..01d7852 --- /dev/null +++ b/fpga/altera/de5/DE5QGen2x8If128_CLK/prj/DE5QGen2x8If128.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.0 Build 145 04/22/2015 SJ Full Version +# Date created = 11:11:58 January 20, 2016 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.0" +DATE = "11:11:58 January 20, 2016" + +# Revisions + +PROJECT_REVISION = "DE5QGen2x8If128" diff --git a/fpga/altera/de5/DE5QGen2x8If128_CLK/prj/DE5QGen2x8If128.qsf b/fpga/altera/de5/DE5QGen2x8If128_CLK/prj/DE5QGen2x8If128.qsf new file mode 100644 index 0000000..b13ef14 --- /dev/null +++ b/fpga/altera/de5/DE5QGen2x8If128_CLK/prj/DE5QGen2x8If128.qsf @@ -0,0 +1,493 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Full Version +# Date created = 11:03:06 March 21, 2014 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# DE5QGen2x8If128_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Stratix V" +set_global_assignment -name DEVICE 5SGXEA7N2F45C2 +set_global_assignment -name TOP_LEVEL_ENTITY DE5QGen2x8If128 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06 MARCH 21, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/ + +################################################################################ +# Timing SDC Files +################################################################################ + +################################################################################ +# PCIE Connections +################################################################################ +# PCIe clk (100 MHz) +set_location_assignment PIN_AK38 -to PCIE_REFCLK +set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK + +set_location_assignment PIN_AU33 -to PCIE_RESET_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_RESET_N + +################################################################################ +#PCIE Pins +################################################################################ +# Settings from SV PCIE User Guide (AV-ST) +# - 1.5V PCML +# - XCVR_VCCR_VCCT_VOLTAGE 1_0V +# - XCVR_VCCA_VOLTAGE 3_0V +# (SV User guide recommends VCCR/VCCT = 0_9 and VCCA = 2_5 , but link does not +# train correctly if these settings are used) +# +# We use CMU PLL's (http://www.altera.com/literature/hb/stratix-v/stx5_52003.pdf) +# Errata: http://www.altera.com/support/kdb/solutions/rd10112012_529.html +################################################################################ +# Gloabal PCIE assignments (Use if signal problems exist) +################################################################################ +# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[*] +# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[*](n)" +# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[*] +# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[*](n)" +# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[*] +# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[*](n)" +# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[*] +# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[*](n)" +# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[*] +# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[*](n)" + +# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_TX_OUT[*] +# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_TX_OUT[*](n)" +# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_TX_OUT[*] +# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_TX_OUT[*](n)" +# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_TX_OUT[*] +# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_TX_OUT[*](n)" +# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_TX_OUT[*] +# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_TX_OUT[*](n)" +# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_TX_OUT[*] +# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_TX_OUT[*](n)" + +################################################################################ +#PCIE RX_IN 0 +################################################################################ + +set_location_assignment PIN_BB43 -to PCIE_RX_IN[0] +set_location_assignment PIN_BB44 -to "PCIE_RX_IN[0](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[0] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[0] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[0] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[0](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[0](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[0](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[0](n)" + +################################################################################ +#PCIE RX_IN 1 +################################################################################ + +set_location_assignment PIN_BA41 -to PCIE_RX_IN[1] +set_location_assignment PIN_BA42 -to "PCIE_RX_IN[1](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[1] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[1] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[1] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[1](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[1](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[1](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[1](n)" + +################################################################################ +#PCIE RX_IN 2 +################################################################################ + +set_location_assignment PIN_AW41 -to PCIE_RX_IN[2] +set_location_assignment PIN_AW42 -to "PCIE_RX_IN[2](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[2] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[2] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[2] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[2](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[2](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[2](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[2](n)" + +################################################################################ +#PCIE RX_IN 3 +################################################################################ + +set_location_assignment PIN_AY43 -to PCIE_RX_IN[3] +set_location_assignment PIN_AY44 -to "PCIE_RX_IN[3](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[3] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[3] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[3] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[3](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[3](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[3](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[3](n)" + +################################################################################ +#PCIE RX_IN 4 +################################################################################ + +set_location_assignment PIN_AT43 -to PCIE_RX_IN[4] +set_location_assignment PIN_AT44 -to "PCIE_RX_IN[4](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[4] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[4] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[4] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[4] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[4](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[4](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[4](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[4](n)" + +################################################################################ +#PCIE RX_IN 5 +################################################################################ + +set_location_assignment PIN_AP43 -to PCIE_RX_IN[5] +set_location_assignment PIN_AP44 -to "PCIE_RX_IN[5](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[5] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[5] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[5] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[5] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[5](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[5](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[5](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[5](n)" + +################################################################################ +#PCIE RX_IN 6 +################################################################################ + +set_location_assignment PIN_AM43 -to PCIE_RX_IN[6] +set_location_assignment PIN_AM44 -to "PCIE_RX_IN[6](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[6] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[6] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[6] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[6] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[6](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[6](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[6](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[6](n)" + +################################################################################ +#PCIE RX_IN 7 +################################################################################ + +set_location_assignment PIN_AK43 -to PCIE_RX_IN[7] +set_location_assignment PIN_AK44 -to "PCIE_RX_IN[7](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[7] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[7] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[7] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[7] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[7](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[7](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[7](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[7](n)" + +################################################################################ +#PCIE TX_OUT 0 +################################################################################ +set_location_assignment PIN_AY39 -to PCIE_TX_OUT[0] +set_location_assignment PIN_AY40 -to "PCIE_TX_OUT[0](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[0] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[0] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[0] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[0](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[0](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[0](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[0](n)" + +################################################################################ +#PCIE TX_OUT 1 +################################################################################ +set_location_assignment PIN_AV39 -to PCIE_TX_OUT[1] +set_location_assignment PIN_AV40 -to "PCIE_TX_OUT[1](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[1] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[1] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[1] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[1](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[1](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[1](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[1](n)" + +################################################################################ +#PCIE TX_OUT 2 +################################################################################ +set_location_assignment PIN_AT39 -to PCIE_TX_OUT[2] +set_location_assignment PIN_AT40 -to "PCIE_TX_OUT[2](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[2] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[2] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[2] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[2](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[2](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[2](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[2](n)" + +################################################################################ +#PCIE TX_OUT 3 +################################################################################ +set_location_assignment PIN_AU41 -to PCIE_TX_OUT[3] +set_location_assignment PIN_AU42 -to "PCIE_TX_OUT[3](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[3] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[3] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[3] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[3](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[3](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[3](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[3](n)" + +################################################################################ +#PCIE TX_OUT 4 +################################################################################ +set_location_assignment PIN_AN41 -to PCIE_TX_OUT[4] +set_location_assignment PIN_AN42 -to "PCIE_TX_OUT[4](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[4] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[4] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[4] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[4] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[4](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[4](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[4](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[4](n)" + +################################################################################ +#PCIE TX_OUT 5 +################################################################################ +set_location_assignment PIN_AL41 -to PCIE_TX_OUT[5] +set_location_assignment PIN_AL42 -to "PCIE_TX_OUT[5](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[5] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[5] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[5] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[5] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[5](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[5](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[5](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[5](n)" + +################################################################################ +#PCIE TX_OUT 6 +################################################################################ +set_location_assignment PIN_AJ41 -to PCIE_TX_OUT[6] +set_location_assignment PIN_AJ42 -to "PCIE_TX_OUT[6](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[6] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[6] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[6] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[6] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[6](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[6](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[6](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[6](n)" + +################################################################################ +#PCIE TX_OUT 7 +################################################################################ + +set_location_assignment PIN_AG41 -to PCIE_TX_OUT[7] +set_location_assignment PIN_AG42 -to "PCIE_TX_OUT[7](n)" + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[7] +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[7] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[7] +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[7] + +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[7](n)" +set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[7](n)" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[7](n)" +set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[7](n)" + +################################################################################ +# LED's +################################################################################ +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7] + +set_location_assignment PIN_AW37 -to LED[0] +set_location_assignment PIN_AV37 -to LED[1] +set_location_assignment PIN_BB36 -to LED[2] +set_location_assignment PIN_BB39 -to LED[3] +set_location_assignment PIN_AH15 -to LED[4] +set_location_assignment PIN_AH13 -to LED[5] +set_location_assignment PIN_AJ13 -to LED[6] +set_location_assignment PIN_AJ14 -to LED[7] + +################################################################################ +# OSCILLATORS +################################################################################ + +set_location_assignment PIN_BC28 -to OSC_BANK3D_50MHZ +set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_BANK3D_50MHZ + +################################################################################ +# End Custom Instantiations +################################################################################ + +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name QSYS_FILE ../ip/QSysDE5QGen2x8If128.qsys +set_global_assignment -name SDC_FILE ../constr/DE5QGen2x8If128.sdc +set_global_assignment -name SEARCH_PATH ../../../../riffa_hdl +set_global_assignment -name VERILOG_FILE ../hdl/DE5QGen2x8If128.v +set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_extender.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_controller.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ohtb.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v +set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/fpga/riffa_hdl/tx_port_monitor_128.v b/fpga/riffa_hdl/tx_port_monitor_128.v index 4229698..7896707 100644 --- a/fpga/riffa_hdl/tx_port_monitor_128.v +++ b/fpga/riffa_hdl/tx_port_monitor_128.v @@ -224,33 +224,4 @@ always @ (*) begin _rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData); end -/* -wire [35:0] wControl0; -chipscope_icon_1 cs_icon( - .CONTROL0(wControl0) -); - -chipscope_ila_t8_512 a0( - .CLK(CLK), - .CONTROL(wControl0), - .TRIG0({TXN, wPayloadData, wEventData, rState}), - .DATA({201'd0, - rWordsRecvd, // 32 - WR_COUNT, // 10 - wPayloadData, // 1 - EVT_DATA_RD_EN, // 1 - RST, // 1 - rTxErr, // 1 - wEventData, // 1 - rReadData, // 64 - OFF, // 31 - LEN, // 32 - LAST, // 1 - TXN, // 1 - EVT_DATA_EMPTY, // 1 - EVT_DATA, // 129 - rState}) // 5 -); -*/ - endmodule diff --git a/fpga/riffa_hdl/tx_port_monitor_32.v b/fpga/riffa_hdl/tx_port_monitor_32.v index c0001cc..3929c3f 100644 --- a/fpga/riffa_hdl/tx_port_monitor_32.v +++ b/fpga/riffa_hdl/tx_port_monitor_32.v @@ -204,7 +204,7 @@ always @ (*) begin _rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY)); // Read until we get a (valid) event - _rRead = (!rState[2] & !(rState[1] & rEvent) & !wEventData & !rAlmostFull); // !S_TXPORTMON32_TXN + _rRead = (!rState[2] & !(rState[1] & (rEvent | wEventData | ~EVT_DATA_EMPTY)) & !wEventData & !rAlmostFull); // !S_TXPORTMON32_TXN // Track detected events _rEvent = wEventData; diff --git a/fpga/riffa_hdl/tx_port_monitor_64.v b/fpga/riffa_hdl/tx_port_monitor_64.v index 744f8ae..b76a79b 100644 --- a/fpga/riffa_hdl/tx_port_monitor_64.v +++ b/fpga/riffa_hdl/tx_port_monitor_64.v @@ -99,7 +99,6 @@ reg rLenEQ0Lo=0, _rLenEQ0Lo=0; reg rLenLE2Lo=0, _rLenLE2Lo=0; reg rTxErr=0, _rTxErr=0; - wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]); wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[3]); // S_TXPORTMON64_READ wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE2Lo)) & wPayloadData); @@ -201,7 +200,7 @@ always @ (*) begin _rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY)); // Read until we get a (valid) event - _rRead = (!rState[2] & !(rState[1] & rEvent) & !wEventData & !rAlmostFull); // !S_TXPORTMON64_TXN + _rRead = (!rState[2] & !(rState[1] & (rEvent | wEventData | ~EVT_DATA_EMPTY)) & !wEventData & !rAlmostFull); // !S_TXPORTMON64_TXN // Track detected events _rEvent = wEventData; @@ -225,32 +224,4 @@ always @ (*) begin _rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData); end -/* -wire [35:0] wControl0; -chipscope_icon_1 cs_icon( - .CONTROL0(wControl0) -); - -chipscope_ila_t8_512 a0( - .CLK(CLK), - .CONTROL(wControl0), - .TRIG0({TXN, wPayloadData, wEventData, rState}), - .DATA({297'd0, - WR_COUNT, // 10 - wPayloadData, // 1 - EVT_DATA_RD_EN, // 1 - RST, // 1 - rTxErr, // 1 - wEventData, // 1 - rReadData, // 64 - OFF, // 31 - LEN, // 32 - LAST, // 1 - TXN, // 1 - EVT_DATA_EMPTY, // 1 - EVT_DATA, // 65 - rState}) // 5 -); -*/ - endmodule diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/Makefile b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/Makefile new file mode 100644 index 0000000..795546b --- /dev/null +++ b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/Makefile @@ -0,0 +1,62 @@ +# ---------------------------------------------------------------------- +# Copyright (c) 2016, The Regents of the University of California All +# rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# +# * Neither the name of The Regents of the University of California +# nor the names of its contributors may be used to endorse or +# promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE +# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +# DAMAGE. +# ---------------------------------------------------------------------- +#----------------------------------------------------------------------- +# Filename: Makefile +# Version: 1.0 +# Description: Project-level makefile for building an example project +# Author: Dustin Richmond (@darichmond) +#----------------------------------------------------------------------- +# This make file expects the following variables to be set: +# RIFFA_HDL_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory. +# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to +# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory +WIDTH=64 +TYPE=ultrascale +CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))) +PROJECT=$(shell basename $(CURRENT_PATH)) + +ifndef RIFFA_HDL_PATH + RIFFA_HDL_PATH:=../../../riffa_hdl +endif +ifndef BOARD_PATH + BOARD_PATH:=.. +endif +ifndef JOBS + JOBS=1 +endif +include $(RIFFA_HDL_PATH)/riffa.mk +include $(BOARD_PATH)/board.mk + +PROJECT_IP+=ip/PCIeGen1x8If64.xci diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/bit/VC709_Gen1x8If64.bit b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/bit/VC709_Gen1x8If64.bit new file mode 100644 index 0000000..10b6d0a Binary files /dev/null and b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/bit/VC709_Gen1x8If64.bit differ diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/constr/VC709_Gen1x8If64.xdc b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/constr/VC709_Gen1x8If64.xdc new file mode 100644 index 0000000..958153f --- /dev/null +++ b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/constr/VC709_Gen1x8If64.xdc @@ -0,0 +1,151 @@ +# ---------------------------------------------------------------------- +# Copyright (c) 2016, The Regents of the University of California All +# rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# +# * Neither the name of The Regents of the University of California +# nor the names of its contributors may be used to endorse or +# promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE +# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +# DAMAGE. +# ---------------------------------------------------------------------- +#---------------------------------------------------------------------------- +# Filename: VC709_Top.xdc +# Version: 1.00.a +# Verilog Standard: Verilog-2001 +# Description: Xilinx Design Constraints for the VC709 board. +# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin +# +# Author: Dustin Richmond (@darichmond) +#----------------------------------------------------------------------------- +# +######################################################################################################################### +# User Constraints +######################################################################################################################### + +############################################################################### +# User Time Names / User Time Groups / Time Specs +############################################################################### + +############################################################################### +# User Physical Constraints +############################################################################### + +# +# LED Status Indicators for Example Design. +# LED 0-2 should be all ON if link is up and functioning correctly +# LED 3 should be blinking if user application is receiving valid clock +# + +#System Reset, User Reset, User Link Up, User Clk Heartbeat +set_property PACKAGE_PIN AM39 [get_ports {LED[0]}] +set_property PACKAGE_PIN AN39 [get_ports {LED[1]}] +set_property PACKAGE_PIN AR37 [get_ports {LED[2]}] +set_property PACKAGE_PIN AT37 [get_ports {LED[3]}] +set_property PACKAGE_PIN AR35 [get_ports {LED[4]}] +set_property PACKAGE_PIN AP41 [get_ports {LED[5]}] +set_property PACKAGE_PIN AP42 [get_ports {LED[6]}] +set_property PACKAGE_PIN AU39 [get_ports {LED[7]}] + +set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {LED[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {LED[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {LED[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {LED[7]}] + +set_false_path -to [get_ports -filter NAME=~LED*] + +######################################################################################################################### +# End User Constraints +######################################################################################################################### +# +# +# +######################################################################################################################### +# PCIE Core Constraints +######################################################################################################################### + +# +# SYS reset (input) signal. The sys_reset_n signal should be +# obtained from the PCI Express interface if possible. For +# slot based form factors, a system reset signal is usually +# present on the connector. For cable based form factors, a +# system reset signal may not be available. In this case, the +# system reset signal must be generated locally by some form of +# supervisory circuit. You may change the IOSTANDARD and LOC +# to suit your requirements and VCCO voltage banking rules. +# Some 7 series devices do not have 3.3 V I/Os available. +# Therefore the appropriate level shift is required to operate +# with these devices that contain only 1.8 V banks. +# + +set_property PACKAGE_PIN AV35 [get_ports PCIE_RESET_N] +set_property IOSTANDARD LVCMOS18 [get_ports PCIE_RESET_N] +set_property PULLUP true [get_ports PCIE_RESET_N] + +# +# +# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n +# signals are the PCI Express reference clock. Virtex-7 GT +# Transceiver architecture requires the use of a dedicated clock +# resources (FPGA input pins) associated with each GT Transceiver. +# To use these pins an IBUFDS primitive (refclk_ibuf) is +# instantiated in user's design. +# Please refer to the Virtex-7 GT Transceiver User Guide +# (UG) for guidelines regarding clock resource selection. +# +set_property LOC IBUFDS_GTE2_X1Y11 [get_cells refclk_ibuf] + +############################################################################### +# Timing Constraints +############################################################################### +create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O] + +############################################################################### +# Physical Constraints +############################################################################### + +set_false_path -from [get_ports PCIE_RESET_N] +############################################################################### +# End +############################################################################### + +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] -group [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT1]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT1]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT2]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT3]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT4]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT5]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen_2/inst/mmcm_adv_inst/CLKOUT0]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen_2/inst/mmcm_adv_inst/CLKOUT1]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen_2/inst/mmcm_adv_inst/CLKOUT2]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen_2/inst/mmcm_adv_inst/CLKOUT3]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen_2/inst/mmcm_adv_inst/CLKOUT4]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen_2/inst/mmcm_adv_inst/CLKOUT5]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/hdl/VC709_Gen1x8If64.v b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/hdl/VC709_Gen1x8If64.v new file mode 100644 index 0000000..8a3ab3d --- /dev/null +++ b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/hdl/VC709_Gen1x8If64.v @@ -0,0 +1,790 @@ +// ---------------------------------------------------------------------- +// Copyright (c) 2016, The Regents of the University of California All +// rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above +// copyright notice, this list of conditions and the following +// disclaimer in the documentation and/or other materials provided +// with the distribution. +// +// * Neither the name of The Regents of the University of California +// nor the names of its contributors may be used to endorse or +// promote products derived from this software without specific +// prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE +// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +// DAMAGE. +// ---------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// Filename: VC709_Gen1x8If64.v +// Version: 1.00.a +// Verilog Standard: Verilog-2001 +// Description: Top level module for RIFFA 2.2 reference design for the +// the Xilinx VC709 Development Board. +// Author: Dustin Richmond (@darichmond) +//----------------------------------------------------------------------------- +`include "functions.vh" +`include "riffa.vh" +`include "ultrascale.vh" +`timescale 1ps / 1ps +module VC709_Gen1x8If64 + #(// Number of RIFFA Channels + parameter C_NUM_CHNL = 12, + // Number of PCIe Lanes + parameter C_NUM_LANES = 8, + // Settings from Vivado IP Generator + parameter C_PCI_DATA_WIDTH = 64, + parameter C_MAX_PAYLOAD_BYTES = 256, + parameter C_LOG_NUM_TAGS = 6) + (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP, + output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN, + input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP, + input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN, + + output [7:0] LED, + input PCIE_REFCLK_P, + input PCIE_REFCLK_N, + input PCIE_RESET_N); + + // Clocks, etc + wire user_lnk_up; + wire user_clk; + wire user_reset; + wire pcie_refclk; + wire pcie_reset_n; + wire riffa_5_clk; + wire riffa_10_clk; + wire riffa_25_clk; + wire riffa_50_clk; + wire riffa_75_clk; + wire riffa_100_clk; + wire riffa_125_clk; + wire riffa_150_clk; + wire riffa_175_clk; + wire riffa_200_clk; + wire riffa_225_clk; + wire riffa_250_clk; + + // Interface: RQ (TXC) + wire s_axis_rq_tlast; + wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata; + wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser; + wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep; + wire s_axis_rq_tready; + wire s_axis_rq_tvalid; + // Interface: RC (RXC) + wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata; + wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser; + wire m_axis_rc_tlast; + wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep; + wire m_axis_rc_tvalid; + wire m_axis_rc_tready; + // Interface: CQ (RXR) + wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata; + wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser; + wire m_axis_cq_tlast; + wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep; + wire m_axis_cq_tvalid; + wire m_axis_cq_tready; + // Interface: CC (TXC) + wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata; + wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser; + wire s_axis_cc_tlast; + wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep; + wire s_axis_cc_tvalid; + wire s_axis_cc_tready; + + // Configuration (CFG) Interface + wire [3:0] pcie_rq_seq_num; + wire pcie_rq_seq_num_vld; + wire [5:0] pcie_rq_tag; + wire pcie_rq_tag_vld; + wire pcie_cq_np_req; + wire [5:0] pcie_cq_np_req_count; + + wire cfg_phy_link_down; + wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH + wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE + wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD + wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST + wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE + wire [5:0] cfg_function_power_state; // Ignorable but not removable + wire [11:0] cfg_vf_status; // Ignorable but not removable + wire [17:0] cfg_vf_power_state; // Ignorable but not removable + wire [1:0] cfg_link_power_state; // Ignorable but not removable + + // Error Reporting Interface + wire cfg_err_cor_out; + wire cfg_err_nonfatal_out; + wire cfg_err_fatal_out; + + wire cfg_ltr_enable; + wire [5:0] cfg_ltssm_state;// TODO: Connect to LED's + wire [1:0] cfg_rcb_status; + wire [1:0] cfg_dpa_substate_change; + wire [1:0] cfg_obff_enable; + wire cfg_pl_status_change; + + wire [1:0] cfg_tph_requester_enable; + wire [5:0] cfg_tph_st_mode; + wire [5:0] cfg_vf_tph_requester_enable; + wire [17:0] cfg_vf_tph_st_mode; + wire [7:0] cfg_fc_ph; + wire [11:0] cfg_fc_pd; + wire [7:0] cfg_fc_nph; + wire [11:0] cfg_fc_npd; + wire [7:0] cfg_fc_cplh; + wire [11:0] cfg_fc_cpld; + wire [2:0] cfg_fc_sel; + + // Interrupt Interface Signals + wire [3:0] cfg_interrupt_int; + wire [1:0] cfg_interrupt_pending; + wire cfg_interrupt_sent; + wire [1:0] cfg_interrupt_msi_enable; + wire [5:0] cfg_interrupt_msi_vf_enable; + wire [5:0] cfg_interrupt_msi_mmenable; + wire cfg_interrupt_msi_mask_update; + wire [31:0] cfg_interrupt_msi_data; + wire [3:0] cfg_interrupt_msi_select; + wire [31:0] cfg_interrupt_msi_int; + wire [63:0] cfg_interrupt_msi_pending_status; + wire cfg_interrupt_msi_sent; + wire cfg_interrupt_msi_fail; + wire [2:0] cfg_interrupt_msi_attr; + wire cfg_interrupt_msi_tph_present; + wire [1:0] cfg_interrupt_msi_tph_type; + wire [8:0] cfg_interrupt_msi_tph_st_tag; + wire [2:0] cfg_interrupt_msi_function_number; + + wire rst_out; + wire [C_NUM_CHNL-1:0] chnl_rx_clk; + wire [C_NUM_CHNL-1:0] chnl_rx; + wire [C_NUM_CHNL-1:0] chnl_rx_ack; + wire [C_NUM_CHNL-1:0] chnl_rx_last; + wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; + wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; + wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data; + wire [C_NUM_CHNL-1:0] chnl_rx_data_valid; + wire [C_NUM_CHNL-1:0] chnl_rx_data_ren; + + wire [C_NUM_CHNL-1:0] chnl_tx_clk; + wire [C_NUM_CHNL-1:0] chnl_tx; + wire [C_NUM_CHNL-1:0] chnl_tx_ack; + wire [C_NUM_CHNL-1:0] chnl_tx_last; + wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; + wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; + wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data; + wire [C_NUM_CHNL-1:0] chnl_tx_data_valid; + wire [C_NUM_CHNL-1:0] chnl_tx_data_ren; + + genvar chnl; + + IBUF + #() + pci_reset_n_ibuf + (.O(pcie_reset_n), + .I(PCIE_RESET_N)); + + IBUFDS_GTE2 + #() + refclk_ibuf + (.O(pcie_refclk), + .ODIV2(), + .I(PCIE_REFCLK_P), + .CEB(1'b0), + .IB(PCIE_REFCLK_N)); + + OBUF + #() + led_0_obuf + (.O(LED[0]), + .I(cfg_ltssm_state[0])); + OBUF + #() + led_1_obuf + (.O(LED[1]), + .I(cfg_ltssm_state[1])); + OBUF + #() + led_2_obuf + (.O(LED[2]), + .I(cfg_ltssm_state[2])); + OBUF + #() + led_3_obuf + (.O(LED[3]), + .I(cfg_ltssm_state[3])); + OBUF + #() + led_4_obuf + (.O(LED[4]), + .I(cfg_ltssm_state[4])); + OBUF + #() + led_5_obuf + (.O(LED[5]), + .I(cfg_ltssm_state[5])); + OBUF + #() + led_6_obuf + (.O(LED[6]), + .I(pcie_reset_n)); + OBUF + #() + led_7_obuf + (.O(LED[7]), + .I(rst_out)); + + // Core Top Level Wrapper + PCIeGen1x8If64 + #() + pcie3_7x_0_i + (//--------------------------------------------------------------------- + // PCI Express (pci_exp) Interface + //--------------------------------------------------------------------- + .pci_exp_txn ( PCI_EXP_TXN ), + .pci_exp_txp ( PCI_EXP_TXP ), + .pci_exp_rxn ( PCI_EXP_RXN ), + .pci_exp_rxp ( PCI_EXP_RXP ), + + //--------------------------------------------------------------------- + // AXI Interface + //--------------------------------------------------------------------- + .user_clk ( user_clk ), + .user_reset ( user_reset ), + .user_lnk_up ( user_lnk_up ), + .user_app_rdy ( ), + + .s_axis_rq_tlast ( s_axis_rq_tlast ), + .s_axis_rq_tdata ( s_axis_rq_tdata ), + .s_axis_rq_tuser ( s_axis_rq_tuser ), + .s_axis_rq_tkeep ( s_axis_rq_tkeep ), + .s_axis_rq_tready ( s_axis_rq_tready ), + .s_axis_rq_tvalid ( s_axis_rq_tvalid ), + + .m_axis_rc_tdata ( m_axis_rc_tdata ), + .m_axis_rc_tuser ( m_axis_rc_tuser ), + .m_axis_rc_tlast ( m_axis_rc_tlast ), + .m_axis_rc_tkeep ( m_axis_rc_tkeep ), + .m_axis_rc_tvalid ( m_axis_rc_tvalid ), + .m_axis_rc_tready ( {22{m_axis_rc_tready}} ), + + .m_axis_cq_tdata ( m_axis_cq_tdata ), + .m_axis_cq_tuser ( m_axis_cq_tuser ), + .m_axis_cq_tlast ( m_axis_cq_tlast ), + .m_axis_cq_tkeep ( m_axis_cq_tkeep ), + .m_axis_cq_tvalid ( m_axis_cq_tvalid ), + .m_axis_cq_tready ( {22{m_axis_cq_tready}} ), + + .s_axis_cc_tdata ( s_axis_cc_tdata ), + .s_axis_cc_tuser ( s_axis_cc_tuser ), + .s_axis_cc_tlast ( s_axis_cc_tlast ), + .s_axis_cc_tkeep ( s_axis_cc_tkeep ), + .s_axis_cc_tvalid ( s_axis_cc_tvalid ), + .s_axis_cc_tready ( s_axis_cc_tready ), + + //--------------------------------------------------------------------- + // Configuration (CFG) Interface + //--------------------------------------------------------------------- + .pcie_rq_seq_num ( pcie_rq_seq_num ), + .pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ), + .pcie_rq_tag ( pcie_rq_tag ), + .pcie_rq_tag_vld ( pcie_rq_tag_vld ), + .pcie_cq_np_req ( pcie_cq_np_req ), + .pcie_cq_np_req_count ( pcie_cq_np_req_count ), + .cfg_phy_link_down ( cfg_phy_link_down ), + .cfg_phy_link_status ( cfg_phy_link_status), + .cfg_negotiated_width ( cfg_negotiated_width ), + .cfg_current_speed ( cfg_current_speed ), + .cfg_max_payload ( cfg_max_payload ), + .cfg_max_read_req ( cfg_max_read_req ), + .cfg_function_status ( cfg_function_status ), + .cfg_function_power_state ( cfg_function_power_state ), + .cfg_vf_status ( cfg_vf_status ), + .cfg_vf_power_state ( cfg_vf_power_state ), + .cfg_link_power_state ( cfg_link_power_state ), + // Error Reporting Interface + .cfg_err_cor_out ( cfg_err_cor_out ), + .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), + .cfg_err_fatal_out ( cfg_err_fatal_out ), + .cfg_ltr_enable ( cfg_ltr_enable ), + .cfg_ltssm_state ( cfg_ltssm_state ), + .cfg_rcb_status ( cfg_rcb_status ), + .cfg_dpa_substate_change ( cfg_dpa_substate_change ), + .cfg_obff_enable ( cfg_obff_enable ), + .cfg_pl_status_change ( cfg_pl_status_change ), + .cfg_tph_requester_enable ( cfg_tph_requester_enable ), + .cfg_tph_st_mode ( cfg_tph_st_mode ), + .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), + .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), + .cfg_fc_ph ( cfg_fc_ph ), + .cfg_fc_pd ( cfg_fc_pd ), + .cfg_fc_nph ( cfg_fc_nph ), + .cfg_fc_npd ( cfg_fc_npd ), + .cfg_fc_cplh ( cfg_fc_cplh ), + .cfg_fc_cpld ( cfg_fc_cpld ), + .cfg_fc_sel ( cfg_fc_sel ), + //--------------------------------------------------------------------- + // EP Only + //--------------------------------------------------------------------- + // Interrupt Interface Signals + .cfg_interrupt_int ( cfg_interrupt_int ), + .cfg_interrupt_pending ( cfg_interrupt_pending ), + .cfg_interrupt_sent ( cfg_interrupt_sent ), + .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ), + .cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ), + .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), + .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), + .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), + .cfg_interrupt_msi_select ( cfg_interrupt_msi_select ), + .cfg_interrupt_msi_int ( cfg_interrupt_msi_int ), + .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ), + .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), + .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), + .cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ), + .cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ), + .cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ), + .cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ), + .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ), + + //--------------------------------------------------------------------- + // System(SYS) Interface + //--------------------------------------------------------------------- + .sys_clk (pcie_refclk), + .sys_reset (~pcie_reset_n)); + + riffa_wrapper_vc709 + #(/*AUTOINSTPARAM*/ + // Parameters + .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), + .C_NUM_CHNL (C_NUM_CHNL), + .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), + .C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES)) + riffa + (// Outputs + .M_AXIS_CQ_TREADY (m_axis_cq_tready), + .M_AXIS_RC_TREADY (m_axis_rc_tready), + .S_AXIS_CC_TVALID (s_axis_cc_tvalid), + .S_AXIS_CC_TLAST (s_axis_cc_tlast), + .S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]), + .S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), + .S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]), + .S_AXIS_RQ_TVALID (s_axis_rq_tvalid), + .S_AXIS_RQ_TLAST (s_axis_rq_tlast), + .S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]), + .S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), + .S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]), + .USER_CLK (user_clk), + .USER_RESET (user_reset), + .CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]), + .CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]), + .CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]), + .CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]), + .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]), + .CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]), + .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present), + .CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]), + .CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]), + .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]), + .CFG_FC_SEL (cfg_fc_sel[2:0]), + .PCIE_CQ_NP_REQ (pcie_cq_np_req), + .RST_OUT (rst_out), + .CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]), + .CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]), + .CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), + .CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), + .CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), + .CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]), + .CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]), + .CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]), + // Inputs + .M_AXIS_CQ_TVALID (m_axis_cq_tvalid), + .M_AXIS_CQ_TLAST (m_axis_cq_tlast), + .M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]), + .M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), + .M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]), + .M_AXIS_RC_TVALID (m_axis_rc_tvalid), + .M_AXIS_RC_TLAST (m_axis_rc_tlast), + .M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]), + .M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), + .M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]), + .S_AXIS_CC_TREADY (s_axis_cc_tready), + .S_AXIS_RQ_TREADY (s_axis_rq_tready), + .CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]), + .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update), + .CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]), + .CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent), + .CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail), + .CFG_FC_CPLH (cfg_fc_cplh[7:0]), + .CFG_FC_CPLD (cfg_fc_cpld[11:0]), + .CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]), + .CFG_CURRENT_SPEED (cfg_current_speed[2:0]), + .CFG_MAX_PAYLOAD (cfg_max_payload[2:0]), + .CFG_MAX_READ_REQ (cfg_max_read_req[2:0]), + .CFG_FUNCTION_STATUS (cfg_function_status[7:0]), + .CFG_RCB_STATUS (cfg_rcb_status[1:0]), + .CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]), + .CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]), + .CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]), + .CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]), + .CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]), + .CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]), + .CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), + .CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), + .CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), + .CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])); + + clk_250MIn_1 + clkgen + (.user_clk(user_clk), + .riffa_5_clk(riffa_5_clk), + .riffa_10_clk(riffa_10_clk), + .riffa_25_clk(riffa_25_clk), + .riffa_50_clk(riffa_50_clk), + .riffa_75_clk(riffa_75_clk), + .riffa_100_clk(riffa_100_clk)); + clk_250MIn_2 + clkgen_2 + (.user_clk(user_clk), + .riffa_125_clk(riffa_125_clk), + .riffa_150_clk(riffa_150_clk), + .riffa_175_clk(riffa_175_clk), + .riffa_200_clk(riffa_200_clk), + .riffa_225_clk(riffa_225_clk), + .riffa_250_clk(riffa_250_clk)); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_5mhz + (.CLK(riffa_5_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[0]), + .CHNL_RX(chnl_rx[0]), + .CHNL_RX_ACK(chnl_rx_ack[0]), + .CHNL_RX_LAST(chnl_rx_last[0]), + .CHNL_RX_LEN(chnl_rx_len[32*0 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*0 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[0]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[0]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[0]), + .CHNL_TX(chnl_tx[0]), + .CHNL_TX_ACK(chnl_tx_ack[0]), + .CHNL_TX_LAST(chnl_tx_last[0]), + .CHNL_TX_LEN(chnl_tx_len[32*0 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*0 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[0]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[0])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_10mhz + (.CLK(riffa_10_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[1]), + .CHNL_RX(chnl_rx[1]), + .CHNL_RX_ACK(chnl_rx_ack[1]), + .CHNL_RX_LAST(chnl_rx_last[1]), + .CHNL_RX_LEN(chnl_rx_len[32*1 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*1 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[1]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[1]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[1]), + .CHNL_TX(chnl_tx[1]), + .CHNL_TX_ACK(chnl_tx_ack[1]), + .CHNL_TX_LAST(chnl_tx_last[1]), + .CHNL_TX_LEN(chnl_tx_len[32*1 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*1 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[1]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[1])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_25mhz + (.CLK(riffa_25_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[2]), + .CHNL_RX(chnl_rx[2]), + .CHNL_RX_ACK(chnl_rx_ack[2]), + .CHNL_RX_LAST(chnl_rx_last[2]), + .CHNL_RX_LEN(chnl_rx_len[32*2 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*2 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[2]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[2]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[2]), + .CHNL_TX(chnl_tx[2]), + .CHNL_TX_ACK(chnl_tx_ack[2]), + .CHNL_TX_LAST(chnl_tx_last[2]), + .CHNL_TX_LEN(chnl_tx_len[32*2 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*2 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[2]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[2])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_50mhz + (.CLK(riffa_50_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[3]), + .CHNL_RX(chnl_rx[3]), + .CHNL_RX_ACK(chnl_rx_ack[3]), + .CHNL_RX_LAST(chnl_rx_last[3]), + .CHNL_RX_LEN(chnl_rx_len[32*3 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*3 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[3]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[3]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[3]), + .CHNL_TX(chnl_tx[3]), + .CHNL_TX_ACK(chnl_tx_ack[3]), + .CHNL_TX_LAST(chnl_tx_last[3]), + .CHNL_TX_LEN(chnl_tx_len[32*3 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*3 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[3]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[3])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_75mhz + (.CLK(riffa_75_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[4]), + .CHNL_RX(chnl_rx[4]), + .CHNL_RX_ACK(chnl_rx_ack[4]), + .CHNL_RX_LAST(chnl_rx_last[4]), + .CHNL_RX_LEN(chnl_rx_len[32*4 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*4 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[4]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[4]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[4]), + .CHNL_TX(chnl_tx[4]), + .CHNL_TX_ACK(chnl_tx_ack[4]), + .CHNL_TX_LAST(chnl_tx_last[4]), + .CHNL_TX_LEN(chnl_tx_len[32*4 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*4 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[4]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[4])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_100mhz + (.CLK(riffa_100_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[5]), + .CHNL_RX(chnl_rx[5]), + .CHNL_RX_ACK(chnl_rx_ack[5]), + .CHNL_RX_LAST(chnl_rx_last[5]), + .CHNL_RX_LEN(chnl_rx_len[32*5 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*5 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[5]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[5]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[5]), + .CHNL_TX(chnl_tx[5]), + .CHNL_TX_ACK(chnl_tx_ack[5]), + .CHNL_TX_LAST(chnl_tx_last[5]), + .CHNL_TX_LEN(chnl_tx_len[32*5 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*5 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[5]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[5])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_125mhz + (.CLK(riffa_125_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[6]), + .CHNL_RX(chnl_rx[6]), + .CHNL_RX_ACK(chnl_rx_ack[6]), + .CHNL_RX_LAST(chnl_rx_last[6]), + .CHNL_RX_LEN(chnl_rx_len[32*6 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*6 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[6]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[6]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[6]), + .CHNL_TX(chnl_tx[6]), + .CHNL_TX_ACK(chnl_tx_ack[6]), + .CHNL_TX_LAST(chnl_tx_last[6]), + .CHNL_TX_LEN(chnl_tx_len[32*6 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*6 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[6]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[6])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_150mhz + (.CLK(riffa_150_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[7]), + .CHNL_RX(chnl_rx[7]), + .CHNL_RX_ACK(chnl_rx_ack[7]), + .CHNL_RX_LAST(chnl_rx_last[7]), + .CHNL_RX_LEN(chnl_rx_len[32*7 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*7 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[7]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[7]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[7]), + .CHNL_TX(chnl_tx[7]), + .CHNL_TX_ACK(chnl_tx_ack[7]), + .CHNL_TX_LAST(chnl_tx_last[7]), + .CHNL_TX_LEN(chnl_tx_len[32*7 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*7 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[7]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[7])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_175mhz + (.CLK(riffa_175_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[8]), + .CHNL_RX(chnl_rx[8]), + .CHNL_RX_ACK(chnl_rx_ack[8]), + .CHNL_RX_LAST(chnl_rx_last[8]), + .CHNL_RX_LEN(chnl_rx_len[32*8 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*8 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[8]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[8]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[8]), + .CHNL_TX(chnl_tx[8]), + .CHNL_TX_ACK(chnl_tx_ack[8]), + .CHNL_TX_LAST(chnl_tx_last[8]), + .CHNL_TX_LEN(chnl_tx_len[32*8 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*8 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[8]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[8])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_200mhz + (.CLK(riffa_200_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[9]), + .CHNL_RX(chnl_rx[9]), + .CHNL_RX_ACK(chnl_rx_ack[9]), + .CHNL_RX_LAST(chnl_rx_last[9]), + .CHNL_RX_LEN(chnl_rx_len[32*9 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*9 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[9]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[9]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[9]), + .CHNL_TX(chnl_tx[9]), + .CHNL_TX_ACK(chnl_tx_ack[9]), + .CHNL_TX_LAST(chnl_tx_last[9]), + .CHNL_TX_LEN(chnl_tx_len[32*9 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*9 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[9]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[9])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_225mhz + (.CLK(riffa_225_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[10]), + .CHNL_RX(chnl_rx[10]), + .CHNL_RX_ACK(chnl_rx_ack[10]), + .CHNL_RX_LAST(chnl_rx_last[10]), + .CHNL_RX_LEN(chnl_rx_len[32*10 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*10 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[10]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[10]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[10]), + .CHNL_TX(chnl_tx[10]), + .CHNL_TX_ACK(chnl_tx_ack[10]), + .CHNL_TX_LAST(chnl_tx_last[10]), + .CHNL_TX_LEN(chnl_tx_len[32*10 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*10 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[10]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[10])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_250mhz + (.CLK(riffa_250_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[11]), + .CHNL_RX(chnl_rx[11]), + .CHNL_RX_ACK(chnl_rx_ack[11]), + .CHNL_RX_LAST(chnl_rx_last[11]), + .CHNL_RX_LEN(chnl_rx_len[32*11 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*11 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[11]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[11]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[11]), + .CHNL_TX(chnl_tx[11]), + .CHNL_TX_ACK(chnl_tx_ack[11]), + .CHNL_TX_LAST(chnl_tx_last[11]), + .CHNL_TX_LEN(chnl_tx_len[32*11 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*11 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[11]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[11])); + +endmodule +// Local Variables: +// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/") +// End: + diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/ip/PCIeGen1x8If64.xci b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/ip/PCIeGen1x8If64.xci new file mode 100644 index 0000000..260b04c --- /dev/null +++ b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/ip/PCIeGen1x8If64.xci @@ -0,0 +1,680 @@ + + + xilinx.com + xci + unknown + 1.0 + + + PCIeGen1x8If64 + + + FALSE + FALSE + FALSE + TRUE + 0x00000 + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + TRUE + FALSE + TRUE + FALSE + 16KB + 64 + 00 + FALSE + FALSE + FALSE + FALSE + TRUE + FALSE + FALSE + FALSE + NONE + 3 + 2.1 + FALSE + FALSE + FALSE + 0x000 + 0x000 + 0x00 + 0b00011 + 0b100 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0x80 + 0x058000 + 0x7018 + FALSE + FALSE + FALSE + FALSE + 00 + FALSE + FALSE + FALSE + 0b010 + 0x000 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x000 + 0b00000 + FALSE + 0x0 + 0 + TRUE + 0x000 + 0x00 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + 0xC0 + 0x000 + 0x90 + FALSE + FALSE + FALSE + FALSE + FALSE + 0x000 + 0x00000 + 0x00000 + 0x00000 + 0x00 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0x0000 + 0x000 + 0x0000 + 0x0 + 0x0000 + 0x0000 + 0x00000553 + 0x0000 + 0x0007 + 0x10EE + TRUE + FALSE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0x10EE + FALSE + FALSE + 0x000 + 0x000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0x80 + 0x058000 + 0x7011 + 0b010 + 0x000 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x000 + 0b00000 + FALSE + 0x0 + 0x00 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + 0x00 + 0x000 + 0x00 + FALSE + 0x000 + 0x00000 + 0x00000 + 0x00000 + 0x00 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0x0000 + 0x000 + 0x0000 + 0x0 + 0x0000 + 0x0001 + 0x00000553 + 0x0000 + 0x0007 + TRUE + FALSE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + FALSE + 1 + 8 + TRUE + FALSE + FALSE + 0 + FALSE + 0x00000000 + FALSE + 0x000 + 0x00000000 + 0x028 + 0x20 + 0x198 + 0x20 + FALSE + FALSE + FALSE + FALSE + FALSE + 4 + 0x000 + 0x80 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + "00000000" + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + "00000000" + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + "00000000" + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + "00000000" + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + "00000000" + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + "00000000" + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0 + 1 + 0 + 0 + 1 + Production + 1 + true + false + PCIeGen1x8If64 + false + false + 058000 + 7018 + false + false + false + 00_Not_Supported + false + false + NONE + true + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + false + false + false + false + 00 + 0 + N/A + 0000 + 00000553 + 0000 + 0007 + 10EE + false + false + false + 058000 + 7011 + NONE + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + 00 + 0 + 0 + N/A + 0001 + 00000553 + 0000 + 0007 + false + 2.5_GT/s + X8 + 100_MHz + Custom + false + false + false + false + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + DWORD_Aligned + No_ASPM + 250 + false + 2FFFF + false + 64_bit + false + false + true + false + true + false + PCI_Express_Endpoint_device + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + Advanced + X0Y1 + false + Extreme + false + true + false + false + true + false + Kilobytes + 1 + Memory + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + Simple_communication_controllers + 05 + 00 + 80 + 512_bytes + false + false + false + Kilobytes + 2 + false + true + false + false + false + false + true + false + Kilobytes + 2 + Memory + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + 0 + Generic_XT_compatible_serial_controller + false + false + true + false + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + Simple_communication_controllers + 05 + 00 + 80 + 512_bytes + false + false + false + Kilobytes + 2 + true + false + false + false + false + true + false + Kilobytes + 2 + Memory + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + Generic_XT_compatible_serial_controller + false + None + false + false + false + Production + None + true + false + 10EE + VC709 + virtex7 + xilinx.com:vc709:part0:1.5 + xc7vx690t + ffg1761 + VERILOG + + MIXED + -2 + C + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2015.4 + OUT_OF_CONTEXT + + + + diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/ip/clk_250MIn_1/clk_250MIn_1.xci b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/ip/clk_250MIn_1/clk_250MIn_1.xci new file mode 100644 index 0000000..e2c02a3 --- /dev/null +++ b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/ip/clk_250MIn_1/clk_250MIn_1.xci @@ -0,0 +1,562 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_250MIn_1 + + + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 40.0 + 100.0 + BUFG + 50.0 + 5.000 + 0.000 + 50.000 + 5 + 0.000 + 1 + BUFG + 50.0 + 10.000 + 0.000 + 50.000 + 10 + 0.000 + 1 + 1 + BUFG + 50.0 + 24.800 + 0.000 + 50.000 + 25 + 0.000 + 1 + 1 + BUFG + 50.0 + 51.667 + 0.000 + 50.000 + 50 + 0.000 + 1 + 1 + BUFG + 50.0 + 77.500 + 0.000 + 50.000 + 75 + 0.000 + 1 + 1 + BUFG + 50.0 + 103.333 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 1 + BUFG + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + riffa_5_clk + riffa_10_clk + riffa_25_clk + riffa_50_clk + riffa_75_clk + riffa_100_clk + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + dout + drdy + dwe + 0 + FDBK_AUTO + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_____________250____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + clk_locked + OPTIMIZED + 62.000 + 0.000 + FALSE + 4.0 + 10.0 + 124.000 + 0.500 + 0.000 + FALSE + 62 + 0.500 + 0.000 + FALSE + 25 + 0.500 + 0.000 + FALSE + 12 + 0.500 + 0.000 + FALSE + FALSE + 8 + 0.500 + 0.000 + FALSE + 6 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 25 + None + 0.010 + 0.010 + FALSE + 6 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + CLK_OUT1_____5.000______0.000______50.0______943.594____894.366 + CLK_OUT2____10.000______0.000______50.0______855.836____894.366 + CLK_OUT3____24.800______0.000______50.0______752.191____894.366 + CLK_OUT4____51.667______0.000______50.0______678.319____894.366 + CLK_OUT5____77.500______0.000______50.0______641.055____894.366 + CLK_OUT6___103.333______0.000______50.0______615.875____894.366 + no_CLK_OUT7_output + 0 + 0 + UNKNOWN + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + user_clk + MMCM + AUTO + 250 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 0 + clk_rst + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + clk_250MIn_1 + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 40.0 + 0.010 + 100.0 + 0.010 + BUFG + 943.594 + 894.366 + 50.000 + 5 + 0.000 + 1 + true + BUFG + 855.836 + 894.366 + 50.000 + 10 + 0.000 + 1 + true + BUFG + 752.191 + 894.366 + 50.000 + 25 + 0.000 + 1 + true + BUFG + 678.319 + 894.366 + 50.000 + 50 + 0.000 + 1 + true + BUFG + 641.055 + 894.366 + 50.000 + 75 + 0.000 + 1 + true + BUFG + 615.875 + 894.366 + 50.000 + 100.000 + 0.000 + 1 + true + BUFG + 0.0 + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + riffa_5_clk + false + riffa_10_clk + false + riffa_25_clk + false + riffa_50_clk + false + riffa_75_clk + false + riffa_100_clk + false + clk_out7 + false + CLK_VALID + auto + clk_250MIn_1 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + clk_locked + OPTIMIZED + 62.000 + 0.000 + false + 4.0 + 10.0 + 124.000 + 0.500 + 0.000 + false + 62 + 0.500 + 0.000 + false + 25 + 0.500 + 0.000 + false + 12 + 0.500 + 0.000 + false + false + 8 + 0.500 + 0.000 + false + 6 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 25 + None + 0.010 + 0.010 + false + 6 + false + false + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + user_clk + MMCM + mmcm_adv + 250 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + REL_PRIMARY + Custom + clk_rst + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + false + false + virtex7 + xilinx.com:vc709:part0:1.5 + xc7vx690t + ffg1761 + VERILOG + + MIXED + -2 + C + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2015.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/ip/clk_250MIn_2/clk_250MIn_2.xci b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/ip/clk_250MIn_2/clk_250MIn_2.xci new file mode 100644 index 0000000..eb17d6e --- /dev/null +++ b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/ip/clk_250MIn_2/clk_250MIn_2.xci @@ -0,0 +1,569 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_250MIn_2 + + + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 40.0 + 100.0 + BUFG + 50.0 + 250.000 + 0.000 + 50.000 + 250 + 0.000 + 1 + BUFG + 50.0 + 250.000 + 0.000 + 50.000 + 250 + 0.000 + 1 + 1 + BUFG + 50.0 + 250.000 + 0.000 + 50.000 + 250 + 0.000 + 1 + 1 + BUFG + 50.0 + 250.000 + 0.000 + 50.000 + 250 + 0.000 + 1 + 1 + BUFG + 50.0 + 250.000 + 0.000 + 50.000 + 250 + 0.000 + 1 + 1 + BUFG + 50.0 + 250.000 + 0.000 + 50.000 + 250 + 0.000 + 1 + 1 + BUFG + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + riffa_125_clk + riffa_150_clk + riffa_175_clk + riffa_200_clk + riffa_225_clk + riffa_250_clk + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + dout + drdy + dwe + 0 + FDBK_AUTO + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_____________250____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + clk_locked + OPTIMIZED + 4.000 + 0.000 + FALSE + 4.0 + 10.0 + 4.000 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + FALSE + 4 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.010 + 0.010 + FALSE + 6 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + CLK_OUT1___250.000______0.000______50.0_______89.528_____85.928 + CLK_OUT2___250.000______0.000______50.0_______89.528_____85.928 + CLK_OUT3___250.000______0.000______50.0_______89.528_____85.928 + CLK_OUT4___250.000______0.000______50.0_______89.528_____85.928 + CLK_OUT5___250.000______0.000______50.0_______89.528_____85.928 + CLK_OUT6___250.000______0.000______50.0_______89.528_____85.928 + no_CLK_OUT7_output + 0 + 0 + UNKNOWN + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + user_clk + MMCM + AUTO + 250 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 0 + clk_rst + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + clk_250MIn_2 + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 40.0 + 0.010 + 100.0 + 0.010 + BUFG + 89.528 + 85.928 + 50.000 + 250 + 0.000 + 1 + true + BUFG + 89.528 + 85.928 + 50.000 + 250 + 0.000 + 1 + true + BUFG + 89.528 + 85.928 + 50.000 + 250 + 0.000 + 1 + true + BUFG + 89.528 + 85.928 + 50.000 + 250 + 0.000 + 1 + true + BUFG + 89.528 + 85.928 + 50.000 + 250 + 0.000 + 1 + true + BUFG + 89.528 + 85.928 + 50.000 + 250 + 0.000 + 1 + true + BUFG + 0.0 + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + riffa_125_clk + false + riffa_150_clk + false + riffa_175_clk + false + riffa_200_clk + false + riffa_225_clk + false + riffa_250_clk + false + clk_out7 + false + CLK_VALID + auto + clk_250MIn_2 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + clk_locked + OPTIMIZED + 4.000 + 0.000 + false + 4.0 + 10.0 + 4.000 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + false + 4 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 6 + false + false + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + user_clk + MMCM + mmcm_adv + 250 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + REL_PRIMARY + Custom + clk_rst + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + false + false + false + false + false + false + false + true + false + false + false + false + false + false + true + false + false + false + false + false + virtex7 + xilinx.com:vc709:part0:1.5 + xc7vx690t + ffg1761 + VERILOG + + MIXED + -2 + C + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2015.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/prj/VC709_Gen1x8If64.xpr b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/prj/VC709_Gen1x8If64.xpr new file mode 100644 index 0000000..d366bc4 --- /dev/null +++ b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/prj/VC709_Gen1x8If64.xpr @@ -0,0 +1,879 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/Makefile b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/Makefile new file mode 100644 index 0000000..d760cff --- /dev/null +++ b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/Makefile @@ -0,0 +1,62 @@ +# ---------------------------------------------------------------------- +# Copyright (c) 2016, The Regents of the University of California All +# rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# +# * Neither the name of The Regents of the University of California +# nor the names of its contributors may be used to endorse or +# promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE +# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +# DAMAGE. +# ---------------------------------------------------------------------- +#----------------------------------------------------------------------- +# Filename: Makefile +# Version: 1.0 +# Description: Project-level makefile for building an example project +# Author: Dustin Richmond (@darichmond) +#----------------------------------------------------------------------- +# This make file expects the following variables to be set: +# RIFFA_HDL_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory. +# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to +# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory +WIDTH=128 +TYPE=ultrascale +CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))) +PROJECT=$(shell basename $(CURRENT_PATH)) + +ifndef RIFFA_HDL_PATH + RIFFA_HDL_PATH:=../../../riffa_hdl +endif +ifndef BOARD_PATH + BOARD_PATH:=.. +endif +ifndef JOBS + JOBS=1 +endif +include $(RIFFA_HDL_PATH)/riffa.mk +include $(BOARD_PATH)/board.mk + +PROJECT_IP+=ip/PCIeGen2x8If128.xci diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/bit/VC709_Gen2x8If128.bit b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/bit/VC709_Gen2x8If128.bit new file mode 100644 index 0000000..fe86802 Binary files /dev/null and b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/bit/VC709_Gen2x8If128.bit differ diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/constr/VC709_Gen2x8If128.xdc b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/constr/VC709_Gen2x8If128.xdc new file mode 100644 index 0000000..e1109d2 --- /dev/null +++ b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/constr/VC709_Gen2x8If128.xdc @@ -0,0 +1,152 @@ +# ---------------------------------------------------------------------- +# Copyright (c) 2016, The Regents of the University of California All +# rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# +# * Neither the name of The Regents of the University of California +# nor the names of its contributors may be used to endorse or +# promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE +# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +# DAMAGE. +# ---------------------------------------------------------------------- +#---------------------------------------------------------------------------- +# Filename: VC709_Top.xdc +# Version: 1.00.a +# Verilog Standard: Verilog-2001 +# Description: Xilinx Design Constraints for the VC709 board. +# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin +# +# Author: Dustin Richmond (@darichmond) +#----------------------------------------------------------------------------- +# +######################################################################################################################### +# User Constraints +######################################################################################################################### + +############################################################################### +# User Time Names / User Time Groups / Time Specs +############################################################################### + +############################################################################### +# User Physical Constraints +############################################################################### + +# +# LED Status Indicators for Example Design. +# LED 0-2 should be all ON if link is up and functioning correctly +# LED 3 should be blinking if user application is receiving valid clock +# + +#System Reset, User Reset, User Link Up, User Clk Heartbeat +set_property PACKAGE_PIN AM39 [get_ports {LED[0]}] +set_property PACKAGE_PIN AN39 [get_ports {LED[1]}] +set_property PACKAGE_PIN AR37 [get_ports {LED[2]}] +set_property PACKAGE_PIN AT37 [get_ports {LED[3]}] +set_property PACKAGE_PIN AR35 [get_ports {LED[4]}] +set_property PACKAGE_PIN AP41 [get_ports {LED[5]}] +set_property PACKAGE_PIN AP42 [get_ports {LED[6]}] +set_property PACKAGE_PIN AU39 [get_ports {LED[7]}] + +set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {LED[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {LED[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {LED[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {LED[7]}] + +set_false_path -to [get_ports -filter NAME=~LED*] + +######################################################################################################################### +# End User Constraints +######################################################################################################################### +# +# +# +######################################################################################################################### +# PCIE Core Constraints +######################################################################################################################### + +# +# SYS reset (input) signal. The sys_reset_n signal should be +# obtained from the PCI Express interface if possible. For +# slot based form factors, a system reset signal is usually +# present on the connector. For cable based form factors, a +# system reset signal may not be available. In this case, the +# system reset signal must be generated locally by some form of +# supervisory circuit. You may change the IOSTANDARD and LOC +# to suit your requirements and VCCO voltage banking rules. +# Some 7 series devices do not have 3.3 V I/Os available. +# Therefore the appropriate level shift is required to operate +# with these devices that contain only 1.8 V banks. +# + +set_property PACKAGE_PIN AV35 [get_ports PCIE_RESET_N] +set_property IOSTANDARD LVCMOS18 [get_ports PCIE_RESET_N] +set_property PULLUP true [get_ports PCIE_RESET_N] + +# +# +# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n +# signals are the PCI Express reference clock. Virtex-7 GT +# Transceiver architecture requires the use of a dedicated clock +# resources (FPGA input pins) associated with each GT Transceiver. +# To use these pins an IBUFDS primitive (refclk_ibuf) is +# instantiated in user's design. +# Please refer to the Virtex-7 GT Transceiver User Guide +# (UG) for guidelines regarding clock resource selection. +# +set_property LOC IBUFDS_GTE2_X1Y11 [get_cells refclk_ibuf] + +############################################################################### +# Timing Constraints +############################################################################### +create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O] + +############################################################################### +# Physical Constraints +############################################################################### + +set_false_path -from [get_ports PCIE_RESET_N] +############################################################################### +# End +############################################################################### + + +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] -group [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT1]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT1]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT2]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT3]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT4]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT5]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen_2/inst/mmcm_adv_inst/CLKOUT0]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen_2/inst/mmcm_adv_inst/CLKOUT1]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen_2/inst/mmcm_adv_inst/CLKOUT2]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen_2/inst/mmcm_adv_inst/CLKOUT3]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen_2/inst/mmcm_adv_inst/CLKOUT4]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins clkgen_2/inst/mmcm_adv_inst/CLKOUT5]] -group [get_clocks -of_objects [get_pins pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT2]] diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/hdl/VC709_Gen2x8If128.v b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/hdl/VC709_Gen2x8If128.v new file mode 100644 index 0000000..c7c6741 --- /dev/null +++ b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/hdl/VC709_Gen2x8If128.v @@ -0,0 +1,792 @@ +// ---------------------------------------------------------------------- +// Copyright (c) 2016, The Regents of the University of California All +// rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above +// copyright notice, this list of conditions and the following +// disclaimer in the documentation and/or other materials provided +// with the distribution. +// +// * Neither the name of The Regents of the University of California +// nor the names of its contributors may be used to endorse or +// promote products derived from this software without specific +// prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE +// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +// DAMAGE. +// ---------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// Filename: VC709_Gen2x8If128.v +// Version: 1.00.a +// Verilog Standard: Verilog-2001 +// Description: Top level module for RIFFA 2.2 reference design for the +// the Xilinx VC709 Development Board. +// Author: Dustin Richmond (@darichmond) +//----------------------------------------------------------------------------- +`include "functions.vh" +`include "riffa.vh" +`include "ultrascale.vh" +`timescale 1ps / 1ps +module VC709_Gen2x8If128 + #(// Number of RIFFA Channels + parameter C_NUM_CHNL = 12, + // Number of PCIe Lanes + parameter C_NUM_LANES = 8, + // Settings from Vivado IP Generator + parameter C_PCI_DATA_WIDTH = 128, + parameter C_MAX_PAYLOAD_BYTES = 256, + parameter C_LOG_NUM_TAGS = 6 + ) + (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP, + output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN, + input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP, + input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN, + + output [7:0] LED, + input PCIE_REFCLK_P, + input PCIE_REFCLK_N, + input PCIE_RESET_N + ); + + // Clocks, etc + wire user_lnk_up; + wire user_clk; + wire user_reset; + wire pcie_refclk; + wire pcie_reset_n; + wire riffa_5_clk; + wire riffa_10_clk; + wire riffa_25_clk; + wire riffa_50_clk; + wire riffa_75_clk; + wire riffa_100_clk; + wire riffa_125_clk; + wire riffa_150_clk; + wire riffa_175_clk; + wire riffa_200_clk; + wire riffa_225_clk; + wire riffa_250_clk; + + // Interface: RQ (TXC) + wire s_axis_rq_tlast; + wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata; + wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser; + wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep; + wire s_axis_rq_tready; + wire s_axis_rq_tvalid; + // Interface: RC (RXC) + wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata; + wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser; + wire m_axis_rc_tlast; + wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep; + wire m_axis_rc_tvalid; + wire m_axis_rc_tready; + // Interface: CQ (RXR) + wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata; + wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser; + wire m_axis_cq_tlast; + wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep; + wire m_axis_cq_tvalid; + wire m_axis_cq_tready; + // Interface: CC (TXC) + wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata; + wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser; + wire s_axis_cc_tlast; + wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep; + wire s_axis_cc_tvalid; + wire s_axis_cc_tready; + + // Configuration (CFG) Interface + wire [3:0] pcie_rq_seq_num; + wire pcie_rq_seq_num_vld; + wire [5:0] pcie_rq_tag; + wire pcie_rq_tag_vld; + wire pcie_cq_np_req; + wire [5:0] pcie_cq_np_req_count; + + wire cfg_phy_link_down; + wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH + wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE + wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD + wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST + wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE + wire [5:0] cfg_function_power_state; // Ignorable but not removable + wire [11:0] cfg_vf_status; // Ignorable but not removable + wire [17:0] cfg_vf_power_state; // Ignorable but not removable + wire [1:0] cfg_link_power_state; // Ignorable but not removable + + // Error Reporting Interface + wire cfg_err_cor_out; + wire cfg_err_nonfatal_out; + wire cfg_err_fatal_out; + + wire cfg_ltr_enable; + wire [5:0] cfg_ltssm_state;// TODO: Connect to LED's + wire [1:0] cfg_rcb_status; + wire [1:0] cfg_dpa_substate_change; + wire [1:0] cfg_obff_enable; + wire cfg_pl_status_change; + + wire [1:0] cfg_tph_requester_enable; + wire [5:0] cfg_tph_st_mode; + wire [5:0] cfg_vf_tph_requester_enable; + wire [17:0] cfg_vf_tph_st_mode; + wire [7:0] cfg_fc_ph; + wire [11:0] cfg_fc_pd; + wire [7:0] cfg_fc_nph; + wire [11:0] cfg_fc_npd; + wire [7:0] cfg_fc_cplh; + wire [11:0] cfg_fc_cpld; + wire [2:0] cfg_fc_sel; + + // Interrupt Interface Signals + wire [3:0] cfg_interrupt_int; + wire [1:0] cfg_interrupt_pending; + wire cfg_interrupt_sent; + wire [1:0] cfg_interrupt_msi_enable; + wire [5:0] cfg_interrupt_msi_vf_enable; + wire [5:0] cfg_interrupt_msi_mmenable; + wire cfg_interrupt_msi_mask_update; + wire [31:0] cfg_interrupt_msi_data; + wire [3:0] cfg_interrupt_msi_select; + wire [31:0] cfg_interrupt_msi_int; + wire [63:0] cfg_interrupt_msi_pending_status; + wire cfg_interrupt_msi_sent; + wire cfg_interrupt_msi_fail; + wire [2:0] cfg_interrupt_msi_attr; + wire cfg_interrupt_msi_tph_present; + wire [1:0] cfg_interrupt_msi_tph_type; + wire [8:0] cfg_interrupt_msi_tph_st_tag; + wire [2:0] cfg_interrupt_msi_function_number; + + wire rst_out; + wire [C_NUM_CHNL-1:0] chnl_rx_clk; + wire [C_NUM_CHNL-1:0] chnl_rx; + wire [C_NUM_CHNL-1:0] chnl_rx_ack; + wire [C_NUM_CHNL-1:0] chnl_rx_last; + wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; + wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; + wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data; + wire [C_NUM_CHNL-1:0] chnl_rx_data_valid; + wire [C_NUM_CHNL-1:0] chnl_rx_data_ren; + + wire [C_NUM_CHNL-1:0] chnl_tx_clk; + wire [C_NUM_CHNL-1:0] chnl_tx; + wire [C_NUM_CHNL-1:0] chnl_tx_ack; + wire [C_NUM_CHNL-1:0] chnl_tx_last; + wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; + wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; + wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data; + wire [C_NUM_CHNL-1:0] chnl_tx_data_valid; + wire [C_NUM_CHNL-1:0] chnl_tx_data_ren; + + genvar chnl; + + IBUF + #() + pci_reset_n_ibuf + (.O(pcie_reset_n), + .I(PCIE_RESET_N)); + + IBUFDS_GTE2 + #() + refclk_ibuf + (.O(pcie_refclk), + .ODIV2(), + .I(PCIE_REFCLK_P), + .CEB(1'b0), + .IB(PCIE_REFCLK_N)); + + OBUF + #() + led_0_obuf + (.O(LED[0]), + .I(cfg_ltssm_state[0])); + OBUF + #() + led_1_obuf + (.O(LED[1]), + .I(cfg_ltssm_state[1])); + OBUF + #() + led_2_obuf + (.O(LED[2]), + .I(cfg_ltssm_state[2])); + OBUF + #() + led_3_obuf + (.O(LED[3]), + .I(cfg_ltssm_state[3])); + OBUF + #() + led_4_obuf + (.O(LED[4]), + .I(cfg_ltssm_state[4])); + OBUF + #() + led_5_obuf + (.O(LED[5]), + .I(cfg_ltssm_state[5])); + OBUF + #() + led_6_obuf + (.O(LED[6]), + .I(pcie_reset_n)); + OBUF + #() + led_7_obuf + (.O(LED[7]), + .I(rst_out)); + + // Core Top Level Wrapper + PCIeGen2x8If128 + #() + pcie3_7x_0_i + (//--------------------------------------------------------------------- + // PCI Express (pci_exp) Interface + //--------------------------------------------------------------------- + .pci_exp_txn ( PCI_EXP_TXN ), + .pci_exp_txp ( PCI_EXP_TXP ), + .pci_exp_rxn ( PCI_EXP_RXN ), + .pci_exp_rxp ( PCI_EXP_RXP ), + + //--------------------------------------------------------------------- + // AXI Interface + //--------------------------------------------------------------------- + .user_clk ( user_clk ), + .user_reset ( user_reset ), + .user_lnk_up ( user_lnk_up ), + .user_app_rdy ( ), + + .s_axis_rq_tlast ( s_axis_rq_tlast ), + .s_axis_rq_tdata ( s_axis_rq_tdata ), + .s_axis_rq_tuser ( s_axis_rq_tuser ), + .s_axis_rq_tkeep ( s_axis_rq_tkeep ), + .s_axis_rq_tready ( s_axis_rq_tready ), + .s_axis_rq_tvalid ( s_axis_rq_tvalid ), + + .m_axis_rc_tdata ( m_axis_rc_tdata ), + .m_axis_rc_tuser ( m_axis_rc_tuser ), + .m_axis_rc_tlast ( m_axis_rc_tlast ), + .m_axis_rc_tkeep ( m_axis_rc_tkeep ), + .m_axis_rc_tvalid ( m_axis_rc_tvalid ), + .m_axis_rc_tready ( {22{m_axis_rc_tready}} ), + + .m_axis_cq_tdata ( m_axis_cq_tdata ), + .m_axis_cq_tuser ( m_axis_cq_tuser ), + .m_axis_cq_tlast ( m_axis_cq_tlast ), + .m_axis_cq_tkeep ( m_axis_cq_tkeep ), + .m_axis_cq_tvalid ( m_axis_cq_tvalid ), + .m_axis_cq_tready ( {22{m_axis_cq_tready}} ), + + .s_axis_cc_tdata ( s_axis_cc_tdata ), + .s_axis_cc_tuser ( s_axis_cc_tuser ), + .s_axis_cc_tlast ( s_axis_cc_tlast ), + .s_axis_cc_tkeep ( s_axis_cc_tkeep ), + .s_axis_cc_tvalid ( s_axis_cc_tvalid ), + .s_axis_cc_tready ( s_axis_cc_tready ), + + //--------------------------------------------------------------------- + // Configuration (CFG) Interface + //--------------------------------------------------------------------- + .pcie_rq_seq_num ( pcie_rq_seq_num ), + .pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ), + .pcie_rq_tag ( pcie_rq_tag ), + .pcie_rq_tag_vld ( pcie_rq_tag_vld ), + .pcie_cq_np_req ( pcie_cq_np_req ), + .pcie_cq_np_req_count ( pcie_cq_np_req_count ), + .cfg_phy_link_down ( cfg_phy_link_down ), + .cfg_phy_link_status ( cfg_phy_link_status), + .cfg_negotiated_width ( cfg_negotiated_width ), + .cfg_current_speed ( cfg_current_speed ), + .cfg_max_payload ( cfg_max_payload ), + .cfg_max_read_req ( cfg_max_read_req ), + .cfg_function_status ( cfg_function_status ), + .cfg_function_power_state ( cfg_function_power_state ), + .cfg_vf_status ( cfg_vf_status ), + .cfg_vf_power_state ( cfg_vf_power_state ), + .cfg_link_power_state ( cfg_link_power_state ), + // Error Reporting Interface + .cfg_err_cor_out ( cfg_err_cor_out ), + .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), + .cfg_err_fatal_out ( cfg_err_fatal_out ), + .cfg_ltr_enable ( cfg_ltr_enable ), + .cfg_ltssm_state ( cfg_ltssm_state ), + .cfg_rcb_status ( cfg_rcb_status ), + .cfg_dpa_substate_change ( cfg_dpa_substate_change ), + .cfg_obff_enable ( cfg_obff_enable ), + .cfg_pl_status_change ( cfg_pl_status_change ), + .cfg_tph_requester_enable ( cfg_tph_requester_enable ), + .cfg_tph_st_mode ( cfg_tph_st_mode ), + .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), + .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), + .cfg_fc_ph ( cfg_fc_ph ), + .cfg_fc_pd ( cfg_fc_pd ), + .cfg_fc_nph ( cfg_fc_nph ), + .cfg_fc_npd ( cfg_fc_npd ), + .cfg_fc_cplh ( cfg_fc_cplh ), + .cfg_fc_cpld ( cfg_fc_cpld ), + .cfg_fc_sel ( cfg_fc_sel ), + //--------------------------------------------------------------------- + // EP Only + //--------------------------------------------------------------------- + // Interrupt Interface Signals + .cfg_interrupt_int ( cfg_interrupt_int ), + .cfg_interrupt_pending ( cfg_interrupt_pending ), + .cfg_interrupt_sent ( cfg_interrupt_sent ), + .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ), + .cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ), + .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), + .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), + .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), + .cfg_interrupt_msi_select ( cfg_interrupt_msi_select ), + .cfg_interrupt_msi_int ( cfg_interrupt_msi_int ), + .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ), + .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), + .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), + .cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ), + .cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ), + .cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ), + .cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ), + .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ), + + //--------------------------------------------------------------------- + // System(SYS) Interface + //--------------------------------------------------------------------- + .sys_clk (pcie_refclk), + .sys_reset (~pcie_reset_n)); + + riffa_wrapper_vc709 + #(/*AUTOINSTPARAM*/ + // Parameters + .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), + .C_NUM_CHNL (C_NUM_CHNL), + .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), + .C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES)) + riffa + (// Outputs + .M_AXIS_CQ_TREADY (m_axis_cq_tready), + .M_AXIS_RC_TREADY (m_axis_rc_tready), + .S_AXIS_CC_TVALID (s_axis_cc_tvalid), + .S_AXIS_CC_TLAST (s_axis_cc_tlast), + .S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]), + .S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), + .S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]), + .S_AXIS_RQ_TVALID (s_axis_rq_tvalid), + .S_AXIS_RQ_TLAST (s_axis_rq_tlast), + .S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]), + .S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), + .S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]), + .USER_CLK (user_clk), + .USER_RESET (user_reset), + .CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]), + .CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]), + .CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]), + .CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]), + .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]), + .CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]), + .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present), + .CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]), + .CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]), + .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]), + .CFG_FC_SEL (cfg_fc_sel[2:0]), + .PCIE_CQ_NP_REQ (pcie_cq_np_req), + .RST_OUT (rst_out), + .CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]), + .CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]), + .CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), + .CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), + .CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), + .CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]), + .CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]), + .CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]), + // Inputs + .M_AXIS_CQ_TVALID (m_axis_cq_tvalid), + .M_AXIS_CQ_TLAST (m_axis_cq_tlast), + .M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]), + .M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), + .M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]), + .M_AXIS_RC_TVALID (m_axis_rc_tvalid), + .M_AXIS_RC_TLAST (m_axis_rc_tlast), + .M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]), + .M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), + .M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]), + .S_AXIS_CC_TREADY (s_axis_cc_tready), + .S_AXIS_RQ_TREADY (s_axis_rq_tready), + .CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]), + .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update), + .CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]), + .CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent), + .CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail), + .CFG_FC_CPLH (cfg_fc_cplh[7:0]), + .CFG_FC_CPLD (cfg_fc_cpld[11:0]), + .CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]), + .CFG_CURRENT_SPEED (cfg_current_speed[2:0]), + .CFG_MAX_PAYLOAD (cfg_max_payload[2:0]), + .CFG_MAX_READ_REQ (cfg_max_read_req[2:0]), + .CFG_FUNCTION_STATUS (cfg_function_status[7:0]), + .CFG_RCB_STATUS (cfg_rcb_status[1:0]), + .CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]), + .CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]), + .CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]), + .CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]), + .CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]), + .CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]), + .CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), + .CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), + .CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), + .CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])); + + clk_250MIn_1 + clkgen + (.user_clk(user_clk), + .riffa_5_clk(riffa_5_clk), + .riffa_10_clk(riffa_10_clk), + .riffa_25_clk(riffa_25_clk), + .riffa_50_clk(riffa_50_clk), + .riffa_75_clk(riffa_75_clk), + .riffa_100_clk(riffa_100_clk)); + clk_250MIn_2 + clkgen_2 + (.user_clk(user_clk), + .riffa_125_clk(riffa_125_clk), + .riffa_150_clk(riffa_150_clk), + .riffa_175_clk(riffa_175_clk), + .riffa_200_clk(riffa_200_clk), + .riffa_225_clk(riffa_225_clk), + .riffa_250_clk(riffa_250_clk)); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_5mhz + (.CLK(riffa_5_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[0]), + .CHNL_RX(chnl_rx[0]), + .CHNL_RX_ACK(chnl_rx_ack[0]), + .CHNL_RX_LAST(chnl_rx_last[0]), + .CHNL_RX_LEN(chnl_rx_len[32*0 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*0 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[0]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[0]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[0]), + .CHNL_TX(chnl_tx[0]), + .CHNL_TX_ACK(chnl_tx_ack[0]), + .CHNL_TX_LAST(chnl_tx_last[0]), + .CHNL_TX_LEN(chnl_tx_len[32*0 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*0 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[0]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[0])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_10mhz + (.CLK(riffa_10_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[1]), + .CHNL_RX(chnl_rx[1]), + .CHNL_RX_ACK(chnl_rx_ack[1]), + .CHNL_RX_LAST(chnl_rx_last[1]), + .CHNL_RX_LEN(chnl_rx_len[32*1 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*1 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[1]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[1]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[1]), + .CHNL_TX(chnl_tx[1]), + .CHNL_TX_ACK(chnl_tx_ack[1]), + .CHNL_TX_LAST(chnl_tx_last[1]), + .CHNL_TX_LEN(chnl_tx_len[32*1 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*1 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[1]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[1])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_25mhz + (.CLK(riffa_25_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[2]), + .CHNL_RX(chnl_rx[2]), + .CHNL_RX_ACK(chnl_rx_ack[2]), + .CHNL_RX_LAST(chnl_rx_last[2]), + .CHNL_RX_LEN(chnl_rx_len[32*2 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*2 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[2]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[2]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[2]), + .CHNL_TX(chnl_tx[2]), + .CHNL_TX_ACK(chnl_tx_ack[2]), + .CHNL_TX_LAST(chnl_tx_last[2]), + .CHNL_TX_LEN(chnl_tx_len[32*2 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*2 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[2]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[2])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_50mhz + (.CLK(riffa_50_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[3]), + .CHNL_RX(chnl_rx[3]), + .CHNL_RX_ACK(chnl_rx_ack[3]), + .CHNL_RX_LAST(chnl_rx_last[3]), + .CHNL_RX_LEN(chnl_rx_len[32*3 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*3 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[3]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[3]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[3]), + .CHNL_TX(chnl_tx[3]), + .CHNL_TX_ACK(chnl_tx_ack[3]), + .CHNL_TX_LAST(chnl_tx_last[3]), + .CHNL_TX_LEN(chnl_tx_len[32*3 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*3 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[3]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[3])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_75mhz + (.CLK(riffa_75_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[4]), + .CHNL_RX(chnl_rx[4]), + .CHNL_RX_ACK(chnl_rx_ack[4]), + .CHNL_RX_LAST(chnl_rx_last[4]), + .CHNL_RX_LEN(chnl_rx_len[32*4 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*4 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[4]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[4]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[4]), + .CHNL_TX(chnl_tx[4]), + .CHNL_TX_ACK(chnl_tx_ack[4]), + .CHNL_TX_LAST(chnl_tx_last[4]), + .CHNL_TX_LEN(chnl_tx_len[32*4 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*4 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[4]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[4])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_100mhz + (.CLK(riffa_100_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[5]), + .CHNL_RX(chnl_rx[5]), + .CHNL_RX_ACK(chnl_rx_ack[5]), + .CHNL_RX_LAST(chnl_rx_last[5]), + .CHNL_RX_LEN(chnl_rx_len[32*5 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*5 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[5]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[5]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[5]), + .CHNL_TX(chnl_tx[5]), + .CHNL_TX_ACK(chnl_tx_ack[5]), + .CHNL_TX_LAST(chnl_tx_last[5]), + .CHNL_TX_LEN(chnl_tx_len[32*5 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*5 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[5]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[5])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_125mhz + (.CLK(riffa_125_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[6]), + .CHNL_RX(chnl_rx[6]), + .CHNL_RX_ACK(chnl_rx_ack[6]), + .CHNL_RX_LAST(chnl_rx_last[6]), + .CHNL_RX_LEN(chnl_rx_len[32*6 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*6 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[6]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[6]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[6]), + .CHNL_TX(chnl_tx[6]), + .CHNL_TX_ACK(chnl_tx_ack[6]), + .CHNL_TX_LAST(chnl_tx_last[6]), + .CHNL_TX_LEN(chnl_tx_len[32*6 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*6 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[6]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[6])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_150mhz + (.CLK(riffa_150_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[7]), + .CHNL_RX(chnl_rx[7]), + .CHNL_RX_ACK(chnl_rx_ack[7]), + .CHNL_RX_LAST(chnl_rx_last[7]), + .CHNL_RX_LEN(chnl_rx_len[32*7 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*7 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[7]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[7]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[7]), + .CHNL_TX(chnl_tx[7]), + .CHNL_TX_ACK(chnl_tx_ack[7]), + .CHNL_TX_LAST(chnl_tx_last[7]), + .CHNL_TX_LEN(chnl_tx_len[32*7 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*7 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[7]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[7])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_175mhz + (.CLK(riffa_175_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[8]), + .CHNL_RX(chnl_rx[8]), + .CHNL_RX_ACK(chnl_rx_ack[8]), + .CHNL_RX_LAST(chnl_rx_last[8]), + .CHNL_RX_LEN(chnl_rx_len[32*8 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*8 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[8]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[8]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[8]), + .CHNL_TX(chnl_tx[8]), + .CHNL_TX_ACK(chnl_tx_ack[8]), + .CHNL_TX_LAST(chnl_tx_last[8]), + .CHNL_TX_LEN(chnl_tx_len[32*8 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*8 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[8]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[8])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_200mhz + (.CLK(riffa_200_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[9]), + .CHNL_RX(chnl_rx[9]), + .CHNL_RX_ACK(chnl_rx_ack[9]), + .CHNL_RX_LAST(chnl_rx_last[9]), + .CHNL_RX_LEN(chnl_rx_len[32*9 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*9 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[9]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[9]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[9]), + .CHNL_TX(chnl_tx[9]), + .CHNL_TX_ACK(chnl_tx_ack[9]), + .CHNL_TX_LAST(chnl_tx_last[9]), + .CHNL_TX_LEN(chnl_tx_len[32*9 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*9 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[9]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[9])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_225mhz + (.CLK(riffa_225_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[10]), + .CHNL_RX(chnl_rx[10]), + .CHNL_RX_ACK(chnl_rx_ack[10]), + .CHNL_RX_LAST(chnl_rx_last[10]), + .CHNL_RX_LEN(chnl_rx_len[32*10 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*10 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[10]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[10]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[10]), + .CHNL_TX(chnl_tx[10]), + .CHNL_TX_ACK(chnl_tx_ack[10]), + .CHNL_TX_LAST(chnl_tx_last[10]), + .CHNL_TX_LEN(chnl_tx_len[32*10 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*10 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[10]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[10])); + + chnl_tester + #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) + chnl_tester_250mhz + (.CLK(riffa_250_clk), + .RST(rst_out), // riffa_reset includes riffa_endpoint resets + // Rx interface + .CHNL_RX_CLK(chnl_rx_clk[11]), + .CHNL_RX(chnl_rx[11]), + .CHNL_RX_ACK(chnl_rx_ack[11]), + .CHNL_RX_LAST(chnl_rx_last[11]), + .CHNL_RX_LEN(chnl_rx_len[32*11 +:32]), + .CHNL_RX_OFF(chnl_rx_off[31*11 +:31]), + .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]), + .CHNL_RX_DATA_VALID(chnl_rx_data_valid[11]), + .CHNL_RX_DATA_REN(chnl_rx_data_ren[11]), + // Tx interface + .CHNL_TX_CLK(chnl_tx_clk[11]), + .CHNL_TX(chnl_tx[11]), + .CHNL_TX_ACK(chnl_tx_ack[11]), + .CHNL_TX_LAST(chnl_tx_last[11]), + .CHNL_TX_LEN(chnl_tx_len[32*11 +:32]), + .CHNL_TX_OFF(chnl_tx_off[31*11 +:31]), + .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]), + .CHNL_TX_DATA_VALID(chnl_tx_data_valid[11]), + .CHNL_TX_DATA_REN(chnl_tx_data_ren[11])); + +endmodule +// Local Variables: +// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/") +// End: + diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/PCIeGen2x8If128.xci b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/PCIeGen2x8If128.xci new file mode 100644 index 0000000..6322bb5 --- /dev/null +++ b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/PCIeGen2x8If128.xci @@ -0,0 +1,680 @@ + + + xilinx.com + xci + unknown + 1.0 + + + PCIeGen2x8If128 + + + FALSE + FALSE + FALSE + TRUE + 0x00000 + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + TRUE + FALSE + TRUE + FALSE + 16KB + 128 + 00 + FALSE + FALSE + FALSE + FALSE + TRUE + FALSE + FALSE + FALSE + NONE + 3 + 2.1 + FALSE + FALSE + FALSE + 0x000 + 0x000 + 0x00 + 0b00011 + 0b100 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0x80 + 0x058000 + 0x7028 + FALSE + FALSE + FALSE + FALSE + 00 + FALSE + TRUE + FALSE + 0b010 + 0x000 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x000 + 0b00000 + FALSE + 0x0 + 0 + TRUE + 0x000 + 0x00 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + 0xC0 + 0x000 + 0x90 + FALSE + FALSE + FALSE + FALSE + FALSE + 0x000 + 0x00000 + 0x00000 + 0x00000 + 0x00 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0x0000 + 0x000 + 0x0000 + 0x0 + 0x0000 + 0x0000 + 0x00000553 + 0x0000 + 0x0007 + 0x10EE + TRUE + FALSE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0x10EE + FALSE + FALSE + 0x000 + 0x000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0x80 + 0x058000 + 0x7011 + 0b010 + 0x000 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x000 + 0b00000 + FALSE + 0x0 + 0x00 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + 0x00 + 0x000 + 0x00 + FALSE + 0x000 + 0x00000 + 0x00000 + 0x00000 + 0x00 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0b00000 + 0b000 + 0x0000 + 0x000 + 0x0000 + 0x0 + 0x0000 + 0x0001 + 0x00000553 + 0x0000 + 0x0007 + TRUE + FALSE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + FALSE + 2 + 8 + TRUE + FALSE + FALSE + 0 + FALSE + 0x00000000 + FALSE + 0x000 + 0x00000000 + 0x028 + 0x20 + 0x198 + 0x20 + FALSE + FALSE + FALSE + FALSE + FALSE + 4 + 0x000 + 0x80 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + "00000000" + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + "00000000" + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + "00000000" + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + "00000000" + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + "00000000" + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + "00000000" + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0 + 1 + 0 + 0 + 1 + Production + 1 + true + false + PCIeGen2x8If128 + false + false + 058000 + 7028 + false + false + false + 00_Not_Supported + false + false + NONE + true + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + false + false + false + false + 00 + 0 + N/A + 0000 + 00000553 + 0000 + 0007 + 10EE + false + false + false + 058000 + 7011 + NONE + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + 00 + 0 + 0 + N/A + 0001 + 00000553 + 0000 + 0007 + false + 5.0_GT/s + X8 + 100_MHz + Custom + false + false + false + false + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + DWORD_Aligned + No_ASPM + 250 + false + 2FFFF + false + 128_bit + false + false + true + false + true + false + PCI_Express_Endpoint_device + false + false + false + false + false + false + false + false + false + false + true + false + true + false + false + Advanced + X0Y1 + false + Extreme + false + true + false + false + true + false + Kilobytes + 1 + Memory + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + Simple_communication_controllers + 05 + 00 + 80 + 512_bytes + false + false + false + Kilobytes + 2 + false + true + false + false + false + false + true + false + Kilobytes + 2 + Memory + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + 0 + Generic_XT_compatible_serial_controller + false + false + true + false + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + Simple_communication_controllers + 05 + 00 + 80 + 512_bytes + false + false + false + Kilobytes + 2 + true + false + false + false + false + true + false + Kilobytes + 2 + Memory + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + Generic_XT_compatible_serial_controller + false + None + false + false + false + Production + None + true + false + 10EE + VC709 + virtex7 + xilinx.com:vc709:part0:1.5 + xc7vx690t + ffg1761 + VERILOG + + MIXED + -2 + C + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2015.4 + OUT_OF_CONTEXT + + + + diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/clk_250MIn_1/clk_250MIn_1.xci b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/clk_250MIn_1/clk_250MIn_1.xci new file mode 100644 index 0000000..e2c02a3 --- /dev/null +++ b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/clk_250MIn_1/clk_250MIn_1.xci @@ -0,0 +1,562 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_250MIn_1 + + + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 40.0 + 100.0 + BUFG + 50.0 + 5.000 + 0.000 + 50.000 + 5 + 0.000 + 1 + BUFG + 50.0 + 10.000 + 0.000 + 50.000 + 10 + 0.000 + 1 + 1 + BUFG + 50.0 + 24.800 + 0.000 + 50.000 + 25 + 0.000 + 1 + 1 + BUFG + 50.0 + 51.667 + 0.000 + 50.000 + 50 + 0.000 + 1 + 1 + BUFG + 50.0 + 77.500 + 0.000 + 50.000 + 75 + 0.000 + 1 + 1 + BUFG + 50.0 + 103.333 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 1 + BUFG + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + riffa_5_clk + riffa_10_clk + riffa_25_clk + riffa_50_clk + riffa_75_clk + riffa_100_clk + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + dout + drdy + dwe + 0 + FDBK_AUTO + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_____________250____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + clk_locked + OPTIMIZED + 62.000 + 0.000 + FALSE + 4.0 + 10.0 + 124.000 + 0.500 + 0.000 + FALSE + 62 + 0.500 + 0.000 + FALSE + 25 + 0.500 + 0.000 + FALSE + 12 + 0.500 + 0.000 + FALSE + FALSE + 8 + 0.500 + 0.000 + FALSE + 6 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 25 + None + 0.010 + 0.010 + FALSE + 6 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + CLK_OUT1_____5.000______0.000______50.0______943.594____894.366 + CLK_OUT2____10.000______0.000______50.0______855.836____894.366 + CLK_OUT3____24.800______0.000______50.0______752.191____894.366 + CLK_OUT4____51.667______0.000______50.0______678.319____894.366 + CLK_OUT5____77.500______0.000______50.0______641.055____894.366 + CLK_OUT6___103.333______0.000______50.0______615.875____894.366 + no_CLK_OUT7_output + 0 + 0 + UNKNOWN + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + user_clk + MMCM + AUTO + 250 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 0 + clk_rst + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + clk_250MIn_1 + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 40.0 + 0.010 + 100.0 + 0.010 + BUFG + 943.594 + 894.366 + 50.000 + 5 + 0.000 + 1 + true + BUFG + 855.836 + 894.366 + 50.000 + 10 + 0.000 + 1 + true + BUFG + 752.191 + 894.366 + 50.000 + 25 + 0.000 + 1 + true + BUFG + 678.319 + 894.366 + 50.000 + 50 + 0.000 + 1 + true + BUFG + 641.055 + 894.366 + 50.000 + 75 + 0.000 + 1 + true + BUFG + 615.875 + 894.366 + 50.000 + 100.000 + 0.000 + 1 + true + BUFG + 0.0 + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + riffa_5_clk + false + riffa_10_clk + false + riffa_25_clk + false + riffa_50_clk + false + riffa_75_clk + false + riffa_100_clk + false + clk_out7 + false + CLK_VALID + auto + clk_250MIn_1 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + clk_locked + OPTIMIZED + 62.000 + 0.000 + false + 4.0 + 10.0 + 124.000 + 0.500 + 0.000 + false + 62 + 0.500 + 0.000 + false + 25 + 0.500 + 0.000 + false + 12 + 0.500 + 0.000 + false + false + 8 + 0.500 + 0.000 + false + 6 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 25 + None + 0.010 + 0.010 + false + 6 + false + false + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + user_clk + MMCM + mmcm_adv + 250 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + REL_PRIMARY + Custom + clk_rst + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + false + false + virtex7 + xilinx.com:vc709:part0:1.5 + xc7vx690t + ffg1761 + VERILOG + + MIXED + -2 + C + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2015.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/clk_250MIn_2/clk_250MIn_2.xci b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/clk_250MIn_2/clk_250MIn_2.xci new file mode 100644 index 0000000..a8dadc0 --- /dev/null +++ b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/ip/clk_250MIn_2/clk_250MIn_2.xci @@ -0,0 +1,569 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_250MIn_2 + + + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 40.0 + 100.0 + BUFG + 50.0 + 250.000 + 0.000 + 50.000 + 250 + 0.000 + 1 + BUFG + 50.0 + 250.000 + 0.000 + 50.000 + 250 + 0.000 + 1 + 1 + BUFG + 50.0 + 250.000 + 0.000 + 50.000 + 250 + 0.000 + 1 + 1 + BUFG + 50.0 + 250.000 + 0.000 + 50.000 + 250 + 0.000 + 1 + 1 + BUFG + 50.0 + 250.000 + 0.000 + 50.000 + 250 + 0.000 + 1 + 1 + BUFG + 50.0 + 250.000 + 0.000 + 50.000 + 250 + 0.000 + 1 + 1 + BUFG + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + riffa_125_clk + riffa_150_clk + riffa_175_clk + riffa_200_clk + riffa_225_clk + riffa_250_clk + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + dout + drdy + dwe + 0 + FDBK_AUTO + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_____________250____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + clk_locked + OPTIMIZED + 4.000 + 0.000 + FALSE + 4.0 + 10.0 + 4.000 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + FALSE + 4 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.010 + 0.010 + FALSE + 6 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + CLK_OUT1___250.000______0.000______50.0_______89.528_____85.928 + CLK_OUT2___250.000______0.000______50.0_______89.528_____85.928 + CLK_OUT3___250.000______0.000______50.0_______89.528_____85.928 + CLK_OUT4___250.000______0.000______50.0_______89.528_____85.928 + CLK_OUT5___250.000______0.000______50.0_______89.528_____85.928 + CLK_OUT6___250.000______0.000______50.0_______89.528_____85.928 + no_CLK_OUT7_output + 0 + 0 + UNKNOWN + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + user_clk + PLL + AUTO + 250 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 0 + clk_rst + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + clk_250MIn_2 + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 40.0 + 0.010 + 100.0 + 0.010 + BUFG + 89.528 + 85.928 + 50.000 + 250 + 0.000 + 1 + true + BUFG + 89.528 + 85.928 + 50.000 + 250 + 0.000 + 1 + true + BUFG + 89.528 + 85.928 + 50.000 + 250 + 0.000 + 1 + true + BUFG + 89.528 + 85.928 + 50.000 + 250 + 0.000 + 1 + true + BUFG + 89.528 + 85.928 + 50.000 + 250 + 0.000 + 1 + true + BUFG + 89.528 + 85.928 + 50.000 + 250 + 0.000 + 1 + true + BUFG + 0.0 + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + riffa_125_clk + false + riffa_150_clk + false + riffa_175_clk + false + riffa_200_clk + false + riffa_225_clk + false + riffa_250_clk + false + clk_out7 + false + CLK_VALID + auto + clk_250MIn_2 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + clk_locked + OPTIMIZED + 4 + 0.000 + false + 4.0 + 10.0 + 4 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + false + 4 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 6 + false + false + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + user_clk + PLL + mmcm_adv + 250 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + REL_PRIMARY + Custom + clk_rst + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + false + false + virtex7 + xilinx.com:vc709:part0:1.5 + xc7vx690t + ffg1761 + VERILOG + + MIXED + -2 + C + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2015.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/prj/VC709_Gen2x8If128.xpr b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/prj/VC709_Gen2x8If128.xpr new file mode 100644 index 0000000..15632e3 --- /dev/null +++ b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/prj/VC709_Gen2x8If128.xpr @@ -0,0 +1,864 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +