diff --git a/docs/riffa_documentation.pdf b/docs/riffa_documentation.pdf index a49e78d..fc7a062 100644 Binary files a/docs/riffa_documentation.pdf and b/docs/riffa_documentation.pdf differ diff --git a/fpga/altera/Makefile b/fpga/altera/Makefile index 3fa5722..d2987d7 100644 --- a/fpga/altera/Makefile +++ b/fpga/altera/Makefile @@ -39,7 +39,7 @@ # Author: Dustin Richmond (@darichmond) #----------------------------------------------------------------------- VENDOR:=altera -BOARDS:=de5 de4 de2i c4dev +BOARDS:=de5 de4 de2i CURRENT_PATH := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))) .DEFAULT_GOAL := all diff --git a/fpga/altera/c4dev/C4DevGen1x4If64/Makefile b/fpga/altera/c4dev/C4DevGen1x4If64/Makefile deleted file mode 100644 index 39be211..0000000 --- a/fpga/altera/c4dev/C4DevGen1x4If64/Makefile +++ /dev/null @@ -1,62 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#----------------------------------------------------------------------- -# Filename: Makefile -# Version: 1.0 -# Description: Project-level makefile for building an example project -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------- -# This make file expects the following variables to be set: -# RIFFA_HDL_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory. -# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to -# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory -WIDTH=64 -TYPE=classic -CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))) -PROJECT=$(shell basename $(CURRENT_PATH)) - -ifndef RIFFA_HDL_PATH - RIFFA_HDL_PATH:=../../../riffa_hdl -endif -ifndef BOARD_PATH - BOARD_PATH:=.. -endif -ifndef JOBS - JOBS=1 -endif -include $(RIFFA_HDL_PATH)/riffa.mk -include $(BOARD_PATH)/board.mk - -PROJECT_IP+=ip/ALTGXPCIeGen1x4.qip ip/ALTPLL50I50O125O250O.qip ip/PCIeGen1x4If64.qip diff --git a/fpga/altera/c4dev/C4DevGen1x4If64/bit/C4DevGen1x4If64.sof b/fpga/altera/c4dev/C4DevGen1x4If64/bit/C4DevGen1x4If64.sof deleted file mode 100644 index 9181b71..0000000 Binary files a/fpga/altera/c4dev/C4DevGen1x4If64/bit/C4DevGen1x4If64.sof and /dev/null differ diff --git a/fpga/altera/c4dev/C4DevGen1x4If64/constr/C4DevGen1x4If64.sdc b/fpga/altera/c4dev/C4DevGen1x4If64/constr/C4DevGen1x4If64.sdc deleted file mode 100644 index 82c42d5..0000000 --- a/fpga/altera/c4dev/C4DevGen1x4If64/constr/C4DevGen1x4If64.sdc +++ /dev/null @@ -1,23 +0,0 @@ -# Oscillator Clocks -create_clock -name CLK1_50 -period 20 [get_ports {CLK1_50}] -create_clock -name CLK2_50 -period 20 [get_ports {CLK2_50}] -create_clock -name CLK3_50 -period 20 [get_ports {CLK3_50}] - -# Refclk (100 MHz differential input) -create_clock -period "100 MHz" -name {refclk} [get_ports {PCIE_REFCLK}] - -# 50 MHZ PLL Clock -create_generated_clock -name clk50 -source [get_ports {CLK1_50}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[0]}] - -# 125 MHZ PLL Clock -create_generated_clock -name clk125 -multiply_by 5 -divide_by 2 -source [get_ports {CLK1_50}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[1]}] - -# 250 MHZ PLL Clock -create_generated_clock -name clk250 -multiply_by 5 -source [get_ports {CLK1_50}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[2]}] - -derive_pll_clocks -derive_clock_uncertainty - -# Imported from IP Compiler user guide -set_clock_groups -exclusive -group [get_clocks { refclk*clkout }] -group [get_clocks { *div0*coreclkout}] -set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }] -group [get_clocks { *central_clk_div1* }] diff --git a/fpga/altera/c4dev/C4DevGen1x4If64/hdl/C4DevGen1x4If64.v b/fpga/altera/c4dev/C4DevGen1x4If64/hdl/C4DevGen1x4If64.v deleted file mode 100644 index a7a64cf..0000000 --- a/fpga/altera/c4dev/C4DevGen1x4If64/hdl/C4DevGen1x4If64.v +++ /dev/null @@ -1,394 +0,0 @@ -// ---------------------------------------------------------------------- -// Copyright (c) 2016, The Regents of the University of California All -// rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above -// copyright notice, this list of conditions and the following -// disclaimer in the documentation and/or other materials provided -// with the distribution. -// -// * Neither the name of The Regents of the University of California -// nor the names of its contributors may be used to endorse or -// promote products derived from this software without specific -// prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -// DAMAGE. -// ---------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// Filename: C4DevGen1x4If64.v -// Version: -// Verilog Standard: Verilog-2001 -// Description: Top level module for RIFFA 2.2 reference design for the -// the Altera Cyclone IV IP Compiler for PCI Express -// module and the Terasic DE2i Development Board. -// Author: Dustin Richmond (@darichmond) -//----------------------------------------------------------------------------- -`include "functions.vh" -`include "riffa.vh" -`include "altera.vh" -module C4DevGen1x4If64 - #(// Number of RIFFA Channels - parameter C_NUM_CHNL = 1, - // Number of PCIe Lanes - parameter C_NUM_LANES = 4, - // Settings from Quartus IP Library - parameter C_PCI_DATA_WIDTH = 64, - parameter C_MAX_PAYLOAD_BYTES = 256, - parameter C_LOG_NUM_TAGS = 5) - (input CLK1_50, - input PCIE_RESET_N, - input PCIE_REFCLK, - input [C_NUM_LANES-1:0] PCIE_RX_IN, - output [C_NUM_LANES-1:0] PCIE_TX_OUT, - // ----------LEDs ---------- - output [7:0] LED_G); - // ----------PLL Signals---------- - wire clk50; - wire clk125; - wire clk250; - wire locked; - wire inclk0; - - // ----------PCIe Core Signals---------- - // ----------PCIe Clocks---------- - wire pld_clk; - wire reconfig_clk; - wire core_clk_out; - wire fixedclk_serdes; - wire refclk; - wire rc_pll_locked; - wire cal_blk_clk; - - // ----------PCIe Resets---------- - wire [ 4: 0] pex_msi_num; - wire pll_powerdown; - wire reset_status; - wire crst; - wire npor; - wire srst; - wire gxb_powerdown; - - // ----------PCIe Transaction layer configuration ---------- - wire [ 3: 0] tl_cfg_add; - wire [ 31: 0] tl_cfg_ctl; - wire tl_cfg_ctl_wr; - wire [ 52: 0] tl_cfg_sts; - wire tl_cfg_sts_wr; - wire [ 19: 0] ko_cpl_spc_vc0; - - // ----------PCIe Local Management Interface---------- - wire lmi_ack; - wire [ 31: 0] lmi_dout; - wire [ 11: 0] lmi_addr; - wire [ 31: 0] lmi_din; - wire lmi_rden; - wire lmi_wren; - - // ----------PCIe Interrupt Interface ---------- - wire app_int_ack; - wire app_msi_ack; - wire app_int_sts; - wire app_msi_req; - - // ----------PCIe Status Signals---------- - wire hotrst_exit; - wire l2_exit; - wire [3:0] lane_act; - wire [4:0] ltssm; - wire pme_to_sr; - wire suc_spd_neg; - - // ----------PCIe RX Interface---------- - wire rx_st_mask0; - wire [ 7: 0] rx_st_bardec0; - wire [ 15: 0] rx_st_be0; - wire [0:0] rx_st_sop0; - wire [0:0] rx_st_eop0; - wire [0:0] rx_st_err0; - wire [0:0] rx_st_valid0; - wire [0:0] rx_st_empty0; - wire rx_st_ready0; - wire [C_PCI_DATA_WIDTH-1:0] rx_st_data0; - - // ----------PCIe TX Interface---------- - wire [0:0] tx_st_sop0; - wire [0:0] tx_st_eop0; - wire [0:0] tx_st_err0; - wire [0:0] tx_st_valid0; - wire [0:0] tx_st_empty0; - wire tx_st_ready0; - wire [C_PCI_DATA_WIDTH-1:0] tx_st_data0; - - // ----------ALTGX Signals---------- - wire busy; - wire busy_altgxb_reconfig; - wire [4:0] reconfig_fromgxb; - wire [3:0] reconfig_togxb; - - // ----------Resets ---------- - reg [4:0] rRstCtr,_rRstCtr; - reg [2:0] rRstSync,_rRstSync; - wire wSyncRst; - - always @(*) begin - _rRstSync = {rRstSync[1:0], ~npor}; - _rRstCtr = rRstCtr; - if (rRstSync[2]) begin - _rRstCtr = 0; - end else if (~rRstCtr[4]) begin - _rRstCtr = rRstCtr + 1; - end - end - - always @(posedge pld_clk) begin - rRstSync <= _rRstSync; - rRstCtr <= _rRstCtr; - end - - assign wSyncRst = ~ rRstCtr[4]; - assign srst = wSyncRst; - assign crst = wSyncRst; - - // ----------PLL assignments---------- - assign inclk0 = CLK1_50; - assign fixedclk_serdes = clk125; - assign reconfig_clk = clk50; - - // ----------PCIe Resets---------- - assign npor = PCIE_RESET_N; - assign gxb_powerdown = ~ npor; - assign pll_powerdown = ~ npor; - - // ----------PCIe Clocks / PLLs---------- - assign refclk = PCIE_REFCLK; - assign pld_clk = core_clk_out; - assign cal_blk_clk = reconfig_clk; - - // ----------ALTGX---------- - assign busy = busy_altgxb_reconfig; - - // -------------------- BEGIN ALTERA IP INSTANTIATION -------------------- - ALTPLL50I50O125O250O ALTPLL50I50O125O250O_inst - ( - // Outputs - .c0 (clk50), - .c1 (clk125), - .c2 (clk250), - .locked (locked), - // Inputs - .inclk0 (inclk0)); - - ALTGXPCIeGen1x4 - altgx_inst - ( - // Outputs - .busy (busy), - .reconfig_togxb (reconfig_togxb[3:0]), - // Inputs - .reconfig_clk (reconfig_clk), - .reconfig_fromgxb (reconfig_fromgxb[4:0])); - - PCIeGen1x4If64 - pcie_inst - ( - // Outputs - .app_int_ack (app_int_ack), - .app_msi_ack (app_msi_ack), - .core_clk_out (core_clk_out), - .hotrst_exit (hotrst_exit), - .l2_exit (l2_exit), - .lane_act (lane_act[3:0]), - .lmi_ack (lmi_ack), - .lmi_dout (lmi_dout[31:0]), - .ltssm (ltssm[4:0]), - .rc_pll_locked (rc_pll_locked), - .reconfig_fromgxb (reconfig_fromgxb[4:0]), - .reset_status (reset_status), - .rx_st_bardec0 (rx_st_bardec0[7:0]), - .rx_st_be0 (rx_st_be0[7:0]), - .rx_st_data0 (rx_st_data0[C_PCI_DATA_WIDTH-1:0]), - .rx_st_eop0 (rx_st_eop0), - .rx_st_err0 (rx_st_err0), - .rx_st_sop0 (rx_st_sop0), - .rx_st_valid0 (rx_st_valid0), - .suc_spd_neg (suc_spd_neg),// Gen 2 successful - .tl_cfg_add (tl_cfg_add[3:0]), - .tl_cfg_ctl (tl_cfg_ctl[31:0]), - .tl_cfg_ctl_wr (tl_cfg_ctl_wr), - .tl_cfg_sts (tl_cfg_sts[52:0]), - .tl_cfg_sts_wr (tl_cfg_sts_wr), - .ko_cpl_spc_vc0 (ko_cpl_spc_vc0), - .tx_out0 (PCIE_TX_OUT[0]), - .tx_out1 (PCIE_TX_OUT[1]), - .tx_out2 (PCIE_TX_OUT[2]), - .tx_out3 (PCIE_TX_OUT[3]), - .tx_st_ready0 (tx_st_ready0), - // Inputs - .app_int_sts (app_int_sts), - .app_msi_num (5'b00000), - .app_msi_req (app_msi_req), - .app_msi_tc (3'b000), - .busy_altgxb_reconfig (busy_altgxb_reconfig), - .cal_blk_clk (cal_blk_clk), - .crst (crst), - .fixedclk_serdes (fixedclk_serdes), - .gxb_powerdown (gxb_powerdown), - .pll_powerdown (pll_powerdown), - .lmi_addr (lmi_addr[11:0]), - .lmi_din (lmi_din[31:0]), - .lmi_rden (lmi_rden), - .lmi_wren (lmi_wren), - .npor (npor), - .pex_msi_num (pex_msi_num[4:0]), - .pld_clk (pld_clk), - .reconfig_clk (reconfig_clk), - .reconfig_togxb (reconfig_togxb[3:0]), - .refclk (refclk), - .rx_in0 (PCIE_RX_IN[0]), - .rx_in1 (PCIE_RX_IN[1]), - .rx_in2 (PCIE_RX_IN[2]), - .rx_in3 (PCIE_RX_IN[3]), - .rx_st_ready0 (rx_st_ready0), - .srst (srst), - .tx_st_data0 (tx_st_data0[C_PCI_DATA_WIDTH-1:0]), - .tx_st_eop0 (tx_st_eop0), - .tx_st_err0 (tx_st_err0), - .tx_st_sop0 (tx_st_sop0), - .tx_st_valid0 (tx_st_valid0)); - - // -------------------- END ALTERA IP INSTANTIATION -------------------- - // -------------------- BEGIN RIFFA INSTANTAION -------------------- - - // ----------RIFFA channel interface---------- - wire [C_NUM_CHNL-1:0] chnl_rx_clk; - wire [C_NUM_CHNL-1:0] chnl_rx; - wire [C_NUM_CHNL-1:0] chnl_rx_ack; - wire [C_NUM_CHNL-1:0] chnl_rx_last; - wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len; - wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data; - wire [C_NUM_CHNL-1:0] chnl_rx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_rx_data_ren; - - wire [C_NUM_CHNL-1:0] chnl_tx_clk; - wire [C_NUM_CHNL-1:0] chnl_tx; - wire [C_NUM_CHNL-1:0] chnl_tx_ack; - wire [C_NUM_CHNL-1:0] chnl_tx_last; - wire [(C_NUM_CHNL*32)-1:0] chnl_tx_len; - wire [(C_NUM_CHNL*31)-1:0] chnl_tx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data; - wire [C_NUM_CHNL-1:0] chnl_tx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_tx_data_ren; - - wire chnl_reset; - wire chnl_clk; - wire rst_out; - - assign chnl_clk = pld_clk; - assign chnl_reset = rst_out; - - riffa_wrapper_c4dev - #(/*AUTOINSTPARAM*/ - // Parameters - .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), - .C_NUM_CHNL (C_NUM_CHNL), - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES)) - riffa - (// Outputs - .RX_ST_READY (rx_st_ready0), - .TX_ST_DATA (tx_st_data0[C_PCI_DATA_WIDTH-1:0]), - .TX_ST_VALID (tx_st_valid0[0:0]), - .TX_ST_EOP (tx_st_eop0[0:0]), - .TX_ST_SOP (tx_st_sop0[0:0]), - .TX_ST_EMPTY (tx_st_empty0[0:0]), - .APP_MSI_REQ (app_msi_req), - .RST_OUT (rst_out), - .CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]), - .CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]), - .CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]), - .CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]), - .CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]), - // Inputs - .RX_ST_DATA (rx_st_data0[C_PCI_DATA_WIDTH-1:0]), - .RX_ST_EOP (rx_st_eop0[0:0]), - .RX_ST_SOP (rx_st_sop0[0:0]), - .RX_ST_VALID (rx_st_valid0[0:0]), - .RX_ST_EMPTY (rx_st_empty0[0:0]), - .TX_ST_READY (tx_st_ready0), - .TL_CFG_CTL (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]), - .TL_CFG_ADD (tl_cfg_add[`SIG_CFG_ADD_W-1:0]), - .TL_CFG_STS (tl_cfg_sts[`SIG_CFG_STS_W-1:0]), - .KO_CPL_SPC_HEADER (ko_cpl_spc_vc0[7:0]), - .KO_CPL_SPC_DATA (ko_cpl_spc_vc0[19:8]), - .APP_MSI_ACK (app_msi_ack), - .PLD_CLK (pld_clk), - .RESET_STATUS (reset_status), - .CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]), - .CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]), - .CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]), - .CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]), - .CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]), - .CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]), - .CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])); - - // -------------------- END RIFFA INSTANTAION -------------------- - // -------------------- BEGIN USER CODE -------------------- - genvar i; - generate - for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels - // Instantiate and assign modules to RIFFA channels. Users should - // replace the chnl_tester instantiation with their own core. - chnl_tester - #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) - chnl_tester_i - (.CLK(chnl_clk), - .RST(chnl_reset), // chnl_reset includes riffa_endpoint resets - // Rx interface - .CHNL_RX_CLK(chnl_rx_clk[i]), - .CHNL_RX(chnl_rx[i]), - .CHNL_RX_ACK(chnl_rx_ack[i]), - .CHNL_RX_LAST(chnl_rx_last[i]), - .CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), - .CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), - .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), - .CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]), - .CHNL_RX_DATA_REN(chnl_rx_data_ren[i]), - // Tx interface - .CHNL_TX_CLK(chnl_tx_clk[i]), - .CHNL_TX(chnl_tx[i]), - .CHNL_TX_ACK(chnl_tx_ack[i]), - .CHNL_TX_LAST(chnl_tx_last[i]), - .CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), - .CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), - .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), - .CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]), - .CHNL_TX_DATA_REN(chnl_tx_data_ren[i])); - end - endgenerate - // -------------------- END USER CODE -------------------- -endmodule // DE2i_PCIe diff --git a/fpga/altera/c4dev/C4DevGen1x4If64/prj/C4DevGen1x4If64.qpf b/fpga/altera/c4dev/C4DevGen1x4If64/prj/C4DevGen1x4If64.qpf deleted file mode 100644 index d095759..0000000 --- a/fpga/altera/c4dev/C4DevGen1x4If64/prj/C4DevGen1x4If64.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Full Version -# Date created = 12:52:42 March 20, 2014 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "12:52:42 March 20, 2014" - -# Revisions - -PROJECT_REVISION = "C4DevGen1x4If64" diff --git a/fpga/altera/c4dev/C4DevGen1x4If64/prj/C4DevGen1x4If64.qsf b/fpga/altera/c4dev/C4DevGen1x4If64/prj/C4DevGen1x4If64.qsf deleted file mode 100644 index 90ba35e..0000000 --- a/fpga/altera/c4dev/C4DevGen1x4If64/prj/C4DevGen1x4If64.qsf +++ /dev/null @@ -1,278 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Full Version -# Date created = 12:52:42 March 20, 2014 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# C4DevGen1x4If64_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Cyclone IV GX" -set_global_assignment -name DEVICE EP4CGX150DF31C7 -set_global_assignment -name TOP_LEVEL_ENTITY C4DevGen1x4If64 -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:52:42 MARCH 20, 2014" -set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/ -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation - -################################################################################ -#Clocks -################################################################################ -set_instance_assignment -name IO_STANDARD "1.8 V" -to CLK1_50 -set_location_assignment PIN_AK16 -to CLK1_50 - -################################################################################ -#PCIE -- Clocks, Resets -################################################################################ - -set_instance_assignment -name IO_STANDARD "1.8 V" -to PCIE_RESET_N -set_location_assignment PIN_A7 -to PCIE_RESET_N - -set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK -set_location_assignment PIN_V15 -to PCIE_REFCLK - -set_instance_assignment -name IO_STANDARD "1.8 V" -to PCIE_WAKE -set_location_assignment IOBANK8 -to PCIE_WAKE - -################################################################################ -#PCIE RX_IN 0 -################################################################################ - -set_location_assignment PIN_AC2 -to PCIE_RX_IN[0] -set_location_assignment PIN_AC1 -to "PCIE_RX_IN[0](n)" - -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[0] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[0](n)" - -################################################################################ -#PCIE RX_IN 1 -################################################################################ - -set_location_assignment PIN_AA2 -to PCIE_RX_IN[1] -set_location_assignment PIN_AA1 -to "PCIE_RX_IN[1](n)" - -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[1] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[1](n)" - -################################################################################ -#PCIE RX_IN 2 -################################################################################ - -set_location_assignment PIN_W2 -to PCIE_RX_IN[2] -set_location_assignment PIN_W1 -to "PCIE_RX_IN[2](n)" - -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[2] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[2](n)" - -################################################################################ -#PCIE RX_IN 3 -################################################################################ - -set_location_assignment PIN_U2 -to PCIE_RX_IN[3] -set_location_assignment PIN_U1 -to "PCIE_RX_IN[3](n)" - -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[3](n)" - -################################################################################ -#PCIE TX_OUT 0 -################################################################################ - -set_location_assignment PIN_AB4 -to PCIE_TX_OUT[0] -set_location_assignment PIN_AB3 -to "PCIE_TX_OUT[0](n)" - -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[0] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[0](n)" - -################################################################################ -#PCIE TX_OUT 1 -################################################################################ - -set_location_assignment PIN_Y4 -to PCIE_TX_OUT[1] -set_location_assignment PIN_Y3 -to "PCIE_TX_OUT[1](n)" - -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[1] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[1](n)" - -################################################################################ -#PCIE TX_OUT 2 -################################################################################ - -set_location_assignment PIN_V4 -to PCIE_TX_OUT[2] -set_location_assignment PIN_V3 -to "PCIE_TX_OUT[2](n)" - -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[2] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[2](n)" - -################################################################################ -#PCIE TX_OUT 3 -################################################################################ - -set_location_assignment PIN_T4 -to PCIE_TX_OUT[3] -set_location_assignment PIN_T3 -to "PCIE_TX_OUT[3](n)" - -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[3](n)" - -################################################################################ -# Green LED's -################################################################################ -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[7] -set_location_assignment PIN_E4 -to LED_G[0] -set_location_assignment PIN_C7 -to LED_G[1] -set_location_assignment PIN_A4 -to LED_G[2] -set_location_assignment PIN_F6 -to LED_G[3] -set_location_assignment PIN_D4 -to LED_G[4] -set_location_assignment PIN_J9 -to LED_G[5] -set_location_assignment PIN_D12 -to LED_G[6] -set_location_assignment PIN_B6 -to LED_G[7] - -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 -set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF - -set_global_assignment -name QIP_FILE ../ip/PCIeGen1x4If64.qip -set_global_assignment -name QIP_FILE ../ip/ALTPLL50I50O125O250O.qip -set_global_assignment -name QIP_FILE ../ip/ALTGXPCIeGen1x4.qip -set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_c4dev.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_extender.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_128.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_128.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_controller.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v -set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v -set_global_assignment -name SEARCH_PATH ../../../../riffa_hdl -set_global_assignment -name SDC_FILE ../constr/C4DevGen1x4If64.sdc -set_global_assignment -name VERILOG_FILE ../hdl/C4DevGen1x4If64.v -set_global_assignment -name SOURCE_FILE db/C4DevGen1x4If64.cmp.rdb -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/fpga/altera/c4dev/Makefile b/fpga/altera/c4dev/Makefile deleted file mode 100644 index 566f905..0000000 --- a/fpga/altera/c4dev/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#----------------------------------------------------------------------- -# Filename: Makefile -# Version: 1.0 -# Description: Top-level makefile for building the example -# projects in a board -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------- -BOARD=c4dev -BOARD_PROJECTS:=C4DevGen1x4If64 -BOARD_TYPE:=classic -VENDOR:=altera -include ../vendor.mk diff --git a/fpga/altera/c4dev/board.mk b/fpga/altera/c4dev/board.mk deleted file mode 100644 index becba70..0000000 --- a/fpga/altera/c4dev/board.mk +++ /dev/null @@ -1,105 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#----------------------------------------------------------------------- -# Filename: board.mk -# Version: 1.0 -# Description: Board-specific include makefile -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------- -include $(RIFFA_ROOT_PATH)/release.mk -.DEFAULT_GOAL=all - -BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v - -PROJECT_IP= -PROJECT_BIT:= bit/$(PROJECT).sof -PROJECT_HDL=hdl/$(PROJECT).v $(BOARD_HDL) $(patsubst %, $(RIFFA_HDL_PATH)/%,$(RIFFA_HDL)) -PROJECT_CONSTR=constr/$(PROJECT).sdc -PROJECT_FILE=prj/$(PROJECT).qsf prj/$(PROJECT).qpf -PROJECT_FILES=$(PROJECT_IP) $(PROJECT_CONSTR) $(PROJECT_QSRCS) $(PROJECT_HDL) - -RELEASE_BIT:=$(PROJECT_BIT) -RELEASE_IP:=$(PROJECT_IP) -RELEASE_HDL:=hdl/$(PROJECT).v -RELEASE_CONSTR:=$(PROJECT_CONSTR) -RELEASE_FILE:=$(PROJECT_FILE) -RELEASE_PROJECT_PATH:=$(RELEASE_SRC_PATH)/fpga/$(VENDOR)/$(BOARD)/$(PROJECT) -copy-files = $(foreach file, $1, cp $(file) $2;) - -.PHONY:$(PROJECT) all synthesis implementation clean clobber $(TYPE) $(VENDOR) $(BOARD) -$(PROJECT): $(PROJECT_BIT) - @echo Compiling Project $@ - -$(PROJECT_BIT): $(PROJECT_FILES) - quartus_sh --flow compile prj/$(PROJECT).qpf - -synthesis: bit/$(PROJECT).map.rpt -bit/$(PROJECT).map.rpt: $(PROJECT_FILES) - quartus_sh --flow analysis_and_synthesis prj/$(PROJECT).qpf - - -implementation:bit/$(PROJECT).fit.rpt -bit/$(PROJECT).fit.rpt: $(PROJECT_FILES) - quartus_sh --flow fitter prj/$(PROJECT).qpf - -all $(TYPE) $(VENDOR) $(BOARD):$(PROJECT) -clean: - rm -rf ip/.qsys_edit ip/*~ - rm -rf prj/db prj/incremental_db prj/*txt prj/*.sopcinfo prj/*.qws prj/*~ - rm -rf bit/*.done bit/*.smsg bit/*.rpt bit/*.summary bit/*.sld bit/*.pin bit/*.jdi bit/*~ - rm -rf hdl/*~ - rm -rf constr/*~ - rm -rf *~ - -clobber: - rm -rf $(PROJECT_BIT) - -destination: $(RELEASE_PROJECT_PATH) - mkdir $(RELEASE_PROJECT_PATH)/bit - mkdir $(RELEASE_PROJECT_PATH)/constr - mkdir $(RELEASE_PROJECT_PATH)/ip - mkdir $(RELEASE_PROJECT_PATH)/hdl - mkdir $(RELEASE_PROJECT_PATH)/prj - -$(RELEASE_PROJECT_PATH): check-release-src - mkdir $@ - -release:check-release-src destination - $(call copy-files, $(RELEASE_BIT), $(RELEASE_PROJECT_PATH)/bit) - $(call copy-files, $(RELEASE_CONSTR), $(RELEASE_PROJECT_PATH)/constr) - $(call copy-files, $(RELEASE_IP), $(RELEASE_PROJECT_PATH)/ip) - $(call copy-files, $(RELEASE_HDL), $(RELEASE_PROJECT_PATH)/hdl) - $(call copy-files, $(RELEASE_FILE), $(RELEASE_PROJECT_PATH)/prj) - diff --git a/fpga/altera/c4dev/riffa_wrapper_c4dev.v b/fpga/altera/c4dev/riffa_wrapper_c4dev.v deleted file mode 100644 index 6ca2132..0000000 --- a/fpga/altera/c4dev/riffa_wrapper_c4dev.v +++ /dev/null @@ -1,627 +0,0 @@ -// ---------------------------------------------------------------------- -// Copyright (c) 2016, The Regents of the University of California All -// rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above -// copyright notice, this list of conditions and the following -// disclaimer in the documentation and/or other materials provided -// with the distribution. -// -// * Neither the name of The Regents of the University of California -// nor the names of its contributors may be used to endorse or -// promote products derived from this software without specific -// prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -// DAMAGE. -// ---------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// Filename: riffa_wrapper_de2i.v -// Version: 1.00a -// Verilog Standard: Verilog-2001 -// Description: Wrapper file for all riffa logic for Altera DE2I boards -// Author: Dustin Richmond (@darichmond) -//----------------------------------------------------------------------------- -`include "trellis.vh" -`include "riffa.vh" -`include "altera.vh" -`include "ultrascale.vh" -`include "functions.vh" -`timescale 1ps / 1ps -module riffa_wrapper_c4dev - #(// Number of RIFFA Channels - parameter C_NUM_CHNL = 1, - // Bit-Width from Quartus IP Generator - parameter C_PCI_DATA_WIDTH = 64, - parameter C_MAX_PAYLOAD_BYTES = 256, - parameter C_LOG_NUM_TAGS = 5, - parameter C_FPGA_ID = "C4DE") - (// Interface: Altera RX - input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA, - input [0:0] RX_ST_EOP, - input [0:0] RX_ST_SOP, - input [0:0] RX_ST_VALID, - output RX_ST_READY, - input [0:0] RX_ST_EMPTY, - - // Interface: Altera TX - output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA, - output [0:0] TX_ST_VALID, - input TX_ST_READY, - output [0:0] TX_ST_EOP, - output [0:0] TX_ST_SOP, - output [0:0] TX_ST_EMPTY, - - // Interface: Altera Config - input [`SIG_CFG_CTL_W-1:0] TL_CFG_CTL, - input [`SIG_CFG_ADD_W-1:0] TL_CFG_ADD, - input [`SIG_CFG_STS_W-1:0] TL_CFG_STS, - - // Interface: Altera Flow Control - input [`SIG_KO_CPLH_W-1:0] KO_CPL_SPC_HEADER, - input [`SIG_KO_CPLD_W-1:0] KO_CPL_SPC_DATA, - - // Interface: Altera Interrupt - input APP_MSI_ACK, - output APP_MSI_REQ, - - // Interface: Altera CLK/RESET - input PLD_CLK, - input RESET_STATUS, - - // RIFFA Interface Signals - output RST_OUT, - input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock - output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal - input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal - output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read - output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length - output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset - output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data - output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid - input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved - - input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock - input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal - output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal - input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write - input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words) - input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset - input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data - input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid - output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved - - localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver - localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2; - localparam C_VENDOR = "ALTERA"; - - localparam C_ALTERA_TX_READY_LATENCY = 2; - localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32; - localparam C_PIPELINE_OUTPUT = 1; - localparam C_PIPELINE_INPUT = 1; - localparam C_DEPTH_PACKETS = 4; - - wire clk; - wire rst_in; - wire done_txc_rst; - wire done_txr_rst; - wire done_rxr_rst; - wire done_rxc_rst; - // Interface: RXC Engine - wire [C_PCI_DATA_WIDTH-1:0] rxc_data; - wire rxc_data_valid; - wire rxc_data_start_flag; - wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset; - wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe; - wire rxc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset; - wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe; - wire [`SIG_TAG_W-1:0] rxc_meta_tag; - wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr; - wire [`SIG_TYPE_W-1:0] rxc_meta_type; - wire [`SIG_LEN_W-1:0] rxc_meta_length; - wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining; - wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id; - wire rxc_meta_ep; - - // Interface: RXR Engine - wire [C_PCI_DATA_WIDTH-1:0] rxr_data; - wire rxr_data_valid; - wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable; - wire rxr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset; - wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe; - wire rxr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset; - wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe; - wire [`SIG_TC_W-1:0] rxr_meta_tc; - wire [`SIG_ATTR_W-1:0] rxr_meta_attr; - wire [`SIG_TAG_W-1:0] rxr_meta_tag; - wire [`SIG_TYPE_W-1:0] rxr_meta_type; - wire [`SIG_ADDR_W-1:0] rxr_meta_addr; - wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded; - wire [`SIG_REQID_W-1:0] rxr_meta_requester_id; - wire [`SIG_LEN_W-1:0] rxr_meta_length; - wire rxr_meta_ep; - - // interface: TXC Engine - wire txc_data_valid; - wire [C_PCI_DATA_WIDTH-1:0] txc_data; - wire txc_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset; - wire txc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset; - wire txc_data_ready; - - wire txc_meta_valid; - wire [`SIG_FBE_W-1:0] txc_meta_fdwbe; - wire [`SIG_LBE_W-1:0] txc_meta_ldwbe; - wire [`SIG_LOWADDR_W-1:0] txc_meta_addr; - wire [`SIG_TYPE_W-1:0] txc_meta_type; - wire [`SIG_LEN_W-1:0] txc_meta_length; - wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count; - wire [`SIG_TAG_W-1:0] txc_meta_tag; - wire [`SIG_REQID_W-1:0] txc_meta_requester_id; - wire [`SIG_TC_W-1:0] txc_meta_tc; - wire [`SIG_ATTR_W-1:0] txc_meta_attr; - wire txc_meta_ep; - wire txc_meta_ready; - wire txc_sent; - - // Interface: TXR Engine - wire txr_data_valid; - wire [C_PCI_DATA_WIDTH-1:0] txr_data; - wire txr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset; - wire txr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset; - wire txr_data_ready; - - wire txr_meta_valid; - wire [`SIG_FBE_W-1:0] txr_meta_fdwbe; - wire [`SIG_LBE_W-1:0] txr_meta_ldwbe; - wire [`SIG_ADDR_W-1:0] txr_meta_addr; - wire [`SIG_LEN_W-1:0] txr_meta_length; - wire [`SIG_TAG_W-1:0] txr_meta_tag; - wire [`SIG_TC_W-1:0] txr_meta_tc; - wire [`SIG_ATTR_W-1:0] txr_meta_attr; - wire [`SIG_TYPE_W-1:0] txr_meta_type; - wire txr_meta_ep; - wire txr_meta_ready; - wire txr_sent; - - // Classic Interface Wires - wire rx_tlp_ready; - wire [C_PCI_DATA_WIDTH-1:0] rx_tlp; - wire rx_tlp_end_flag; - wire [`SIG_OFFSET_W-1:0] rx_tlp_end_offset; - wire rx_tlp_start_flag; - wire [`SIG_OFFSET_W-1:0] rx_tlp_start_offset; - wire rx_tlp_valid; - wire [`SIG_BARDECODE_W-1:0] rx_tlp_bar_decode; - - wire tx_tlp_ready; - wire [C_PCI_DATA_WIDTH-1:0] tx_tlp; - wire tx_tlp_end_flag; - wire [`SIG_OFFSET_W-1:0] tx_tlp_end_offset; - wire tx_tlp_start_flag; - wire [`SIG_OFFSET_W-1:0] tx_tlp_start_offset; - wire tx_tlp_valid; - - // Unconnected Wires (Used in ultrascale interface) - // Interface: RQ (TXC) - wire s_axis_rq_tlast_nc; - wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata_nc; - wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser_nc; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep_nc; - wire s_axis_rq_tready_nc = 0; - wire s_axis_rq_tvalid_nc; - // Interface: RC (RXC) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata_nc = 0; - wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser_nc = 0; - wire m_axis_rc_tlast_nc = 0; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep_nc = 0; - wire m_axis_rc_tvalid_nc = 0; - wire m_axis_rc_tready_nc; - // Interface: CQ (RXR) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata_nc = 0; - wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser_nc = 0; - wire m_axis_cq_tlast_nc = 0; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep_nc = 0; - wire m_axis_cq_tvalid_nc = 0; - wire m_axis_cq_tready_nc = 0; - // Interface: CC (TXC) - wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata_nc; - wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser_nc; - wire s_axis_cc_tlast_nc; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep_nc; - wire s_axis_cc_tvalid_nc; - wire s_axis_cc_tready_nc = 0; - - // Interface: Configuration - wire config_bus_master_enable; - wire [`SIG_CPLID_W-1:0] config_completer_id; - wire config_cpl_boundary_sel; - wire config_interrupt_msienable; - wire [`SIG_LINKRATE_W-1:0] config_link_rate; - wire [`SIG_LINKWIDTH_W-1:0] config_link_width; - wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size; - wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size; - wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data; - wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr; - - wire intr_msi_request; - wire intr_msi_rdy; - - genvar chnl; - - assign clk = PLD_CLK; - assign rst_in = RESET_STATUS; - - translation_altera - #(/*AUTOINSTPARAM*/ - // Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH)) - trans - ( - // Outputs - .RX_TLP (rx_tlp[C_PCI_DATA_WIDTH-1:0]), - .RX_TLP_VALID (rx_tlp_valid), - .RX_TLP_START_FLAG (rx_tlp_start_flag), - .RX_TLP_START_OFFSET (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RX_TLP_END_FLAG (rx_tlp_end_flag), - .RX_TLP_END_OFFSET (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RX_TLP_BAR_DECODE (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]), - .TX_TLP_READY (tx_tlp_ready), - .CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]), - .CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable), - .CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]), - .CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]), - .CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]), - .CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]), - .CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable), - .CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel), - .CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]), - .CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]), - .INTR_MSI_RDY (intr_msi_rdy), - // Inputs - .CLK (clk), - .RST_IN (rst_in), - .RX_TLP_READY (rx_tlp_ready), - .TX_TLP (tx_tlp[C_PCI_DATA_WIDTH-1:0]), - .TX_TLP_VALID (tx_tlp_valid), - .TX_TLP_START_FLAG (tx_tlp_start_flag), - .TX_TLP_START_OFFSET (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TX_TLP_END_FLAG (tx_tlp_end_flag), - .TX_TLP_END_OFFSET (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .INTR_MSI_REQUEST (intr_msi_request), - /*AUTOINST*/ - // Outputs - .RX_ST_READY (RX_ST_READY), - .TX_ST_DATA (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]), - .TX_ST_VALID (TX_ST_VALID[0:0]), - .TX_ST_EOP (TX_ST_EOP[0:0]), - .TX_ST_SOP (TX_ST_SOP[0:0]), - .TX_ST_EMPTY (TX_ST_EMPTY[0:0]), - .APP_MSI_REQ (APP_MSI_REQ), - // Inputs - .RX_ST_DATA (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]), - .RX_ST_EOP (RX_ST_EOP[0:0]), - .RX_ST_SOP (RX_ST_SOP[0:0]), - .RX_ST_VALID (RX_ST_VALID[0:0]), - .RX_ST_EMPTY (RX_ST_EMPTY[0:0]), - .TX_ST_READY (TX_ST_READY), - .TL_CFG_CTL (TL_CFG_CTL[`SIG_CFG_CTL_W-1:0]), - .TL_CFG_ADD (TL_CFG_ADD[`SIG_CFG_ADD_W-1:0]), - .TL_CFG_STS (TL_CFG_STS[`SIG_CFG_STS_W-1:0]), - .KO_CPL_SPC_HEADER (KO_CPL_SPC_HEADER[`SIG_FC_CPLH_W-1:0]), - .KO_CPL_SPC_DATA (KO_CPL_SPC_DATA[`SIG_FC_CPLD_W-1:0]), - .APP_MSI_ACK (APP_MSI_ACK)); - - engine_layer - #(// Parameters - .C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4), - /*AUTOINSTPARAM*/ - // Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), - .C_PIPELINE_INPUT (C_PIPELINE_INPUT), - .C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT), - .C_VENDOR (C_VENDOR)) - engine_layer_inst - (// Outputs - .RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]), - .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_DATA_VALID (rxc_data_valid), - .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]), - .RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]), - .RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]), - .RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]), - .RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]), - .RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]), - .RXC_META_EP (rxc_meta_ep), - - .RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]), - .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_VALID (rxr_data_valid), - .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), - .RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]), - .RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]), - .RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]), - .RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]), - .RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]), - .RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]), - .RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]), - .RXR_META_EP (rxr_meta_ep), - - .TXC_DATA_READY (txc_data_ready), - .TXC_META_READY (txc_meta_ready), - .TXC_SENT (txc_sent), - - .TXR_DATA_READY (txr_data_ready), - .TXR_META_READY (txr_meta_ready), - .TXR_SENT (txr_sent), - - .RST_LOGIC (RST_OUT), - // Unconnected Outputs - .TX_TLP (tx_tlp), - .TX_TLP_VALID (tx_tlp_valid), - .TX_TLP_START_FLAG (tx_tlp_start_flag), - .TX_TLP_START_OFFSET (tx_tlp_start_offset), - .TX_TLP_END_FLAG (tx_tlp_end_flag), - .TX_TLP_END_OFFSET (tx_tlp_end_offset), - - .RX_TLP_READY (rx_tlp_ready), - // Inputs - .CLK_BUS (clk), - .RST_BUS (rst_in), - - .CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]), - - .TXC_DATA_VALID (txc_data_valid), - .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), - .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_META_VALID (txc_meta_valid), - .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]), - .TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]), - .TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]), - .TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]), - .TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]), - .TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]), - .TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]), - .TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]), - .TXC_META_EP (txc_meta_ep), - - .TXR_DATA_VALID (txr_data_valid), - .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), - .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_META_VALID (txr_meta_valid), - .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]), - .TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]), - .TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]), - .TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]), - .TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]), - .TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]), - .TXR_META_EP (txr_meta_ep), - // Unconnected Inputs - .RX_TLP (rx_tlp), - .RX_TLP_VALID (rx_tlp_valid), - .RX_TLP_START_FLAG (rx_tlp_start_flag), - .RX_TLP_START_OFFSET (rx_tlp_start_offset), - .RX_TLP_END_FLAG (rx_tlp_end_flag), - .RX_TLP_END_OFFSET (rx_tlp_end_offset), - .RX_TLP_BAR_DECODE (rx_tlp_bar_decode), - - .TX_TLP_READY (tx_tlp_ready), - .DONE_TXC_RST (done_txc_rst), - .DONE_TXR_RST (done_txr_rst), - .DONE_RXR_RST (done_rxc_rst), - .DONE_RXC_RST (done_rxr_rst), - // Outputs - .M_AXIS_CQ_TREADY (m_axis_cq_tready_nc), - .M_AXIS_RC_TREADY (m_axis_rc_tready_nc), - .S_AXIS_CC_TVALID (s_axis_cc_tvalid_nc), - .S_AXIS_CC_TLAST (s_axis_cc_tlast_nc), - .S_AXIS_CC_TDATA (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_CC_TKEEP (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_CC_TUSER (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]), - .S_AXIS_RQ_TVALID (s_axis_rq_tvalid_nc), - .S_AXIS_RQ_TLAST (s_axis_rq_tlast_nc), - .S_AXIS_RQ_TDATA (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_RQ_TKEEP (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_RQ_TUSER (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]), - // Inputs - .M_AXIS_CQ_TVALID (m_axis_cq_tvalid_nc), - .M_AXIS_CQ_TLAST (m_axis_cq_tlast_nc), - .M_AXIS_CQ_TDATA (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_CQ_TKEEP (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_CQ_TUSER (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]), - .M_AXIS_RC_TVALID (m_axis_rc_tvalid_nc), - .M_AXIS_RC_TLAST (m_axis_rc_tlast_nc), - .M_AXIS_RC_TDATA (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_RC_TKEEP (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_RC_TUSER (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]), - .S_AXIS_CC_TREADY (s_axis_cc_tready_nc), - .S_AXIS_RQ_TREADY (s_axis_rq_tready_nc) - /*AUTOINST*/); - - riffa - #(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/ - /*AUTOINSTPARAM*/ - // Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_NUM_CHNL (C_NUM_CHNL), - .C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES), - .C_VENDOR (C_VENDOR), - .C_FPGA_NAME (C_FPGA_NAME), - .C_FPGA_ID (C_FPGA_ID), - .C_DEPTH_PACKETS (C_DEPTH_PACKETS)) - riffa_inst - (// Outputs - .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), - .TXC_DATA_VALID (txc_data_valid), - .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_META_VALID (txc_meta_valid), - .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]), - .TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]), - .TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]), - .TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]), - .TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]), - .TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]), - .TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]), - .TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]), - .TXC_META_EP (txc_meta_ep), - - .TXR_DATA_VALID (txr_data_valid), - .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), - .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_META_VALID (txr_meta_valid), - .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]), - .TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]), - .TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]), - .TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]), - .TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]), - .TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]), - .TXR_META_EP (txr_meta_ep), - - .INTR_MSI_REQUEST (intr_msi_request), - // Inputs - .CLK (clk), - .RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]), - .RXR_DATA_VALID (rxr_data_valid), - .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), - .RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]), - .RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]), - .RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]), - .RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]), - .RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]), - .RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]), - .RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]), - .RXR_META_EP (rxr_meta_ep), - - .RXC_DATA_VALID (rxc_data_valid), - .RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]), - .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]), - .RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]), - .RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]), - .RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]), - .RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]), - .RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]), - .RXC_META_EP (rxc_meta_ep), - - .TXC_DATA_READY (txc_data_ready), - .TXC_META_READY (txc_meta_ready), - .TXC_SENT (txc_sent), - - .TXR_DATA_READY (txr_data_ready), - .TXR_META_READY (txr_meta_ready), - .TXR_SENT (txr_sent), - - .CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]), - .CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable), - .CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]), - .CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]), - .CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]), - .CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]), - .CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable), - .CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel), - .CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]), - .CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]), - - .INTR_MSI_RDY (intr_msi_rdy), - - .DONE_TXC_RST (done_txc_rst), - .DONE_TXR_RST (done_txr_rst), - .RST_BUS (rst_in), - /*AUTOINST*/ - // Outputs - .RST_OUT (RST_OUT), - .CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]), - .CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]), - .CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]), - .CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]), - .CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]), - .CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]), - .CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]), - // Inputs - .CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]), - .CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]), - .CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]), - .CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]), - .CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]), - .CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]), - .CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]), - .CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]), - .CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0])); - -endmodule -// Local Variables: -// verilog-library-directories:("../../riffa_hdl/") -// End: - diff --git a/fpga/xilinx/Makefile b/fpga/xilinx/Makefile index 891bd65..1b4bfe5 100644 --- a/fpga/xilinx/Makefile +++ b/fpga/xilinx/Makefile @@ -39,8 +39,8 @@ # Author: Dustin Richmond (@darichmond) #----------------------------------------------------------------------- VENDOR:=xilinx -ULTRASCALE:=NetFPGA adm7V3 kcu105 vc709 vcu108 -CLASSIC:=ac701 kc705 vc707 zc706 +ULTRASCALE:=NetFPGA adm7V3 vc709 +CLASSIC:=vc707 zc706 BOARDS:=$(CLASSIC) $(ULTRASCALE) CURRENT_PATH := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))) .DEFAULT_GOAL=all diff --git a/fpga/xilinx/kcu105/KCU105_Gen1x8If64/Makefile b/fpga/xilinx/kcu105/KCU105_Gen1x8If64/Makefile deleted file mode 100644 index 795546b..0000000 --- a/fpga/xilinx/kcu105/KCU105_Gen1x8If64/Makefile +++ /dev/null @@ -1,62 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#----------------------------------------------------------------------- -# Filename: Makefile -# Version: 1.0 -# Description: Project-level makefile for building an example project -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------- -# This make file expects the following variables to be set: -# RIFFA_HDL_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory. -# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to -# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory -WIDTH=64 -TYPE=ultrascale -CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))) -PROJECT=$(shell basename $(CURRENT_PATH)) - -ifndef RIFFA_HDL_PATH - RIFFA_HDL_PATH:=../../../riffa_hdl -endif -ifndef BOARD_PATH - BOARD_PATH:=.. -endif -ifndef JOBS - JOBS=1 -endif -include $(RIFFA_HDL_PATH)/riffa.mk -include $(BOARD_PATH)/board.mk - -PROJECT_IP+=ip/PCIeGen1x8If64.xci diff --git a/fpga/xilinx/kcu105/KCU105_Gen1x8If64/bit/KCU105_Gen1x8If64.bit b/fpga/xilinx/kcu105/KCU105_Gen1x8If64/bit/KCU105_Gen1x8If64.bit deleted file mode 100644 index ffe60f0..0000000 Binary files a/fpga/xilinx/kcu105/KCU105_Gen1x8If64/bit/KCU105_Gen1x8If64.bit and /dev/null differ diff --git a/fpga/xilinx/kcu105/KCU105_Gen1x8If64/constr/KCU105_Gen1x8If64.xdc b/fpga/xilinx/kcu105/KCU105_Gen1x8If64/constr/KCU105_Gen1x8If64.xdc deleted file mode 100644 index 019982a..0000000 --- a/fpga/xilinx/kcu105/KCU105_Gen1x8If64/constr/KCU105_Gen1x8If64.xdc +++ /dev/null @@ -1,119 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#---------------------------------------------------------------------------- -# Filename: KCU105_Top.xdc -# Version: 1.00.a -# Verilog Standard: Verilog-2001 -# Description: Xilinx Design Constraints for the KCU105 board. -# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin -# -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------------- -# -######################################################################################################################### -# User Constraints -######################################################################################################################### - -############################################################################### -# User Time Names / User Time Groups / Time Specs -############################################################################### - -############################################################################### -# User Physical Constraints -############################################################################### - -set_property PACKAGE_PIN AP8 [get_ports {LED[0]}] -set_property PACKAGE_PIN H23 [get_ports {LED[1]}] -set_property PACKAGE_PIN P20 [get_ports {LED[2]}] -set_property PACKAGE_PIN P21 [get_ports {LED[3]}] -set_property PACKAGE_PIN N22 [get_ports {LED[4]}] -set_property PACKAGE_PIN M22 [get_ports {LED[5]}] -set_property PACKAGE_PIN R23 [get_ports {LED[6]}] -set_property PACKAGE_PIN P23 [get_ports {LED[7]}] - -set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[4]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[5]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[6]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[7]}] - -set_false_path -to [get_ports -filter NAME=~LED*] - -######################################################################################################################### -# End User Constraints -######################################################################################################################### -# -# -# -######################################################################################################################### -# PCIE Core Constraints -######################################################################################################################### - -# -# SYS reset (input) signal. The sys_reset_n signal should be -# obtained from the PCI Express interface if possible. For -# slot based form factors, a system reset signal is usually -# present on the connector. For cable based form factors, a -# system reset signal may not be available. In this case, the -# system reset signal must be generated locally by some form of -# supervisory circuit. You may change the IOSTANDARD and LOC -# to suit your requirements and VCCO voltage banking rules. -# Some 7 series devices do not have 3.3 V I/Os available. -# Therefore the appropriate level shift is required to operate -# with these devices that contain only 1.8 V banks. -# - -set_property LOC [get_package_pins -filter {PIN_FUNC == IO_T3U_N12_PERSTN0_65}] [get_ports PCIE_RESET_N] -set_property IOSTANDARD LVCMOS18 [get_ports PCIE_RESET_N] -set_property PULLUP true [get_ports PCIE_RESET_N] - -set_property LOC AB6 [get_cells refclk_ibuf] - -############################################################################### -# Timing Constraints -############################################################################### -create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O] - -############################################################################### -# Physical Constraints -############################################################################### - -set_false_path -from [get_ports PCIE_RESET_N] -############################################################################### -# End -############################################################################### diff --git a/fpga/xilinx/kcu105/KCU105_Gen1x8If64/hdl/KCU105_Gen1x8If64.v b/fpga/xilinx/kcu105/KCU105_Gen1x8If64/hdl/KCU105_Gen1x8If64.v deleted file mode 100644 index 55f4681..0000000 --- a/fpga/xilinx/kcu105/KCU105_Gen1x8If64/hdl/KCU105_Gen1x8If64.v +++ /dev/null @@ -1,491 +0,0 @@ -// ---------------------------------------------------------------------- -// Copyright (c) 2016, The Regents of the University of California All -// rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above -// copyright notice, this list of conditions and the following -// disclaimer in the documentation and/or other materials provided -// with the distribution. -// -// * Neither the name of The Regents of the University of California -// nor the names of its contributors may be used to endorse or -// promote products derived from this software without specific -// prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -// DAMAGE. -// ---------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// Filename: KCU105_Gen1x8If64.v -// Version: 1.00.a -// Verilog Standard: Verilog-2001 -// Description: Top level module for RIFFA 2.2 reference design for the -// the Xilinx KCU105 Development Board. -// Author: Dustin Richmond (@darichmond) -//----------------------------------------------------------------------------- -`include "functions.vh" -`include "riffa.vh" -`include "ultrascale.vh" -`timescale 1ps / 1ps -module KCU105_Gen1x8If64 - #(// Number of RIFFA Channels - parameter C_NUM_CHNL = 1, - // Number of PCIe Lanes - parameter C_NUM_LANES = 8, - // Settings from Vivado IP Generator - parameter C_PCI_DATA_WIDTH = 64, - parameter C_MAX_PAYLOAD_BYTES = 256, - parameter C_LOG_NUM_TAGS = 6) - (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP, - output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN, - input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP, - input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN, - - output [7:0] LED, - input PCIE_REFCLK_P, - input PCIE_REFCLK_N, - input PCIE_RESET_N); - - // Clocks, etc - wire user_lnk_up; - wire user_clk; - wire user_reset; - wire pcie_refclk; - wire pcie_refclk_by2; - wire pcie_reset_n; - - // Interface: RQ (TXC) - wire s_axis_rq_tlast; - wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata; - wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep; - wire s_axis_rq_tready; - wire s_axis_rq_tvalid; - // Interface: RC (RXC) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata; - wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser; - wire m_axis_rc_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep; - wire m_axis_rc_tvalid; - wire m_axis_rc_tready; - // Interface: CQ (RXR) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata; - wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser; - wire m_axis_cq_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep; - wire m_axis_cq_tvalid; - wire m_axis_cq_tready; - // Interface: CC (TXC) - wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata; - wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser; - wire s_axis_cc_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep; - wire s_axis_cc_tvalid; - wire s_axis_cc_tready; - - // Configuration (CFG) Interface - wire [3:0] pcie_rq_seq_num; - wire pcie_rq_seq_num_vld; - wire [5:0] pcie_rq_tag; - wire pcie_rq_tag_vld; - wire pcie_cq_np_req; - wire [5:0] pcie_cq_np_req_count; - - wire cfg_phy_link_down; - wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH - wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE - wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD - wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST - wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE - wire [5:0] cfg_function_power_state; // Ignorable but not removable - wire [11:0] cfg_vf_status; // Ignorable but not removable - wire [17:0] cfg_vf_power_state; // Ignorable but not removable - wire [1:0] cfg_link_power_state; // Ignorable but not removable - - // Error Reporting Interface - wire cfg_err_cor_out; - wire cfg_err_nonfatal_out; - wire cfg_err_fatal_out; - - wire cfg_ltr_enable; - wire [5:0] cfg_ltssm_state; - wire [1:0] cfg_rcb_status; - wire [1:0] cfg_dpa_substate_change; - wire [1:0] cfg_obff_enable; - wire cfg_pl_status_change; - - wire [1:0] cfg_tph_requester_enable; - wire [5:0] cfg_tph_st_mode; - wire [5:0] cfg_vf_tph_requester_enable; - wire [17:0] cfg_vf_tph_st_mode; - wire [7:0] cfg_fc_ph; - wire [11:0] cfg_fc_pd; - wire [7:0] cfg_fc_nph; - wire [11:0] cfg_fc_npd; - wire [7:0] cfg_fc_cplh; - wire [11:0] cfg_fc_cpld; - wire [2:0] cfg_fc_sel; - - // Interrupt Interface Signals - wire [3:0] cfg_interrupt_int; - wire [1:0] cfg_interrupt_pending; - wire cfg_interrupt_sent; - wire [1:0] cfg_interrupt_msi_enable; - wire [5:0] cfg_interrupt_msi_vf_enable; - wire [5:0] cfg_interrupt_msi_mmenable; - wire cfg_interrupt_msi_mask_update; - wire [31:0] cfg_interrupt_msi_data; - wire [3:0] cfg_interrupt_msi_select; - wire [31:0] cfg_interrupt_msi_int; - wire [63:0] cfg_interrupt_msi_pending_status; - wire cfg_interrupt_msi_sent; - wire cfg_interrupt_msi_fail; - wire [2:0] cfg_interrupt_msi_attr; - wire cfg_interrupt_msi_tph_present; - wire [1:0] cfg_interrupt_msi_tph_type; - wire [8:0] cfg_interrupt_msi_tph_st_tag; - wire [2:0] cfg_interrupt_msi_function_number; - - wire rst_out; - wire [C_NUM_CHNL-1:0] chnl_rx_clk; - wire [C_NUM_CHNL-1:0] chnl_rx; - wire [C_NUM_CHNL-1:0] chnl_rx_ack; - wire [C_NUM_CHNL-1:0] chnl_rx_last; - wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; - wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data; - wire [C_NUM_CHNL-1:0] chnl_rx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_rx_data_ren; - - wire [C_NUM_CHNL-1:0] chnl_tx_clk; - wire [C_NUM_CHNL-1:0] chnl_tx; - wire [C_NUM_CHNL-1:0] chnl_tx_ack; - wire [C_NUM_CHNL-1:0] chnl_tx_last; - wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; - wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data; - wire [C_NUM_CHNL-1:0] chnl_tx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_tx_data_ren; - - genvar chnl; - - IBUF - #() - pci_reset_n_ibuf - (.O(pcie_reset_n), - .I(PCIE_RESET_N)); - - IBUFDS_GTE3 - #() - refclk_ibuf - (.O(pcie_refclk), - .ODIV2(pcie_refclk_by2), - .I(PCIE_REFCLK_P), - .CEB(1'b0), - .IB(PCIE_REFCLK_N)); - - OBUF - #() - led_0_obuf - (.O(LED[0]), - .I(cfg_ltssm_state[0])); - OBUF - #() - led_1_obuf - (.O(LED[1]), - .I(cfg_ltssm_state[1])); - OBUF - #() - led_2_obuf - (.O(LED[2]), - .I(cfg_ltssm_state[2])); - OBUF - #() - led_3_obuf - (.O(LED[3]), - .I(cfg_ltssm_state[3])); - OBUF - #() - led_4_obuf - (.O(LED[4]), - .I(cfg_ltssm_state[4])); - OBUF - #() - led_5_obuf - (.O(LED[5]), - .I(cfg_ltssm_state[5])); - OBUF - #() - led_6_obuf - (.O(LED[6]), - .I(user_reset)); - OBUF - #() - led_7_obuf - (.O(LED[7]), - .I(rst_out)); - - // Core Top Level Wrapper - PCIeGen1x8If64 - #() - pcie3_7x_0_i - (//--------------------------------------------------------------------- - // PCI Express (pci_exp) Interface - //--------------------------------------------------------------------- - .pci_exp_txn ( PCI_EXP_TXN ), - .pci_exp_txp ( PCI_EXP_TXP ), - .pci_exp_rxn ( PCI_EXP_RXN ), - .pci_exp_rxp ( PCI_EXP_RXP ), - - //--------------------------------------------------------------------- - // AXI Interface - //--------------------------------------------------------------------- - .user_clk ( user_clk ), - .user_reset ( user_reset ), - .user_lnk_up ( user_lnk_up ), - - .s_axis_rq_tlast ( s_axis_rq_tlast ), - .s_axis_rq_tdata ( s_axis_rq_tdata ), - .s_axis_rq_tuser ( s_axis_rq_tuser ), - .s_axis_rq_tkeep ( s_axis_rq_tkeep ), - .s_axis_rq_tready ( s_axis_rq_tready ), - .s_axis_rq_tvalid ( s_axis_rq_tvalid ), - - .m_axis_rc_tdata ( m_axis_rc_tdata ), - .m_axis_rc_tuser ( m_axis_rc_tuser ), - .m_axis_rc_tlast ( m_axis_rc_tlast ), - .m_axis_rc_tkeep ( m_axis_rc_tkeep ), - .m_axis_rc_tvalid ( m_axis_rc_tvalid ), - .m_axis_rc_tready ( {22{m_axis_rc_tready}} ), - - .m_axis_cq_tdata ( m_axis_cq_tdata ), - .m_axis_cq_tuser ( m_axis_cq_tuser ), - .m_axis_cq_tlast ( m_axis_cq_tlast ), - .m_axis_cq_tkeep ( m_axis_cq_tkeep ), - .m_axis_cq_tvalid ( m_axis_cq_tvalid ), - .m_axis_cq_tready ( {22{m_axis_cq_tready}} ), - - .s_axis_cc_tdata ( s_axis_cc_tdata ), - .s_axis_cc_tuser ( s_axis_cc_tuser ), - .s_axis_cc_tlast ( s_axis_cc_tlast ), - .s_axis_cc_tkeep ( s_axis_cc_tkeep ), - .s_axis_cc_tvalid ( s_axis_cc_tvalid ), - .s_axis_cc_tready ( s_axis_cc_tready ), - - //--------------------------------------------------------------------- - // Configuration (CFG) Interface - //--------------------------------------------------------------------- - .pcie_rq_seq_num ( pcie_rq_seq_num ), - .pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ), - .pcie_rq_tag ( pcie_rq_tag ), - .pcie_rq_tag_vld ( pcie_rq_tag_vld ), - .pcie_cq_np_req ( pcie_cq_np_req ), - .pcie_cq_np_req_count ( pcie_cq_np_req_count ), - .cfg_phy_link_down ( cfg_phy_link_down ), - .cfg_phy_link_status ( cfg_phy_link_status), - .cfg_negotiated_width ( cfg_negotiated_width ), - .cfg_current_speed ( cfg_current_speed ), - .cfg_max_payload ( cfg_max_payload ), - .cfg_max_read_req ( cfg_max_read_req ), - .cfg_function_status ( cfg_function_status ), - .cfg_function_power_state ( cfg_function_power_state ), - .cfg_vf_status ( cfg_vf_status ), - .cfg_vf_power_state ( cfg_vf_power_state ), - .cfg_link_power_state ( cfg_link_power_state ), - // Error Reporting Interface - .cfg_err_cor_out ( cfg_err_cor_out ), - .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), - .cfg_err_fatal_out ( cfg_err_fatal_out ), - .cfg_ltr_enable ( cfg_ltr_enable ), - .cfg_ltssm_state ( cfg_ltssm_state ), - .cfg_rcb_status ( cfg_rcb_status ), - .cfg_dpa_substate_change ( cfg_dpa_substate_change ), - .cfg_obff_enable ( cfg_obff_enable ), - .cfg_pl_status_change ( cfg_pl_status_change ), - .cfg_tph_requester_enable ( cfg_tph_requester_enable ), - .cfg_tph_st_mode ( cfg_tph_st_mode ), - .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), - .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), - .cfg_fc_ph ( cfg_fc_ph ), - .cfg_fc_pd ( cfg_fc_pd ), - .cfg_fc_nph ( cfg_fc_nph ), - .cfg_fc_npd ( cfg_fc_npd ), - .cfg_fc_cplh ( cfg_fc_cplh ), - .cfg_fc_cpld ( cfg_fc_cpld ), - .cfg_fc_sel ( cfg_fc_sel ), - //--------------------------------------------------------------------- - // EP Only - //--------------------------------------------------------------------- - // Interrupt Interface Signals - .cfg_interrupt_int ( cfg_interrupt_int ), - .cfg_interrupt_pending ( cfg_interrupt_pending ), - .cfg_interrupt_sent ( cfg_interrupt_sent ), - .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ), - .cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ), - .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), - .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), - .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), - .cfg_interrupt_msi_select ( cfg_interrupt_msi_select ), - .cfg_interrupt_msi_int ( cfg_interrupt_msi_int ), - .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ), - .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), - .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), - .cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ), - .cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ), - .cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ), - .cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ), - .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ), - .cfg_interrupt_msi_pending_status_function_num ( 4'b0), - .cfg_interrupt_msi_pending_status_data_enable ( 1'b0), - - - //--------------------------------------------------------------------------------------// - // Reset Pass Through Signals - // - Only used for PCIe_X0Y0 - //--------------------------------------------------------------------------------------// - .pcie_perstn0_out (pcie_reset_n_core), - .pcie_perstn1_in (1'b0), - .pcie_perstn1_out (), - - //--------------------------------------------------------------------- - // System(SYS) Interface - //--------------------------------------------------------------------- - .sys_clk (pcie_refclk_by2), - .sys_clk_gt (pcie_refclk), - .sys_reset (pcie_reset_n)); - - riffa_wrapper_kcu105 - #(/*AUTOINSTPARAM*/ - // Parameters - .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), - .C_NUM_CHNL (C_NUM_CHNL), - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES)) - riffa - (// Outputs - .M_AXIS_CQ_TREADY (m_axis_cq_tready), - .M_AXIS_RC_TREADY (m_axis_rc_tready), - .S_AXIS_CC_TVALID (s_axis_cc_tvalid), - .S_AXIS_CC_TLAST (s_axis_cc_tlast), - .S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]), - .S_AXIS_RQ_TVALID (s_axis_rq_tvalid), - .S_AXIS_RQ_TLAST (s_axis_rq_tlast), - .S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]), - .USER_CLK (user_clk), - .USER_RESET (user_reset), - .CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]), - .CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]), - .CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]), - .CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]), - .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]), - .CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]), - .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present), - .CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]), - .CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]), - .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]), - .CFG_FC_SEL (cfg_fc_sel[2:0]), - .PCIE_CQ_NP_REQ (pcie_cq_np_req), - .RST_OUT (rst_out), - .CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]), - .CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]), - .CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]), - .CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]), - .CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]), - // Inputs - .M_AXIS_CQ_TVALID (m_axis_cq_tvalid), - .M_AXIS_CQ_TLAST (m_axis_cq_tlast), - .M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]), - .M_AXIS_RC_TVALID (m_axis_rc_tvalid), - .M_AXIS_RC_TLAST (m_axis_rc_tlast), - .M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]), - .S_AXIS_CC_TREADY (s_axis_cc_tready), - .S_AXIS_RQ_TREADY (s_axis_rq_tready), - .CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]), - .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update), - .CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]), - .CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent), - .CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail), - .CFG_FC_CPLH (cfg_fc_cplh[7:0]), - .CFG_FC_CPLD (cfg_fc_cpld[11:0]), - .CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]), - .CFG_CURRENT_SPEED (cfg_current_speed[2:0]), - .CFG_MAX_PAYLOAD (cfg_max_payload[2:0]), - .CFG_MAX_READ_REQ (cfg_max_read_req[2:0]), - .CFG_FUNCTION_STATUS (cfg_function_status[7:0]), - .CFG_RCB_STATUS (cfg_rcb_status[1:0]), - .CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]), - .CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]), - .CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]), - .CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]), - .CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]), - .CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]), - .CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])); - - generate - for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels - chnl_tester - #(/*AUTOINSTPARAM*/ - // Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH)) - module1 - (.CLK(user_clk), - .RST(rst_out), // riffa_reset includes riffa_endpoint resets - // Rx interface - .CHNL_RX_CLK(chnl_rx_clk[chnl]), - .CHNL_RX(chnl_rx[chnl]), - .CHNL_RX_ACK(chnl_rx_ack[chnl]), - .CHNL_RX_LAST(chnl_rx_last[chnl]), - .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), - .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), - .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), - .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), - .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]), - // Tx interface - .CHNL_TX_CLK(chnl_tx_clk[chnl]), - .CHNL_TX(chnl_tx[chnl]), - .CHNL_TX_ACK(chnl_tx_ack[chnl]), - .CHNL_TX_LAST(chnl_tx_last[chnl]), - .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), - .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), - .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), - .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), - .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl]) - /*AUTOINST*/); - end - endgenerate -endmodule -// Local Variables: -// verilog-library-directories:("../../../../riffa_hdl/" "../../") -// End: - diff --git a/fpga/xilinx/kcu105/KCU105_Gen1x8If64/ip/PCIeGen1x8If64.xci b/fpga/xilinx/kcu105/KCU105_Gen1x8If64/ip/PCIeGen1x8If64.xci deleted file mode 100644 index d27e2bd..0000000 --- a/fpga/xilinx/kcu105/KCU105_Gen1x8If64/ip/PCIeGen1x8If64.xci +++ /dev/null @@ -1,729 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - PCIeGen1x8If64 - - - FALSE - FALSE - FALSE - TRUE - 0x00000 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - TRUE - FALSE - TRUE - FALSE - 16KB - 1 - 64 - TRUE - 0 - FALSE - FALSE - FALSE - FALSE - 0x000 - NONE - FALSE - TRUE - FALSE - FALSE - NONE - 2 - 2.0 - FALSE - FALSE - FALSE - 0x000 - 0x000 - 0x00 - 0x03 - 0x4 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x058000 - 0x8018 - FALSE - FALSE - FALSE - FALSE - 0x0 - FALSE - TRUE - FALSE - 0x2 - 0x000 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x000 - 0x00 - FALSE - 0x0 - 0 - TRUE - 0x000 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0xC0 - 0x000 - 0x90 - FALSE - FALSE - FALSE - FALSE - FALSE - 0x000 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x0 - 0x0000 - 0x0000 - 0x00000553 - 0x0000 - 0x0007 - 0x10EE - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0x10EE - FALSE - FALSE - 0x000 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x058000 - 0x8011 - 0x2 - 0x000 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x000 - 0x00 - FALSE - 0x0 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - 0x000 - 0x00 - FALSE - 0x000 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x0 - 0x0000 - 0x0001 - 0x00000553 - 0x0000 - 0x0007 - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 4 - FALSE - 0 - FALSE - 1 - 8 - TRUE - FALSE - 0 - 0 - GTH_Quad_224 - 1 - 0x00000000 - FALSE - 0 - 0x000 - 0x00 - 0x028 - 0x20 - 0x198 - 0x20 - FALSE - FALSE - 0x0 - FALSE - FALSE - 3 - 0x000 - 0x80 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - FALSE - 1 - 0 - 0 - 0 - 0 - 0 - 0 - Production - 1 - true - false - PCIeGen1x8If64 - 15 - false - false - 058000 - 8018 - false - false - false - 00_Not_Supported - false - false - NONE - true - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - false - false - false - false - 00 - 0 - N/A - 0000 - 00000553 - 0000 - 0007 - 10EE - false - false - false - 058000 - 8011 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 0 - N/A - 0001 - 00000553 - 0000 - 0007 - false - 4 - 2.5_GT/s - X8 - 100_MHz - Default - 0 - 0 - false - false - 1 - false - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - DWORD_Aligned - No_ASPM - 250 - true - 2FFFF - false - 64_bit - false - false - true - false - true - false - 250 - true - PCI_Express_Endpoint_device - false - false - true - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - None - Advanced - X0Y0 - false - Extreme - false - true - false - false - true - false - Kilobytes - 1 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Simple_communication_controllers - 05 - 00 - 80 - 512_bytes - false - false - false - Kilobytes - 2 - false - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - 0 - Generic_XT_compatible_serial_controller - false - false - true - false - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Simple_communication_controllers - 05 - 00 - 80 - 512_bytes - false - false - false - Kilobytes - 2 - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Generic_XT_compatible_serial_controller - false - false - CPLL - false - GTH_Quad_224 - ACTIVE LOW - None - true - false - 10EE - KCU105 - kintexu - xilinx.com:kcu105:part0:1.0 - xcku040 - ffva1156 - VERILOG - - MIXED - -2 - E - TRUE - TRUE - IP_Flow - 1 - TRUE - . - - . - 2015.4 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/xilinx/kcu105/KCU105_Gen1x8If64/prj/KCU105_Gen1x8If64.xpr b/fpga/xilinx/kcu105/KCU105_Gen1x8If64/prj/KCU105_Gen1x8If64.xpr deleted file mode 100644 index 73033ce..0000000 --- a/fpga/xilinx/kcu105/KCU105_Gen1x8If64/prj/KCU105_Gen1x8If64.xpr +++ /dev/null @@ -1,810 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/xilinx/kcu105/KCU105_Gen2x8If128/Makefile b/fpga/xilinx/kcu105/KCU105_Gen2x8If128/Makefile deleted file mode 100644 index d760cff..0000000 --- a/fpga/xilinx/kcu105/KCU105_Gen2x8If128/Makefile +++ /dev/null @@ -1,62 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#----------------------------------------------------------------------- -# Filename: Makefile -# Version: 1.0 -# Description: Project-level makefile for building an example project -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------- -# This make file expects the following variables to be set: -# RIFFA_HDL_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory. -# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to -# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory -WIDTH=128 -TYPE=ultrascale -CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))) -PROJECT=$(shell basename $(CURRENT_PATH)) - -ifndef RIFFA_HDL_PATH - RIFFA_HDL_PATH:=../../../riffa_hdl -endif -ifndef BOARD_PATH - BOARD_PATH:=.. -endif -ifndef JOBS - JOBS=1 -endif -include $(RIFFA_HDL_PATH)/riffa.mk -include $(BOARD_PATH)/board.mk - -PROJECT_IP+=ip/PCIeGen2x8If128.xci diff --git a/fpga/xilinx/kcu105/KCU105_Gen2x8If128/bit/KCU105_Gen2x8If128.bit b/fpga/xilinx/kcu105/KCU105_Gen2x8If128/bit/KCU105_Gen2x8If128.bit deleted file mode 100644 index a64d46e..0000000 Binary files a/fpga/xilinx/kcu105/KCU105_Gen2x8If128/bit/KCU105_Gen2x8If128.bit and /dev/null differ diff --git a/fpga/xilinx/kcu105/KCU105_Gen2x8If128/constr/KCU105_Gen2x8If128.xdc b/fpga/xilinx/kcu105/KCU105_Gen2x8If128/constr/KCU105_Gen2x8If128.xdc deleted file mode 100644 index 019982a..0000000 --- a/fpga/xilinx/kcu105/KCU105_Gen2x8If128/constr/KCU105_Gen2x8If128.xdc +++ /dev/null @@ -1,119 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#---------------------------------------------------------------------------- -# Filename: KCU105_Top.xdc -# Version: 1.00.a -# Verilog Standard: Verilog-2001 -# Description: Xilinx Design Constraints for the KCU105 board. -# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin -# -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------------- -# -######################################################################################################################### -# User Constraints -######################################################################################################################### - -############################################################################### -# User Time Names / User Time Groups / Time Specs -############################################################################### - -############################################################################### -# User Physical Constraints -############################################################################### - -set_property PACKAGE_PIN AP8 [get_ports {LED[0]}] -set_property PACKAGE_PIN H23 [get_ports {LED[1]}] -set_property PACKAGE_PIN P20 [get_ports {LED[2]}] -set_property PACKAGE_PIN P21 [get_ports {LED[3]}] -set_property PACKAGE_PIN N22 [get_ports {LED[4]}] -set_property PACKAGE_PIN M22 [get_ports {LED[5]}] -set_property PACKAGE_PIN R23 [get_ports {LED[6]}] -set_property PACKAGE_PIN P23 [get_ports {LED[7]}] - -set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[4]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[5]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[6]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[7]}] - -set_false_path -to [get_ports -filter NAME=~LED*] - -######################################################################################################################### -# End User Constraints -######################################################################################################################### -# -# -# -######################################################################################################################### -# PCIE Core Constraints -######################################################################################################################### - -# -# SYS reset (input) signal. The sys_reset_n signal should be -# obtained from the PCI Express interface if possible. For -# slot based form factors, a system reset signal is usually -# present on the connector. For cable based form factors, a -# system reset signal may not be available. In this case, the -# system reset signal must be generated locally by some form of -# supervisory circuit. You may change the IOSTANDARD and LOC -# to suit your requirements and VCCO voltage banking rules. -# Some 7 series devices do not have 3.3 V I/Os available. -# Therefore the appropriate level shift is required to operate -# with these devices that contain only 1.8 V banks. -# - -set_property LOC [get_package_pins -filter {PIN_FUNC == IO_T3U_N12_PERSTN0_65}] [get_ports PCIE_RESET_N] -set_property IOSTANDARD LVCMOS18 [get_ports PCIE_RESET_N] -set_property PULLUP true [get_ports PCIE_RESET_N] - -set_property LOC AB6 [get_cells refclk_ibuf] - -############################################################################### -# Timing Constraints -############################################################################### -create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O] - -############################################################################### -# Physical Constraints -############################################################################### - -set_false_path -from [get_ports PCIE_RESET_N] -############################################################################### -# End -############################################################################### diff --git a/fpga/xilinx/kcu105/KCU105_Gen2x8If128/hdl/KCU105_Gen2x8If128.v b/fpga/xilinx/kcu105/KCU105_Gen2x8If128/hdl/KCU105_Gen2x8If128.v deleted file mode 100644 index c8efb2b..0000000 --- a/fpga/xilinx/kcu105/KCU105_Gen2x8If128/hdl/KCU105_Gen2x8If128.v +++ /dev/null @@ -1,491 +0,0 @@ -// ---------------------------------------------------------------------- -// Copyright (c) 2016, The Regents of the University of California All -// rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above -// copyright notice, this list of conditions and the following -// disclaimer in the documentation and/or other materials provided -// with the distribution. -// -// * Neither the name of The Regents of the University of California -// nor the names of its contributors may be used to endorse or -// promote products derived from this software without specific -// prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -// DAMAGE. -// ---------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// Filename: KCU105_Gen2x8If128.v -// Version: 1.00.a -// Verilog Standard: Verilog-2001 -// Description: Top level module for RIFFA 2.2 reference design for the -// the Xilinx KCU105 Development Board. -// Author: Dustin Richmond (@darichmond) -//----------------------------------------------------------------------------- -`include "functions.vh" -`include "riffa.vh" -`include "ultrascale.vh" -`timescale 1ps / 1ps -module KCU105_Gen2x8If128 - #(// Number of RIFFA Channels - parameter C_NUM_CHNL = 1, - // Number of PCIe Lanes - parameter C_NUM_LANES = 8, - // Settings from Vivado IP Generator - parameter C_PCI_DATA_WIDTH = 128, - parameter C_MAX_PAYLOAD_BYTES = 256, - parameter C_LOG_NUM_TAGS = 6) - (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP, - output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN, - input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP, - input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN, - - output [7:0] LED, - input PCIE_REFCLK_P, - input PCIE_REFCLK_N, - input PCIE_RESET_N); - - // Clocks, etc - wire user_lnk_up; - wire user_clk; - wire user_reset; - wire pcie_refclk; - wire pcie_refclk_by2; - wire pcie_reset_n; - - // Interface: RQ (TXC) - wire s_axis_rq_tlast; - wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata; - wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep; - wire s_axis_rq_tready; - wire s_axis_rq_tvalid; - // Interface: RC (RXC) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata; - wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser; - wire m_axis_rc_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep; - wire m_axis_rc_tvalid; - wire m_axis_rc_tready; - // Interface: CQ (RXR) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata; - wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser; - wire m_axis_cq_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep; - wire m_axis_cq_tvalid; - wire m_axis_cq_tready; - // Interface: CC (TXC) - wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata; - wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser; - wire s_axis_cc_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep; - wire s_axis_cc_tvalid; - wire s_axis_cc_tready; - - // Configuration (CFG) Interface - wire [3:0] pcie_rq_seq_num; - wire pcie_rq_seq_num_vld; - wire [5:0] pcie_rq_tag; - wire pcie_rq_tag_vld; - wire pcie_cq_np_req; - wire [5:0] pcie_cq_np_req_count; - - wire cfg_phy_link_down; - wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH - wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE - wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD - wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST - wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE - wire [5:0] cfg_function_power_state; // Ignorable but not removable - wire [11:0] cfg_vf_status; // Ignorable but not removable - wire [17:0] cfg_vf_power_state; // Ignorable but not removable - wire [1:0] cfg_link_power_state; // Ignorable but not removable - - // Error Reporting Interface - wire cfg_err_cor_out; - wire cfg_err_nonfatal_out; - wire cfg_err_fatal_out; - - wire cfg_ltr_enable; - wire [5:0] cfg_ltssm_state; - wire [1:0] cfg_rcb_status; - wire [1:0] cfg_dpa_substate_change; - wire [1:0] cfg_obff_enable; - wire cfg_pl_status_change; - - wire [1:0] cfg_tph_requester_enable; - wire [5:0] cfg_tph_st_mode; - wire [5:0] cfg_vf_tph_requester_enable; - wire [17:0] cfg_vf_tph_st_mode; - wire [7:0] cfg_fc_ph; - wire [11:0] cfg_fc_pd; - wire [7:0] cfg_fc_nph; - wire [11:0] cfg_fc_npd; - wire [7:0] cfg_fc_cplh; - wire [11:0] cfg_fc_cpld; - wire [2:0] cfg_fc_sel; - - // Interrupt Interface Signals - wire [3:0] cfg_interrupt_int; - wire [1:0] cfg_interrupt_pending; - wire cfg_interrupt_sent; - wire [1:0] cfg_interrupt_msi_enable; - wire [5:0] cfg_interrupt_msi_vf_enable; - wire [5:0] cfg_interrupt_msi_mmenable; - wire cfg_interrupt_msi_mask_update; - wire [31:0] cfg_interrupt_msi_data; - wire [3:0] cfg_interrupt_msi_select; - wire [31:0] cfg_interrupt_msi_int; - wire [63:0] cfg_interrupt_msi_pending_status; - wire cfg_interrupt_msi_sent; - wire cfg_interrupt_msi_fail; - wire [2:0] cfg_interrupt_msi_attr; - wire cfg_interrupt_msi_tph_present; - wire [1:0] cfg_interrupt_msi_tph_type; - wire [8:0] cfg_interrupt_msi_tph_st_tag; - wire [2:0] cfg_interrupt_msi_function_number; - - wire rst_out; - wire [C_NUM_CHNL-1:0] chnl_rx_clk; - wire [C_NUM_CHNL-1:0] chnl_rx; - wire [C_NUM_CHNL-1:0] chnl_rx_ack; - wire [C_NUM_CHNL-1:0] chnl_rx_last; - wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; - wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data; - wire [C_NUM_CHNL-1:0] chnl_rx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_rx_data_ren; - - wire [C_NUM_CHNL-1:0] chnl_tx_clk; - wire [C_NUM_CHNL-1:0] chnl_tx; - wire [C_NUM_CHNL-1:0] chnl_tx_ack; - wire [C_NUM_CHNL-1:0] chnl_tx_last; - wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; - wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data; - wire [C_NUM_CHNL-1:0] chnl_tx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_tx_data_ren; - - genvar chnl; - - IBUF - #() - pci_reset_n_ibuf - (.O(pcie_reset_n), - .I(PCIE_RESET_N)); - - IBUFDS_GTE3 - #() - refclk_ibuf - (.O(pcie_refclk), - .ODIV2(pcie_refclk_by2), - .I(PCIE_REFCLK_P), - .CEB(1'b0), - .IB(PCIE_REFCLK_N)); - - OBUF - #() - led_0_obuf - (.O(LED[0]), - .I(cfg_ltssm_state[0])); - OBUF - #() - led_1_obuf - (.O(LED[1]), - .I(cfg_ltssm_state[1])); - OBUF - #() - led_2_obuf - (.O(LED[2]), - .I(cfg_ltssm_state[2])); - OBUF - #() - led_3_obuf - (.O(LED[3]), - .I(cfg_ltssm_state[3])); - OBUF - #() - led_4_obuf - (.O(LED[4]), - .I(cfg_ltssm_state[4])); - OBUF - #() - led_5_obuf - (.O(LED[5]), - .I(cfg_ltssm_state[5])); - OBUF - #() - led_6_obuf - (.O(LED[6]), - .I(user_reset)); - OBUF - #() - led_7_obuf - (.O(LED[7]), - .I(rst_out)); - - // Core Top Level Wrapper - PCIeGen2x8If128 - #() - pcie3_7x_0_i - (//--------------------------------------------------------------------- - // PCI Express (pci_exp) Interface - //--------------------------------------------------------------------- - .pci_exp_txn ( PCI_EXP_TXN ), - .pci_exp_txp ( PCI_EXP_TXP ), - .pci_exp_rxn ( PCI_EXP_RXN ), - .pci_exp_rxp ( PCI_EXP_RXP ), - - //--------------------------------------------------------------------- - // AXI Interface - //--------------------------------------------------------------------- - .user_clk ( user_clk ), - .user_reset ( user_reset ), - .user_lnk_up ( user_lnk_up ), - - .s_axis_rq_tlast ( s_axis_rq_tlast ), - .s_axis_rq_tdata ( s_axis_rq_tdata ), - .s_axis_rq_tuser ( s_axis_rq_tuser ), - .s_axis_rq_tkeep ( s_axis_rq_tkeep ), - .s_axis_rq_tready ( s_axis_rq_tready ), - .s_axis_rq_tvalid ( s_axis_rq_tvalid ), - - .m_axis_rc_tdata ( m_axis_rc_tdata ), - .m_axis_rc_tuser ( m_axis_rc_tuser ), - .m_axis_rc_tlast ( m_axis_rc_tlast ), - .m_axis_rc_tkeep ( m_axis_rc_tkeep ), - .m_axis_rc_tvalid ( m_axis_rc_tvalid ), - .m_axis_rc_tready ( {22{m_axis_rc_tready}} ), - - .m_axis_cq_tdata ( m_axis_cq_tdata ), - .m_axis_cq_tuser ( m_axis_cq_tuser ), - .m_axis_cq_tlast ( m_axis_cq_tlast ), - .m_axis_cq_tkeep ( m_axis_cq_tkeep ), - .m_axis_cq_tvalid ( m_axis_cq_tvalid ), - .m_axis_cq_tready ( {22{m_axis_cq_tready}} ), - - .s_axis_cc_tdata ( s_axis_cc_tdata ), - .s_axis_cc_tuser ( s_axis_cc_tuser ), - .s_axis_cc_tlast ( s_axis_cc_tlast ), - .s_axis_cc_tkeep ( s_axis_cc_tkeep ), - .s_axis_cc_tvalid ( s_axis_cc_tvalid ), - .s_axis_cc_tready ( s_axis_cc_tready ), - - //--------------------------------------------------------------------- - // Configuration (CFG) Interface - //--------------------------------------------------------------------- - .pcie_rq_seq_num ( pcie_rq_seq_num ), - .pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ), - .pcie_rq_tag ( pcie_rq_tag ), - .pcie_rq_tag_vld ( pcie_rq_tag_vld ), - .pcie_cq_np_req ( pcie_cq_np_req ), - .pcie_cq_np_req_count ( pcie_cq_np_req_count ), - .cfg_phy_link_down ( cfg_phy_link_down ), - .cfg_phy_link_status ( cfg_phy_link_status), - .cfg_negotiated_width ( cfg_negotiated_width ), - .cfg_current_speed ( cfg_current_speed ), - .cfg_max_payload ( cfg_max_payload ), - .cfg_max_read_req ( cfg_max_read_req ), - .cfg_function_status ( cfg_function_status ), - .cfg_function_power_state ( cfg_function_power_state ), - .cfg_vf_status ( cfg_vf_status ), - .cfg_vf_power_state ( cfg_vf_power_state ), - .cfg_link_power_state ( cfg_link_power_state ), - // Error Reporting Interface - .cfg_err_cor_out ( cfg_err_cor_out ), - .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), - .cfg_err_fatal_out ( cfg_err_fatal_out ), - .cfg_ltr_enable ( cfg_ltr_enable ), - .cfg_ltssm_state ( cfg_ltssm_state ), - .cfg_rcb_status ( cfg_rcb_status ), - .cfg_dpa_substate_change ( cfg_dpa_substate_change ), - .cfg_obff_enable ( cfg_obff_enable ), - .cfg_pl_status_change ( cfg_pl_status_change ), - .cfg_tph_requester_enable ( cfg_tph_requester_enable ), - .cfg_tph_st_mode ( cfg_tph_st_mode ), - .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), - .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), - .cfg_fc_ph ( cfg_fc_ph ), - .cfg_fc_pd ( cfg_fc_pd ), - .cfg_fc_nph ( cfg_fc_nph ), - .cfg_fc_npd ( cfg_fc_npd ), - .cfg_fc_cplh ( cfg_fc_cplh ), - .cfg_fc_cpld ( cfg_fc_cpld ), - .cfg_fc_sel ( cfg_fc_sel ), - //--------------------------------------------------------------------- - // EP Only - //--------------------------------------------------------------------- - // Interrupt Interface Signals - .cfg_interrupt_int ( cfg_interrupt_int ), - .cfg_interrupt_pending ( cfg_interrupt_pending ), - .cfg_interrupt_sent ( cfg_interrupt_sent ), - .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ), - .cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ), - .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), - .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), - .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), - .cfg_interrupt_msi_select ( cfg_interrupt_msi_select ), - .cfg_interrupt_msi_int ( cfg_interrupt_msi_int ), - .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ), - .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), - .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), - .cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ), - .cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ), - .cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ), - .cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ), - .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ), - .cfg_interrupt_msi_pending_status_function_num ( 4'b0), - .cfg_interrupt_msi_pending_status_data_enable ( 1'b0), - - - //--------------------------------------------------------------------------------------// - // Reset Pass Through Signals - // - Only used for PCIe_X0Y0 - //--------------------------------------------------------------------------------------// - .pcie_perstn0_out (pcie_reset_n_core), - .pcie_perstn1_in (1'b0), - .pcie_perstn1_out (), - - //--------------------------------------------------------------------- - // System(SYS) Interface - //--------------------------------------------------------------------- - .sys_clk (pcie_refclk_by2), - .sys_clk_gt (pcie_refclk), - .sys_reset (pcie_reset_n)); - - riffa_wrapper_kcu105 - #(/*AUTOINSTPARAM*/ - // Parameters - .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), - .C_NUM_CHNL (C_NUM_CHNL), - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES)) - riffa - (// Outputs - .M_AXIS_CQ_TREADY (m_axis_cq_tready), - .M_AXIS_RC_TREADY (m_axis_rc_tready), - .S_AXIS_CC_TVALID (s_axis_cc_tvalid), - .S_AXIS_CC_TLAST (s_axis_cc_tlast), - .S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]), - .S_AXIS_RQ_TVALID (s_axis_rq_tvalid), - .S_AXIS_RQ_TLAST (s_axis_rq_tlast), - .S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]), - .USER_CLK (user_clk), - .USER_RESET (user_reset), - .CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]), - .CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]), - .CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]), - .CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]), - .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]), - .CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]), - .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present), - .CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]), - .CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]), - .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]), - .CFG_FC_SEL (cfg_fc_sel[2:0]), - .PCIE_CQ_NP_REQ (pcie_cq_np_req), - .RST_OUT (rst_out), - .CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]), - .CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]), - .CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]), - .CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]), - .CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]), - // Inputs - .M_AXIS_CQ_TVALID (m_axis_cq_tvalid), - .M_AXIS_CQ_TLAST (m_axis_cq_tlast), - .M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]), - .M_AXIS_RC_TVALID (m_axis_rc_tvalid), - .M_AXIS_RC_TLAST (m_axis_rc_tlast), - .M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]), - .S_AXIS_CC_TREADY (s_axis_cc_tready), - .S_AXIS_RQ_TREADY (s_axis_rq_tready), - .CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]), - .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update), - .CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]), - .CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent), - .CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail), - .CFG_FC_CPLH (cfg_fc_cplh[7:0]), - .CFG_FC_CPLD (cfg_fc_cpld[11:0]), - .CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]), - .CFG_CURRENT_SPEED (cfg_current_speed[2:0]), - .CFG_MAX_PAYLOAD (cfg_max_payload[2:0]), - .CFG_MAX_READ_REQ (cfg_max_read_req[2:0]), - .CFG_FUNCTION_STATUS (cfg_function_status[7:0]), - .CFG_RCB_STATUS (cfg_rcb_status[1:0]), - .CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]), - .CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]), - .CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]), - .CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]), - .CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]), - .CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]), - .CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])); - - generate - for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels - chnl_tester - #(/*AUTOINSTPARAM*/ - // Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH)) - module1 - (.CLK(user_clk), - .RST(rst_out), // riffa_reset includes riffa_endpoint resets - // Rx interface - .CHNL_RX_CLK(chnl_rx_clk[chnl]), - .CHNL_RX(chnl_rx[chnl]), - .CHNL_RX_ACK(chnl_rx_ack[chnl]), - .CHNL_RX_LAST(chnl_rx_last[chnl]), - .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), - .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), - .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), - .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), - .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]), - // Tx interface - .CHNL_TX_CLK(chnl_tx_clk[chnl]), - .CHNL_TX(chnl_tx[chnl]), - .CHNL_TX_ACK(chnl_tx_ack[chnl]), - .CHNL_TX_LAST(chnl_tx_last[chnl]), - .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), - .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), - .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), - .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), - .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl]) - /*AUTOINST*/); - end - endgenerate -endmodule -// Local Variables: -// verilog-library-directories:("../../../../riffa_hdl/" "../../") -// End: - diff --git a/fpga/xilinx/kcu105/KCU105_Gen2x8If128/ip/PCIeGen2x8If128.xci b/fpga/xilinx/kcu105/KCU105_Gen2x8If128/ip/PCIeGen2x8If128.xci deleted file mode 100644 index c0aa3d0..0000000 --- a/fpga/xilinx/kcu105/KCU105_Gen2x8If128/ip/PCIeGen2x8If128.xci +++ /dev/null @@ -1,730 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - PCIeGen2x8If128 - - - FALSE - FALSE - FALSE - TRUE - 0x00000 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - TRUE - FALSE - TRUE - FALSE - 16KB - 1 - 128 - TRUE - 0 - FALSE - FALSE - FALSE - FALSE - 0x000 - NONE - FALSE - TRUE - FALSE - FALSE - NONE - 3 - 2.0 - FALSE - FALSE - FALSE - 0x000 - 0x000 - 0x00 - 0x03 - 0x4 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x058000 - 0x8028 - FALSE - FALSE - FALSE - FALSE - 0x0 - FALSE - TRUE - FALSE - 0x2 - 0x000 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x000 - 0x00 - FALSE - 0x0 - 0 - TRUE - 0x000 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0xC0 - 0x000 - 0x90 - FALSE - FALSE - FALSE - FALSE - FALSE - 0x000 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x0 - 0x0000 - 0x0000 - 0x00000553 - 0x0000 - 0x0007 - 0x10EE - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0x10EE - FALSE - FALSE - 0x000 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x058000 - 0x8011 - 0x2 - 0x000 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x000 - 0x00 - FALSE - 0x0 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - 0x000 - 0x00 - FALSE - 0x000 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x0 - 0x0000 - 0x0001 - 0x00000553 - 0x0000 - 0x0007 - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 4 - FALSE - 2 - FALSE - 2 - 8 - TRUE - FALSE - 0 - 0 - GTH_Quad_224 - 1 - 0x00000000 - FALSE - 0 - 0x000 - 0x00 - 0x028 - 0x20 - 0x198 - 0x20 - FALSE - FALSE - 0x0 - FALSE - FALSE - 3 - 0x000 - 0x80 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - FALSE - 1 - 0 - 0 - 0 - 0 - 0 - 0 - Production - 1 - true - false - PCIeGen2x8If128 - 15 - false - false - 058000 - 8028 - false - false - false - 00_Not_Supported - false - false - NONE - true - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - false - false - false - false - 00 - 0 - N/A - 0000 - 00000553 - 0000 - 0007 - 10EE - false - false - false - 058000 - 8011 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 0 - N/A - 0001 - 00000553 - 0000 - 0007 - false - 4 - 5.0_GT/s - X8 - 100_MHz - Default - 0 - 0 - false - false - 1 - false - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - DWORD_Aligned - No_ASPM - 250 - true - 2FFFF - false - 128_bit - false - false - true - false - true - false - 250 - true - PCI_Express_Endpoint_device - false - false - true - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - None - Advanced - X0Y0 - false - Extreme - false - true - false - false - true - false - Kilobytes - 1 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Simple_communication_controllers - 05 - 00 - 80 - 512_bytes - false - false - false - Kilobytes - 2 - false - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - 0 - Generic_XT_compatible_serial_controller - false - false - true - false - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Simple_communication_controllers - 05 - 00 - 80 - 512_bytes - false - false - false - Kilobytes - 2 - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Generic_XT_compatible_serial_controller - false - false - QPLL1 - false - GTH_Quad_224 - ACTIVE LOW - None - true - false - 10EE - KCU105 - kintexu - xilinx.com:kcu105:part0:1.0 - xcku040 - ffva1156 - VERILOG - - MIXED - -2 - E - TRUE - TRUE - IP_Flow - 1 - TRUE - . - - . - 2015.4 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/xilinx/kcu105/KCU105_Gen2x8If128/prj/KCU105_Gen2x8If128.xpr b/fpga/xilinx/kcu105/KCU105_Gen2x8If128/prj/KCU105_Gen2x8If128.xpr deleted file mode 100644 index 6abecc1..0000000 --- a/fpga/xilinx/kcu105/KCU105_Gen2x8If128/prj/KCU105_Gen2x8If128.xpr +++ /dev/null @@ -1,810 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/xilinx/kcu105/KCU105_Gen3x4If128/Makefile b/fpga/xilinx/kcu105/KCU105_Gen3x4If128/Makefile deleted file mode 100644 index 5ddddf7..0000000 --- a/fpga/xilinx/kcu105/KCU105_Gen3x4If128/Makefile +++ /dev/null @@ -1,62 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#----------------------------------------------------------------------- -# Filename: Makefile -# Version: 1.0 -# Description: Project-level makefile for building an example project -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------- -# This make file expects the following variables to be set: -# RIFFA_HDL_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory. -# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to -# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory -WIDTH=128 -TYPE=ultrascale -CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))) -PROJECT=$(shell basename $(CURRENT_PATH)) - -ifndef RIFFA_HDL_PATH - RIFFA_HDL_PATH:=../../../riffa_hdl -endif -ifndef BOARD_PATH - BOARD_PATH:=.. -endif -ifndef JOBS - JOBS=1 -endif -include $(RIFFA_HDL_PATH)/riffa.mk -include $(BOARD_PATH)/board.mk - -PROJECT_IP+=ip/PCIeGen3x4If128.xci diff --git a/fpga/xilinx/kcu105/KCU105_Gen3x4If128/bit/KCU105_Gen3x4If128.bit b/fpga/xilinx/kcu105/KCU105_Gen3x4If128/bit/KCU105_Gen3x4If128.bit deleted file mode 100644 index 5810881..0000000 Binary files a/fpga/xilinx/kcu105/KCU105_Gen3x4If128/bit/KCU105_Gen3x4If128.bit and /dev/null differ diff --git a/fpga/xilinx/kcu105/KCU105_Gen3x4If128/constr/KCU105_Gen3x4If128.xdc b/fpga/xilinx/kcu105/KCU105_Gen3x4If128/constr/KCU105_Gen3x4If128.xdc deleted file mode 100644 index 019982a..0000000 --- a/fpga/xilinx/kcu105/KCU105_Gen3x4If128/constr/KCU105_Gen3x4If128.xdc +++ /dev/null @@ -1,119 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#---------------------------------------------------------------------------- -# Filename: KCU105_Top.xdc -# Version: 1.00.a -# Verilog Standard: Verilog-2001 -# Description: Xilinx Design Constraints for the KCU105 board. -# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin -# -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------------- -# -######################################################################################################################### -# User Constraints -######################################################################################################################### - -############################################################################### -# User Time Names / User Time Groups / Time Specs -############################################################################### - -############################################################################### -# User Physical Constraints -############################################################################### - -set_property PACKAGE_PIN AP8 [get_ports {LED[0]}] -set_property PACKAGE_PIN H23 [get_ports {LED[1]}] -set_property PACKAGE_PIN P20 [get_ports {LED[2]}] -set_property PACKAGE_PIN P21 [get_ports {LED[3]}] -set_property PACKAGE_PIN N22 [get_ports {LED[4]}] -set_property PACKAGE_PIN M22 [get_ports {LED[5]}] -set_property PACKAGE_PIN R23 [get_ports {LED[6]}] -set_property PACKAGE_PIN P23 [get_ports {LED[7]}] - -set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[4]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[5]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[6]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[7]}] - -set_false_path -to [get_ports -filter NAME=~LED*] - -######################################################################################################################### -# End User Constraints -######################################################################################################################### -# -# -# -######################################################################################################################### -# PCIE Core Constraints -######################################################################################################################### - -# -# SYS reset (input) signal. The sys_reset_n signal should be -# obtained from the PCI Express interface if possible. For -# slot based form factors, a system reset signal is usually -# present on the connector. For cable based form factors, a -# system reset signal may not be available. In this case, the -# system reset signal must be generated locally by some form of -# supervisory circuit. You may change the IOSTANDARD and LOC -# to suit your requirements and VCCO voltage banking rules. -# Some 7 series devices do not have 3.3 V I/Os available. -# Therefore the appropriate level shift is required to operate -# with these devices that contain only 1.8 V banks. -# - -set_property LOC [get_package_pins -filter {PIN_FUNC == IO_T3U_N12_PERSTN0_65}] [get_ports PCIE_RESET_N] -set_property IOSTANDARD LVCMOS18 [get_ports PCIE_RESET_N] -set_property PULLUP true [get_ports PCIE_RESET_N] - -set_property LOC AB6 [get_cells refclk_ibuf] - -############################################################################### -# Timing Constraints -############################################################################### -create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O] - -############################################################################### -# Physical Constraints -############################################################################### - -set_false_path -from [get_ports PCIE_RESET_N] -############################################################################### -# End -############################################################################### diff --git a/fpga/xilinx/kcu105/KCU105_Gen3x4If128/hdl/KCU105_Gen3x4If128.v b/fpga/xilinx/kcu105/KCU105_Gen3x4If128/hdl/KCU105_Gen3x4If128.v deleted file mode 100644 index c7b4106..0000000 --- a/fpga/xilinx/kcu105/KCU105_Gen3x4If128/hdl/KCU105_Gen3x4If128.v +++ /dev/null @@ -1,491 +0,0 @@ -// ---------------------------------------------------------------------- -// Copyright (c) 2016, The Regents of the University of California All -// rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above -// copyright notice, this list of conditions and the following -// disclaimer in the documentation and/or other materials provided -// with the distribution. -// -// * Neither the name of The Regents of the University of California -// nor the names of its contributors may be used to endorse or -// promote products derived from this software without specific -// prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -// DAMAGE. -// ---------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// Filename: KCU105_Gen3x4If128.v -// Version: 1.00.a -// Verilog Standard: Verilog-2001 -// Description: Top level module for RIFFA 2.2 reference design for the -// the Xilinx KCU105 Development Board. -// Author: Dustin Richmond (@darichmond) -//----------------------------------------------------------------------------- -`include "functions.vh" -`include "riffa.vh" -`include "ultrascale.vh" -`timescale 1ps / 1ps -module KCU105_Gen3x4If128 - #(// Number of RIFFA Channels - parameter C_NUM_CHNL = 1, - // Number of PCIe Lanes - parameter C_NUM_LANES = 4, - // Settings from Vivado IP Generator - parameter C_PCI_DATA_WIDTH = 128, - parameter C_MAX_PAYLOAD_BYTES = 256, - parameter C_LOG_NUM_TAGS = 6) - (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP, - output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN, - input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP, - input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN, - - output [7:0] LED, - input PCIE_REFCLK_P, - input PCIE_REFCLK_N, - input PCIE_RESET_N); - - // Clocks, etc - wire user_lnk_up; - wire user_clk; - wire user_reset; - wire pcie_refclk; - wire pcie_refclk_by2; - wire pcie_reset_n; - - // Interface: RQ (TXC) - wire s_axis_rq_tlast; - wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata; - wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep; - wire s_axis_rq_tready; - wire s_axis_rq_tvalid; - // Interface: RC (RXC) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata; - wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser; - wire m_axis_rc_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep; - wire m_axis_rc_tvalid; - wire m_axis_rc_tready; - // Interface: CQ (RXR) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata; - wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser; - wire m_axis_cq_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep; - wire m_axis_cq_tvalid; - wire m_axis_cq_tready; - // Interface: CC (TXC) - wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata; - wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser; - wire s_axis_cc_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep; - wire s_axis_cc_tvalid; - wire s_axis_cc_tready; - - // Configuration (CFG) Interface - wire [3:0] pcie_rq_seq_num; - wire pcie_rq_seq_num_vld; - wire [5:0] pcie_rq_tag; - wire pcie_rq_tag_vld; - wire pcie_cq_np_req; - wire [5:0] pcie_cq_np_req_count; - - wire cfg_phy_link_down; - wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH - wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE - wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD - wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST - wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE - wire [5:0] cfg_function_power_state; // Ignorable but not removable - wire [11:0] cfg_vf_status; // Ignorable but not removable - wire [17:0] cfg_vf_power_state; // Ignorable but not removable - wire [1:0] cfg_link_power_state; // Ignorable but not removable - - // Error Reporting Interface - wire cfg_err_cor_out; - wire cfg_err_nonfatal_out; - wire cfg_err_fatal_out; - - wire cfg_ltr_enable; - wire [5:0] cfg_ltssm_state; - wire [1:0] cfg_rcb_status; - wire [1:0] cfg_dpa_substate_change; - wire [1:0] cfg_obff_enable; - wire cfg_pl_status_change; - - wire [1:0] cfg_tph_requester_enable; - wire [5:0] cfg_tph_st_mode; - wire [5:0] cfg_vf_tph_requester_enable; - wire [17:0] cfg_vf_tph_st_mode; - wire [7:0] cfg_fc_ph; - wire [11:0] cfg_fc_pd; - wire [7:0] cfg_fc_nph; - wire [11:0] cfg_fc_npd; - wire [7:0] cfg_fc_cplh; - wire [11:0] cfg_fc_cpld; - wire [2:0] cfg_fc_sel; - - // Interrupt Interface Signals - wire [3:0] cfg_interrupt_int; - wire [1:0] cfg_interrupt_pending; - wire cfg_interrupt_sent; - wire [1:0] cfg_interrupt_msi_enable; - wire [5:0] cfg_interrupt_msi_vf_enable; - wire [5:0] cfg_interrupt_msi_mmenable; - wire cfg_interrupt_msi_mask_update; - wire [31:0] cfg_interrupt_msi_data; - wire [3:0] cfg_interrupt_msi_select; - wire [31:0] cfg_interrupt_msi_int; - wire [63:0] cfg_interrupt_msi_pending_status; - wire cfg_interrupt_msi_sent; - wire cfg_interrupt_msi_fail; - wire [2:0] cfg_interrupt_msi_attr; - wire cfg_interrupt_msi_tph_present; - wire [1:0] cfg_interrupt_msi_tph_type; - wire [8:0] cfg_interrupt_msi_tph_st_tag; - wire [2:0] cfg_interrupt_msi_function_number; - - wire rst_out; - wire [C_NUM_CHNL-1:0] chnl_rx_clk; - wire [C_NUM_CHNL-1:0] chnl_rx; - wire [C_NUM_CHNL-1:0] chnl_rx_ack; - wire [C_NUM_CHNL-1:0] chnl_rx_last; - wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; - wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data; - wire [C_NUM_CHNL-1:0] chnl_rx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_rx_data_ren; - - wire [C_NUM_CHNL-1:0] chnl_tx_clk; - wire [C_NUM_CHNL-1:0] chnl_tx; - wire [C_NUM_CHNL-1:0] chnl_tx_ack; - wire [C_NUM_CHNL-1:0] chnl_tx_last; - wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; - wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data; - wire [C_NUM_CHNL-1:0] chnl_tx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_tx_data_ren; - - genvar chnl; - - IBUF - #() - pci_reset_n_ibuf - (.O(pcie_reset_n), - .I(PCIE_RESET_N)); - - IBUFDS_GTE3 - #() - refclk_ibuf - (.O(pcie_refclk), - .ODIV2(pcie_refclk_by2), - .I(PCIE_REFCLK_P), - .CEB(1'b0), - .IB(PCIE_REFCLK_N)); - - OBUF - #() - led_0_obuf - (.O(LED[0]), - .I(cfg_ltssm_state[0])); - OBUF - #() - led_1_obuf - (.O(LED[1]), - .I(cfg_ltssm_state[1])); - OBUF - #() - led_2_obuf - (.O(LED[2]), - .I(cfg_ltssm_state[2])); - OBUF - #() - led_3_obuf - (.O(LED[3]), - .I(cfg_ltssm_state[3])); - OBUF - #() - led_4_obuf - (.O(LED[4]), - .I(cfg_ltssm_state[4])); - OBUF - #() - led_5_obuf - (.O(LED[5]), - .I(cfg_ltssm_state[5])); - OBUF - #() - led_6_obuf - (.O(LED[6]), - .I(user_reset)); - OBUF - #() - led_7_obuf - (.O(LED[7]), - .I(rst_out)); - - // Core Top Level Wrapper - PCIeGen3x4If128 - #() - pcie3_7x_0_i - (//--------------------------------------------------------------------- - // PCI Express (pci_exp) Interface - //--------------------------------------------------------------------- - .pci_exp_txn ( PCI_EXP_TXN ), - .pci_exp_txp ( PCI_EXP_TXP ), - .pci_exp_rxn ( PCI_EXP_RXN ), - .pci_exp_rxp ( PCI_EXP_RXP ), - - //--------------------------------------------------------------------- - // AXI Interface - //--------------------------------------------------------------------- - .user_clk ( user_clk ), - .user_reset ( user_reset ), - .user_lnk_up ( user_lnk_up ), - - .s_axis_rq_tlast ( s_axis_rq_tlast ), - .s_axis_rq_tdata ( s_axis_rq_tdata ), - .s_axis_rq_tuser ( s_axis_rq_tuser ), - .s_axis_rq_tkeep ( s_axis_rq_tkeep ), - .s_axis_rq_tready ( s_axis_rq_tready ), - .s_axis_rq_tvalid ( s_axis_rq_tvalid ), - - .m_axis_rc_tdata ( m_axis_rc_tdata ), - .m_axis_rc_tuser ( m_axis_rc_tuser ), - .m_axis_rc_tlast ( m_axis_rc_tlast ), - .m_axis_rc_tkeep ( m_axis_rc_tkeep ), - .m_axis_rc_tvalid ( m_axis_rc_tvalid ), - .m_axis_rc_tready ( {22{m_axis_rc_tready}} ), - - .m_axis_cq_tdata ( m_axis_cq_tdata ), - .m_axis_cq_tuser ( m_axis_cq_tuser ), - .m_axis_cq_tlast ( m_axis_cq_tlast ), - .m_axis_cq_tkeep ( m_axis_cq_tkeep ), - .m_axis_cq_tvalid ( m_axis_cq_tvalid ), - .m_axis_cq_tready ( {22{m_axis_cq_tready}} ), - - .s_axis_cc_tdata ( s_axis_cc_tdata ), - .s_axis_cc_tuser ( s_axis_cc_tuser ), - .s_axis_cc_tlast ( s_axis_cc_tlast ), - .s_axis_cc_tkeep ( s_axis_cc_tkeep ), - .s_axis_cc_tvalid ( s_axis_cc_tvalid ), - .s_axis_cc_tready ( s_axis_cc_tready ), - - //--------------------------------------------------------------------- - // Configuration (CFG) Interface - //--------------------------------------------------------------------- - .pcie_rq_seq_num ( pcie_rq_seq_num ), - .pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ), - .pcie_rq_tag ( pcie_rq_tag ), - .pcie_rq_tag_vld ( pcie_rq_tag_vld ), - .pcie_cq_np_req ( pcie_cq_np_req ), - .pcie_cq_np_req_count ( pcie_cq_np_req_count ), - .cfg_phy_link_down ( cfg_phy_link_down ), - .cfg_phy_link_status ( cfg_phy_link_status), - .cfg_negotiated_width ( cfg_negotiated_width ), - .cfg_current_speed ( cfg_current_speed ), - .cfg_max_payload ( cfg_max_payload ), - .cfg_max_read_req ( cfg_max_read_req ), - .cfg_function_status ( cfg_function_status ), - .cfg_function_power_state ( cfg_function_power_state ), - .cfg_vf_status ( cfg_vf_status ), - .cfg_vf_power_state ( cfg_vf_power_state ), - .cfg_link_power_state ( cfg_link_power_state ), - // Error Reporting Interface - .cfg_err_cor_out ( cfg_err_cor_out ), - .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), - .cfg_err_fatal_out ( cfg_err_fatal_out ), - .cfg_ltr_enable ( cfg_ltr_enable ), - .cfg_ltssm_state ( cfg_ltssm_state ), - .cfg_rcb_status ( cfg_rcb_status ), - .cfg_dpa_substate_change ( cfg_dpa_substate_change ), - .cfg_obff_enable ( cfg_obff_enable ), - .cfg_pl_status_change ( cfg_pl_status_change ), - .cfg_tph_requester_enable ( cfg_tph_requester_enable ), - .cfg_tph_st_mode ( cfg_tph_st_mode ), - .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), - .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), - .cfg_fc_ph ( cfg_fc_ph ), - .cfg_fc_pd ( cfg_fc_pd ), - .cfg_fc_nph ( cfg_fc_nph ), - .cfg_fc_npd ( cfg_fc_npd ), - .cfg_fc_cplh ( cfg_fc_cplh ), - .cfg_fc_cpld ( cfg_fc_cpld ), - .cfg_fc_sel ( cfg_fc_sel ), - //--------------------------------------------------------------------- - // EP Only - //--------------------------------------------------------------------- - // Interrupt Interface Signals - .cfg_interrupt_int ( cfg_interrupt_int ), - .cfg_interrupt_pending ( cfg_interrupt_pending ), - .cfg_interrupt_sent ( cfg_interrupt_sent ), - .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ), - .cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ), - .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), - .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), - .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), - .cfg_interrupt_msi_select ( cfg_interrupt_msi_select ), - .cfg_interrupt_msi_int ( cfg_interrupt_msi_int ), - .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ), - .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), - .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), - .cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ), - .cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ), - .cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ), - .cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ), - .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ), - .cfg_interrupt_msi_pending_status_function_num ( 4'b0), - .cfg_interrupt_msi_pending_status_data_enable ( 1'b0), - - - //--------------------------------------------------------------------------------------// - // Reset Pass Through Signals - // - Only used for PCIe_X0Y0 - //--------------------------------------------------------------------------------------// - .pcie_perstn0_out (pcie_reset_n_core), - .pcie_perstn1_in (1'b0), - .pcie_perstn1_out (), - - //--------------------------------------------------------------------- - // System(SYS) Interface - //--------------------------------------------------------------------- - .sys_clk (pcie_refclk_by2), - .sys_clk_gt (pcie_refclk), - .sys_reset (pcie_reset_n)); - - riffa_wrapper_kcu105 - #(/*AUTOINSTPARAM*/ - // Parameters - .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), - .C_NUM_CHNL (C_NUM_CHNL), - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES)) - riffa - (// Outputs - .M_AXIS_CQ_TREADY (m_axis_cq_tready), - .M_AXIS_RC_TREADY (m_axis_rc_tready), - .S_AXIS_CC_TVALID (s_axis_cc_tvalid), - .S_AXIS_CC_TLAST (s_axis_cc_tlast), - .S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]), - .S_AXIS_RQ_TVALID (s_axis_rq_tvalid), - .S_AXIS_RQ_TLAST (s_axis_rq_tlast), - .S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]), - .USER_CLK (user_clk), - .USER_RESET (user_reset), - .CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]), - .CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]), - .CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]), - .CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]), - .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]), - .CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]), - .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present), - .CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]), - .CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]), - .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]), - .CFG_FC_SEL (cfg_fc_sel[2:0]), - .PCIE_CQ_NP_REQ (pcie_cq_np_req), - .RST_OUT (rst_out), - .CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]), - .CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]), - .CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]), - .CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]), - .CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]), - // Inputs - .M_AXIS_CQ_TVALID (m_axis_cq_tvalid), - .M_AXIS_CQ_TLAST (m_axis_cq_tlast), - .M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]), - .M_AXIS_RC_TVALID (m_axis_rc_tvalid), - .M_AXIS_RC_TLAST (m_axis_rc_tlast), - .M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]), - .S_AXIS_CC_TREADY (s_axis_cc_tready), - .S_AXIS_RQ_TREADY (s_axis_rq_tready), - .CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]), - .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update), - .CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]), - .CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent), - .CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail), - .CFG_FC_CPLH (cfg_fc_cplh[7:0]), - .CFG_FC_CPLD (cfg_fc_cpld[11:0]), - .CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]), - .CFG_CURRENT_SPEED (cfg_current_speed[2:0]), - .CFG_MAX_PAYLOAD (cfg_max_payload[2:0]), - .CFG_MAX_READ_REQ (cfg_max_read_req[2:0]), - .CFG_FUNCTION_STATUS (cfg_function_status[7:0]), - .CFG_RCB_STATUS (cfg_rcb_status[1:0]), - .CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]), - .CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]), - .CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]), - .CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]), - .CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]), - .CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]), - .CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])); - - generate - for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels - chnl_tester - #(/*AUTOINSTPARAM*/ - // Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH)) - module1 - (.CLK(user_clk), - .RST(rst_out), // riffa_reset includes riffa_endpoint resets - // Rx interface - .CHNL_RX_CLK(chnl_rx_clk[chnl]), - .CHNL_RX(chnl_rx[chnl]), - .CHNL_RX_ACK(chnl_rx_ack[chnl]), - .CHNL_RX_LAST(chnl_rx_last[chnl]), - .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), - .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), - .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), - .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), - .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]), - // Tx interface - .CHNL_TX_CLK(chnl_tx_clk[chnl]), - .CHNL_TX(chnl_tx[chnl]), - .CHNL_TX_ACK(chnl_tx_ack[chnl]), - .CHNL_TX_LAST(chnl_tx_last[chnl]), - .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), - .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), - .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), - .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), - .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl]) - /*AUTOINST*/); - end - endgenerate -endmodule -// Local Variables: -// verilog-library-directories:("../../../../riffa_hdl/" "../../") -// End: - diff --git a/fpga/xilinx/kcu105/KCU105_Gen3x4If128/ip/PCIeGen3x4If128.xci b/fpga/xilinx/kcu105/KCU105_Gen3x4If128/ip/PCIeGen3x4If128.xci deleted file mode 100644 index 663243e..0000000 --- a/fpga/xilinx/kcu105/KCU105_Gen3x4If128/ip/PCIeGen3x4If128.xci +++ /dev/null @@ -1,731 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - PCIeGen3x4If128 - - - FALSE - FALSE - FALSE - TRUE - 0x00000 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - TRUE - FALSE - TRUE - FALSE - 16KB - 1 - 128 - TRUE - 0 - FALSE - FALSE - FALSE - FALSE - 0x000 - NONE - FALSE - TRUE - FALSE - FALSE - NONE - 3 - 2.0 - FALSE - FALSE - FALSE - 0x300 - 0x000 - 0x00 - 0x03 - 0x4 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x058000 - 0x8034 - FALSE - FALSE - FALSE - FALSE - 0x0 - FALSE - TRUE - FALSE - 0x2 - 0x300 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x300 - 0x00 - FALSE - 0x0 - 0 - TRUE - 0x300 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0xC0 - 0x274 - 0x90 - FALSE - FALSE - FALSE - FALSE - FALSE - 0x300 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x300 - 0x0000 - 0x0 - 0x0000 - 0x0000 - 0x00000553 - 0x0000 - 0x0007 - 0x10EE - TRUE - FALSE - FALSE - 0x300 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0x10EE - FALSE - FALSE - 0x000 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x058000 - 0x8011 - 0x2 - 0x000 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x000 - 0x00 - FALSE - 0x0 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - 0x000 - 0x00 - FALSE - 0x000 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x0 - 0x0000 - 0x0001 - 0x00000553 - 0x0000 - 0x0007 - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 4 - FALSE - 2 - FALSE - 4 - 4 - TRUE - FALSE - 0 - 0 - GTH_Quad_224 - 1 - 0x00000000 - FALSE - 0 - 0x000 - 0x00 - 0x028 - 0x20 - 0x198 - 0x20 - FALSE - FALSE - 0x0 - FALSE - FALSE - 3 - 0x000 - 0x80 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - FALSE - 1 - 0 - 0 - 0 - 0 - 0 - 0 - Production - 1 - true - false - PCIeGen3x4If128 - 15 - false - false - 058000 - 8034 - false - false - false - 00_Not_Supported - false - false - NONE - true - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - false - false - false - false - 00 - 0 - N/A - 0000 - 00000553 - 0000 - 0007 - 10EE - false - false - false - 058000 - 8011 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 0 - N/A - 0001 - 00000553 - 0000 - 0007 - false - 4 - 8.0_GT/s - X4 - 100_MHz - Default - 0 - 0 - false - false - 1 - false - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - DWORD_Aligned - No_ASPM - 250 - true - 2FFFF - false - 128_bit - false - false - true - false - true - false - 250 - true - PCI_Express_Endpoint_device - false - false - true - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - None - Advanced - X0Y0 - false - Extreme - false - true - false - false - true - false - Kilobytes - 1 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Simple_communication_controllers - 05 - 00 - 80 - 512_bytes - false - false - false - Kilobytes - 2 - false - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - 0 - Generic_XT_compatible_serial_controller - false - false - true - false - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Simple_communication_controllers - 05 - 00 - 80 - 512_bytes - false - false - false - Kilobytes - 2 - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Generic_XT_compatible_serial_controller - false - false - QPLL1 - false - GTH_Quad_224 - ACTIVE LOW - None - true - false - 10EE - KCU105 - kintexu - xilinx.com:kcu105:part0:1.0 - xcku040 - ffva1156 - VERILOG - - MIXED - -2 - E - TRUE - TRUE - IP_Flow - 1 - TRUE - . - - . - 2015.4 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/xilinx/kcu105/KCU105_Gen3x4If128/prj/KCU105_Gen3x4If128.xpr b/fpga/xilinx/kcu105/KCU105_Gen3x4If128/prj/KCU105_Gen3x4If128.xpr deleted file mode 100644 index c2c52f0..0000000 --- a/fpga/xilinx/kcu105/KCU105_Gen3x4If128/prj/KCU105_Gen3x4If128.xpr +++ /dev/null @@ -1,810 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/xilinx/kcu105/Makefile b/fpga/xilinx/kcu105/Makefile deleted file mode 100644 index 337451c..0000000 --- a/fpga/xilinx/kcu105/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#----------------------------------------------------------------------- -# Filename: Makefile -# Version: 1.0 -# Description: Top-level makefile for building the example -# projects in a board -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------- -BOARD:=kcu105 -BOARD_PROJECTS:=KCU105_Gen1x8If64 KCU105_Gen2x8If128 KCU105_Gen3x4If128 -BOARD_TYPE:=ultrascale -VENDOR:=xilinx -include ../vendor.mk diff --git a/fpga/xilinx/kcu105/board.mk b/fpga/xilinx/kcu105/board.mk deleted file mode 100644 index 0d6b7bf..0000000 --- a/fpga/xilinx/kcu105/board.mk +++ /dev/null @@ -1,103 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#----------------------------------------------------------------------- -# Filename: board.mk -# Version: 1.0 -# Description: Board-specific include makefile -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------- -include $(RIFFA_ROOT_PATH)/release.mk -.DEFAULT_GOAL=all - -BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v - -PROJECT_IP= -PROJECT_BIT:= bit/$(PROJECT).bit -PROJECT_HDL=hdl/$(PROJECT).v $(BOARD_HDL) $(patsubst %, $(RIFFA_HDL_PATH)/%,$(RIFFA_HDL)) -PROJECT_CONSTR=constr/$(PROJECT).xdc -PROJECT_FILE=prj/$(PROJECT).xpr -PROJECT_FILES=$(PROJECT_IP) $(PROJECT_CONSTR) $(PROJECT_QSRCS) $(PROJECT_HDL) - -RELEASE_BIT:=$(PROJECT_BIT) -RELEASE_IP=$(PROJECT_IP) # Note the difference between this and the other assignments (Projects add their own IP) -RELEASE_HDL:=hdl/$(PROJECT).v -RELEASE_CONSTR:=$(PROJECT_CONSTR) -RELEASE_FILE:=$(PROJECT_FILE) -RELEASE_PROJECT_PATH:=$(RELEASE_SRC_PATH)/fpga/$(VENDOR)/$(BOARD)/$(PROJECT) -copy-files = $(foreach file, $1, cp $(file) $2;) - -.PHONY:$(PROJECT) all synthesis implementation clean clobber $(TYPE) $(VENDOR) $(BOARD) -$(PROJECT): $(PROJECT_BIT) - @echo Compiling Project $@ - -$(PROJECT_BIT): $(PROJECT_FILES) - echo "launch_runs impl_1 -to_step write_bitstream -jobs $(JOBS); wait_on_run impl_1" | vivado -mode tcl prj/$(PROJECT).xpr - mv prj/$(PROJECT).runs/impl_1/$(PROJECT).bit bit/ - -synthesis: prj/$(PROJECT).runs/synth_1 -prj/$(PROJECT).runs/synth_1: $(PROJECT_FILES) - echo "launch_runs synth_1 -jobs $(JOBS); wait_on_run synth_1" | vivado -mode tcl prj/$(PROJECT).xpr - -implementation:prj/$(PROJECT).runs/impl_1 -prj/$(PROJECT).runs/impl_1: $(PROJECT_FILES) - echo "launch_runs impl_1 -jobs $(JOBS); wait_on_run impl1" | vivado -mode tcl prj/$(PROJECT).xpr - -all $(TYPE) $(VENDOR) $(BOARD):$(PROJECT) -clean: - echo "reset_run impl_1; reset_run synth_1;" | vivado -mode tcl prj/$(PROJECT).xpr - rm -rf *.log *.jou *~ .Xil - rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~ - rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~ - -clobber: - rm -rf $(PROJECT_BIT) - -destination: $(RELEASE_PROJECT_PATH) - mkdir $(RELEASE_PROJECT_PATH)/bit - mkdir $(RELEASE_PROJECT_PATH)/constr - mkdir $(RELEASE_PROJECT_PATH)/ip - mkdir $(RELEASE_PROJECT_PATH)/hdl - mkdir $(RELEASE_PROJECT_PATH)/prj - -$(RELEASE_PROJECT_PATH): check-release-src - mkdir $@ - -release:check-release-src destination - $(call copy-files, $(RELEASE_BIT), $(RELEASE_PROJECT_PATH)/bit) - $(call copy-files, $(RELEASE_CONSTR), $(RELEASE_PROJECT_PATH)/constr) - $(call copy-files, $(RELEASE_IP), $(RELEASE_PROJECT_PATH)/ip) - $(call copy-files, $(RELEASE_HDL), $(RELEASE_PROJECT_PATH)/hdl) - $(call copy-files, $(RELEASE_FILE), $(RELEASE_PROJECT_PATH)/prj) - diff --git a/fpga/xilinx/kcu105/riffa_wrapper_kcu105.v b/fpga/xilinx/kcu105/riffa_wrapper_kcu105.v deleted file mode 100644 index 93a06c3..0000000 --- a/fpga/xilinx/kcu105/riffa_wrapper_kcu105.v +++ /dev/null @@ -1,592 +0,0 @@ -// ---------------------------------------------------------------------- -// Copyright (c) 2016, The Regents of the University of California All -// rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above -// copyright notice, this list of conditions and the following -// disclaimer in the documentation and/or other materials provided -// with the distribution. -// -// * Neither the name of The Regents of the University of California -// nor the names of its contributors may be used to endorse or -// promote products derived from this software without specific -// prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -// DAMAGE. -// ---------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// Filename: riffa_wrapper_vc709.v -// Version: 1.00.a -// Verilog Standard: Verilog-2001 -// Description: RIFFA wrapper for the KCU105 Development board. -// Author: Dustin Richmond (@darichmond) -//----------------------------------------------------------------------------- -`include "trellis.vh" -`include "riffa.vh" -`include "ultrascale.vh" -`include "functions.vh" -`timescale 1ps / 1ps -module riffa_wrapper_kcu105 - #(// Number of RIFFA Channels - parameter C_NUM_CHNL = 1, - // Bit-Width from Vivado IP Generator - parameter C_PCI_DATA_WIDTH = 128, - // 4-Byte Name for this FPGA - parameter C_MAX_PAYLOAD_BYTES = 256, - parameter C_LOG_NUM_TAGS = 5, - parameter C_FPGA_ID = "7V30") - (//Interface: CQ Ultrascale (RXR) - input M_AXIS_CQ_TVALID, - input M_AXIS_CQ_TLAST, - input [C_PCI_DATA_WIDTH-1:0] M_AXIS_CQ_TDATA, - input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_CQ_TKEEP, - input [`SIG_CQ_TUSER_W-1:0] M_AXIS_CQ_TUSER, - output M_AXIS_CQ_TREADY, - - //Interface: RC Ultrascale (RXC) - input M_AXIS_RC_TVALID, - input M_AXIS_RC_TLAST, - input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RC_TDATA, - input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_RC_TKEEP, - input [`SIG_RC_TUSER_W-1:0] M_AXIS_RC_TUSER, - output M_AXIS_RC_TREADY, - - //Interface: CC Ultrascale (TXC) - input S_AXIS_CC_TREADY, - output S_AXIS_CC_TVALID, - output S_AXIS_CC_TLAST, - output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA, - output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP, - output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER, - - //Interface: RQ Ultrascale (TXR) - input S_AXIS_RQ_TREADY, - output S_AXIS_RQ_TVALID, - output S_AXIS_RQ_TLAST, - output [C_PCI_DATA_WIDTH-1:0] S_AXIS_RQ_TDATA, - output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_RQ_TKEEP, - output [`SIG_RQ_TUSER_W-1:0] S_AXIS_RQ_TUSER, - - input USER_CLK, - input USER_RESET, - - output [3:0] CFG_INTERRUPT_INT, - output [1:0] CFG_INTERRUPT_PENDING, - input [1:0] CFG_INTERRUPT_MSI_ENABLE, - input CFG_INTERRUPT_MSI_MASK_UPDATE, - input [31:0] CFG_INTERRUPT_MSI_DATA, - output [3:0] CFG_INTERRUPT_MSI_SELECT, - output [31:0] CFG_INTERRUPT_MSI_INT, - output [63:0] CFG_INTERRUPT_MSI_PENDING_STATUS, - input CFG_INTERRUPT_MSI_SENT, - input CFG_INTERRUPT_MSI_FAIL, - output [2:0] CFG_INTERRUPT_MSI_ATTR, - output CFG_INTERRUPT_MSI_TPH_PRESENT, - output [1:0] CFG_INTERRUPT_MSI_TPH_TYPE, - output [8:0] CFG_INTERRUPT_MSI_TPH_ST_TAG, - output [2:0] CFG_INTERRUPT_MSI_FUNCTION_NUMBER, - - input [7:0] CFG_FC_CPLH, - input [11:0] CFG_FC_CPLD, - output [2:0] CFG_FC_SEL, - - input [3:0] CFG_NEGOTIATED_WIDTH, // CONFIG_LINK_WIDTH - input [2:0] CFG_CURRENT_SPEED, // CONFIG_LINK_RATE - input [2:0] CFG_MAX_PAYLOAD, // CONFIG_MAX_PAYLOAD - input [2:0] CFG_MAX_READ_REQ, // CONFIG_MAX_READ_REQUEST - input [7:0] CFG_FUNCTION_STATUS, // [2] = CONFIG_BUS_MASTER_ENABLE - input [1:0] CFG_RCB_STATUS, - - output PCIE_CQ_NP_REQ, - - // RIFFA Interface Signals - output RST_OUT, - input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock - output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal - input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal - output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read - output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length - output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset - output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data - output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid - input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved - - input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock - input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal - output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal - input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write - input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words) - input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset - input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data - input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid - output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved - - localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver - localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2; - // ALTERA, XILINX or ULTRASCALE - localparam C_VENDOR = "ULTRASCALE"; - - localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32; - localparam C_PIPELINE_OUTPUT = 1; - localparam C_PIPELINE_INPUT = 1; - localparam C_DEPTH_PACKETS = 4; - - wire clk; - wire rst_in; - wire done_txc_rst; - wire done_txr_rst; - wire done_rxr_rst; - wire done_rxc_rst; - // Interface: RXC Engine - wire [C_PCI_DATA_WIDTH-1:0] rxc_data; - wire rxc_data_valid; - wire rxc_data_start_flag; - wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset; - wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe; - wire rxc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset; - wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe; - wire [`SIG_TAG_W-1:0] rxc_meta_tag; - wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr; - wire [`SIG_TYPE_W-1:0] rxc_meta_type; - wire [`SIG_LEN_W-1:0] rxc_meta_length; - wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining; - wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id; - wire rxc_meta_ep; - - // Interface: RXR Engine - wire [C_PCI_DATA_WIDTH-1:0] rxr_data; - wire rxr_data_valid; - wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable; - wire rxr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset; - wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe; - wire rxr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset; - wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe; - wire [`SIG_TC_W-1:0] rxr_meta_tc; - wire [`SIG_ATTR_W-1:0] rxr_meta_attr; - wire [`SIG_TAG_W-1:0] rxr_meta_tag; - wire [`SIG_TYPE_W-1:0] rxr_meta_type; - wire [`SIG_ADDR_W-1:0] rxr_meta_addr; - wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded; - wire [`SIG_REQID_W-1:0] rxr_meta_requester_id; - wire [`SIG_LEN_W-1:0] rxr_meta_length; - wire rxr_meta_ep; - - // interface: TXC Engine - wire txc_data_valid; - wire [C_PCI_DATA_WIDTH-1:0] txc_data; - wire txc_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset; - wire txc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset; - wire txc_data_ready; - - wire txc_meta_valid; - wire [`SIG_FBE_W-1:0] txc_meta_fdwbe; - wire [`SIG_LBE_W-1:0] txc_meta_ldwbe; - wire [`SIG_LOWADDR_W-1:0] txc_meta_addr; - wire [`SIG_TYPE_W-1:0] txc_meta_type; - wire [`SIG_LEN_W-1:0] txc_meta_length; - wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count; - wire [`SIG_TAG_W-1:0] txc_meta_tag; - wire [`SIG_REQID_W-1:0] txc_meta_requester_id; - wire [`SIG_TC_W-1:0] txc_meta_tc; - wire [`SIG_ATTR_W-1:0] txc_meta_attr; - wire txc_meta_ep; - wire txc_meta_ready; - wire txc_sent; - - // Interface: TXR Engine - wire txr_data_valid; - wire [C_PCI_DATA_WIDTH-1:0] txr_data; - wire txr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset; - wire txr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset; - wire txr_data_ready; - - wire txr_meta_valid; - wire [`SIG_FBE_W-1:0] txr_meta_fdwbe; - wire [`SIG_LBE_W-1:0] txr_meta_ldwbe; - wire [`SIG_ADDR_W-1:0] txr_meta_addr; - wire [`SIG_LEN_W-1:0] txr_meta_length; - wire [`SIG_TAG_W-1:0] txr_meta_tag; - wire [`SIG_TC_W-1:0] txr_meta_tc; - wire [`SIG_ATTR_W-1:0] txr_meta_attr; - wire [`SIG_TYPE_W-1:0] txr_meta_type; - wire txr_meta_ep; - wire txr_meta_ready; - wire txr_sent; - - // Unconnected Wires (Used in classic interface) - wire wRxTlpReady_nc; - wire [C_PCI_DATA_WIDTH-1:0] wRxTlp_nc = 0; - wire wRxTlpEndFlag_nc = 0; - wire [`SIG_OFFSET_W-1:0] wRxTlpEndOffset_nc = 0; - wire wRxTlpStartFlag_nc = 0; - wire [`SIG_OFFSET_W-1:0] wRxTlpStartOffset_nc = 0; - wire wRxTlpValid_nc = 0; - wire [`SIG_BARDECODE_W-1:0] wRxTlpBarDecode_nc = 0; - - wire wTxTlpReady_nc = 0; - wire [C_PCI_DATA_WIDTH-1:0] wTxTlp_nc; - wire wTxTlpEndFlag_nc; - wire [`SIG_OFFSET_W-1:0] wTxTlpEndOffset_nc; - wire wTxTlpStartFlag_nc; - wire [`SIG_OFFSET_W-1:0] wTxTlpStartOffset_nc; - wire wTxTlpValid_nc; - - //-------------------------------------------------------------------------- - - // Interface: Configuration - wire config_bus_master_enable; - wire [`SIG_CPLID_W-1:0] config_completer_id; - wire config_cpl_boundary_sel; - wire config_interrupt_msienable; - wire [`SIG_LINKRATE_W-1:0] config_link_rate; - wire [`SIG_LINKWIDTH_W-1:0] config_link_width; - wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size; - wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size; - wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data; - wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr; - - wire intr_msi_request; - wire intr_msi_rdy; - - genvar chnl; - - assign clk = USER_CLK; - assign rst_in = USER_RESET; - - assign config_completer_id = 0; // Not used in ULTRASCALE implementation - assign config_bus_master_enable = CFG_FUNCTION_STATUS[2]; - assign config_link_width = {2'b00,CFG_NEGOTIATED_WIDTH}; // CONFIG_LINK_WIDTH - assign config_link_rate = CFG_CURRENT_SPEED[2]? 2'b11 : CFG_CURRENT_SPEED[2] ? 2'b10 : 2'b01; - assign config_max_payload_size = CFG_MAX_PAYLOAD; // CONFIG_MAX_PAYLOAD - assign config_max_read_request_size = CFG_MAX_READ_REQ; // CONFIG_MAX_READ_REQUEST - assign config_cpl_boundary_sel = CFG_RCB_STATUS[0]; - assign config_interrupt_msienable = CFG_INTERRUPT_MSI_ENABLE[0]; - assign config_max_cpl_data = CFG_FC_CPLD; - assign config_max_cpl_hdr = CFG_FC_CPLH; - - assign CFG_FC_SEL = 3'b001; // Always display credit maximum for the signals below - assign CFG_INTERRUPT_MSI_INT = {31'b0,intr_msi_request}; - assign CFG_INTERRUPT_MSI_SELECT = 0; - assign CFG_INTERRUPT_INT = 0; - assign CFG_INTERRUPT_PENDING = 0; - assign CFG_INTERRUPT_MSI_SELECT = 0; - assign CFG_INTERRUPT_MSI_PENDING_STATUS = {63'b0,intr_msi_request}; - assign CFG_INTERRUPT_MSI_ATTR = 0; - assign CFG_INTERRUPT_MSI_TPH_PRESENT = 0; - assign CFG_INTERRUPT_MSI_TPH_ST_TAG = 0; - assign CFG_INTERRUPT_MSI_TPH_TYPE = 0; - assign CFG_INTERRUPT_MSI_FUNCTION_NUMBER = 0; - - assign intr_msi_rdy = CFG_INTERRUPT_MSI_SENT & ~CFG_INTERRUPT_MSI_FAIL; - - assign PCIE_CQ_NP_REQ = 1; - - engine_layer - #(// Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), - .C_PIPELINE_INPUT (C_PIPELINE_INPUT), - .C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT), - .C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4), - .C_VENDOR (C_VENDOR)) - engine_layer_inst - (// Outputs - .RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]), - .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_DATA_VALID (rxc_data_valid), - .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]), - .RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]), - .RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]), - .RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]), - .RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]), - .RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]), - .RXC_META_EP (rxc_meta_ep), - - .RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]), - .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_VALID (rxr_data_valid), - .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), - .RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]), - .RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]), - .RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]), - .RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]), - .RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]), - .RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]), - .RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]), - .RXR_META_EP (rxr_meta_ep), - - .TXC_DATA_READY (txc_data_ready), - .TXC_META_READY (txc_meta_ready), - .TXC_SENT (txc_sent), - - .TXR_DATA_READY (txr_data_ready), - .TXR_META_READY (txr_meta_ready), - .TXR_SENT (txr_sent), - - .RST_LOGIC (RST_OUT), - // Unconnected Outputs - .TX_TLP (wTxTlp_nc), - .TX_TLP_VALID (wTxTlpValid_nc), - .TX_TLP_START_FLAG (wTxTlpStartFlag_nc), - .TX_TLP_START_OFFSET (wTxTlpStartOffset_nc), - .TX_TLP_END_FLAG (wTxTlpEndFlag_nc), - .TX_TLP_END_OFFSET (wTxTlpEndOffset_nc), - - .RX_TLP_READY (wRxTlpReady_nc), - // Inputs - .CLK_BUS (clk), - .RST_BUS (rst_in), - - .CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]), - - .TXC_DATA_VALID (txc_data_valid), - .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), - .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_META_VALID (txc_meta_valid), - .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]), - .TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]), - .TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]), - .TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]), - .TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]), - .TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]), - .TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]), - .TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]), - .TXC_META_EP (txc_meta_ep), - - .TXR_DATA_VALID (txr_data_valid), - .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), - .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_META_VALID (txr_meta_valid), - .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]), - .TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]), - .TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]), - .TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]), - .TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]), - .TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]), - .TXR_META_EP (txr_meta_ep), - // Unconnected Inputs - .RX_TLP (wRxTlp_nc), - .RX_TLP_VALID (wRxTlpValid_nc), - .RX_TLP_START_FLAG (wRxTlpStartFlag_nc), - .RX_TLP_START_OFFSET (wRxTlpStartOffset_nc), - .RX_TLP_END_FLAG (wRxTlpEndFlag_nc), - .RX_TLP_END_OFFSET (wRxTlpEndOffset_nc), - .RX_TLP_BAR_DECODE (wRxTlpBarDecode_nc), - - .TX_TLP_READY (wTxTlpReady_nc), - /*AUTOINST*/ - // Outputs - .M_AXIS_CQ_TREADY (M_AXIS_CQ_TREADY), - .M_AXIS_RC_TREADY (M_AXIS_RC_TREADY), - .S_AXIS_CC_TVALID (S_AXIS_CC_TVALID), - .S_AXIS_CC_TLAST (S_AXIS_CC_TLAST), - .S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]), - .S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID), - .S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST), - .S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_RQ_TKEEP (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_RQ_TUSER (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]), - // Inputs - .M_AXIS_CQ_TVALID (M_AXIS_CQ_TVALID), - .M_AXIS_CQ_TLAST (M_AXIS_CQ_TLAST), - .M_AXIS_CQ_TDATA (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_CQ_TKEEP (M_AXIS_CQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_CQ_TUSER (M_AXIS_CQ_TUSER[`SIG_CQ_TUSER_W-1:0]), - .M_AXIS_RC_TVALID (M_AXIS_RC_TVALID), - .M_AXIS_RC_TLAST (M_AXIS_RC_TLAST), - .M_AXIS_RC_TDATA (M_AXIS_RC_TDATA[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_RC_TKEEP (M_AXIS_RC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_RC_TUSER (M_AXIS_RC_TUSER[`SIG_RC_TUSER_W-1:0]), - .S_AXIS_CC_TREADY (S_AXIS_CC_TREADY), - .S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY)); - - riffa - #(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/ - /*AUTOINSTPARAM*/ - // Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_NUM_CHNL (C_NUM_CHNL), - .C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES), - .C_VENDOR (C_VENDOR), - .C_FPGA_NAME (C_FPGA_NAME), - .C_FPGA_ID (C_FPGA_ID), - .C_DEPTH_PACKETS (C_DEPTH_PACKETS)) - riffa_inst - (// Outputs - .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), - .TXC_DATA_VALID (txc_data_valid), - .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_META_VALID (txc_meta_valid), - .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]), - .TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]), - .TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]), - .TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]), - .TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]), - .TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]), - .TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]), - .TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]), - .TXC_META_EP (txc_meta_ep), - - .TXR_DATA_VALID (txr_data_valid), - .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), - .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_META_VALID (txr_meta_valid), - .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]), - .TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]), - .TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]), - .TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]), - .TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]), - .TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]), - .TXR_META_EP (txr_meta_ep), - - .INTR_MSI_REQUEST (intr_msi_request), - // Inputs - .CLK (clk), - .RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]), - .RXR_DATA_VALID (rxr_data_valid), - .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), - .RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]), - .RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]), - .RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]), - .RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]), - .RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]), - .RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]), - .RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]), - .RXR_META_EP (rxr_meta_ep), - - .RXC_DATA_VALID (rxc_data_valid), - .RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]), - .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]), - .RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]), - .RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]), - .RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]), - .RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]), - .RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]), - .RXC_META_EP (rxc_meta_ep), - - .TXC_DATA_READY (txc_data_ready), - .TXC_META_READY (txc_meta_ready), - .TXC_SENT (txc_sent), - - .TXR_DATA_READY (txr_data_ready), - .TXR_META_READY (txr_meta_ready), - .TXR_SENT (txr_sent), - - .CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]), - .CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable), - .CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]), - .CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]), - .CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]), - .CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]), - .CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable), - .CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel), - .CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]), - .CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]), - - .INTR_MSI_RDY (intr_msi_rdy), - - .DONE_TXC_RST (done_txc_rst), - .DONE_TXR_RST (done_txr_rst), - .RST_BUS (rst_in), - /*AUTOINST*/ - // Outputs - .RST_OUT (RST_OUT), - .CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]), - .CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]), - .CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]), - .CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]), - .CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]), - .CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]), - .CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]), - // Inputs - .CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]), - .CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]), - .CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]), - .CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]), - .CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]), - .CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]), - .CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]), - .CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]), - .CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0])); - -endmodule -// Local Variables: -// verilog-library-directories:("../../riffa_hdl/") -// End: - diff --git a/fpga/xilinx/ml605/ML605Gen2x4If128/bit/PLACEHOLDER.txt b/fpga/xilinx/ml605/ML605Gen2x4If128/bit/PLACEHOLDER.txt deleted file mode 100644 index e69de29..0000000 diff --git a/fpga/xilinx/ml605/ML605Gen2x4If128/constr/ML605_Top.ucf b/fpga/xilinx/ml605/ML605Gen2x4If128/constr/ML605_Top.ucf deleted file mode 100644 index 6d3d5f4..0000000 --- a/fpga/xilinx/ml605/ML605Gen2x4If128/constr/ML605_Top.ucf +++ /dev/null @@ -1,112 +0,0 @@ -############################################################################### -# Define Device, Package And Speed Grade -############################################################################### - -CONFIG PART = xc6vlx240t-ff1156-1; - -############################################################################### -# User Time Names / User Time Groups / Time Specs -############################################################################### - -############################################################################### -# User Physical Constraints -############################################################################### - -############################################################################### -# Pinout and Related I/O Constraints -############################################################################### - -# -# SYS reset (input) signal. The sys_reset_n signal should be -# obtained from the PCI Express interface if possible. For -# slot based form factors, a system reset signal is usually -# present on the connector. For cable based form factors, a -# system reset signal may not be available. In this case, the -# system reset signal must be generated locally by some form of -# supervisory circuit. You may change the IOSTANDARD and LOC -# to suit your requirements and VCCO voltage banking rules. -# - -NET "PCIE_RESET_N" TIG; -NET "PCIE_RESET_N" LOC = AE13 | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ; - -# -# -# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n -# signals are the PCI Express reference clock. Virtex-6 GT -# Transceiver architecture requires the use of a dedicated clock -# resources (FPGA input pins) associated with each GT Transceiver. -# To use these pins an IBUFDS primitive (refclk_ibuf) is -# instantiated in user's design. -# Please refer to the Virtex-6 GT Transceiver User Guide -# (UG) for guidelines regarding clock resource selection. -# - -#NET "PCIE_REFCLK_P" LOC = P6; -#NET "PCIE_REFCLK_N" LOC = P5; -INST "refclk_ibuf" LOC = IBUFDS_GTXE1_X0Y6; - -# -# Transceiver instance placement. This constraint selects the -# transceivers to be used, which also dictates the pinout for the -# transmit and receive differential pairs. Please refer to the -# Virtex-6 GT Transceiver User Guide (UG) for more information. -# - -# PCIe Lane 0 -INST "PCIeGen*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[0].GTX" LOC = GTXE1_X0Y15; - -# PCIe Lane 1 -INST "PCIeGen*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[1].GTX" LOC = GTXE1_X0Y14; - -# PCIe Lane 2 -INST "PCIeGen*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[2].GTX" LOC = GTXE1_X0Y13; - -# PCIe Lane 3 -INST "PCIeGen*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[3].GTX" LOC = GTXE1_X0Y12; - -# -# PCI Express Block placement. This constraint selects the PCI Express -# Block to be used. -# - -INST "PCIe*/pcie_2_0_i/pcie_block_i" LOC = PCIE_X0Y1; - -# -# MMCM Placment. This constraint selects the MMCM Placement -# -INST "PCIe*/pcie_clocking_i/mmcm_adv_i" LOC = MMCM_ADV_X0Y7; - - -############################################################################### -# Timing Constraints -############################################################################### - -# -# Timing requirements and related constraints. -# - -NET "pcie_refclk" TNM_NET = "SYSCLK" ; -NET "PCIeGen*/pcie_clocking_i/clk_125" TNM_NET = "CLK_125" ; -NET "PCIeGen*/TxOutClk_bufg" TNM_NET = "TXOUTCLKBUFG"; -NET "PCIeGen*/pcie_clocking_i/clk_250" TNM_NET = "CLK_250" ; - -TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 100 MHz HIGH 50 % ; -TIMESPEC "TS_CLK_125" = PERIOD "CLK_125" TS_SYSCLK*1.25 HIGH 50 % PRIORITY 100 ; -TIMESPEC "TS_TXOUTCLKBUFG" = PERIOD "TXOUTCLKBUFG" 100 MHz HIGH 50 % PRIORITY 100 ; -TIMESPEC "TS_CLK_250" = PERIOD "CLK_250" TS_SYSCLK*2.5 HIGH 50 % PRIORITY 1; - -NET "PCIeGen*/pcie_clocking_i/sel_lnk_rate_d" TIG ; -PIN "PCIeGen*/trn_reset_n_int_i.CLR" TIG ; -PIN "PCIeGen*/trn_reset_n_i.CLR" TIG ; -PIN "PCIeGen*/pcie_clocking_i/mmcm_adv_i.RST" TIG ; - -TIMESPEC "TS_RESETN" = FROM FFS(*) TO FFS(user_reset_n_i) 8 ns; - -############################################################################### -# Physical Constraints -############################################################################### - -############################################################################### -# End -############################################################################### diff --git a/fpga/xilinx/ml605/ML605Gen2x4If128/hdl/ML605Gen2x4If128.v b/fpga/xilinx/ml605/ML605Gen2x4If128/hdl/ML605Gen2x4If128.v deleted file mode 100644 index cac8179..0000000 --- a/fpga/xilinx/ml605/ML605Gen2x4If128/hdl/ML605Gen2x4If128.v +++ /dev/null @@ -1,346 +0,0 @@ -// ---------------------------------------------------------------------- -// Copyright (c) 2016, The Regents of the University of California All -// rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above -// copyright notice, this list of conditions and the following -// disclaimer in the documentation and/or other materials provided -// with the distribution. -// -// * Neither the name of The Regents of the University of California -// nor the names of its contributors may be used to endorse or -// promote products derived from this software without specific -// prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -// DAMAGE. -// ---------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// Filename: ML605_Gen2x4If128.v -// Version: 1.00.a -// Verilog Standard: Verilog-2001 -// Description: Top level module for RIFFA 2.2 reference design for the -// the Xilinx ML605 Development Board. -// Author: Dustin Richmond (@darichmond) -//----------------------------------------------------------------------------- -`include "trellis.vh" -`include "riffa.vh" -`include "tlp.vh" -`include "xilinx.vh" -`timescale 1ps / 1ps -module ML605Gen2x4If128 - #(// Number of RIFFA Channels - parameter C_NUM_CHNL = 1, - // Number of PCIe Lanes - parameter C_NUM_LANES = 4, - // Settings from Vivado IP Generator - parameter C_PCI_DATA_WIDTH = 64, - parameter C_MAX_PAYLOAD_BYTES = 256, - parameter C_LOG_NUM_TAGS = 5) - (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP, - output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN, - input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP, - input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN, - input PCIE_REFCLK_P, - input PCIE_REFCLK_N, - input PCIE_RESET_N); - - wire pcie_refclk; - wire pcie_reset_n; - - wire user_clk; - wire user_reset; - wire user_reset_int; - wire user_lnk_up; - - wire s_axis_tx_tready; - wire [C_PCI_DATA_WIDTH-1 : 0] s_axis_tx_tdata; - wire [(C_PCI_DATA_WIDTH/8)-1 : 0] s_axis_tx_tkeep; - wire s_axis_tx_tlast; - wire s_axis_tx_tvalid; - wire [`SIG_XIL_TX_TUSER_W : 0] s_axis_tx_tuser; - - wire [C_PCI_DATA_WIDTH-1 : 0] m_axis_rx_tdata; - wire [(C_PCI_DATA_WIDTH/8)-1 : 0] m_axis_rx_tkeep; - wire m_axis_rx_tlast; - wire m_axis_rx_tvalid; - wire m_axis_rx_tready; - wire [`SIG_XIL_RX_TUSER_W - 1 : 0] m_axis_rx_tuser; - - wire tx_cfg_gnt; - wire rx_np_ok; - wire tx_cfg_req; - wire cfg_trn_pending; - - wire [11 : 0] fc_cpld; - wire [7 : 0] fc_cplh; - wire [11 : 0] fc_npd; - wire [7 : 0] fc_nph; - wire [11 : 0] fc_pd; - wire [7 : 0] fc_ph; - wire [2 : 0] fc_sel; - - wire [15 : 0] cfg_status; - wire [15 : 0] cfg_command; - wire [15 : 0] cfg_dstatus; - wire [15 : 0] cfg_dcommand; - wire [15 : 0] cfg_lstatus; - wire [15 : 0] cfg_lcommand; - wire [15 : 0] cfg_dcommand2; - - wire [2 : 0] cfg_pcie_link_state; - wire cfg_pmcsr_pme_en; - wire [1 : 0] cfg_pmcsr_powerstate; - wire cfg_pmcsr_pme_status; - wire cfg_received_func_lvl_rst; - wire [4 : 0] cfg_pciecap_interrupt_msgnum; - wire cfg_to_turnoff; - wire [7 : 0] cfg_bus_number; - wire [4 : 0] cfg_device_number; - wire [2 : 0] cfg_function_number; - - wire cfg_interrupt; - wire cfg_interrupt_rdy; - wire cfg_interrupt_assert; - wire [7 : 0] cfg_interrupt_di; - wire [7 : 0] cfg_interrupt_do; - wire [2 : 0] cfg_interrupt_mmenable; - wire cfg_interrupt_msienable; - wire cfg_interrupt_msixenable; - wire cfg_interrupt_msixfm; - wire cfg_interrupt_stat; - - wire rst_out; - wire [C_NUM_CHNL-1:0] chnl_rx_clk; - wire [C_NUM_CHNL-1:0] chnl_rx; - wire [C_NUM_CHNL-1:0] chnl_rx_ack; - wire [C_NUM_CHNL-1:0] chnl_rx_last; - wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; - wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data; - wire [C_NUM_CHNL-1:0] chnl_rx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_rx_data_ren; - - wire [C_NUM_CHNL-1:0] chnl_tx_clk; - wire [C_NUM_CHNL-1:0] chnl_tx; - wire [C_NUM_CHNL-1:0] chnl_tx_ack; - wire [C_NUM_CHNL-1:0] chnl_tx_last; - wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; - wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data; - wire [C_NUM_CHNL-1:0] chnl_tx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_tx_data_ren; - - genvar chnl; - assign cfg_turnoff_ok = 0; - assign cfg_trn_pending = 0; - assign cfg_interrupt_assert = 0; - assign cfg_interrupt_di = 0; - assign cfg_interrupt_stat = 0; - assign cfg_turnoff_ok = 0; - assign cfg_pm_wake = 0; - - IBUF - pci_reset_n_ibuf - (.O(pcie_reset_n), - .I(PCIE_RESET_N)); - - IBUFDS_GTXE1 - refclk_ibuf - (.O(pcie_refclk), - .ODIV2(), - .I(PCIE_REFCLK_P), - .CEB(1'b0), - .IB(PCIE_REFCLK_N)); - - FDCP - #(.INIT(1'b1)) - user_reset_n_i - (.Q (user_reset), - .D (user_reset_int), - .C (user_clk), - .CLR (1'b0), - .PRE (1'b0)); - - - // Core Top Level Wrapper - PCIeGen2x4If128 PCIeGen2x4If128_inst - (// Tx - .pci_exp_txn ( PCI_EXP_TXN ), - .pci_exp_txp ( PCI_EXP_TXP ), - - // Rx - .pci_exp_rxn ( PCI_EXP_RXN ), - .pci_exp_rxp ( PCI_EXP_RXP ), - - // Common - .user_clk_out ( user_clk ), - .user_reset_out ( user_reset_int ), - - // TX - .s_axis_tx_tready ( s_axis_tx_tready ), - .s_axis_tx_tdata ( s_axis_tx_tdata ), - .s_axis_tx_tkeep ( s_axis_tx_tkeep ), - .s_axis_tx_tuser ( s_axis_tx_tuser ), - .s_axis_tx_tlast ( s_axis_tx_tlast ), - .s_axis_tx_tvalid ( s_axis_tx_tvalid ), - - // Rx - .m_axis_rx_tdata ( m_axis_rx_tdata ), - .m_axis_rx_tkeep ( m_axis_rx_tkeep ), - .m_axis_rx_tlast ( m_axis_rx_tlast ), - .m_axis_rx_tvalid ( m_axis_rx_tvalid ), - .m_axis_rx_tready ( m_axis_rx_tready ), - .m_axis_rx_tuser ( m_axis_rx_tuser ), - - .tx_cfg_gnt ( tx_cfg_gnt ), - .rx_np_ok ( rx_np_ok ), - .tx_cfg_req ( tx_cfg_req ), - - .fc_cpld ( fc_cpld ), - .fc_cplh ( fc_cplh ), - .fc_npd ( fc_npd ), - .fc_nph ( fc_nph ), - .fc_pd ( fc_pd ), - .fc_ph ( fc_ph ), - .fc_sel ( fc_sel ), - - .cfg_trn_pending ( cfg_trn_pending ), - .cfg_turnoff_ok ( cfg_turnoff_ok ), - .cfg_pm_wake ( cfg_pm_wake ), - - .cfg_device_number ( cfg_device_number ), - .cfg_dcommand2 ( cfg_dcommand2 ), - .cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status ), - .cfg_status ( cfg_status ), - .cfg_dcommand ( cfg_dcommand ), - .cfg_bus_number ( cfg_bus_number ), - .cfg_function_number ( cfg_function_number ), - .cfg_command ( cfg_command ), - .cfg_dstatus ( cfg_dstatus ), - .cfg_lstatus ( cfg_lstatus ), - .cfg_pcie_link_state ( cfg_pcie_link_state ), - .cfg_lcommand ( cfg_lcommand ), - .cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en ), - .cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate ), - - .cfg_interrupt ( cfg_interrupt ), - .cfg_interrupt_rdy ( cfg_interrupt_rdy ), - .cfg_interrupt_assert ( cfg_interrupt_assert ), - .cfg_interrupt_di ( cfg_interrupt_di ), - .cfg_interrupt_do ( cfg_interrupt_do ), - .cfg_interrupt_mmenable ( cfg_interrupt_mmenable ), - .cfg_interrupt_msienable ( cfg_interrupt_msienable ), - .cfg_interrupt_msixenable ( cfg_interrupt_msixenable ), - .cfg_interrupt_msixfm ( cfg_interrupt_msixfm ), - - .sys_clk ( pcie_refclk ), - .sys_reset ( ~pcie_reset_n )); - - riffa_wrapper_ml605 - #(/*AUTOINSTPARAM*/ - // Parameters - .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), - .C_NUM_CHNL (C_NUM_CHNL), - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES)) - riffa - (// Outputs - .CFG_INTERRUPT (cfg_interrupt), - .M_AXIS_RX_TREADY (m_axis_rx_tready), - .S_AXIS_TX_TDATA (s_axis_tx_tdata[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_TX_TKEEP (s_axis_tx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]), - .S_AXIS_TX_TLAST (s_axis_tx_tlast), - .S_AXIS_TX_TVALID (s_axis_tx_tvalid), - .S_AXIS_TX_TUSER (s_axis_tx_tuser[`SIG_XIL_TX_TUSER_W-1:0]), - .FC_SEL (fc_sel[`SIG_FC_SEL_W-1:0]), - .RST_OUT (rst_out), - .CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]), - .CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]), - .CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]), - .CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]), - .CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]), - // Inputs - .M_AXIS_RX_TDATA (m_axis_rx_tdata[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_RX_TKEEP (m_axis_rx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]), - .M_AXIS_RX_TLAST (m_axis_rx_tlast), - .M_AXIS_RX_TVALID (m_axis_rx_tvalid), - .M_AXIS_RX_TUSER (m_axis_rx_tuser[`SIG_XIL_RX_TUSER_W-1:0]), - .S_AXIS_TX_TREADY (s_axis_tx_tready), - .CFG_BUS_NUMBER (cfg_bus_number[`SIG_BUSID_W-1:0]), - .CFG_DEVICE_NUMBER (cfg_device_number[`SIG_DEVID_W-1:0]), - .CFG_FUNCTION_NUMBER (cfg_function_number[`SIG_FNID_W-1:0]), - .CFG_COMMAND (cfg_command[`SIG_CFGREG_W-1:0]), - .CFG_DCOMMAND (cfg_dcommand[`SIG_CFGREG_W-1:0]), - .CFG_LSTATUS (cfg_lstatus[`SIG_CFGREG_W-1:0]), - .CFG_LCOMMAND (cfg_lcommand[`SIG_CFGREG_W-1:0]), - .FC_CPLD (fc_cpld[`SIG_FC_CPLD_W-1:0]), - .FC_CPLH (fc_cplh[`SIG_FC_CPLH_W-1:0]), - .CFG_INTERRUPT_MSIEN (cfg_interrupt_msien), - .CFG_INTERRUPT_RDY (cfg_interrupt_rdy), - .USER_CLK (user_clk), - .USER_RESET (user_reset), - .CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]), - .CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]), - .CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]), - .CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]), - .CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]), - .CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]), - .CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]), - .RX_NP_OK (rx_np_ok), - .TX_CFG_GNT (tx_cfg_gnt) - /*AUTOINST*/); - - generate - for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels - chnl_tester - #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) - module1 - (.CLK(user_clk), - .RST(rst_out), // riffa_reset includes riffa_endpoint resets - // Rx interface - .CHNL_RX_CLK(chnl_rx_clk[chnl]), - .CHNL_RX(chnl_rx[chnl]), - .CHNL_RX_ACK(chnl_rx_ack[chnl]), - .CHNL_RX_LAST(chnl_rx_last[chnl]), - .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), - .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), - .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), - .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), - .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]), - // Tx interface - .CHNL_TX_CLK(chnl_tx_clk[chnl]), - .CHNL_TX(chnl_tx[chnl]), - .CHNL_TX_ACK(chnl_tx_ack[chnl]), - .CHNL_TX_LAST(chnl_tx_last[chnl]), - .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), - .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), - .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), - .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), - .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])); - end - endgenerate -endmodule diff --git a/fpga/xilinx/ml605/ML605Gen2x4If128/ip/PCIeGen2x4If128.xco b/fpga/xilinx/ml605/ML605Gen2x4If128/ip/PCIeGen2x4If128.xco deleted file mode 100644 index 5584a80..0000000 --- a/fpga/xilinx/ml605/ML605Gen2x4If128/ip/PCIeGen2x4If128.xco +++ /dev/null @@ -1,208 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.7 -# Date: Fri Aug 14 21:28:34 2015 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:v6_pcie:2.5 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc6vlx240t -SET devicefamily = virtex6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1156 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT Virtex-6_Integrated_Block_for_PCI_Express xilinx.com:ip:v6_pcie:2.5 -# END Select -# BEGIN Parameters -CSET acceptable_l0s_latency=Maximum_of_64_ns -CSET acceptable_l1_latency=No_limit -CSET ack_nak_timeout_func=Absolute -CSET ack_nak_timeout_value=0000 -CSET bar0_64bit=false -CSET bar0_enabled=true -CSET bar0_prefetchable=false -CSET bar0_scale=Kilobytes -CSET bar0_size=1 -CSET bar0_type=Memory -CSET bar1_64bit=false -CSET bar1_enabled=false -CSET bar1_prefetchable=false -CSET bar1_scale=Kilobytes -CSET bar1_size=2 -CSET bar1_type=N/A -CSET bar2_64bit=false -CSET bar2_enabled=false -CSET bar2_prefetchable=false -CSET bar2_scale=Bytes -CSET bar2_size=128 -CSET bar2_type=N/A -CSET bar3_64bit=false -CSET bar3_enabled=false -CSET bar3_prefetchable=false -CSET bar3_scale=Kilobytes -CSET bar3_size=2 -CSET bar3_type=N/A -CSET bar4_64bit=false -CSET bar4_enabled=false -CSET bar4_prefetchable=false -CSET bar4_scale=Kilobytes -CSET bar4_size=2 -CSET bar4_type=N/A -CSET bar5_enabled=false -CSET bar5_prefetchable=false -CSET bar5_scale=Kilobytes -CSET bar5_size=2 -CSET bar5_type=N/A -CSET base_class_menu=Simple_communication_controllers -CSET buf_opt_bma=true -CSET cardbus_cis_pointer=00000000 -CSET class_code_base=05 -CSET class_code_interface=00 -CSET class_code_sub=00 -CSET component_name=PCIeGen2x4If128 -CSET cost_table=1 -CSET cpl_finite=false -CSET cpl_timeout_disable_sup=false -CSET cpl_timeout_range=Range_B -CSET d0_pme_support=true -CSET d0_power_consumed=0 -CSET d0_power_consumed_factor=0 -CSET d0_power_dissipated=0 -CSET d0_power_dissipated_factor=0 -CSET d1_pme_support=true -CSET d1_power_consumed=0 -CSET d1_power_consumed_factor=0 -CSET d1_power_dissipated=0 -CSET d1_power_dissipated_factor=0 -CSET d1_support=false -CSET d2_pme_support=true -CSET d2_power_consumed=0 -CSET d2_power_consumed_factor=0 -CSET d2_power_dissipated=0 -CSET d2_power_dissipated_factor=0 -CSET d2_support=false -CSET d3_power_consumed=0 -CSET d3_power_consumed_factor=0 -CSET d3_power_dissipated=0 -CSET d3_power_dissipated_factor=0 -CSET d3cold_pme_support=false -CSET d3hot_pme_support=true -CSET de_emph=0 -CSET device_id=6024 -CSET device_port_type=PCI_Express_Endpoint_device -CSET device_specific_initialization=false -CSET disable_tx_aspm_l0s=false -CSET dll_link_active_cap=false -CSET downstream_link_num=00 -CSET dsn_enabled=false -CSET en_route_err_cor=false -CSET en_route_err_ftl=false -CSET en_route_err_nfl=false -CSET en_route_inta=false -CSET en_route_intb=false -CSET en_route_intc=false -CSET en_route_intd=false -CSET en_route_pm_pme=false -CSET en_route_pme_to=false -CSET en_route_pme_to_ack=false -CSET en_route_unlock=false -CSET enable_ack_nak_timer=false -CSET enable_lane_reversal=false -CSET enable_replay_timer=true -CSET enable_slot_clock_cfg=false -CSET expansion_rom_enabled=false -CSET expansion_rom_scale=Kilobytes -CSET expansion_rom_size=2 -CSET ext_pci_cfg_space=false -CSET ext_pci_cfg_space_addr=3FF -CSET extended_tag_field=true -CSET force_no_scrambling=false -CSET hw_auton_spd_disable=false -CSET intx_generation=false -CSET io_base_limit_registers=Disabled -CSET legacy_interrupt=NONE -CSET link_speed=5.0_GT/s -CSET max_payload_size=512_bytes -CSET maximum_link_width=X4 -CSET msi_64b=true -CSET msi_enabled=true -CSET msi_vec_mask=false -CSET msix_enabled=false -CSET msix_pba_bir=BAR_0 -CSET msix_pba_offset=0 -CSET msix_table_bir=BAR_0 -CSET msix_table_offset=0 -CSET msix_table_size=1 -CSET multiple_message_capable=1_vector -CSET no_soft_reset=true -CSET pci_cfg_space=false -CSET pci_cfg_space_addr=3F -CSET pcie_blk_locn=X0Y0 -CSET pcie_cap_slot_implemented=false -CSET pcie_debug_ports=false -CSET perf_level=High -CSET phantom_functions=No_function_number_bits_used -CSET pipe_pipeline=None -CSET prefetchable_memory_base_limit_registers=Disabled -CSET rcb=64_byte -CSET ref_clk_freq=100_MHz -CSET replay_timeout_func=Add -CSET replay_timeout_value=0026 -CSET revision_id=00 -CSET root_cap_crs=false -CSET slot_cap_attn_butn=false -CSET slot_cap_attn_ind=false -CSET slot_cap_elec_interlock=false -CSET slot_cap_hotplug_cap=false -CSET slot_cap_hotplug_surprise=false -CSET slot_cap_mrl=false -CSET slot_cap_no_cmd_comp_sup=false -CSET slot_cap_physical_slot_num=0 -CSET slot_cap_pwr_ctrl=false -CSET slot_cap_pwr_ind=false -CSET slot_cap_pwr_limit_scale=0 -CSET slot_cap_pwr_limit_value=0 -CSET sub_class_interface_menu=Generic_XT_compatible_serial_controller -CSET subsystem_id=0007 -CSET subsystem_vendor_id=10EE -CSET trans_buf_pipeline=None -CSET trgt_link_speed=4'h2 -CSET trim_tlp_digest=false -CSET upconfigure_capable=true -CSET user_clk_freq=250_default -CSET vc_cap_enabled=false -CSET vc_cap_reject_snoop=false -CSET vendor_id=10EE -CSET vsec_enabled=false -CSET xlnx_ref_board=ML_605 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-10-13T18:30:52Z -# END Extra information -GENERATE -# CRC: a826f31d diff --git a/fpga/xilinx/ml605/ML605Gen2x4If128/prj/ML605Gen2x4If128/ML605Gen2x4If128.xise b/fpga/xilinx/ml605/ML605Gen2x4If128/prj/ML605Gen2x4If128/ML605Gen2x4If128.xise deleted file mode 100644 index a04cb01..0000000 --- a/fpga/xilinx/ml605/ML605Gen2x4If128/prj/ML605Gen2x4If128/ML605Gen2x4If128.xise +++ /dev/null @@ -1,742 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/xilinx/ml605/riffa_wrapper_ml605.v b/fpga/xilinx/ml605/riffa_wrapper_ml605.v deleted file mode 100644 index e59f1c9..0000000 --- a/fpga/xilinx/ml605/riffa_wrapper_ml605.v +++ /dev/null @@ -1,647 +0,0 @@ -// ---------------------------------------------------------------------- -// Copyright (c) 2016, The Regents of the University of California All -// rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above -// copyright notice, this list of conditions and the following -// disclaimer in the documentation and/or other materials provided -// with the distribution. -// -// * Neither the name of The Regents of the University of California -// nor the names of its contributors may be used to endorse or -// promote products derived from this software without specific -// prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -// DAMAGE. -// ---------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// Filename: riffa_wrapper_ml605.v -// Version: 1.00.a -// Verilog Standard: Verilog-2001 -// Description: RIFFA wrapper for the ml605 Development board. -// Author: Dustin Richmond (@darichmond) -//----------------------------------------------------------------------------- -`include "trellis.vh" -`include "riffa.vh" -`include "xilinx.vh" -`include "ultrascale.vh" -`include "functions.vh" -`timescale 1ps / 1ps -module riffa_wrapper_ml605 - #(// Number of RIFFA Channels - parameter C_NUM_CHNL = 1, - // Bit-Width from Vivado IP Generator - parameter C_PCI_DATA_WIDTH = 128, - // 4-Byte Name for this FPGA - parameter C_MAX_PAYLOAD_BYTES = 256, - parameter C_LOG_NUM_TAGS = 5, - parameter C_FPGA_ID = "M605") - (// Interface: Xilinx RX - input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA, - input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP, - input M_AXIS_RX_TLAST, - input M_AXIS_RX_TVALID, - output M_AXIS_RX_TREADY, - input [`SIG_XIL_RX_TUSER_W-1:0] M_AXIS_RX_TUSER, - output RX_NP_OK, - output RX_NP_REQ, - - // Interface: Xilinx TX - output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA, - output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP, - output S_AXIS_TX_TLAST, - output S_AXIS_TX_TVALID, - input S_AXIS_TX_TREADY, - output [`SIG_XIL_TX_TUSER_W-1:0] S_AXIS_TX_TUSER, - output TX_CFG_GNT, - - // Interface: Xilinx Configuration - input [`SIG_BUSID_W-1:0] CFG_BUS_NUMBER, - input [`SIG_DEVID_W-1:0] CFG_DEVICE_NUMBER, - input [`SIG_FNID_W-1:0] CFG_FUNCTION_NUMBER, - input [`SIG_CFGREG_W-1:0] CFG_COMMAND, - input [`SIG_CFGREG_W-1:0] CFG_DCOMMAND, - input [`SIG_CFGREG_W-1:0] CFG_LSTATUS, - input [`SIG_CFGREG_W-1:0] CFG_LCOMMAND, - - // Interface: Xilinx Flow Control - input [`SIG_FC_CPLD_W-1:0] FC_CPLD, - input [`SIG_FC_CPLH_W-1:0] FC_CPLH, - output [`SIG_FC_SEL_W-1:0] FC_SEL, - - // Interface: Xilinx Interrupt - input CFG_INTERRUPT_MSIEN, - input CFG_INTERRUPT_RDY, - output CFG_INTERRUPT, - - input USER_CLK, - input USER_RESET, - - // RIFFA Interface Signals - output RST_OUT, - input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock - output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal - input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal - output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read - output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length - output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset - output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data - output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid - input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved - - input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock - input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal - output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal - input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write - input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words) - input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset - input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data - input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid - output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved - - localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver - localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2; - // ALTERA, XILINX or ULTRASCALE - localparam C_VENDOR = "XILINX"; - - localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32; - localparam C_PIPELINE_OUTPUT = 1; - localparam C_PIPELINE_INPUT = 1; - localparam C_DEPTH_PACKETS = 4; - - wire clk; - wire rst_in; - wire done_txc_rst; - wire done_txr_rst; - wire done_rxr_rst; - wire done_rxc_rst; - // Interface: RXC Engine - wire [C_PCI_DATA_WIDTH-1:0] rxc_data; - wire rxc_data_valid; - wire rxc_data_start_flag; - wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset; - wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe; - wire rxc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset; - wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe; - wire [`SIG_TAG_W-1:0] rxc_meta_tag; - wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr; - wire [`SIG_TYPE_W-1:0] rxc_meta_type; - wire [`SIG_LEN_W-1:0] rxc_meta_length; - wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining; - wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id; - wire rxc_meta_ep; - - // Interface: RXR Engine - wire [C_PCI_DATA_WIDTH-1:0] rxr_data; - wire rxr_data_valid; - wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable; - wire rxr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset; - wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe; - wire rxr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset; - wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe; - wire [`SIG_TC_W-1:0] rxr_meta_tc; - wire [`SIG_ATTR_W-1:0] rxr_meta_attr; - wire [`SIG_TAG_W-1:0] rxr_meta_tag; - wire [`SIG_TYPE_W-1:0] rxr_meta_type; - wire [`SIG_ADDR_W-1:0] rxr_meta_addr; - wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded; - wire [`SIG_REQID_W-1:0] rxr_meta_requester_id; - wire [`SIG_LEN_W-1:0] rxr_meta_length; - wire rxr_meta_ep; - - // interface: TXC Engine - wire txc_data_valid; - wire [C_PCI_DATA_WIDTH-1:0] txc_data; - wire txc_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset; - wire txc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset; - wire txc_data_ready; - - wire txc_meta_valid; - wire [`SIG_FBE_W-1:0] txc_meta_fdwbe; - wire [`SIG_LBE_W-1:0] txc_meta_ldwbe; - wire [`SIG_LOWADDR_W-1:0] txc_meta_addr; - wire [`SIG_TYPE_W-1:0] txc_meta_type; - wire [`SIG_LEN_W-1:0] txc_meta_length; - wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count; - wire [`SIG_TAG_W-1:0] txc_meta_tag; - wire [`SIG_REQID_W-1:0] txc_meta_requester_id; - wire [`SIG_TC_W-1:0] txc_meta_tc; - wire [`SIG_ATTR_W-1:0] txc_meta_attr; - wire txc_meta_ep; - wire txc_meta_ready; - wire txc_sent; - - // Interface: TXR Engine - wire txr_data_valid; - wire [C_PCI_DATA_WIDTH-1:0] txr_data; - wire txr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset; - wire txr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset; - wire txr_data_ready; - - wire txr_meta_valid; - wire [`SIG_FBE_W-1:0] txr_meta_fdwbe; - wire [`SIG_LBE_W-1:0] txr_meta_ldwbe; - wire [`SIG_ADDR_W-1:0] txr_meta_addr; - wire [`SIG_LEN_W-1:0] txr_meta_length; - wire [`SIG_TAG_W-1:0] txr_meta_tag; - wire [`SIG_TC_W-1:0] txr_meta_tc; - wire [`SIG_ATTR_W-1:0] txr_meta_attr; - wire [`SIG_TYPE_W-1:0] txr_meta_type; - wire txr_meta_ep; - wire txr_meta_ready; - wire txr_sent; - - // Classic Interface Wires - wire rx_tlp_ready; - wire [C_PCI_DATA_WIDTH-1:0] rx_tlp; - wire rx_tlp_end_flag; - wire [`SIG_OFFSET_W-1:0] rx_tlp_end_offset; - wire rx_tlp_start_flag; - wire [`SIG_OFFSET_W-1:0] rx_tlp_start_offset; - wire rx_tlp_valid; - wire [`SIG_BARDECODE_W-1:0] rx_tlp_bar_decode; - - wire tx_tlp_ready; - wire [C_PCI_DATA_WIDTH-1:0] tx_tlp; - wire tx_tlp_end_flag; - wire [`SIG_OFFSET_W-1:0] tx_tlp_end_offset; - wire tx_tlp_start_flag; - wire [`SIG_OFFSET_W-1:0] tx_tlp_start_offset; - wire tx_tlp_valid; - - // Unconnected Wires (Used in ultrascale interface) - // Interface: RQ (TXC) - wire s_axis_rq_tlast_nc; - wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata_nc; - wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser_nc; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep_nc; - wire s_axis_rq_tready_nc = 0; - wire s_axis_rq_tvalid_nc; - // Interface: RC (RXC) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata_nc = 0; - wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser_nc = 0; - wire m_axis_rc_tlast_nc = 0; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep_nc = 0; - wire m_axis_rc_tvalid_nc = 0; - wire m_axis_rc_tready_nc; - // Interface: CQ (RXR) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata_nc = 0; - wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser_nc = 0; - wire m_axis_cq_tlast_nc = 0; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep_nc = 0; - wire m_axis_cq_tvalid_nc = 0; - wire m_axis_cq_tready_nc = 0; - // Interface: CC (TXC) - wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata_nc; - wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser_nc; - wire s_axis_cc_tlast_nc; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep_nc; - wire s_axis_cc_tvalid_nc; - wire s_axis_cc_tready_nc = 0; - - // Interface: Configuration - wire config_bus_master_enable; - wire [`SIG_CPLID_W-1:0] config_completer_id; - wire config_cpl_boundary_sel; - wire config_interrupt_msienable; - wire [`SIG_LINKRATE_W-1:0] config_link_rate; - wire [`SIG_LINKWIDTH_W-1:0] config_link_width; - wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size; - wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size; - wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data; - wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr; - - wire intr_msi_request; - wire intr_msi_rdy; - - genvar chnl; - - reg rRxTlpValid; - reg rRxTlpEndFlag; - - assign clk = USER_CLK; - assign rst_in = USER_RESET; - - translation_xilinx - #(/*AUTOINSTPARAM*/ - // Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH)) - trans - (// Outputs - .RX_TLP (rx_tlp[C_PCI_DATA_WIDTH-1:0]), - .RX_TLP_VALID (rx_tlp_valid), - .RX_TLP_START_FLAG (rx_tlp_start_flag), - .RX_TLP_START_OFFSET (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RX_TLP_END_FLAG (rx_tlp_end_flag), - .RX_TLP_END_OFFSET (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RX_TLP_BAR_DECODE (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]), - .TX_TLP_READY (tx_tlp_ready), - .CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]), - .CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable), - .CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]), - .CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]), - .CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]), - .CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]), - .CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable), - .CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel), - .CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]), - .CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]), - .INTR_MSI_RDY (intr_msi_rdy), - // Inputs - .CLK (clk), - .RST_IN (rst_in), - .RX_TLP_READY (rx_tlp_ready), - .TX_TLP (tx_tlp[C_PCI_DATA_WIDTH-1:0]), - .TX_TLP_VALID (tx_tlp_valid), - .TX_TLP_START_FLAG (tx_tlp_start_flag), - .TX_TLP_START_OFFSET (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TX_TLP_END_FLAG (tx_tlp_end_flag), - .TX_TLP_END_OFFSET (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .INTR_MSI_REQUEST (intr_msi_request), - /*AUTOINST*/ - // Outputs - .M_AXIS_RX_TREADY (M_AXIS_RX_TREADY), - .RX_NP_OK (RX_NP_OK), - .RX_NP_REQ (RX_NP_REQ), - .S_AXIS_TX_TDATA (S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_TX_TKEEP (S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]), - .S_AXIS_TX_TLAST (S_AXIS_TX_TLAST), - .S_AXIS_TX_TVALID (S_AXIS_TX_TVALID), - .S_AXIS_TX_TUSER (S_AXIS_TX_TUSER[`SIG_XIL_TX_TUSER_W-1:0]), - .TX_CFG_GNT (TX_CFG_GNT), - .FC_SEL (FC_SEL[`SIG_FC_SEL_W-1:0]), - .CFG_INTERRUPT (CFG_INTERRUPT), - // Inputs - .M_AXIS_RX_TDATA (M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_RX_TKEEP (M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]), - .M_AXIS_RX_TLAST (M_AXIS_RX_TLAST), - .M_AXIS_RX_TVALID (M_AXIS_RX_TVALID), - .M_AXIS_RX_TUSER (M_AXIS_RX_TUSER[`SIG_XIL_RX_TUSER_W-1:0]), - .S_AXIS_TX_TREADY (S_AXIS_TX_TREADY), - .CFG_BUS_NUMBER (CFG_BUS_NUMBER[`SIG_BUSID_W-1:0]), - .CFG_DEVICE_NUMBER (CFG_DEVICE_NUMBER[`SIG_DEVID_W-1:0]), - .CFG_FUNCTION_NUMBER (CFG_FUNCTION_NUMBER[`SIG_FNID_W-1:0]), - .CFG_COMMAND (CFG_COMMAND[`SIG_CFGREG_W-1:0]), - .CFG_DCOMMAND (CFG_DCOMMAND[`SIG_CFGREG_W-1:0]), - .CFG_LSTATUS (CFG_LSTATUS[`SIG_CFGREG_W-1:0]), - .CFG_LCOMMAND (CFG_LCOMMAND[`SIG_CFGREG_W-1:0]), - .FC_CPLD (FC_CPLD[`SIG_FC_CPLD_W-1:0]), - .FC_CPLH (FC_CPLH[`SIG_FC_CPLH_W-1:0]), - .CFG_INTERRUPT_MSIEN (CFG_INTERRUPT_MSIEN), - .CFG_INTERRUPT_RDY (CFG_INTERRUPT_RDY)); - - engine_layer - #(// Parameters - .C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4), - /*AUTOINSTPARAM*/ - // Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), - .C_PIPELINE_INPUT (C_PIPELINE_INPUT), - .C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT), - .C_VENDOR (C_VENDOR)) - engine_layer_inst - (// Outputs - .RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]), - .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_DATA_VALID (rxc_data_valid), - .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]), - .RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]), - .RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]), - .RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]), - .RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]), - .RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]), - .RXC_META_EP (rxc_meta_ep), - - .RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]), - .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_VALID (rxr_data_valid), - .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), - .RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]), - .RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]), - .RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]), - .RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]), - .RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]), - .RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]), - .RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]), - .RXR_META_EP (rxr_meta_ep), - - .TXC_DATA_READY (txc_data_ready), - .TXC_META_READY (txc_meta_ready), - .TXC_SENT (txc_sent), - - .TXR_DATA_READY (txr_data_ready), - .TXR_META_READY (txr_meta_ready), - .TXR_SENT (txr_sent), - - .RST_LOGIC (RST_OUT), - // Unconnected Outputs - .TX_TLP (tx_tlp), - .TX_TLP_VALID (tx_tlp_valid), - .TX_TLP_START_FLAG (tx_tlp_start_flag), - .TX_TLP_START_OFFSET (tx_tlp_start_offset), - .TX_TLP_END_FLAG (tx_tlp_end_flag), - .TX_TLP_END_OFFSET (tx_tlp_end_offset), - - .RX_TLP_READY (rx_tlp_ready), - // Inputs - .CLK_BUS (clk), - .RST_BUS (rst_in), - - .CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]), - - .TXC_DATA_VALID (txc_data_valid), - .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), - .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_META_VALID (txc_meta_valid), - .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]), - .TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]), - .TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]), - .TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]), - .TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]), - .TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]), - .TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]), - .TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]), - .TXC_META_EP (txc_meta_ep), - - .TXR_DATA_VALID (txr_data_valid), - .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), - .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_META_VALID (txr_meta_valid), - .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]), - .TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]), - .TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]), - .TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]), - .TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]), - .TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]), - .TXR_META_EP (txr_meta_ep), - // Unconnected Inputs - .RX_TLP (rx_tlp), - .RX_TLP_VALID (rx_tlp_valid), - .RX_TLP_START_FLAG (rx_tlp_start_flag), - .RX_TLP_START_OFFSET (rx_tlp_start_offset), - .RX_TLP_END_FLAG (rx_tlp_end_flag), - .RX_TLP_END_OFFSET (rx_tlp_end_offset), - .RX_TLP_BAR_DECODE (rx_tlp_bar_decode), - - .TX_TLP_READY (tx_tlp_ready), - .DONE_TXC_RST (done_txc_rst), - .DONE_TXR_RST (done_txr_rst), - .DONE_RXR_RST (done_rxc_rst), - .DONE_RXC_RST (done_rxr_rst), - // Outputs - .M_AXIS_CQ_TREADY (m_axis_cq_tready_nc), - .M_AXIS_RC_TREADY (m_axis_rc_tready_nc), - .S_AXIS_CC_TVALID (s_axis_cc_tvalid_nc), - .S_AXIS_CC_TLAST (s_axis_cc_tlast_nc), - .S_AXIS_CC_TDATA (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_CC_TKEEP (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_CC_TUSER (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]), - .S_AXIS_RQ_TVALID (s_axis_rq_tvalid_nc), - .S_AXIS_RQ_TLAST (s_axis_rq_tlast_nc), - .S_AXIS_RQ_TDATA (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_RQ_TKEEP (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_RQ_TUSER (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]), - // Inputs - .M_AXIS_CQ_TVALID (m_axis_cq_tvalid_nc), - .M_AXIS_CQ_TLAST (m_axis_cq_tlast_nc), - .M_AXIS_CQ_TDATA (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_CQ_TKEEP (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_CQ_TUSER (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]), - .M_AXIS_RC_TVALID (m_axis_rc_tvalid_nc), - .M_AXIS_RC_TLAST (m_axis_rc_tlast_nc), - .M_AXIS_RC_TDATA (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_RC_TKEEP (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_RC_TUSER (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]), - .S_AXIS_CC_TREADY (s_axis_cc_tready_nc), - .S_AXIS_RQ_TREADY (s_axis_rq_tready_nc) - /*AUTOINST*/); - - riffa - #(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/ - /*AUTOINSTPARAM*/ - // Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_NUM_CHNL (C_NUM_CHNL), - .C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES), - .C_VENDOR (C_VENDOR), - .C_FPGA_NAME (C_FPGA_NAME), - .C_FPGA_ID (C_FPGA_ID), - .C_DEPTH_PACKETS (C_DEPTH_PACKETS)) - riffa_inst - (// Outputs - .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), - .TXC_DATA_VALID (txc_data_valid), - .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_META_VALID (txc_meta_valid), - .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]), - .TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]), - .TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]), - .TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]), - .TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]), - .TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]), - .TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]), - .TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]), - .TXC_META_EP (txc_meta_ep), - - .TXR_DATA_VALID (txr_data_valid), - .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), - .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_META_VALID (txr_meta_valid), - .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]), - .TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]), - .TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]), - .TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]), - .TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]), - .TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]), - .TXR_META_EP (txr_meta_ep), - - .INTR_MSI_REQUEST (intr_msi_request), - // Inputs - .CLK (clk), - .RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]), - .RXR_DATA_VALID (rxr_data_valid), - .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), - .RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]), - .RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]), - .RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]), - .RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]), - .RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]), - .RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]), - .RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]), - .RXR_META_EP (rxr_meta_ep), - - .RXC_DATA_VALID (rxc_data_valid), - .RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]), - .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]), - .RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]), - .RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]), - .RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]), - .RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]), - .RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]), - .RXC_META_EP (rxc_meta_ep), - - .TXC_DATA_READY (txc_data_ready), - .TXC_META_READY (txc_meta_ready), - .TXC_SENT (txc_sent), - - .TXR_DATA_READY (txr_data_ready), - .TXR_META_READY (txr_meta_ready), - .TXR_SENT (txr_sent), - - .CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]), - .CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable), - .CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]), - .CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]), - .CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]), - .CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]), - .CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable), - .CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel), - .CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]), - .CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]), - - .INTR_MSI_RDY (intr_msi_rdy), - - .DONE_TXC_RST (done_txc_rst), - .DONE_TXR_RST (done_txr_rst), - .RST_BUS (rst_in), - /*AUTOINST*/ - // Outputs - .RST_OUT (RST_OUT), - .CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]), - .CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]), - .CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]), - .CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]), - .CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]), - .CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]), - .CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]), - // Inputs - .CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]), - .CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]), - .CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]), - .CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]), - .CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]), - .CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]), - .CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]), - .CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]), - .CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0])); - -endmodule -// Local Variables: -// verilog-library-directories:("../../riffa_hdl/") -// End: - diff --git a/fpga/xilinx/vcu108/Makefile b/fpga/xilinx/vcu108/Makefile deleted file mode 100644 index 5306be7..0000000 --- a/fpga/xilinx/vcu108/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#----------------------------------------------------------------------- -# Filename: Makefile -# Version: 1.0 -# Description: Top-level makefile for building the example -# projects in a board -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------- -BOARD:=vcu108 -BOARD_PROJECTS:=VCU108_Gen1x8If64 VCU108_Gen2x8If128 VCU108_Gen3x4If128 -BOARD_TYPE:=ultrascale -VENDOR:=xilinx -include ../vendor.mk diff --git a/fpga/xilinx/vcu108/VCU108_Gen1x8If64/Makefile b/fpga/xilinx/vcu108/VCU108_Gen1x8If64/Makefile deleted file mode 100644 index 795546b..0000000 --- a/fpga/xilinx/vcu108/VCU108_Gen1x8If64/Makefile +++ /dev/null @@ -1,62 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#----------------------------------------------------------------------- -# Filename: Makefile -# Version: 1.0 -# Description: Project-level makefile for building an example project -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------- -# This make file expects the following variables to be set: -# RIFFA_HDL_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory. -# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to -# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory -WIDTH=64 -TYPE=ultrascale -CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))) -PROJECT=$(shell basename $(CURRENT_PATH)) - -ifndef RIFFA_HDL_PATH - RIFFA_HDL_PATH:=../../../riffa_hdl -endif -ifndef BOARD_PATH - BOARD_PATH:=.. -endif -ifndef JOBS - JOBS=1 -endif -include $(RIFFA_HDL_PATH)/riffa.mk -include $(BOARD_PATH)/board.mk - -PROJECT_IP+=ip/PCIeGen1x8If64.xci diff --git a/fpga/xilinx/vcu108/VCU108_Gen1x8If64/bit/VCU108_Gen1x8If64.bit b/fpga/xilinx/vcu108/VCU108_Gen1x8If64/bit/VCU108_Gen1x8If64.bit deleted file mode 100644 index b63d6fb..0000000 Binary files a/fpga/xilinx/vcu108/VCU108_Gen1x8If64/bit/VCU108_Gen1x8If64.bit and /dev/null differ diff --git a/fpga/xilinx/vcu108/VCU108_Gen1x8If64/constr/VCU108_Gen1x8If64.xdc b/fpga/xilinx/vcu108/VCU108_Gen1x8If64/constr/VCU108_Gen1x8If64.xdc deleted file mode 100644 index e478e68..0000000 --- a/fpga/xilinx/vcu108/VCU108_Gen1x8If64/constr/VCU108_Gen1x8If64.xdc +++ /dev/null @@ -1,120 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#---------------------------------------------------------------------------- -# Filename: VCU108_Top.xdc -# Version: 1.00.a -# Verilog Standard: Verilog-2001 -# Description: Xilinx Design Constraints for the VCU108 board. -# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin -# -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------------- -# -######################################################################################################################### -# User Constraints -######################################################################################################################### - -############################################################################### -# User Time Names / User Time Groups / Time Specs -############################################################################### - -############################################################################### -# User Physical Constraints -############################################################################### - -set_property PACKAGE_PIN AT32 [get_ports {LED[0]}] -set_property PACKAGE_PIN AV34 [get_ports {LED[1]}] -set_property PACKAGE_PIN AY30 [get_ports {LED[2]}] -set_property PACKAGE_PIN BB32 [get_ports {LED[3]}] -set_property PACKAGE_PIN BF32 [get_ports {LED[4]}] -set_property PACKAGE_PIN AV36 [get_ports {LED[5]}] -set_property PACKAGE_PIN AY35 [get_ports {LED[6]}] -set_property PACKAGE_PIN BA37 [get_ports {LED[7]}] - -set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[4]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[5]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[6]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[7]}] - -set_false_path -to [get_ports -filter NAME=~LED*] - -######################################################################################################################### -# End User Constraints -######################################################################################################################### -# -# -# -######################################################################################################################### -# PCIE Core Constraints -######################################################################################################################### - -# -# SYS reset (input) signal. The sys_reset_n signal should be -# obtained from the PCI Express interface if possible. For -# slot based form factors, a system reset signal is usually -# present on the connector. For cable based form factors, a -# system reset signal may not be available. In this case, the -# system reset signal must be generated locally by some form of -# supervisory circuit. You may change the IOSTANDARD and LOC -# to suit your requirements and VCCO voltage banking rules. -# Some 7 series devices do not have 3.3 V I/Os available. -# Therefore the appropriate level shift is required to operate -# with these devices that contain only 1.8 V banks. -# - -set_property LOC [get_package_pins -filter {PIN_FUNC == IO_T3U_N12_PERSTN0_65}] [get_ports PCIE_RESET_N] -set_property IOSTANDARD LVCMOS15 [get_ports PCIE_RESET_N] -set_property PULLUP true [get_ports PCIE_RESET_N] - -#set_property LOC [get_package_pins -filter {PIN_FUNC == MGTREFCLK0P_225}] [get_ports refclk_ibuf] -set_property LOC AN9 [get_cells refclk_ibuf] - -############################################################################### -# Timing Constraints -############################################################################### -create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O] - -############################################################################### -# Physical Constraints -############################################################################### - -set_false_path -from [get_ports PCIE_RESET_N] -############################################################################### -# End -############################################################################### diff --git a/fpga/xilinx/vcu108/VCU108_Gen1x8If64/hdl/VCU108_Gen1x8If64.v b/fpga/xilinx/vcu108/VCU108_Gen1x8If64/hdl/VCU108_Gen1x8If64.v deleted file mode 100644 index 7362017..0000000 --- a/fpga/xilinx/vcu108/VCU108_Gen1x8If64/hdl/VCU108_Gen1x8If64.v +++ /dev/null @@ -1,491 +0,0 @@ -// ---------------------------------------------------------------------- -// Copyright (c) 2016, The Regents of the University of California All -// rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above -// copyright notice, this list of conditions and the following -// disclaimer in the documentation and/or other materials provided -// with the distribution. -// -// * Neither the name of The Regents of the University of California -// nor the names of its contributors may be used to endorse or -// promote products derived from this software without specific -// prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -// DAMAGE. -// ---------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// Filename: VCU108_Gen1x8If64.v -// Version: 1.00.a -// Verilog Standard: Verilog-2001 -// Description: Top level module for RIFFA 2.2 reference design for the -// the Xilinx VCU108 Development Board. -// Author: Dustin Richmond (@darichmond) -//----------------------------------------------------------------------------- -`include "functions.vh" -`include "riffa.vh" -`include "ultrascale.vh" -`timescale 1ps / 1ps -module VCU108_Gen1x8If64 - #(// Number of RIFFA Channels - parameter C_NUM_CHNL = 1, - // Number of PCIe Lanes - parameter C_NUM_LANES = 8, - // Settings from Vivado IP Generator - parameter C_PCI_DATA_WIDTH = 64, - parameter C_MAX_PAYLOAD_BYTES = 256, - parameter C_LOG_NUM_TAGS = 6) - (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP, - output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN, - input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP, - input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN, - - output [7:0] LED, - input PCIE_REFCLK_P, - input PCIE_REFCLK_N, - input PCIE_RESET_N); - - // Clocks, etc - wire user_lnk_up; - wire user_clk; - wire user_reset; - wire pcie_refclk; - wire pcie_refclk_by2; - wire pcie_reset_n; - - // Interface: RQ (TXC) - wire s_axis_rq_tlast; - wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata; - wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep; - wire s_axis_rq_tready; - wire s_axis_rq_tvalid; - // Interface: RC (RXC) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata; - wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser; - wire m_axis_rc_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep; - wire m_axis_rc_tvalid; - wire m_axis_rc_tready; - // Interface: CQ (RXR) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata; - wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser; - wire m_axis_cq_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep; - wire m_axis_cq_tvalid; - wire m_axis_cq_tready; - // Interface: CC (TXC) - wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata; - wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser; - wire s_axis_cc_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep; - wire s_axis_cc_tvalid; - wire s_axis_cc_tready; - - // Configuration (CFG) Interface - wire [3:0] pcie_rq_seq_num; - wire pcie_rq_seq_num_vld; - wire [5:0] pcie_rq_tag; - wire pcie_rq_tag_vld; - wire pcie_cq_np_req; - wire [5:0] pcie_cq_np_req_count; - - wire cfg_phy_link_down; - wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH - wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE - wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD - wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST - wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE - wire [5:0] cfg_function_power_state; // Ignorable but not removable - wire [11:0] cfg_vf_status; // Ignorable but not removable - wire [17:0] cfg_vf_power_state; // Ignorable but not removable - wire [1:0] cfg_link_power_state; // Ignorable but not removable - - // Error Reporting Interface - wire cfg_err_cor_out; - wire cfg_err_nonfatal_out; - wire cfg_err_fatal_out; - - wire cfg_ltr_enable; - wire [5:0] cfg_ltssm_state; - wire [1:0] cfg_rcb_status; - wire [1:0] cfg_dpa_substate_change; - wire [1:0] cfg_obff_enable; - wire cfg_pl_status_change; - - wire [1:0] cfg_tph_requester_enable; - wire [5:0] cfg_tph_st_mode; - wire [5:0] cfg_vf_tph_requester_enable; - wire [17:0] cfg_vf_tph_st_mode; - wire [7:0] cfg_fc_ph; - wire [11:0] cfg_fc_pd; - wire [7:0] cfg_fc_nph; - wire [11:0] cfg_fc_npd; - wire [7:0] cfg_fc_cplh; - wire [11:0] cfg_fc_cpld; - wire [2:0] cfg_fc_sel; - - // Interrupt Interface Signals - wire [3:0] cfg_interrupt_int; - wire [1:0] cfg_interrupt_pending; - wire cfg_interrupt_sent; - wire [1:0] cfg_interrupt_msi_enable; - wire [5:0] cfg_interrupt_msi_vf_enable; - wire [5:0] cfg_interrupt_msi_mmenable; - wire cfg_interrupt_msi_mask_update; - wire [31:0] cfg_interrupt_msi_data; - wire [3:0] cfg_interrupt_msi_select; - wire [31:0] cfg_interrupt_msi_int; - wire [63:0] cfg_interrupt_msi_pending_status; - wire cfg_interrupt_msi_sent; - wire cfg_interrupt_msi_fail; - wire [2:0] cfg_interrupt_msi_attr; - wire cfg_interrupt_msi_tph_present; - wire [1:0] cfg_interrupt_msi_tph_type; - wire [8:0] cfg_interrupt_msi_tph_st_tag; - wire [2:0] cfg_interrupt_msi_function_number; - - wire rst_out; - wire [C_NUM_CHNL-1:0] chnl_rx_clk; - wire [C_NUM_CHNL-1:0] chnl_rx; - wire [C_NUM_CHNL-1:0] chnl_rx_ack; - wire [C_NUM_CHNL-1:0] chnl_rx_last; - wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; - wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data; - wire [C_NUM_CHNL-1:0] chnl_rx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_rx_data_ren; - - wire [C_NUM_CHNL-1:0] chnl_tx_clk; - wire [C_NUM_CHNL-1:0] chnl_tx; - wire [C_NUM_CHNL-1:0] chnl_tx_ack; - wire [C_NUM_CHNL-1:0] chnl_tx_last; - wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; - wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data; - wire [C_NUM_CHNL-1:0] chnl_tx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_tx_data_ren; - - genvar chnl; - - IBUF - #() - pci_reset_n_ibuf - (.O(pcie_reset_n), - .I(PCIE_RESET_N)); - - IBUFDS_GTE3 - #() - refclk_ibuf - (.O(pcie_refclk), - .ODIV2(pcie_refclk_by2), - .I(PCIE_REFCLK_P), - .CEB(1'b0), - .IB(PCIE_REFCLK_N)); - - OBUF - #() - led_0_obuf - (.O(LED[0]), - .I(cfg_ltssm_state[0])); - OBUF - #() - led_1_obuf - (.O(LED[1]), - .I(cfg_ltssm_state[1])); - OBUF - #() - led_2_obuf - (.O(LED[2]), - .I(cfg_ltssm_state[2])); - OBUF - #() - led_3_obuf - (.O(LED[3]), - .I(cfg_ltssm_state[3])); - OBUF - #() - led_4_obuf - (.O(LED[4]), - .I(cfg_ltssm_state[4])); - OBUF - #() - led_5_obuf - (.O(LED[5]), - .I(cfg_ltssm_state[5])); - OBUF - #() - led_6_obuf - (.O(LED[6]), - .I(user_reset)); - OBUF - #() - led_7_obuf - (.O(LED[7]), - .I(rst_out)); - - // Core Top Level Wrapper - PCIeGen1x8If64 - #() - pcie3_7x_0_i - (//--------------------------------------------------------------------- - // PCI Express (pci_exp) Interface - //--------------------------------------------------------------------- - .pci_exp_txn ( PCI_EXP_TXN ), - .pci_exp_txp ( PCI_EXP_TXP ), - .pci_exp_rxn ( PCI_EXP_RXN ), - .pci_exp_rxp ( PCI_EXP_RXP ), - - //--------------------------------------------------------------------- - // AXI Interface - //--------------------------------------------------------------------- - .user_clk ( user_clk ), - .user_reset ( user_reset ), - .user_lnk_up ( user_lnk_up ), - - .s_axis_rq_tlast ( s_axis_rq_tlast ), - .s_axis_rq_tdata ( s_axis_rq_tdata ), - .s_axis_rq_tuser ( s_axis_rq_tuser ), - .s_axis_rq_tkeep ( s_axis_rq_tkeep ), - .s_axis_rq_tready ( s_axis_rq_tready ), - .s_axis_rq_tvalid ( s_axis_rq_tvalid ), - - .m_axis_rc_tdata ( m_axis_rc_tdata ), - .m_axis_rc_tuser ( m_axis_rc_tuser ), - .m_axis_rc_tlast ( m_axis_rc_tlast ), - .m_axis_rc_tkeep ( m_axis_rc_tkeep ), - .m_axis_rc_tvalid ( m_axis_rc_tvalid ), - .m_axis_rc_tready ( {22{m_axis_rc_tready}} ), - - .m_axis_cq_tdata ( m_axis_cq_tdata ), - .m_axis_cq_tuser ( m_axis_cq_tuser ), - .m_axis_cq_tlast ( m_axis_cq_tlast ), - .m_axis_cq_tkeep ( m_axis_cq_tkeep ), - .m_axis_cq_tvalid ( m_axis_cq_tvalid ), - .m_axis_cq_tready ( {22{m_axis_cq_tready}} ), - - .s_axis_cc_tdata ( s_axis_cc_tdata ), - .s_axis_cc_tuser ( s_axis_cc_tuser ), - .s_axis_cc_tlast ( s_axis_cc_tlast ), - .s_axis_cc_tkeep ( s_axis_cc_tkeep ), - .s_axis_cc_tvalid ( s_axis_cc_tvalid ), - .s_axis_cc_tready ( s_axis_cc_tready ), - - //--------------------------------------------------------------------- - // Configuration (CFG) Interface - //--------------------------------------------------------------------- - .pcie_rq_seq_num ( pcie_rq_seq_num ), - .pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ), - .pcie_rq_tag ( pcie_rq_tag ), - .pcie_rq_tag_vld ( pcie_rq_tag_vld ), - .pcie_cq_np_req ( pcie_cq_np_req ), - .pcie_cq_np_req_count ( pcie_cq_np_req_count ), - .cfg_phy_link_down ( cfg_phy_link_down ), - .cfg_phy_link_status ( cfg_phy_link_status), - .cfg_negotiated_width ( cfg_negotiated_width ), - .cfg_current_speed ( cfg_current_speed ), - .cfg_max_payload ( cfg_max_payload ), - .cfg_max_read_req ( cfg_max_read_req ), - .cfg_function_status ( cfg_function_status ), - .cfg_function_power_state ( cfg_function_power_state ), - .cfg_vf_status ( cfg_vf_status ), - .cfg_vf_power_state ( cfg_vf_power_state ), - .cfg_link_power_state ( cfg_link_power_state ), - // Error Reporting Interface - .cfg_err_cor_out ( cfg_err_cor_out ), - .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), - .cfg_err_fatal_out ( cfg_err_fatal_out ), - .cfg_ltr_enable ( cfg_ltr_enable ), - .cfg_ltssm_state ( cfg_ltssm_state ), - .cfg_rcb_status ( cfg_rcb_status ), - .cfg_dpa_substate_change ( cfg_dpa_substate_change ), - .cfg_obff_enable ( cfg_obff_enable ), - .cfg_pl_status_change ( cfg_pl_status_change ), - .cfg_tph_requester_enable ( cfg_tph_requester_enable ), - .cfg_tph_st_mode ( cfg_tph_st_mode ), - .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), - .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), - .cfg_fc_ph ( cfg_fc_ph ), - .cfg_fc_pd ( cfg_fc_pd ), - .cfg_fc_nph ( cfg_fc_nph ), - .cfg_fc_npd ( cfg_fc_npd ), - .cfg_fc_cplh ( cfg_fc_cplh ), - .cfg_fc_cpld ( cfg_fc_cpld ), - .cfg_fc_sel ( cfg_fc_sel ), - //--------------------------------------------------------------------- - // EP Only - //--------------------------------------------------------------------- - // Interrupt Interface Signals - .cfg_interrupt_int ( cfg_interrupt_int ), - .cfg_interrupt_pending ( cfg_interrupt_pending ), - .cfg_interrupt_sent ( cfg_interrupt_sent ), - .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ), - .cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ), - .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), - .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), - .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), - .cfg_interrupt_msi_select ( cfg_interrupt_msi_select ), - .cfg_interrupt_msi_int ( cfg_interrupt_msi_int ), - .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ), - .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), - .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), - .cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ), - .cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ), - .cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ), - .cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ), - .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ), - .cfg_interrupt_msi_pending_status_function_num ( 4'b0), - .cfg_interrupt_msi_pending_status_data_enable ( 1'b0), - - - //--------------------------------------------------------------------------------------// - // Reset Pass Through Signals - // - Only used for PCIe_X0Y0 - //--------------------------------------------------------------------------------------// - .pcie_perstn0_out (), - .pcie_perstn1_in (1'b0), - .pcie_perstn1_out (), - - //--------------------------------------------------------------------- - // System(SYS) Interface - //--------------------------------------------------------------------- - .sys_clk (pcie_refclk_by2), - .sys_clk_gt (pcie_refclk), - .sys_reset (pcie_reset_n)); - - riffa_wrapper_vcu108 - #(/*AUTOINSTPARAM*/ - // Parameters - .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), - .C_NUM_CHNL (C_NUM_CHNL), - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES)) - riffa - (// Outputs - .M_AXIS_CQ_TREADY (m_axis_cq_tready), - .M_AXIS_RC_TREADY (m_axis_rc_tready), - .S_AXIS_CC_TVALID (s_axis_cc_tvalid), - .S_AXIS_CC_TLAST (s_axis_cc_tlast), - .S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]), - .S_AXIS_RQ_TVALID (s_axis_rq_tvalid), - .S_AXIS_RQ_TLAST (s_axis_rq_tlast), - .S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]), - .USER_CLK (user_clk), - .USER_RESET (user_reset), - .CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]), - .CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]), - .CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]), - .CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]), - .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]), - .CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]), - .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present), - .CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]), - .CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]), - .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]), - .CFG_FC_SEL (cfg_fc_sel[2:0]), - .PCIE_CQ_NP_REQ (pcie_cq_np_req), - .RST_OUT (rst_out), - .CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]), - .CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]), - .CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]), - .CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]), - .CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]), - // Inputs - .M_AXIS_CQ_TVALID (m_axis_cq_tvalid), - .M_AXIS_CQ_TLAST (m_axis_cq_tlast), - .M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]), - .M_AXIS_RC_TVALID (m_axis_rc_tvalid), - .M_AXIS_RC_TLAST (m_axis_rc_tlast), - .M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]), - .S_AXIS_CC_TREADY (s_axis_cc_tready), - .S_AXIS_RQ_TREADY (s_axis_rq_tready), - .CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]), - .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update), - .CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]), - .CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent), - .CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail), - .CFG_FC_CPLH (cfg_fc_cplh[7:0]), - .CFG_FC_CPLD (cfg_fc_cpld[11:0]), - .CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]), - .CFG_CURRENT_SPEED (cfg_current_speed[2:0]), - .CFG_MAX_PAYLOAD (cfg_max_payload[2:0]), - .CFG_MAX_READ_REQ (cfg_max_read_req[2:0]), - .CFG_FUNCTION_STATUS (cfg_function_status[7:0]), - .CFG_RCB_STATUS (cfg_rcb_status[1:0]), - .CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]), - .CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]), - .CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]), - .CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]), - .CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]), - .CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]), - .CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])); - - generate - for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels - chnl_tester - #(/*AUTOINSTPARAM*/ - // Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH)) - module1 - (.CLK(user_clk), - .RST(rst_out), // riffa_reset includes riffa_endpoint resets - // Rx interface - .CHNL_RX_CLK(chnl_rx_clk[chnl]), - .CHNL_RX(chnl_rx[chnl]), - .CHNL_RX_ACK(chnl_rx_ack[chnl]), - .CHNL_RX_LAST(chnl_rx_last[chnl]), - .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), - .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), - .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), - .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), - .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]), - // Tx interface - .CHNL_TX_CLK(chnl_tx_clk[chnl]), - .CHNL_TX(chnl_tx[chnl]), - .CHNL_TX_ACK(chnl_tx_ack[chnl]), - .CHNL_TX_LAST(chnl_tx_last[chnl]), - .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), - .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), - .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), - .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), - .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl]) - /*AUTOINST*/); - end - endgenerate -endmodule -// Local Variables: -// verilog-library-directories:("../../../../riffa_hdl/" "../../") -// End: - diff --git a/fpga/xilinx/vcu108/VCU108_Gen1x8If64/ip/PCIeGen1x8If64.xci b/fpga/xilinx/vcu108/VCU108_Gen1x8If64/ip/PCIeGen1x8If64.xci deleted file mode 100644 index f1060e1..0000000 --- a/fpga/xilinx/vcu108/VCU108_Gen1x8If64/ip/PCIeGen1x8If64.xci +++ /dev/null @@ -1,729 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - PCIeGen1x8If64 - - - FALSE - FALSE - FALSE - TRUE - 0x00000 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - TRUE - FALSE - TRUE - FALSE - 16KB - 1 - 64 - TRUE - 0 - FALSE - FALSE - FALSE - FALSE - 0x000 - NONE - FALSE - TRUE - FALSE - FALSE - NONE - 2 - 2.0 - FALSE - FALSE - FALSE - 0x000 - 0x000 - 0x00 - 0x03 - 0x4 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x058000 - 0x8018 - FALSE - FALSE - FALSE - FALSE - 0x0 - FALSE - TRUE - FALSE - 0x2 - 0x000 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x000 - 0x00 - FALSE - 0x0 - 0 - TRUE - 0x000 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0xC0 - 0x000 - 0x90 - FALSE - FALSE - FALSE - FALSE - FALSE - 0x000 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x0 - 0x0000 - 0x0000 - 0x00000553 - 0x0000 - 0x0007 - 0x10EE - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0x10EE - FALSE - FALSE - 0x000 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x058000 - 0x8011 - 0x2 - 0x000 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x000 - 0x00 - FALSE - 0x0 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - 0x000 - 0x00 - FALSE - 0x000 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x0 - 0x0000 - 0x0001 - 0x00000553 - 0x0000 - 0x0007 - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 4 - FALSE - 0 - FALSE - 1 - 8 - TRUE - FALSE - 0 - 0 - GTH_Quad_224 - 1 - 0x00000000 - FALSE - 0 - 0x000 - 0x00 - 0x028 - 0x20 - 0x198 - 0x20 - FALSE - FALSE - 0x0 - FALSE - FALSE - 3 - 0x000 - 0x80 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - FALSE - 1 - 0 - 0 - 0 - 0 - 0 - 0 - ES2 - 0 - true - false - PCIeGen1x8If64 - 15 - false - false - 058000 - 8018 - false - false - false - 00_Not_Supported - false - false - NONE - true - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - false - false - false - false - 00 - 0 - N/A - 0000 - 00000553 - 0000 - 0007 - 10EE - false - false - false - 058000 - 8011 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 0 - N/A - 0001 - 00000553 - 0000 - 0007 - false - 4 - 2.5_GT/s - X8 - 100_MHz - Default - 0 - 0 - false - false - 1 - false - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - DWORD_Aligned - No_ASPM - 250 - true - 2FFFF - false - 64_bit - false - false - true - false - true - false - 250 - true - PCI_Express_Endpoint_device - false - false - true - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - None - Advanced - X0Y0 - false - Extreme - false - true - false - false - true - false - Kilobytes - 1 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Simple_communication_controllers - 05 - 00 - 80 - 512_bytes - false - false - false - Kilobytes - 2 - false - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - 0 - Generic_XT_compatible_serial_controller - false - false - true - false - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Simple_communication_controllers - 05 - 00 - 80 - 512_bytes - false - false - false - Kilobytes - 2 - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Generic_XT_compatible_serial_controller - false - false - CPLL - false - GTH_Quad_224 - ACTIVE LOW - None - true - false - 10EE - None - virtexu - - xcvu095 - ffva2104 - VERILOG - es2 - MIXED - -2 - E - TRUE - TRUE - IP_Flow - 1 - TRUE - . - - . - 2015.4 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/xilinx/vcu108/VCU108_Gen1x8If64/prj/VCU108_Gen1x8If64.xpr b/fpga/xilinx/vcu108/VCU108_Gen1x8If64/prj/VCU108_Gen1x8If64.xpr deleted file mode 100644 index f7f7de3..0000000 --- a/fpga/xilinx/vcu108/VCU108_Gen1x8If64/prj/VCU108_Gen1x8If64.xpr +++ /dev/null @@ -1,810 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/xilinx/vcu108/VCU108_Gen2x8If128/Makefile b/fpga/xilinx/vcu108/VCU108_Gen2x8If128/Makefile deleted file mode 100644 index d760cff..0000000 --- a/fpga/xilinx/vcu108/VCU108_Gen2x8If128/Makefile +++ /dev/null @@ -1,62 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#----------------------------------------------------------------------- -# Filename: Makefile -# Version: 1.0 -# Description: Project-level makefile for building an example project -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------- -# This make file expects the following variables to be set: -# RIFFA_HDL_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory. -# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to -# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory -WIDTH=128 -TYPE=ultrascale -CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))) -PROJECT=$(shell basename $(CURRENT_PATH)) - -ifndef RIFFA_HDL_PATH - RIFFA_HDL_PATH:=../../../riffa_hdl -endif -ifndef BOARD_PATH - BOARD_PATH:=.. -endif -ifndef JOBS - JOBS=1 -endif -include $(RIFFA_HDL_PATH)/riffa.mk -include $(BOARD_PATH)/board.mk - -PROJECT_IP+=ip/PCIeGen2x8If128.xci diff --git a/fpga/xilinx/vcu108/VCU108_Gen2x8If128/bit/VCU108_Gen2x8If128.bit b/fpga/xilinx/vcu108/VCU108_Gen2x8If128/bit/VCU108_Gen2x8If128.bit deleted file mode 100644 index f688f55..0000000 Binary files a/fpga/xilinx/vcu108/VCU108_Gen2x8If128/bit/VCU108_Gen2x8If128.bit and /dev/null differ diff --git a/fpga/xilinx/vcu108/VCU108_Gen2x8If128/constr/VCU108_Gen2x8If128.xdc b/fpga/xilinx/vcu108/VCU108_Gen2x8If128/constr/VCU108_Gen2x8If128.xdc deleted file mode 100644 index e478e68..0000000 --- a/fpga/xilinx/vcu108/VCU108_Gen2x8If128/constr/VCU108_Gen2x8If128.xdc +++ /dev/null @@ -1,120 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#---------------------------------------------------------------------------- -# Filename: VCU108_Top.xdc -# Version: 1.00.a -# Verilog Standard: Verilog-2001 -# Description: Xilinx Design Constraints for the VCU108 board. -# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin -# -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------------- -# -######################################################################################################################### -# User Constraints -######################################################################################################################### - -############################################################################### -# User Time Names / User Time Groups / Time Specs -############################################################################### - -############################################################################### -# User Physical Constraints -############################################################################### - -set_property PACKAGE_PIN AT32 [get_ports {LED[0]}] -set_property PACKAGE_PIN AV34 [get_ports {LED[1]}] -set_property PACKAGE_PIN AY30 [get_ports {LED[2]}] -set_property PACKAGE_PIN BB32 [get_ports {LED[3]}] -set_property PACKAGE_PIN BF32 [get_ports {LED[4]}] -set_property PACKAGE_PIN AV36 [get_ports {LED[5]}] -set_property PACKAGE_PIN AY35 [get_ports {LED[6]}] -set_property PACKAGE_PIN BA37 [get_ports {LED[7]}] - -set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[4]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[5]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[6]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[7]}] - -set_false_path -to [get_ports -filter NAME=~LED*] - -######################################################################################################################### -# End User Constraints -######################################################################################################################### -# -# -# -######################################################################################################################### -# PCIE Core Constraints -######################################################################################################################### - -# -# SYS reset (input) signal. The sys_reset_n signal should be -# obtained from the PCI Express interface if possible. For -# slot based form factors, a system reset signal is usually -# present on the connector. For cable based form factors, a -# system reset signal may not be available. In this case, the -# system reset signal must be generated locally by some form of -# supervisory circuit. You may change the IOSTANDARD and LOC -# to suit your requirements and VCCO voltage banking rules. -# Some 7 series devices do not have 3.3 V I/Os available. -# Therefore the appropriate level shift is required to operate -# with these devices that contain only 1.8 V banks. -# - -set_property LOC [get_package_pins -filter {PIN_FUNC == IO_T3U_N12_PERSTN0_65}] [get_ports PCIE_RESET_N] -set_property IOSTANDARD LVCMOS15 [get_ports PCIE_RESET_N] -set_property PULLUP true [get_ports PCIE_RESET_N] - -#set_property LOC [get_package_pins -filter {PIN_FUNC == MGTREFCLK0P_225}] [get_ports refclk_ibuf] -set_property LOC AN9 [get_cells refclk_ibuf] - -############################################################################### -# Timing Constraints -############################################################################### -create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O] - -############################################################################### -# Physical Constraints -############################################################################### - -set_false_path -from [get_ports PCIE_RESET_N] -############################################################################### -# End -############################################################################### diff --git a/fpga/xilinx/vcu108/VCU108_Gen2x8If128/hdl/VCU108_Gen2x8If128.v b/fpga/xilinx/vcu108/VCU108_Gen2x8If128/hdl/VCU108_Gen2x8If128.v deleted file mode 100644 index 09a39cb..0000000 --- a/fpga/xilinx/vcu108/VCU108_Gen2x8If128/hdl/VCU108_Gen2x8If128.v +++ /dev/null @@ -1,491 +0,0 @@ -// ---------------------------------------------------------------------- -// Copyright (c) 2016, The Regents of the University of California All -// rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above -// copyright notice, this list of conditions and the following -// disclaimer in the documentation and/or other materials provided -// with the distribution. -// -// * Neither the name of The Regents of the University of California -// nor the names of its contributors may be used to endorse or -// promote products derived from this software without specific -// prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -// DAMAGE. -// ---------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// Filename: VCU108_Gen2x8If128.v -// Version: 1.00.a -// Verilog Standard: Verilog-2001 -// Description: Top level module for RIFFA 2.2 reference design for the -// the Xilinx VCU108 Development Board. -// Author: Dustin Richmond (@darichmond) -//----------------------------------------------------------------------------- -`include "functions.vh" -`include "riffa.vh" -`include "ultrascale.vh" -`timescale 1ps / 1ps -module VCU108_Gen2x8If128 - #(// Number of RIFFA Channels - parameter C_NUM_CHNL = 1, - // Number of PCIe Lanes - parameter C_NUM_LANES = 8, - // Settings from Vivado IP Generator - parameter C_PCI_DATA_WIDTH = 128, - parameter C_MAX_PAYLOAD_BYTES = 256, - parameter C_LOG_NUM_TAGS = 6) - (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP, - output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN, - input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP, - input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN, - - output [7:0] LED, - input PCIE_REFCLK_P, - input PCIE_REFCLK_N, - input PCIE_RESET_N); - - // Clocks, etc - wire user_lnk_up; - wire user_clk; - wire user_reset; - wire pcie_refclk; - wire pcie_refclk_by2; - wire pcie_reset_n; - - // Interface: RQ (TXC) - wire s_axis_rq_tlast; - wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata; - wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep; - wire s_axis_rq_tready; - wire s_axis_rq_tvalid; - // Interface: RC (RXC) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata; - wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser; - wire m_axis_rc_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep; - wire m_axis_rc_tvalid; - wire m_axis_rc_tready; - // Interface: CQ (RXR) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata; - wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser; - wire m_axis_cq_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep; - wire m_axis_cq_tvalid; - wire m_axis_cq_tready; - // Interface: CC (TXC) - wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata; - wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser; - wire s_axis_cc_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep; - wire s_axis_cc_tvalid; - wire s_axis_cc_tready; - - // Configuration (CFG) Interface - wire [3:0] pcie_rq_seq_num; - wire pcie_rq_seq_num_vld; - wire [5:0] pcie_rq_tag; - wire pcie_rq_tag_vld; - wire pcie_cq_np_req; - wire [5:0] pcie_cq_np_req_count; - - wire cfg_phy_link_down; - wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH - wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE - wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD - wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST - wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE - wire [5:0] cfg_function_power_state; // Ignorable but not removable - wire [11:0] cfg_vf_status; // Ignorable but not removable - wire [17:0] cfg_vf_power_state; // Ignorable but not removable - wire [1:0] cfg_link_power_state; // Ignorable but not removable - - // Error Reporting Interface - wire cfg_err_cor_out; - wire cfg_err_nonfatal_out; - wire cfg_err_fatal_out; - - wire cfg_ltr_enable; - wire [5:0] cfg_ltssm_state; - wire [1:0] cfg_rcb_status; - wire [1:0] cfg_dpa_substate_change; - wire [1:0] cfg_obff_enable; - wire cfg_pl_status_change; - - wire [1:0] cfg_tph_requester_enable; - wire [5:0] cfg_tph_st_mode; - wire [5:0] cfg_vf_tph_requester_enable; - wire [17:0] cfg_vf_tph_st_mode; - wire [7:0] cfg_fc_ph; - wire [11:0] cfg_fc_pd; - wire [7:0] cfg_fc_nph; - wire [11:0] cfg_fc_npd; - wire [7:0] cfg_fc_cplh; - wire [11:0] cfg_fc_cpld; - wire [2:0] cfg_fc_sel; - - // Interrupt Interface Signals - wire [3:0] cfg_interrupt_int; - wire [1:0] cfg_interrupt_pending; - wire cfg_interrupt_sent; - wire [1:0] cfg_interrupt_msi_enable; - wire [5:0] cfg_interrupt_msi_vf_enable; - wire [5:0] cfg_interrupt_msi_mmenable; - wire cfg_interrupt_msi_mask_update; - wire [31:0] cfg_interrupt_msi_data; - wire [3:0] cfg_interrupt_msi_select; - wire [31:0] cfg_interrupt_msi_int; - wire [63:0] cfg_interrupt_msi_pending_status; - wire cfg_interrupt_msi_sent; - wire cfg_interrupt_msi_fail; - wire [2:0] cfg_interrupt_msi_attr; - wire cfg_interrupt_msi_tph_present; - wire [1:0] cfg_interrupt_msi_tph_type; - wire [8:0] cfg_interrupt_msi_tph_st_tag; - wire [2:0] cfg_interrupt_msi_function_number; - - wire rst_out; - wire [C_NUM_CHNL-1:0] chnl_rx_clk; - wire [C_NUM_CHNL-1:0] chnl_rx; - wire [C_NUM_CHNL-1:0] chnl_rx_ack; - wire [C_NUM_CHNL-1:0] chnl_rx_last; - wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; - wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data; - wire [C_NUM_CHNL-1:0] chnl_rx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_rx_data_ren; - - wire [C_NUM_CHNL-1:0] chnl_tx_clk; - wire [C_NUM_CHNL-1:0] chnl_tx; - wire [C_NUM_CHNL-1:0] chnl_tx_ack; - wire [C_NUM_CHNL-1:0] chnl_tx_last; - wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; - wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data; - wire [C_NUM_CHNL-1:0] chnl_tx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_tx_data_ren; - - genvar chnl; - - IBUF - #() - pci_reset_n_ibuf - (.O(pcie_reset_n), - .I(PCIE_RESET_N)); - - IBUFDS_GTE3 - #() - refclk_ibuf - (.O(pcie_refclk), - .ODIV2(pcie_refclk_by2), - .I(PCIE_REFCLK_P), - .CEB(1'b0), - .IB(PCIE_REFCLK_N)); - - OBUF - #() - led_0_obuf - (.O(LED[0]), - .I(cfg_ltssm_state[0])); - OBUF - #() - led_1_obuf - (.O(LED[1]), - .I(cfg_ltssm_state[1])); - OBUF - #() - led_2_obuf - (.O(LED[2]), - .I(cfg_ltssm_state[2])); - OBUF - #() - led_3_obuf - (.O(LED[3]), - .I(cfg_ltssm_state[3])); - OBUF - #() - led_4_obuf - (.O(LED[4]), - .I(cfg_ltssm_state[4])); - OBUF - #() - led_5_obuf - (.O(LED[5]), - .I(cfg_ltssm_state[5])); - OBUF - #() - led_6_obuf - (.O(LED[6]), - .I(user_reset)); - OBUF - #() - led_7_obuf - (.O(LED[7]), - .I(rst_out)); - - // Core Top Level Wrapper - PCIeGen2x8If128 - #() - pcie3_7x_0_i - (//--------------------------------------------------------------------- - // PCI Express (pci_exp) Interface - //--------------------------------------------------------------------- - .pci_exp_txn ( PCI_EXP_TXN ), - .pci_exp_txp ( PCI_EXP_TXP ), - .pci_exp_rxn ( PCI_EXP_RXN ), - .pci_exp_rxp ( PCI_EXP_RXP ), - - //--------------------------------------------------------------------- - // AXI Interface - //--------------------------------------------------------------------- - .user_clk ( user_clk ), - .user_reset ( user_reset ), - .user_lnk_up ( user_lnk_up ), - - .s_axis_rq_tlast ( s_axis_rq_tlast ), - .s_axis_rq_tdata ( s_axis_rq_tdata ), - .s_axis_rq_tuser ( s_axis_rq_tuser ), - .s_axis_rq_tkeep ( s_axis_rq_tkeep ), - .s_axis_rq_tready ( s_axis_rq_tready ), - .s_axis_rq_tvalid ( s_axis_rq_tvalid ), - - .m_axis_rc_tdata ( m_axis_rc_tdata ), - .m_axis_rc_tuser ( m_axis_rc_tuser ), - .m_axis_rc_tlast ( m_axis_rc_tlast ), - .m_axis_rc_tkeep ( m_axis_rc_tkeep ), - .m_axis_rc_tvalid ( m_axis_rc_tvalid ), - .m_axis_rc_tready ( {22{m_axis_rc_tready}} ), - - .m_axis_cq_tdata ( m_axis_cq_tdata ), - .m_axis_cq_tuser ( m_axis_cq_tuser ), - .m_axis_cq_tlast ( m_axis_cq_tlast ), - .m_axis_cq_tkeep ( m_axis_cq_tkeep ), - .m_axis_cq_tvalid ( m_axis_cq_tvalid ), - .m_axis_cq_tready ( {22{m_axis_cq_tready}} ), - - .s_axis_cc_tdata ( s_axis_cc_tdata ), - .s_axis_cc_tuser ( s_axis_cc_tuser ), - .s_axis_cc_tlast ( s_axis_cc_tlast ), - .s_axis_cc_tkeep ( s_axis_cc_tkeep ), - .s_axis_cc_tvalid ( s_axis_cc_tvalid ), - .s_axis_cc_tready ( s_axis_cc_tready ), - - //--------------------------------------------------------------------- - // Configuration (CFG) Interface - //--------------------------------------------------------------------- - .pcie_rq_seq_num ( pcie_rq_seq_num ), - .pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ), - .pcie_rq_tag ( pcie_rq_tag ), - .pcie_rq_tag_vld ( pcie_rq_tag_vld ), - .pcie_cq_np_req ( pcie_cq_np_req ), - .pcie_cq_np_req_count ( pcie_cq_np_req_count ), - .cfg_phy_link_down ( cfg_phy_link_down ), - .cfg_phy_link_status ( cfg_phy_link_status), - .cfg_negotiated_width ( cfg_negotiated_width ), - .cfg_current_speed ( cfg_current_speed ), - .cfg_max_payload ( cfg_max_payload ), - .cfg_max_read_req ( cfg_max_read_req ), - .cfg_function_status ( cfg_function_status ), - .cfg_function_power_state ( cfg_function_power_state ), - .cfg_vf_status ( cfg_vf_status ), - .cfg_vf_power_state ( cfg_vf_power_state ), - .cfg_link_power_state ( cfg_link_power_state ), - // Error Reporting Interface - .cfg_err_cor_out ( cfg_err_cor_out ), - .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), - .cfg_err_fatal_out ( cfg_err_fatal_out ), - .cfg_ltr_enable ( cfg_ltr_enable ), - .cfg_ltssm_state ( cfg_ltssm_state ), - .cfg_rcb_status ( cfg_rcb_status ), - .cfg_dpa_substate_change ( cfg_dpa_substate_change ), - .cfg_obff_enable ( cfg_obff_enable ), - .cfg_pl_status_change ( cfg_pl_status_change ), - .cfg_tph_requester_enable ( cfg_tph_requester_enable ), - .cfg_tph_st_mode ( cfg_tph_st_mode ), - .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), - .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), - .cfg_fc_ph ( cfg_fc_ph ), - .cfg_fc_pd ( cfg_fc_pd ), - .cfg_fc_nph ( cfg_fc_nph ), - .cfg_fc_npd ( cfg_fc_npd ), - .cfg_fc_cplh ( cfg_fc_cplh ), - .cfg_fc_cpld ( cfg_fc_cpld ), - .cfg_fc_sel ( cfg_fc_sel ), - //--------------------------------------------------------------------- - // EP Only - //--------------------------------------------------------------------- - // Interrupt Interface Signals - .cfg_interrupt_int ( cfg_interrupt_int ), - .cfg_interrupt_pending ( cfg_interrupt_pending ), - .cfg_interrupt_sent ( cfg_interrupt_sent ), - .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ), - .cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ), - .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), - .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), - .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), - .cfg_interrupt_msi_select ( cfg_interrupt_msi_select ), - .cfg_interrupt_msi_int ( cfg_interrupt_msi_int ), - .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ), - .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), - .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), - .cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ), - .cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ), - .cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ), - .cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ), - .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ), - .cfg_interrupt_msi_pending_status_function_num ( 4'b0), - .cfg_interrupt_msi_pending_status_data_enable ( 1'b0), - - - //--------------------------------------------------------------------------------------// - // Reset Pass Through Signals - // - Only used for PCIe_X0Y0 - //--------------------------------------------------------------------------------------// - .pcie_perstn0_out (), - .pcie_perstn1_in (1'b0), - .pcie_perstn1_out (), - - //--------------------------------------------------------------------- - // System(SYS) Interface - //--------------------------------------------------------------------- - .sys_clk (pcie_refclk_by2), - .sys_clk_gt (pcie_refclk), - .sys_reset (pcie_reset_n)); - - riffa_wrapper_vcu108 - #(/*AUTOINSTPARAM*/ - // Parameters - .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), - .C_NUM_CHNL (C_NUM_CHNL), - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES)) - riffa - (// Outputs - .M_AXIS_CQ_TREADY (m_axis_cq_tready), - .M_AXIS_RC_TREADY (m_axis_rc_tready), - .S_AXIS_CC_TVALID (s_axis_cc_tvalid), - .S_AXIS_CC_TLAST (s_axis_cc_tlast), - .S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]), - .S_AXIS_RQ_TVALID (s_axis_rq_tvalid), - .S_AXIS_RQ_TLAST (s_axis_rq_tlast), - .S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]), - .USER_CLK (user_clk), - .USER_RESET (user_reset), - .CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]), - .CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]), - .CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]), - .CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]), - .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]), - .CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]), - .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present), - .CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]), - .CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]), - .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]), - .CFG_FC_SEL (cfg_fc_sel[2:0]), - .PCIE_CQ_NP_REQ (pcie_cq_np_req), - .RST_OUT (rst_out), - .CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]), - .CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]), - .CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]), - .CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]), - .CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]), - // Inputs - .M_AXIS_CQ_TVALID (m_axis_cq_tvalid), - .M_AXIS_CQ_TLAST (m_axis_cq_tlast), - .M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]), - .M_AXIS_RC_TVALID (m_axis_rc_tvalid), - .M_AXIS_RC_TLAST (m_axis_rc_tlast), - .M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]), - .S_AXIS_CC_TREADY (s_axis_cc_tready), - .S_AXIS_RQ_TREADY (s_axis_rq_tready), - .CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]), - .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update), - .CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]), - .CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent), - .CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail), - .CFG_FC_CPLH (cfg_fc_cplh[7:0]), - .CFG_FC_CPLD (cfg_fc_cpld[11:0]), - .CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]), - .CFG_CURRENT_SPEED (cfg_current_speed[2:0]), - .CFG_MAX_PAYLOAD (cfg_max_payload[2:0]), - .CFG_MAX_READ_REQ (cfg_max_read_req[2:0]), - .CFG_FUNCTION_STATUS (cfg_function_status[7:0]), - .CFG_RCB_STATUS (cfg_rcb_status[1:0]), - .CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]), - .CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]), - .CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]), - .CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]), - .CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]), - .CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]), - .CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])); - - generate - for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels - chnl_tester - #(/*AUTOINSTPARAM*/ - // Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH)) - module1 - (.CLK(user_clk), - .RST(rst_out), // riffa_reset includes riffa_endpoint resets - // Rx interface - .CHNL_RX_CLK(chnl_rx_clk[chnl]), - .CHNL_RX(chnl_rx[chnl]), - .CHNL_RX_ACK(chnl_rx_ack[chnl]), - .CHNL_RX_LAST(chnl_rx_last[chnl]), - .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), - .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), - .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), - .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), - .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]), - // Tx interface - .CHNL_TX_CLK(chnl_tx_clk[chnl]), - .CHNL_TX(chnl_tx[chnl]), - .CHNL_TX_ACK(chnl_tx_ack[chnl]), - .CHNL_TX_LAST(chnl_tx_last[chnl]), - .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), - .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), - .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), - .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), - .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl]) - /*AUTOINST*/); - end - endgenerate -endmodule -// Local Variables: -// verilog-library-directories:("../../../../riffa_hdl/" "../../") -// End: - diff --git a/fpga/xilinx/vcu108/VCU108_Gen2x8If128/ip/PCIeGen2x8If128.xci b/fpga/xilinx/vcu108/VCU108_Gen2x8If128/ip/PCIeGen2x8If128.xci deleted file mode 100644 index 9b2c14a..0000000 --- a/fpga/xilinx/vcu108/VCU108_Gen2x8If128/ip/PCIeGen2x8If128.xci +++ /dev/null @@ -1,730 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - PCIeGen2x8If128 - - - FALSE - FALSE - FALSE - TRUE - 0x00000 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - TRUE - FALSE - TRUE - FALSE - 16KB - 1 - 128 - TRUE - 0 - FALSE - FALSE - FALSE - FALSE - 0x000 - NONE - FALSE - TRUE - FALSE - FALSE - NONE - 3 - 2.0 - FALSE - FALSE - FALSE - 0x000 - 0x000 - 0x00 - 0x03 - 0x4 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x058000 - 0x8028 - FALSE - FALSE - FALSE - FALSE - 0x0 - FALSE - TRUE - FALSE - 0x2 - 0x000 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x000 - 0x00 - FALSE - 0x0 - 0 - TRUE - 0x000 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0xC0 - 0x000 - 0x90 - FALSE - FALSE - FALSE - FALSE - FALSE - 0x000 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x0 - 0x0000 - 0x0000 - 0x00000553 - 0x0000 - 0x0007 - 0x10EE - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0x10EE - FALSE - FALSE - 0x000 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x058000 - 0x8011 - 0x2 - 0x000 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x000 - 0x00 - FALSE - 0x0 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - 0x000 - 0x00 - FALSE - 0x000 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x0 - 0x0000 - 0x0001 - 0x00000553 - 0x0000 - 0x0007 - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 4 - FALSE - 2 - FALSE - 2 - 8 - TRUE - FALSE - 0 - 0 - GTH_Quad_224 - 1 - 0x00000000 - FALSE - 0 - 0x000 - 0x00 - 0x028 - 0x20 - 0x198 - 0x20 - FALSE - FALSE - 0x0 - FALSE - FALSE - 3 - 0x000 - 0x80 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - FALSE - 1 - 0 - 0 - 0 - 0 - 0 - 0 - ES2 - 0 - true - false - PCIeGen2x8If128 - 15 - false - false - 058000 - 8028 - false - false - false - 00_Not_Supported - false - false - NONE - true - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - false - false - false - false - 00 - 0 - N/A - 0000 - 00000553 - 0000 - 0007 - 10EE - false - false - false - 058000 - 8011 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 0 - N/A - 0001 - 00000553 - 0000 - 0007 - false - 4 - 5.0_GT/s - X8 - 100_MHz - Default - 0 - 0 - false - false - 1 - false - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - DWORD_Aligned - No_ASPM - 250 - true - 2FFFF - false - 128_bit - false - false - true - false - true - false - 250 - true - PCI_Express_Endpoint_device - false - false - true - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - None - Advanced - X0Y0 - false - Extreme - false - true - false - false - true - false - Kilobytes - 1 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Simple_communication_controllers - 05 - 00 - 80 - 512_bytes - false - false - false - Kilobytes - 2 - false - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - 0 - Generic_XT_compatible_serial_controller - false - false - true - false - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Simple_communication_controllers - 05 - 00 - 80 - 512_bytes - false - false - false - Kilobytes - 2 - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Generic_XT_compatible_serial_controller - false - false - QPLL1 - false - GTH_Quad_224 - ACTIVE LOW - None - true - false - 10EE - None - virtexu - - xcvu095 - ffva2104 - VERILOG - es2 - MIXED - -2 - E - TRUE - TRUE - IP_Flow - 1 - TRUE - . - - . - 2015.4 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/xilinx/vcu108/VCU108_Gen2x8If128/prj/VCU108_Gen2x8If128.xpr b/fpga/xilinx/vcu108/VCU108_Gen2x8If128/prj/VCU108_Gen2x8If128.xpr deleted file mode 100644 index 2728e15..0000000 --- a/fpga/xilinx/vcu108/VCU108_Gen2x8If128/prj/VCU108_Gen2x8If128.xpr +++ /dev/null @@ -1,810 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/xilinx/vcu108/VCU108_Gen3x4If128/Makefile b/fpga/xilinx/vcu108/VCU108_Gen3x4If128/Makefile deleted file mode 100644 index 5ddddf7..0000000 --- a/fpga/xilinx/vcu108/VCU108_Gen3x4If128/Makefile +++ /dev/null @@ -1,62 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#----------------------------------------------------------------------- -# Filename: Makefile -# Version: 1.0 -# Description: Project-level makefile for building an example project -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------- -# This make file expects the following variables to be set: -# RIFFA_HDL_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory. -# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to -# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory -WIDTH=128 -TYPE=ultrascale -CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))) -PROJECT=$(shell basename $(CURRENT_PATH)) - -ifndef RIFFA_HDL_PATH - RIFFA_HDL_PATH:=../../../riffa_hdl -endif -ifndef BOARD_PATH - BOARD_PATH:=.. -endif -ifndef JOBS - JOBS=1 -endif -include $(RIFFA_HDL_PATH)/riffa.mk -include $(BOARD_PATH)/board.mk - -PROJECT_IP+=ip/PCIeGen3x4If128.xci diff --git a/fpga/xilinx/vcu108/VCU108_Gen3x4If128/bit/VCU108_Gen3x4If128.bit b/fpga/xilinx/vcu108/VCU108_Gen3x4If128/bit/VCU108_Gen3x4If128.bit deleted file mode 100644 index a312791..0000000 Binary files a/fpga/xilinx/vcu108/VCU108_Gen3x4If128/bit/VCU108_Gen3x4If128.bit and /dev/null differ diff --git a/fpga/xilinx/vcu108/VCU108_Gen3x4If128/constr/VCU108_Gen3x4If128.xdc b/fpga/xilinx/vcu108/VCU108_Gen3x4If128/constr/VCU108_Gen3x4If128.xdc deleted file mode 100644 index e478e68..0000000 --- a/fpga/xilinx/vcu108/VCU108_Gen3x4If128/constr/VCU108_Gen3x4If128.xdc +++ /dev/null @@ -1,120 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#---------------------------------------------------------------------------- -# Filename: VCU108_Top.xdc -# Version: 1.00.a -# Verilog Standard: Verilog-2001 -# Description: Xilinx Design Constraints for the VCU108 board. -# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin -# -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------------- -# -######################################################################################################################### -# User Constraints -######################################################################################################################### - -############################################################################### -# User Time Names / User Time Groups / Time Specs -############################################################################### - -############################################################################### -# User Physical Constraints -############################################################################### - -set_property PACKAGE_PIN AT32 [get_ports {LED[0]}] -set_property PACKAGE_PIN AV34 [get_ports {LED[1]}] -set_property PACKAGE_PIN AY30 [get_ports {LED[2]}] -set_property PACKAGE_PIN BB32 [get_ports {LED[3]}] -set_property PACKAGE_PIN BF32 [get_ports {LED[4]}] -set_property PACKAGE_PIN AV36 [get_ports {LED[5]}] -set_property PACKAGE_PIN AY35 [get_ports {LED[6]}] -set_property PACKAGE_PIN BA37 [get_ports {LED[7]}] - -set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[4]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[5]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[6]}] -set_property IOSTANDARD LVCMOS18 [get_ports {LED[7]}] - -set_false_path -to [get_ports -filter NAME=~LED*] - -######################################################################################################################### -# End User Constraints -######################################################################################################################### -# -# -# -######################################################################################################################### -# PCIE Core Constraints -######################################################################################################################### - -# -# SYS reset (input) signal. The sys_reset_n signal should be -# obtained from the PCI Express interface if possible. For -# slot based form factors, a system reset signal is usually -# present on the connector. For cable based form factors, a -# system reset signal may not be available. In this case, the -# system reset signal must be generated locally by some form of -# supervisory circuit. You may change the IOSTANDARD and LOC -# to suit your requirements and VCCO voltage banking rules. -# Some 7 series devices do not have 3.3 V I/Os available. -# Therefore the appropriate level shift is required to operate -# with these devices that contain only 1.8 V banks. -# - -set_property LOC [get_package_pins -filter {PIN_FUNC == IO_T3U_N12_PERSTN0_65}] [get_ports PCIE_RESET_N] -set_property IOSTANDARD LVCMOS15 [get_ports PCIE_RESET_N] -set_property PULLUP true [get_ports PCIE_RESET_N] - -#set_property LOC [get_package_pins -filter {PIN_FUNC == MGTREFCLK0P_225}] [get_ports refclk_ibuf] -set_property LOC AN9 [get_cells refclk_ibuf] - -############################################################################### -# Timing Constraints -############################################################################### -create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O] - -############################################################################### -# Physical Constraints -############################################################################### - -set_false_path -from [get_ports PCIE_RESET_N] -############################################################################### -# End -############################################################################### diff --git a/fpga/xilinx/vcu108/VCU108_Gen3x4If128/hdl/VCU108_Gen3x4If128.v b/fpga/xilinx/vcu108/VCU108_Gen3x4If128/hdl/VCU108_Gen3x4If128.v deleted file mode 100644 index e9de990..0000000 --- a/fpga/xilinx/vcu108/VCU108_Gen3x4If128/hdl/VCU108_Gen3x4If128.v +++ /dev/null @@ -1,491 +0,0 @@ -// ---------------------------------------------------------------------- -// Copyright (c) 2016, The Regents of the University of California All -// rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above -// copyright notice, this list of conditions and the following -// disclaimer in the documentation and/or other materials provided -// with the distribution. -// -// * Neither the name of The Regents of the University of California -// nor the names of its contributors may be used to endorse or -// promote products derived from this software without specific -// prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -// DAMAGE. -// ---------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// Filename: VCU108_Gen3x4If128.v -// Version: 1.00.a -// Verilog Standard: Verilog-2001 -// Description: Top level module for RIFFA 2.2 reference design for the -// the Xilinx VCU108 Development Board. -// Author: Dustin Richmond (@darichmond) -//----------------------------------------------------------------------------- -`include "functions.vh" -`include "riffa.vh" -`include "ultrascale.vh" -`timescale 1ps / 1ps -module VCU108_Gen3x4If128 - #(// Number of RIFFA Channels - parameter C_NUM_CHNL = 1, - // Number of PCIe Lanes - parameter C_NUM_LANES = 4, - // Settings from Vivado IP Generator - parameter C_PCI_DATA_WIDTH = 128, - parameter C_MAX_PAYLOAD_BYTES = 256, - parameter C_LOG_NUM_TAGS = 6) - (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP, - output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN, - input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP, - input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN, - - output [7:0] LED, - input PCIE_REFCLK_P, - input PCIE_REFCLK_N, - input PCIE_RESET_N); - - // Clocks, etc - wire user_lnk_up; - wire user_clk; - wire user_reset; - wire pcie_refclk; - wire pcie_refclk_by2; - wire pcie_reset_n; - - // Interface: RQ (TXC) - wire s_axis_rq_tlast; - wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata; - wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep; - wire s_axis_rq_tready; - wire s_axis_rq_tvalid; - // Interface: RC (RXC) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata; - wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser; - wire m_axis_rc_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep; - wire m_axis_rc_tvalid; - wire m_axis_rc_tready; - // Interface: CQ (RXR) - wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata; - wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser; - wire m_axis_cq_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep; - wire m_axis_cq_tvalid; - wire m_axis_cq_tready; - // Interface: CC (TXC) - wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata; - wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser; - wire s_axis_cc_tlast; - wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep; - wire s_axis_cc_tvalid; - wire s_axis_cc_tready; - - // Configuration (CFG) Interface - wire [3:0] pcie_rq_seq_num; - wire pcie_rq_seq_num_vld; - wire [5:0] pcie_rq_tag; - wire pcie_rq_tag_vld; - wire pcie_cq_np_req; - wire [5:0] pcie_cq_np_req_count; - - wire cfg_phy_link_down; - wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH - wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE - wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD - wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST - wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE - wire [5:0] cfg_function_power_state; // Ignorable but not removable - wire [11:0] cfg_vf_status; // Ignorable but not removable - wire [17:0] cfg_vf_power_state; // Ignorable but not removable - wire [1:0] cfg_link_power_state; // Ignorable but not removable - - // Error Reporting Interface - wire cfg_err_cor_out; - wire cfg_err_nonfatal_out; - wire cfg_err_fatal_out; - - wire cfg_ltr_enable; - wire [5:0] cfg_ltssm_state; - wire [1:0] cfg_rcb_status; - wire [1:0] cfg_dpa_substate_change; - wire [1:0] cfg_obff_enable; - wire cfg_pl_status_change; - - wire [1:0] cfg_tph_requester_enable; - wire [5:0] cfg_tph_st_mode; - wire [5:0] cfg_vf_tph_requester_enable; - wire [17:0] cfg_vf_tph_st_mode; - wire [7:0] cfg_fc_ph; - wire [11:0] cfg_fc_pd; - wire [7:0] cfg_fc_nph; - wire [11:0] cfg_fc_npd; - wire [7:0] cfg_fc_cplh; - wire [11:0] cfg_fc_cpld; - wire [2:0] cfg_fc_sel; - - // Interrupt Interface Signals - wire [3:0] cfg_interrupt_int; - wire [1:0] cfg_interrupt_pending; - wire cfg_interrupt_sent; - wire [1:0] cfg_interrupt_msi_enable; - wire [5:0] cfg_interrupt_msi_vf_enable; - wire [5:0] cfg_interrupt_msi_mmenable; - wire cfg_interrupt_msi_mask_update; - wire [31:0] cfg_interrupt_msi_data; - wire [3:0] cfg_interrupt_msi_select; - wire [31:0] cfg_interrupt_msi_int; - wire [63:0] cfg_interrupt_msi_pending_status; - wire cfg_interrupt_msi_sent; - wire cfg_interrupt_msi_fail; - wire [2:0] cfg_interrupt_msi_attr; - wire cfg_interrupt_msi_tph_present; - wire [1:0] cfg_interrupt_msi_tph_type; - wire [8:0] cfg_interrupt_msi_tph_st_tag; - wire [2:0] cfg_interrupt_msi_function_number; - - wire rst_out; - wire [C_NUM_CHNL-1:0] chnl_rx_clk; - wire [C_NUM_CHNL-1:0] chnl_rx; - wire [C_NUM_CHNL-1:0] chnl_rx_ack; - wire [C_NUM_CHNL-1:0] chnl_rx_last; - wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; - wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data; - wire [C_NUM_CHNL-1:0] chnl_rx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_rx_data_ren; - - wire [C_NUM_CHNL-1:0] chnl_tx_clk; - wire [C_NUM_CHNL-1:0] chnl_tx; - wire [C_NUM_CHNL-1:0] chnl_tx_ack; - wire [C_NUM_CHNL-1:0] chnl_tx_last; - wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; - wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; - wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data; - wire [C_NUM_CHNL-1:0] chnl_tx_data_valid; - wire [C_NUM_CHNL-1:0] chnl_tx_data_ren; - - genvar chnl; - - IBUF - #() - pci_reset_n_ibuf - (.O(pcie_reset_n), - .I(PCIE_RESET_N)); - - IBUFDS_GTE3 - #() - refclk_ibuf - (.O(pcie_refclk), - .ODIV2(pcie_refclk_by2), - .I(PCIE_REFCLK_P), - .CEB(1'b0), - .IB(PCIE_REFCLK_N)); - - OBUF - #() - led_0_obuf - (.O(LED[0]), - .I(cfg_ltssm_state[0])); - OBUF - #() - led_1_obuf - (.O(LED[1]), - .I(cfg_ltssm_state[1])); - OBUF - #() - led_2_obuf - (.O(LED[2]), - .I(cfg_ltssm_state[2])); - OBUF - #() - led_3_obuf - (.O(LED[3]), - .I(cfg_ltssm_state[3])); - OBUF - #() - led_4_obuf - (.O(LED[4]), - .I(cfg_ltssm_state[4])); - OBUF - #() - led_5_obuf - (.O(LED[5]), - .I(cfg_ltssm_state[5])); - OBUF - #() - led_6_obuf - (.O(LED[6]), - .I(user_reset)); - OBUF - #() - led_7_obuf - (.O(LED[7]), - .I(rst_out)); - - // Core Top Level Wrapper - PCIeGen3x4If128 - #() - pcie3_7x_0_i - (//--------------------------------------------------------------------- - // PCI Express (pci_exp) Interface - //--------------------------------------------------------------------- - .pci_exp_txn ( PCI_EXP_TXN ), - .pci_exp_txp ( PCI_EXP_TXP ), - .pci_exp_rxn ( PCI_EXP_RXN ), - .pci_exp_rxp ( PCI_EXP_RXP ), - - //--------------------------------------------------------------------- - // AXI Interface - //--------------------------------------------------------------------- - .user_clk ( user_clk ), - .user_reset ( user_reset ), - .user_lnk_up ( user_lnk_up ), - - .s_axis_rq_tlast ( s_axis_rq_tlast ), - .s_axis_rq_tdata ( s_axis_rq_tdata ), - .s_axis_rq_tuser ( s_axis_rq_tuser ), - .s_axis_rq_tkeep ( s_axis_rq_tkeep ), - .s_axis_rq_tready ( s_axis_rq_tready ), - .s_axis_rq_tvalid ( s_axis_rq_tvalid ), - - .m_axis_rc_tdata ( m_axis_rc_tdata ), - .m_axis_rc_tuser ( m_axis_rc_tuser ), - .m_axis_rc_tlast ( m_axis_rc_tlast ), - .m_axis_rc_tkeep ( m_axis_rc_tkeep ), - .m_axis_rc_tvalid ( m_axis_rc_tvalid ), - .m_axis_rc_tready ( {22{m_axis_rc_tready}} ), - - .m_axis_cq_tdata ( m_axis_cq_tdata ), - .m_axis_cq_tuser ( m_axis_cq_tuser ), - .m_axis_cq_tlast ( m_axis_cq_tlast ), - .m_axis_cq_tkeep ( m_axis_cq_tkeep ), - .m_axis_cq_tvalid ( m_axis_cq_tvalid ), - .m_axis_cq_tready ( {22{m_axis_cq_tready}} ), - - .s_axis_cc_tdata ( s_axis_cc_tdata ), - .s_axis_cc_tuser ( s_axis_cc_tuser ), - .s_axis_cc_tlast ( s_axis_cc_tlast ), - .s_axis_cc_tkeep ( s_axis_cc_tkeep ), - .s_axis_cc_tvalid ( s_axis_cc_tvalid ), - .s_axis_cc_tready ( s_axis_cc_tready ), - - //--------------------------------------------------------------------- - // Configuration (CFG) Interface - //--------------------------------------------------------------------- - .pcie_rq_seq_num ( pcie_rq_seq_num ), - .pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ), - .pcie_rq_tag ( pcie_rq_tag ), - .pcie_rq_tag_vld ( pcie_rq_tag_vld ), - .pcie_cq_np_req ( pcie_cq_np_req ), - .pcie_cq_np_req_count ( pcie_cq_np_req_count ), - .cfg_phy_link_down ( cfg_phy_link_down ), - .cfg_phy_link_status ( cfg_phy_link_status), - .cfg_negotiated_width ( cfg_negotiated_width ), - .cfg_current_speed ( cfg_current_speed ), - .cfg_max_payload ( cfg_max_payload ), - .cfg_max_read_req ( cfg_max_read_req ), - .cfg_function_status ( cfg_function_status ), - .cfg_function_power_state ( cfg_function_power_state ), - .cfg_vf_status ( cfg_vf_status ), - .cfg_vf_power_state ( cfg_vf_power_state ), - .cfg_link_power_state ( cfg_link_power_state ), - // Error Reporting Interface - .cfg_err_cor_out ( cfg_err_cor_out ), - .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), - .cfg_err_fatal_out ( cfg_err_fatal_out ), - .cfg_ltr_enable ( cfg_ltr_enable ), - .cfg_ltssm_state ( cfg_ltssm_state ), - .cfg_rcb_status ( cfg_rcb_status ), - .cfg_dpa_substate_change ( cfg_dpa_substate_change ), - .cfg_obff_enable ( cfg_obff_enable ), - .cfg_pl_status_change ( cfg_pl_status_change ), - .cfg_tph_requester_enable ( cfg_tph_requester_enable ), - .cfg_tph_st_mode ( cfg_tph_st_mode ), - .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), - .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), - .cfg_fc_ph ( cfg_fc_ph ), - .cfg_fc_pd ( cfg_fc_pd ), - .cfg_fc_nph ( cfg_fc_nph ), - .cfg_fc_npd ( cfg_fc_npd ), - .cfg_fc_cplh ( cfg_fc_cplh ), - .cfg_fc_cpld ( cfg_fc_cpld ), - .cfg_fc_sel ( cfg_fc_sel ), - //--------------------------------------------------------------------- - // EP Only - //--------------------------------------------------------------------- - // Interrupt Interface Signals - .cfg_interrupt_int ( cfg_interrupt_int ), - .cfg_interrupt_pending ( cfg_interrupt_pending ), - .cfg_interrupt_sent ( cfg_interrupt_sent ), - .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ), - .cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ), - .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), - .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), - .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), - .cfg_interrupt_msi_select ( cfg_interrupt_msi_select ), - .cfg_interrupt_msi_int ( cfg_interrupt_msi_int ), - .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ), - .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), - .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), - .cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ), - .cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ), - .cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ), - .cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ), - .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ), - .cfg_interrupt_msi_pending_status_function_num ( 4'b0), - .cfg_interrupt_msi_pending_status_data_enable ( 1'b0), - - - //--------------------------------------------------------------------------------------// - // Reset Pass Through Signals - // - Only used for PCIe_X0Y0 - //--------------------------------------------------------------------------------------// - .pcie_perstn0_out (), - .pcie_perstn1_in (1'b0), - .pcie_perstn1_out (), - - //--------------------------------------------------------------------- - // System(SYS) Interface - //--------------------------------------------------------------------- - .sys_clk (pcie_refclk_by2), - .sys_clk_gt (pcie_refclk), - .sys_reset (pcie_reset_n)); - - riffa_wrapper_vcu108 - #(/*AUTOINSTPARAM*/ - // Parameters - .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), - .C_NUM_CHNL (C_NUM_CHNL), - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES)) - riffa - (// Outputs - .M_AXIS_CQ_TREADY (m_axis_cq_tready), - .M_AXIS_RC_TREADY (m_axis_rc_tready), - .S_AXIS_CC_TVALID (s_axis_cc_tvalid), - .S_AXIS_CC_TLAST (s_axis_cc_tlast), - .S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]), - .S_AXIS_RQ_TVALID (s_axis_rq_tvalid), - .S_AXIS_RQ_TLAST (s_axis_rq_tlast), - .S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]), - .USER_CLK (user_clk), - .USER_RESET (user_reset), - .CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]), - .CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]), - .CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]), - .CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]), - .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]), - .CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]), - .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present), - .CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]), - .CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]), - .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]), - .CFG_FC_SEL (cfg_fc_sel[2:0]), - .PCIE_CQ_NP_REQ (pcie_cq_np_req), - .RST_OUT (rst_out), - .CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]), - .CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]), - .CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]), - .CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]), - .CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]), - // Inputs - .M_AXIS_CQ_TVALID (m_axis_cq_tvalid), - .M_AXIS_CQ_TLAST (m_axis_cq_tlast), - .M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]), - .M_AXIS_RC_TVALID (m_axis_rc_tvalid), - .M_AXIS_RC_TLAST (m_axis_rc_tlast), - .M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]), - .S_AXIS_CC_TREADY (s_axis_cc_tready), - .S_AXIS_RQ_TREADY (s_axis_rq_tready), - .CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]), - .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update), - .CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]), - .CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent), - .CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail), - .CFG_FC_CPLH (cfg_fc_cplh[7:0]), - .CFG_FC_CPLD (cfg_fc_cpld[11:0]), - .CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]), - .CFG_CURRENT_SPEED (cfg_current_speed[2:0]), - .CFG_MAX_PAYLOAD (cfg_max_payload[2:0]), - .CFG_MAX_READ_REQ (cfg_max_read_req[2:0]), - .CFG_FUNCTION_STATUS (cfg_function_status[7:0]), - .CFG_RCB_STATUS (cfg_rcb_status[1:0]), - .CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]), - .CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]), - .CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]), - .CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]), - .CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]), - .CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]), - .CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]), - .CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]), - .CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])); - - generate - for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels - chnl_tester - #(/*AUTOINSTPARAM*/ - // Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH)) - module1 - (.CLK(user_clk), - .RST(rst_out), // riffa_reset includes riffa_endpoint resets - // Rx interface - .CHNL_RX_CLK(chnl_rx_clk[chnl]), - .CHNL_RX(chnl_rx[chnl]), - .CHNL_RX_ACK(chnl_rx_ack[chnl]), - .CHNL_RX_LAST(chnl_rx_last[chnl]), - .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), - .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), - .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), - .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), - .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]), - // Tx interface - .CHNL_TX_CLK(chnl_tx_clk[chnl]), - .CHNL_TX(chnl_tx[chnl]), - .CHNL_TX_ACK(chnl_tx_ack[chnl]), - .CHNL_TX_LAST(chnl_tx_last[chnl]), - .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), - .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), - .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), - .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), - .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl]) - /*AUTOINST*/); - end - endgenerate -endmodule -// Local Variables: -// verilog-library-directories:("../../../../riffa_hdl/" "../../") -// End: - diff --git a/fpga/xilinx/vcu108/VCU108_Gen3x4If128/ip/PCIeGen3x4If128.xci b/fpga/xilinx/vcu108/VCU108_Gen3x4If128/ip/PCIeGen3x4If128.xci deleted file mode 100644 index 6a1d41b..0000000 --- a/fpga/xilinx/vcu108/VCU108_Gen3x4If128/ip/PCIeGen3x4If128.xci +++ /dev/null @@ -1,730 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - PCIeGen3x4If128 - - - FALSE - FALSE - FALSE - TRUE - 0x00000 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - TRUE - FALSE - TRUE - FALSE - 16KB - 1 - 128 - TRUE - 0 - FALSE - FALSE - FALSE - FALSE - 0x000 - NONE - FALSE - TRUE - FALSE - FALSE - NONE - 3 - 2.0 - FALSE - FALSE - FALSE - 0x300 - 0x000 - 0x00 - 0x03 - 0x4 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x058000 - 0x8034 - FALSE - FALSE - FALSE - FALSE - 0x0 - FALSE - TRUE - FALSE - 0x2 - 0x300 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x300 - 0x00 - FALSE - 0x0 - 0 - TRUE - 0x300 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0xC0 - 0x274 - 0x90 - FALSE - FALSE - FALSE - FALSE - FALSE - 0x300 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x300 - 0x0000 - 0x0 - 0x0000 - 0x0000 - 0x00000553 - 0x0000 - 0x0007 - 0x10EE - TRUE - FALSE - FALSE - 0x300 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0x10EE - FALSE - FALSE - 0x000 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x058000 - 0x8011 - 0x2 - 0x000 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x000 - 0x00 - FALSE - 0x0 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - 0x000 - 0x00 - FALSE - 0x000 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x0 - 0x0000 - 0x0001 - 0x00000553 - 0x0000 - 0x0007 - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 4 - FALSE - 2 - FALSE - 4 - 4 - TRUE - FALSE - 0 - 0 - GTH_Quad_224 - 1 - 0x00000000 - FALSE - 0 - 0x000 - 0x00 - 0x028 - 0x20 - 0x198 - 0x20 - FALSE - FALSE - 0x0 - FALSE - FALSE - 3 - 0x000 - 0x80 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - FALSE - 1 - 0 - 0 - 0 - 0 - 0 - 0 - ES2 - 0 - true - false - PCIeGen3x4If128 - 15 - false - false - 058000 - 8034 - false - false - false - 00_Not_Supported - false - false - NONE - true - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - false - false - false - false - 00 - 0 - N/A - 0000 - 00000553 - 0000 - 0007 - 10EE - false - false - false - 058000 - 8011 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 0 - N/A - 0001 - 00000553 - 0000 - 0007 - false - 4 - 8.0_GT/s - X4 - 100_MHz - Default - 0 - 0 - false - false - 1 - false - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - DWORD_Aligned - No_ASPM - 250 - true - 2FFFF - false - 128_bit - false - false - true - false - true - false - 250 - true - PCI_Express_Endpoint_device - false - false - true - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - None - Advanced - X0Y0 - false - Extreme - false - true - false - false - true - false - Kilobytes - 1 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Simple_communication_controllers - 05 - 00 - 80 - 512_bytes - false - false - false - Kilobytes - 2 - false - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - 0 - Generic_XT_compatible_serial_controller - false - false - true - false - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Simple_communication_controllers - 05 - 00 - 80 - 512_bytes - false - false - false - Kilobytes - 2 - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Generic_XT_compatible_serial_controller - false - false - QPLL1 - false - GTH_Quad_224 - ACTIVE LOW - None - true - false - 10EE - None - virtexu - - xcvu095 - ffva2104 - VERILOG - es2 - MIXED - -2 - E - TRUE - TRUE - IP_Flow - 1 - TRUE - . - - . - 2015.4 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/xilinx/vcu108/VCU108_Gen3x4If128/prj/VCU108_Gen3x4If128.xpr b/fpga/xilinx/vcu108/VCU108_Gen3x4If128/prj/VCU108_Gen3x4If128.xpr deleted file mode 100644 index a7104d1..0000000 --- a/fpga/xilinx/vcu108/VCU108_Gen3x4If128/prj/VCU108_Gen3x4If128.xpr +++ /dev/null @@ -1,810 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/xilinx/vcu108/board.mk b/fpga/xilinx/vcu108/board.mk deleted file mode 100644 index 0d6b7bf..0000000 --- a/fpga/xilinx/vcu108/board.mk +++ /dev/null @@ -1,103 +0,0 @@ -# ---------------------------------------------------------------------- -# Copyright (c) 2016, The Regents of the University of California All -# rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# -# * Neither the name of The Regents of the University of California -# nor the names of its contributors may be used to endorse or -# promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -# DAMAGE. -# ---------------------------------------------------------------------- -#----------------------------------------------------------------------- -# Filename: board.mk -# Version: 1.0 -# Description: Board-specific include makefile -# Author: Dustin Richmond (@darichmond) -#----------------------------------------------------------------------- -include $(RIFFA_ROOT_PATH)/release.mk -.DEFAULT_GOAL=all - -BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v - -PROJECT_IP= -PROJECT_BIT:= bit/$(PROJECT).bit -PROJECT_HDL=hdl/$(PROJECT).v $(BOARD_HDL) $(patsubst %, $(RIFFA_HDL_PATH)/%,$(RIFFA_HDL)) -PROJECT_CONSTR=constr/$(PROJECT).xdc -PROJECT_FILE=prj/$(PROJECT).xpr -PROJECT_FILES=$(PROJECT_IP) $(PROJECT_CONSTR) $(PROJECT_QSRCS) $(PROJECT_HDL) - -RELEASE_BIT:=$(PROJECT_BIT) -RELEASE_IP=$(PROJECT_IP) # Note the difference between this and the other assignments (Projects add their own IP) -RELEASE_HDL:=hdl/$(PROJECT).v -RELEASE_CONSTR:=$(PROJECT_CONSTR) -RELEASE_FILE:=$(PROJECT_FILE) -RELEASE_PROJECT_PATH:=$(RELEASE_SRC_PATH)/fpga/$(VENDOR)/$(BOARD)/$(PROJECT) -copy-files = $(foreach file, $1, cp $(file) $2;) - -.PHONY:$(PROJECT) all synthesis implementation clean clobber $(TYPE) $(VENDOR) $(BOARD) -$(PROJECT): $(PROJECT_BIT) - @echo Compiling Project $@ - -$(PROJECT_BIT): $(PROJECT_FILES) - echo "launch_runs impl_1 -to_step write_bitstream -jobs $(JOBS); wait_on_run impl_1" | vivado -mode tcl prj/$(PROJECT).xpr - mv prj/$(PROJECT).runs/impl_1/$(PROJECT).bit bit/ - -synthesis: prj/$(PROJECT).runs/synth_1 -prj/$(PROJECT).runs/synth_1: $(PROJECT_FILES) - echo "launch_runs synth_1 -jobs $(JOBS); wait_on_run synth_1" | vivado -mode tcl prj/$(PROJECT).xpr - -implementation:prj/$(PROJECT).runs/impl_1 -prj/$(PROJECT).runs/impl_1: $(PROJECT_FILES) - echo "launch_runs impl_1 -jobs $(JOBS); wait_on_run impl1" | vivado -mode tcl prj/$(PROJECT).xpr - -all $(TYPE) $(VENDOR) $(BOARD):$(PROJECT) -clean: - echo "reset_run impl_1; reset_run synth_1;" | vivado -mode tcl prj/$(PROJECT).xpr - rm -rf *.log *.jou *~ .Xil - rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~ - rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~ - -clobber: - rm -rf $(PROJECT_BIT) - -destination: $(RELEASE_PROJECT_PATH) - mkdir $(RELEASE_PROJECT_PATH)/bit - mkdir $(RELEASE_PROJECT_PATH)/constr - mkdir $(RELEASE_PROJECT_PATH)/ip - mkdir $(RELEASE_PROJECT_PATH)/hdl - mkdir $(RELEASE_PROJECT_PATH)/prj - -$(RELEASE_PROJECT_PATH): check-release-src - mkdir $@ - -release:check-release-src destination - $(call copy-files, $(RELEASE_BIT), $(RELEASE_PROJECT_PATH)/bit) - $(call copy-files, $(RELEASE_CONSTR), $(RELEASE_PROJECT_PATH)/constr) - $(call copy-files, $(RELEASE_IP), $(RELEASE_PROJECT_PATH)/ip) - $(call copy-files, $(RELEASE_HDL), $(RELEASE_PROJECT_PATH)/hdl) - $(call copy-files, $(RELEASE_FILE), $(RELEASE_PROJECT_PATH)/prj) - diff --git a/fpga/xilinx/vcu108/riffa_wrapper_vcu108.v b/fpga/xilinx/vcu108/riffa_wrapper_vcu108.v deleted file mode 100644 index 5d92ada..0000000 --- a/fpga/xilinx/vcu108/riffa_wrapper_vcu108.v +++ /dev/null @@ -1,592 +0,0 @@ -// ---------------------------------------------------------------------- -// Copyright (c) 2016, The Regents of the University of California All -// rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above -// copyright notice, this list of conditions and the following -// disclaimer in the documentation and/or other materials provided -// with the distribution. -// -// * Neither the name of The Regents of the University of California -// nor the names of its contributors may be used to endorse or -// promote products derived from this software without specific -// prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -// DAMAGE. -// ---------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// Filename: riffa_wrapper_vc709.v -// Version: 1.00.a -// Verilog Standard: Verilog-2001 -// Description: RIFFA wrapper for the VCU108 Development board. -// Author: Dustin Richmond (@darichmond) -//----------------------------------------------------------------------------- -`include "trellis.vh" -`include "riffa.vh" -`include "ultrascale.vh" -`include "functions.vh" -`timescale 1ps / 1ps -module riffa_wrapper_vcu108 - #(// Number of RIFFA Channels - parameter C_NUM_CHNL = 1, - // Bit-Width from Vivado IP Generator - parameter C_PCI_DATA_WIDTH = 128, - // 4-Byte Name for this FPGA - parameter C_MAX_PAYLOAD_BYTES = 256, - parameter C_LOG_NUM_TAGS = 5, - parameter C_FPGA_ID = "7V30") - (//Interface: CQ Ultrascale (RXR) - input M_AXIS_CQ_TVALID, - input M_AXIS_CQ_TLAST, - input [C_PCI_DATA_WIDTH-1:0] M_AXIS_CQ_TDATA, - input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_CQ_TKEEP, - input [`SIG_CQ_TUSER_W-1:0] M_AXIS_CQ_TUSER, - output M_AXIS_CQ_TREADY, - - //Interface: RC Ultrascale (RXC) - input M_AXIS_RC_TVALID, - input M_AXIS_RC_TLAST, - input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RC_TDATA, - input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_RC_TKEEP, - input [`SIG_RC_TUSER_W-1:0] M_AXIS_RC_TUSER, - output M_AXIS_RC_TREADY, - - //Interface: CC Ultrascale (TXC) - input S_AXIS_CC_TREADY, - output S_AXIS_CC_TVALID, - output S_AXIS_CC_TLAST, - output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA, - output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP, - output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER, - - //Interface: RQ Ultrascale (TXR) - input S_AXIS_RQ_TREADY, - output S_AXIS_RQ_TVALID, - output S_AXIS_RQ_TLAST, - output [C_PCI_DATA_WIDTH-1:0] S_AXIS_RQ_TDATA, - output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_RQ_TKEEP, - output [`SIG_RQ_TUSER_W-1:0] S_AXIS_RQ_TUSER, - - input USER_CLK, - input USER_RESET, - - output [3:0] CFG_INTERRUPT_INT, - output [1:0] CFG_INTERRUPT_PENDING, - input [1:0] CFG_INTERRUPT_MSI_ENABLE, - input CFG_INTERRUPT_MSI_MASK_UPDATE, - input [31:0] CFG_INTERRUPT_MSI_DATA, - output [3:0] CFG_INTERRUPT_MSI_SELECT, - output [31:0] CFG_INTERRUPT_MSI_INT, - output [63:0] CFG_INTERRUPT_MSI_PENDING_STATUS, - input CFG_INTERRUPT_MSI_SENT, - input CFG_INTERRUPT_MSI_FAIL, - output [2:0] CFG_INTERRUPT_MSI_ATTR, - output CFG_INTERRUPT_MSI_TPH_PRESENT, - output [1:0] CFG_INTERRUPT_MSI_TPH_TYPE, - output [8:0] CFG_INTERRUPT_MSI_TPH_ST_TAG, - output [2:0] CFG_INTERRUPT_MSI_FUNCTION_NUMBER, - - input [7:0] CFG_FC_CPLH, - input [11:0] CFG_FC_CPLD, - output [2:0] CFG_FC_SEL, - - input [3:0] CFG_NEGOTIATED_WIDTH, // CONFIG_LINK_WIDTH - input [2:0] CFG_CURRENT_SPEED, // CONFIG_LINK_RATE - input [2:0] CFG_MAX_PAYLOAD, // CONFIG_MAX_PAYLOAD - input [2:0] CFG_MAX_READ_REQ, // CONFIG_MAX_READ_REQUEST - input [7:0] CFG_FUNCTION_STATUS, // [2] = CONFIG_BUS_MASTER_ENABLE - input [1:0] CFG_RCB_STATUS, - - output PCIE_CQ_NP_REQ, - - // RIFFA Interface Signals - output RST_OUT, - input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock - output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal - input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal - output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read - output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length - output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset - output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data - output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid - input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved - - input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock - input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal - output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal - input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write - input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words) - input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset - input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data - input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid - output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved - - localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver - localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2; - // ALTERA, XILINX or ULTRASCALE - localparam C_VENDOR = "ULTRASCALE"; - - localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32; - localparam C_PIPELINE_OUTPUT = 1; - localparam C_PIPELINE_INPUT = 1; - localparam C_DEPTH_PACKETS = 4; - - wire clk; - wire rst_in; - wire done_txc_rst; - wire done_txr_rst; - wire done_rxr_rst; - wire done_rxc_rst; - // Interface: RXC Engine - wire [C_PCI_DATA_WIDTH-1:0] rxc_data; - wire rxc_data_valid; - wire rxc_data_start_flag; - wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset; - wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe; - wire rxc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset; - wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe; - wire [`SIG_TAG_W-1:0] rxc_meta_tag; - wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr; - wire [`SIG_TYPE_W-1:0] rxc_meta_type; - wire [`SIG_LEN_W-1:0] rxc_meta_length; - wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining; - wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id; - wire rxc_meta_ep; - - // Interface: RXR Engine - wire [C_PCI_DATA_WIDTH-1:0] rxr_data; - wire rxr_data_valid; - wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable; - wire rxr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset; - wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe; - wire rxr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset; - wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe; - wire [`SIG_TC_W-1:0] rxr_meta_tc; - wire [`SIG_ATTR_W-1:0] rxr_meta_attr; - wire [`SIG_TAG_W-1:0] rxr_meta_tag; - wire [`SIG_TYPE_W-1:0] rxr_meta_type; - wire [`SIG_ADDR_W-1:0] rxr_meta_addr; - wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded; - wire [`SIG_REQID_W-1:0] rxr_meta_requester_id; - wire [`SIG_LEN_W-1:0] rxr_meta_length; - wire rxr_meta_ep; - - // interface: TXC Engine - wire txc_data_valid; - wire [C_PCI_DATA_WIDTH-1:0] txc_data; - wire txc_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset; - wire txc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset; - wire txc_data_ready; - - wire txc_meta_valid; - wire [`SIG_FBE_W-1:0] txc_meta_fdwbe; - wire [`SIG_LBE_W-1:0] txc_meta_ldwbe; - wire [`SIG_LOWADDR_W-1:0] txc_meta_addr; - wire [`SIG_TYPE_W-1:0] txc_meta_type; - wire [`SIG_LEN_W-1:0] txc_meta_length; - wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count; - wire [`SIG_TAG_W-1:0] txc_meta_tag; - wire [`SIG_REQID_W-1:0] txc_meta_requester_id; - wire [`SIG_TC_W-1:0] txc_meta_tc; - wire [`SIG_ATTR_W-1:0] txc_meta_attr; - wire txc_meta_ep; - wire txc_meta_ready; - wire txc_sent; - - // Interface: TXR Engine - wire txr_data_valid; - wire [C_PCI_DATA_WIDTH-1:0] txr_data; - wire txr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset; - wire txr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset; - wire txr_data_ready; - - wire txr_meta_valid; - wire [`SIG_FBE_W-1:0] txr_meta_fdwbe; - wire [`SIG_LBE_W-1:0] txr_meta_ldwbe; - wire [`SIG_ADDR_W-1:0] txr_meta_addr; - wire [`SIG_LEN_W-1:0] txr_meta_length; - wire [`SIG_TAG_W-1:0] txr_meta_tag; - wire [`SIG_TC_W-1:0] txr_meta_tc; - wire [`SIG_ATTR_W-1:0] txr_meta_attr; - wire [`SIG_TYPE_W-1:0] txr_meta_type; - wire txr_meta_ep; - wire txr_meta_ready; - wire txr_sent; - - // Unconnected Wires (Used in classic interface) - wire wRxTlpReady_nc; - wire [C_PCI_DATA_WIDTH-1:0] wRxTlp_nc = 0; - wire wRxTlpEndFlag_nc = 0; - wire [`SIG_OFFSET_W-1:0] wRxTlpEndOffset_nc = 0; - wire wRxTlpStartFlag_nc = 0; - wire [`SIG_OFFSET_W-1:0] wRxTlpStartOffset_nc = 0; - wire wRxTlpValid_nc = 0; - wire [`SIG_BARDECODE_W-1:0] wRxTlpBarDecode_nc = 0; - - wire wTxTlpReady_nc = 0; - wire [C_PCI_DATA_WIDTH-1:0] wTxTlp_nc; - wire wTxTlpEndFlag_nc; - wire [`SIG_OFFSET_W-1:0] wTxTlpEndOffset_nc; - wire wTxTlpStartFlag_nc; - wire [`SIG_OFFSET_W-1:0] wTxTlpStartOffset_nc; - wire wTxTlpValid_nc; - - //-------------------------------------------------------------------------- - - // Interface: Configuration - wire config_bus_master_enable; - wire [`SIG_CPLID_W-1:0] config_completer_id; - wire config_cpl_boundary_sel; - wire config_interrupt_msienable; - wire [`SIG_LINKRATE_W-1:0] config_link_rate; - wire [`SIG_LINKWIDTH_W-1:0] config_link_width; - wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size; - wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size; - wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data; - wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr; - - wire intr_msi_request; - wire intr_msi_rdy; - - genvar chnl; - - assign clk = USER_CLK; - assign rst_in = USER_RESET; - - assign config_completer_id = 0; // Not used in ULTRASCALE implementation - assign config_bus_master_enable = CFG_FUNCTION_STATUS[2]; - assign config_link_width = {2'b00,CFG_NEGOTIATED_WIDTH}; // CONFIG_LINK_WIDTH - assign config_link_rate = CFG_CURRENT_SPEED[2]? 2'b11 : CFG_CURRENT_SPEED[2] ? 2'b10 : 2'b01; - assign config_max_payload_size = CFG_MAX_PAYLOAD; // CONFIG_MAX_PAYLOAD - assign config_max_read_request_size = CFG_MAX_READ_REQ; // CONFIG_MAX_READ_REQUEST - assign config_cpl_boundary_sel = CFG_RCB_STATUS[0]; - assign config_interrupt_msienable = CFG_INTERRUPT_MSI_ENABLE[0]; - assign config_max_cpl_data = CFG_FC_CPLD; - assign config_max_cpl_hdr = CFG_FC_CPLH; - - assign CFG_FC_SEL = 3'b001; // Always display credit maximum for the signals below - assign CFG_INTERRUPT_MSI_INT = {31'b0,intr_msi_request}; - assign CFG_INTERRUPT_MSI_SELECT = 0; - assign CFG_INTERRUPT_INT = 0; - assign CFG_INTERRUPT_PENDING = 0; - assign CFG_INTERRUPT_MSI_SELECT = 0; - assign CFG_INTERRUPT_MSI_PENDING_STATUS = {63'b0,intr_msi_request}; - assign CFG_INTERRUPT_MSI_ATTR = 0; - assign CFG_INTERRUPT_MSI_TPH_PRESENT = 0; - assign CFG_INTERRUPT_MSI_TPH_ST_TAG = 0; - assign CFG_INTERRUPT_MSI_TPH_TYPE = 0; - assign CFG_INTERRUPT_MSI_FUNCTION_NUMBER = 0; - - assign intr_msi_rdy = CFG_INTERRUPT_MSI_SENT & ~CFG_INTERRUPT_MSI_FAIL; - - assign PCIE_CQ_NP_REQ = 1; - - engine_layer - #(// Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), - .C_PIPELINE_INPUT (C_PIPELINE_INPUT), - .C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT), - .C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4), - .C_VENDOR (C_VENDOR)) - engine_layer_inst - (// Outputs - .RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]), - .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_DATA_VALID (rxc_data_valid), - .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]), - .RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]), - .RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]), - .RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]), - .RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]), - .RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]), - .RXC_META_EP (rxc_meta_ep), - - .RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]), - .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_VALID (rxr_data_valid), - .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), - .RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]), - .RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]), - .RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]), - .RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]), - .RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]), - .RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]), - .RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]), - .RXR_META_EP (rxr_meta_ep), - - .TXC_DATA_READY (txc_data_ready), - .TXC_META_READY (txc_meta_ready), - .TXC_SENT (txc_sent), - - .TXR_DATA_READY (txr_data_ready), - .TXR_META_READY (txr_meta_ready), - .TXR_SENT (txr_sent), - - .RST_LOGIC (RST_OUT), - // Unconnected Outputs - .TX_TLP (wTxTlp_nc), - .TX_TLP_VALID (wTxTlpValid_nc), - .TX_TLP_START_FLAG (wTxTlpStartFlag_nc), - .TX_TLP_START_OFFSET (wTxTlpStartOffset_nc), - .TX_TLP_END_FLAG (wTxTlpEndFlag_nc), - .TX_TLP_END_OFFSET (wTxTlpEndOffset_nc), - - .RX_TLP_READY (wRxTlpReady_nc), - // Inputs - .CLK_BUS (clk), - .RST_BUS (rst_in), - - .CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]), - - .TXC_DATA_VALID (txc_data_valid), - .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), - .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_META_VALID (txc_meta_valid), - .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]), - .TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]), - .TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]), - .TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]), - .TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]), - .TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]), - .TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]), - .TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]), - .TXC_META_EP (txc_meta_ep), - - .TXR_DATA_VALID (txr_data_valid), - .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), - .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_META_VALID (txr_meta_valid), - .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]), - .TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]), - .TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]), - .TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]), - .TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]), - .TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]), - .TXR_META_EP (txr_meta_ep), - // Unconnected Inputs - .RX_TLP (wRxTlp_nc), - .RX_TLP_VALID (wRxTlpValid_nc), - .RX_TLP_START_FLAG (wRxTlpStartFlag_nc), - .RX_TLP_START_OFFSET (wRxTlpStartOffset_nc), - .RX_TLP_END_FLAG (wRxTlpEndFlag_nc), - .RX_TLP_END_OFFSET (wRxTlpEndOffset_nc), - .RX_TLP_BAR_DECODE (wRxTlpBarDecode_nc), - - .TX_TLP_READY (wTxTlpReady_nc), - /*AUTOINST*/ - // Outputs - .M_AXIS_CQ_TREADY (M_AXIS_CQ_TREADY), - .M_AXIS_RC_TREADY (M_AXIS_RC_TREADY), - .S_AXIS_CC_TVALID (S_AXIS_CC_TVALID), - .S_AXIS_CC_TLAST (S_AXIS_CC_TLAST), - .S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]), - .S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID), - .S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST), - .S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_RQ_TKEEP (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_RQ_TUSER (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]), - // Inputs - .M_AXIS_CQ_TVALID (M_AXIS_CQ_TVALID), - .M_AXIS_CQ_TLAST (M_AXIS_CQ_TLAST), - .M_AXIS_CQ_TDATA (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_CQ_TKEEP (M_AXIS_CQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_CQ_TUSER (M_AXIS_CQ_TUSER[`SIG_CQ_TUSER_W-1:0]), - .M_AXIS_RC_TVALID (M_AXIS_RC_TVALID), - .M_AXIS_RC_TLAST (M_AXIS_RC_TLAST), - .M_AXIS_RC_TDATA (M_AXIS_RC_TDATA[C_PCI_DATA_WIDTH-1:0]), - .M_AXIS_RC_TKEEP (M_AXIS_RC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]), - .M_AXIS_RC_TUSER (M_AXIS_RC_TUSER[`SIG_RC_TUSER_W-1:0]), - .S_AXIS_CC_TREADY (S_AXIS_CC_TREADY), - .S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY)); - - riffa - #(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/ - /*AUTOINSTPARAM*/ - // Parameters - .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_NUM_CHNL (C_NUM_CHNL), - .C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES), - .C_VENDOR (C_VENDOR), - .C_FPGA_NAME (C_FPGA_NAME), - .C_FPGA_ID (C_FPGA_ID), - .C_DEPTH_PACKETS (C_DEPTH_PACKETS)) - riffa_inst - (// Outputs - .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), - .TXC_DATA_VALID (txc_data_valid), - .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXC_META_VALID (txc_meta_valid), - .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]), - .TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]), - .TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]), - .TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]), - .TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]), - .TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]), - .TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]), - .TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]), - .TXC_META_EP (txc_meta_ep), - - .TXR_DATA_VALID (txr_data_valid), - .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), - .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .TXR_META_VALID (txr_meta_valid), - .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), - .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), - .TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]), - .TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]), - .TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]), - .TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]), - .TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]), - .TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]), - .TXR_META_EP (txr_meta_ep), - - .INTR_MSI_REQUEST (intr_msi_request), - // Inputs - .CLK (clk), - .RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]), - .RXR_DATA_VALID (rxr_data_valid), - .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), - .RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]), - .RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]), - .RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]), - .RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]), - .RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]), - .RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]), - .RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]), - .RXR_META_EP (rxr_meta_ep), - - .RXC_DATA_VALID (rxc_data_valid), - .RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]), - .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), - .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), - .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), - .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]), - .RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]), - .RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]), - .RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]), - .RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]), - .RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]), - .RXC_META_EP (rxc_meta_ep), - - .TXC_DATA_READY (txc_data_ready), - .TXC_META_READY (txc_meta_ready), - .TXC_SENT (txc_sent), - - .TXR_DATA_READY (txr_data_ready), - .TXR_META_READY (txr_meta_ready), - .TXR_SENT (txr_sent), - - .CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]), - .CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable), - .CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]), - .CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]), - .CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]), - .CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]), - .CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable), - .CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel), - .CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]), - .CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]), - - .INTR_MSI_RDY (intr_msi_rdy), - - .DONE_TXC_RST (done_txc_rst), - .DONE_TXR_RST (done_txr_rst), - .RST_BUS (rst_in), - /*AUTOINST*/ - // Outputs - .RST_OUT (RST_OUT), - .CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]), - .CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]), - .CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]), - .CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]), - .CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]), - .CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]), - .CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]), - // Inputs - .CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]), - .CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]), - .CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]), - .CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]), - .CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]), - .CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]), - .CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]), - .CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]), - .CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]), - .CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0])); - -endmodule -// Local Variables: -// verilog-library-directories:("../../riffa_hdl/") -// End: -