From 31b82c177778a1d77b353d028b0d7bef84236bd0 Mon Sep 17 00:00:00 2001 From: Dustin Richmond Date: Wed, 22 Jul 2015 17:29:35 -0700 Subject: [PATCH] Adding graceful reset logic to the Ultrascale TX Engines The graceful reset logic splits the RST_IN port into the RST_BUS and RST_LOGIC ports. The RST_BUS port is for when the entire PCIe (or whatever) bus is undergoing reset and the RIFFA logic should not worry about corrupting any state by terminating a packet early (causing a malformed packet). RST_LOGIC is for logic resets, where PCIe state is not affected and may be corrupted by a malformed packet. --- fpga/riffa_hdl/reset_controller.v | 44 +++++ fpga/riffa_hdl/resetter.v | 91 ---------- fpga/riffa_hdl/tx_alignment_pipeline.v | 35 +++- fpga/riffa_hdl/tx_data_fifo.v | 18 ++ fpga/riffa_hdl/tx_data_pipeline.v | 5 +- fpga/riffa_hdl/tx_engine.v | 10 +- fpga/riffa_hdl/txc_engine_ultrascale.v | 227 +++++++++++++------------ fpga/riffa_hdl/txr_engine_ultrascale.v | 202 +++++++++++----------- 8 files changed, 327 insertions(+), 305 deletions(-) delete mode 100644 fpga/riffa_hdl/resetter.v diff --git a/fpga/riffa_hdl/reset_controller.v b/fpga/riffa_hdl/reset_controller.v index a6422b0..df45ab1 100644 --- a/fpga/riffa_hdl/reset_controller.v +++ b/fpga/riffa_hdl/reset_controller.v @@ -1,3 +1,47 @@ +// ---------------------------------------------------------------------- +// Copyright (c) 2015, The Regents of the University of California All +// rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above +// copyright notice, this list of conditions and the following +// disclaimer in the documentation and/or other materials provided +// with the distribution. +// +// * Neither the name of The Regents of the University of California +// nor the names of its contributors may be used to endorse or +// promote products derived from this software without specific +// prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE +// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +// DAMAGE. +// ---------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// Filename: trellis.vh +// Version: 1.0 +// Verilog Standard: Verilog-2001 +// Description: The reset_controller module will safely reset a single stage +// pipeline without using an asychronous reset (bleh). It is intended for use in +// the TX engines, where it will control the output stage of the engine, and +// provide a gracefull end-of-packet reset +// Author: Dustin Richmond (@darichmond) +//----------------------------------------------------------------------------- `define S_RC_IDLE 3'b001 `define S_RC_WAIT 3'b010 `define S_RC_ACTIVE 3'b100 diff --git a/fpga/riffa_hdl/resetter.v b/fpga/riffa_hdl/resetter.v deleted file mode 100644 index b6ac155..0000000 --- a/fpga/riffa_hdl/resetter.v +++ /dev/null @@ -1,91 +0,0 @@ -// ---------------------------------------------------------------------- -// Copyright (c) 2015, The Regents of the University of California All -// rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above -// copyright notice, this list of conditions and the following -// disclaimer in the documentation and/or other materials provided -// with the distribution. -// -// * Neither the name of The Regents of the University of California -// nor the names of its contributors may be used to endorse or -// promote products derived from this software without specific -// prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE -// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR -// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -// DAMAGE. -// ---------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// Filename: resetter.v -// Version: 1.00.a -// Verilog Standard: Verilog-2001 -// Description: A simple reset controller. -// Author: Dustin Richmond (@darichmond) -//----------------------------------------------------------------------------- -`timescale 1ns/1ns -`include "functions.vh" -module resetter - #(parameter C_RST_COUNT = 10, - parameter C_RST_USE_SHREG = 0) - (input CLK, - input RST_IN, - output RST_OUT); - localparam C_CLOG2_RST_COUNT = clog2s(C_RST_COUNT); - localparam C_CEIL2_RST_COUNT = 1 << C_CLOG2_RST_COUNT; - - generate - wire [C_RST_COUNT-1:0] wRstShift; - if(C_RST_USE_SHREG > 0) begin : rst_shreg - shiftreg - #(// Parameters - .C_DEPTH (C_RST_COUNT), - .C_WIDTH (1), - .C_VALUE (1'b1)) - rst_shreg - (// Outputs - .RD_DATA (wRstShift), - // Inputs - .WR_DATA (0), - /*AUTOINST*/ - // Inputs - .CLK (CLK), - .RST_IN (RST_IN)); - assign RST_OUT = wRstShift[C_RST_COUNT-1]; - end else begin : rst_counter // block: rst_shreg - wire [C_CLOG2_RST_COUNT-1:0] wRstCount; - counter - #(// Parameters - .C_MAX_VALUE (C_CEIL2_RST_COUNT - 1), - .C_SAT_VALUE (C_CEIL2_RST_COUNT - 1), - .C_RST_VALUE (C_CEIL2_RST_COUNT - C_RST_COUNT) - /*AUTOINSTPARAM*/) - rst_counter - (// Outputs - .VALUE (wRstCount), - // Inputs - .ENABLE (1'b1), - /*AUTOINST*/ - // Inputs - .CLK (CLK), - .RST_IN (RST_IN)); - assign RST_OUT = wRstCount[C_CLOG2_RST_COUNT-1]; - end - endgenerate -endmodule diff --git a/fpga/riffa_hdl/tx_alignment_pipeline.v b/fpga/riffa_hdl/tx_alignment_pipeline.v index 8bfcefb..5aa90f9 100644 --- a/fpga/riffa_hdl/tx_alignment_pipeline.v +++ b/fpga/riffa_hdl/tx_alignment_pipeline.v @@ -106,6 +106,7 @@ module tx_alignment_pipeline input [(C_DATA_WIDTH/32)-1:0] TX_DATA_WORD_VALID, input [C_DATA_WIDTH-1:0] TX_DATA, input TX_DATA_START_FLAG, + input TX_DATA_PACKET_VALID, input [(C_DATA_WIDTH/32)-1:0] TX_DATA_END_FLAGS, output [(C_DATA_WIDTH/32)-1:0] TX_DATA_WORD_READY, @@ -141,6 +142,7 @@ module tx_alignment_pipeline // Wires from the data interface input registers wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordValid; + wire wTxDataPacketValid; wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordReady; wire [C_DATA_WIDTH-1:0] wTxData; wire wTxDataStartFlag; @@ -239,13 +241,13 @@ module tx_alignment_pipeline // Assignments for the ready stage assign wTxHdrReady = (wTxMuxSelectDataEndFlag & wTxMuxSelectValid & wTxMuxSelectReady) | ~wTxMuxSelectValid; assign wTxMuxSelectReady = (wTxPktReady & wTxHdrNoPayload) | - (wTxPktReady & wTxDataWordValid != 0) | + (wTxPktReady & wTxDataPacketValid) | (~wTxMuxSelectValid); assign wTxPktStartFlag = wTxMuxSelectPktStartFlag; assign wTxPktEndFlag = wTxMuxSelectDataEndFlag; assign wTxPktEndOffset = wTxHdrPacketLen[C_OFFSET_WIDTH-1:0]-1; // TODO: Retime -1? - assign wTxPktValid = wTxMuxSelectValid & (wTxHdrNoPayload | (~wTxHdrNoPayload & (wTxDataWordValid != 0))); - assign wTxDataWordReady = wTxMuxSelectDataReady & {C_NUM_MUXES{wTxPktReady & wTxMuxSelectValid & ~wTxHdrNoPayload}}; + assign wTxPktValid = wTxMuxSelectValid & (wTxHdrNoPayload | (~wTxHdrNoPayload & wTxDataPacketValid)); + assign wTxDataWordReady = wTxMuxSelectDataReady & {C_NUM_MUXES{wTxPktReady & wTxMuxSelectValid & wTxDataPacketValid & ~wTxHdrNoPayload}}; // Assignments for the output stage assign TX_PKT_START_OFFSET = {C_OFFSET_WIDTH{1'b0}}; @@ -423,6 +425,27 @@ module tx_alignment_pipeline assign wAggregate[i] = wTxHdr[i*32 +: 32]; end + pipeline + #(// Parameters + .C_DEPTH (C_PIPELINE_DATA_INPUT?1:0), + .C_WIDTH (1), + .C_USE_MEMORY (0) + /*AUTOINSTPARAM*/) + packet_valid_register + (// Outputs + .WR_DATA_READY (), + .RD_DATA (), + .RD_DATA_VALID (wTxDataPacketValid), + // Inputs + .WR_DATA (), + .WR_DATA_VALID (TX_DATA_PACKET_VALID), + .RD_DATA_READY (~wTxDataPacketValid | + ((wTxDataEndFlags & wTxDataWordReady) != 0)), + // TODO: End flag read? This is odd, you want to read when there is not a valid packet + /*AUTOINST*/ + // Inputs + .CLK (CLK), + .RST_IN (RST_IN)); for( i = 0; i < C_NUM_MUXES ; i = i + 1) begin : gen_data_input_regs assign wAggregate[i + C_MAX_HDR_WIDTH/32] = wTxData[32*i +: 32]; pipeline @@ -434,10 +457,12 @@ module tx_alignment_pipeline data_register_ (// Outputs .WR_DATA_READY (TX_DATA_WORD_READY[i]), - .RD_DATA ({wTxData[32*i +: 32],wTxDataEndFlags[i]}), + .RD_DATA ({wTxData[32*i +: 32], + wTxDataEndFlags[i]}), .RD_DATA_VALID (wTxDataWordValid[i]), // Inputs - .WR_DATA ({TX_DATA[32*i +: 32],TX_DATA_END_FLAGS[i] & TX_DATA_WORD_VALID[i]}), + .WR_DATA ({TX_DATA[32*i +: 32], + TX_DATA_END_FLAGS[i] & TX_DATA_WORD_VALID[i]}), .WR_DATA_VALID (TX_DATA_WORD_VALID[i]), .RD_DATA_READY (wTxDataWordReady[i]), /*AUTOINST*/ diff --git a/fpga/riffa_hdl/tx_data_fifo.v b/fpga/riffa_hdl/tx_data_fifo.v index 65c0e70..aaca47d 100644 --- a/fpga/riffa_hdl/tx_data_fifo.v +++ b/fpga/riffa_hdl/tx_data_fifo.v @@ -236,6 +236,24 @@ module tx_data_fifo .CLK (CLK), .RST_IN (RST_IN)); end // for ( i = 0 ; i < C_NUM_FIFOS ; i = i + 1 ) + pipeline + #(.C_DEPTH (C_FIFO_OUTPUT_DEPTH), + .C_USE_MEMORY (0), + .C_WIDTH (1) + /*AUTOINSTPARAM*/) + packet_valid_reg + (// Outputs + .WR_DATA_READY (), + .RD_DATA (), + .RD_DATA_VALID (RD_TX_DATA_PACKET_VALID), + // Inputs + .WR_DATA (), + .WR_DATA_VALID (wRdTxDataPacketValid), + .RD_DATA_READY ((RD_TX_DATA_WORD_READY & RD_TX_DATA_END_FLAGS) !== 0), + /*AUTOINST*/ + // Inputs + .CLK (CLK), + .RST_IN (RST_IN)); endgenerate endmodule // Local Variables: diff --git a/fpga/riffa_hdl/tx_data_pipeline.v b/fpga/riffa_hdl/tx_data_pipeline.v index be98acc..a022cda 100644 --- a/fpga/riffa_hdl/tx_data_pipeline.v +++ b/fpga/riffa_hdl/tx_data_pipeline.v @@ -81,7 +81,8 @@ module tx_data_pipeline output [C_DATA_WIDTH-1:0] RD_TX_DATA, output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_END_FLAGS, output RD_TX_DATA_START_FLAG, - output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_VALID + output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_VALID, + output RD_TX_DATA_PACKET_VALID ); wire wRdTxDataValid; @@ -143,7 +144,7 @@ module tx_data_pipeline .RD_TX_DATA_START_FLAG (RD_TX_DATA_START_FLAG), .RD_TX_DATA_WORD_VALID (RD_TX_DATA_WORD_VALID[(C_DATA_WIDTH/32)-1:0]), .RD_TX_DATA_END_FLAGS (RD_TX_DATA_END_FLAGS[(C_DATA_WIDTH/32)-1:0]), - .RD_TX_DATA_PACKET_VALID (), + .RD_TX_DATA_PACKET_VALID (RD_TX_DATA_PACKET_VALID), // Inputs .WR_TX_DATA (wRdTxData), .WR_TX_DATA_VALID (wRdTxDataValid), diff --git a/fpga/riffa_hdl/tx_engine.v b/fpga/riffa_hdl/tx_engine.v index 12e6a77..ea7ef03 100644 --- a/fpga/riffa_hdl/tx_engine.v +++ b/fpga/riffa_hdl/tx_engine.v @@ -113,6 +113,7 @@ module tx_engine wire [C_DATA_WIDTH-1:0] wTxData; wire [clog2s(C_DATA_WIDTH/32)-1:0] wTxDataEndOffset; wire wTxDataStartFlag; + wire wTxDataPacketValid; wire [(C_DATA_WIDTH/32)-1:0] wTxDataEndFlags; wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordValid; wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordReady; @@ -134,6 +135,7 @@ module tx_engine .RD_TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]), .RD_TX_DATA_START_FLAG (wTxDataStartFlag), .RD_TX_DATA_END_FLAGS (wTxDataEndFlags[(C_DATA_WIDTH/32)-1:0]), + .RD_TX_DATA_PACKET_VALID (wTxDataPacketValid), .WR_TX_DATA_READY (TX_DATA_READY), // Inputs .RD_TX_DATA_WORD_READY (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]), @@ -155,7 +157,7 @@ module tx_engine .C_PIPELINE_INPUT (C_PIPELINE_HDR_FIFO_INPUT), /*AUTOINSTPARAM*/ // Parameters - .C_DEPTH_PACKETS (C_ACTUAL_HDR_FIFO_DEPTH), + .C_DEPTH_PACKETS (C_DEPTH_PACKETS), .C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH), .C_VENDOR (C_VENDOR)) txhf_inst @@ -177,15 +179,13 @@ module tx_engine .WR_TX_HDR_PACKET_LEN (TX_HDR_PACKET_LEN[`SIG_PACKETLEN_W-1:0]), .RD_TX_HDR_READY (wTxHdrReady), /*AUTOINST*/ - // Outputs // Inputs .CLK (CLK), .RST_IN (RST_IN)); // TX Header Fifo tx_alignment_pipeline - #( - // Parameters + #(// Parameters .C_PIPELINE_OUTPUT (1), .C_PIPELINE_DATA_INPUT (1), .C_PIPELINE_HDR_INPUT (C_PIPELINE_HDR_INPUT), @@ -195,6 +195,7 @@ module tx_engine // Parameters .C_USE_COMPUTE_REG (C_USE_COMPUTE_REG), .C_USE_READY_REG (C_USE_READY_REG), + .C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH), .C_VENDOR (C_VENDOR)) tx_alignment_inst ( @@ -211,6 +212,7 @@ module tx_engine .TX_DATA_START_FLAG (wTxDataStartFlag), .TX_DATA_END_FLAGS (wTxDataEndFlags), .TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]), + .TX_DATA_PACKET_VALID (wTxDataPacketValid), .TX_DATA (wTxData[C_DATA_WIDTH-1:0]), .TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]), .TX_HDR_VALID (wTxHdrValid), diff --git a/fpga/riffa_hdl/txc_engine_ultrascale.v b/fpga/riffa_hdl/txc_engine_ultrascale.v index c5dd9af..c5338fb 100644 --- a/fpga/riffa_hdl/txc_engine_ultrascale.v +++ b/fpga/riffa_hdl/txc_engine_ultrascale.v @@ -105,10 +105,13 @@ module txc_engine_ultrascale localparam C_MAX_NONPAY_DWORDS = C_MAX_HDR_DWORDS + C_MAX_ALIGN_DWORDS; // localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT; - localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT; - localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT; - + localparam C_PIPELINE_FORMATTER_OUTPUT = 1; + localparam C_FORMATTER_DELAY = 1 + C_PIPELINE_FORMATTER_INPUT; + localparam C_RST_COUNT = 10; /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire RST_OUT; // From txc_trans_inst of txc_translation_layer.v + // End of automatics /*AUTOINPUT*/ ///*AUTOOUTPUT*/ @@ -135,37 +138,29 @@ module txc_engine_ultrascale wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktStartOffset; wire wTxcPktValid; wire wTxcPktReady; - wire wNDoneRst; + + wire wTransDoneRst; + wire wTransRstOut; + wire wEngDoneRst; + wire wRst; + wire [C_RST_COUNT:0] wShiftRegRst; - reg rRstSticky, _rRstSticky; - reg rRST, _rRST; + assign DONE_TXC_RST = wTransDoneRst & wEngDoneRst; + assign wRst = wShiftRegRst[C_RST_COUNT-3]; + assign wEngDoneRst = ~wShiftRegRst[C_RST_COUNT]; - assign DONE_TXC_RST = ~wNDoneRst; - - // First-draft reset controller for the ultrascale engines - // (This might be moved into the TX Engines eventually...) - always @(*) begin - _rRST = RST_BUS | ((RST_LOGIC | rRstSticky) & (~S_AXIS_CC_TVALID | S_AXIS_CC_TVALID & S_AXIS_CC_TVALID & S_AXIS_CC_TLAST)); - end - - always @(posedge CLK) begin - rRST <= _rRST; - if(rRST) - rRstSticky <= 0; - else if(RST_LOGIC) - rRstSticky <= 1; - end - - resetter + shiftreg #(// Parameters - .C_RST_COUNT (10), // Arbitrary magic number - .C_RST_USE_SHREG (1) + .C_DEPTH (C_RST_COUNT), + .C_WIDTH (1), + .C_VALUE (1) /*AUTOINSTPARAM*/) - rst_done + rst_shiftreg (// Outputs - .RST_OUT (wNDoneRst), + .RD_DATA (wShiftRegRst), // Inputs - .RST_IN (rRST | rRstSticky | RST_BUS), + .RST_IN (RST_BUS), + .WR_DATA (wTransRstOut), /*AUTOINST*/ // Inputs .CLK (CLK)); @@ -188,7 +183,7 @@ module txc_engine_ultrascale .TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]), // Inputs .TX_HDR_READY (wTxHdrReady), - .RST_IN (rRST), + .RST_IN (wRst), /*AUTOINST*/ // Outputs .TXC_META_READY (TXC_META_READY), @@ -243,37 +238,40 @@ module txc_engine_ultrascale .TX_DATA_END_FLAG (TXC_DATA_END_FLAG), .TX_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]), .TX_PKT_READY (wTxcPktReady), - .RST_IN (rRST), + .RST_IN (wRst), /*AUTOINST*/ // Inputs .CLK (CLK)); txc_translation_layer - #(// Parameters + #(/*AUTOINSTPARAM*/ + // Parameters .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), - .C_PIPELINE_INPUT (C_PIPELINE_INPUT), - .C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT) - /*AUTOINSTPARAM*/) + .C_PIPELINE_INPUT (C_PIPELINE_INPUT)) txc_trans_inst (// Outputs .TXC_PKT_READY (wTxcPktReady), - .S_AXIS_CC_TVALID (S_AXIS_CC_TVALID), - .S_AXIS_CC_TLAST (S_AXIS_CC_TLAST), - .S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]), + .DONE_RST (wTransDoneRst), + .RST_OUT (wTransRstOut), // Inputs - .RST_IN (rRST), .TXC_PKT (wTxcPkt), .TXC_PKT_VALID (wTxcPktValid), .TXC_PKT_START_FLAG (wTxcPktStartFlag), .TXC_PKT_START_OFFSET (wTxcPktStartOffset), .TXC_PKT_END_FLAG (wTxcPktEndFlag), .TXC_PKT_END_OFFSET (wTxcPktEndOffset), - .S_AXIS_CC_TREADY (S_AXIS_CC_TREADY), /*AUTOINST*/ + // Outputs + .S_AXIS_CC_TVALID (S_AXIS_CC_TVALID), + .S_AXIS_CC_TLAST (S_AXIS_CC_TLAST), + .S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]), + .S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]), + .S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]), // Inputs - .CLK (CLK)); + .CLK (CLK), + .RST_BUS (RST_BUS), + .RST_LOGIC (RST_LOGIC), + .S_AXIS_CC_TREADY (S_AXIS_CC_TREADY)); endmodule // txc_engine_ultrascale @@ -359,20 +357,20 @@ module txc_formatter_ultrascale pipeline #( // Parameters - .C_DEPTH (C_PIPELINE_INPUT?1:0), - .C_WIDTH (C_MAX_HDR_WIDTH + `SIG_TYPE_W), - .C_USE_MEMORY (0) + .C_DEPTH (C_PIPELINE_INPUT?1:0), + .C_WIDTH (C_MAX_HDR_WIDTH + `SIG_TYPE_W), + .C_USE_MEMORY (0) /*AUTOINSTPARAM*/) input_inst ( // Outputs - .WR_DATA_READY (TXC_META_READY), - .RD_DATA ({wTxHdr,wTxType}), - .RD_DATA_VALID (wTxHdrValid), + .WR_DATA_READY (TXC_META_READY), + .RD_DATA ({wTxHdr,wTxType}), + .RD_DATA_VALID (wTxHdrValid), // Inputs - .WR_DATA ({32'b0,wHdr,TXC_META_TYPE}), - .WR_DATA_VALID (TXC_META_VALID), - .RD_DATA_READY (wTxHdrReady), + .WR_DATA ({32'b0,wHdr,TXC_META_TYPE}), + .WR_DATA_VALID (TXC_META_VALID), + .RD_DATA_READY (wTxHdrReady), /*AUTOINST*/ // Inputs .CLK (CLK), @@ -381,20 +379,20 @@ module txc_formatter_ultrascale pipeline #( // Parameters - .C_DEPTH (C_PIPELINE_OUTPUT?1:0), - .C_WIDTH (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W), - .C_USE_MEMORY (0) + .C_DEPTH (C_PIPELINE_OUTPUT?1:0), + .C_WIDTH (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W), + .C_USE_MEMORY (0) /*AUTOINSTPARAM*/) output_inst ( // Outputs - .WR_DATA_READY (wTxHdrReady), - .RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}), - .RD_DATA_VALID (TX_HDR_VALID), + .WR_DATA_READY (wTxHdrReady), + .RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}), + .RD_DATA_VALID (TX_HDR_VALID), // Inputs - .WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}), - .WR_DATA_VALID (wTxHdrValid), - .RD_DATA_READY (TX_HDR_READY), + .WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}), + .WR_DATA_VALID (wTxHdrValid), + .RD_DATA_READY (TX_HDR_READY), /*AUTOINST*/ // Inputs .CLK (CLK), @@ -402,19 +400,16 @@ module txc_formatter_ultrascale endmodule module txc_translation_layer - #( - parameter C_PCI_DATA_WIDTH = 10'd128, - parameter C_PIPELINE_INPUT = 1, - parameter C_PIPELINE_OUTPUT = 0 - - ) - ( - // Interface: Clocks + #(parameter C_PCI_DATA_WIDTH = 10'd128, + parameter C_PIPELINE_INPUT = 1) + (// Interface: Clocks input CLK, // Interface: Resets - input RST_IN, - + input RST_BUS, // Replacement for generic RST_IN + input RST_LOGIC, // Addition for RIFFA_RST + output DONE_RST, + output RST_OUT, // Interface: TXC Classic output TXC_PKT_READY, input [C_PCI_DATA_WIDTH-1:0] TXC_PKT, @@ -434,8 +429,8 @@ module txc_translation_layer ); localparam C_INPUT_STAGES = C_PIPELINE_INPUT != 0? 1:0; - localparam C_OUTPUT_STAGES = C_PIPELINE_OUTPUT != 0? 1:0; - + localparam C_OUTPUT_STAGES = 1; + localparam C_RST_COUNT = 10; wire wTxcPktReady; wire [C_PCI_DATA_WIDTH-1:0] wTxcPkt; wire wTxcPktValid; @@ -451,46 +446,65 @@ module txc_translation_layer wire [(C_PCI_DATA_WIDTH/32)-1:0] wSAxisCcTKeep; wire [`SIG_CC_TUSER_W-1:0] wSAxisCcTUser; + wire wRst; + wire wRstWaiting; /*ASSIGN TXC -> CC*/ assign wTxcPktReady = wSAxisCcTReady; assign wSAxisCcTValid = wTxcPktValid; assign wSAxisCcTLast = wTxcPktEndFlag; assign wSAxisCcTData = wTxcPkt; - assign S_AXIS_CC_TUSER = `SIG_CC_TUSER_W'd0; // Do not enable parity bits, and no discontinues + // Do not enable parity bits, and no discontinues + assign S_AXIS_CC_TUSER = `SIG_CC_TUSER_W'd0; + assign RST_OUT = wRst; + + // This reset controller assumes there is always an output stage + reset_controller + #(/*AUTOINSTPARAM*/ + // Parameters + .C_RST_COUNT (C_RST_COUNT)) + rc + (// Outputs + .RST_OUT (wRst), + .WAITING_RESET (wRstWaiting), + // Inputs + .RST_IN (RST_BUS), + .SIGNAL_RST (RST_LOGIC), + .WAIT_RST (S_AXIS_CC_TVALID), + .NEXT_CYC_RST (S_AXIS_CC_TREADY & S_AXIS_CC_TLAST), + /*AUTOINST*/ + // Outputs + .DONE_RST (DONE_RST), + // Inputs + .CLK (CLK)); pipeline - #( - // Parameters - .C_DEPTH (C_INPUT_STAGES), - .C_WIDTH (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))), - .C_USE_MEMORY (0) + #(// Parameters + .C_DEPTH (C_INPUT_STAGES), + .C_WIDTH (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))), + .C_USE_MEMORY (0) /*AUTOINSTPARAM*/) input_inst - ( - // Outputs - .WR_DATA_READY (TXC_PKT_READY), - .RD_DATA ({wTxcPkt,wTxcPktStartFlag,wTxcPktStartOffset,wTxcPktEndFlag,wTxcPktEndOffset}), - .RD_DATA_VALID (wTxcPktValid), + (// Outputs + .WR_DATA_READY (TXC_PKT_READY), + .RD_DATA ({wTxcPkt,wTxcPktStartFlag,wTxcPktStartOffset,wTxcPktEndFlag,wTxcPktEndOffset}), + .RD_DATA_VALID (wTxcPktValid), // Inputs - .WR_DATA ({TXC_PKT,TXC_PKT_START_FLAG,TXC_PKT_START_OFFSET, - TXC_PKT_END_FLAG,TXC_PKT_END_OFFSET}), - .WR_DATA_VALID (TXC_PKT_VALID), - .RD_DATA_READY (wTxcPktReady), + .WR_DATA ({TXC_PKT,TXC_PKT_START_FLAG,TXC_PKT_START_OFFSET, + TXC_PKT_END_FLAG,TXC_PKT_END_OFFSET}), + .WR_DATA_VALID (TXC_PKT_VALID), + .RD_DATA_READY (wTxcPktReady), + .RST_IN (wRst), /*AUTOINST*/ // Inputs - .CLK (CLK), - .RST_IN (RST_IN)); - + .CLK (CLK)); offset_to_mask - #( - // Parameters + #(// Parameters .C_MASK_SWAP (0), .C_MASK_WIDTH (C_PCI_DATA_WIDTH/32) /*AUTOINSTPARAM*/) otom_inst - ( - // Outputs + (// Outputs .MASK (wSAxisCcTKeep), // Inputs .OFFSET_ENABLE (wTxcPktEndFlag), @@ -498,26 +512,25 @@ module txc_translation_layer /*AUTOINST*/); pipeline - #( - // Parameters - .C_DEPTH (C_OUTPUT_STAGES), - .C_WIDTH (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)), - .C_USE_MEMORY (0) + #(// Parameters + .C_DEPTH (C_OUTPUT_STAGES), + .C_WIDTH (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)), + .C_USE_MEMORY (0) /*AUTOINSTPARAM*/) output_inst ( // Outputs - .WR_DATA_READY (wSAxisCcTReady), - .RD_DATA ({S_AXIS_CC_TDATA,S_AXIS_CC_TLAST,S_AXIS_CC_TKEEP}), - .RD_DATA_VALID (S_AXIS_CC_TVALID), + .WR_DATA_READY (wSAxisCcTReady), + .RD_DATA ({S_AXIS_CC_TDATA,S_AXIS_CC_TLAST,S_AXIS_CC_TKEEP}), + .RD_DATA_VALID (S_AXIS_CC_TVALID), // Inputs - .WR_DATA ({wSAxisCcTData,wSAxisCcTLast,wSAxisCcTKeep}), - .WR_DATA_VALID (wSAxisCcTValid), - .RD_DATA_READY (S_AXIS_CC_TREADY), + .WR_DATA ({wSAxisCcTData,wSAxisCcTLast,wSAxisCcTKeep}), + .WR_DATA_VALID (wSAxisCcTValid & ~wRstWaiting), + .RD_DATA_READY (S_AXIS_CC_TREADY), + .RST_IN (wRst), /*AUTOINST*/ // Inputs - .CLK (CLK), - .RST_IN (RST_IN)); + .CLK (CLK)); endmodule // Local Variables: diff --git a/fpga/riffa_hdl/txr_engine_ultrascale.v b/fpga/riffa_hdl/txr_engine_ultrascale.v index 93ea68d..e97fefb 100644 --- a/fpga/riffa_hdl/txr_engine_ultrascale.v +++ b/fpga/riffa_hdl/txr_engine_ultrascale.v @@ -105,7 +105,7 @@ module txr_engine_ultrascale localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT; localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT; localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT; - + localparam C_RST_COUNT = 10; /*AUTOWIRE*/ /*AUTOINPUT*/ ///*AUTOOUTPUT*/ @@ -133,44 +133,35 @@ module txr_engine_ultrascale wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrPktStartOffset; wire wTxrPktValid; wire wTxrPktReady; - wire wNDoneRst; + + wire wTransDoneRst; + wire wTransRstOut; + wire wEngDoneRst; + wire wRst; + wire [C_RST_COUNT:0] wShiftRegRst; + + assign DONE_TXR_RST = wTransDoneRst & wEngDoneRst; + assign wRst = wShiftRegRst[C_RST_COUNT-3]; + assign wEngDoneRst = ~wShiftRegRst[C_RST_COUNT]; - reg rRstSticky, _rRstSticky; - reg rRST, _rRST; - - assign DONE_TXR_RST = ~wNDoneRst; - - // First-draft reset controller for the ultrascale engines - // (This might be moved into the TX Engines eventually...) - always @(*) begin - _rRST = RST_BUS | ((RST_LOGIC | rRstSticky) & (~S_AXIS_RQ_TVALID | S_AXIS_RQ_TVALID & S_AXIS_RQ_TLAST & S_AXIS_RQ_TREADY)); - end - - always @(posedge CLK) begin - rRST <= _rRST; - if(rRST) - rRstSticky <= 0; - else if(RST_LOGIC) - rRstSticky <= 1; - end - - resetter + shiftreg #(// Parameters - .C_RST_COUNT (10), // Arbitrary magic number - .C_RST_USE_SHREG (1) + .C_DEPTH (C_RST_COUNT), + .C_WIDTH (1), + .C_VALUE (1) /*AUTOINSTPARAM*/) - rst_done + rst_shiftreg (// Outputs - .RST_OUT (wNDoneRst), + .RD_DATA (wShiftRegRst), // Inputs - .RST_IN (rRST | rRstSticky | RST_BUS), + .RST_IN (RST_BUS), + .WR_DATA (wTransRstOut), /*AUTOINST*/ // Inputs .CLK (CLK)); - + txr_formatter_ultrascale - #( - .C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT), + #(.C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT), .C_PIPELINE_INPUT (C_PIPELINE_FORMATTER_INPUT), /*AUTOINSTPARAM*/ // Parameters @@ -179,8 +170,7 @@ module txr_engine_ultrascale .C_MAX_NONPAY_DWORDS (C_MAX_NONPAY_DWORDS), .C_MAX_PACKET_DWORDS (C_MAX_PACKET_DWORDS)) txr_formatter_inst - ( - // Outputs + (// Outputs .TX_HDR_VALID (wTxHdrValid), .TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]), .TX_HDR_NOPAYLOAD (wTxHdrNopayload), @@ -189,7 +179,7 @@ module txr_engine_ultrascale .TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]), // Inputs .TX_HDR_READY (wTxHdrReady), - .RST_IN (rRST), + .RST_IN (wRst), /*AUTOINST*/ // Outputs .TXR_META_READY (TXR_META_READY), @@ -208,8 +198,7 @@ module txr_engine_ultrascale .TXR_META_EP (TXR_META_EP)); tx_engine - #( - .C_DATA_WIDTH (C_PCI_DATA_WIDTH), + #(.C_DATA_WIDTH (C_PCI_DATA_WIDTH), /*AUTOINSTPARAM*/ // Parameters .C_DEPTH_PACKETS (C_DEPTH_PACKETS), @@ -220,8 +209,7 @@ module txr_engine_ultrascale .C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS), .C_VENDOR (C_VENDOR)) txr_engine_inst - ( - // Outputs + (// Outputs .TX_HDR_READY (wTxHdrReady), .TX_DATA_READY (TXR_DATA_READY), .TX_PKT (wTxrPkt[C_DATA_WIDTH-1:0]), @@ -244,27 +232,22 @@ module txr_engine_ultrascale .TX_DATA_END_FLAG (TXR_DATA_END_FLAG), .TX_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]), .TX_PKT_READY (wTxrPktReady), - .RST_IN (rRST), + .RST_IN (wRst),// TODO: /*AUTOINST*/ // Inputs .CLK (CLK)); txr_translation_layer - #( + #(/*AUTOINSTPARAM*/ // Parameters .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), .C_PIPELINE_INPUT (C_PIPELINE_INPUT), - .C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT) - /*AUTOINSTPARAM*/) + .C_RST_COUNT (C_RST_COUNT)) txr_trans_inst - ( - // Outputs + (// Outputs .TXR_PKT_READY (wTxrPktReady), - .S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID), - .S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST), - .S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]), - .S_AXIS_RQ_TKEEP (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]), - .S_AXIS_RQ_TUSER (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]), + .DONE_RST (wTransDoneRst), + .RST_OUT (wTransRstOut), // Inputs .TXR_PKT (wTxrPkt), .TXR_PKT_VALID (wTxrPktValid), @@ -272,11 +255,18 @@ module txr_engine_ultrascale .TXR_PKT_START_OFFSET (wTxrPktStartOffset), .TXR_PKT_END_FLAG (wTxrPktEndFlag), .TXR_PKT_END_OFFSET (wTxrPktEndOffset), - .S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY), - .RST_IN (rRST), /*AUTOINST*/ + // Outputs + .S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID), + .S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST), + .S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]), + .S_AXIS_RQ_TKEEP (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]), + .S_AXIS_RQ_TUSER (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]), // Inputs - .CLK (CLK)); + .CLK (CLK), + .RST_BUS (RST_BUS), + .RST_LOGIC (RST_LOGIC), + .S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY)); endmodule // txr_engine_ultrascale @@ -412,17 +402,17 @@ endmodule module txr_translation_layer - #( - parameter C_PCI_DATA_WIDTH = 10'd128, + #(parameter C_PCI_DATA_WIDTH = 10'd128, parameter C_PIPELINE_INPUT = 1, - parameter C_PIPELINE_OUTPUT = 0 - ) - ( - // Interface: Clocks + parameter C_RST_COUNT = 1) + (// Interface: Clocks input CLK, // Interface: Resets - input RST_IN, + input RST_BUS, // Replacement for generic RST_IN + input RST_LOGIC, // Addition for RIFFA_RST + output RST_OUT, + output DONE_RST, // Interface: TXR Classic output TXR_PKT_READY, @@ -439,12 +429,11 @@ module txr_translation_layer output S_AXIS_RQ_TLAST, output [C_PCI_DATA_WIDTH-1:0] S_AXIS_RQ_TDATA, output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_RQ_TKEEP, - output [`SIG_RQ_TUSER_W-1:0] S_AXIS_RQ_TUSER - ); + output [`SIG_RQ_TUSER_W-1:0] S_AXIS_RQ_TUSER); localparam C_INPUT_STAGES = C_PIPELINE_INPUT != 0? 1:0; - localparam C_OUTPUT_STAGES = C_PIPELINE_OUTPUT != 0? 1:0; - + localparam C_OUTPUT_STAGES = 1; + wire wTxrPktReady; wire [C_PCI_DATA_WIDTH-1:0] wTxrPkt; wire wTxrPktValid; @@ -466,6 +455,8 @@ module txr_translation_layer wire [C_PCI_DATA_WIDTH-1:0] _wSAxisRqTData; wire [(C_PCI_DATA_WIDTH/32)-1:0] _wSAxisRqTKeep; + wire wRst; + wire wRstWaiting; /*ASSIGN TXR -> RQ*/ assign wTxrPktReady = _wSAxisRqTReady; @@ -476,31 +467,50 @@ module txr_translation_layer // BE Hack assign wSAxisRqTUser[3:0] = wTxrPkt[(`UPKT_TXR_FBE_I % C_PCI_DATA_WIDTH) +: `UPKT_TXR_FBE_W]; assign wSAxisRqTUser[7:4] = wTxrPkt[(`UPKT_TXR_LBE_I % C_PCI_DATA_WIDTH) +: `UPKT_TXR_LBE_W]; - assign wSAxisRqTUser[`SIG_RQ_TUSER_W-1:8] = 0; + assign RST_OUT = wRst; + // This reset controller assumes there is always an output stage + reset_controller + #(/*AUTOINSTPARAM*/ + // Parameters + .C_RST_COUNT (C_RST_COUNT)) + rc + (// Outputs + .RST_OUT (wRst), + .WAITING_RESET (wRstWaiting), + // Inputs + .RST_IN (RST_BUS), + .SIGNAL_RST (RST_LOGIC), + .WAIT_RST (S_AXIS_RQ_TVALID), + .NEXT_CYC_RST (S_AXIS_RQ_TREADY & S_AXIS_RQ_TLAST), + /*AUTOINST*/ + // Outputs + .DONE_RST (DONE_RST), + // Inputs + .CLK (CLK)); pipeline #(// Parameters - .C_DEPTH (C_INPUT_STAGES), - .C_WIDTH (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))), - .C_USE_MEMORY (0) + .C_DEPTH (C_INPUT_STAGES), + .C_WIDTH (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))), + .C_USE_MEMORY (0) /*AUTOINSTPARAM*/) input_inst ( // Outputs - .WR_DATA_READY (TXR_PKT_READY), - .RD_DATA ({wTxrPkt,wTxrPktStartFlag,wTxrPktStartOffset,wTxrPktEndFlag,wTxrPktEndOffset}), - .RD_DATA_VALID (wTxrPktValid), + .WR_DATA_READY (TXR_PKT_READY), + .RD_DATA ({wTxrPkt,wTxrPktStartFlag,wTxrPktStartOffset,wTxrPktEndFlag,wTxrPktEndOffset}), + .RD_DATA_VALID (wTxrPktValid), // Inputs - .WR_DATA ({TXR_PKT,TXR_PKT_START_FLAG,TXR_PKT_START_OFFSET, + .WR_DATA ({TXR_PKT,TXR_PKT_START_FLAG,TXR_PKT_START_OFFSET, TXR_PKT_END_FLAG,TXR_PKT_END_OFFSET}), - .WR_DATA_VALID (TXR_PKT_VALID), - .RD_DATA_READY (wTxrPktReady), + .WR_DATA_VALID (TXR_PKT_VALID), + .RD_DATA_READY (wTxrPktReady), + .RST_IN (wRst), /*AUTOINST*/ // Inputs - .CLK (CLK), - .RST_IN (RST_IN)); + .CLK (CLK)); offset_to_mask @@ -522,46 +532,46 @@ module txr_translation_layer pipeline #( // Parameters - .C_DEPTH (64/C_PCI_DATA_WIDTH), - .C_WIDTH (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)), - .C_USE_MEMORY (0) + .C_DEPTH (64/C_PCI_DATA_WIDTH), + .C_WIDTH (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)), + .C_USE_MEMORY (0) /*AUTOINSTPARAM*/) fbe_hack_inst ( // Outputs - .WR_DATA_READY (_wSAxisRqTReady), - .RD_DATA ({wSAxisRqTData,wSAxisRqTLast,wSAxisRqTKeep}), - .RD_DATA_VALID (wSAxisRqTValid), + .WR_DATA_READY (_wSAxisRqTReady), + .RD_DATA ({wSAxisRqTData,wSAxisRqTLast,wSAxisRqTKeep}), + .RD_DATA_VALID (wSAxisRqTValid), // Inputs - .WR_DATA ({_wSAxisRqTData,_wSAxisRqTLast,_wSAxisRqTKeep}), - .WR_DATA_VALID (_wSAxisRqTValid), - .RD_DATA_READY (wSAxisRqTReady), + .WR_DATA ({_wSAxisRqTData,_wSAxisRqTLast,_wSAxisRqTKeep}), + .WR_DATA_VALID (_wSAxisRqTValid), + .RD_DATA_READY (wSAxisRqTReady), + .RST_IN (wRst), /*AUTOINST*/ // Inputs - .CLK (CLK), - .RST_IN (RST_IN)); + .CLK (CLK)); pipeline #( // Parameters - .C_DEPTH (C_OUTPUT_STAGES), - .C_WIDTH (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32) + `SIG_RQ_TUSER_W), - .C_USE_MEMORY (0) + .C_DEPTH (C_OUTPUT_STAGES), + .C_WIDTH (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32) + `SIG_RQ_TUSER_W), + .C_USE_MEMORY (0) /*AUTOINSTPARAM*/) output_inst ( // Outputs - .WR_DATA_READY (wSAxisRqTReady), - .RD_DATA ({S_AXIS_RQ_TDATA,S_AXIS_RQ_TLAST,S_AXIS_RQ_TKEEP,S_AXIS_RQ_TUSER}), - .RD_DATA_VALID (S_AXIS_RQ_TVALID), + .WR_DATA_READY (wSAxisRqTReady), + .RD_DATA ({S_AXIS_RQ_TDATA,S_AXIS_RQ_TLAST,S_AXIS_RQ_TKEEP,S_AXIS_RQ_TUSER}), + .RD_DATA_VALID (S_AXIS_RQ_TVALID), // Inputs - .WR_DATA ({wSAxisRqTData,wSAxisRqTLast,wSAxisRqTKeep,wSAxisRqTUser}), - .WR_DATA_VALID (wSAxisRqTValid), - .RD_DATA_READY (S_AXIS_RQ_TREADY), + .WR_DATA ({wSAxisRqTData,wSAxisRqTLast,wSAxisRqTKeep,wSAxisRqTUser}), + .WR_DATA_VALID (wSAxisRqTValid & ~wRstWaiting), + .RD_DATA_READY (S_AXIS_RQ_TREADY), + .RST_IN (wRst), /*AUTOINST*/ // Inputs - .CLK (CLK), - .RST_IN (RST_IN)); + .CLK (CLK)); endmodule // Local Variables: