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Fixed a bug (uncovered by the clock ratio issue) where the tx_multiplexer would

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confuse the tx_port_monitor by returning too few or too many write-packet
acknowledgements, resulting in a hang (but correct data!).
This commit is contained in:
Dustin Richmond 2016-02-16 16:04:10 -08:00
parent 753ffffd93
commit 4d0bc24319
1 changed files with 5 additions and 4 deletions
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9
fpga/riffa_hdl/tx_multiplexer.v
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@ -98,14 +98,15 @@ module tx_multiplexer
input TXR_SENT);
wire [C_NUM_CHNL-1:0] wAckRdData;
wire wAckValid;
reg [C_NUM_CHNL-1:0] rAckWrData; // Registered fifo input (only write acks)
reg [C_NUM_CHNL-1:0] rAckRdData; // Registered fifo output (only write acks)
reg rAckWrEn,_rAckWrEn; // Fifo write enable (RD or WR_ACK)
reg rAckRdEn; // Fifo read enable (TXR_SENT)
always @(*) begin
_rAckWrEn = (WR_ACK != 0) | (RD_ACK != 0);
_rAckWrEn = (WR_ACK != 0);
end
always @(posedge CLK) begin
@ -116,7 +117,7 @@ module tx_multiplexer
always @(posedge CLK) begin
rAckRdEn <= TXR_SENT;
if(rAckRdEn) begin
rAckRdData <= wAckRdData;
rAckRdData <= wAckRdData & {C_NUM_CHNL{wAckValid}};
end else begin
rAckRdData <= 0;
end
@ -134,7 +135,7 @@ module tx_multiplexer
(// Outputs
.WR_READY (),
.RD_DATA (wAckRdData),
.RD_VALID (),
.RD_VALID (wAckValid),
// Inputs
.WR_DATA (rAckWrData),
.WR_VALID (rAckWrEn),