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https://github.com/KastnerRG/riffa.git
synced 2025-01-30 23:02:54 +08:00
Adding timing improvements to tx_alignment pipeline.
This does not fix the user bug, which occurs in the 64-bit interface. I suspect this is a data under-read/over-read error in the data fifo but I have yet to confirm it.
This commit is contained in:
Dustin Richmond
parent
e11eb70853
commit
5058a758fc
@ -85,18 +85,15 @@
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`timescale 1ns/1ns
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`include "trellis.vh" // Defines the user-facing signal widths.
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module tx_alignment_pipeline
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#(
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parameter C_PIPELINE_OUTPUT = 1,
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#(parameter C_PIPELINE_OUTPUT = 1,
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parameter C_PIPELINE_DATA_INPUT = 1,
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parameter C_PIPELINE_HDR_INPUT = 1,
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parameter C_USE_COMPUTE_REG = 1,
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parameter C_USE_READY_REG = 1,
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parameter C_DATA_WIDTH = 128,
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parameter C_MAX_HDR_WIDTH = 128,
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parameter C_VENDOR = "ALTERA"
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)
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(
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// Interface: Clocks
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parameter C_VENDOR = "ALTERA")
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(// Interface: Clocks
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input CLK,
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// Interface: Reset
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@ -126,8 +123,7 @@ module tx_alignment_pipeline
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output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_START_OFFSET,
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output TX_PKT_END_FLAG,
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output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_END_OFFSET,
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output TX_PKT_VALID
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);
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output TX_PKT_VALID);
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localparam C_OFFSET_WIDTH = clog2s(C_DATA_WIDTH/32);
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localparam C_AGGREGATE_WIDTH = (C_DATA_WIDTH+C_MAX_HDR_WIDTH);
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@ -182,6 +178,7 @@ module tx_alignment_pipeline
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wire [32*C_MUX_INPUTS-1:0] wTxMuxInputs[C_NUM_MUXES-1:0];
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wire [(C_CLOG_MUX_INPUTS*C_NUM_MUXES)-1:0] wTxMuxSelect,_wTxMuxSelect;
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wire [C_NUM_MUXES-1:0] wTxMuxSelectDataReady,_wTxMuxSelectDataReady;
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wire [C_NUM_MUXES-1:0] wTxMuxSelectDataReadyAndPayload,_wTxMuxSelectDataReadyAndPayload;
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wire wTxMuxSelectDataEndFlag,_wTxMuxSelectDataEndFlag;
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wire wTxMuxSelectDataStartFlag,_wTxMuxSelectDataStartFlag;
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wire wTxMuxSelectPktStartFlag,_wTxMuxSelectPktStartFlag;
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@ -234,6 +231,10 @@ module tx_alignment_pipeline
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assign wReadyMux[3] = _wTxHdrStartEndReady;
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assign _wTxMuxSelectValid = _wTxHdrValid;
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assign _wTxMuxSelectDataReady = wReadyMux[wReadyMuxSelect] & {C_NUM_MUXES{(wPktCtr >= _wTxHdrNonpayLen[`SIG_NONPAY_W-1:clog2s(C_NUM_MUXES)])}};
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assign _wTxMuxSelectDataReadyAndPayload = wReadyMux[wReadyMuxSelect] &
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{C_NUM_MUXES{(wPktCtr >= _wTxHdrNonpayLen[`SIG_NONPAY_W-1:clog2s(C_NUM_MUXES)])}} &
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{C_NUM_MUXES{~_wTxHdrNoPayload}} &
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{C_NUM_MUXES{_wTxHdrValid}};
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assign _wTxMuxSelectPktStartFlag = wPktCtr == 0;
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assign _wTxMuxSelectDataStartFlag = wPktCtr == _wTxHdrNonpayLen[`SIG_NONPAY_W-1:clog2s(C_NUM_MUXES)];
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assign _wTxMuxSelectDataEndFlag = ({wPktCtr,{clog2s(C_NUM_MUXES){1'b0}}} + C_NUM_MUXES) >= _wTxHdrPacketLen;// TODO: Simplify
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@ -247,7 +248,8 @@ module tx_alignment_pipeline
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assign wTxPktEndFlag = wTxMuxSelectDataEndFlag;
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assign wTxPktEndOffset = wTxHdrPacketLen[C_OFFSET_WIDTH-1:0]-1; // TODO: Retime -1?
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assign wTxPktValid = wTxMuxSelectValid & (wTxHdrNoPayload | (~wTxHdrNoPayload & wTxDataPacketValid));
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assign wTxDataWordReady = wTxMuxSelectDataReady & {C_NUM_MUXES{wTxPktReady & wTxMuxSelectValid & wTxDataPacketValid & ~wTxHdrNoPayload}};
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// assign wTxDataWordReady = wTxMuxSelectDataReady & {C_NUM_MUXES{wTxPktReady & wTxMuxSelectValid & wTxDataPacketValid}};
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assign wTxDataWordReady = wTxMuxSelectDataReadyAndPayload & {C_NUM_MUXES{wTxPktReady & wTxDataPacketValid}};
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// Assignments for the output stage
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assign TX_PKT_START_OFFSET = {C_OFFSET_WIDTH{1'b0}};
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@ -292,8 +294,7 @@ module tx_alignment_pipeline
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.C_WIDTH (C_NUM_MUXES)
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/*AUTOINSTPARAM*/)
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rot_inst
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(
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// Outputs
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(// Outputs
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.RD_DATA (__wTxHdrEndReady),
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// Inputs
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.WR_DATA (__wTxHdrPacketMask),
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@ -301,15 +302,13 @@ module tx_alignment_pipeline
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/*AUTOINST*/);
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pipeline
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#(
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// Parameters
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#(// Parameters
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.C_DEPTH (C_PIPELINE_HDR_INPUT?1:0),
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.C_WIDTH (C_MAX_HDR_WIDTH + `SIG_NONPAY_W + `SIG_PACKETLEN_W + `SIG_LEN_W + 1),
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.C_USE_MEMORY (0)
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/*AUTOINSTPARAM*/)
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hdr_input_reg
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(
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// Outputs
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(// Outputs
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.WR_DATA_READY (TX_HDR_READY),
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.RD_DATA ({__wTxHdr,__wTxHdrNonpayLen,__wTxHdrPacketLen,__wTxHdrPayloadLen,__wTxHdrNoPayload}),
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.RD_DATA_VALID (__wTxHdrValid),
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@ -323,15 +322,13 @@ module tx_alignment_pipeline
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.RST_IN (RST_IN));
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pipeline
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#(
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// Parameters
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#(// Parameters
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.C_DEPTH (C_USE_COMPUTE_REG?1:0),
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.C_WIDTH (C_MAX_HDR_WIDTH + `SIG_NONPAY_W + `SIG_PACKETLEN_W + `SIG_LEN_W + 1 + 4*C_MASK_WIDTH),
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.C_USE_MEMORY (0)
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/*AUTOINSTPARAM*/)
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compute_reg
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(
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// Outputs
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(// Outputs
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.WR_DATA_READY (__wTxHdrReady),
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.RD_DATA ({_wTxHdr,_wTxHdrNonpayLen,_wTxHdrPacketLen,_wTxHdrPayloadLen,_wTxHdrNoPayload,
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_wTxHdrSteadyStateReady,_wTxHdrStartReady,_wTxHdrEndReady,_wTxHdrStartEndReady}),
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@ -347,15 +344,13 @@ module tx_alignment_pipeline
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.RST_IN (RST_IN));
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pipeline
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#(
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// Parameters
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#(// Parameters
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.C_DEPTH (C_USE_READY_REG?1:0),
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.C_WIDTH (C_MAX_HDR_WIDTH + `SIG_NONPAY_W + `SIG_PACKETLEN_W + `SIG_LEN_W + 1),
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.C_USE_MEMORY (0)
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/*AUTOINSTPARAM*/)
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ready_reg
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(
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// Outputs
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(// Outputs
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.WR_DATA_READY (_wTxHdrReady),
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.RD_DATA ({wTxHdr,wTxHdrNonpayLen,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNoPayload}),
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.RD_DATA_VALID (wTxHdrValid),
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@ -369,20 +364,24 @@ module tx_alignment_pipeline
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.RST_IN (RST_IN));
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pipeline
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#(
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// Parameters
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#(// Parameters
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.C_DEPTH (C_USE_READY_REG?1:0),
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.C_WIDTH (C_NUM_MUXES + C_CLOG_MUX_INPUTS * C_NUM_MUXES + 3),
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.C_WIDTH (2*C_NUM_MUXES + C_CLOG_MUX_INPUTS * C_NUM_MUXES + 3),
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.C_USE_MEMORY (0)
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/*AUTOINSTPARAM*/)
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select_reg
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(
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// Outputs
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(// Outputs
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.WR_DATA_READY (_wTxMuxSelectReady),
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.RD_DATA ({wTxMuxSelectDataReady,wTxMuxSelect,wTxMuxSelectDataEndFlag,wTxMuxSelectDataStartFlag,wTxMuxSelectPktStartFlag}),
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.RD_DATA ({wTxMuxSelectDataReady,wTxMuxSelect,
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wTxMuxSelectDataEndFlag,wTxMuxSelectDataStartFlag,
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wTxMuxSelectPktStartFlag,
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wTxMuxSelectDataReadyAndPayload}),
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.RD_DATA_VALID (wTxMuxSelectValid),
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// Inputs
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.WR_DATA ({_wTxMuxSelectDataReady,_wTxMuxSelect,_wTxMuxSelectDataEndFlag,_wTxMuxSelectDataStartFlag,_wTxMuxSelectPktStartFlag}),
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.WR_DATA ({_wTxMuxSelectDataReady,_wTxMuxSelect,
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_wTxMuxSelectDataEndFlag,_wTxMuxSelectDataStartFlag,
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_wTxMuxSelectPktStartFlag,
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_wTxMuxSelectDataReadyAndPayload}),
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.WR_DATA_VALID (_wTxMuxSelectValid),
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.RD_DATA_READY (wTxMuxSelectReady),
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/*AUTOINST*/
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@ -400,10 +399,11 @@ module tx_alignment_pipeline
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(// Outputs
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.VALUE (wSatCtr),
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// Inputs
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.CLK (CLK),
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.RST_IN (wSatCtrReset),
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.ENABLE (wSatCtrEnable)
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/*AUTOINST*/);
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.ENABLE (wSatCtrEnable),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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counter
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#(// Parameters
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@ -415,10 +415,11 @@ module tx_alignment_pipeline
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(// Outputs
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.VALUE (wPktCtr),
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// Inputs
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.CLK (CLK),
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.RST_IN (wPktCtrReset),
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.ENABLE (wPktCtrEnable)
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/*AUTOINST*/);
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.ENABLE (wPktCtrEnable),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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generate
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for( i = 0 ; i < C_MAX_HDR_WIDTH/32 ; i = i + 1) begin : gen_aggregate
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@ -473,16 +474,14 @@ module tx_alignment_pipeline
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for( i = 0 ; i < C_NUM_MUXES ; i = i + 1) begin : gen_packet_format_multiplexers
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mux
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#(
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// Parameters
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#(// Parameters
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.C_NUM_INPUTS (C_MUX_INPUTS),
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.C_CLOG_NUM_INPUTS (C_CLOG_MUX_INPUTS),
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.C_WIDTH (32),
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.C_MUX_TYPE ("SELECT")
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/*AUTOINSTPARAM*/)
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dw_mux_
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(
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// Outputs
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(// Outputs
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.MUX_OUTPUT (wTxPkt[32*i +: 32]),
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// Inputs
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.MUX_INPUTS (wTxMuxInputs[i]),
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@ -492,15 +491,13 @@ module tx_alignment_pipeline
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endgenerate
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pipeline
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#(
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// Parameters
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#(// Parameters
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.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
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.C_WIDTH (C_DATA_WIDTH + 2 + C_OFFSET_WIDTH),
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.C_USE_MEMORY (0)
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/*AUTOINSTPARAM*/)
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output_register_inst
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(
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// Outputs
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(// Outputs
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.WR_DATA_READY (wTxPktReady),
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.RD_DATA ({TX_PKT,TX_PKT_START_FLAG,TX_PKT_END_FLAG,TX_PKT_END_OFFSET}),
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.RD_DATA_VALID (TX_PKT_VALID),
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