FPGA/riffa
1
0
Fork 0
mirror of https://github.com/KastnerRG/riffa.git synced 2025-01-30 23:02:54 +08:00
Code Issues Projects Releases Wiki Activity

Replaced RST_IN with RST_BUS and RST_LOGIC and addded DONE_RST in top level engine layer files.

Browse Source 
Still need to propagate the changes and hook the resets up in the formatters,
multiplexers, etc. RST_BUS will be the equivalent of a PCIe PERST Pin reset, a
general inelegant reset where formatting is disregarded. RST_LOGIC is a reset
caused by application or higher level logic, where formatting needs to be
considered so that the bus does not lock up. DONE_RST will signal that the
engine layer has finished resetting, and is ready to transmit data.
This commit is contained in:
Dustin Richmond 2015-07-16 12:07:04 -07:00
parent 744953c2ad
commit 5ee3747243
15 changed files with 918 additions and 875 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
fpga/riffa_hdl/engine_layer.v
View File

@ -43,20 +43,19 @@
`include "trellis.vh" `include "trellis.vh"
`include "ultrascale.vh" `include "ultrascale.vh"
module engine_layer module engine_layer
#( #(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PCI_DATA_WIDTH = 128,
parameter C_LOG_NUM_TAGS=6, parameter C_LOG_NUM_TAGS=6,
parameter C_PIPELINE_INPUT = 1, parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0, parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64, parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_VENDOR="ULTRASCALE" parameter C_VENDOR="ULTRASCALE")
) (// Interface: Clocks
( input CLK_BUS, // Replacement for generic CLK
// Interface: Clocks
input CLK,
// Interface: Resets // Interface: Resets
input RST_IN, input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
// Interface: Configuration // Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID, input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
@ -196,9 +195,12 @@ module engine_layer
input [`SIG_TYPE_W-1:0] TXR_META_TYPE, input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
input TXR_META_EP, input TXR_META_EP,
output TXR_META_READY, output TXR_META_READY,
output TXR_SENT output TXR_SENT);
);
wire CLK;
assign CLK = CLK_BUS;
generate generate
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
if(C_VENDOR != "ULTRASCALE") begin if(C_VENDOR != "ULTRASCALE") begin
@ -226,6 +228,7 @@ module engine_layer
rx_engine_classic_inst rx_engine_classic_inst
(/*AUTOINST*/ (/*AUTOINST*/
// Outputs // Outputs
.DONE_RST (DONE_RST),
.RX_TLP_READY (RX_TLP_READY), .RX_TLP_READY (RX_TLP_READY),
.RXC_DATA (RXC_DATA[C_PCI_DATA_WIDTH-1:0]), .RXC_DATA (RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_VALID (RXC_DATA_VALID), .RXC_DATA_VALID (RXC_DATA_VALID),
@ -263,7 +266,8 @@ module engine_layer
.RXR_META_EP (RXR_META_EP), .RXR_META_EP (RXR_META_EP),
// Inputs // Inputs
.CLK (CLK), .CLK (CLK),
.RST_IN (RST_IN), .RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.RX_TLP (RX_TLP[C_PCI_DATA_WIDTH-1:0]), .RX_TLP (RX_TLP[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (RX_TLP_VALID), .RX_TLP_VALID (RX_TLP_VALID),
.RX_TLP_START_FLAG (RX_TLP_START_FLAG), .RX_TLP_START_FLAG (RX_TLP_START_FLAG),
@ -283,6 +287,7 @@ module engine_layer
tx_engine_classic_inst tx_engine_classic_inst
(/*AUTOINST*/ (/*AUTOINST*/
// Outputs // Outputs
.DONE_RST (DONE_RST),
.TX_TLP (TX_TLP[C_PCI_DATA_WIDTH-1:0]), .TX_TLP (TX_TLP[C_PCI_DATA_WIDTH-1:0]),
.TX_TLP_VALID (TX_TLP_VALID), .TX_TLP_VALID (TX_TLP_VALID),
.TX_TLP_START_FLAG (TX_TLP_START_FLAG), .TX_TLP_START_FLAG (TX_TLP_START_FLAG),
@ -297,7 +302,8 @@ module engine_layer
.TXR_SENT (TXR_SENT), .TXR_SENT (TXR_SENT),
// Inputs // Inputs
.CLK (CLK), .CLK (CLK),
.RST_IN (RST_IN), .RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]), .CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TX_TLP_READY (TX_TLP_READY), .TX_TLP_READY (TX_TLP_READY),
.TXC_DATA_VALID (TXC_DATA_VALID), .TXC_DATA_VALID (TXC_DATA_VALID),
@ -333,7 +339,8 @@ module engine_layer
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]), .TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]), .TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]), .TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP)); .TXR_META_EP (TXR_META_EP),
.RST_IN (RST_IN));
end else begin end else begin
@ -351,6 +358,7 @@ module engine_layer
rx_engine_ultrascale_inst rx_engine_ultrascale_inst
(/*AUTOINST*/ (/*AUTOINST*/
// Outputs // Outputs
.DONE_RST (DONE_RST),
.M_AXIS_CQ_TREADY (M_AXIS_CQ_TREADY), .M_AXIS_CQ_TREADY (M_AXIS_CQ_TREADY),
.M_AXIS_RC_TREADY (M_AXIS_RC_TREADY), .M_AXIS_RC_TREADY (M_AXIS_RC_TREADY),
.RXC_DATA (RXC_DATA[C_PCI_DATA_WIDTH-1:0]), .RXC_DATA (RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
@ -389,7 +397,8 @@ module engine_layer
.RXR_META_EP (RXR_META_EP), .RXR_META_EP (RXR_META_EP),
// Inputs // Inputs
.CLK (CLK), .CLK (CLK),
.RST_IN (RST_IN), .RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.M_AXIS_CQ_TVALID (M_AXIS_CQ_TVALID), .M_AXIS_CQ_TVALID (M_AXIS_CQ_TVALID),
.M_AXIS_CQ_TLAST (M_AXIS_CQ_TLAST), .M_AXIS_CQ_TLAST (M_AXIS_CQ_TLAST),
.M_AXIS_CQ_TDATA (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]), .M_AXIS_CQ_TDATA (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
@ -411,6 +420,7 @@ module engine_layer
tx_engine_ultrascale_inst tx_engine_ultrascale_inst
(/*AUTOINST*/ (/*AUTOINST*/
// Outputs // Outputs
.DONE_RST (DONE_RST),
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID), .S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST), .S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]), .S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
@ -429,7 +439,8 @@ module engine_layer
.TXR_SENT (TXR_SENT), .TXR_SENT (TXR_SENT),
// Inputs // Inputs
.CLK (CLK), .CLK (CLK),
.RST_IN (RST_IN), .RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]), .CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY), .S_AXIS_CC_TREADY (S_AXIS_CC_TREADY),
.TXC_DATA_VALID (TXC_DATA_VALID), .TXC_DATA_VALID (TXC_DATA_VALID),

26
fpga/riffa_hdl/rx_engine_classic.v
View File

@ -48,14 +48,14 @@
module rx_engine_classic module rx_engine_classic
#(parameter C_VENDOR = "ALTERA", #(parameter C_VENDOR = "ALTERA",
parameter C_PCI_DATA_WIDTH = 128, parameter C_PCI_DATA_WIDTH = 128,
parameter C_LOG_NUM_TAGS=6 parameter C_LOG_NUM_TAGS=6)
) (// Interface: Clocks
(
// Interface: Clocks
input CLK, input CLK,
// Interface: Resets // Interface: Resets
input RST_IN, input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
// Interface: RX Classic // Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP, input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
@ -276,6 +276,7 @@ module rx_engine_classic
.RXR_DATA (_RXR_DATA[C_PCI_DATA_WIDTH-1:0]), .RXR_DATA (_RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.DONE_RST (DONE_RST),
.RXR_DATA_VALID (RXR_DATA_VALID), .RXR_DATA_VALID (RXR_DATA_VALID),
.RXR_DATA_WORD_ENABLE (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_WORD_ENABLE (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG), .RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
@ -295,7 +296,8 @@ module rx_engine_classic
.RXR_META_EP (RXR_META_EP), .RXR_META_EP (RXR_META_EP),
// Inputs // Inputs
.CLK (CLK), .CLK (CLK),
.RST_IN (RST_IN), .RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.RX_TLP (RX_TLP[C_PCI_DATA_WIDTH-1:0]), .RX_TLP (RX_TLP[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (RX_TLP_VALID), .RX_TLP_VALID (RX_TLP_VALID),
.RX_TLP_START_FLAG (RX_TLP_START_FLAG), .RX_TLP_START_FLAG (RX_TLP_START_FLAG),
@ -322,6 +324,7 @@ module rx_engine_classic
.RXC_DATA (_RXC_DATA[C_PCI_DATA_WIDTH-1:0]), .RXC_DATA (_RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.DONE_RST (DONE_RST),
.RXC_DATA_VALID (RXC_DATA_VALID), .RXC_DATA_VALID (RXC_DATA_VALID),
.RXC_DATA_WORD_ENABLE (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_WORD_ENABLE (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_START_FLAG (RXC_DATA_START_FLAG), .RXC_DATA_START_FLAG (RXC_DATA_START_FLAG),
@ -339,7 +342,8 @@ module rx_engine_classic
.RXC_META_EP (RXC_META_EP), .RXC_META_EP (RXC_META_EP),
// Inputs // Inputs
.CLK (CLK), .CLK (CLK),
.RST_IN (RST_IN), .RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.RX_TLP (RX_TLP[C_PCI_DATA_WIDTH-1:0]), .RX_TLP (RX_TLP[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (RX_TLP_VALID), .RX_TLP_VALID (RX_TLP_VALID),
.RX_TLP_START_FLAG (RX_TLP_START_FLAG), .RX_TLP_START_FLAG (RX_TLP_START_FLAG),
@ -366,6 +370,7 @@ module rx_engine_classic
.RXR_DATA (_RXR_DATA[C_PCI_DATA_WIDTH-1:0]), .RXR_DATA (_RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.DONE_RST (DONE_RST),
.RXR_DATA_VALID (RXR_DATA_VALID), .RXR_DATA_VALID (RXR_DATA_VALID),
.RXR_DATA_WORD_ENABLE (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_WORD_ENABLE (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG), .RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
@ -385,7 +390,8 @@ module rx_engine_classic
.RXR_META_EP (RXR_META_EP), .RXR_META_EP (RXR_META_EP),
// Inputs // Inputs
.CLK (CLK), .CLK (CLK),
.RST_IN (RST_IN), .RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.RX_TLP (RX_TLP[C_PCI_DATA_WIDTH-1:0]), .RX_TLP (RX_TLP[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (RX_TLP_VALID), .RX_TLP_VALID (RX_TLP_VALID),
.RX_TLP_START_FLAG (RX_TLP_START_FLAG), .RX_TLP_START_FLAG (RX_TLP_START_FLAG),
@ -412,6 +418,7 @@ module rx_engine_classic
.RXC_DATA (_RXC_DATA[C_PCI_DATA_WIDTH-1:0]), .RXC_DATA (_RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.DONE_RST (DONE_RST),
.RXC_DATA_VALID (RXC_DATA_VALID), .RXC_DATA_VALID (RXC_DATA_VALID),
.RXC_DATA_WORD_ENABLE (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_WORD_ENABLE (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_START_FLAG (RXC_DATA_START_FLAG), .RXC_DATA_START_FLAG (RXC_DATA_START_FLAG),
@ -429,7 +436,8 @@ module rx_engine_classic
.RXC_META_EP (RXC_META_EP), .RXC_META_EP (RXC_META_EP),
// Inputs // Inputs
.CLK (CLK), .CLK (CLK),
.RST_IN (RST_IN), .RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.RX_TLP (RX_TLP[C_PCI_DATA_WIDTH-1:0]), .RX_TLP (RX_TLP[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (RX_TLP_VALID), .RX_TLP_VALID (RX_TLP_VALID),
.RX_TLP_START_FLAG (RX_TLP_START_FLAG), .RX_TLP_START_FLAG (RX_TLP_START_FLAG),

20
fpga/riffa_hdl/rx_engine_ultrascale.v
View File

@ -46,14 +46,14 @@
`include "ultrascale.vh" `include "ultrascale.vh"
`include "trellis.vh" `include "trellis.vh"
module rx_engine_ultrascale module rx_engine_ultrascale
#(parameter C_PCI_DATA_WIDTH = 128 #(parameter C_PCI_DATA_WIDTH = 128)
) (// Interface: Clocks
( input CLK, // Replacement for generic CLK
// Interface: Clocks
input CLK,
// Interface: Resets // Interface: Resets
input RST_IN, input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
// Interface: CQ // Interface: CQ
input M_AXIS_CQ_TVALID, input M_AXIS_CQ_TVALID,
@ -122,6 +122,7 @@ module rx_engine_ultrascale
rxc_engine_inst rxc_engine_inst
(/*AUTOINST*/ (/*AUTOINST*/
// Outputs // Outputs
.DONE_RST (DONE_RST),
.M_AXIS_RC_TREADY (M_AXIS_RC_TREADY), .M_AXIS_RC_TREADY (M_AXIS_RC_TREADY),
.RXC_DATA (RXC_DATA[C_PCI_DATA_WIDTH-1:0]), .RXC_DATA (RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_VALID (RXC_DATA_VALID), .RXC_DATA_VALID (RXC_DATA_VALID),
@ -141,7 +142,8 @@ module rx_engine_ultrascale
.RXC_META_EP (RXC_META_EP), .RXC_META_EP (RXC_META_EP),
// Inputs // Inputs
.CLK (CLK), .CLK (CLK),
.RST_IN (RST_IN), .RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.M_AXIS_RC_TVALID (M_AXIS_RC_TVALID), .M_AXIS_RC_TVALID (M_AXIS_RC_TVALID),
.M_AXIS_RC_TLAST (M_AXIS_RC_TLAST), .M_AXIS_RC_TLAST (M_AXIS_RC_TLAST),
.M_AXIS_RC_TDATA (M_AXIS_RC_TDATA[C_PCI_DATA_WIDTH-1:0]), .M_AXIS_RC_TDATA (M_AXIS_RC_TDATA[C_PCI_DATA_WIDTH-1:0]),
@ -156,6 +158,7 @@ module rx_engine_ultrascale
rxr_engine_inst rxr_engine_inst
(/*AUTOINST*/ (/*AUTOINST*/
// Outputs // Outputs
.DONE_RST (DONE_RST),
.M_AXIS_CQ_TREADY (M_AXIS_CQ_TREADY), .M_AXIS_CQ_TREADY (M_AXIS_CQ_TREADY),
.RXR_DATA (RXR_DATA[C_PCI_DATA_WIDTH-1:0]), .RXR_DATA (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (RXR_DATA_VALID), .RXR_DATA_VALID (RXR_DATA_VALID),
@ -177,7 +180,8 @@ module rx_engine_ultrascale
.RXR_META_EP (RXR_META_EP), .RXR_META_EP (RXR_META_EP),
// Inputs // Inputs
.CLK (CLK), .CLK (CLK),
.RST_IN (RST_IN), .RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.M_AXIS_CQ_TVALID (M_AXIS_CQ_TVALID), .M_AXIS_CQ_TVALID (M_AXIS_CQ_TVALID),
.M_AXIS_CQ_TLAST (M_AXIS_CQ_TLAST), .M_AXIS_CQ_TLAST (M_AXIS_CQ_TLAST),
.M_AXIS_CQ_TDATA (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]), .M_AXIS_CQ_TDATA (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]),

346
fpga/riffa_hdl/rxc_engine_128.v Normal file
View File

@ -0,0 +1,346 @@
`include "trellis.vh"
`include "tlp.vh"
module rxc_engine_128
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
input RX_TLP_VALID,
input RX_TLP_START_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
input RX_TLP_END_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
// Interface: RXC Engine
output [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
output RXC_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
output RXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
output RXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
output [`SIG_LBE_W-1:0] RXC_META_LDWBE,
output [`SIG_FBE_W-1:0] RXC_META_FDWBE,
output [`SIG_TAG_W-1:0] RXC_META_TAG,
output [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
output [`SIG_TYPE_W-1:0] RXC_META_TYPE,
output [`SIG_LEN_W-1:0] RXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
output [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
output RXC_META_EP,
// Interface: RX Shift Register
input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_START_OFFSET,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID
);
/*AUTOWIRE*/
///*AUTOOUTPUT*/
localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 1;
localparam C_RX_OUTPUT_STAGES = 1;
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_RX_HDR_STAGES = 1; // Specific to the Xilinx 128-bit RXC Engine
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES + C_RX_HDR_STAGES;
localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
localparam C_STRADDLE_W = 64;
localparam C_HDR_NOSTRADDLE_I = C_RX_INPUT_STAGES * C_PCI_DATA_WIDTH;
localparam C_OUTPUT_STAGE_WIDTH = (C_PCI_DATA_WIDTH/32) + 2 + clog2s(C_PCI_DATA_WIDTH/32) + 1 + `SIG_TAG_W + `SIG_TYPE_W + `SIG_LOWADDR_W + `SIG_REQID_W + `SIG_LEN_W + `SIG_BYTECNT_W;
// Header Reg Inputs
wire [`SIG_OFFSET_W-1:0] __wRxcStartOffset;
wire [`SIG_OFFSET_W-1:0] __wRxcStraddledStartOffset;
wire [`TLP_MAXHDR_W-1:0] __wRxcHdr;
wire [`TLP_MAXHDR_W-1:0] __wRxcHdrStraddled;
wire [`TLP_MAXHDR_W-1:0] __wRxcHdrNotStraddled;
wire __wRxcHdrStraddle;
wire __wRxcHdrValid;
wire __wRxcHdrSOP;
wire __wRxcHdrSOPStraddle;
// Header Reg Outputs
wire _wRxcHdrValid;
wire _wRxcHdrStraddle;
wire _wRxcHdrSOPStraddle;
wire _wRxcHdrSOP;
wire [`TLP_MAXHDR_W-1:0] _wRxcHdr;
wire _wRxcHdrSF;
wire [2:0] _wRxcHdrDataSoff;
wire _wRxcHdrEF;
wire [1:0] _wRxcHdrDataEoff;
wire _wRxcHdrSCP; // Single Cycle Packet
wire _wRxcHdrMCP; // Multi Cycle Packet
wire _wRxcHdrRegSF;
wire _wRxcHdrRegValid;
wire _wRxcHdrStartFlag;
wire _wRxcHdr3DWHSF;
wire [3:0] _wRxcHdrStartMask;
wire [3:0] _wRxcHdrEndMask;
// Header Reg Outputs
wire [`TLP_MAXHDR_W-1:0] wRxcHdr;
wire wRxcHdrSF;
wire wRxcHdrEF;
wire wRxcHdrValid;
wire [63:0] wRxcMetadata;
wire [`TLP_TYPE_W-1:0] wRxcType;
wire [`TLP_LEN_W-1:0] wRxcLength;
wire [2:0] wRxcHdrLength;// TODO:
wire [`SIG_OFFSET_W-1:0] wRxcHdrStartOffset;// TODO:
wire wRxcHdrSCP; // Single Cycle Packet
wire wRxcHdrMCP; // Multi Cycle Packet
wire [1:0] wRxcHdrDataSoff;
wire [3:0] wRxcHdrStartMask;
wire [3:0] wRxcHdrEndMask;
// Output Register Inputs
wire [C_PCI_DATA_WIDTH-1:0] wRxcData;
wire wRxcDataValid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataWordEnable;
wire wRxcDataStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataStartOffset;
wire wRxcDataEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataEndOffset;
wire [`SIG_TAG_W-1:0] wRxcMetaTag;
wire [`SIG_TYPE_W-1:0] wRxcMetaType;
wire [`SIG_LOWADDR_W-1:0] wRxcMetaAddr;
wire [`SIG_REQID_W-1:0] wRxcMetaCompleterId;
wire [`SIG_LEN_W-1:0] wRxcMetaLength;
wire wRxcMetaEP;
wire [`SIG_BYTECNT_W-1:0] wRxcMetaBytesRemaining;
reg rStraddledSOP;
reg rStraddledSOPSplit;
// ----- Header Register -----
assign __wRxcHdrSOP = RX_SR_SOP[C_RX_INPUT_STAGES] & ~__wRxcStartOffset[1];
assign __wRxcHdrSOPStraddle = RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxcStraddledStartOffset[1];
assign __wRxcHdrNotStraddled = RX_SR_DATA[C_HDR_NOSTRADDLE_I +: C_PCI_DATA_WIDTH];
assign __wRxcHdrStraddled = {RX_SR_DATA[C_RX_INPUT_STAGES*C_PCI_DATA_WIDTH +: C_STRADDLE_W],
RX_SR_DATA[(C_RX_INPUT_STAGES+1)*C_PCI_DATA_WIDTH + C_STRADDLE_W +: C_STRADDLE_W ]};
assign __wRxcStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*C_RX_INPUT_STAGES +: `SIG_OFFSET_W];
assign __wRxcStraddledStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*(C_RX_INPUT_STAGES) +: `SIG_OFFSET_W];
assign __wRxcHdrValid = __wRxcHdrSOP | ((rStraddledSOP | rStraddledSOPSplit) & RX_SR_VALID[C_RX_INPUT_STAGES]);
assign _wRxcHdrRegSF = RX_SR_SOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES] & _wRxcHdrValid;
assign _wRxcHdrDataSoff = {1'b0,_wRxcHdrSOPStraddle,1'b0} + 3'd3;
assign _wRxcHdrRegValid = RX_SR_VALID[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
assign _wRxcHdr3DWHSF = ~_wRxcHdr[`TLP_4DWHBIT_I] & _wRxcHdrSOP;
assign _wRxcHdrSF = (_wRxcHdr3DWHSF | _wRxcHdrSOPStraddle);
assign _wRxcHdrEF = RX_SR_EOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
assign _wRxcHdrDataEoff = RX_SR_END_OFFSET[(C_RX_INPUT_STAGES+C_RX_HDR_STAGES)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
assign _wRxcHdrSCP = _wRxcHdrSF & _wRxcHdrEF & (_wRxcHdr[`TLP_TYPE_R] == `TLP_TYPE_CPL);
assign _wRxcHdrMCP = (_wRxcHdrSF & ~_wRxcHdrEF & (_wRxcHdr[`TLP_TYPE_R] == `TLP_TYPE_CPL)) |
(wRxcHdrMCP & ~wRxcHdrEF);
assign _wRxcHdrStartMask = 4'hf << (_wRxcHdrSF ? _wRxcHdrDataSoff[1:0] : 0);
assign wRxcDataWordEnable = wRxcHdrEndMask & wRxcHdrStartMask & {4{wRxcDataValid}};
assign wRxcDataValid = wRxcHdrSCP | wRxcHdrMCP;
assign wRxcDataStartFlag = wRxcHdrSF;
assign wRxcDataEndFlag = wRxcHdrEF;
assign wRxcDataStartOffset = wRxcHdrDataSoff;
assign wRxcMetaBytesRemaining = wRxcHdr[`TLP_CPLBYTECNT_R];
assign wRxcMetaTag = wRxcHdr[`TLP_CPLTAG_R];
assign wRxcMetaAddr = wRxcHdr[`TLP_CPLADDR_R];
assign wRxcMetaCompleterId = wRxcHdr[`TLP_REQREQID_R];
assign wRxcMetaLength = wRxcHdr[`TLP_LEN_R];
assign wRxcMetaEP = wRxcHdr[`TLP_EP_R];
assign wRxcMetaType = tlp_to_trellis_type({wRxcHdr[`TLP_FMT_R],wRxcHdr[`TLP_TYPE_R]});
assign RXC_DATA = RX_SR_DATA[C_PCI_DATA_WIDTH*C_TOTAL_STAGES +: C_PCI_DATA_WIDTH];
assign RXC_DATA_END_OFFSET = RX_SR_END_OFFSET[`SIG_OFFSET_W*(C_TOTAL_STAGES) +: C_OFFSET_WIDTH];
always @(posedge CLK) begin
rStraddledSOP <= RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxcStraddledStartOffset[1];
// Set Straddled SOP Split when there is a straddled packet where the
// header is not contiguous. (Not sure if this is ever possible, but
// better safe than sorry assert Straddled SOP Split. See Virtex 6 PCIe
// errata.)
if(__wRxcHdrSOP | RST_IN) begin
rStraddledSOPSplit <=0;
end else begin
rStraddledSOPSplit <= (rStraddledSOP | rStraddledSOPSplit) & ~RX_SR_VALID[C_RX_INPUT_STAGES];
end
end
mux
#(
// Parameters
.C_NUM_INPUTS (2),
.C_CLOG_NUM_INPUTS (1),
.C_WIDTH (`TLP_MAXHDR_W),
.C_MUX_TYPE ("SELECT")
/*AUTOINSTPARAM*/)
hdr_mux
(
// Outputs
.MUX_OUTPUT (__wRxcHdr[`TLP_MAXHDR_W-1:0]),
// Inputs
.MUX_INPUTS ({__wRxcHdrStraddled[`TLP_MAXHDR_W-1:0],
__wRxcHdrNotStraddled[`TLP_MAXHDR_W-1:0]}),
.MUX_SELECT (rStraddledSOP | rStraddledSOPSplit)
/*AUTOINST*/);
register
#(
// Parameters
.C_WIDTH (64 + 1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
hdr_register_63_0
(
// Outputs
.RD_DATA ({_wRxcHdr[C_STRADDLE_W-1:0], _wRxcHdrValid}),
// Inputs
.WR_DATA ({__wRxcHdr[C_STRADDLE_W-1:0], __wRxcHdrValid}),
.WR_EN (__wRxcHdrSOP | rStraddledSOP),
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (64),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
hdr_register_127_64
(
// Outputs
.RD_DATA (_wRxcHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
// Inputs
.WR_DATA (__wRxcHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
.WR_EN (__wRxcHdrSOP | rStraddledSOP | rStraddledSOPSplit), // Non straddled start, Straddled, or straddled split
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (2),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
sf4dwh// TODO: Rename
(
// Outputs
.RD_DATA ({_wRxcHdrSOPStraddle,_wRxcHdrSOP}),
// Inputs
.WR_DATA ({rStraddledSOP,__wRxcHdrSOP}),
.WR_EN (1),
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
// ----- Computation Register -----
register
#(
// Parameters
.C_WIDTH (128 + 4),/* TODO: TLP_METADATA_W*/
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata
(// Output
.RD_DATA ({wRxcHdr,
wRxcHdrSF, wRxcHdrDataSoff,
wRxcHdrEF}),
// Inputs
.RST_IN (0),
.WR_DATA ({_wRxcHdr,
_wRxcHdrSF, _wRxcHdrDataSoff[1:0],
_wRxcHdrEF}),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (3+8),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_valid
(// Output
.RD_DATA ({wRxcHdrValid,
wRxcHdrSCP, wRxcHdrMCP,
wRxcHdrEndMask, wRxcHdrStartMask}),
// Inputs
.RST_IN (RST_IN),
.WR_DATA ({_wRxcHdrValid,
_wRxcHdrSCP, _wRxcHdrMCP,
_wRxcHdrEndMask, _wRxcHdrStartMask}), // Need to invert the start mask
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (4)
/*AUTOINSTPARAM*/)
o2m_ef
(
// Outputs
.MASK (_wRxcHdrEndMask),
// Inputs
.OFFSET_ENABLE (_wRxcHdrEF),
.OFFSET (_wRxcHdrDataEoff)
/*AUTOINST*/);
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (C_OUTPUT_STAGE_WIDTH),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(
// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({RXC_DATA_WORD_ENABLE, RXC_DATA_START_FLAG, RXC_DATA_START_OFFSET,
RXC_DATA_END_FLAG, RXC_META_TAG, RXC_META_TYPE,
RXC_META_ADDR, RXC_META_COMPLETER_ID, RXC_META_BYTES_REMAINING,
RXC_META_LENGTH, RXC_META_EP}),
.RD_DATA_VALID (RXC_DATA_VALID),
// Inputs
.WR_DATA ({wRxcDataWordEnable, wRxcDataStartFlag, wRxcDataStartOffset,
wRxcDataEndFlag, wRxcMetaTag, wRxcMetaType,
wRxcMetaAddr, wRxcMetaCompleterId, wRxcMetaBytesRemaining,
wRxcMetaLength, wRxcMetaEP}),
.WR_DATA_VALID (wRxcDataValid),
.RD_DATA_READY (1'b1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common")
// End:

351
fpga/riffa_hdl/rxc_engine_classic.v
View File

@ -47,14 +47,14 @@
module rxc_engine_classic module rxc_engine_classic
#(parameter C_VENDOR = "ALTERA", #(parameter C_VENDOR = "ALTERA",
parameter C_PCI_DATA_WIDTH = 128, parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH = 10 parameter C_RX_PIPELINE_DEPTH = 10)
) (// Interface: Clocks
(
// Interface: Clocks
input CLK, input CLK,
// Interface: Resets // Interface: Resets
input RST_IN, input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
// Interface: RX Classic // Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP, input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
@ -444,344 +444,3 @@ module rxc_engine_classic
.CLK (CLK)); .CLK (CLK));
endmodule endmodule
module rxc_engine_128
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
input RX_TLP_VALID,
input RX_TLP_START_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
input RX_TLP_END_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
// Interface: RXC Engine
output [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
output RXC_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
output RXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
output RXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
output [`SIG_LBE_W-1:0] RXC_META_LDWBE,
output [`SIG_FBE_W-1:0] RXC_META_FDWBE,
output [`SIG_TAG_W-1:0] RXC_META_TAG,
output [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
output [`SIG_TYPE_W-1:0] RXC_META_TYPE,
output [`SIG_LEN_W-1:0] RXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
output [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
output RXC_META_EP,
// Interface: RX Shift Register
input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_START_OFFSET,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID
);
/*AUTOWIRE*/
///*AUTOOUTPUT*/
localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 1;
localparam C_RX_OUTPUT_STAGES = 1;
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_RX_HDR_STAGES = 1; // Specific to the Xilinx 128-bit RXC Engine
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES + C_RX_HDR_STAGES;
localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
localparam C_STRADDLE_W = 64;
localparam C_HDR_NOSTRADDLE_I = C_RX_INPUT_STAGES * C_PCI_DATA_WIDTH;
localparam C_OUTPUT_STAGE_WIDTH = (C_PCI_DATA_WIDTH/32) + 2 + clog2s(C_PCI_DATA_WIDTH/32) + 1 + `SIG_TAG_W + `SIG_TYPE_W + `SIG_LOWADDR_W + `SIG_REQID_W + `SIG_LEN_W + `SIG_BYTECNT_W;
// Header Reg Inputs
wire [`SIG_OFFSET_W-1:0] __wRxcStartOffset;
wire [`SIG_OFFSET_W-1:0] __wRxcStraddledStartOffset;
wire [`TLP_MAXHDR_W-1:0] __wRxcHdr;
wire [`TLP_MAXHDR_W-1:0] __wRxcHdrStraddled;
wire [`TLP_MAXHDR_W-1:0] __wRxcHdrNotStraddled;
wire __wRxcHdrStraddle;
wire __wRxcHdrValid;
wire __wRxcHdrSOP;
wire __wRxcHdrSOPStraddle;
// Header Reg Outputs
wire _wRxcHdrValid;
wire _wRxcHdrStraddle;
wire _wRxcHdrSOPStraddle;
wire _wRxcHdrSOP;
wire [`TLP_MAXHDR_W-1:0] _wRxcHdr;
wire _wRxcHdrSF;
wire [2:0] _wRxcHdrDataSoff;
wire _wRxcHdrEF;
wire [1:0] _wRxcHdrDataEoff;
wire _wRxcHdrSCP; // Single Cycle Packet
wire _wRxcHdrMCP; // Multi Cycle Packet
wire _wRxcHdrRegSF;
wire _wRxcHdrRegValid;
wire _wRxcHdrStartFlag;
wire _wRxcHdr3DWHSF;
wire [3:0] _wRxcHdrStartMask;
wire [3:0] _wRxcHdrEndMask;
// Header Reg Outputs
wire [`TLP_MAXHDR_W-1:0] wRxcHdr;
wire wRxcHdrSF;
wire wRxcHdrEF;
wire wRxcHdrValid;
wire [63:0] wRxcMetadata;
wire [`TLP_TYPE_W-1:0] wRxcType;
wire [`TLP_LEN_W-1:0] wRxcLength;
wire [2:0] wRxcHdrLength;// TODO:
wire [`SIG_OFFSET_W-1:0] wRxcHdrStartOffset;// TODO:
wire wRxcHdrSCP; // Single Cycle Packet
wire wRxcHdrMCP; // Multi Cycle Packet
wire [1:0] wRxcHdrDataSoff;
wire [3:0] wRxcHdrStartMask;
wire [3:0] wRxcHdrEndMask;
// Output Register Inputs
wire [C_PCI_DATA_WIDTH-1:0] wRxcData;
wire wRxcDataValid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataWordEnable;
wire wRxcDataStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataStartOffset;
wire wRxcDataEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataEndOffset;
wire [`SIG_TAG_W-1:0] wRxcMetaTag;
wire [`SIG_TYPE_W-1:0] wRxcMetaType;
wire [`SIG_LOWADDR_W-1:0] wRxcMetaAddr;
wire [`SIG_REQID_W-1:0] wRxcMetaCompleterId;
wire [`SIG_LEN_W-1:0] wRxcMetaLength;
wire wRxcMetaEP;
wire [`SIG_BYTECNT_W-1:0] wRxcMetaBytesRemaining;
reg rStraddledSOP;
reg rStraddledSOPSplit;
// ----- Header Register -----
assign __wRxcHdrSOP = RX_SR_SOP[C_RX_INPUT_STAGES] & ~__wRxcStartOffset[1];
assign __wRxcHdrSOPStraddle = RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxcStraddledStartOffset[1];
assign __wRxcHdrNotStraddled = RX_SR_DATA[C_HDR_NOSTRADDLE_I +: C_PCI_DATA_WIDTH];
assign __wRxcHdrStraddled = {RX_SR_DATA[C_RX_INPUT_STAGES*C_PCI_DATA_WIDTH +: C_STRADDLE_W],
RX_SR_DATA[(C_RX_INPUT_STAGES+1)*C_PCI_DATA_WIDTH + C_STRADDLE_W +: C_STRADDLE_W ]};
assign __wRxcStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*C_RX_INPUT_STAGES +: `SIG_OFFSET_W];
assign __wRxcStraddledStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*(C_RX_INPUT_STAGES) +: `SIG_OFFSET_W];
assign __wRxcHdrValid = __wRxcHdrSOP | ((rStraddledSOP | rStraddledSOPSplit) & RX_SR_VALID[C_RX_INPUT_STAGES]);
assign _wRxcHdrRegSF = RX_SR_SOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES] & _wRxcHdrValid;
assign _wRxcHdrDataSoff = {1'b0,_wRxcHdrSOPStraddle,1'b0} + 3'd3;
assign _wRxcHdrRegValid = RX_SR_VALID[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
assign _wRxcHdr3DWHSF = ~_wRxcHdr[`TLP_4DWHBIT_I] & _wRxcHdrSOP;
assign _wRxcHdrSF = (_wRxcHdr3DWHSF | _wRxcHdrSOPStraddle);
assign _wRxcHdrEF = RX_SR_EOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
assign _wRxcHdrDataEoff = RX_SR_END_OFFSET[(C_RX_INPUT_STAGES+C_RX_HDR_STAGES)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
assign _wRxcHdrSCP = _wRxcHdrSF & _wRxcHdrEF & (_wRxcHdr[`TLP_TYPE_R] == `TLP_TYPE_CPL);
assign _wRxcHdrMCP = (_wRxcHdrSF & ~_wRxcHdrEF & (_wRxcHdr[`TLP_TYPE_R] == `TLP_TYPE_CPL)) |
(wRxcHdrMCP & ~wRxcHdrEF);
assign _wRxcHdrStartMask = 4'hf << (_wRxcHdrSF ? _wRxcHdrDataSoff[1:0] : 0);
assign wRxcDataWordEnable = wRxcHdrEndMask & wRxcHdrStartMask & {4{wRxcDataValid}};
assign wRxcDataValid = wRxcHdrSCP | wRxcHdrMCP;
assign wRxcDataStartFlag = wRxcHdrSF;
assign wRxcDataEndFlag = wRxcHdrEF;
assign wRxcDataStartOffset = wRxcHdrDataSoff;
assign wRxcMetaBytesRemaining = wRxcHdr[`TLP_CPLBYTECNT_R];
assign wRxcMetaTag = wRxcHdr[`TLP_CPLTAG_R];
assign wRxcMetaAddr = wRxcHdr[`TLP_CPLADDR_R];
assign wRxcMetaCompleterId = wRxcHdr[`TLP_REQREQID_R];
assign wRxcMetaLength = wRxcHdr[`TLP_LEN_R];
assign wRxcMetaEP = wRxcHdr[`TLP_EP_R];
assign wRxcMetaType = tlp_to_trellis_type({wRxcHdr[`TLP_FMT_R],wRxcHdr[`TLP_TYPE_R]});
assign RXC_DATA = RX_SR_DATA[C_PCI_DATA_WIDTH*C_TOTAL_STAGES +: C_PCI_DATA_WIDTH];
assign RXC_DATA_END_OFFSET = RX_SR_END_OFFSET[`SIG_OFFSET_W*(C_TOTAL_STAGES) +: C_OFFSET_WIDTH];
always @(posedge CLK) begin
rStraddledSOP <= RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxcStraddledStartOffset[1];
// Set Straddled SOP Split when there is a straddled packet where the
// header is not contiguous. (Not sure if this is ever possible, but
// better safe than sorry assert Straddled SOP Split. See Virtex 6 PCIe
// errata.)
if(__wRxcHdrSOP | RST_IN) begin
rStraddledSOPSplit <=0;
end else begin
rStraddledSOPSplit <= (rStraddledSOP | rStraddledSOPSplit) & ~RX_SR_VALID[C_RX_INPUT_STAGES];
end
end
mux
#(
// Parameters
.C_NUM_INPUTS (2),
.C_CLOG_NUM_INPUTS (1),
.C_WIDTH (`TLP_MAXHDR_W),
.C_MUX_TYPE ("SELECT")
/*AUTOINSTPARAM*/)
hdr_mux
(
// Outputs
.MUX_OUTPUT (__wRxcHdr[`TLP_MAXHDR_W-1:0]),
// Inputs
.MUX_INPUTS ({__wRxcHdrStraddled[`TLP_MAXHDR_W-1:0],
__wRxcHdrNotStraddled[`TLP_MAXHDR_W-1:0]}),
.MUX_SELECT (rStraddledSOP | rStraddledSOPSplit)
/*AUTOINST*/);
register
#(
// Parameters
.C_WIDTH (64 + 1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
hdr_register_63_0
(
// Outputs
.RD_DATA ({_wRxcHdr[C_STRADDLE_W-1:0], _wRxcHdrValid}),
// Inputs
.WR_DATA ({__wRxcHdr[C_STRADDLE_W-1:0], __wRxcHdrValid}),
.WR_EN (__wRxcHdrSOP | rStraddledSOP),
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (64),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
hdr_register_127_64
(
// Outputs
.RD_DATA (_wRxcHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
// Inputs
.WR_DATA (__wRxcHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
.WR_EN (__wRxcHdrSOP | rStraddledSOP | rStraddledSOPSplit), // Non straddled start, Straddled, or straddled split
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (2),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
sf4dwh// TODO: Rename
(
// Outputs
.RD_DATA ({_wRxcHdrSOPStraddle,_wRxcHdrSOP}),
// Inputs
.WR_DATA ({rStraddledSOP,__wRxcHdrSOP}),
.WR_EN (1),
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
// ----- Computation Register -----
register
#(
// Parameters
.C_WIDTH (128 + 4),/* TODO: TLP_METADATA_W*/
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata
(// Output
.RD_DATA ({wRxcHdr,
wRxcHdrSF, wRxcHdrDataSoff,
wRxcHdrEF}),
// Inputs
.RST_IN (0),
.WR_DATA ({_wRxcHdr,
_wRxcHdrSF, _wRxcHdrDataSoff[1:0],
_wRxcHdrEF}),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (3+8),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_valid
(// Output
.RD_DATA ({wRxcHdrValid,
wRxcHdrSCP, wRxcHdrMCP,
wRxcHdrEndMask, wRxcHdrStartMask}),
// Inputs
.RST_IN (RST_IN),
.WR_DATA ({_wRxcHdrValid,
_wRxcHdrSCP, _wRxcHdrMCP,
_wRxcHdrEndMask, _wRxcHdrStartMask}), // Need to invert the start mask
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (4)
/*AUTOINSTPARAM*/)
o2m_ef
(
// Outputs
.MASK (_wRxcHdrEndMask),
// Inputs
.OFFSET_ENABLE (_wRxcHdrEF),
.OFFSET (_wRxcHdrDataEoff)
/*AUTOINST*/);
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (C_OUTPUT_STAGE_WIDTH),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(
// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({RXC_DATA_WORD_ENABLE, RXC_DATA_START_FLAG, RXC_DATA_START_OFFSET,
RXC_DATA_END_FLAG, RXC_META_TAG, RXC_META_TYPE,
RXC_META_ADDR, RXC_META_COMPLETER_ID, RXC_META_BYTES_REMAINING,
RXC_META_LENGTH, RXC_META_EP}),
.RD_DATA_VALID (RXC_DATA_VALID),
// Inputs
.WR_DATA ({wRxcDataWordEnable, wRxcDataStartFlag, wRxcDataStartOffset,
wRxcDataEndFlag, wRxcMetaTag, wRxcMetaType,
wRxcMetaAddr, wRxcMetaCompleterId, wRxcMetaBytesRemaining,
wRxcMetaLength, wRxcMetaEP}),
.WR_DATA_VALID (wRxcDataValid),
.RD_DATA_READY (1'b1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule

13
fpga/riffa_hdl/rxc_engine_ultrascale.v
View File

@ -45,19 +45,18 @@
`include "trellis.vh" `include "trellis.vh"
`include "ultrascale.vh" `include "ultrascale.vh"
module rxc_engine_ultrascale module rxc_engine_ultrascale
#( #(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10, parameter C_RX_PIPELINE_DEPTH=10,
// Number of data pipeline registers for metadata and data stages // Number of data pipeline registers for metadata and data stages
parameter C_RX_META_STAGES = 0, parameter C_RX_META_STAGES = 0,
parameter C_RX_DATA_STAGES = 1 parameter C_RX_DATA_STAGES = 1)
) (// Interface: Clocks
(
// Interface: Clocks
input CLK, input CLK,
// Interface: Resets // Interface: Resets
input RST_IN, input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
// Interface: RC // Interface: RC
input M_AXIS_RC_TVALID, input M_AXIS_RC_TVALID,

433
fpga/riffa_hdl/rxr_engine_128.v Normal file
View File

@ -0,0 +1,433 @@
`include "trellis.vh"
`include "tlp.vh"
module rxr_engine_128
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
input RX_TLP_VALID,
input RX_TLP_START_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
input RX_TLP_END_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
// Interface: RXR
output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
output RXR_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
output RXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
output RXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
output [`SIG_TC_W-1:0] RXR_META_TC,
output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
output [`SIG_TAG_W-1:0] RXR_META_TAG,
output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
output RXR_META_EP,
// Interface: RX Shift Register
input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_START_OFFSET,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID
);
/*AUTOWIRE*/
///*AUTOOUTPUT*/
// End of automatics
localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 1;
localparam C_RX_OUTPUT_STAGES = 1;
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_RX_HDR_STAGES = 1; // Specific to the Xilinx 128-bit RXR Engine
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES + C_RX_HDR_STAGES;
localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
localparam C_STRADDLE_W = 64;
localparam C_HDR_NOSTRADDLE_I = C_RX_INPUT_STAGES * C_PCI_DATA_WIDTH;
localparam C_OUTPUT_STAGE_WIDTH = (C_PCI_DATA_WIDTH/32) + 2 + clog2s(C_PCI_DATA_WIDTH/32) + 1 + `SIG_FBE_W + `SIG_LBE_W + `SIG_TC_W + `SIG_ATTR_W + `SIG_TAG_W + `SIG_TYPE_W + `SIG_ADDR_W + `SIG_BARDECODE_W + `SIG_REQID_W + `SIG_LEN_W;
// Header Reg Inputs
wire [`SIG_OFFSET_W-1:0] __wRxrStartOffset;
wire [`SIG_OFFSET_W-1:0] __wRxrStraddledStartOffset;
wire [`TLP_MAXHDR_W-1:0] __wRxrHdr;
wire [`TLP_MAXHDR_W-1:0] __wRxrHdrStraddled;
wire [`TLP_MAXHDR_W-1:0] __wRxrHdrNotStraddled;
wire __wRxrHdrValid;
wire [`TLP_TYPE_W-1:0] __wRxrHdrType;
wire [`TLP_TYPE_W-1:0] __wRxrHdrTypeStraddled;
wire __wRxrHdrSOP; // Asserted on non-straddle SOP
wire __wRxrHdrSOPStraddle;
wire __wRxrHdr4DWHWDataSF;
// Header Reg Outputs
wire _wRxrHdrValid;
wire [`TLP_MAXHDR_W-1:0] _wRxrHdr;
wire [`SIG_ADDR_W-1:0] _wRxrAddrUnformatted;
wire [`SIG_ADDR_W-1:0] _wRxrAddr;
wire [63:0] _wRxrTlpMetadata;
wire [`TLP_TYPE_W-1:0] _wRxrType;
wire [`TLP_LEN_W-1:0] _wRxrLength;
wire [2:0] _wRxrHdrHdrLen;// TODO:
wire [`SIG_OFFSET_W-1:0] _wRxrHdrStartOffset;// TODO:
wire _wRxrHdrDelayedSOP;
wire _wRxrHdrSOPStraddle;
wire _wRxrHdrSOP;
wire _wRxrHdrSF;
wire _wRxrHdrEF;
wire _wRxrHdrSCP; // Single Cycle Packet
wire _wRxrHdrMCP; // Multi Cycle Packet
wire _wRxrHdrRegSF;
wire _wRxrHdrRegValid;
wire _wRxrHdr4DWHSF;
wire _wRxrHdr4DWHNoDataSF;
wire _wRxrHdr4DWHWDataSF;
wire _wRxrHdr3DWHSF;
wire [2:0] _wRxrHdrDataSoff;
wire [1:0] _wRxrHdrDataEoff;
wire [3:0] _wRxrHdrStartMask;
wire [3:0] _wRxrHdrEndMask;
// Header Reg Outputs
wire wRxrHdrSF;
wire wRxrHdrEF;
wire wRxrHdrValid;
wire [`TLP_MAXHDR_W-1:0] wRxrHdr;
wire [63:0] wRxrMetadata;
wire [`TLP_TYPE_W-1:0] wRxrType;
wire [`TLP_LEN_W-1:0] wRxrLength;
wire [2:0] wRxrHdrLength; // TODO:
wire [`SIG_OFFSET_W-1:0] wRxrHdrStartOffset; // TODO:
wire wRxrHdrSCP; // Single Cycle Packet
wire wRxrHdrMCP; // Multi Cycle Packet
wire [1:0] wRxrHdrDataSoff;
wire [3:0] wRxrHdrStartMask;
wire [3:0] wRxrHdrEndMask;
// Output Register Inputs
wire [C_PCI_DATA_WIDTH-1:0] wRxrData;
wire wRxrDataValid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataWordEnable;
wire wRxrDataStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataStartOffset;
wire wRxrDataEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataEndOffset;
wire [`SIG_FBE_W-1:0] wRxrMetaFdwbe;
wire [`SIG_LBE_W-1:0] wRxrMetaLdwbe;
wire [`SIG_TC_W-1:0] wRxrMetaTC;
wire [`SIG_ATTR_W-1:0] wRxrMetaAttr;
wire [`SIG_TAG_W-1:0] wRxrMetaTag;
wire [`SIG_TYPE_W-1:0] wRxrMetaType;
wire [`SIG_ADDR_W-1:0] wRxrMetaAddr;
wire [`SIG_BARDECODE_W-1:0] wRxrMetaBarDecoded;
wire [`SIG_REQID_W-1:0] wRxrMetaRequesterId;
wire [`SIG_LEN_W-1:0] wRxrMetaLength;
wire wRxrMetaEP;
reg rStraddledSOP;
reg rStraddledSOPSplit;
// ----- Header Register -----
assign __wRxrHdrSOP = RX_SR_SOP[C_RX_INPUT_STAGES] & ~__wRxrStartOffset[1];
assign __wRxrHdrSOPStraddle = RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxrStraddledStartOffset[1];
assign __wRxrHdrNotStraddled = RX_SR_DATA[C_HDR_NOSTRADDLE_I +: C_PCI_DATA_WIDTH];
assign __wRxrHdrStraddled = {RX_SR_DATA[C_RX_INPUT_STAGES*C_PCI_DATA_WIDTH +: C_STRADDLE_W],
RX_SR_DATA[(C_RX_INPUT_STAGES+1)*C_PCI_DATA_WIDTH + C_STRADDLE_W +: C_STRADDLE_W ]};
assign __wRxrStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*C_RX_INPUT_STAGES +: `SIG_OFFSET_W];
assign __wRxrStraddledStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*(C_RX_INPUT_STAGES) +: `SIG_OFFSET_W];
assign __wRxrHdrValid = __wRxrHdrSOP | ((rStraddledSOP | rStraddledSOPSplit) & RX_SR_VALID[C_RX_INPUT_STAGES]);
assign __wRxrHdr4DWHWDataSF = (_wRxrHdr[`TLP_4DWHBIT_I] & _wRxrHdr[`TLP_PAYBIT_I] & RX_SR_VALID[C_RX_INPUT_STAGES] & _wRxrHdrDelayedSOP);
assign _wRxrHdrHdrLen = {_wRxrHdr[`TLP_4DWHBIT_I],~_wRxrHdr[`TLP_4DWHBIT_I],~_wRxrHdr[`TLP_4DWHBIT_I]};
assign _wRxrHdrDataSoff = {1'b0,_wRxrHdrSOPStraddle,1'b0} + _wRxrHdrHdrLen;
assign _wRxrHdrRegSF = RX_SR_SOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
assign _wRxrHdrRegValid = RX_SR_VALID[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
assign _wRxrHdr4DWHNoDataSF = _wRxrHdr[`TLP_4DWHBIT_I] & ~_wRxrHdr[`TLP_PAYBIT_I] & _wRxrHdrSOP;
assign _wRxrHdr4DWHSF = _wRxrHdr4DWHNoDataSF | (_wRxrHdr4DWHWDataSF & _wRxrHdrRegValid);
assign _wRxrHdr3DWHSF = ~_wRxrHdr[`TLP_4DWHBIT_I] & _wRxrHdrSOP;
assign _wRxrHdrSF = (_wRxrHdr3DWHSF | _wRxrHdr4DWHSF | _wRxrHdrSOPStraddle);
assign _wRxrHdrEF = RX_SR_EOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
assign _wRxrHdrDataEoff = RX_SR_END_OFFSET[(C_RX_INPUT_STAGES+C_RX_HDR_STAGES)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
assign _wRxrHdrSCP = _wRxrHdrSF & _wRxrHdrEF & (_wRxrHdr[`TLP_TYPE_R] == `TLP_TYPE_REQ);
assign _wRxrHdrMCP = (_wRxrHdrSF & ~_wRxrHdrEF & (_wRxrHdr[`TLP_TYPE_R] == `TLP_TYPE_REQ)) |
(wRxrHdrMCP & ~wRxrHdrEF);
assign _wRxrHdrStartMask = 4'hf << (_wRxrHdrSF ? _wRxrHdrDataSoff[1:0] : 0);
assign wRxrDataWordEnable = wRxrHdrEndMask & wRxrHdrStartMask & {4{wRxrDataValid}};
assign wRxrDataValid = wRxrHdrSCP | wRxrHdrMCP;
assign wRxrDataStartFlag = wRxrHdrSF;
assign wRxrDataEndFlag = wRxrHdrEF;
assign wRxrDataStartOffset = wRxrHdrDataSoff;
assign wRxrMetaFdwbe = wRxrHdr[`TLP_REQFBE_R];
assign wRxrMetaLdwbe = wRxrHdr[`TLP_REQLBE_R];
assign wRxrMetaTC = wRxrHdr[`TLP_TC_R];
assign wRxrMetaAttr = {wRxrHdr[`TLP_ATTR1_R], wRxrHdr[`TLP_ATTR0_R]};
assign wRxrMetaTag = wRxrHdr[`TLP_REQTAG_R];
assign wRxrMetaAddr = wRxrHdr[`TLP_REQADDRDW0_I +: `TLP_REQADDR_W];/* TODO: REQADDR_R*/
assign wRxrMetaRequesterId = wRxrHdr[`TLP_REQREQID_R];
assign wRxrMetaLength = wRxrHdr[`TLP_LEN_R];
assign wRxrMetaEP = wRxrHdr[`TLP_EP_R];
assign wRxrMetaType = tlp_to_trellis_type({wRxrHdr[`TLP_FMT_R],wRxrHdr[`TLP_TYPE_R]});
assign RXR_DATA = RX_SR_DATA[C_PCI_DATA_WIDTH*C_TOTAL_STAGES +: C_PCI_DATA_WIDTH];
assign RXR_DATA_END_OFFSET = RX_SR_END_OFFSET[`SIG_OFFSET_W*(C_TOTAL_STAGES) +: C_OFFSET_WIDTH];
always @(posedge CLK) begin
rStraddledSOP <= __wRxrHdrSOPStraddle;
// Set Straddled SOP Split when there is a straddled packet where the
// header is not contiguous. (Not sure if this is ever possible, but
// better safe than sorry assert Straddled SOP Split. See Virtex 6 PCIe
// errata.
if(__wRxrHdrSOP | RST_IN) begin
rStraddledSOPSplit <=0;
end else begin
rStraddledSOPSplit <= (__wRxrHdrSOPStraddle | rStraddledSOPSplit) & ~RX_SR_VALID[C_RX_INPUT_STAGES];
end
end
mux
#(
// Parameters
.C_NUM_INPUTS (2),
.C_CLOG_NUM_INPUTS (1),
.C_WIDTH (`TLP_MAXHDR_W),
.C_MUX_TYPE ("SELECT")
/*AUTOINSTPARAM*/)
hdr_mux
(
// Outputs
.MUX_OUTPUT (__wRxrHdr[`TLP_MAXHDR_W-1:0]),
// Inputs
.MUX_INPUTS ({__wRxrHdrStraddled[`TLP_MAXHDR_W-1:0],
__wRxrHdrNotStraddled[`TLP_MAXHDR_W-1:0]}),
.MUX_SELECT (rStraddledSOP | rStraddledSOPSplit)
/*AUTOINST*/);
register
#(
// Parameters
.C_WIDTH (64 + 1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
hdr_register_63_0
(
// Outputs
.RD_DATA ({_wRxrHdr[C_STRADDLE_W-1:0], _wRxrHdrValid}),
// Inputs
.WR_DATA ({__wRxrHdr[C_STRADDLE_W-1:0], __wRxrHdrValid}),
.WR_EN (__wRxrHdrSOP | rStraddledSOP),
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (3),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
sf4dwh
(
// Outputs
.RD_DATA ({_wRxrHdr4DWHWDataSF, _wRxrHdrSOPStraddle,_wRxrHdrSOP}),
// Inputs
.WR_DATA ({__wRxrHdr4DWHWDataSF,rStraddledSOP,__wRxrHdrSOP}),
.WR_EN (1),
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
delayed_sop
(
// Outputs
.RD_DATA ({_wRxrHdrDelayedSOP}),
// Inputs
.WR_DATA ({__wRxrHdrSOP}),
.WR_EN (RX_SR_VALID[C_RX_INPUT_STAGES]),
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (64),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
hdr_register_127_64
(
// Outputs
.RD_DATA (_wRxrHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
// Inputs
.WR_DATA (__wRxrHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
.WR_EN (__wRxrHdrSOP | rStraddledSOP | rStraddledSOPSplit), // Non straddled start, Straddled, or straddled split
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
// ----- Computation Register -----
register
#(
// Parameters
.C_WIDTH (64 + 4),/* TODO: TLP_METADATA_W*/
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata
(// Outputs
.RD_DATA ({wRxrHdr[`TLP_REQMETADW0_I +: 64],
wRxrHdrSF,wRxrHdrDataSoff,
wRxrHdrEF}),/* TODO: TLP_METADATA_R and other signals*/
// Inputs
.RST_IN (0),/* TODO: Never need to reset?*/
.WR_DATA ({_wRxrHdr[`TLP_REQMETADW0_I +: 64],
_wRxrHdrSF,_wRxrHdrDataSoff[1:0],
_wRxrHdrEF}),/* TODO: TLP_METADATA_R*/
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (3+8),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_valid
(// Output
.RD_DATA ({wRxrHdrValid,
wRxrHdrSCP, wRxrHdrMCP,
wRxrHdrEndMask, wRxrHdrStartMask}),
// Inputs
.RST_IN (RST_IN),
.WR_DATA ({_wRxrHdrValid,
_wRxrHdrSCP, _wRxrHdrMCP,
_wRxrHdrEndMask, _wRxrHdrStartMask}),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (`SIG_ADDR_W/2),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_63_32
(// Outputs
.RD_DATA (wRxrHdr[`TLP_REQADDRHI_R]),
// Inputs
.RST_IN (~_wRxrHdr[`TLP_4DWHBIT_I]),
.WR_DATA (_wRxrHdr[`TLP_REQADDRLO_R]), // Instead of a mux, we'll use the reset
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (`SIG_ADDR_W/2),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_31_0
(// Outputs
.RD_DATA (wRxrHdr[`TLP_REQADDRLO_R]),
// Inputs
.RST_IN (0),// Never need to reset
.WR_DATA (_wRxrHdr[`TLP_4DWHBIT_I] ? _wRxrHdr[`TLP_REQADDRHI_R] : _wRxrHdr[`TLP_REQADDRLO_R]),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (4)
/*AUTOINSTPARAM*/)
o2m_ef
(
// Outputs
.MASK (_wRxrHdrEndMask),
// Inputs
.OFFSET_ENABLE (_wRxrHdrEF),
.OFFSET (_wRxrHdrDataEoff)
/*AUTOINST*/);
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (C_OUTPUT_STAGE_WIDTH),// TODO:
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(
// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({RXR_DATA_WORD_ENABLE, RXR_DATA_START_FLAG, RXR_DATA_START_OFFSET,
RXR_DATA_END_FLAG,
RXR_META_FDWBE, RXR_META_LDWBE, RXR_META_TC,
RXR_META_ATTR, RXR_META_TAG, RXR_META_TYPE,
RXR_META_ADDR, RXR_META_BAR_DECODED, RXR_META_REQUESTER_ID,
RXR_META_LENGTH, RXR_META_EP}),
.RD_DATA_VALID (RXR_DATA_VALID),
// Inputs
.WR_DATA ({wRxrDataWordEnable, wRxrDataStartFlag, wRxrDataStartOffset,
wRxrDataEndFlag,
wRxrMetaFdwbe, wRxrMetaLdwbe, wRxrMetaTC,
wRxrMetaAttr, wRxrMetaTag, wRxrMetaType,
wRxrMetaAddr, wRxrMetaBarDecoded, wRxrMetaRequesterId,
wRxrMetaLength, wRxrMetaEP}),
.WR_DATA_VALID (wRxrDataValid),
.RD_DATA_READY (1'b1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common")
// End:

438
fpga/riffa_hdl/rxr_engine_classic.v
View File

@ -47,14 +47,14 @@
module rxr_engine_classic module rxr_engine_classic
#(parameter C_VENDOR = "ALTERA", #(parameter C_VENDOR = "ALTERA",
parameter C_PCI_DATA_WIDTH = 128, parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10 parameter C_RX_PIPELINE_DEPTH=10)
) (// Interface: Clocks
(
// Interface: Clocks
input CLK, input CLK,
// Interface: Resets // Interface: Resets
input RST_IN, input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
// Interface: RX Classic // Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP, input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
@ -545,434 +545,6 @@ module rxr_engine_classic
.CLK (CLK)); .CLK (CLK));
endmodule endmodule
module rxr_engine_128
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
input RX_TLP_VALID,
input RX_TLP_START_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
input RX_TLP_END_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
// Interface: RXR
output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
output RXR_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
output RXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
output RXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
output [`SIG_TC_W-1:0] RXR_META_TC,
output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
output [`SIG_TAG_W-1:0] RXR_META_TAG,
output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
output RXR_META_EP,
// Interface: RX Shift Register
input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_START_OFFSET,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID
);
/*AUTOWIRE*/
///*AUTOOUTPUT*/
// End of automatics
localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 1;
localparam C_RX_OUTPUT_STAGES = 1;
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_RX_HDR_STAGES = 1; // Specific to the Xilinx 128-bit RXR Engine
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES + C_RX_HDR_STAGES;
localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
localparam C_STRADDLE_W = 64;
localparam C_HDR_NOSTRADDLE_I = C_RX_INPUT_STAGES * C_PCI_DATA_WIDTH;
localparam C_OUTPUT_STAGE_WIDTH = (C_PCI_DATA_WIDTH/32) + 2 + clog2s(C_PCI_DATA_WIDTH/32) + 1 + `SIG_FBE_W + `SIG_LBE_W + `SIG_TC_W + `SIG_ATTR_W + `SIG_TAG_W + `SIG_TYPE_W + `SIG_ADDR_W + `SIG_BARDECODE_W + `SIG_REQID_W + `SIG_LEN_W;
// Header Reg Inputs
wire [`SIG_OFFSET_W-1:0] __wRxrStartOffset;
wire [`SIG_OFFSET_W-1:0] __wRxrStraddledStartOffset;
wire [`TLP_MAXHDR_W-1:0] __wRxrHdr;
wire [`TLP_MAXHDR_W-1:0] __wRxrHdrStraddled;
wire [`TLP_MAXHDR_W-1:0] __wRxrHdrNotStraddled;
wire __wRxrHdrValid;
wire [`TLP_TYPE_W-1:0] __wRxrHdrType;
wire [`TLP_TYPE_W-1:0] __wRxrHdrTypeStraddled;
wire __wRxrHdrSOP; // Asserted on non-straddle SOP
wire __wRxrHdrSOPStraddle;
wire __wRxrHdr4DWHWDataSF;
// Header Reg Outputs
wire _wRxrHdrValid;
wire [`TLP_MAXHDR_W-1:0] _wRxrHdr;
wire [`SIG_ADDR_W-1:0] _wRxrAddrUnformatted;
wire [`SIG_ADDR_W-1:0] _wRxrAddr;
wire [63:0] _wRxrTlpMetadata;
wire [`TLP_TYPE_W-1:0] _wRxrType;
wire [`TLP_LEN_W-1:0] _wRxrLength;
wire [2:0] _wRxrHdrHdrLen;// TODO:
wire [`SIG_OFFSET_W-1:0] _wRxrHdrStartOffset;// TODO:
wire _wRxrHdrDelayedSOP;
wire _wRxrHdrSOPStraddle;
wire _wRxrHdrSOP;
wire _wRxrHdrSF;
wire _wRxrHdrEF;
wire _wRxrHdrSCP; // Single Cycle Packet
wire _wRxrHdrMCP; // Multi Cycle Packet
wire _wRxrHdrRegSF;
wire _wRxrHdrRegValid;
wire _wRxrHdr4DWHSF;
wire _wRxrHdr4DWHNoDataSF;
wire _wRxrHdr4DWHWDataSF;
wire _wRxrHdr3DWHSF;
wire [2:0] _wRxrHdrDataSoff;
wire [1:0] _wRxrHdrDataEoff;
wire [3:0] _wRxrHdrStartMask;
wire [3:0] _wRxrHdrEndMask;
// Header Reg Outputs
wire wRxrHdrSF;
wire wRxrHdrEF;
wire wRxrHdrValid;
wire [`TLP_MAXHDR_W-1:0] wRxrHdr;
wire [63:0] wRxrMetadata;
wire [`TLP_TYPE_W-1:0] wRxrType;
wire [`TLP_LEN_W-1:0] wRxrLength;
wire [2:0] wRxrHdrLength; // TODO:
wire [`SIG_OFFSET_W-1:0] wRxrHdrStartOffset; // TODO:
wire wRxrHdrSCP; // Single Cycle Packet
wire wRxrHdrMCP; // Multi Cycle Packet
wire [1:0] wRxrHdrDataSoff;
wire [3:0] wRxrHdrStartMask;
wire [3:0] wRxrHdrEndMask;
// Output Register Inputs
wire [C_PCI_DATA_WIDTH-1:0] wRxrData;
wire wRxrDataValid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataWordEnable;
wire wRxrDataStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataStartOffset;
wire wRxrDataEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataEndOffset;
wire [`SIG_FBE_W-1:0] wRxrMetaFdwbe;
wire [`SIG_LBE_W-1:0] wRxrMetaLdwbe;
wire [`SIG_TC_W-1:0] wRxrMetaTC;
wire [`SIG_ATTR_W-1:0] wRxrMetaAttr;
wire [`SIG_TAG_W-1:0] wRxrMetaTag;
wire [`SIG_TYPE_W-1:0] wRxrMetaType;
wire [`SIG_ADDR_W-1:0] wRxrMetaAddr;
wire [`SIG_BARDECODE_W-1:0] wRxrMetaBarDecoded;
wire [`SIG_REQID_W-1:0] wRxrMetaRequesterId;
wire [`SIG_LEN_W-1:0] wRxrMetaLength;
wire wRxrMetaEP;
reg rStraddledSOP;
reg rStraddledSOPSplit;
// ----- Header Register -----
assign __wRxrHdrSOP = RX_SR_SOP[C_RX_INPUT_STAGES] & ~__wRxrStartOffset[1];
assign __wRxrHdrSOPStraddle = RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxrStraddledStartOffset[1];
assign __wRxrHdrNotStraddled = RX_SR_DATA[C_HDR_NOSTRADDLE_I +: C_PCI_DATA_WIDTH];
assign __wRxrHdrStraddled = {RX_SR_DATA[C_RX_INPUT_STAGES*C_PCI_DATA_WIDTH +: C_STRADDLE_W],
RX_SR_DATA[(C_RX_INPUT_STAGES+1)*C_PCI_DATA_WIDTH + C_STRADDLE_W +: C_STRADDLE_W ]};
assign __wRxrStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*C_RX_INPUT_STAGES +: `SIG_OFFSET_W];
assign __wRxrStraddledStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*(C_RX_INPUT_STAGES) +: `SIG_OFFSET_W];
assign __wRxrHdrValid = __wRxrHdrSOP | ((rStraddledSOP | rStraddledSOPSplit) & RX_SR_VALID[C_RX_INPUT_STAGES]);
assign __wRxrHdr4DWHWDataSF = (_wRxrHdr[`TLP_4DWHBIT_I] & _wRxrHdr[`TLP_PAYBIT_I] & RX_SR_VALID[C_RX_INPUT_STAGES] & _wRxrHdrDelayedSOP);
assign _wRxrHdrHdrLen = {_wRxrHdr[`TLP_4DWHBIT_I],~_wRxrHdr[`TLP_4DWHBIT_I],~_wRxrHdr[`TLP_4DWHBIT_I]};
assign _wRxrHdrDataSoff = {1'b0,_wRxrHdrSOPStraddle,1'b0} + _wRxrHdrHdrLen;
assign _wRxrHdrRegSF = RX_SR_SOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
assign _wRxrHdrRegValid = RX_SR_VALID[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
assign _wRxrHdr4DWHNoDataSF = _wRxrHdr[`TLP_4DWHBIT_I] & ~_wRxrHdr[`TLP_PAYBIT_I] & _wRxrHdrSOP;
assign _wRxrHdr4DWHSF = _wRxrHdr4DWHNoDataSF | (_wRxrHdr4DWHWDataSF & _wRxrHdrRegValid);
assign _wRxrHdr3DWHSF = ~_wRxrHdr[`TLP_4DWHBIT_I] & _wRxrHdrSOP;
assign _wRxrHdrSF = (_wRxrHdr3DWHSF | _wRxrHdr4DWHSF | _wRxrHdrSOPStraddle);
assign _wRxrHdrEF = RX_SR_EOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
assign _wRxrHdrDataEoff = RX_SR_END_OFFSET[(C_RX_INPUT_STAGES+C_RX_HDR_STAGES)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
assign _wRxrHdrSCP = _wRxrHdrSF & _wRxrHdrEF & (_wRxrHdr[`TLP_TYPE_R] == `TLP_TYPE_REQ);
assign _wRxrHdrMCP = (_wRxrHdrSF & ~_wRxrHdrEF & (_wRxrHdr[`TLP_TYPE_R] == `TLP_TYPE_REQ)) |
(wRxrHdrMCP & ~wRxrHdrEF);
assign _wRxrHdrStartMask = 4'hf << (_wRxrHdrSF ? _wRxrHdrDataSoff[1:0] : 0);
assign wRxrDataWordEnable = wRxrHdrEndMask & wRxrHdrStartMask & {4{wRxrDataValid}};
assign wRxrDataValid = wRxrHdrSCP | wRxrHdrMCP;
assign wRxrDataStartFlag = wRxrHdrSF;
assign wRxrDataEndFlag = wRxrHdrEF;
assign wRxrDataStartOffset = wRxrHdrDataSoff;
assign wRxrMetaFdwbe = wRxrHdr[`TLP_REQFBE_R];
assign wRxrMetaLdwbe = wRxrHdr[`TLP_REQLBE_R];
assign wRxrMetaTC = wRxrHdr[`TLP_TC_R];
assign wRxrMetaAttr = {wRxrHdr[`TLP_ATTR1_R], wRxrHdr[`TLP_ATTR0_R]};
assign wRxrMetaTag = wRxrHdr[`TLP_REQTAG_R];
assign wRxrMetaAddr = wRxrHdr[`TLP_REQADDRDW0_I +: `TLP_REQADDR_W];/* TODO: REQADDR_R*/
assign wRxrMetaRequesterId = wRxrHdr[`TLP_REQREQID_R];
assign wRxrMetaLength = wRxrHdr[`TLP_LEN_R];
assign wRxrMetaEP = wRxrHdr[`TLP_EP_R];
assign wRxrMetaType = tlp_to_trellis_type({wRxrHdr[`TLP_FMT_R],wRxrHdr[`TLP_TYPE_R]});
assign RXR_DATA = RX_SR_DATA[C_PCI_DATA_WIDTH*C_TOTAL_STAGES +: C_PCI_DATA_WIDTH];
assign RXR_DATA_END_OFFSET = RX_SR_END_OFFSET[`SIG_OFFSET_W*(C_TOTAL_STAGES) +: C_OFFSET_WIDTH];
always @(posedge CLK) begin
rStraddledSOP <= __wRxrHdrSOPStraddle;
// Set Straddled SOP Split when there is a straddled packet where the
// header is not contiguous. (Not sure if this is ever possible, but
// better safe than sorry assert Straddled SOP Split. See Virtex 6 PCIe
// errata.
if(__wRxrHdrSOP | RST_IN) begin
rStraddledSOPSplit <=0;
end else begin
rStraddledSOPSplit <= (__wRxrHdrSOPStraddle | rStraddledSOPSplit) & ~RX_SR_VALID[C_RX_INPUT_STAGES];
end
end
mux
#(
// Parameters
.C_NUM_INPUTS (2),
.C_CLOG_NUM_INPUTS (1),
.C_WIDTH (`TLP_MAXHDR_W),
.C_MUX_TYPE ("SELECT")
/*AUTOINSTPARAM*/)
hdr_mux
(
// Outputs
.MUX_OUTPUT (__wRxrHdr[`TLP_MAXHDR_W-1:0]),
// Inputs
.MUX_INPUTS ({__wRxrHdrStraddled[`TLP_MAXHDR_W-1:0],
__wRxrHdrNotStraddled[`TLP_MAXHDR_W-1:0]}),
.MUX_SELECT (rStraddledSOP | rStraddledSOPSplit)
/*AUTOINST*/);
register
#(
// Parameters
.C_WIDTH (64 + 1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
hdr_register_63_0
(
// Outputs
.RD_DATA ({_wRxrHdr[C_STRADDLE_W-1:0], _wRxrHdrValid}),
// Inputs
.WR_DATA ({__wRxrHdr[C_STRADDLE_W-1:0], __wRxrHdrValid}),
.WR_EN (__wRxrHdrSOP | rStraddledSOP),
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (3),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
sf4dwh
(
// Outputs
.RD_DATA ({_wRxrHdr4DWHWDataSF, _wRxrHdrSOPStraddle,_wRxrHdrSOP}),
// Inputs
.WR_DATA ({__wRxrHdr4DWHWDataSF,rStraddledSOP,__wRxrHdrSOP}),
.WR_EN (1),
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
delayed_sop
(
// Outputs
.RD_DATA ({_wRxrHdrDelayedSOP}),
// Inputs
.WR_DATA ({__wRxrHdrSOP}),
.WR_EN (RX_SR_VALID[C_RX_INPUT_STAGES]),
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (64),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
hdr_register_127_64
(
// Outputs
.RD_DATA (_wRxrHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
// Inputs
.WR_DATA (__wRxrHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
.WR_EN (__wRxrHdrSOP | rStraddledSOP | rStraddledSOPSplit), // Non straddled start, Straddled, or straddled split
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
// ----- Computation Register -----
register
#(
// Parameters
.C_WIDTH (64 + 4),/* TODO: TLP_METADATA_W*/
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata
(// Outputs
.RD_DATA ({wRxrHdr[`TLP_REQMETADW0_I +: 64],
wRxrHdrSF,wRxrHdrDataSoff,
wRxrHdrEF}),/* TODO: TLP_METADATA_R and other signals*/
// Inputs
.RST_IN (0),/* TODO: Never need to reset?*/
.WR_DATA ({_wRxrHdr[`TLP_REQMETADW0_I +: 64],
_wRxrHdrSF,_wRxrHdrDataSoff[1:0],
_wRxrHdrEF}),/* TODO: TLP_METADATA_R*/
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (3+8),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_valid
(// Output
.RD_DATA ({wRxrHdrValid,
wRxrHdrSCP, wRxrHdrMCP,
wRxrHdrEndMask, wRxrHdrStartMask}),
// Inputs
.RST_IN (RST_IN),
.WR_DATA ({_wRxrHdrValid,
_wRxrHdrSCP, _wRxrHdrMCP,
_wRxrHdrEndMask, _wRxrHdrStartMask}),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (`SIG_ADDR_W/2),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_63_32
(// Outputs
.RD_DATA (wRxrHdr[`TLP_REQADDRHI_R]),
// Inputs
.RST_IN (~_wRxrHdr[`TLP_4DWHBIT_I]),
.WR_DATA (_wRxrHdr[`TLP_REQADDRLO_R]), // Instead of a mux, we'll use the reset
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (`SIG_ADDR_W/2),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_31_0
(// Outputs
.RD_DATA (wRxrHdr[`TLP_REQADDRLO_R]),
// Inputs
.RST_IN (0),// Never need to reset
.WR_DATA (_wRxrHdr[`TLP_4DWHBIT_I] ? _wRxrHdr[`TLP_REQADDRHI_R] : _wRxrHdr[`TLP_REQADDRLO_R]),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (4)
/*AUTOINSTPARAM*/)
o2m_ef
(
// Outputs
.MASK (_wRxrHdrEndMask),
// Inputs
.OFFSET_ENABLE (_wRxrHdrEF),
.OFFSET (_wRxrHdrDataEoff)
/*AUTOINST*/);
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (C_OUTPUT_STAGE_WIDTH),// TODO:
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(
// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({RXR_DATA_WORD_ENABLE, RXR_DATA_START_FLAG, RXR_DATA_START_OFFSET,
RXR_DATA_END_FLAG,
RXR_META_FDWBE, RXR_META_LDWBE, RXR_META_TC,
RXR_META_ATTR, RXR_META_TAG, RXR_META_TYPE,
RXR_META_ADDR, RXR_META_BAR_DECODED, RXR_META_REQUESTER_ID,
RXR_META_LENGTH, RXR_META_EP}),
.RD_DATA_VALID (RXR_DATA_VALID),
// Inputs
.WR_DATA ({wRxrDataWordEnable, wRxrDataStartFlag, wRxrDataStartOffset,
wRxrDataEndFlag,
wRxrMetaFdwbe, wRxrMetaLdwbe, wRxrMetaTC,
wRxrMetaAttr, wRxrMetaTag, wRxrMetaType,
wRxrMetaAddr, wRxrMetaBarDecoded, wRxrMetaRequesterId,
wRxrMetaLength, wRxrMetaEP}),
.WR_DATA_VALID (wRxrDataValid),
.RD_DATA_READY (1'b1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables: // Local Variables:
// verilog-library-directories:("." "../../../common") // verilog-library-directories:("." "../../../common")
// End: // End:

10
fpga/riffa_hdl/rxr_engine_ultrascale.v
View File

@ -46,14 +46,14 @@
`include "ultrascale.vh" `include "ultrascale.vh"
module rxr_engine_ultrascale module rxr_engine_ultrascale
#(parameter C_PCI_DATA_WIDTH = 128, #(parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10 parameter C_RX_PIPELINE_DEPTH=10)
) (// Interface: Clocks
(
// Interface: Clocks
input CLK, input CLK,
// Interface: Resets // Interface: Resets
input RST_IN, input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
// Interface: CQ // Interface: CQ
input M_AXIS_CQ_TVALID, input M_AXIS_CQ_TVALID,

27
fpga/riffa_hdl/tx_engine_classic.v
View File

@ -52,19 +52,18 @@
`include "trellis.vh" `include "trellis.vh"
`include "tlp.vh" `include "tlp.vh"
module tx_engine_classic module tx_engine_classic
#( #(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1, parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1, parameter C_PIPELINE_OUTPUT = 1,
parameter C_MAX_PAYLOAD_DWORDS = 256, parameter C_MAX_PAYLOAD_DWORDS = 256,
parameter C_VENDOR = "ALTERA" parameter C_VENDOR = "ALTERA")
) (// Interface: Clocks
(
// Interface: Clocks
input CLK, input CLK,
// Interface: Resets // Interface: Resets
input RST_IN, input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
// Interface: Configuration // Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID, input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
@ -128,6 +127,9 @@ module tx_engine_classic
localparam C_DEPTH_PACKETS = 10; localparam C_DEPTH_PACKETS = 10;
/*AUTOWIRE*/ /*AUTOWIRE*/
/*AUTOINPUT*/ /*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input RST_IN; // To txr_engine_inst of txr_engine_classic.v, ...
// End of automatics
wire [C_PCI_DATA_WIDTH-1:0] _TXC_DATA; wire [C_PCI_DATA_WIDTH-1:0] _TXC_DATA;
wire [C_PCI_DATA_WIDTH-1:0] _TXR_DATA; wire [C_PCI_DATA_WIDTH-1:0] _TXR_DATA;
@ -216,11 +218,13 @@ module tx_engine_classic
.TXC_DATA (_TXC_DATA[C_PCI_DATA_WIDTH-1:0]), .TXC_DATA (_TXC_DATA[C_PCI_DATA_WIDTH-1:0]),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.DONE_RST (DONE_RST),
.TXC_DATA_READY (TXC_DATA_READY), .TXC_DATA_READY (TXC_DATA_READY),
.TXC_META_READY (TXC_META_READY), .TXC_META_READY (TXC_META_READY),
// Inputs // Inputs
.CLK (CLK), .CLK (CLK),
.RST_IN (RST_IN), .RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]), .CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (TXC_DATA_VALID), .TXC_DATA_VALID (TXC_DATA_VALID),
.TXC_DATA_START_FLAG (TXC_DATA_START_FLAG), .TXC_DATA_START_FLAG (TXC_DATA_START_FLAG),
@ -264,11 +268,13 @@ module tx_engine_classic
.TXR_TLP_READY (wTxrTlpReady), .TXR_TLP_READY (wTxrTlpReady),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.DONE_RST (DONE_RST),
.TXR_DATA_READY (TXR_DATA_READY), .TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY), .TXR_META_READY (TXR_META_READY),
// Inputs // Inputs
.CLK (CLK), .CLK (CLK),
.RST_IN (RST_IN), .RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]), .CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXR_DATA_VALID (TXR_DATA_VALID), .TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG), .TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
@ -284,7 +290,8 @@ module tx_engine_classic
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]), .TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]), .TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]), .TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP)); .TXR_META_EP (TXR_META_EP),
.RST_IN (RST_IN));
tx_mux tx_mux
#( #(

23
fpga/riffa_hdl/tx_engine_ultrascale.v
View File

@ -48,17 +48,18 @@
`include "trellis.vh" `include "trellis.vh"
`include "ultrascale.vh" `include "ultrascale.vh"
module tx_engine_ultrascale module tx_engine_ultrascale
#( #(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1, parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0, parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64 parameter C_MAX_PAYLOAD_DWORDS = 64)
) (// Interface: Clocks
(
// Interface: Clocks
input CLK, input CLK,
// Interface: Resets // Interface: Resets
input RST_IN, input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
// Interface: Configuration // Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID, input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
@ -153,6 +154,7 @@ module tx_engine_ultrascale
txr_engine_inst txr_engine_inst
(/*AUTOINST*/ (/*AUTOINST*/
// Outputs // Outputs
.DONE_RST (DONE_RST),
.S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID), .S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID),
.S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST), .S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST),
.S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]), .S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
@ -162,7 +164,8 @@ module tx_engine_ultrascale
.TXR_META_READY (TXR_META_READY), .TXR_META_READY (TXR_META_READY),
// Inputs // Inputs
.CLK (CLK), .CLK (CLK),
.RST_IN (RST_IN), .RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]), .CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY), .S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY),
.TXR_DATA_VALID (TXR_DATA_VALID), .TXR_DATA_VALID (TXR_DATA_VALID),
@ -195,6 +198,7 @@ module tx_engine_ultrascale
txc_engine_inst txc_engine_inst
(/*AUTOINST*/ (/*AUTOINST*/
// Outputs // Outputs
.DONE_RST (DONE_RST),
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID), .S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST), .S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]), .S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
@ -204,7 +208,8 @@ module tx_engine_ultrascale
.TXC_META_READY (TXC_META_READY), .TXC_META_READY (TXC_META_READY),
// Inputs // Inputs
.CLK (CLK), .CLK (CLK),
.RST_IN (RST_IN), .RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]), .CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY), .S_AXIS_CC_TREADY (S_AXIS_CC_TREADY),
.TXC_DATA_VALID (TXC_DATA_VALID), .TXC_DATA_VALID (TXC_DATA_VALID),

13
fpga/riffa_hdl/txc_engine_classic.v
View File

@ -50,20 +50,19 @@
`include "trellis.vh" // Defines the user-facing signal widths. `include "trellis.vh" // Defines the user-facing signal widths.
`include "tlp.vh" // Defines the endpoint-facing field widths in a TLP `include "tlp.vh" // Defines the endpoint-facing field widths in a TLP
module txc_engine_classic module txc_engine_classic
#( #(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1, parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0, parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64, parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_DEPTH_PACKETS = 10, parameter C_DEPTH_PACKETS = 10,
parameter C_VENDOR = "ALTERA" parameter C_VENDOR = "ALTERA")
) (// Interface: Clocks
(
// Interface: Clocks
input CLK, input CLK,
// Interface: Resets // Interface: Resets
input RST_IN, input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
// Interface: Configuration // Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID, input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,

13
fpga/riffa_hdl/txc_engine_ultrascale.v
View File

@ -49,19 +49,18 @@
`include "trellis.vh" `include "trellis.vh"
`include "ultrascale.vh" `include "ultrascale.vh"
module txc_engine_ultrascale module txc_engine_ultrascale
#( #(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1, parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1, parameter C_PIPELINE_OUTPUT = 1,
parameter C_DEPTH_PACKETS = 10, parameter C_DEPTH_PACKETS = 10,
parameter C_MAX_PAYLOAD_DWORDS = 256 parameter C_MAX_PAYLOAD_DWORDS = 256)
) (// Interface: Clocks
(
// Interface: Clocks
input CLK, input CLK,
// Interface: Resets // Interface: Resets
input RST_IN, input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
// Interface: Configuration // Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID, input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,

16
fpga/riffa_hdl/txr_engine_classic.v
View File

@ -49,20 +49,19 @@
`include "trellis.vh" // Defines the user-facing signal widths. `include "trellis.vh" // Defines the user-facing signal widths.
`include "tlp.vh" // Defines the endpoint-facing field widths in a TLP `include "tlp.vh" // Defines the endpoint-facing field widths in a TLP
module txr_engine_classic module txr_engine_classic
#( #(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1, parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0, parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64, parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_DEPTH_PACKETS = 10, parameter C_DEPTH_PACKETS = 10,
parameter C_VENDOR = "ALTERA" parameter C_VENDOR = "ALTERA")
) (// Interface: Clocks
(
// Interface: Clocks
input CLK, input CLK,
// Interface: Resets // Interface: Resets
input RST_IN, input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
// Interface: Configuration // Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID, input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
@ -110,6 +109,9 @@ module txr_engine_classic
/*AUTOWIRE*/ /*AUTOWIRE*/
/*AUTOINPUT*/ /*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input RST_IN; // To txr_formatter_inst of txr_formatter_classic.v, ...
// End of automatics
///*AUTOOUTPUT*/ ///*AUTOOUTPUT*/
wire wTxHdrReady; wire wTxHdrReady;

13
fpga/riffa_hdl/txr_engine_ultrascale.v
View File

@ -49,19 +49,18 @@
`include "trellis.vh" `include "trellis.vh"
`include "ultrascale.vh" `include "ultrascale.vh"
module txr_engine_ultrascale module txr_engine_ultrascale
#( #(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1, parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1, parameter C_PIPELINE_OUTPUT = 1,
parameter C_DEPTH_PACKETS = 10, parameter C_DEPTH_PACKETS = 10,
parameter C_MAX_PAYLOAD_DWORDS = 256 parameter C_MAX_PAYLOAD_DWORDS = 256)
) (// Interface: Clocks
(
// Interface: Clocks
input CLK, input CLK,
// Interface: Resets // Interface: Resets
input RST_IN, input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
// Interface: Configuration // Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID, input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,