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Fixed a bug where a clock ratio of less than 1:2 between the user-provided clock

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and the PCIe core clock would cause some transfers to return 0 words (but not
hang).
This commit is contained in:
Dustin Richmond 2016-02-16 16:02:42 -08:00
parent eb75cd688e
commit 753ffffd93
3 changed files with 48 additions and 30 deletions
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26
fpga/riffa_hdl/tx_port_monitor_128.v
View File

@ -42,11 +42,12 @@
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTMON128_NEXT 5'b0_0001
`define S_TXPORTMON128_TXN 5'b0_0010
`define S_TXPORTMON128_READ 5'b0_0100
`define S_TXPORTMON128_END_0 5'b0_1000
`define S_TXPORTMON128_END_1 5'b1_0000
`define S_TXPORTMON128_NEXT 6'b00_0001
`define S_TXPORTMON128_EVT_2 6'b00_0010
`define S_TXPORTMON128_TXN 6'b00_0100
`define S_TXPORTMON128_READ 6'b00_1000
`define S_TXPORTMON128_END_0 6'b01_0000
`define S_TXPORTMON128_END_1 6'b10_0000
`timescale 1ns/1ns
module tx_port_monitor_128 #(
@ -84,7 +85,7 @@ module tx_port_monitor_128 #(
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [4:0] rState=`S_TXPORTMON128_NEXT, _rState=`S_TXPORTMON128_NEXT;
reg [5:0] rState=`S_TXPORTMON128_NEXT, _rState=`S_TXPORTMON128_NEXT;
reg rRead=0, _rRead=0;
reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
reg rEvent=0, _rEvent=0;
@ -99,7 +100,7 @@ reg rLenLE4Lo=0, _rLenLE4Lo=0;
reg rTxErr=0, _rTxErr=0;
wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[2]); // S_TXPORTMON128_READ
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[3]); // S_TXPORTMON128_READ
wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE4Lo)) & wPayloadData);
assign EVT_DATA_RD_EN = rRead;
@ -107,12 +108,12 @@ assign EVT_DATA_RD_EN = rRead;
assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
assign WR_EN = wPayloadData; // S_TXPORTMON128_READ
assign TXN = rState[1]; // S_TXPORTMON128_TXN
assign TXN = rState[2]; // S_TXPORTMON128_TXN
assign LAST = rReadData[0];
assign OFF = rReadData[31:1];
assign LEN = rReadData[63:32];
assign WORDS_RECVD = rWordsRecvd;
assign DONE = !rState[2]; // !S_TXPORTMON128_READ
assign DONE = !rState[3]; // !S_TXPORTMON128_READ
@ -137,6 +138,11 @@ always @ (*) begin
case (rState)
`S_TXPORTMON128_NEXT: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_EVT_2;
end
`S_TXPORTMON128_EVT_2: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_TXN;
end
@ -194,7 +200,7 @@ always @ (*) begin
_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
// Read until we get a (valid) event
_rRead = (!rState[1] & !wEventData & !rAlmostFull); // !S_TXPORTMON128_TXN
_rRead = (!rState[2] & !(rState[1] & rEvent) & !wEventData & !rAlmostFull); // !S_TXPORTMON128_TXN
// Track detected events
_rEvent = wEventData;

26
fpga/riffa_hdl/tx_port_monitor_32.v
View File

@ -42,11 +42,12 @@
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTMON32_NEXT 5'b0_0001
`define S_TXPORTMON32_TXN 5'b0_0010
`define S_TXPORTMON32_READ 5'b0_0100
`define S_TXPORTMON32_END_0 5'b0_1000
`define S_TXPORTMON32_END_1 5'b1_0000
`define S_TXPORTMON32_NEXT 6'b00_0001
`define S_TXPORTMON32_EVT_2 6'b00_0010
`define S_TXPORTMON32_TXN 6'b00_0100
`define S_TXPORTMON32_READ 6'b00_1000
`define S_TXPORTMON32_END_0 6'b01_0000
`define S_TXPORTMON32_END_1 6'b10_0000
`timescale 1ns/1ns
module tx_port_monitor_32 #(
@ -84,7 +85,7 @@ module tx_port_monitor_32 #(
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [4:0] rState=`S_TXPORTMON32_NEXT, _rState=`S_TXPORTMON32_NEXT;
reg [5:0] rState=`S_TXPORTMON32_NEXT, _rState=`S_TXPORTMON32_NEXT;
reg rRead=0, _rRead=0;
reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
reg rEvent=0, _rEvent=0;
@ -101,7 +102,7 @@ reg rLenLE1Lo=0, _rLenLE1Lo=0;
reg rTxErr=0, _rTxErr=0;
wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[2]); // S_TXPORTMON32_READ
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[3]); // S_TXPORTMON32_READ
wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE1Lo)) & wPayloadData);
assign EVT_DATA_RD_EN = rRead;
@ -109,12 +110,12 @@ assign EVT_DATA_RD_EN = rRead;
assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
assign WR_EN = wPayloadData;
assign TXN = rState[1]; // S_TXPORTMON32_TXN
assign TXN = rState[2]; // S_TXPORTMON32_TXN
assign LAST = rReadOffLast[0];
assign OFF = rReadOffLast[31:1];
assign LEN = rReadLen;
assign WORDS_RECVD = rWordsRecvd;
assign DONE = !rState[2]; // !S_TXPORTMON32_READ
assign DONE = !rState[3]; // !S_TXPORTMON32_READ
@ -143,6 +144,11 @@ always @ (*) begin
_rState = `S_TXPORTMON32_TXN;
end
`S_TXPORTMON32_EVT_2: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_TXN;
end
`S_TXPORTMON32_TXN: begin // Don't read, wait until transaction has been acknowledged
if (ACK)
_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON32_END_0 : `S_TXPORTMON32_READ);
@ -198,7 +204,7 @@ always @ (*) begin
_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
// Read until we get a (valid) event
_rRead = (!rState[1] & !wEventData & !rAlmostFull); // !S_TXPORTMON32_TXN
_rRead = (!rState[2] & !(rState[1] & rEvent) & !wEventData & !rAlmostFull); // !S_TXPORTMON32_TXN
// Track detected events
_rEvent = wEventData;

26
fpga/riffa_hdl/tx_port_monitor_64.v
View File

@ -42,11 +42,12 @@
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTMON64_NEXT 5'b0_0001
`define S_TXPORTMON64_TXN 5'b0_0010
`define S_TXPORTMON64_READ 5'b0_0100
`define S_TXPORTMON64_END_0 5'b0_1000
`define S_TXPORTMON64_END_1 5'b1_0000
`define S_TXPORTMON64_NEXT 6'b00_0001
`define S_TXPORTMON64_EVT_2 6'b00_0010
`define S_TXPORTMON64_TXN 6'b00_0100
`define S_TXPORTMON64_READ 6'b00_1000
`define S_TXPORTMON64_END_0 6'b01_0000
`define S_TXPORTMON64_END_1 6'b10_0000
`timescale 1ns/1ns
module tx_port_monitor_64 #(
@ -84,7 +85,7 @@ module tx_port_monitor_64 #(
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [4:0] rState=`S_TXPORTMON64_NEXT, _rState=`S_TXPORTMON64_NEXT;
reg [5:0] rState=`S_TXPORTMON64_NEXT, _rState=`S_TXPORTMON64_NEXT;
reg rRead=0, _rRead=0;
reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
reg rEvent=0, _rEvent=0;
@ -100,7 +101,7 @@ reg rTxErr=0, _rTxErr=0;
wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[2]); // S_TXPORTMON64_READ
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[3]); // S_TXPORTMON64_READ
wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE2Lo)) & wPayloadData);
assign EVT_DATA_RD_EN = rRead;
@ -108,12 +109,12 @@ assign EVT_DATA_RD_EN = rRead;
assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
assign WR_EN = wPayloadData; // S_TXPORTMON64_READ
assign TXN = rState[1]; // S_TXPORTMON64_TXN
assign TXN = rState[2]; // S_TXPORTMON64_TXN
assign LAST = rReadData[0];
assign OFF = rReadData[31:1];
assign LEN = rReadData[63:32];
assign WORDS_RECVD = rWordsRecvd;
assign DONE = !rState[2]; // !S_TXPORTMON64_READ
assign DONE = !rState[3]; // !S_TXPORTMON64_READ
@ -138,6 +139,11 @@ always @ (*) begin
case (rState)
`S_TXPORTMON64_NEXT: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON64_EVT_2;
end
`S_TXPORTMON64_EVT_2: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON64_TXN;
end
@ -195,7 +201,7 @@ always @ (*) begin
_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
// Read until we get a (valid) event
_rRead = (!rState[1] & !wEventData & !rAlmostFull); // !S_TXPORTMON64_TXN
_rRead = (!rState[2] & !(rState[1] & rEvent) & !wEventData & !rAlmostFull); // !S_TXPORTMON64_TXN
// Track detected events
_rEvent = wEventData;