diff --git a/LICENSE b/LICENSE
index 6dac56b..8611a96 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,28 +1,34 @@
-Copyright (c) 2015, drichmond
-All rights reserved.
+----------------------------------------------------------------------
+Copyright (c) 2015, The Regents of the University of California All
+rights reserved.
 
 Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are
+met:
 
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
 
-* Redistributions in binary form must reproduce the above copyright notice,
-  this list of conditions and the following disclaimer in the documentation
-  and/or other materials provided with the distribution.
+    * Redistributions in binary form must reproduce the above
+      copyright notice, this list of conditions and the following
+      disclaimer in the documentation and/or other materials provided
+      with the distribution.
 
-* Neither the name of riffa-stable nor the names of its
-  contributors may be used to endorse or promote products derived from
-  this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+    * Neither the name of The Regents of the University of California
+      nor the names of its contributors may be used to endorse or
+      promote products derived from this software without specific
+      prior written permission.
 
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+DAMAGE.
+----------------------------------------------------------------------
diff --git a/c_c++/linux/x64/README.txt b/c_c++/linux/x64/README.txt
new file mode 100644
index 0000000..baeb4fb
--- /dev/null
+++ b/c_c++/linux/x64/README.txt
@@ -0,0 +1,3 @@
+The Linux C/C++ library is compiled and installed with the kernel driver. This
+directory contains a sample application subdirectory that you can use to test
+your design. 
diff --git a/c_c++/linux/x64/sample_app/Makefile b/c_c++/linux/x64/sample_app/Makefile
new file mode 100644
index 0000000..c326bcf
--- /dev/null
+++ b/c_c++/linux/x64/sample_app/Makefile
@@ -0,0 +1,27 @@
+program_NAME := testutil
+program_C_SRCS := $(wildcard *.c)
+program_CXX_SRCS := $(wildcard *.cpp)
+program_C_OBJS := ${program_C_SRCS:.c=.o}
+program_CXX_OBJS := ${program_CXX_SRCS:.cpp=.o}
+program_OBJS := $(program_C_OBJS) $(program_CXX_OBJS)
+program_INCLUDE_DIRS :=
+program_LIBRARY_DIRS :=
+program_LIBRARIES := riffa
+CPPFLAGS += -g
+
+CPPFLAGS += $(foreach includedir,$(program_INCLUDE_DIRS),-I$(includedir))
+LDFLAGS += $(foreach librarydir,$(program_LIBRARY_DIRS),-L$(librarydir))
+LDFLAGS += $(foreach library,$(program_LIBRARIES),-l$(library))
+
+.PHONY: all clean distclean
+
+all: $(program_NAME)
+
+$(program_NAME): $(program_OBJS)
+	$(CC) $(CPPFLAGS) $(program_OBJS) -o $(program_NAME) $(LDFLAGS)
+
+clean:
+	@- $(RM) $(program_NAME)
+	@- $(RM) $(program_OBJS)
+
+distclean: clean
diff --git a/c_c++/linux/x64/sample_app/README.txt b/c_c++/linux/x64/sample_app/README.txt
new file mode 100644
index 0000000..870fd4b
--- /dev/null
+++ b/c_c++/linux/x64/sample_app/README.txt
@@ -0,0 +1,8 @@
+The testutil example application works with the Verilog chnl_tester module
+which receives data and then sends data back to the workstation. 
+
+To compile the example application:
+
+make
+
+The riffa C/C++ library must be installed (it gets installed with the driver).
diff --git a/c_c++/linux/x64/sample_app/testutil.c b/c_c++/linux/x64/sample_app/testutil.c
new file mode 100644
index 0000000..abb2442
--- /dev/null
+++ b/c_c++/linux/x64/sample_app/testutil.c
@@ -0,0 +1,145 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include "timer.h"
+#include "riffa.h"
+
+int main(int argc, char** argv) {
+	fpga_t * fpga;
+	fpga_info_list info;
+	int option;
+	int i;
+	int id;
+	int chnl;
+	size_t numWords;
+	int sent;
+	int recvd;
+	unsigned int * sendBuffer;
+	unsigned int * recvBuffer;
+	GET_TIME_INIT(3);
+
+	if (argc < 2) {
+		printf("Usage: %s <option>\n", argv[0]);
+		return -1;
+	}
+
+	option = atoi(argv[1]);
+
+	if (option == 0) {	// List FPGA info
+		// Populate the fpga_info_list struct
+		if (fpga_list(&info) != 0) {
+			printf("Error populating fpga_info_list\n");
+			return -1;
+		}
+		printf("Number of devices: %d\n", info.num_fpgas);
+		for (i = 0; i < info.num_fpgas; i++) {
+			printf("%d: id:%d\n", i, info.id[i]);
+			printf("%d: num_chnls:%d\n", i, info.num_chnls[i]);
+			printf("%d: name:%s\n", i, info.name[i]);
+			printf("%d: vendor id:%04X\n", i, info.vendor_id[i]);
+			printf("%d: device id:%04X\n", i, info.device_id[i]);
+		}
+	}
+	else if (option == 1) { // Reset FPGA
+		if (argc < 3) {
+			printf("Usage: %s %d <fpga id>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Reset
+		fpga_reset(fpga);
+
+		// Done with device
+        fpga_close(fpga);
+	}
+	else if (option == 2) { // Send data, receive data
+		if (argc < 5) {
+			printf("Usage: %s %d <fpga id> <chnl> <num words to transfer>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+		chnl = atoi(argv[3]);
+		numWords = atoi(argv[4]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Malloc the arrays
+		sendBuffer = (unsigned int *)malloc(numWords<<2);
+		if (sendBuffer == NULL) {
+			printf("Could not malloc memory for sendBuffer\n");
+			fpga_close(fpga);
+			return -1;
+	    }
+		recvBuffer = (unsigned int *)malloc(numWords<<2);
+		if (recvBuffer == NULL) {
+			printf("Could not malloc memory for recvBuffer\n");
+			free(sendBuffer);
+			fpga_close(fpga);
+			return -1;
+	    }
+
+		// Initialize the data
+		for (i = 0; i < numWords; i++) {
+			sendBuffer[i] = i+1;
+			recvBuffer[i] = 0;
+		}
+
+		GET_TIME_VAL(0);
+
+		// Send the data
+		sent = fpga_send(fpga, chnl, sendBuffer, numWords, 0, 1, 25000);
+		printf("words sent: %d\n", sent);
+
+		GET_TIME_VAL(1);
+
+		if (sent != 0) {
+			// Recv the data
+			recvd = fpga_recv(fpga, chnl, recvBuffer, numWords, 25000);
+			printf("words recv: %d\n", recvd);
+		}
+
+		GET_TIME_VAL(2);
+
+		// Done with device
+        fpga_close(fpga);
+
+		// Display some data
+		for (i = 0; i < 20; i++) {
+			printf("recvBuffer[%d]: %d\n", i, recvBuffer[i]);
+		}
+
+		// Check the data
+		if (recvd != 0) {
+			for (i = 4; i < recvd; i++) {
+				if (recvBuffer[i] != sendBuffer[i]) {
+					printf("recvBuffer[%d]: %d, expected %d\n", i, recvBuffer[i], sendBuffer[i]);
+					break;
+				}
+			}
+
+			printf("send bw: %f MB/s %fms\n",
+				sent*4.0/1024/1024/((TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0))/1000.0),
+				(TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0)) );
+
+			printf("recv bw: %f MB/s %fms\n",
+				recvd*4.0/1024/1024/((TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1))/1000.0),
+				(TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1)) );
+		}
+	}
+
+	return 0;
+}
diff --git a/c_c++/linux/x64/sample_app/timer.h b/c_c++/linux/x64/sample_app/timer.h
new file mode 100644
index 0000000..623ad66
--- /dev/null
+++ b/c_c++/linux/x64/sample_app/timer.h
@@ -0,0 +1,8 @@
+#include <sys/time.h>
+
+#define GET_TIME_INIT(num) struct timeval _timers[num]
+
+#define GET_TIME_VAL(num) gettimeofday(&_timers[num], NULL)
+
+#define TIME_VAL_TO_MS(num) (((double)_timers[num].tv_sec*1000.0) + ((double)_timers[num].tv_usec/1000.0))
+
diff --git a/c_c++/linux/x86/README.txt b/c_c++/linux/x86/README.txt
new file mode 100644
index 0000000..baeb4fb
--- /dev/null
+++ b/c_c++/linux/x86/README.txt
@@ -0,0 +1,3 @@
+The Linux C/C++ library is compiled and installed with the kernel driver. This
+directory contains a sample application subdirectory that you can use to test
+your design. 
diff --git a/c_c++/linux/x86/sample_app/Makefile b/c_c++/linux/x86/sample_app/Makefile
new file mode 100644
index 0000000..c326bcf
--- /dev/null
+++ b/c_c++/linux/x86/sample_app/Makefile
@@ -0,0 +1,27 @@
+program_NAME := testutil
+program_C_SRCS := $(wildcard *.c)
+program_CXX_SRCS := $(wildcard *.cpp)
+program_C_OBJS := ${program_C_SRCS:.c=.o}
+program_CXX_OBJS := ${program_CXX_SRCS:.cpp=.o}
+program_OBJS := $(program_C_OBJS) $(program_CXX_OBJS)
+program_INCLUDE_DIRS :=
+program_LIBRARY_DIRS :=
+program_LIBRARIES := riffa
+CPPFLAGS += -g
+
+CPPFLAGS += $(foreach includedir,$(program_INCLUDE_DIRS),-I$(includedir))
+LDFLAGS += $(foreach librarydir,$(program_LIBRARY_DIRS),-L$(librarydir))
+LDFLAGS += $(foreach library,$(program_LIBRARIES),-l$(library))
+
+.PHONY: all clean distclean
+
+all: $(program_NAME)
+
+$(program_NAME): $(program_OBJS)
+	$(CC) $(CPPFLAGS) $(program_OBJS) -o $(program_NAME) $(LDFLAGS)
+
+clean:
+	@- $(RM) $(program_NAME)
+	@- $(RM) $(program_OBJS)
+
+distclean: clean
diff --git a/c_c++/linux/x86/sample_app/README.txt b/c_c++/linux/x86/sample_app/README.txt
new file mode 100644
index 0000000..870fd4b
--- /dev/null
+++ b/c_c++/linux/x86/sample_app/README.txt
@@ -0,0 +1,8 @@
+The testutil example application works with the Verilog chnl_tester module
+which receives data and then sends data back to the workstation. 
+
+To compile the example application:
+
+make
+
+The riffa C/C++ library must be installed (it gets installed with the driver).
diff --git a/c_c++/linux/x86/sample_app/testutil.c b/c_c++/linux/x86/sample_app/testutil.c
new file mode 100644
index 0000000..abb2442
--- /dev/null
+++ b/c_c++/linux/x86/sample_app/testutil.c
@@ -0,0 +1,145 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include "timer.h"
+#include "riffa.h"
+
+int main(int argc, char** argv) {
+	fpga_t * fpga;
+	fpga_info_list info;
+	int option;
+	int i;
+	int id;
+	int chnl;
+	size_t numWords;
+	int sent;
+	int recvd;
+	unsigned int * sendBuffer;
+	unsigned int * recvBuffer;
+	GET_TIME_INIT(3);
+
+	if (argc < 2) {
+		printf("Usage: %s <option>\n", argv[0]);
+		return -1;
+	}
+
+	option = atoi(argv[1]);
+
+	if (option == 0) {	// List FPGA info
+		// Populate the fpga_info_list struct
+		if (fpga_list(&info) != 0) {
+			printf("Error populating fpga_info_list\n");
+			return -1;
+		}
+		printf("Number of devices: %d\n", info.num_fpgas);
+		for (i = 0; i < info.num_fpgas; i++) {
+			printf("%d: id:%d\n", i, info.id[i]);
+			printf("%d: num_chnls:%d\n", i, info.num_chnls[i]);
+			printf("%d: name:%s\n", i, info.name[i]);
+			printf("%d: vendor id:%04X\n", i, info.vendor_id[i]);
+			printf("%d: device id:%04X\n", i, info.device_id[i]);
+		}
+	}
+	else if (option == 1) { // Reset FPGA
+		if (argc < 3) {
+			printf("Usage: %s %d <fpga id>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Reset
+		fpga_reset(fpga);
+
+		// Done with device
+        fpga_close(fpga);
+	}
+	else if (option == 2) { // Send data, receive data
+		if (argc < 5) {
+			printf("Usage: %s %d <fpga id> <chnl> <num words to transfer>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+		chnl = atoi(argv[3]);
+		numWords = atoi(argv[4]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Malloc the arrays
+		sendBuffer = (unsigned int *)malloc(numWords<<2);
+		if (sendBuffer == NULL) {
+			printf("Could not malloc memory for sendBuffer\n");
+			fpga_close(fpga);
+			return -1;
+	    }
+		recvBuffer = (unsigned int *)malloc(numWords<<2);
+		if (recvBuffer == NULL) {
+			printf("Could not malloc memory for recvBuffer\n");
+			free(sendBuffer);
+			fpga_close(fpga);
+			return -1;
+	    }
+
+		// Initialize the data
+		for (i = 0; i < numWords; i++) {
+			sendBuffer[i] = i+1;
+			recvBuffer[i] = 0;
+		}
+
+		GET_TIME_VAL(0);
+
+		// Send the data
+		sent = fpga_send(fpga, chnl, sendBuffer, numWords, 0, 1, 25000);
+		printf("words sent: %d\n", sent);
+
+		GET_TIME_VAL(1);
+
+		if (sent != 0) {
+			// Recv the data
+			recvd = fpga_recv(fpga, chnl, recvBuffer, numWords, 25000);
+			printf("words recv: %d\n", recvd);
+		}
+
+		GET_TIME_VAL(2);
+
+		// Done with device
+        fpga_close(fpga);
+
+		// Display some data
+		for (i = 0; i < 20; i++) {
+			printf("recvBuffer[%d]: %d\n", i, recvBuffer[i]);
+		}
+
+		// Check the data
+		if (recvd != 0) {
+			for (i = 4; i < recvd; i++) {
+				if (recvBuffer[i] != sendBuffer[i]) {
+					printf("recvBuffer[%d]: %d, expected %d\n", i, recvBuffer[i], sendBuffer[i]);
+					break;
+				}
+			}
+
+			printf("send bw: %f MB/s %fms\n",
+				sent*4.0/1024/1024/((TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0))/1000.0),
+				(TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0)) );
+
+			printf("recv bw: %f MB/s %fms\n",
+				recvd*4.0/1024/1024/((TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1))/1000.0),
+				(TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1)) );
+		}
+	}
+
+	return 0;
+}
diff --git a/c_c++/linux/x86/sample_app/timer.h b/c_c++/linux/x86/sample_app/timer.h
new file mode 100644
index 0000000..623ad66
--- /dev/null
+++ b/c_c++/linux/x86/sample_app/timer.h
@@ -0,0 +1,8 @@
+#include <sys/time.h>
+
+#define GET_TIME_INIT(num) struct timeval _timers[num]
+
+#define GET_TIME_VAL(num) gettimeofday(&_timers[num], NULL)
+
+#define TIME_VAL_TO_MS(num) (((double)_timers[num].tv_sec*1000.0) + ((double)_timers[num].tv_usec/1000.0))
+
diff --git a/c_c++/windows/x64/README.txt b/c_c++/windows/x64/README.txt
new file mode 100755
index 0000000..4acb562
--- /dev/null
+++ b/c_c++/windows/x64/README.txt
@@ -0,0 +1,14 @@
+To build the C/C++ library:
+
+windres.exe riffa.rc resource.o
+gcc.exe -m64 -c -o riffa.o riffa.c -D RIFFA_EXPORTS
+gcc.exe -m64 -o riffa.dll riffa.o resource.o -s -shared -Wl,--subsystem,windows,--out-implib,riffa.lib -luser32 -lsetupapi
+del riffa.lib
+gendef riffa.dll
+lib /def:riffa.def /machine:X64 /out:riffa.lib
+
+This will compile the resource file for the dll (metadata properties for the 
+.dll). This will also produce a .dll and .lib file. The .dll is the dynamic
+library. The .lib file is the import library. You will want to copy the .dll
+into say Windows\System32. You will want to use the .h file and the .lib files
+when compiling and linking your applications.
diff --git a/c_c++/windows/x64/riffa.c b/c_c++/windows/x64/riffa.c
new file mode 100755
index 0000000..dc40b64
--- /dev/null
+++ b/c_c++/windows/x64/riffa.c
@@ -0,0 +1,431 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.c
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#define INITGUID
+
+#include <windows.h>
+#include <setupapi.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "riffa_driver.h"
+#include "riffa.h"
+
+// The structure used to hold data transfer information
+typedef struct RIFFA_FPGA_CHNL_IO {
+	UINT32					Id;
+	UINT32					Chnl;
+	UINT32					Length;
+	UINT32					Offset;
+	UINT32					Last;
+	UINT64					Timeout;
+} RIFFA_FPGA_CHNL_IO, * PRIFFA_FPGA_CHNL_IO;
+
+// Represents the FPGA device
+struct fpga_t
+{
+	HANDLE dev;
+	int id;
+};
+
+HANDLE get_device(UINT32 index, BOOLEAN overlapped);
+DWORD fill_device_info(fpga_info_list * info);
+
+fpga_t * RIFFACALL fpga_open(int id) {
+	fpga_t * fpga;
+
+	// Allocate space for the fpga_dev
+	fpga = (fpga_t *)malloc(sizeof(fpga_t));
+	if (fpga == NULL)
+		return NULL;
+	fpga->id = id;
+
+	// Open the device handle.
+	fpga->dev = get_device(id, TRUE);
+	if (fpga->dev == INVALID_HANDLE_VALUE) {
+		free(fpga);
+		return NULL;
+	}
+
+	return fpga;
+}
+
+void RIFFACALL fpga_close(fpga_t * fpga) {
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return;
+	}
+
+	// Close the device handle.
+	CloseHandle(fpga->dev);
+	fpga->dev = NULL;
+
+	// Free the fpga_t struct
+	free(fpga);
+}
+
+int RIFFACALL fpga_send(fpga_t * fpga, int chnl, void * data, int len,
+	int destoff, int last, long long timeout) {
+	RIFFA_FPGA_CHNL_IO io;
+	OVERLAPPED overlapStruct = {0};
+	HANDLE evt;
+	BOOLEAN status;
+	ULONG wordsReturned;
+
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return 0;
+	}
+
+	// Initialize the RIFFA_FPGA_CHNL_IO struct
+	io.Id = fpga->id;
+	io.Chnl = chnl;
+	io.Length = len;
+	io.Offset = destoff;
+	io.Last = last;
+	io.Timeout = timeout;
+
+	// Create a thread specific event to wait on.
+	evt = CreateEvent(NULL, TRUE, TRUE, NULL);
+	overlapStruct.hEvent = evt;
+
+	// Call IOCTL with IOCTL_RIFFA_SEND
+	status = DeviceIoControl(fpga->dev, IOCTL_RIFFA_SEND, (LPVOID)&io,
+		sizeof(io), data, (len<<2), &wordsReturned, &overlapStruct);
+	if(!status) {
+		// Should be the IO Pending error
+		if(GetLastError() == ERROR_IO_PENDING) {
+			// Wait for the IOCTL to complete and get the return value
+			WaitForSingleObject(evt, INFINITE);
+			status = GetOverlappedResult(fpga->dev, &overlapStruct,
+				&wordsReturned, FALSE);
+			if(!status) {
+				if (GetLastError() == ERROR_OPERATION_ABORTED)
+					printf("Operation timed out or was aborted\n");
+				else
+					printf("Error in GetOverlappedResult: %d\n", GetLastError());
+			}
+		}
+		else {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+		}
+	}
+	return wordsReturned;
+}
+
+int RIFFACALL fpga_recv(fpga_t * fpga, int chnl, void * data, int len,
+	long long timeout) {
+	RIFFA_FPGA_CHNL_IO io;
+	OVERLAPPED overlapStruct = {0};
+	HANDLE evt;
+	BOOLEAN status;
+	ULONG wordsReturned;
+
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return 0;
+	}
+
+	// Initialize the RIFFA_FPGA_CHNL_IO struct
+	io.Id = fpga->id;
+	io.Chnl = chnl;
+	io.Length = len;
+	io.Timeout = timeout;
+
+	// Create a thread specific event to wait on.
+	evt = CreateEvent(NULL, TRUE, TRUE, NULL);
+	overlapStruct.hEvent = evt;
+
+	// Call IOCTL with IOCTL_RIFFA_RECV
+	status = DeviceIoControl(fpga->dev, IOCTL_RIFFA_RECV, (LPVOID)&io,
+		sizeof(io), data, (len<<2), &wordsReturned, &overlapStruct);
+	if(!status) {
+		// Should be the IO Pending error
+		if(GetLastError() == ERROR_IO_PENDING) {
+			// Wait for the IOCTL to complete and get the return value
+			WaitForSingleObject(evt, INFINITE);
+			status = GetOverlappedResult(fpga->dev, &overlapStruct,
+				&wordsReturned, FALSE);
+			if(!status) {
+				if (GetLastError() == ERROR_OPERATION_ABORTED)
+					printf("Operation timed out or was aborted\n");
+				else
+					printf("Error in GetOverlappedResult: %d\n", GetLastError());
+			}
+		}
+		else {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+		}
+	}
+	return wordsReturned;
+}
+
+void RIFFACALL fpga_reset(fpga_t * fpga) {
+	BOOLEAN status;
+	OVERLAPPED overlapStruct = {0};
+	ULONG wordsReturned;
+
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return;
+	}
+
+	// Call IOCTL with IOCTL_RIFFA_RESET. Must use the overlapped struct as the
+	// device was opened with overlap support.
+	status = DeviceIoControl(fpga->dev, IOCTL_RIFFA_RESET, NULL, 0, NULL, 0,
+		&wordsReturned, &overlapStruct);
+	if(!status) {
+		// Should be the IO Pending error
+		if(GetLastError() == ERROR_IO_PENDING) {
+			// Wait for the IOCTL to complete and get the return value
+			status = GetOverlappedResult(fpga->dev, &overlapStruct,
+				&wordsReturned, TRUE);
+			if(!status)
+				printf("Error in GetOverlappedResult: %d\n", GetLastError());
+		}
+		else {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+		}
+	}
+}
+
+int RIFFACALL fpga_list(fpga_info_list * list) {
+	// Populate the fpga_info_list struct
+	list->num_fpgas = 0;
+	return (int)fill_device_info(list);
+}
+
+/**
+ * Returns a handle to the FPGA device specified by index. On failure, returns
+ * an INVALID_HANDLE_VALUE. If the value of overlapped is TRUE, the device
+ * handle will be opened with flag FILE_FLAG_OVERLAPPED to signal that future
+ * operations will use overlapped IO. If the value of overlapped is FALSE, the
+ * device handle will be opened with flag FILE_ATTRIBUTE_NORMAL and no
+ * overlapped IO can be used with the returned device handle.
+ */
+HANDLE get_device(UINT32 index, BOOLEAN overlapped) {
+    PSP_DEVICE_INTERFACE_DETAIL_DATA devIntfDetail;
+    SP_DEVICE_INTERFACE_DATA devIntfData;
+    SP_DEVINFO_DATA devInfoData;
+    SECURITY_ATTRIBUTES secAttr;
+    HDEVINFO devInfo;
+    BOOLEAN status = TRUE;
+    ULONG size;
+    HANDLE dev;
+    DWORD flags;
+
+    //  Retreive the device information for all RIFFA devices.
+    devInfo = SetupDiGetClassDevs(&GUID_RIFFA_INTERFACE, NULL, NULL,
+    	DIGCF_DEVICEINTERFACE | DIGCF_PRESENT);
+	if (devInfo == INVALID_HANDLE_VALUE) {
+        printf("SetupDiGetClassDevs failed, Error: %d\n", GetLastError());
+        return INVALID_HANDLE_VALUE;
+	}
+
+    //  Initialize the appropriate data structures for the SetupDi calls.
+    devIntfData.cbSize = sizeof(SP_DEVICE_INTERFACE_DATA);
+    devInfoData.cbSize = sizeof(SP_DEVINFO_DATA);
+
+    //  Get information for specific device.
+    status = SetupDiEnumDeviceInterfaces(devInfo, NULL, (LPGUID)&GUID_RIFFA_INTERFACE,
+    	index, &devIntfData);
+    if (!status) {
+        printf("SetupDiEnumDeviceInterfaces failed, Error: %d\n", GetLastError());
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+    // Determine the size required for the devIntfData
+    SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, NULL, 0, &size, NULL);
+    if (GetLastError() != ERROR_INSUFFICIENT_BUFFER) {
+        printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+    devIntfDetail = (PSP_DEVICE_INTERFACE_DETAIL_DATA)malloc(size);
+    if (!devIntfDetail) {
+        printf("Insufficient memory.\n");
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+    // Initialize structure and retrieve data.
+    devIntfDetail->cbSize = sizeof(SP_DEVICE_INTERFACE_DETAIL_DATA);
+    status = SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, devIntfDetail,
+    	size, NULL, &devInfoData);
+    if (!status) {
+        printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+        free(devIntfDetail);
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+	// Prepare the security attributes for interitance.
+	secAttr.nLength = sizeof(SECURITY_ATTRIBUTES);
+	secAttr.bInheritHandle = TRUE;
+	secAttr.lpSecurityDescriptor = NULL;
+
+	// Get the device handle itself (finally!)
+	flags = (overlapped ? FILE_FLAG_OVERLAPPED : FILE_ATTRIBUTE_NORMAL);
+	flags = flags | FILE_FLAG_NO_BUFFERING;
+	dev = CreateFile(devIntfDetail->DevicePath, GENERIC_READ|GENERIC_WRITE,
+		FILE_SHARE_READ | FILE_SHARE_WRITE, &secAttr, OPEN_EXISTING, flags, NULL);
+	if (dev == INVALID_HANDLE_VALUE) {
+		printf("CreateFile failed.  Error:%d\n", GetLastError());
+        free(devIntfDetail);
+		SetupDiDestroyDeviceInfoList(devInfo);
+		return INVALID_HANDLE_VALUE;
+	}
+	free(devIntfDetail);
+	SetupDiDestroyDeviceInfoList(devInfo);
+
+    return dev;
+}
+
+/**
+ * Populates the specified fpga_info_list struct with FPGA information. Returns
+ * zero on success. On failure, returns an error code (positive value).
+ */
+DWORD fill_device_info(fpga_info_list * info) {
+    PSP_DEVICE_INTERFACE_DETAIL_DATA devIntfDetail;
+    SP_DEVICE_INTERFACE_DATA devIntfData;
+    SP_DEVINFO_DATA devInfoData;
+    HDEVINFO devInfo;
+    BOOLEAN status = TRUE;
+    ULONG size;
+    UINT32 i;
+    ULONG wordsReturned;
+    HANDLE dev;
+
+    //  Retreive the device information for all RIFFA devices.
+    devInfo = SetupDiGetClassDevs(&GUID_RIFFA_INTERFACE, NULL, NULL,
+    	DIGCF_DEVICEINTERFACE | DIGCF_PRESENT);
+	if (devInfo == INVALID_HANDLE_VALUE) {
+        printf("SetupDiGetClassDevs failed, Error: %d\n", GetLastError());
+        return GetLastError();
+	}
+
+    //  Initialize the appropriate data structures for the SetupDi calls.
+    devIntfData.cbSize = sizeof(SP_DEVICE_INTERFACE_DATA);
+    devInfoData.cbSize = sizeof(SP_DEVINFO_DATA);
+
+    //  Loop through the device list.
+    i = 0;
+    while (SetupDiEnumDeviceInterfaces(devInfo, NULL, (LPGUID)&GUID_RIFFA_INTERFACE,
+    	i, &devIntfData)) {
+        // Determine the size required for the devIntfData
+        SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, NULL, 0, &size, NULL);
+        if (GetLastError() != ERROR_INSUFFICIENT_BUFFER) {
+            printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+			SetupDiDestroyDeviceInfoList(devInfo);
+            return GetLastError();
+        }
+
+		// Create the SP_DEVICE_INTERFACE_DETAIL_DATA
+        devIntfDetail = (PSP_DEVICE_INTERFACE_DETAIL_DATA)malloc(size);
+        if (!devIntfDetail) {
+            printf("Insufficient memory.\n");
+			SetupDiDestroyDeviceInfoList(devInfo);
+            return ERROR_NOT_ENOUGH_MEMORY;
+        }
+
+		// Initialize structure and retrieve data.
+		devIntfDetail->cbSize = sizeof(SP_DEVICE_INTERFACE_DETAIL_DATA);
+		status = SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, devIntfDetail,
+			size, NULL, &devInfoData);
+		if (!status) {
+			printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+	        free(devIntfDetail);
+			SetupDiDestroyDeviceInfoList(devInfo);
+			return GetLastError();
+		}
+
+		// Get the device handle itself (no overlap)
+		dev = CreateFile(devIntfDetail->DevicePath, GENERIC_READ|GENERIC_WRITE,
+			FILE_SHARE_READ | FILE_SHARE_WRITE, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL);
+		if (dev == INVALID_HANDLE_VALUE) {
+			printf("CreateFile failed.  Error:%d\n", GetLastError());
+	        free(devIntfDetail);
+			SetupDiDestroyDeviceInfoList(devInfo);
+			return GetLastError();
+		}
+
+		// Call IOCTL with IOCTL_RIFFA_LIST
+		status = DeviceIoControl(dev, IOCTL_RIFFA_LIST, (LPVOID)&i, sizeof(i),
+			(LPVOID)info, sizeof(*info), &wordsReturned, NULL);
+		if (!status) {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+	        CloseHandle(dev);
+	        free(devIntfDetail);
+			SetupDiDestroyDeviceInfoList(devInfo);
+			return GetLastError();
+		}
+		info->num_fpgas = info->num_fpgas + 1;
+
+		// Done with the device
+		CloseHandle(dev);
+		free(devIntfDetail);
+
+        // Cycle through the available devices.
+        i++;
+    }
+
+	// Done with the DeviceInfo
+	SetupDiDestroyDeviceInfoList(devInfo);
+
+	return 0;
+}
+
+
+
diff --git a/c_c++/windows/x64/riffa.def b/c_c++/windows/x64/riffa.def
new file mode 100755
index 0000000..ab29750
--- /dev/null
+++ b/c_c++/windows/x64/riffa.def
@@ -0,0 +1,13 @@
+;
+; Definition file of riffa.dll
+; Automatic generated by gendef
+; written by Kai Tietz 2008
+;
+LIBRARY "riffa.dll"
+EXPORTS
+fpga_close
+fpga_list
+fpga_open
+fpga_recv
+fpga_reset
+fpga_send
diff --git a/c_c++/windows/x64/riffa.dll b/c_c++/windows/x64/riffa.dll
new file mode 100755
index 0000000..9a339e0
Binary files /dev/null and b/c_c++/windows/x64/riffa.dll differ
diff --git a/c_c++/windows/x64/riffa.exp b/c_c++/windows/x64/riffa.exp
new file mode 100755
index 0000000..3890312
Binary files /dev/null and b/c_c++/windows/x64/riffa.exp differ
diff --git a/c_c++/windows/x64/riffa.h b/c_c++/windows/x64/riffa.h
new file mode 100755
index 0000000..fb51d9a
--- /dev/null
+++ b/c_c++/windows/x64/riffa.h
@@ -0,0 +1,150 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.h
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#ifndef RIFFA_H
+#define RIFFA_H
+
+// Must RIFFA_EXPORTS *only* when building the DLL.
+#ifdef RIFFA_EXPORTS
+  #define RIFFAAPI __declspec(dllexport)
+#else
+  #define RIFFAAPI __declspec(dllimport)
+#endif
+
+// Define calling convention in one place, for convenience.
+#define RIFFACALL __cdecl
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Maximum number of RIFFA FPGAs
+#define RIFFA_MAX_NUM_FPGAS (5)
+
+// Holds FPGA information for installed RIFFA FPGAs
+struct fpga_info_list
+{
+	int num_fpgas;
+	int id[RIFFA_MAX_NUM_FPGAS];
+	int num_chnls[RIFFA_MAX_NUM_FPGAS];
+	char name[RIFFA_MAX_NUM_FPGAS][16];
+	int vendor_id[RIFFA_MAX_NUM_FPGAS];
+	int device_id[RIFFA_MAX_NUM_FPGAS];
+};
+typedef struct fpga_info_list fpga_info_list;
+
+// Represents the FPGA device
+struct fpga_t;
+typedef struct fpga_t fpga_t;
+
+/**
+ * Populates the fpga_info_list pointer with all FPGAs registered in the system.
+ * Returns 0 on success, non-zero on error.
+ */
+RIFFAAPI int RIFFACALL fpga_list(fpga_info_list * list);
+
+/**
+ * Initializes the FPGA specified by id. On success, returns a pointer to a
+ * fpga_t struct. On error, returns NULL. Each FPGA must be opened before any
+ * channels can be accessed. Once opened, any number of threads can use the
+ * fpga_t struct.
+ */
+RIFFAAPI fpga_t * RIFFACALL fpga_open(int id);
+
+/**
+ * Cleans up memory/resources for the FPGA specified by the fd descriptor.
+ */
+RIFFAAPI void RIFFACALL fpga_close(fpga_t * fpga);
+
+/**
+ * Sends len words (4 byte words) from data to FPGA channel chnl using the
+ * fpga_t struct. The FPGA channel will be sent len, destoff, and last. If last
+ * is 1, the channel should interpret the end of this send as the end of a
+ * transaction. If last is 0, the channel should wait for additional sends
+ * before the end of the transaction. If timeout is non-zero, this call will
+ * send data and wait up to timeout ms for the FPGA to respond (between
+ * packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads sending on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words sent.
+ */
+RIFFAAPI int RIFFACALL fpga_send(fpga_t * fpga, int chnl, void * data, int len,
+	int destoff, int last, long long timeout);
+
+/**
+ * Receives data from the FPGA channel chnl to the data pointer, using the
+ * fpga_t struct. The FPGA channel can send any amount of data, so the data
+ * array should be large enough to accommodate. The len parameter specifies the
+ * actual size of the data buffer in words (4 byte words). The FPGA channel will
+ * specify an offset which will determine where in the data array the data will
+ * start being written. If the amount of data (plus offset) exceed the size of
+ * the data array (len), then that data will be discarded. If timeout is
+ * non-zero, this call will wait up to timeout ms for the FPGA to respond
+ * (between packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads receiving on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words received to the data array.
+ */
+RIFFAAPI int RIFFACALL fpga_recv(fpga_t * fpga, int chnl, void * data, int len,
+	long long timeout);
+
+/**
+ * Resets the state of the FPGA and all transfers across all channels. This is
+ * meant to be used as an alternative to rebooting if an error occurs while
+ * sending/receiving. Calling this function while other threads are sending or
+ * receiving will result in unexpected behavior.
+ */
+RIFFAAPI void RIFFACALL fpga_reset(fpga_t * fpga);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c_c++/windows/x64/riffa.lib b/c_c++/windows/x64/riffa.lib
new file mode 100755
index 0000000..655788d
Binary files /dev/null and b/c_c++/windows/x64/riffa.lib differ
diff --git a/c_c++/windows/x64/riffa.rc b/c_c++/windows/x64/riffa.rc
new file mode 100755
index 0000000..48a72b2
--- /dev/null
+++ b/c_c++/windows/x64/riffa.rc
@@ -0,0 +1,83 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.rc
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+1 VERSIONINFO
+ FILEVERSION 1,0,0,0
+ PRODUCTVERSION 2,0,0,0
+ FILEFLAGSMASK 0x17L
+#ifdef _DEBUG
+ FILEFLAGS 0x1L
+#else
+ FILEFLAGS 0x0L
+#endif
+ FILEOS 0x4L
+ FILETYPE 0x1L
+ FILESUBTYPE 0x0L
+BEGIN
+    BLOCK "StringFileInfo"
+    BEGIN
+        BLOCK "040904b0"
+        BEGIN
+            VALUE "Comments", "RIFFA 64 bit Windows Library"
+            VALUE "CompanyName", "University of California, San Diego"
+            VALUE "FileDescription", "User 64 bit library for RIFFA."
+            VALUE "FileVersion", "1, 0, 0, 0"
+            VALUE "InternalName", "RIFFA"
+            VALUE "LegalCopyright", "Copyright © 2011 The Regents of the University of California. All Rights Reserved."
+            VALUE "OriginalFilename", "riffa.dll"
+            VALUE "ProductName", "RIFFA Library"
+            VALUE "ProductVersion", "2, 0, 0, 0"
+        END
+    END
+    BLOCK "VarFileInfo"
+    BEGIN
+        VALUE "Translation", 0x409, 1200
+    END
+END
\ No newline at end of file
diff --git a/c_c++/windows/x64/riffa_driver.h b/c_c++/windows/x64/riffa_driver.h
new file mode 100755
index 0000000..7368e86
--- /dev/null
+++ b/c_c++/windows/x64/riffa_driver.h
@@ -0,0 +1,19 @@
+//
+// The following value is arbitrarily chosen from the space defined
+// by Microsoft as being "for non-Microsoft use"
+//
+//
+// {40d49fb9-6085-4e1d-8753-822be944d7bb}
+DEFINE_GUID (GUID_RIFFA_INTERFACE,
+   0x40d49fb9, 0x6085, 0x4e1d, 0x87, 0x53, 0x82, 0x2b, 0xe9, 0x44, 0xd7, 0xbb);
+
+// The IOCTL function codes from 0x800 to 0xFFF are for customer use.
+#define IOCTL_RIFFA_SEND \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x900, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)
+#define IOCTL_RIFFA_RECV \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x901, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)
+#define IOCTL_RIFFA_LIST \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x902, METHOD_OUT_DIRECT ,FILE_ANY_ACCESS)
+#define IOCTL_RIFFA_RESET \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x903, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)
+
diff --git a/c_c++/windows/x64/sample_app/README.txt b/c_c++/windows/x64/sample_app/README.txt
new file mode 100755
index 0000000..90ce396
--- /dev/null
+++ b/c_c++/windows/x64/sample_app/README.txt
@@ -0,0 +1,10 @@
+The testutil example application works with the Verilog chnl_tester module
+which receives data and then sends data back to the workstation. 
+
+To compile the example application:
+
+gcc.exe -o testutil.exe testutil.c -L. -lriffa
+
+The riffa.lib import library must be in the directory specified by the -L 
+parameter (in this example, the current directory). The riffa.h header must be
+in the same directory as testutil.c.
diff --git a/c_c++/windows/x64/sample_app/riffa.h b/c_c++/windows/x64/sample_app/riffa.h
new file mode 100755
index 0000000..fb51d9a
--- /dev/null
+++ b/c_c++/windows/x64/sample_app/riffa.h
@@ -0,0 +1,150 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.h
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#ifndef RIFFA_H
+#define RIFFA_H
+
+// Must RIFFA_EXPORTS *only* when building the DLL.
+#ifdef RIFFA_EXPORTS
+  #define RIFFAAPI __declspec(dllexport)
+#else
+  #define RIFFAAPI __declspec(dllimport)
+#endif
+
+// Define calling convention in one place, for convenience.
+#define RIFFACALL __cdecl
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Maximum number of RIFFA FPGAs
+#define RIFFA_MAX_NUM_FPGAS (5)
+
+// Holds FPGA information for installed RIFFA FPGAs
+struct fpga_info_list
+{
+	int num_fpgas;
+	int id[RIFFA_MAX_NUM_FPGAS];
+	int num_chnls[RIFFA_MAX_NUM_FPGAS];
+	char name[RIFFA_MAX_NUM_FPGAS][16];
+	int vendor_id[RIFFA_MAX_NUM_FPGAS];
+	int device_id[RIFFA_MAX_NUM_FPGAS];
+};
+typedef struct fpga_info_list fpga_info_list;
+
+// Represents the FPGA device
+struct fpga_t;
+typedef struct fpga_t fpga_t;
+
+/**
+ * Populates the fpga_info_list pointer with all FPGAs registered in the system.
+ * Returns 0 on success, non-zero on error.
+ */
+RIFFAAPI int RIFFACALL fpga_list(fpga_info_list * list);
+
+/**
+ * Initializes the FPGA specified by id. On success, returns a pointer to a
+ * fpga_t struct. On error, returns NULL. Each FPGA must be opened before any
+ * channels can be accessed. Once opened, any number of threads can use the
+ * fpga_t struct.
+ */
+RIFFAAPI fpga_t * RIFFACALL fpga_open(int id);
+
+/**
+ * Cleans up memory/resources for the FPGA specified by the fd descriptor.
+ */
+RIFFAAPI void RIFFACALL fpga_close(fpga_t * fpga);
+
+/**
+ * Sends len words (4 byte words) from data to FPGA channel chnl using the
+ * fpga_t struct. The FPGA channel will be sent len, destoff, and last. If last
+ * is 1, the channel should interpret the end of this send as the end of a
+ * transaction. If last is 0, the channel should wait for additional sends
+ * before the end of the transaction. If timeout is non-zero, this call will
+ * send data and wait up to timeout ms for the FPGA to respond (between
+ * packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads sending on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words sent.
+ */
+RIFFAAPI int RIFFACALL fpga_send(fpga_t * fpga, int chnl, void * data, int len,
+	int destoff, int last, long long timeout);
+
+/**
+ * Receives data from the FPGA channel chnl to the data pointer, using the
+ * fpga_t struct. The FPGA channel can send any amount of data, so the data
+ * array should be large enough to accommodate. The len parameter specifies the
+ * actual size of the data buffer in words (4 byte words). The FPGA channel will
+ * specify an offset which will determine where in the data array the data will
+ * start being written. If the amount of data (plus offset) exceed the size of
+ * the data array (len), then that data will be discarded. If timeout is
+ * non-zero, this call will wait up to timeout ms for the FPGA to respond
+ * (between packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads receiving on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words received to the data array.
+ */
+RIFFAAPI int RIFFACALL fpga_recv(fpga_t * fpga, int chnl, void * data, int len,
+	long long timeout);
+
+/**
+ * Resets the state of the FPGA and all transfers across all channels. This is
+ * meant to be used as an alternative to rebooting if an error occurs while
+ * sending/receiving. Calling this function while other threads are sending or
+ * receiving will result in unexpected behavior.
+ */
+RIFFAAPI void RIFFACALL fpga_reset(fpga_t * fpga);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c_c++/windows/x64/sample_app/riffa.lib b/c_c++/windows/x64/sample_app/riffa.lib
new file mode 100755
index 0000000..02609f6
Binary files /dev/null and b/c_c++/windows/x64/sample_app/riffa.lib differ
diff --git a/c_c++/windows/x64/sample_app/testutil.c b/c_c++/windows/x64/sample_app/testutil.c
new file mode 100755
index 0000000..96be35a
--- /dev/null
+++ b/c_c++/windows/x64/sample_app/testutil.c
@@ -0,0 +1,146 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include <windows.h>
+#include "timer.h"
+#include "riffa.h"
+
+int main(int argc, char** argv) {
+	fpga_t * fpga;
+	fpga_info_list info;
+	int option;
+	int i;
+	int id;
+	int chnl;
+	size_t numWords;
+	int sent;
+	int recvd;
+	unsigned int * sendBuffer;
+	unsigned int * recvBuffer;
+	GET_TIME_INIT(3);
+
+	if (argc < 2) {
+		printf("Usage: %s <option>\n", argv[0]);
+		return -1;
+	}
+
+	option = atoi(argv[1]);
+
+	if (option == 0) {	// List FPGA info
+		// Populate the fpga_info_list struct
+		if (fpga_list(&info) != 0) {
+			printf("Error populating fpga_info_list\n");
+			return -1;
+		}
+		printf("Number of devices: %d\n", info.num_fpgas);
+		for (i = 0; i < info.num_fpgas; i++) {
+			printf("%d: id:%d\n", i, info.id[i]);
+			printf("%d: num_chnls:%d\n", i, info.num_chnls[i]);
+			printf("%d: name:%s\n", i, info.name[i]);
+			printf("%d: vendor id:%04X\n", i, info.vendor_id[i]);
+			printf("%d: device id:%04X\n", i, info.device_id[i]);
+		}
+	}
+	else if (option == 1) { // Reset FPGA
+		if (argc < 3) {
+			printf("Usage: %s %d <fpga id>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Reset
+		fpga_reset(fpga);
+
+		// Done with device
+        fpga_close(fpga);
+	}
+	else if (option == 2) { // Send data, receive data
+		if (argc < 5) {
+			printf("Usage: %s %d <fpga id> <chnl> <num words to transfer>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+		chnl = atoi(argv[3]);
+		numWords = atoi(argv[4]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Malloc the arrays
+		sendBuffer = (unsigned int *)malloc(numWords<<2);
+		if (sendBuffer == NULL) {
+			printf("Could not malloc memory for sendBuffer\n");
+			fpga_close(fpga);
+			return -1;
+	    }
+		recvBuffer = (unsigned int *)malloc(numWords<<2);
+		if (recvBuffer == NULL) {
+			printf("Could not malloc memory for recvBuffer\n");
+			free(sendBuffer);
+			fpga_close(fpga);
+			return -1;
+	    }
+
+		// Initialize the data
+		for (i = 0; i < numWords; i++) {
+			sendBuffer[i] = i+1;
+			recvBuffer[i] = 0;
+		}
+
+		GET_TIME_VAL(0);
+
+		// Send the data
+		sent = fpga_send(fpga, chnl, sendBuffer, numWords, 0, 1, 25000);
+		printf("words sent: %d\n", sent);
+
+		GET_TIME_VAL(1);
+
+		if (sent != 0) {
+			// Recv the data
+			recvd = fpga_recv(fpga, chnl, recvBuffer, numWords, 25000);
+			printf("words recv: %d\n", recvd);
+		}
+
+		GET_TIME_VAL(2);
+
+		// Done with device
+        fpga_close(fpga);
+
+		// Display some data
+		for (i = 0; i < 20; i++) {
+			printf("recvBuffer[%d]: %d\n", i, recvBuffer[i]);
+		}
+
+		// Check the data
+		if (recvd != 0) {
+			for (i = 4; i < recvd; i++) {
+				if (recvBuffer[i] != sendBuffer[i]) {
+					printf("recvBuffer[%d]: %d, expected %d\n", i, recvBuffer[i], sendBuffer[i]);
+					break;
+				}
+			}
+
+			printf("send bw: %f MB/s %fms\n",
+				sent*4.0/1024/1024/((TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0))/1000.0),
+				(TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0)) );
+
+			printf("recv bw: %f MB/s %fms\n",
+				recvd*4.0/1024/1024/((TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1))/1000.0),
+				(TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1)) );
+		}
+	}
+
+	return 0;
+}
diff --git a/c_c++/windows/x64/sample_app/testutil.exe b/c_c++/windows/x64/sample_app/testutil.exe
new file mode 100644
index 0000000..bd49599
Binary files /dev/null and b/c_c++/windows/x64/sample_app/testutil.exe differ
diff --git a/c_c++/windows/x64/sample_app/timer.h b/c_c++/windows/x64/sample_app/timer.h
new file mode 100755
index 0000000..15b64a2
--- /dev/null
+++ b/c_c++/windows/x64/sample_app/timer.h
@@ -0,0 +1,7 @@
+#include <windows.h>
+
+#define GET_TIME_INIT(num) LARGE_INTEGER _timers[num]; LARGE_INTEGER _freq; QueryPerformanceFrequency(&_freq)
+
+#define GET_TIME_VAL(num) QueryPerformanceCounter(&_timers[num])
+
+#define TIME_VAL_TO_MS(num) ((double)_timers[num].QuadPart*1000.0/_freq.QuadPart)
\ No newline at end of file
diff --git a/c_c++/windows/x86/README.txt b/c_c++/windows/x86/README.txt
new file mode 100755
index 0000000..34f2557
--- /dev/null
+++ b/c_c++/windows/x86/README.txt
@@ -0,0 +1,14 @@
+To build the C/C++ library:
+
+windres.exe riffa.rc resource.o
+gcc.exe -c -o riffa.o riffa.c -D RIFFA_EXPORTS
+gcc.exe -o riffa.dll riffa.o resource.o -s -shared -Wl,--subsystem,windows,--out-implib,riffa.lib -luser32 -lsetupapi
+del riffa.lib
+gendef riffa.dll
+lib /def:riffa.def /machine:x86 /out:riffa.lib
+
+This will compile the resource file for the dll (metadata properties for the 
+.dll). This will also produce a .dll and .lib file. The .dll is the dynamic
+library. The .lib file is the import library. You will want to copy the .dll
+into say Windows\System32. You will want to use the .h file and the .lib files
+when compiling and linking your applications.
diff --git a/c_c++/windows/x86/riffa.c b/c_c++/windows/x86/riffa.c
new file mode 100755
index 0000000..dc40b64
--- /dev/null
+++ b/c_c++/windows/x86/riffa.c
@@ -0,0 +1,431 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.c
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#define INITGUID
+
+#include <windows.h>
+#include <setupapi.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "riffa_driver.h"
+#include "riffa.h"
+
+// The structure used to hold data transfer information
+typedef struct RIFFA_FPGA_CHNL_IO {
+	UINT32					Id;
+	UINT32					Chnl;
+	UINT32					Length;
+	UINT32					Offset;
+	UINT32					Last;
+	UINT64					Timeout;
+} RIFFA_FPGA_CHNL_IO, * PRIFFA_FPGA_CHNL_IO;
+
+// Represents the FPGA device
+struct fpga_t
+{
+	HANDLE dev;
+	int id;
+};
+
+HANDLE get_device(UINT32 index, BOOLEAN overlapped);
+DWORD fill_device_info(fpga_info_list * info);
+
+fpga_t * RIFFACALL fpga_open(int id) {
+	fpga_t * fpga;
+
+	// Allocate space for the fpga_dev
+	fpga = (fpga_t *)malloc(sizeof(fpga_t));
+	if (fpga == NULL)
+		return NULL;
+	fpga->id = id;
+
+	// Open the device handle.
+	fpga->dev = get_device(id, TRUE);
+	if (fpga->dev == INVALID_HANDLE_VALUE) {
+		free(fpga);
+		return NULL;
+	}
+
+	return fpga;
+}
+
+void RIFFACALL fpga_close(fpga_t * fpga) {
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return;
+	}
+
+	// Close the device handle.
+	CloseHandle(fpga->dev);
+	fpga->dev = NULL;
+
+	// Free the fpga_t struct
+	free(fpga);
+}
+
+int RIFFACALL fpga_send(fpga_t * fpga, int chnl, void * data, int len,
+	int destoff, int last, long long timeout) {
+	RIFFA_FPGA_CHNL_IO io;
+	OVERLAPPED overlapStruct = {0};
+	HANDLE evt;
+	BOOLEAN status;
+	ULONG wordsReturned;
+
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return 0;
+	}
+
+	// Initialize the RIFFA_FPGA_CHNL_IO struct
+	io.Id = fpga->id;
+	io.Chnl = chnl;
+	io.Length = len;
+	io.Offset = destoff;
+	io.Last = last;
+	io.Timeout = timeout;
+
+	// Create a thread specific event to wait on.
+	evt = CreateEvent(NULL, TRUE, TRUE, NULL);
+	overlapStruct.hEvent = evt;
+
+	// Call IOCTL with IOCTL_RIFFA_SEND
+	status = DeviceIoControl(fpga->dev, IOCTL_RIFFA_SEND, (LPVOID)&io,
+		sizeof(io), data, (len<<2), &wordsReturned, &overlapStruct);
+	if(!status) {
+		// Should be the IO Pending error
+		if(GetLastError() == ERROR_IO_PENDING) {
+			// Wait for the IOCTL to complete and get the return value
+			WaitForSingleObject(evt, INFINITE);
+			status = GetOverlappedResult(fpga->dev, &overlapStruct,
+				&wordsReturned, FALSE);
+			if(!status) {
+				if (GetLastError() == ERROR_OPERATION_ABORTED)
+					printf("Operation timed out or was aborted\n");
+				else
+					printf("Error in GetOverlappedResult: %d\n", GetLastError());
+			}
+		}
+		else {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+		}
+	}
+	return wordsReturned;
+}
+
+int RIFFACALL fpga_recv(fpga_t * fpga, int chnl, void * data, int len,
+	long long timeout) {
+	RIFFA_FPGA_CHNL_IO io;
+	OVERLAPPED overlapStruct = {0};
+	HANDLE evt;
+	BOOLEAN status;
+	ULONG wordsReturned;
+
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return 0;
+	}
+
+	// Initialize the RIFFA_FPGA_CHNL_IO struct
+	io.Id = fpga->id;
+	io.Chnl = chnl;
+	io.Length = len;
+	io.Timeout = timeout;
+
+	// Create a thread specific event to wait on.
+	evt = CreateEvent(NULL, TRUE, TRUE, NULL);
+	overlapStruct.hEvent = evt;
+
+	// Call IOCTL with IOCTL_RIFFA_RECV
+	status = DeviceIoControl(fpga->dev, IOCTL_RIFFA_RECV, (LPVOID)&io,
+		sizeof(io), data, (len<<2), &wordsReturned, &overlapStruct);
+	if(!status) {
+		// Should be the IO Pending error
+		if(GetLastError() == ERROR_IO_PENDING) {
+			// Wait for the IOCTL to complete and get the return value
+			WaitForSingleObject(evt, INFINITE);
+			status = GetOverlappedResult(fpga->dev, &overlapStruct,
+				&wordsReturned, FALSE);
+			if(!status) {
+				if (GetLastError() == ERROR_OPERATION_ABORTED)
+					printf("Operation timed out or was aborted\n");
+				else
+					printf("Error in GetOverlappedResult: %d\n", GetLastError());
+			}
+		}
+		else {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+		}
+	}
+	return wordsReturned;
+}
+
+void RIFFACALL fpga_reset(fpga_t * fpga) {
+	BOOLEAN status;
+	OVERLAPPED overlapStruct = {0};
+	ULONG wordsReturned;
+
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return;
+	}
+
+	// Call IOCTL with IOCTL_RIFFA_RESET. Must use the overlapped struct as the
+	// device was opened with overlap support.
+	status = DeviceIoControl(fpga->dev, IOCTL_RIFFA_RESET, NULL, 0, NULL, 0,
+		&wordsReturned, &overlapStruct);
+	if(!status) {
+		// Should be the IO Pending error
+		if(GetLastError() == ERROR_IO_PENDING) {
+			// Wait for the IOCTL to complete and get the return value
+			status = GetOverlappedResult(fpga->dev, &overlapStruct,
+				&wordsReturned, TRUE);
+			if(!status)
+				printf("Error in GetOverlappedResult: %d\n", GetLastError());
+		}
+		else {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+		}
+	}
+}
+
+int RIFFACALL fpga_list(fpga_info_list * list) {
+	// Populate the fpga_info_list struct
+	list->num_fpgas = 0;
+	return (int)fill_device_info(list);
+}
+
+/**
+ * Returns a handle to the FPGA device specified by index. On failure, returns
+ * an INVALID_HANDLE_VALUE. If the value of overlapped is TRUE, the device
+ * handle will be opened with flag FILE_FLAG_OVERLAPPED to signal that future
+ * operations will use overlapped IO. If the value of overlapped is FALSE, the
+ * device handle will be opened with flag FILE_ATTRIBUTE_NORMAL and no
+ * overlapped IO can be used with the returned device handle.
+ */
+HANDLE get_device(UINT32 index, BOOLEAN overlapped) {
+    PSP_DEVICE_INTERFACE_DETAIL_DATA devIntfDetail;
+    SP_DEVICE_INTERFACE_DATA devIntfData;
+    SP_DEVINFO_DATA devInfoData;
+    SECURITY_ATTRIBUTES secAttr;
+    HDEVINFO devInfo;
+    BOOLEAN status = TRUE;
+    ULONG size;
+    HANDLE dev;
+    DWORD flags;
+
+    //  Retreive the device information for all RIFFA devices.
+    devInfo = SetupDiGetClassDevs(&GUID_RIFFA_INTERFACE, NULL, NULL,
+    	DIGCF_DEVICEINTERFACE | DIGCF_PRESENT);
+	if (devInfo == INVALID_HANDLE_VALUE) {
+        printf("SetupDiGetClassDevs failed, Error: %d\n", GetLastError());
+        return INVALID_HANDLE_VALUE;
+	}
+
+    //  Initialize the appropriate data structures for the SetupDi calls.
+    devIntfData.cbSize = sizeof(SP_DEVICE_INTERFACE_DATA);
+    devInfoData.cbSize = sizeof(SP_DEVINFO_DATA);
+
+    //  Get information for specific device.
+    status = SetupDiEnumDeviceInterfaces(devInfo, NULL, (LPGUID)&GUID_RIFFA_INTERFACE,
+    	index, &devIntfData);
+    if (!status) {
+        printf("SetupDiEnumDeviceInterfaces failed, Error: %d\n", GetLastError());
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+    // Determine the size required for the devIntfData
+    SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, NULL, 0, &size, NULL);
+    if (GetLastError() != ERROR_INSUFFICIENT_BUFFER) {
+        printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+    devIntfDetail = (PSP_DEVICE_INTERFACE_DETAIL_DATA)malloc(size);
+    if (!devIntfDetail) {
+        printf("Insufficient memory.\n");
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+    // Initialize structure and retrieve data.
+    devIntfDetail->cbSize = sizeof(SP_DEVICE_INTERFACE_DETAIL_DATA);
+    status = SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, devIntfDetail,
+    	size, NULL, &devInfoData);
+    if (!status) {
+        printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+        free(devIntfDetail);
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+	// Prepare the security attributes for interitance.
+	secAttr.nLength = sizeof(SECURITY_ATTRIBUTES);
+	secAttr.bInheritHandle = TRUE;
+	secAttr.lpSecurityDescriptor = NULL;
+
+	// Get the device handle itself (finally!)
+	flags = (overlapped ? FILE_FLAG_OVERLAPPED : FILE_ATTRIBUTE_NORMAL);
+	flags = flags | FILE_FLAG_NO_BUFFERING;
+	dev = CreateFile(devIntfDetail->DevicePath, GENERIC_READ|GENERIC_WRITE,
+		FILE_SHARE_READ | FILE_SHARE_WRITE, &secAttr, OPEN_EXISTING, flags, NULL);
+	if (dev == INVALID_HANDLE_VALUE) {
+		printf("CreateFile failed.  Error:%d\n", GetLastError());
+        free(devIntfDetail);
+		SetupDiDestroyDeviceInfoList(devInfo);
+		return INVALID_HANDLE_VALUE;
+	}
+	free(devIntfDetail);
+	SetupDiDestroyDeviceInfoList(devInfo);
+
+    return dev;
+}
+
+/**
+ * Populates the specified fpga_info_list struct with FPGA information. Returns
+ * zero on success. On failure, returns an error code (positive value).
+ */
+DWORD fill_device_info(fpga_info_list * info) {
+    PSP_DEVICE_INTERFACE_DETAIL_DATA devIntfDetail;
+    SP_DEVICE_INTERFACE_DATA devIntfData;
+    SP_DEVINFO_DATA devInfoData;
+    HDEVINFO devInfo;
+    BOOLEAN status = TRUE;
+    ULONG size;
+    UINT32 i;
+    ULONG wordsReturned;
+    HANDLE dev;
+
+    //  Retreive the device information for all RIFFA devices.
+    devInfo = SetupDiGetClassDevs(&GUID_RIFFA_INTERFACE, NULL, NULL,
+    	DIGCF_DEVICEINTERFACE | DIGCF_PRESENT);
+	if (devInfo == INVALID_HANDLE_VALUE) {
+        printf("SetupDiGetClassDevs failed, Error: %d\n", GetLastError());
+        return GetLastError();
+	}
+
+    //  Initialize the appropriate data structures for the SetupDi calls.
+    devIntfData.cbSize = sizeof(SP_DEVICE_INTERFACE_DATA);
+    devInfoData.cbSize = sizeof(SP_DEVINFO_DATA);
+
+    //  Loop through the device list.
+    i = 0;
+    while (SetupDiEnumDeviceInterfaces(devInfo, NULL, (LPGUID)&GUID_RIFFA_INTERFACE,
+    	i, &devIntfData)) {
+        // Determine the size required for the devIntfData
+        SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, NULL, 0, &size, NULL);
+        if (GetLastError() != ERROR_INSUFFICIENT_BUFFER) {
+            printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+			SetupDiDestroyDeviceInfoList(devInfo);
+            return GetLastError();
+        }
+
+		// Create the SP_DEVICE_INTERFACE_DETAIL_DATA
+        devIntfDetail = (PSP_DEVICE_INTERFACE_DETAIL_DATA)malloc(size);
+        if (!devIntfDetail) {
+            printf("Insufficient memory.\n");
+			SetupDiDestroyDeviceInfoList(devInfo);
+            return ERROR_NOT_ENOUGH_MEMORY;
+        }
+
+		// Initialize structure and retrieve data.
+		devIntfDetail->cbSize = sizeof(SP_DEVICE_INTERFACE_DETAIL_DATA);
+		status = SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, devIntfDetail,
+			size, NULL, &devInfoData);
+		if (!status) {
+			printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+	        free(devIntfDetail);
+			SetupDiDestroyDeviceInfoList(devInfo);
+			return GetLastError();
+		}
+
+		// Get the device handle itself (no overlap)
+		dev = CreateFile(devIntfDetail->DevicePath, GENERIC_READ|GENERIC_WRITE,
+			FILE_SHARE_READ | FILE_SHARE_WRITE, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL);
+		if (dev == INVALID_HANDLE_VALUE) {
+			printf("CreateFile failed.  Error:%d\n", GetLastError());
+	        free(devIntfDetail);
+			SetupDiDestroyDeviceInfoList(devInfo);
+			return GetLastError();
+		}
+
+		// Call IOCTL with IOCTL_RIFFA_LIST
+		status = DeviceIoControl(dev, IOCTL_RIFFA_LIST, (LPVOID)&i, sizeof(i),
+			(LPVOID)info, sizeof(*info), &wordsReturned, NULL);
+		if (!status) {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+	        CloseHandle(dev);
+	        free(devIntfDetail);
+			SetupDiDestroyDeviceInfoList(devInfo);
+			return GetLastError();
+		}
+		info->num_fpgas = info->num_fpgas + 1;
+
+		// Done with the device
+		CloseHandle(dev);
+		free(devIntfDetail);
+
+        // Cycle through the available devices.
+        i++;
+    }
+
+	// Done with the DeviceInfo
+	SetupDiDestroyDeviceInfoList(devInfo);
+
+	return 0;
+}
+
+
+
diff --git a/c_c++/windows/x86/riffa.def b/c_c++/windows/x86/riffa.def
new file mode 100755
index 0000000..ab29750
--- /dev/null
+++ b/c_c++/windows/x86/riffa.def
@@ -0,0 +1,13 @@
+;
+; Definition file of riffa.dll
+; Automatic generated by gendef
+; written by Kai Tietz 2008
+;
+LIBRARY "riffa.dll"
+EXPORTS
+fpga_close
+fpga_list
+fpga_open
+fpga_recv
+fpga_reset
+fpga_send
diff --git a/c_c++/windows/x86/riffa.dll b/c_c++/windows/x86/riffa.dll
new file mode 100755
index 0000000..74e713d
Binary files /dev/null and b/c_c++/windows/x86/riffa.dll differ
diff --git a/c_c++/windows/x86/riffa.exp b/c_c++/windows/x86/riffa.exp
new file mode 100755
index 0000000..46fa403
Binary files /dev/null and b/c_c++/windows/x86/riffa.exp differ
diff --git a/c_c++/windows/x86/riffa.h b/c_c++/windows/x86/riffa.h
new file mode 100755
index 0000000..fb51d9a
--- /dev/null
+++ b/c_c++/windows/x86/riffa.h
@@ -0,0 +1,150 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.h
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#ifndef RIFFA_H
+#define RIFFA_H
+
+// Must RIFFA_EXPORTS *only* when building the DLL.
+#ifdef RIFFA_EXPORTS
+  #define RIFFAAPI __declspec(dllexport)
+#else
+  #define RIFFAAPI __declspec(dllimport)
+#endif
+
+// Define calling convention in one place, for convenience.
+#define RIFFACALL __cdecl
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Maximum number of RIFFA FPGAs
+#define RIFFA_MAX_NUM_FPGAS (5)
+
+// Holds FPGA information for installed RIFFA FPGAs
+struct fpga_info_list
+{
+	int num_fpgas;
+	int id[RIFFA_MAX_NUM_FPGAS];
+	int num_chnls[RIFFA_MAX_NUM_FPGAS];
+	char name[RIFFA_MAX_NUM_FPGAS][16];
+	int vendor_id[RIFFA_MAX_NUM_FPGAS];
+	int device_id[RIFFA_MAX_NUM_FPGAS];
+};
+typedef struct fpga_info_list fpga_info_list;
+
+// Represents the FPGA device
+struct fpga_t;
+typedef struct fpga_t fpga_t;
+
+/**
+ * Populates the fpga_info_list pointer with all FPGAs registered in the system.
+ * Returns 0 on success, non-zero on error.
+ */
+RIFFAAPI int RIFFACALL fpga_list(fpga_info_list * list);
+
+/**
+ * Initializes the FPGA specified by id. On success, returns a pointer to a
+ * fpga_t struct. On error, returns NULL. Each FPGA must be opened before any
+ * channels can be accessed. Once opened, any number of threads can use the
+ * fpga_t struct.
+ */
+RIFFAAPI fpga_t * RIFFACALL fpga_open(int id);
+
+/**
+ * Cleans up memory/resources for the FPGA specified by the fd descriptor.
+ */
+RIFFAAPI void RIFFACALL fpga_close(fpga_t * fpga);
+
+/**
+ * Sends len words (4 byte words) from data to FPGA channel chnl using the
+ * fpga_t struct. The FPGA channel will be sent len, destoff, and last. If last
+ * is 1, the channel should interpret the end of this send as the end of a
+ * transaction. If last is 0, the channel should wait for additional sends
+ * before the end of the transaction. If timeout is non-zero, this call will
+ * send data and wait up to timeout ms for the FPGA to respond (between
+ * packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads sending on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words sent.
+ */
+RIFFAAPI int RIFFACALL fpga_send(fpga_t * fpga, int chnl, void * data, int len,
+	int destoff, int last, long long timeout);
+
+/**
+ * Receives data from the FPGA channel chnl to the data pointer, using the
+ * fpga_t struct. The FPGA channel can send any amount of data, so the data
+ * array should be large enough to accommodate. The len parameter specifies the
+ * actual size of the data buffer in words (4 byte words). The FPGA channel will
+ * specify an offset which will determine where in the data array the data will
+ * start being written. If the amount of data (plus offset) exceed the size of
+ * the data array (len), then that data will be discarded. If timeout is
+ * non-zero, this call will wait up to timeout ms for the FPGA to respond
+ * (between packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads receiving on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words received to the data array.
+ */
+RIFFAAPI int RIFFACALL fpga_recv(fpga_t * fpga, int chnl, void * data, int len,
+	long long timeout);
+
+/**
+ * Resets the state of the FPGA and all transfers across all channels. This is
+ * meant to be used as an alternative to rebooting if an error occurs while
+ * sending/receiving. Calling this function while other threads are sending or
+ * receiving will result in unexpected behavior.
+ */
+RIFFAAPI void RIFFACALL fpga_reset(fpga_t * fpga);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c_c++/windows/x86/riffa.lib b/c_c++/windows/x86/riffa.lib
new file mode 100755
index 0000000..79c45ac
Binary files /dev/null and b/c_c++/windows/x86/riffa.lib differ
diff --git a/c_c++/windows/x86/riffa.rc b/c_c++/windows/x86/riffa.rc
new file mode 100755
index 0000000..70f244f
--- /dev/null
+++ b/c_c++/windows/x86/riffa.rc
@@ -0,0 +1,83 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.rc
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+1 VERSIONINFO
+ FILEVERSION 1,0,0,0
+ PRODUCTVERSION 2,0,0,0
+ FILEFLAGSMASK 0x17L
+#ifdef _DEBUG
+ FILEFLAGS 0x1L
+#else
+ FILEFLAGS 0x0L
+#endif
+ FILEOS 0x4L
+ FILETYPE 0x1L
+ FILESUBTYPE 0x0L
+BEGIN
+    BLOCK "StringFileInfo"
+    BEGIN
+        BLOCK "040904b0"
+        BEGIN
+            VALUE "Comments", "RIFFA 64 bit Windows Library"
+            VALUE "CompanyName", "University of California, San Diego"
+            VALUE "FileDescription", "User 32 bit library for RIFFA."
+            VALUE "FileVersion", "1, 0, 0, 0"
+            VALUE "InternalName", "RIFFA"
+            VALUE "LegalCopyright", "Copyright © 2011 The Regents of the University of California. All Rights Reserved."
+            VALUE "OriginalFilename", "riffa.dll"
+            VALUE "ProductName", "RIFFA Library"
+            VALUE "ProductVersion", "2, 0, 0, 0"
+        END
+    END
+    BLOCK "VarFileInfo"
+    BEGIN
+        VALUE "Translation", 0x409, 1200
+    END
+END
\ No newline at end of file
diff --git a/c_c++/windows/x86/riffa_driver.h b/c_c++/windows/x86/riffa_driver.h
new file mode 100755
index 0000000..82daf6e
--- /dev/null
+++ b/c_c++/windows/x86/riffa_driver.h
@@ -0,0 +1,23 @@
+//
+// The following value is arbitrarily chosen from the space defined
+// by Microsoft as being "for non-Microsoft use"
+//
+//
+// {40d49fb9-6085-4e1d-8753-822be944d7bb}
+DEFINE_GUID (GUID_RIFFA_INTERFACE,
+   0x40d49fb9, 0x6085, 0x4e1d, 0x87, 0x53, 0x82, 0x2b, 0xe9, 0x44, 0xd7, 0xbb);
+
+// The IOCTL function codes from 0x800 to 0xFFF are for customer use.
+#define CTL_CODE( DeviceType, Function, Method, Access ) (                 \
+    ((DeviceType) << 16) | ((Access) << 14) | ((Function) << 2) | (Method) \
+)
+
+#define IOCTL_RIFFA_SEND \
+    CTL_CODE(0x00000022, 0x900, 2, 0)
+#define IOCTL_RIFFA_RECV \
+    CTL_CODE(0x00000022, 0x901, 2, 0)
+#define IOCTL_RIFFA_LIST \
+    CTL_CODE(0x00000022, 0x902, 2 ,0)
+#define IOCTL_RIFFA_RESET \
+    CTL_CODE(0x00000022, 0x903, 2, 0)
+
diff --git a/c_c++/windows/x86/sample_app/README.txt b/c_c++/windows/x86/sample_app/README.txt
new file mode 100755
index 0000000..90ce396
--- /dev/null
+++ b/c_c++/windows/x86/sample_app/README.txt
@@ -0,0 +1,10 @@
+The testutil example application works with the Verilog chnl_tester module
+which receives data and then sends data back to the workstation. 
+
+To compile the example application:
+
+gcc.exe -o testutil.exe testutil.c -L. -lriffa
+
+The riffa.lib import library must be in the directory specified by the -L 
+parameter (in this example, the current directory). The riffa.h header must be
+in the same directory as testutil.c.
diff --git a/c_c++/windows/x86/sample_app/riffa.h b/c_c++/windows/x86/sample_app/riffa.h
new file mode 100755
index 0000000..fb51d9a
--- /dev/null
+++ b/c_c++/windows/x86/sample_app/riffa.h
@@ -0,0 +1,150 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.h
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#ifndef RIFFA_H
+#define RIFFA_H
+
+// Must RIFFA_EXPORTS *only* when building the DLL.
+#ifdef RIFFA_EXPORTS
+  #define RIFFAAPI __declspec(dllexport)
+#else
+  #define RIFFAAPI __declspec(dllimport)
+#endif
+
+// Define calling convention in one place, for convenience.
+#define RIFFACALL __cdecl
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Maximum number of RIFFA FPGAs
+#define RIFFA_MAX_NUM_FPGAS (5)
+
+// Holds FPGA information for installed RIFFA FPGAs
+struct fpga_info_list
+{
+	int num_fpgas;
+	int id[RIFFA_MAX_NUM_FPGAS];
+	int num_chnls[RIFFA_MAX_NUM_FPGAS];
+	char name[RIFFA_MAX_NUM_FPGAS][16];
+	int vendor_id[RIFFA_MAX_NUM_FPGAS];
+	int device_id[RIFFA_MAX_NUM_FPGAS];
+};
+typedef struct fpga_info_list fpga_info_list;
+
+// Represents the FPGA device
+struct fpga_t;
+typedef struct fpga_t fpga_t;
+
+/**
+ * Populates the fpga_info_list pointer with all FPGAs registered in the system.
+ * Returns 0 on success, non-zero on error.
+ */
+RIFFAAPI int RIFFACALL fpga_list(fpga_info_list * list);
+
+/**
+ * Initializes the FPGA specified by id. On success, returns a pointer to a
+ * fpga_t struct. On error, returns NULL. Each FPGA must be opened before any
+ * channels can be accessed. Once opened, any number of threads can use the
+ * fpga_t struct.
+ */
+RIFFAAPI fpga_t * RIFFACALL fpga_open(int id);
+
+/**
+ * Cleans up memory/resources for the FPGA specified by the fd descriptor.
+ */
+RIFFAAPI void RIFFACALL fpga_close(fpga_t * fpga);
+
+/**
+ * Sends len words (4 byte words) from data to FPGA channel chnl using the
+ * fpga_t struct. The FPGA channel will be sent len, destoff, and last. If last
+ * is 1, the channel should interpret the end of this send as the end of a
+ * transaction. If last is 0, the channel should wait for additional sends
+ * before the end of the transaction. If timeout is non-zero, this call will
+ * send data and wait up to timeout ms for the FPGA to respond (between
+ * packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads sending on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words sent.
+ */
+RIFFAAPI int RIFFACALL fpga_send(fpga_t * fpga, int chnl, void * data, int len,
+	int destoff, int last, long long timeout);
+
+/**
+ * Receives data from the FPGA channel chnl to the data pointer, using the
+ * fpga_t struct. The FPGA channel can send any amount of data, so the data
+ * array should be large enough to accommodate. The len parameter specifies the
+ * actual size of the data buffer in words (4 byte words). The FPGA channel will
+ * specify an offset which will determine where in the data array the data will
+ * start being written. If the amount of data (plus offset) exceed the size of
+ * the data array (len), then that data will be discarded. If timeout is
+ * non-zero, this call will wait up to timeout ms for the FPGA to respond
+ * (between packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads receiving on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words received to the data array.
+ */
+RIFFAAPI int RIFFACALL fpga_recv(fpga_t * fpga, int chnl, void * data, int len,
+	long long timeout);
+
+/**
+ * Resets the state of the FPGA and all transfers across all channels. This is
+ * meant to be used as an alternative to rebooting if an error occurs while
+ * sending/receiving. Calling this function while other threads are sending or
+ * receiving will result in unexpected behavior.
+ */
+RIFFAAPI void RIFFACALL fpga_reset(fpga_t * fpga);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c_c++/windows/x86/sample_app/riffa.lib b/c_c++/windows/x86/sample_app/riffa.lib
new file mode 100755
index 0000000..79c45ac
Binary files /dev/null and b/c_c++/windows/x86/sample_app/riffa.lib differ
diff --git a/c_c++/windows/x86/sample_app/testutil.c b/c_c++/windows/x86/sample_app/testutil.c
new file mode 100755
index 0000000..96be35a
--- /dev/null
+++ b/c_c++/windows/x86/sample_app/testutil.c
@@ -0,0 +1,146 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include <windows.h>
+#include "timer.h"
+#include "riffa.h"
+
+int main(int argc, char** argv) {
+	fpga_t * fpga;
+	fpga_info_list info;
+	int option;
+	int i;
+	int id;
+	int chnl;
+	size_t numWords;
+	int sent;
+	int recvd;
+	unsigned int * sendBuffer;
+	unsigned int * recvBuffer;
+	GET_TIME_INIT(3);
+
+	if (argc < 2) {
+		printf("Usage: %s <option>\n", argv[0]);
+		return -1;
+	}
+
+	option = atoi(argv[1]);
+
+	if (option == 0) {	// List FPGA info
+		// Populate the fpga_info_list struct
+		if (fpga_list(&info) != 0) {
+			printf("Error populating fpga_info_list\n");
+			return -1;
+		}
+		printf("Number of devices: %d\n", info.num_fpgas);
+		for (i = 0; i < info.num_fpgas; i++) {
+			printf("%d: id:%d\n", i, info.id[i]);
+			printf("%d: num_chnls:%d\n", i, info.num_chnls[i]);
+			printf("%d: name:%s\n", i, info.name[i]);
+			printf("%d: vendor id:%04X\n", i, info.vendor_id[i]);
+			printf("%d: device id:%04X\n", i, info.device_id[i]);
+		}
+	}
+	else if (option == 1) { // Reset FPGA
+		if (argc < 3) {
+			printf("Usage: %s %d <fpga id>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Reset
+		fpga_reset(fpga);
+
+		// Done with device
+        fpga_close(fpga);
+	}
+	else if (option == 2) { // Send data, receive data
+		if (argc < 5) {
+			printf("Usage: %s %d <fpga id> <chnl> <num words to transfer>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+		chnl = atoi(argv[3]);
+		numWords = atoi(argv[4]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Malloc the arrays
+		sendBuffer = (unsigned int *)malloc(numWords<<2);
+		if (sendBuffer == NULL) {
+			printf("Could not malloc memory for sendBuffer\n");
+			fpga_close(fpga);
+			return -1;
+	    }
+		recvBuffer = (unsigned int *)malloc(numWords<<2);
+		if (recvBuffer == NULL) {
+			printf("Could not malloc memory for recvBuffer\n");
+			free(sendBuffer);
+			fpga_close(fpga);
+			return -1;
+	    }
+
+		// Initialize the data
+		for (i = 0; i < numWords; i++) {
+			sendBuffer[i] = i+1;
+			recvBuffer[i] = 0;
+		}
+
+		GET_TIME_VAL(0);
+
+		// Send the data
+		sent = fpga_send(fpga, chnl, sendBuffer, numWords, 0, 1, 25000);
+		printf("words sent: %d\n", sent);
+
+		GET_TIME_VAL(1);
+
+		if (sent != 0) {
+			// Recv the data
+			recvd = fpga_recv(fpga, chnl, recvBuffer, numWords, 25000);
+			printf("words recv: %d\n", recvd);
+		}
+
+		GET_TIME_VAL(2);
+
+		// Done with device
+        fpga_close(fpga);
+
+		// Display some data
+		for (i = 0; i < 20; i++) {
+			printf("recvBuffer[%d]: %d\n", i, recvBuffer[i]);
+		}
+
+		// Check the data
+		if (recvd != 0) {
+			for (i = 4; i < recvd; i++) {
+				if (recvBuffer[i] != sendBuffer[i]) {
+					printf("recvBuffer[%d]: %d, expected %d\n", i, recvBuffer[i], sendBuffer[i]);
+					break;
+				}
+			}
+
+			printf("send bw: %f MB/s %fms\n",
+				sent*4.0/1024/1024/((TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0))/1000.0),
+				(TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0)) );
+
+			printf("recv bw: %f MB/s %fms\n",
+				recvd*4.0/1024/1024/((TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1))/1000.0),
+				(TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1)) );
+		}
+	}
+
+	return 0;
+}
diff --git a/c_c++/windows/x86/sample_app/testutil.exe b/c_c++/windows/x86/sample_app/testutil.exe
new file mode 100644
index 0000000..de52626
Binary files /dev/null and b/c_c++/windows/x86/sample_app/testutil.exe differ
diff --git a/c_c++/windows/x86/sample_app/timer.h b/c_c++/windows/x86/sample_app/timer.h
new file mode 100755
index 0000000..15b64a2
--- /dev/null
+++ b/c_c++/windows/x86/sample_app/timer.h
@@ -0,0 +1,7 @@
+#include <windows.h>
+
+#define GET_TIME_INIT(num) LARGE_INTEGER _timers[num]; LARGE_INTEGER _freq; QueryPerformanceFrequency(&_freq)
+
+#define GET_TIME_VAL(num) QueryPerformanceCounter(&_timers[num])
+
+#define TIME_VAL_TO_MS(num) ((double)_timers[num].QuadPart*1000.0/_freq.QuadPart)
\ No newline at end of file
diff --git a/driver/linux/Makefile b/driver/linux/Makefile
new file mode 100644
index 0000000..c505026
--- /dev/null
+++ b/driver/linux/Makefile
@@ -0,0 +1,155 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+
+# Filename: Makefile
+# Version: 2.0
+# Description: Makefile for Linux PCIe device driver for RIFFA.
+# Author: Matthew Jacobsen
+# History: @mattj: Initial release. Version 2.0.
+
+# You must specify the following variables. You can leave the defaults if you
+# like, but make sure they will work in your system.
+# The VENDOR_ID _must_ match what is configured on your FPGA's PCIe endpoint 
+# header. Xilinx has a VENDOR_ID = 10EE.
+NAME := riffa
+VENDOR_ID0 := 10EE
+VENDOR_ID1 := 1172
+MAJNUM := 100
+
+# Build variables
+KVER := $(shell uname -r)
+KDIR := /lib/modules/`uname -r`/build
+RHR := /etc/redhat-release
+LIB_SRCS := riffa.c
+LIB_OBJS := $(patsubst %.c,%.o,$(LIB_SRCS))
+LIB_HDR := riffa.h
+LIB_VER_MAJ := 1
+LIB_VER_MIN := 0
+LIB_VER := $(LIB_VER_MAJ).$(LIB_VER_MIN)
+DRVR_HDR := riffa_driver.h
+DBUGVAL := DBUG
+
+obj-m += $(NAME).o
+$(NAME)-y := riffa_driver.o circ_queue.o
+
+# Helper functions
+define assert
+  $(if $1,,$(error Assertion failed: $2))
+endef
+define assert-not-null
+  $(call assert,$($1),The variable "$1" is null, please specify it.)
+endef
+define assert-variables
+	$(call assert-not-null,NAME)
+	$(call assert-not-null,MAJNUM)
+	$(call assert-not-null,VENDOR_ID0)
+	$(call assert-not-null,VENDOR_ID1)
+	@printf "Compiling driver for kernel: %s with the following values\n" $(KVER)
+	@printf "     NAME: '%s'\n" $(NAME)
+	@printf "   MAJNUM: '%s'\n" $(MAJNUM)
+	@printf "VENDOR_ID0: '%s'\n" $(VENDOR_ID0)
+	@printf "VENDOR_ID1: '%s'\n" $(VENDOR_ID1)
+	@printf "\n"
+endef
+
+all: builddvr
+debug: CC += -DDEBUG -g
+debug: DBUGVAL = DEBUG
+debug: builddvr
+builddvr: $(NAME).ko $(NAME).so.$(LIB_VER)
+
+$(NAME).ko: *.c *.h
+	$(call assert-variables)
+	sed -i 's/#define MAJOR_NUM [^\n]*/#define MAJOR_NUM $(MAJNUM)/g' $(DRVR_HDR)
+	sed -i 's/#define DEVICE_NAME [^\n]*/#define DEVICE_NAME "$(NAME)"/g' $(DRVR_HDR)
+	sed -i 's/#define VENDOR_ID0 [^\n]*/#define VENDOR_ID0 0x$(VENDOR_ID0)/g' $(DRVR_HDR)
+	sed -i 's/#define VENDOR_ID1 [^\n]*/#define VENDOR_ID1 0x$(VENDOR_ID1)/g' $(DRVR_HDR)
+	sed -i 's/#define DEBUG [^\n]*/#define DBUG 1/g' $(DRVR_HDR)
+	sed -i 's/#define DBUG [^\n]*/#define $(DBUGVAL) 1/g' $(DRVR_HDR)
+	make -C $(KDIR) SUBDIRS=`pwd` modules
+	rm -rf $(LIB_OBJS)
+
+$(NAME).so.$(LIB_VER): $(LIB_OBJS)
+	$(CC) -shared -Wl,-soname,lib$(NAME).so.$(LIB_VER_MAJ) -o lib$@ $^
+
+$(LIB_OBJS): $(LIB_SRCS)
+	$(CC) -g -Wall -fPIC -c $^
+
+load: $(NAME).ko
+	insmod $(NAME).ko
+	
+unload:
+	rmmod $(NAME)
+
+clean:
+	rm -Rf *.ko *.cmd *.o *.so *.so.* .*.cmd Module.symvers Module.markers modules.order *.mod.c .tmp_versions
+
+setup:
+	if [ -f "$(RHR)" ]; then yum install kernel-devel-`uname -r`;\
+	else apt-get install linux-headers-`uname -r`; fi
+
+install: $(NAME).so.$(LIB_VER) $(NAME).ko 
+	mkdir -p /lib/modules/$(KVER)/kernel/drivers/$(NAME)
+	cp $(NAME).ko /lib/modules/$(KVER)/kernel/drivers/$(NAME)/
+	if [ -f "$(RHR)" ]; then\
+		printf "%b\n" "#!/bin/sh\nexec /sbin/modprobe $(NAME) >/dev/null 2>&1" > /etc/sysconfig/modules/$(NAME).modules;\
+		chmod 755 /etc/sysconfig/modules/$(NAME).modules;\
+	else\
+		if ! grep -Fxq "$(NAME)" /etc/modules; then echo "$(NAME)" >> /etc/modules; fi;\
+	fi
+	printf "%b\n" "KERNEL==\"$(NAME)\", MODE=\"777\", GROUP=\"root\"" > /etc/udev/rules.d/99-$(NAME).rules
+	printf "/usr/local/lib\n" > $(NAME).conf
+	mv $(NAME).conf /etc/ld.so.conf.d/
+	cp $(DRVR_HDR) /usr/local/include/
+	cp $(LIB_HDR) /usr/local/include/
+	mv lib$(NAME).so.1.0 /usr/local/lib
+	ln -sf /usr/local/lib/lib$(NAME).so.$(LIB_VER) /usr/local/lib/lib$(NAME).so.$(LIB_VER_MAJ)
+	ln -sf /usr/local/lib/lib$(NAME).so.$(LIB_VER) /usr/local/lib/lib$(NAME).so
+	ldconfig
+	depmod
+
+uninstall: 
+	rm -f /usr/local/lib/lib$(NAME).so*
+	rm -f /usr/local/include/$(LIB_HDR)
+	rm -f /usr/local/include/$(DRVR_HDR)
+	rm -f /etc/ld.so.conf.d/$(NAME).conf
+	rm -rf /lib/modules/$(KVER)/kernel/drivers/$(NAME)
+	rm -f /etc/udev/rules.d/99-$(NAME).rules
+	if [ -f "$(RHR)" ]; then rm -f /etc/sysconfig/modules/$(NAME).modules;\
+	else cp /etc/modules ./etc.modules.bak; sed -i '/$(NAME)/d' /etc/modules; fi
+	ldconfig
+	depmod
+
+
diff --git a/driver/linux/README.txt b/driver/linux/README.txt
new file mode 100644
index 0000000..36e9f62
--- /dev/null
+++ b/driver/linux/README.txt
@@ -0,0 +1,38 @@
+You must build the Linux driver against the version of the Linux kernel you have
+installed. This will require the Linux kernel headers. After you've built the
+driver you can install it in your system so that it loads at boot time. If the
+driver is installed and there is a RIFFA 2.0.1 capable FPGA installed as well, 
+the driver will detect it. Output in the system log will provide additional 
+information. This makefile will also build and install the C/C++ native library.
+
+Ensure you have the kernel headers installed:
+
+sudo make setup
+
+This will attempt to install the kernel headers using your system's package
+manager. You can skip this step if you've already installed the kernel headers.
+
+Compile the driver and C/C++ library:
+
+make
+
+or 
+
+make debug
+
+Using make debug will compile in code to output debug messages to the system log
+at runtime. These messages are useful when developing your design. However they
+pollute your system log and incur some overhead. So you may want to install the
+non-debug version after you've completed development.
+
+Install the driver and library:
+
+sudo make install
+
+The system will be configured to load the driver at boot time. The C/C++ library
+will be installed in the default library path. The header files will be placed
+in the default include path. You will want to reboot after you've installed for
+the driver to be (re)loaded.
+
+When compiling an application you should only need to include the <riffa.h> 
+header file and link with -lriffa.
diff --git a/driver/linux/circ_queue.c b/driver/linux/circ_queue.c
new file mode 100644
index 0000000..f9a1f30
--- /dev/null
+++ b/driver/linux/circ_queue.c
@@ -0,0 +1,188 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+/*
+ * Filename: circ_queue.c
+ * Version: 1.0
+ * Description: A lock-free single-producer circular queue implementation 
+ *   modeled after the more elaborate C++ version from Faustino Frechilla at:
+ *   http://www.codeproject.com/Articles/153898/Yet-another-implementation-of-a-lock-free-circular
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 1.0.
+ */
+
+#include <linux/slab.h>
+#include "circ_queue.h"
+
+circ_queue * init_circ_queue(int len)
+{
+	int i;
+	circ_queue * q;
+
+	q = kzalloc(sizeof(circ_queue), GFP_KERNEL);
+	if (q == NULL) {
+		printk(KERN_ERR "Not enough memory to allocate circ_queue");
+		return NULL;
+	}
+
+	atomic_set(&q->writeIndex, 0);
+	atomic_set(&q->readIndex, 0);
+	q->len = len;
+
+	q->vals = (unsigned int**) kzalloc(len*sizeof(unsigned int*), GFP_KERNEL);  
+	if (q->vals == NULL) {
+		printk(KERN_ERR "Not enough memory to allocate circ_queue array");
+		return NULL;
+	}
+	for (i = 0; i < len; i++) {
+		q->vals[i] = (unsigned int*) kzalloc(2*sizeof(unsigned int), GFP_KERNEL);
+		if (q->vals[i] == NULL) {
+			printk(KERN_ERR "Not enough memory to allocate circ_queue array position");
+			return NULL;
+		}
+	}
+
+	return q;
+}
+
+/**
+ * Internal function to help count. Returns the queue size normalized position.
+ */
+unsigned int queue_count_to_index(unsigned int count, unsigned int len)
+{
+	return (count % len);
+}
+
+int push_circ_queue(circ_queue * q, unsigned int val1, unsigned int val2)
+{
+	unsigned int currReadIndex;
+	unsigned int currWriteIndex;
+
+	currWriteIndex = atomic_read(&q->writeIndex);
+	currReadIndex  = atomic_read(&q->readIndex);
+	if (queue_count_to_index(currWriteIndex+1, q->len) == queue_count_to_index(currReadIndex, q->len)) {
+		// The queue is full
+		return 1;
+	}
+
+	// Save the data into the queue
+	q->vals[queue_count_to_index(currWriteIndex, q->len)][0] = val1;
+	q->vals[queue_count_to_index(currWriteIndex, q->len)][1] = val2;
+	// Increment atomically write index. Now a consumer thread can read
+	// the piece of data that was just stored.
+	atomic_inc(&q->writeIndex);
+
+	return 0;
+}
+
+int pop_circ_queue(circ_queue * q, unsigned int * val1, unsigned int * val2)
+{
+	unsigned int currReadIndex;
+	unsigned int currMaxReadIndex;
+
+	do
+	{
+		currReadIndex = atomic_read(&q->readIndex);
+		currMaxReadIndex = atomic_read(&q->writeIndex);
+		if (queue_count_to_index(currReadIndex, q->len) == queue_count_to_index(currMaxReadIndex, q->len)) {
+			// The queue is empty or a producer thread has allocate space in the queue
+			// but is waiting to commit the data into it
+			return 1;
+		}
+
+		// Retrieve the data from the queue
+		*val1 = q->vals[queue_count_to_index(currReadIndex, q->len)][0];
+		*val2 = q->vals[queue_count_to_index(currReadIndex, q->len)][1];
+
+		// Try to perfrom now the CAS operation on the read index. If we succeed
+		// label & val already contain what q->readIndex pointed to before we 
+		// increased it.
+		if (atomic_cmpxchg(&q->readIndex, currReadIndex, currReadIndex+1) == currReadIndex) {
+			// The lable & val were retrieved from the queue. Note that the
+			// data inside the label or value arrays are not deleted.
+			return 0;
+		}
+
+		// Failed to retrieve the elements off the queue. Someone else must
+		// have read the element stored at countToIndex(currReadIndex)
+		// before we could perform the CAS operation.       
+	} while(1); // keep looping to try again!
+
+	return 1;
+}
+
+int circ_queue_empty(circ_queue * q)
+{
+	unsigned int currReadIndex;
+	unsigned int currMaxReadIndex;
+
+	currReadIndex = atomic_read(&q->readIndex);
+	currMaxReadIndex = atomic_read(&q->writeIndex);
+	if (queue_count_to_index(currReadIndex, q->len) == queue_count_to_index(currMaxReadIndex, q->len)) {
+		// The queue is empty or a producer thread has allocate space in the queue
+		// but is waiting to commit the data into it
+		return 1;
+	}
+	return 0;
+}
+
+int circ_queue_full(circ_queue * q)
+{
+	unsigned int currReadIndex;
+	unsigned int currWriteIndex;
+
+	currWriteIndex = atomic_read(&q->writeIndex);
+	currReadIndex  = atomic_read(&q->readIndex);
+	if (queue_count_to_index(currWriteIndex+1, q->len) == queue_count_to_index(currReadIndex, q->len)) {
+		// The queue is full
+		return 1;
+	}
+	return 0;
+}
+
+void free_circ_queue(circ_queue * q)
+{
+	int i;
+
+	if (q == NULL)
+		return;
+
+	for (i = 0; i < q->len; i++) {  
+		kfree(q->vals[i]);  
+	}
+	kfree(q->vals);
+	kfree(q);
+}
+
diff --git a/driver/linux/circ_queue.h b/driver/linux/circ_queue.h
new file mode 100644
index 0000000..b4e193f
--- /dev/null
+++ b/driver/linux/circ_queue.h
@@ -0,0 +1,96 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+/*
+ * Filename: circ_queue.h
+ * Version: 1.0
+ * Description: A lock-free single-producer circular queue implementation 
+ *   modeled after the more elaborate C++ version from Faustino Frechilla at:
+ *   http://www.codeproject.com/Articles/153898/Yet-another-implementation-of-a-lock-free-circular
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 1.0.
+ */
+#ifndef CIRC_QUEUE_H
+#define CIRC_QUEUE_H
+
+#include <asm/atomic.h>
+
+/* Struct for the circular queue. */
+struct circ_queue {
+	atomic_t writeIndex;
+	atomic_t readIndex;
+	unsigned int ** vals;
+	unsigned int len;
+};
+typedef struct circ_queue circ_queue;
+
+/**
+ * Initializes a circ_queue with depth/length len. Returns non-NULL on success, 
+ * NULL if there was a problem creating the queue.
+ */
+circ_queue * init_circ_queue(int len);
+
+/**
+ * Pushes a pair of unsigned int values into the specified queue at the head. 
+ * Returns 0 on success, non-zero if there is no more space in the queue.
+ */
+int push_circ_queue(circ_queue * q, unsigned int val1, unsigned int val2);
+
+/**
+ * Pops a pair of unsigned int values out of the specified queue from the tail.
+ * Returns 0 on success, non-zero if the queue is empty.
+ */
+int pop_circ_queue(circ_queue * q, unsigned int * val1, unsigned int * val2);
+
+/**
+ * Returns 1 if the circ_queue is empty, 0 otherwise. Note, this is not a 
+ * synchronized function. If another thread is accessing this circ_queue, the
+ * return value may not be valid.
+ */
+int circ_queue_empty(circ_queue * q);
+
+/**
+ * Returns 1 if the circ_queue is full, 0 otherwise. Note, this is not a 
+ * synchronized function. If another thread is accessing this circ_queue, the
+ * return value may not be valid.
+ */
+int circ_queue_full(circ_queue * q);
+
+/**
+ * Frees the resources associated with the specified circ_queue.
+ */
+void free_circ_queue(circ_queue * q);
+
+#endif
diff --git a/driver/linux/riffa.c b/driver/linux/riffa.c
new file mode 100644
index 0000000..ccdde34
--- /dev/null
+++ b/driver/linux/riffa.c
@@ -0,0 +1,131 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+/*
+ * Filename: riffa.c
+ * Version: 2.0
+ * Description: Linux PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include "riffa.h"
+
+struct fpga_t
+{
+	int fd;
+	int id;
+};
+
+fpga_t * fpga_open(int id) 
+{
+	fpga_t * fpga;
+
+	// Allocate space for the fpga_dev
+	fpga = (fpga_t *)malloc(sizeof(fpga_t));
+	if (fpga == NULL)
+		return NULL;
+	fpga->id = id;	
+
+	// Open the device file.
+	fpga->fd = open("/dev/" DEVICE_NAME, O_RDWR | O_SYNC);
+	if (fpga->fd < 0) {
+		free(fpga); 
+		return NULL;
+	}
+	
+	return fpga;
+}
+
+void fpga_close(fpga_t * fpga) 
+{
+	// Close the device file.
+	close(fpga->fd);
+	free(fpga);
+}
+
+int fpga_send(fpga_t * fpga, int chnl, void * data, int len, int destoff, 
+	int last, long long timeout)
+{
+	fpga_chnl_io io;
+
+	io.id = fpga->id;
+	io.chnl = chnl;
+	io.len = len;
+	io.offset = destoff;
+	io.last = last;
+	io.timeout = timeout;
+	io.data = (char *)data;
+
+	return ioctl(fpga->fd, IOCTL_SEND, &io);
+}
+
+int fpga_recv(fpga_t * fpga, int chnl, void * data, int len, long long timeout)
+{
+	fpga_chnl_io io;
+
+	io.id = fpga->id;
+	io.chnl = chnl;
+	io.len = len;
+	io.timeout = timeout;
+	io.data = (char *)data;
+
+	return ioctl(fpga->fd, IOCTL_RECV, &io);
+}
+
+void fpga_reset(fpga_t * fpga)
+{
+	ioctl(fpga->fd, IOCTL_RESET, fpga->id);
+}
+
+int fpga_list(fpga_info_list * list) {
+	int fd;
+	int rc;
+
+	fd = open("/dev/" DEVICE_NAME, O_RDWR | O_SYNC);
+	if (fd < 0)
+		return fd;
+	rc = ioctl(fd, IOCTL_LIST, list);
+	close(fd);
+	return rc;
+}
+
+
+
diff --git a/driver/linux/riffa.h b/driver/linux/riffa.h
new file mode 100644
index 0000000..a844315
--- /dev/null
+++ b/driver/linux/riffa.h
@@ -0,0 +1,120 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+/*
+ * Filename: riffa.h
+ * Version: 2.0
+ * Description: Linux PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#ifndef RIFFA_H
+#define RIFFA_H
+
+#include "riffa_driver.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct fpga_t;
+typedef struct fpga_t fpga_t;
+
+/**
+ * Populates the fpga_info_list pointer with all FPGAs registered in the system.
+ * Returns 0 on success, a negative value on error.
+ */
+int fpga_list(fpga_info_list * list);
+
+/**
+ * Initializes the FPGA specified by id. On success, returns a pointer to a 
+ * fpga_t struct. On error, returns NULL. Each FPGA must be opened before any 
+ * channels can be accessed. Once opened, any number of threads can use the 
+ * fpga_t struct.
+ */
+fpga_t * fpga_open(int id);
+
+/**
+ * Cleans up memory/resources for the FPGA specified by the fd descriptor.
+ */
+void fpga_close(fpga_t * fpga);
+
+/**
+ * Sends len words (4 byte words) from data to FPGA channel chnl using the 
+ * fpga_t struct. The FPGA channel will be sent len, destoff, and last. If last
+ * is 1, the channel should interpret the end of this send as the end of a
+ * transaction. If last is 0, the channel should wait for additional sends 
+ * before the end of the transaction. If timeout is non-zero, this call will 
+ * send data and wait up to timeout ms for the FPGA to respond (between
+ * packets) before timing out. If timeout is zero, this call may block 
+ * indefinitely. Multiple threads sending on the same channel may result in 
+ * corrupt data or error. This function is thread safe across channels.
+ * On success, returns the number of words sent. On error returns a negative 
+ * value. 
+ */
+int fpga_send(fpga_t * fpga, int chnl, void * data, int len, int destoff, 
+	int last, long long timeout);
+
+/**
+ * Receives data from the FPGA channel chnl to the data pointer, using the 
+ * fpga_t struct. The FPGA channel can send any amount of data, so the data 
+ * array should be large enough to accommodate. The len parameter specifies the
+ * actual size of the data buffer in words (4 byte words). The FPGA channel will
+ * specify an offset which will determine where in the data array the data will
+ * start being written. If the amount of data (plus offset) exceed the size of
+ * the data array (len), then that data will be discarded. If timeout is 
+ * non-zero, this call will wait up to timeout ms for the FPGA to respond 
+ * (between packets) before timing out. If timeout is zero, this call may block 
+ * indefinitely. Multiple threads receiving on the same channel may result in 
+ * corrupt data or error. This function is thread safe across channels.
+ * On success, returns the number of words written to the data array. On error 
+ * returns a negative value. 
+ */
+int fpga_recv(fpga_t * fpga, int chnl, void * data, int len, long long timeout);
+
+/**
+ * Resets the state of the FPGA and all transfers across all channels. This is
+ * meant to be used as an alternative to rebooting if an error occurs while 
+ * sending/receiving. Calling this function while other threads are sending or
+ * receiving will result in unexpected behavior.
+ */
+void fpga_reset(fpga_t * fpga);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/driver/linux/riffa_driver.c b/driver/linux/riffa_driver.c
new file mode 100644
index 0000000..0efe230
--- /dev/null
+++ b/driver/linux/riffa_driver.c
@@ -0,0 +1,1498 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+/*
+ * Filename: riffa_driver.c
+ * Version: 2.0
+ * Description: Linux PCIe device driver for RIFFA. Uses Linux kernel APIs in
+ *  version 2.6.27+ (tested on version 2.6.32 - 3.3.0).
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/fs.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/rwsem.h>
+#include <linux/dma-mapping.h>
+#include <linux/pagemap.h>
+#include <asm/uaccess.h>
+#include <asm/div64.h>
+#include "riffa_driver.h"
+#include "circ_queue.h"
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("PCIe driver for RIFFA, Linux (2.6.27+)");
+MODULE_AUTHOR("Matt Jacobsen, Patrick Lai");
+
+#ifndef __devinit
+#define __devinit
+#define __devexit
+#define __devexit_p
+#endif
+
+#define CHNL_REG(c, o) ((c<<4) + o)
+#if !defined(__LP64__) && !defined(_LP64)
+#define BUILD_32 1
+#endif
+
+struct sg_mapping {
+	struct page ** pages;
+	struct scatterlist * sgl;
+	enum dma_data_direction direction;
+	int num_sg;
+	unsigned long num_pages;
+	unsigned long long length;
+	unsigned long long overflow;
+};
+
+struct chnl_dir {
+	wait_queue_head_t waitq;
+	struct circ_queue * msgs;
+	void * buf_addr;
+	dma_addr_t buf_hw_addr;
+	struct sg_mapping * sg_map_0;
+	struct sg_mapping * sg_map_1;
+};
+
+struct fpga_state {
+	struct pci_dev * dev;
+	unsigned long long irq;
+	void __iomem *bar0;
+	unsigned long long bar0_addr;
+	unsigned long long bar0_len;
+	unsigned long long bar0_flags;  
+	atomic_t intr_disabled;
+	void * spill_buf_addr;
+	dma_addr_t spill_buf_hw_addr;
+	int num_sg;
+	int sg_buf_size;
+	int id;
+	char name[16];
+	int vendor_id;
+	int device_id;
+	int num_chnls;
+	struct chnl_dir ** recv;
+	struct chnl_dir ** send;
+};
+
+// Global variables (to this file only)
+static struct class * mymodule_class;
+static dev_t devt;
+static atomic_t used_fpgas[NUM_FPGAS];
+static struct fpga_state * fpgas[NUM_FPGAS];
+
+///////////////////////////////////////////////////////
+// MEMORY ALLOCATION & HELPER FUNCTIONS
+///////////////////////////////////////////////////////
+
+/** 
+ * Returns the value at the specified address.
+ */
+static inline unsigned int read_reg(struct fpga_state * sc, int offset)
+{
+	return readl(sc->bar0 + (offset<<2));
+}
+
+/** 
+ * Writes the value to the specified address.
+ */
+static inline void write_reg(struct fpga_state * sc, int offset, unsigned int val)
+{
+	writel(val, sc->bar0 + (offset<<2));
+}
+
+#ifdef BUILD_32
+/**
+ * Needed for 32 bit OS because dma_map_sg macro eventually does some 64 bit
+ * division.
+ */
+unsigned long long __udivdi3(unsigned long long num, unsigned long long den)
+{
+	do_div(num, den);
+	return num;
+}
+#endif
+
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(3,6,11)
+/**
+ * Used to set ETB and RCB, but not available before 3.7. As it is peppered 
+ * throughout the clean up code, it's just easier to define empty implementations
+ * here than a bunch of conditionals everywhere else.
+ */
+#ifndef PCI_EXP_DEVCTL
+#define PCI_EXP_DEVCTL 0
+#endif
+#ifndef PCI_EXP_DEVCTL_EXT_TAG
+#define PCI_EXP_DEVCTL_EXT_TAG 0
+#endif
+#ifndef PCI_EXP_DEVCTL_RELAX_EN
+#define PCI_EXP_DEVCTL_RELAX_EN 0
+#endif
+#ifndef PCI_EXP_DEVCTL2
+#define PCI_EXP_DEVCTL2 0
+#endif
+#ifndef PCI_EXP_DEVCTL2_IDO_REQ_EN
+#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0
+#endif
+#ifndef PCI_EXP_DEVCTL2_IDO_CMP_EN
+#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0
+#endif
+#ifndef PCI_EXP_DEVCTL
+#define PCI_EXP_DEVCTL 0
+#endif
+#ifndef PCI_EXP_LNKCTL_RCB
+#define PCI_EXP_LNKCTL_RCB 0
+#endif
+
+int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
+{
+	return 0;
+}
+
+int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
+{
+	return 0;
+}
+
+int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
+{
+	return 0;
+}
+
+int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
+{
+	return 0;
+}
+#endif
+
+///////////////////////////////////////////////////////
+// INTERRUPT HANDLER
+///////////////////////////////////////////////////////
+
+/**
+ * Reads the interrupt vector and processes it. If processing VECT0, off will
+ * be 0. If processing VECT1, off will be 6.
+ */
+static inline void process_intr_vector(struct fpga_state * sc, int off, 
+				unsigned int vect)
+{
+	// VECT_0/VECT_1 are organized from right to left (LSB to MSB) as:
+	// [ 0] TX_TXN			for channel 0 in VECT_0, channel 6 in VECT_1
+	// [ 1] TX_SG_BUF_RECVD	for channel 0 in VECT_0, channel 6 in VECT_1
+	// [ 2] TX_TXN_DONE		for channel 0 in VECT_0, channel 6 in VECT_1
+	// [ 3] RX_SG_BUF_RECVD	for channel 0 in VECT_0, channel 6 in VECT_1
+	// [ 4] RX_TXN_DONE		for channel 0 in VECT_0, channel 6 in VECT_1
+	// ...
+	// [25] TX_TXN			for channel 5 in VECT_0, channel 11 in VECT_1
+	// [26] TX_SG_BUF_RECVD	for channel 5 in VECT_0, channel 11 in VECT_1
+	// [27] TX_TXN_DONE		for channel 5 in VECT_0, channel 11 in VECT_1
+	// [28] RX_SG_BUF_RECVD	for channel 5 in VECT_0, channel 11 in VECT_1
+	// [29] RX_TXN_DONE		for channel 5 in VECT_0, channel 11 in VECT_1
+	// Positions 30 - 31 in both VECT_0 and VECT_1 are zero.
+
+	unsigned int offlast;
+	unsigned int len;
+	int recv;
+	int send;
+	int chnl;
+	int i;
+
+//printk(KERN_INFO "riffa: intrpt_handler received:%08x\n", vect);
+	if (vect & 0xC0000000) {
+		printk(KERN_ERR "riffa: fpga:%d, received bad interrupt vector:%08x\n", sc->id, vect);
+		return;
+	}
+
+	for (i = 0; i < 6 && (i+off) < sc->num_chnls; ++i) {
+		chnl = i + off;
+		recv = 0; 
+		send = 0; 
+
+		// TX (PC receive) scatter gather buffer is read.
+		if (vect & (1<<((5*i)+1))) { 
+			recv = 1; 
+			// Keep track so the thread can handle this.
+			if (push_circ_queue(sc->recv[chnl]->msgs, EVENT_SG_BUF_READ, 0)) {
+				printk(KERN_ERR "riffa: fpga:%d chnl:%d, recv sg buf read msg queue full\n", sc->id, chnl);
+			}
+			DEBUG_MSG(KERN_INFO "riffa: fpga:%d chnl:%d, recv sg buf read\n", sc->id, chnl);
+		}
+
+		// TX (PC receive) transaction done.
+		if (vect & (1<<((5*i)+2))) { 
+			recv = 1; 
+			// Read the transferred amount.
+			len = read_reg(sc, CHNL_REG(chnl, TX_TNFR_LEN_REG_OFF));
+			// Notify the thread.
+			if (push_circ_queue(sc->recv[chnl]->msgs, EVENT_TXN_DONE, len)) {
+				printk(KERN_ERR "riffa: fpga:%d chnl:%d, recv txn done msg queue full\n", sc->id, chnl);
+			}
+			DEBUG_MSG(KERN_INFO "riffa: fpga:%d chnl:%d, recv txn done\n", sc->id, chnl);
+		}
+
+		// New TX (PC receive) transaction.
+		if (vect & (1<<((5*i)+0))) { 
+			recv = 1; 
+			// Read the offset/last and length
+			offlast = read_reg(sc, CHNL_REG(chnl, TX_OFFLAST_REG_OFF));
+			len = read_reg(sc, CHNL_REG(chnl, TX_LEN_REG_OFF));
+			// Keep track of this transaction
+			if (push_circ_queue(sc->recv[chnl]->msgs, EVENT_TXN_OFFLAST, offlast)) {
+				printk(KERN_ERR "riffa: fpga:%d chnl:%d, recv txn offlast msg queue full\n", sc->id, chnl);
+			}
+			if (push_circ_queue(sc->recv[chnl]->msgs, EVENT_TXN_LEN, len)) {
+				printk(KERN_ERR "riffa: fpga:%d chnl:%d, recv txn len msg queue full\n", sc->id, chnl);
+			}
+			DEBUG_MSG(KERN_INFO "riffa: fpga:%d chnl:%d, recv txn (len:%d off:%d last:%d)\n", sc->id, chnl, len, (offlast>>1), (offlast & 0x1));
+		}
+
+		// RX (PC send) scatter gather buffer is read.
+		if (vect & (1<<((5*i)+3))) { 
+			send = 1; 
+			// Keep track so the thread can handle this.
+			if (push_circ_queue(sc->send[chnl]->msgs, EVENT_SG_BUF_READ, 0)) {
+				printk(KERN_ERR "riffa: fpga:%d chnl:%d, send sg buf read msg queue full\n", sc->id, chnl);
+			}
+			DEBUG_MSG(KERN_INFO "riffa: fpga:%d chnl:%d, send sg buf read\n", sc->id, chnl);
+		}
+
+		// RX (PC send) transaction done.
+		if (vect & (1<<((5*i)+4))) {
+			send = 1; 
+			// Read the transferred amount.
+			len = read_reg(sc, CHNL_REG(chnl, RX_TNFR_LEN_REG_OFF));
+			// Notify the thread.
+			if (push_circ_queue(sc->send[chnl]->msgs, EVENT_TXN_DONE, len)) {
+				printk(KERN_ERR "riffa: fpga:%d chnl:%d, send txn done msg queue full\n", sc->id, chnl);
+			}
+			DEBUG_MSG(KERN_INFO "riffa: fpga:%d chnl:%d, send txn done\n", sc->id, chnl);
+		}
+
+		// Wake up the thread?
+		if (recv)
+			wake_up(&sc->recv[chnl]->waitq);
+		if (send)
+			wake_up(&sc->send[chnl]->waitq);
+	}
+}
+
+/**
+ * Interrupt handler for all interrupts on all files. Reads data/values
+ * from FPGA and wakes up waiting threads to process the data. Always returns
+ * IRQ_HANDLED.
+ */
+static irqreturn_t intrpt_handler(int irq, void *dev_id) 
+{
+	unsigned int vect0;
+	unsigned int vect1;
+	struct fpga_state * sc;
+
+	sc = (struct fpga_state *)dev_id;
+	vect0 = 0;
+	vect1 = 0;
+
+	if (sc == NULL) {
+		printk(KERN_ERR "riffa: invalid fpga_state pointer\n");
+		return IRQ_HANDLED;
+	}
+
+	if (!atomic_read(&sc->intr_disabled)) {
+		// Read the interrupt vector(s):
+		vect0 = read_reg(sc, IRQ_REG0_OFF);
+		if (sc->num_chnls > 6)
+			vect1 = read_reg(sc, IRQ_REG1_OFF);
+
+		// Process the vector(s)
+		process_intr_vector(sc, 0, vect0);
+		if (sc->num_chnls > 6)
+			process_intr_vector(sc, 6, vect1);
+	}
+
+	return IRQ_HANDLED;
+}
+
+
+///////////////////////////////////////////////////////
+// FILE OPERATION HANDLERS
+///////////////////////////////////////////////////////
+
+/**
+ * Creates and returns a struct_sg_mapping that holds all the data for the user
+ * pages that have been mapped into a scatterlist array. Assumes the user data
+ * is 32 bit word aligned. Up to length bytes from the udata pointer will be
+ * mapped. After all length bytes are mapped, up to overflow bytes will be
+ * mapped using the common spill buffer for the channel. The overflow is used
+ * if we run out of space in the supplied udata pointer.
+ */
+static inline struct sg_mapping * fill_sg_buf(struct fpga_state * sc, int chnl, 
+					void * sg_buf, unsigned long udata, unsigned long long length, 
+					unsigned long long overflow, enum dma_data_direction direction) {
+	const char * dir = (direction == DMA_TO_DEVICE ? "send" : "recv");
+	struct sg_mapping * sg_map;
+	struct page ** pages = NULL;
+	struct scatterlist * sgl = NULL;
+	struct scatterlist * sg;
+	unsigned long num_pages_reqd = 0;
+	long num_pages = 0;
+	unsigned int fp_offset;
+	unsigned int len;
+	unsigned int hw_len;
+	dma_addr_t hw_addr;
+	unsigned long long len_rem = length;
+	unsigned long long overflow_rem = overflow;
+	unsigned int * sg_buf_ptr = (unsigned int *)sg_buf;
+	int num_sg = 0;
+	int i;
+
+	// Create the sg_mapping struct.
+	if ((sg_map = (struct sg_mapping *)kmalloc(sizeof(*sg_map), GFP_KERNEL)) == NULL) {
+		printk(KERN_ERR "riffa: fpga:%d chnl:%d, %s could not allocate memory for sg_mapping struct\n", sc->id, chnl, dir);
+		return NULL;
+	}
+
+	if (length > 0) {
+		// Create the pages array.
+		num_pages_reqd = ((udata + length - 1)>>PAGE_SHIFT) - (udata>>PAGE_SHIFT) + 1;
+		num_pages_reqd = (num_pages_reqd > sc->num_sg ? sc->num_sg : num_pages_reqd);
+		if ((pages = kmalloc(num_pages_reqd * sizeof(*pages), GFP_KERNEL)) == NULL) {
+			printk(KERN_ERR "riffa: fpga:%d chnl:%d, %s could not allocate memory for pages array\n", sc->id, chnl, dir);
+			kfree(sg_map);
+			return NULL;
+		}
+
+		// Page in the user pages.
+		down_read(&current->mm->mmap_sem);
+		num_pages = get_user_pages(current, current->mm, udata, num_pages_reqd, 1, 0, pages, NULL);
+		up_read(&current->mm->mmap_sem);
+		if (num_pages <= 0) {
+			printk(KERN_ERR "riffa: fpga:%d chnl:%d, %s unable to pin any pages in memory\n", sc->id, chnl, dir);
+			kfree(pages);
+			kfree(sg_map);
+			return NULL;
+		}
+
+		// Create the scatterlist array.
+		if ((sgl = kcalloc(num_pages, sizeof(*sgl), GFP_KERNEL)) == NULL) {
+			printk(KERN_ERR "riffa: fpga:%d chnl:%d, %s could not allocate memory for scatterlist array\n", sc->id, chnl, dir);
+			for (i = 0; i < num_pages; ++i)
+				page_cache_release(pages[i]);
+			kfree(pages);
+			kfree(sg_map);
+			return NULL;
+		}
+
+		// Set the scatterlist values
+		fp_offset = (udata & (~PAGE_MASK));
+		sg_init_table(sgl, num_pages);
+		for (i = 0; i < num_pages; ++i) {
+			len = ((fp_offset + len_rem) > PAGE_SIZE ? (PAGE_SIZE - fp_offset) : len_rem);
+			sg_set_page(&sgl[i], pages[i], len, fp_offset);
+			len_rem -= len;
+			fp_offset = 0;
+		}
+
+		// Map the scatterlist values and write to the common buffer area
+		num_sg = dma_map_sg(&sc->dev->dev, sgl, num_pages, direction);
+		for_each_sg(sgl, sg, num_sg, i) {
+			hw_addr = sg_dma_address(sg);
+			hw_len = sg_dma_len(sg);
+			sg_buf_ptr[(i*4)+0] = (hw_addr & 0xFFFFFFFF);
+			sg_buf_ptr[(i*4)+1] = ((hw_addr>>32) & 0xFFFFFFFF);
+			sg_buf_ptr[(i*4)+2] = hw_len>>2; // Words!
+		}
+	}
+
+	// Provide scatter gather mappings for overflow data (all in spill common buffer)
+	while (len_rem == 0 && overflow_rem > 0 && num_sg < sc->num_sg) {
+		sg_buf_ptr[(num_sg*4)+0] = (sc->spill_buf_hw_addr & 0xFFFFFFFF);
+		sg_buf_ptr[(num_sg*4)+1] = ((sc->spill_buf_hw_addr>>32) & 0xFFFFFFFF);
+		sg_buf_ptr[(num_sg*4)+2] = SPILL_BUF_SIZE>>2; // Words!
+		num_sg++;
+		overflow_rem -= (SPILL_BUF_SIZE > overflow ? overflow : SPILL_BUF_SIZE);
+	}
+
+	// Populate the number of bytes mapped and other sg data
+	sg_map->direction = direction;
+	sg_map->num_pages = num_pages;
+	sg_map->num_sg = num_sg;
+	sg_map->length = (length - len_rem);
+	sg_map->overflow = (overflow - overflow_rem);
+	sg_map->pages = pages;
+	sg_map->sgl = sgl;
+
+	return sg_map;
+}
+
+/**
+ * Frees the scatterlist mappings in the struct sg_mapping pointer and frees all
+ * corresponding structs.
+ */
+static inline void free_sg_buf(struct fpga_state * sc, struct sg_mapping * sg_map) {
+	int i;
+
+	if (sg_map == NULL)
+		return;
+
+	// Unmap the pages.
+	if (sg_map->sgl != NULL)
+		dma_unmap_sg(&sc->dev->dev, sg_map->sgl, sg_map->num_pages, sg_map->direction);
+
+	// Free the pages (mark dirty if necessary).
+	if (sg_map->pages != NULL) {
+		if (sg_map->direction == DMA_FROM_DEVICE) {
+			for (i = 0; i < sg_map->num_pages; ++i) {
+				if (!PageReserved(sg_map->pages[i]))
+					SetPageDirty(sg_map->pages[i]);
+				page_cache_release(sg_map->pages[i]);
+			}
+		}
+		else {
+			for (i = 0; i < sg_map->num_pages; ++i) {
+				page_cache_release(sg_map->pages[i]);
+			}
+		}
+	}
+
+	// Free the structures.
+	if (sg_map->pages != NULL)
+		kfree(sg_map->pages);
+	if (sg_map->sgl != NULL)
+		kfree(sg_map->sgl);
+	kfree(sg_map);
+}
+
+/**
+ * Reads data from the FPGA. Will block until all the data is received from the
+ * FPGA unless timeout is non-zero. If timeout is non-zero, the function will 
+ * block until all the data is received or until the timeout expires. Received 
+ * data will be written directly into the user buffer, bufp, by the DMA process
+ * (using scatter gather). Up to len words (each word == 32 bits) will be 
+ * written. On success, the number of words received are returned. On error, 
+ * returns a negative value. 
+ */
+static inline unsigned int chnl_recv(struct fpga_state * sc, int chnl,
+				char  __user * bufp, unsigned int len, unsigned long long timeout)
+{
+	struct sg_mapping * sg_map;
+	long tymeouto;
+	long tymeout;
+	int nomsg;
+	unsigned int msg_type;
+	unsigned int msg;
+	int last = -1;
+	unsigned long long offset = 0;
+	unsigned long long length = 0;
+	unsigned long long overflow = 0;
+	unsigned long long capacity = (((unsigned long long)len)<<2);
+	unsigned long long recvd = 0;
+	unsigned long udata = (unsigned long)bufp;
+	unsigned long max_ptr;
+
+	DEFINE_WAIT(wait);
+
+	// Validate the parameters.
+	if (chnl >= sc->num_chnls || chnl < 0) {
+		printk(KERN_INFO "riffa: fpga:%d chnl:%d, recv channel invalid!\n", sc->id, chnl);
+		return 0;
+	}
+	if (udata & 0x3) {
+		printk(KERN_INFO "riffa: fpga:%d chnl:%d, recv user buffer must be 32 bit word aligned!\n", sc->id, chnl);
+		return -EINVAL;
+	}
+
+	// Convert timeout to jiffies.
+	tymeout = (timeout == 0 ? MAX_SCHEDULE_TIMEOUT : (timeout * HZ/1000 > LONG_MAX ? LONG_MAX : timeout * HZ/1000));
+	tymeouto = tymeout;
+
+	// Initialize the sg_maps
+	sc->recv[chnl]->sg_map_0 = NULL;
+	sc->recv[chnl]->sg_map_1 = NULL;
+
+	// Continue until we get a message or timeout.
+	while (1) {
+		while ((nomsg = pop_circ_queue(sc->recv[chnl]->msgs, &msg_type, &msg))) {
+			prepare_to_wait(&sc->recv[chnl]->waitq, &wait, TASK_INTERRUPTIBLE);
+			// Another check before we schedule.
+			if ((nomsg = pop_circ_queue(sc->recv[chnl]->msgs, &msg_type, &msg)))
+				tymeout = schedule_timeout(tymeout);
+			finish_wait(&sc->recv[chnl]->waitq, &wait);
+			if (signal_pending(current)) {
+				free_sg_buf(sc, sc->recv[chnl]->sg_map_0);
+				free_sg_buf(sc, sc->recv[chnl]->sg_map_1);
+				return -ERESTARTSYS;
+			}
+			if (!nomsg)
+				break;
+			if (tymeout == 0) {
+				printk(KERN_ERR "riffa: fpga:%d chnl:%d, recv timed out\n", sc->id, chnl);
+				free_sg_buf(sc, sc->recv[chnl]->sg_map_0);
+				free_sg_buf(sc, sc->recv[chnl]->sg_map_1);
+				return (unsigned int)(recvd>>2);
+			}
+		}
+		tymeout = tymeouto;
+
+		// Process the message.
+		switch (msg_type) {
+		case EVENT_TXN_OFFLAST:
+			// Read the offset and last flags (always before reading length)
+			offset = (((unsigned long long)(msg>>1))<<2);
+			last = (msg & 0x1);
+			break;
+
+		case EVENT_TXN_LEN:
+			// Read the length
+			length = (((unsigned long long)msg)<<2);
+			recvd = 0;
+			overflow = 0;
+			// Check for address overflow
+			max_ptr = (unsigned long)(udata + offset + length - 1);
+			if (max_ptr < udata) {
+				printk(KERN_ERR "riffa: fpga:%d chnl:%d, recv pointer address overflow\n", sc->id, chnl);
+				overflow = length;
+				length = 0;
+			}
+			// Check for capacity overflow
+			if ((offset + length) > capacity) {
+				if (offset > capacity) {
+					overflow = length;
+					length = 0;
+				}
+				else {
+					overflow = length + offset - capacity;
+					length = capacity - offset;
+				}
+			}
+			// Use the recv common buffer to share the scatter gather elements.
+			if (length > 0 || overflow > 0) {
+				udata = udata + offset;
+				sg_map = fill_sg_buf(sc, chnl, sc->recv[chnl]->buf_addr, udata, length, overflow, DMA_FROM_DEVICE);
+				if (sg_map == NULL || sg_map->num_sg == 0)
+					return (unsigned int)(recvd>>2);
+				// Update based on the sg_mapping
+				udata += sg_map->length;
+				length -= sg_map->length;
+				overflow -= sg_map->overflow;
+				sc->recv[chnl]->sg_map_1 = sg_map;
+				// Let FPGA know about the scatter gather buffer.
+				write_reg(sc, CHNL_REG(chnl, TX_SG_ADDR_LO_REG_OFF), (sc->recv[chnl]->buf_hw_addr & 0xFFFFFFFF));
+				write_reg(sc, CHNL_REG(chnl, TX_SG_ADDR_HI_REG_OFF), ((sc->recv[chnl]->buf_hw_addr>>32) & 0xFFFFFFFF));
+				write_reg(sc, CHNL_REG(chnl, TX_SG_LEN_REG_OFF), 4 * sg_map->num_sg);
+				DEBUG_MSG(KERN_INFO "riffa: fpga:%d chnl:%d, recv sg buf populated, %d sent\n", sc->id, chnl, sg_map->num_sg);
+			}
+			break;
+
+		case EVENT_SG_BUF_READ:
+			// Ignore if we haven't received offlast/len.
+			if (last == -1)
+				break;
+			// Release the previous scatter gather data.
+			if (sc->recv[chnl]->sg_map_0 != NULL)
+				recvd += sc->recv[chnl]->sg_map_0->length;
+			free_sg_buf(sc, sc->recv[chnl]->sg_map_0);
+			sc->recv[chnl]->sg_map_0 = NULL;
+			// Populate the common buffer with more scatter gather data?
+			if (length > 0 || overflow > 0) {
+				sg_map = fill_sg_buf(sc, chnl, sc->recv[chnl]->buf_addr, udata, length, overflow, DMA_FROM_DEVICE);
+				if (sg_map == NULL || sg_map->num_sg == 0) {
+					free_sg_buf(sc, sc->recv[chnl]->sg_map_0);
+					free_sg_buf(sc, sc->recv[chnl]->sg_map_1);
+					return (unsigned int)(recvd>>2);
+				}
+				// Update based on the sg_mapping
+				udata += sg_map->length;
+				length -= sg_map->length;
+				overflow -= sg_map->overflow;
+				sc->recv[chnl]->sg_map_0 = sc->recv[chnl]->sg_map_1;
+				sc->recv[chnl]->sg_map_1 = sg_map;
+				write_reg(sc, CHNL_REG(chnl, TX_SG_ADDR_LO_REG_OFF), (sc->recv[chnl]->buf_hw_addr & 0xFFFFFFFF));
+				write_reg(sc, CHNL_REG(chnl, TX_SG_ADDR_HI_REG_OFF), ((sc->recv[chnl]->buf_hw_addr>>32) & 0xFFFFFFFF));
+				write_reg(sc, CHNL_REG(chnl, TX_SG_LEN_REG_OFF), 4 * sg_map->num_sg);
+				DEBUG_MSG(KERN_INFO "riffa: fpga:%d chnl:%d, recv sg buf populated, %d sent\n", sc->id, chnl, sg_map->num_sg);
+			}
+			break;
+
+		case EVENT_TXN_DONE:
+			// Ignore if we haven't received offlast/len.
+			if (last == -1)
+				break;
+			// Update with the true value of words transferred.
+			recvd = (((unsigned long long)msg)<<2);
+			// Return if this was the last transaction.
+			free_sg_buf(sc, sc->recv[chnl]->sg_map_0);
+			free_sg_buf(sc, sc->recv[chnl]->sg_map_1);
+			sc->recv[chnl]->sg_map_0 = NULL;
+			sc->recv[chnl]->sg_map_1 = NULL;
+			DEBUG_MSG(KERN_INFO "riffa: fpga:%d chnl:%d, received %d words\n", sc->id, chnl, (unsigned int)(recvd>>2));
+			if (last)
+				return (unsigned int)(recvd>>2);
+			break;
+
+		default: 
+			printk(KERN_ERR "riffa: fpga:%d chnl:%d, received unknown msg: %08x\n", sc->id, chnl, msg);
+			break;
+		}
+	}
+	return 0;
+}
+
+/**
+ * Writes data to the FPGA channel specified. Will block until all the data is 
+ * sent to the FPGA unless a non-zero timeout is configured. If timeout is non-
+ * zero, then the function will block until all data is sent or when the timeout
+ * ms elapses. User data from the bufp pointer will be sent, up to len words
+ * (each word == 32 bits). The channel will be told how much data to expect and 
+ * at what offset. If last == 1, the FPGA channel will recognize this 
+ * transaction as complete after sending. If last == 0, the FPGA channel will 
+ * expect additional transactions. On success, returns the number of words sent. 
+ * On error, returns a negative value. 
+ */
+static inline unsigned int chnl_send(struct fpga_state * sc, int chnl,
+				const char  __user * bufp, unsigned int len, unsigned int offset, 
+				unsigned int last, unsigned long long timeout)
+{
+	struct sg_mapping * sg_map;
+	long tymeouto;
+	long tymeout;
+	int nomsg;
+	unsigned int msg_type;
+	unsigned int msg;
+	unsigned long long sent = 0;
+	unsigned long long length = (((unsigned long long)len)<<2);
+	unsigned long udata = (unsigned long)bufp;
+	unsigned long max_ptr;
+
+	DEFINE_WAIT(wait);
+
+	// Validate the parameters.
+	if (chnl >= sc->num_chnls || chnl < 0) {
+		printk(KERN_INFO "riffa: fpga:%d chnl:%d, send channel invalid!\n", sc->id, chnl);
+		return 0;
+	}
+	max_ptr = (unsigned long)(udata + length - 1);
+	if (max_ptr < udata) {
+		printk(KERN_ERR "riffa: fpga:%d chnl:%d, send pointer address overflow\n", sc->id, chnl);
+		return -EINVAL;
+	}
+	if (udata & 0x3) {
+		printk(KERN_INFO "riffa: fpga:%d chnl:%d, send user buffer must be 32 bit word aligned!\n", sc->id, chnl);
+		return -EINVAL;
+	}
+
+	// Convert timeout to jiffies.
+	tymeout = (timeout == 0 ? MAX_SCHEDULE_TIMEOUT : (timeout * HZ/1000 > LONG_MAX ? LONG_MAX : timeout * HZ/1000));
+	tymeouto = tymeout;
+
+	// Clear the message queue.
+	while (!pop_circ_queue(sc->send[chnl]->msgs, &msg_type, &msg));
+
+	// Initialize the sg_maps
+	sc->send[chnl]->sg_map_0 = NULL;
+	sc->send[chnl]->sg_map_1 = NULL;
+
+	// Let FPGA know about transfer.
+	DEBUG_MSG(KERN_INFO "riffa: fpga:%d chnl:%d, send (len:%d off:%d last:%d)\n", sc->id, chnl, len, offset, last);
+	write_reg(sc, CHNL_REG(chnl, RX_OFFLAST_REG_OFF), ((offset<<1) | last));
+	write_reg(sc, CHNL_REG(chnl, RX_LEN_REG_OFF), len);
+	if (len == 0)
+		return 0;
+
+	// Use the send common buffer to share the scatter gather data
+	sg_map = fill_sg_buf(sc, chnl, sc->send[chnl]->buf_addr, udata, length, 0, DMA_TO_DEVICE);
+	if (sg_map == NULL || sg_map->num_sg == 0)
+		return (unsigned int)(sent>>2);
+
+	// Update based on the sg_mapping
+	udata += sg_map->length;
+	length -= sg_map->length;
+	sc->send[chnl]->sg_map_1 = sg_map;
+
+	// Let FPGA know about the scatter gather buffer.
+	write_reg(sc, CHNL_REG(chnl, RX_SG_ADDR_LO_REG_OFF), (sc->send[chnl]->buf_hw_addr & 0xFFFFFFFF));
+	write_reg(sc, CHNL_REG(chnl, RX_SG_ADDR_HI_REG_OFF), ((sc->send[chnl]->buf_hw_addr>>32) & 0xFFFFFFFF));
+	write_reg(sc, CHNL_REG(chnl, RX_SG_LEN_REG_OFF), 4 * sg_map->num_sg);
+	DEBUG_MSG(KERN_INFO "riffa: fpga:%d chnl:%d, send sg buf populated, %d sent\n", sc->id, chnl, sg_map->num_sg);
+
+	// Continue until we get a message or timeout.
+	while (1) {
+		while ((nomsg = pop_circ_queue(sc->send[chnl]->msgs, &msg_type, &msg))) {
+			prepare_to_wait(&sc->send[chnl]->waitq, &wait, TASK_INTERRUPTIBLE);
+			// Another check before we schedule.
+			if ((nomsg = pop_circ_queue(sc->send[chnl]->msgs, &msg_type, &msg)))
+				tymeout = schedule_timeout(tymeout);
+			finish_wait(&sc->send[chnl]->waitq, &wait);
+			if (signal_pending(current)) {
+				free_sg_buf(sc, sc->send[chnl]->sg_map_0);
+				free_sg_buf(sc, sc->send[chnl]->sg_map_1);
+				return -ERESTARTSYS;
+			}
+			if (!nomsg)
+				break;
+			if (tymeout == 0) {
+				printk(KERN_ERR "riffa: fpga:%d chnl:%d, send timed out\n", sc->id, chnl);
+				free_sg_buf(sc, sc->send[chnl]->sg_map_0);
+				free_sg_buf(sc, sc->send[chnl]->sg_map_1);
+				return (unsigned int)(sent>>2);
+			}
+		}
+		tymeout = tymeouto;
+
+		// Process the message.
+		switch (msg_type) {
+		case EVENT_SG_BUF_READ:
+			// Release the previous scatter gather data?
+			if (sc->send[chnl]->sg_map_0 != NULL)
+				sent += sc->send[chnl]->sg_map_0->length;
+			free_sg_buf(sc, sc->send[chnl]->sg_map_0);
+			sc->send[chnl]->sg_map_0 = NULL;
+			// Populate the common buffer with more scatter gather data?
+			if (length > 0) {
+				sg_map = fill_sg_buf(sc, chnl, sc->send[chnl]->buf_addr, udata, length, 0, DMA_TO_DEVICE);
+				if (sg_map == NULL || sg_map->num_sg == 0) {
+					free_sg_buf(sc, sc->send[chnl]->sg_map_0);
+					free_sg_buf(sc, sc->send[chnl]->sg_map_1);
+					return (unsigned int)(sent>>2);
+				}
+				// Update based on the sg_mapping
+				udata += sg_map->length;
+				length -= sg_map->length;
+				sc->send[chnl]->sg_map_0 = sc->send[chnl]->sg_map_1;
+				sc->send[chnl]->sg_map_1 = sg_map;
+				write_reg(sc, CHNL_REG(chnl, RX_SG_ADDR_LO_REG_OFF), (sc->send[chnl]->buf_hw_addr & 0xFFFFFFFF));
+				write_reg(sc, CHNL_REG(chnl, RX_SG_ADDR_HI_REG_OFF), ((sc->send[chnl]->buf_hw_addr>>32) & 0xFFFFFFFF));
+				write_reg(sc, CHNL_REG(chnl, RX_SG_LEN_REG_OFF), 4 * sg_map->num_sg);
+				DEBUG_MSG(KERN_INFO "riffa: fpga:%d chnl:%d, send sg buf populated, %d sent\n", sc->id, chnl, sg_map->num_sg);
+			}
+			break;
+
+		case EVENT_TXN_DONE:
+			// Update with the true value of words transferred.
+			sent = (((unsigned long long)msg)<<2);
+			// Return as this is the end of the transaction.
+			free_sg_buf(sc, sc->send[chnl]->sg_map_0);
+			free_sg_buf(sc, sc->send[chnl]->sg_map_1);
+			DEBUG_MSG(KERN_INFO "riffa: fpga:%d chnl:%d, sent %d words\n", sc->id, chnl, (unsigned int)(sent>>2));
+			return (unsigned int)(sent>>2);
+			break;
+
+		default: 
+			printk(KERN_ERR "riffa: fpga:%d chnl:%d, received unknown msg: %08x\n", sc->id, chnl, msg);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * Populates the fpga_info struct with the current FPGA state information. On 
+ * success, returns 0. On error, returns a negative value. 
+ */
+static inline int list_fpgas(fpga_info_list * list)
+{
+	int i;
+	int num_fpgas = 0;
+	struct fpga_state * sc;
+
+	for (i = 0; i < NUM_FPGAS; ++i) {
+		if (atomic_read(&used_fpgas[i])) {
+			sc = fpgas[i];
+			list->id[num_fpgas] = sc->id;
+			list->num_chnls[num_fpgas] = sc->num_chnls;
+			list->vendor_id[num_fpgas] = sc->vendor_id;
+			list->device_id[num_fpgas] = sc->device_id;
+			memcpy(list->name[num_fpgas], sc->name, 16*sizeof(char));
+			num_fpgas++;
+		}
+	}
+	// Zero out the rest
+	for (i = num_fpgas; i < NUM_FPGAS; ++i) {
+		list->id[i] = -1;
+		list->num_chnls[i] = 0;
+		list->vendor_id[i] = 0;
+		list->device_id[i] = 0;
+		memset(list->name[i], 0, 16*sizeof(char));
+	}
+	list->num_fpgas = num_fpgas;
+
+	return 0;
+}
+
+/**
+ * Resets the driver for the specified FPGA. The fpga_state struct for all 
+ * channels will be reset as will the FPGA itself. 
+ */
+static inline void reset(int id)
+{
+	int i;
+	unsigned int dummy0;
+	unsigned int dummy1;
+	struct fpga_state * sc;
+
+	if (atomic_read(&used_fpgas[id])) {
+		sc = fpgas[id];
+		// Disable interrupts
+		atomic_set(&sc->intr_disabled, 1);
+		// Reset the FPGA
+		read_reg(sc, INFO_REG_OFF);
+
+		// Reset all the channels
+		for (i = 0; i < sc->num_chnls; ++i) {
+			while (!pop_circ_queue(sc->send[i]->msgs, &dummy0, &dummy1));
+			while (!pop_circ_queue(sc->recv[i]->msgs, &dummy0, &dummy1));
+			wake_up(&sc->send[i]->waitq);
+			wake_up(&sc->recv[i]->waitq);
+		}
+		// Enable interrupts
+		atomic_set(&sc->intr_disabled, 0);
+	}
+}
+
+/**
+ * Main entry point for reading and writing on the device. Return value depends 
+ * on ioctlnum and expected behavior. See code for details.
+ */
+static long fpga_ioctl(struct file *filp, unsigned int ioctlnum, 
+		unsigned long ioctlparam)
+{	
+	int rc;
+	fpga_chnl_io io;
+	fpga_info_list list;
+
+	switch (ioctlnum) {
+	case IOCTL_SEND:
+		if ((rc = copy_from_user(&io, (void *)ioctlparam, sizeof(fpga_chnl_io)))) {
+			printk(KERN_ERR "riffa: cannot read ioctl user parameter.\n");
+			return rc;
+		}
+		if (io.id < 0 || io.id >= NUM_FPGAS || !atomic_read(&used_fpgas[io.id]))
+			return 0;
+		return chnl_send(fpgas[io.id], io.chnl, io.data, io.len, io.offset, 
+				io.last, io.timeout);
+	case IOCTL_RECV:
+		if ((rc = copy_from_user(&io, (void *)ioctlparam, sizeof(fpga_chnl_io)))) {
+			printk(KERN_ERR "riffa: cannot read ioctl user parameter.\n");
+			return rc;
+		}
+		if (io.id < 0 || io.id >= NUM_FPGAS || !atomic_read(&used_fpgas[io.id]))
+			return 0;
+		return chnl_recv(fpgas[io.id], io.chnl, io.data, io.len, io.timeout);
+	case IOCTL_LIST:
+		list_fpgas(&list);
+		if ((rc = copy_to_user((void *)ioctlparam, &list, sizeof(fpga_info_list))))
+			printk(KERN_ERR "riffa: cannot write ioctl user parameter.\n");
+		return rc;
+	case IOCTL_RESET:
+		reset((int)ioctlparam);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+
+///////////////////////////////////////////////////////
+// PCI DRIVER HANDLERS
+///////////////////////////////////////////////////////
+
+/**
+ * Allocates and initializes chnl_dir structs for each channel. Returns the 
+ * number of chnl_dir structs allocated.
+ */
+static inline int __devinit allocate_chnls(struct pci_dev *dev, struct fpga_state * sc) 
+{
+	int i;
+	dma_addr_t hw_addr;
+
+	for (i = 0; i < sc->num_chnls; ++i) {
+		// Allocate the recv struct
+		sc->recv[i] = (struct chnl_dir *) kzalloc(sizeof(struct chnl_dir), GFP_KERNEL);
+		if (sc->recv[i] == NULL)
+			return i;
+		init_waitqueue_head(&sc->recv[i]->waitq);
+		if ((sc->recv[i]->msgs = init_circ_queue(5)) == NULL) {
+			kfree(sc->recv[i]);
+			return i;
+		}
+		sc->recv[i]->buf_addr = pci_alloc_consistent(dev, sc->sg_buf_size, &hw_addr);
+		sc->recv[i]->buf_hw_addr = hw_addr;
+		if (sc->recv[i]->buf_addr == NULL) {
+			free_circ_queue(sc->recv[i]->msgs);
+			kfree(sc->recv[i]);
+			return i;
+		}
+
+		// Allocate the send struct
+		sc->send[i] = (struct chnl_dir *) kzalloc(sizeof(struct chnl_dir), GFP_KERNEL);
+		if (sc->send[i] == NULL) {
+			pci_free_consistent(dev, sc->sg_buf_size, sc->recv[i]->buf_addr, 
+					(dma_addr_t)sc->recv[i]->buf_hw_addr);
+			free_circ_queue(sc->recv[i]->msgs);
+			kfree(sc->recv[i]);
+			return i;
+		}
+		init_waitqueue_head(&sc->send[i]->waitq);
+		if ((sc->send[i]->msgs = init_circ_queue(4)) == NULL) {
+			kfree(sc->send[i]);
+			pci_free_consistent(dev, sc->sg_buf_size, sc->recv[i]->buf_addr, 
+					(dma_addr_t)sc->recv[i]->buf_hw_addr);
+			free_circ_queue(sc->recv[i]->msgs);
+			kfree(sc->recv[i]);
+			return i;
+		}
+		sc->send[i]->buf_addr = pci_alloc_consistent(dev, sc->sg_buf_size, &hw_addr);
+		sc->send[i]->buf_hw_addr = hw_addr;
+		if (sc->send[i]->buf_addr == NULL) {
+			free_circ_queue(sc->send[i]->msgs);
+			kfree(sc->send[i]);
+			pci_free_consistent(dev, sc->sg_buf_size, sc->recv[i]->buf_addr, 
+					(dma_addr_t)sc->recv[i]->buf_hw_addr);
+			free_circ_queue(sc->recv[i]->msgs);
+			kfree(sc->recv[i]);
+			return i;
+		}
+	}
+
+	return i;
+}
+
+/**
+ * Called by the OS when the device is ready for access. Returns 0 on success,
+ * negative value on failure.
+ */
+static int __devinit fpga_probe(struct pci_dev *dev, const struct pci_device_id *id) 
+{
+	int i;
+	int j;
+	int error;
+	struct fpga_state * sc;
+	dma_addr_t hw_addr;
+	unsigned int reg;
+	u32 lnkctl_result = 0;
+	u32 devctl_result = 0;
+	u32 devctl2_result = 0;
+
+	// Setup the PCIe device.
+	error = pci_enable_device(dev);
+	if (error < 0) {
+		printk(KERN_ERR "riffa: pci_enable_device returned %d\n", error);
+		return (-ENODEV);
+	}
+
+	// Enable bus master
+	pci_set_master(dev);
+
+	// Set the mask size
+	error = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
+	if (!error)
+		error = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
+	if (error) {
+		printk(KERN_ERR "riffa: cannot set 64 bit DMA mode\n");
+		pci_disable_device(dev);
+		return error;
+	}
+
+	// Allocate device structure.
+	sc = kzalloc(sizeof(*sc), GFP_KERNEL);
+	if (sc == NULL) {
+		printk(KERN_ERR "riffa: not enough memory to allocate sc\n");
+		pci_disable_device(dev);
+		return (-ENOMEM);
+	}
+	atomic_set(&sc->intr_disabled, 0);
+	snprintf(sc->name, sizeof(sc->name), "%s%d", pci_name(dev), 0);
+	sc->vendor_id = dev->vendor;
+	sc->device_id = dev->device;
+	printk(KERN_INFO "riffa: found FPGA with name: %s\n", sc->name);
+	printk(KERN_INFO "riffa: vendor id: 0x%04X\n", sc->vendor_id);
+	printk(KERN_INFO "riffa: device id: 0x%04X\n", sc->device_id);
+
+	// Setup the BAR memory regions
+	error = pci_request_regions(dev, sc->name);
+	if (error < 0) {
+		printk(KERN_ERR "riffa: pci_request_regions returned error: %d\n", error);
+		pci_disable_device(dev);
+		kfree(sc);
+		return (-ENODEV);
+	}
+	
+	// PCI BAR 0
+	sc->bar0_addr = pci_resource_start(dev, 0);
+	sc->bar0_len = pci_resource_len(dev, 0);
+	sc->bar0_flags = pci_resource_flags(dev, 0);
+	printk(KERN_INFO "riffa: BAR 0 address: %llx\n", sc->bar0_addr);
+	printk(KERN_INFO "riffa: BAR 0 length: %lld bytes\n", sc->bar0_len);
+	if (sc->bar0_len != 1024) {
+		printk(KERN_ERR "riffa: BAR 0 incorrect length\n");
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return (-ENODEV);
+	}
+	sc->bar0 = ioremap(sc->bar0_addr, sc->bar0_len);
+	if (!sc->bar0) {
+		printk(KERN_ERR "riffa: could not ioremap BAR 0\n");
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return (-ENODEV);
+	}
+
+	// Setup MSI interrupts 
+	error = pci_enable_msi(dev);
+	if (error != 0) {
+		printk(KERN_ERR "riffa: pci_enable_msi returned error: %d\n", error);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return error;
+	}
+
+	// Request an interrupt
+	error = request_irq(dev->irq, intrpt_handler, IRQF_SHARED, sc->name, sc);
+	if (error != 0) {
+		printk(KERN_ERR "riffa: request_irq(%d) returned error: %d\n", dev->irq, error);
+		pci_disable_msi(dev);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return error;
+	}
+	sc->irq = dev->irq;
+	printk(KERN_INFO "riffa: MSI setup on irq %d\n", dev->irq);
+
+	// Set extended tag bit
+    error = pcie_capability_read_dword(dev,PCI_EXP_DEVCTL,&devctl_result);
+	if (error != 0) {
+		printk(KERN_ERR "riffa: pcie_capability_read_dword returned error: %d\n", error);
+		free_irq(dev->irq, sc);
+		pci_disable_msi(dev);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return error;
+	}
+	printk(KERN_INFO "riffa: PCIE_EXP_DEVCTL register: %x\n",devctl_result);  
+
+	error = pcie_capability_write_dword(dev,PCI_EXP_DEVCTL,(devctl_result|PCI_EXP_DEVCTL_EXT_TAG));
+	if (error != 0) {
+		printk(KERN_ERR "riffa: pcie_capability_write_dword returned error: %d\n", error);
+		free_irq(dev->irq, sc);
+		pci_disable_msi(dev);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return error;
+	}
+
+	// Set IDO bits
+	error = pcie_capability_read_dword(dev,PCI_EXP_DEVCTL2,&devctl2_result);
+	if (error != 0) {
+		printk(KERN_ERR "riffa: pcie_capability_read_dword returned error: %d\n", error);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);
+		free_irq(dev->irq, sc);
+		pci_disable_msi(dev);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return error;
+	}
+	printk(KERN_INFO "riffa: PCIE_EXP_DEVCTL2 register: %x\n",devctl2_result);  
+
+	error = pcie_capability_write_dword(dev,PCI_EXP_DEVCTL2,(devctl2_result | PCI_EXP_DEVCTL2_IDO_REQ_EN | PCI_EXP_DEVCTL2_IDO_CMP_EN));
+	if (error != 0) {
+		printk(KERN_ERR "riffa: pcie_capability_write_dword returned error: %d\n", error);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);
+		free_irq(dev->irq, sc);
+		pci_disable_msi(dev);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return error;
+	}
+
+	// Set RCB to 128
+    error = pcie_capability_read_dword(dev,PCI_EXP_LNKCTL,&lnkctl_result);
+	if (error != 0) {
+		printk(KERN_ERR "riffa: pcie_capability_read_dword returned error: %d\n", error);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL2,devctl2_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);
+		free_irq(dev->irq, sc);
+		pci_disable_msi(dev);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return error;
+	}
+	printk(KERN_INFO "riffa: PCIE_EXP_LNKCTL register: %x\n",lnkctl_result);  
+
+	error = pcie_capability_write_dword(dev,PCI_EXP_LNKCTL,(lnkctl_result|PCI_EXP_LNKCTL_RCB));
+	if (error != 0) {
+		printk(KERN_ERR "riffa: pcie_capability_write_dword returned error: %d\n", error);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL2,devctl2_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);
+		free_irq(dev->irq, sc);
+		pci_disable_msi(dev);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return error;
+	}
+	// Read device configuration
+	reg = read_reg(sc, INFO_REG_OFF);
+	sc->num_chnls = ((reg>>0) & 0xF);
+	sc->num_sg = SG_ELEMS*((reg>>19) & 0xF);
+	sc->sg_buf_size = SG_BUF_SIZE*((reg>>19) & 0xF);
+	printk(KERN_INFO "riffa: number of channels: %d\n", ((reg>>0) & 0xF));
+	printk(KERN_INFO "riffa: bus interface width: %d\n", ((reg>>19) & 0xF)<<5);
+	printk(KERN_INFO "riffa: bus master enabled: %d\n", ((reg>>4) & 0x1));
+	printk(KERN_INFO "riffa: negotiated link width: %d\n", ((reg>>5) & 0x3F));
+	printk(KERN_INFO "riffa: negotiated link rate: %d MTs\n", ((reg>>11) & 0x3)*2500);
+	printk(KERN_INFO "riffa: max downstream payload: %d bytes\n", 128<<((reg>>13) & 0x7) );
+	printk(KERN_INFO "riffa: max upstream payload: %d bytes\n", 128<<((reg>>16) & 0x7) );
+
+	if (((reg>>4) & 0x1) != 1) {
+		printk(KERN_ERR "riffa: bus master not enabled!\n");
+		pcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL2,devctl2_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);
+		free_irq(dev->irq, sc);
+		pci_disable_msi(dev);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return (-ENODEV);
+	}
+
+	if (((reg>>5) & 0x3F) == 0 || ((reg>>11) & 0x3) == 0) {
+		printk(KERN_ERR "riffa: bad link parameters!\n");
+		pcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL2,devctl2_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);
+		free_irq(dev->irq, sc);
+		pci_disable_msi(dev);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return (-ENODEV);
+	}
+
+	if ((reg & 0xF) == 0 || (reg & 0xF) > MAX_CHNLS) {
+		printk(KERN_ERR "riffa: bad number of channels!\n");
+		pcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL2,devctl2_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);
+		free_irq(dev->irq, sc);
+		pci_disable_msi(dev);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return (-ENODEV);
+	}
+
+	if (((reg>>19) & 0xF) == 0 || ((reg>>19) & 0xF) > MAX_BUS_WIDTH_PARAM) {
+		printk(KERN_ERR "riffa: bad bus width!\n");
+		pcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL2,devctl2_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);
+		free_irq(dev->irq, sc);
+		pci_disable_msi(dev);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return (-ENODEV);
+	}
+
+	// Create chnl_dir structs.
+	sc->recv = (struct chnl_dir **) kzalloc(sc->num_chnls*sizeof(struct chnl_dir*), GFP_KERNEL);  
+	sc->send = (struct chnl_dir **) kzalloc(sc->num_chnls*sizeof(struct chnl_dir*), GFP_KERNEL);  
+	if (sc->recv == NULL || sc->send == NULL) {
+		printk(KERN_ERR "riffa: not enough memory to allocate chnl_dir arrays\n");
+		if (sc->recv != NULL)
+			kfree(sc->recv);
+		if (sc->send != NULL)
+			kfree(sc->send);
+		pcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL2,devctl2_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);
+		free_irq(dev->irq, sc);
+		pci_disable_msi(dev);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return (-ENOMEM);
+	}
+	j = allocate_chnls(dev, sc);
+	if (j < sc->num_chnls) {
+		sc->num_chnls = j;
+		printk(KERN_ERR "riffa: not enough memory to allocate chnl_dir structs\n");
+		for (i = 0; i < sc->num_chnls; ++i) {
+			pci_free_consistent(dev, sc->sg_buf_size, sc->send[i]->buf_addr, 
+					(dma_addr_t)sc->send[i]->buf_hw_addr);
+			pci_free_consistent(dev, sc->sg_buf_size, sc->recv[i]->buf_addr, 
+					(dma_addr_t)sc->recv[i]->buf_hw_addr);
+			free_circ_queue(sc->send[i]->msgs);
+			free_circ_queue(sc->recv[i]->msgs);
+			kfree(sc->send[i]);
+			kfree(sc->recv[i]);
+		}
+		kfree(sc->recv);
+		kfree(sc->send);
+		pcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL2,devctl2_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);
+		free_irq(dev->irq, sc);
+		pci_disable_msi(dev);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return (-ENOMEM);
+	}
+
+	// Create spill buffer (for overflow on receive).
+	sc->spill_buf_addr = pci_alloc_consistent(dev, SPILL_BUF_SIZE, &hw_addr);
+	sc->spill_buf_hw_addr = hw_addr;
+	if (sc->spill_buf_addr == NULL) {
+		printk(KERN_ERR "riffa: not enough memory to allocate spill buffer\n");
+		for (i = 0; i < sc->num_chnls; ++i) {
+			pci_free_consistent(dev, sc->sg_buf_size, sc->send[i]->buf_addr, 
+					(dma_addr_t)sc->send[i]->buf_hw_addr);
+			pci_free_consistent(dev, sc->sg_buf_size, sc->recv[i]->buf_addr, 
+					(dma_addr_t)sc->recv[i]->buf_hw_addr);
+			free_circ_queue(sc->send[i]->msgs);
+			free_circ_queue(sc->recv[i]->msgs);
+			kfree(sc->send[i]);
+			kfree(sc->recv[i]);
+		}
+		pcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL2,devctl2_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);
+		kfree(sc->recv);
+		kfree(sc->send);
+		free_irq(dev->irq, sc);
+		pci_disable_msi(dev);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+	}
+
+	// Save pointer to structure 
+	pci_set_drvdata(dev, sc);
+	sc->dev = dev;
+	sc->id = -1;
+	for (i = 0; i < NUM_FPGAS; i++) {
+		if (!atomic_xchg(&used_fpgas[i], 1)) {
+			sc->id = i;
+			fpgas[i] = sc;
+			break;
+		}
+	}
+	if (sc->id == -1) {
+		printk(KERN_ERR "riffa: could not save FPGA information, %d is limit.\n", NUM_FPGAS);
+		for (i = 0; i < sc->num_chnls; ++i) {
+			pci_free_consistent(dev, sc->sg_buf_size, sc->send[i]->buf_addr, 
+					(dma_addr_t)sc->send[i]->buf_hw_addr);
+			pci_free_consistent(dev, sc->sg_buf_size, sc->recv[i]->buf_addr, 
+					(dma_addr_t)sc->recv[i]->buf_hw_addr);
+			free_circ_queue(sc->send[i]->msgs);
+			free_circ_queue(sc->recv[i]->msgs);
+			kfree(sc->send[i]);
+			kfree(sc->recv[i]);
+		}
+		kfree(sc->recv);
+		kfree(sc->send);
+		pci_free_consistent(dev, SPILL_BUF_SIZE, sc->spill_buf_addr, 
+				(dma_addr_t)sc->spill_buf_hw_addr);
+		pcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL2,devctl2_result);
+		pcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);
+		free_irq(dev->irq, sc);
+		pci_disable_msi(dev);
+		iounmap(sc->bar0);
+		pci_release_regions(dev);
+		pci_disable_device(dev);
+		kfree(sc);
+		return (-ENOMEM);
+	}
+	else {
+		printk(KERN_INFO "riffa: saved FPGA with id: %d\n", sc->id);
+	}
+
+	return 0;
+}
+
+/**
+ * Called when the device is unloaded.
+ */
+static void __devexit fpga_remove(struct pci_dev *dev) 
+{
+	int i;
+	u32 result;
+	struct fpga_state * sc;
+
+	pcie_capability_read_dword(dev,PCI_EXP_DEVCTL,&result);
+	pcie_capability_write_dword(dev,PCI_EXP_DEVCTL,result & ~(PCI_EXP_DEVCTL_EXT_TAG | PCI_EXP_DEVCTL_RELAX_EN));
+
+	pcie_capability_read_dword(dev,PCI_EXP_DEVCTL2,&result);
+	pcie_capability_write_dword(dev,PCI_EXP_DEVCTL2,result & ~(PCI_EXP_DEVCTL2_IDO_REQ_EN | PCI_EXP_DEVCTL2_IDO_CMP_EN));
+
+	pcie_capability_read_dword(dev,PCI_EXP_DEVCTL,&result);
+	pcie_capability_write_dword(dev,PCI_EXP_LNKCTL,result & (~PCI_EXP_LNKCTL_RCB));
+
+	if ((sc = (struct fpga_state *)pci_get_drvdata(dev)) != NULL) {
+		// Free structs, memory regions, etc.
+		atomic_set(&used_fpgas[sc->id], 0);
+		for (i = 0; i < sc->num_chnls; ++i) {
+			pci_free_consistent(dev, sc->sg_buf_size, sc->send[i]->buf_addr, 
+					(dma_addr_t)sc->send[i]->buf_hw_addr);
+			pci_free_consistent(dev, sc->sg_buf_size, sc->recv[i]->buf_addr, 
+					(dma_addr_t)sc->recv[i]->buf_hw_addr);
+			free_circ_queue(sc->send[i]->msgs);
+			free_circ_queue(sc->recv[i]->msgs);
+			kfree(sc->send[i]);
+			kfree(sc->recv[i]);
+		}
+		kfree(sc->recv);
+		kfree(sc->send);
+		pci_free_consistent(dev, SPILL_BUF_SIZE, sc->spill_buf_addr, 
+				(dma_addr_t)sc->spill_buf_hw_addr);
+		free_irq(dev->irq, sc);
+		iounmap(sc->bar0);
+		kfree(sc);
+	}
+	pci_disable_msi(dev);
+	pci_release_regions(dev);
+	pci_disable_device(dev);
+	pci_set_drvdata(dev, NULL);
+}
+
+
+///////////////////////////////////////////////////////
+// MODULE INIT/EXIT FUNCTIONS
+///////////////////////////////////////////////////////
+
+static DEFINE_PCI_DEVICE_TABLE(fpga_ids) = {
+	{PCI_DEVICE(VENDOR_ID0, PCI_ANY_ID)},
+	{PCI_DEVICE(VENDOR_ID1, PCI_ANY_ID)},
+	{0},
+};
+
+MODULE_DEVICE_TABLE(pci, fpga_ids);
+static struct pci_driver fpga_driver = {
+	.name		= DEVICE_NAME,
+	.id_table	= fpga_ids,
+	.probe		= fpga_probe,
+	.remove		= __devexit_p(fpga_remove),
+};
+
+static const struct file_operations fpga_fops = {
+	.owner			= THIS_MODULE,
+	.unlocked_ioctl	= fpga_ioctl,
+};
+
+/**
+ * Called to initialize the PCI device. 
+ */
+static int __init fpga_init(void) 
+{	
+	int i;
+	int error;
+
+	for (i = 0; i < NUM_FPGAS; i++)
+		atomic_set(&used_fpgas[i], 0);
+
+	error = pci_register_driver(&fpga_driver);
+	if (error != 0) {
+		printk(KERN_ERR "riffa: pci_module_register returned %d\n", error);
+		return (error);
+	}
+
+	error = register_chrdev(MAJOR_NUM, DEVICE_NAME, &fpga_fops);
+	if (error < 0) {
+		printk(KERN_ERR "riffa: register_chrdev returned %d\n", error);
+		return (error);
+	}
+
+	mymodule_class = class_create(THIS_MODULE, DEVICE_NAME);
+	if (IS_ERR(mymodule_class)) {
+		error = PTR_ERR(mymodule_class);
+		printk(KERN_ERR "riffa: class_create() returned %d\n", error);
+		return (error);
+	}
+
+	devt = MKDEV(MAJOR_NUM, 0);
+	device_create(mymodule_class, NULL, devt, "%s", DEVICE_NAME);
+
+	return 0;
+}
+
+/**
+ * Called to destroy the PCI device.
+ */
+static void __exit fpga_exit(void)
+{
+	device_destroy(mymodule_class, devt); 
+	class_destroy(mymodule_class);
+	pci_unregister_driver(&fpga_driver);
+	unregister_chrdev(MAJOR_NUM, DEVICE_NAME);
+}
+
+module_init(fpga_init);
+module_exit(fpga_exit);
+
diff --git a/driver/linux/riffa_driver.h b/driver/linux/riffa_driver.h
new file mode 100644
index 0000000..4dbf95c
--- /dev/null
+++ b/driver/linux/riffa_driver.h
@@ -0,0 +1,131 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+/*
+ * Filename: riffa_driver.h
+ * Version: 2.0
+ * Description: Linux PCIe device driver for RIFFA. Uses Linux kernel APIs in
+ *  version 2.6.27+ (tested on version 2.6.32 - 3.3.0).
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#ifndef RIFFA_DRIVER_H
+#define RIFFA_DRIVER_H
+
+#include <linux/ioctl.h>
+
+#define DBUG 1
+
+#ifdef DEBUG
+#define DEBUG_MSG(...) printk(__VA_ARGS__)
+#else
+#define DEBUG_MSG(...)
+#endif
+
+
+// The major device number. We can't rely on dynamic registration because ioctls
+// need to know it.
+#define MAJOR_NUM 100
+#define DEVICE_NAME "riffa"
+#define VENDOR_ID0 0x10EE
+#define VENDOR_ID1 0x1172
+
+// Message events for readmsgs/writemsgs queues.
+#define EVENT_TXN_LEN				1
+#define EVENT_TXN_OFFLAST			2
+#define EVENT_TXN_DONE				3
+#define EVENT_SG_BUF_READ			4
+
+// Constants and device offsets
+#define NUM_FPGAS					5 	// max # of FPGAs to support in a single PC
+#define MAX_CHNLS					12	// max # of channels per FPGA
+#define MAX_BUS_WIDTH_PARAM			4	// max bus width parameter
+#define SG_BUF_SIZE					(4*1024)	// size of shared SG buffer
+#define SG_ELEMS					200 // # of SG elements to transfer at a time
+#define SPILL_BUF_SIZE				(4*1024)	// size of shared spill common buffer
+
+#define RX_SG_LEN_REG_OFF			0x0	// config offset for RX SG buf length
+#define RX_SG_ADDR_LO_REG_OFF		0x1	// config offset for RX SG buf low addr
+#define RX_SG_ADDR_HI_REG_OFF		0x2	// config offset for RX SG buf high addr
+#define RX_LEN_REG_OFF				0x3	// config offset for RX txn length
+#define RX_OFFLAST_REG_OFF			0x4	// config offset for RX txn last/offset
+#define RX_TNFR_LEN_REG_OFF			0xD	// config offset for RX transfer length
+#define TX_SG_LEN_REG_OFF			0x5	// config offset for TX SG buf length
+#define TX_SG_ADDR_LO_REG_OFF		0x6	// config offset for TX SG buf low addr
+#define TX_SG_ADDR_HI_REG_OFF		0x7	// config offset for TX SG buf high addr
+#define TX_LEN_REG_OFF				0x8	// config offset for TX txn length
+#define TX_OFFLAST_REG_OFF			0x9	// config offset for TX txn last/offset
+#define TX_TNFR_LEN_REG_OFF			0xE	// config offset for TX transfer length
+
+#define INFO_REG_OFF				0xA	// config offset for link info
+
+#define IRQ_REG0_OFF				0xB	// config offset for interrupt reg 0
+#define IRQ_REG1_OFF				0xC	// config offset for interrupt reg 1
+
+
+// Structs
+struct fpga_chnl_io
+{
+	int id;
+	int chnl;
+	unsigned int len;
+	unsigned int offset;
+	unsigned int last;
+	unsigned long long timeout;
+	char * data;
+};
+typedef struct fpga_chnl_io fpga_chnl_io;
+
+struct fpga_info_list
+{
+	int num_fpgas;
+	int id[NUM_FPGAS];
+	int num_chnls[NUM_FPGAS];
+	char name[NUM_FPGAS][16];
+	int vendor_id[NUM_FPGAS];
+	int device_id[NUM_FPGAS];
+};
+typedef struct fpga_info_list fpga_info_list;
+
+// IOCTLs
+#define IOCTL_SEND _IOW(MAJOR_NUM, 1, fpga_chnl_io *)
+#define IOCTL_RECV _IOR(MAJOR_NUM, 2, fpga_chnl_io *)
+#define IOCTL_LIST _IOR(MAJOR_NUM, 3, fpga_info_list *)
+#define IOCTL_RESET _IOW(MAJOR_NUM, 4, int)
+
+
+
+#endif
diff --git a/driver/windows/README.txt b/driver/windows/README.txt
new file mode 100755
index 0000000..a6aed3a
--- /dev/null
+++ b/driver/windows/README.txt
@@ -0,0 +1,40 @@
+To build the Windows driver:
+
+1) Install Windows Driver Development Kit supporting Windows 7 (tested on 
+   version 7600.16385.1).
+2) Open a DDK command window environment for Windows 7 (which ever version 
+   you're targeting).
+3) Move to the directory containing this README.txt and run: build -ceZ
+4) The driver should be built and ready in the output directory along with a
+   Windows 7 catalog file and the coinstaller DLLs.
+
+A few notes:
+
+- You will need to sign the driver (riffa.sys) and catalog file (riffa.cat) 
+  before you can install it on a x64 Windows 7 or Vista computer. The build 
+  process will attempt to sign the catalog file with the UCSD certificate. You
+  don't have that, so you won't get a signed driver simply by building. You'll
+  need to get a certificate from a certificate authority that is capable of 
+  cross-certificate kernel driver signing. See this page for more details:
+  http://msdn.microsoft.com/en-us/windows/hardware/gg487315.aspx
+    
+- Debugging on Windows is difficult because there exists no kernel log file.
+  Drivers are supposed to log messages using a trace events framework which is
+  overly complex and requires developer tools to first collect the output and
+  then more (different) tools to make the output human readable. Instead, this
+  driver writes normal log messages via a kernel debugger facility. To see the
+  messages you'll need the Windows Development Kit debugger (WinDbg) or a small
+  utility called DbgView. DbgView is a standalone kernel debug viewer that can
+  be downloaded from Microsoft here:
+  http://technet.microsoft.com/en-us/sysinternals/bb896647.aspx
+  Just start with administrator privileges and be sure to enable Capture Kernel, 
+  Capture Events, and Capture Verbose Kernel Output.
+
+- Building with the checked environment will produce a version of the driver
+  with verbose debugging output. Building with the free environment will 
+  produce a version of the driver with minimal messaging output. The debug 
+  version will have a "(Debug)" label in the Windows device manager, so you 
+  can tell which version is installed.
+
+- Inno Setup scripts produce a Windows Installer. You may use our script if you
+  like.
diff --git a/driver/windows/dirs b/driver/windows/dirs
new file mode 100644
index 0000000..addbfb4
--- /dev/null
+++ b/driver/windows/dirs
@@ -0,0 +1,2 @@
+DIRS= \
+     sys
\ No newline at end of file
diff --git a/driver/windows/install/install.bat b/driver/windows/install/install.bat
new file mode 100755
index 0000000..861cd5b
--- /dev/null
+++ b/driver/windows/install/install.bat
@@ -0,0 +1,25 @@
+@echo off
+
+rmdir /s /q build
+md build
+md build\x86
+md build\x64
+
+copy win7.iss .\build
+copy license.txt .\build
+
+xcopy /E /H /K /I /Y %1 .\build\x86
+xcopy /E /H /K /I /Y %2 .\build\x64
+xcopy /E /H /K /I /Y ..\..\..\c_c++\windows .\build\c_c++
+xcopy /E /H /K /I /Y ..\..\..\java .\build\java
+xcopy /E /H /K /I /Y ..\..\..\python .\build\python
+xcopy /E /H /K /I /Y ..\..\..\matlab .\build\matlab
+
+if "%3" == "chk" (
+    "c:\program files\inno setup 5\iscc.exe" /dDebug="1" /o.\build .\build\win7.iss 
+) else (
+    "c:\program files\inno setup 5\iscc.exe" /o.\build .\build\win7.iss 
+)
+signtool sign /v /s my /n "University of California, San Diego" /t http://timestamp.verisign.com/scripts/timestamp.dll .\build\setup.exe
+
+
diff --git a/driver/windows/install/license.txt b/driver/windows/install/license.txt
new file mode 100755
index 0000000..a28b107
--- /dev/null
+++ b/driver/windows/install/license.txt
@@ -0,0 +1,34 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+//
+// * Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// * Redistributions in binary form must reproduce the above
+// copyright notice, this list of conditions and the following
+// disclaimer in the documentation and/or other materials provided
+// with the distribution.
+//
+// * Neither the name of The Regents of the University of California
+// nor the names of its contributors may be used to endorse or
+// promote products derived from this software without specific
+// prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
\ No newline at end of file
diff --git a/driver/windows/install/win7.iss b/driver/windows/install/win7.iss
new file mode 100755
index 0000000..5e6a87a
--- /dev/null
+++ b/driver/windows/install/win7.iss
@@ -0,0 +1,87 @@
+; -- 64Bit.iss --
+; Demonstrates installation of a program built for the x64 (a.k.a. AMD64)
+; architecture.
+; To successfully run this installation and the program it installs,
+; you must have a "x64" edition of Windows.
+
+; SEE THE DOCUMENTATION FOR DETAILS ON CREATING .ISS SCRIPT FILES!
+#ifdef Debug
+#define DebugMsg1 "%n%nNOTE: This version has been compiled to output additional debug messages (with some performance overhead)."
+#else
+#define DebugMsg1 ""
+#endif
+
+[Setup]
+AppName=RIFFA
+AppVersion=2.0
+AppPublisher=University of California, San Diego
+AppPublisherURL=https://sites.google.com/a/eng.ucsd.edu/matt-jacobsen/riffa
+AppCopyright=Copyright (C) 2012 The Regents of the University of California. All Rights Reserved.
+LicenseFile=license.txt
+PrivilegesRequired=admin
+MinVersion=6.1
+OnlyBelowVersion=6.2
+DisableProgramGroupPage=yes
+Compression=lzma2
+SolidCompression=yes
+UsePreviousAppDir=no
+DefaultDirName={pf}\Riffa
+OutputDir=outputdir
+; "ArchitecturesInstallIn64BitMode=x64" requests that the install be
+; done in "64-bit mode" on x64, meaning it should use the native
+; 64-bit Program Files directory and the 64-bit view of the registry.
+ArchitecturesInstallIn64BitMode=x64
+
+[Messages]
+WelcomeLabel1=Welcome to the [name] Setup Wizard
+WelcomeLabel2=This will install the [name/ver] FPGA drivers and C/C++ bindings on your computer.{#DebugMsg1}%n%nSee the install program directory for details on installing other language bindings.%n%nIt is recommended that you close all other applications and disable any anti virus before continuing.
+FinishedLabelNoIcons=Setup has finished installing [name/ver] on your computer.%n%nAny [name] compatible FPGA devices should be detected upon reboot.
+
+[Dirs]
+Name: "{app}\c_c++"; Permissions: users-modify
+Name: "{app}\java"; Permissions: users-modify
+Name: "{app}\python"; Permissions: users-modify
+Name: "{app}\matlab"; Permissions: users-modify
+
+[Files]
+Source: "c_c++\x86\riffa.lib"; DestDir: "{app}\c_c++"; DestName: "riffa32.lib"
+Source: "c_c++\x86\riffa.h"; DestDir: "{app}\c_c++"; Check: "not IsWin64"
+Source: "c_c++\x86\sample_app\README.txt"; DestDir: "{app}\c_c++"; Check: "not IsWin64"
+Source: "c_c++\x86\sample_app\timer.h"; DestDir: "{app}\c_c++"; Check: "not IsWin64"
+Source: "c_c++\x86\sample_app\testutil.c"; DestDir: "{app}\c_c++"; Check: "not IsWin64"
+Source: "c_c++\x86\sample_app\testutil.exe"; DestDir: "{app}\c_c++"; Check: "not IsWin64"
+Source: "c_c++\x64\riffa.lib"; DestDir: "{app}\c_c++"; DestName: "riffa64.lib"; Check: IsWin64
+Source: "c_c++\x64\riffa.h"; DestDir: "{app}\c_c++"; Check: IsWin64
+Source: "c_c++\x64\sample_app\README.txt"; DestDir: "{app}\c_c++"; Check: IsWin64
+Source: "c_c++\x64\sample_app\timer.h"; DestDir: "{app}\c_c++"; Check: IsWin64
+Source: "c_c++\x64\sample_app\testutil.c"; DestDir: "{app}\c_c++"; Check: IsWin64
+Source: "c_c++\x64\sample_app\testutil.exe"; DestDir: "{app}\c_c++"; Check: IsWin64
+
+Source: "java\README.txt"; DestDir: "{app}\java"
+Source: "java\riffa.jar"; DestDir: "{app}\java"
+Source: "java\SampleApp.java"; DestDir: "{app}\java"
+
+Source: "matlab\README.txt"; DestDir: "{app}\matlab"
+Source: "matlab\Riffa.m"; DestDir: "{app}\matlab"
+
+Source: "python\dist\README.txt"; DestDir: "{app}\python"
+Source: "python\dist\riffa-2.0.zip"; DestDir: "{app}\python"
+Source: "python\sample_app\sampleapp.py"; DestDir: "{app}\python"
+
+Source: "x86\riffa.sys"; DestDir: "{tmp}"; Check: "not IsWin64"
+Source: "x86\riffa.inf"; DestDir: "{tmp}"; Check: "not IsWin64"
+Source: "x86\riffa.cat"; DestDir: "{tmp}"; Check: "not IsWin64"
+Source: "x86\WdfCoInstaller01009.dll"; DestDir: "{tmp}"; Check: "not IsWin64"
+Source: "x86\WdfCoInstaller01009_chk.dll"; DestDir: "{tmp}"; Check: "not IsWin64"
+Source: "x64\riffa.sys"; DestDir: "{tmp}"; Check: IsWin64
+Source: "x64\riffa.inf"; DestDir: "{tmp}"; Check: IsWin64
+Source: "x64\riffa.cat"; DestDir: "{tmp}"; Check: IsWin64
+Source: "x64\WdfCoInstaller01009.dll"; DestDir: "{tmp}"; Check: IsWin64
+Source: "x64\WdfCoInstaller01009_chk.dll"; DestDir: "{tmp}"; Check: IsWin64
+
+Source: "c_c++\x86\riffa.dll"; DestDir: {sys}; Flags: 32bit
+Source: "c_c++\x64\riffa.dll"; DestDir: {sys}; Flags: 64bit; Check: IsWin64
+
+[Run]
+Filename: "{sys}\pnputil.exe"; Parameters: " -i -a {tmp}\riffa.inf"; WorkingDir: "{tmp}"; Description: "Install driver"; StatusMsg: "Installing drivers..."; Flags: runascurrentuser runhidden;
+
diff --git a/driver/windows/sys/makefile b/driver/windows/sys/makefile
new file mode 100755
index 0000000..7c5e927
--- /dev/null
+++ b/driver/windows/sys/makefile
@@ -0,0 +1,7 @@
+#
+# DO NOT EDIT THIS FILE!!!  Edit .\sources. if you want to add a new source
+# file to this component.  This file merely indirects to the real make file
+# that is shared by all the components of Windows
+#
+!INCLUDE $(NTMAKEENV)\makefile.def
+
diff --git a/driver/windows/sys/makefile.inc b/driver/windows/sys/makefile.inc
new file mode 100755
index 0000000..7d1cd6a
--- /dev/null
+++ b/driver/windows/sys/makefile.inc
@@ -0,0 +1,28 @@
+_LNG=$(LANGUAGE)
+_INX=.
+STAMP=stampinf -f $@ -a $(_BUILDARCH) -k $(KMDF_VERSION_MAJOR).$(KMDF_VERSION_MINOR)
+
+
+$(OBJ_PATH)\$(O)\$(INF_NAME).inf: $(_INX)\$(INF_NAME).inx
+    copy $(_INX)\$(@B).inx $@
+    $(STAMP)
+!   if "$(DDKBUILDENV)" == "chk"
+        echo RIFFA.DEBUG=" (Debug)" >> $@
+!   else    
+        echo RIFFA.DEBUG="" >> $@
+!   endif    
+
+
+POST:
+    copy $(BASEDIR)\redist\wdf\$(_BUILDARCH)\WdfCoInstaller*.dll $(OBJ_PATH)\$(O)
+!   if "$(DDK_TARGET_OS)" == "Win7"
+!       if "$(_BUILDARCH)" == "x86"
+            inf2cat /driver:$(OBJ_PATH)\$(O) /os:7_x86
+!       else 
+            inf2cat /driver:$(OBJ_PATH)\$(O) /os:7_x64
+!       endif 
+!   endif 
+    signtool sign /v /ac "$(_INX)\GlobalSign Root CA.crt" /s my /n "University of California, San Diego" /t http://timestamp.verisign.com/scripts/timestamp.dll $(OBJ_PATH)\$(O)\$(INF_NAME).cat
+    signtool sign /v /ac "$(_INX)\GlobalSign Root CA.crt" /s my /n "University of California, San Diego" /t http://timestamp.verisign.com/scripts/timestamp.dll $(OBJ_PATH)\$(O)\$(INF_NAME).sys
+
+    
\ No newline at end of file
diff --git a/driver/windows/sys/precomp.h b/driver/windows/sys/precomp.h
new file mode 100755
index 0000000..8731c24
--- /dev/null
+++ b/driver/windows/sys/precomp.h
@@ -0,0 +1,21 @@
+#define WIN9X_COMPAT_SPINLOCK
+#include <ntddk.h>
+#pragma warning(disable:4201)  // nameless struct/union warning
+
+#include <stdarg.h>
+#include <wdf.h>
+#include <ntstrsafe.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+#pragma warning(default:4201)
+
+#include <initguid.h> // required for GUID definitions
+#include <wdmguid.h>  // required for WMILIB_CONTEXT
+
+
+#include "riffa_driver.h"
+#include "riffa_private.h"
+#include "trace.h"
+
+
diff --git a/driver/windows/sys/riffa.c b/driver/windows/sys/riffa.c
new file mode 100755
index 0000000..eb833c0
--- /dev/null
+++ b/driver/windows/sys/riffa.c
@@ -0,0 +1,2029 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+//
+// * Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// * Redistributions in binary form must reproduce the above
+// copyright notice, this list of conditions and the following
+// disclaimer in the documentation and/or other materials provided
+// with the distribution.
+//
+// * Neither the name of The Regents of the University of California
+// nor the names of its contributors may be used to endorse or
+// promote products derived from this software without specific
+// prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+#include "precomp.h"
+
+// The trace message header (.tmh) file must be included in a source file
+// before any WPP macro calls and after defining a WPP_CONTROL_GUIDS
+// macro (defined in toaster.h). During the compilation, WPP scans the source
+// files for DoTraceMessage() calls and builds a .tmh file which stores a unique
+// data GUID for each message, the text resource string for each message,
+// and the data types of the variables passed in for each message.  This file
+// is automatically generated by the WPP preprocessor.
+//
+#include "riffa.tmh"
+
+
+#ifdef ALLOC_PRAGMA
+#pragma alloc_text (INIT, DriverEntry)
+#pragma alloc_text (PAGE, RiffaEvtDeviceAdd)
+#pragma alloc_text (PAGE, RiffaEvtDriverContextCleanup)
+#pragma alloc_text (PAGE, RiffaEvtDevicePrepareHardware)
+#pragma alloc_text (PAGE, RiffaEvtDeviceReleaseHardware)
+
+#endif
+
+/**
+ * DriverEntry initializes the driver and is the first routine called by the
+ * system after the driver is loaded. DriverEntry configures and creates a WDF driver
+ * object.
+ *	.
+ * DriverObject - represents the instance of the function driver that is loaded
+ * into memory. DriverObject is allocated by the system before the
+ * driver is loaded, and it is released by the system after the system unloads
+ * the function driver from memory.
+ *
+ * RegistryPath - represents the driver specific path in the Registry.
+ * The function driver can use the path to store driver related data between
+ * reboots. The path does not store hardware instance specific data.
+ *
+ * Returns STATUS_SUCCESS if successful, STATUS_UNSUCCESSFUL otherwise.
+ */
+NTSTATUS DriverEntry(IN PDRIVER_OBJECT  DriverObject, IN PUNICODE_STRING RegistryPath)
+{
+	NTSTATUS status = STATUS_SUCCESS;
+	WDF_DRIVER_CONFIG config;
+	WDF_OBJECT_ATTRIBUTES attributes;
+
+	// Initialize WDF WPP tracing.
+	WPP_INIT_TRACING(DriverObject, RegistryPath);
+
+	// TraceEvents function is mapped to DoTraceMessage provided by
+	// WPP by using a directive in the sources file.
+	TraceEvents(TRACE_LEVEL_INFORMATION, DBG_INIT, "RIFFA Driver.");
+	TraceEvents(TRACE_LEVEL_INFORMATION, DBG_INIT, "Built %s %s", __DATE__, __TIME__);
+
+	// Initialize the Driver Config structure.
+	WDF_DRIVER_CONFIG_INIT(&config, RiffaEvtDeviceAdd);
+
+	// Register a cleanup callback so that we can call WPP_CLEANUP when
+	// the framework driver object is deleted during driver unload.
+	WDF_OBJECT_ATTRIBUTES_INIT(&attributes);
+	attributes.EvtCleanupCallback = RiffaEvtDriverContextCleanup;
+
+	// Create the WDFDRIVER object
+	status = WdfDriverCreate(DriverObject, RegistryPath, &attributes, &config,
+		WDF_NO_HANDLE);
+
+	if (!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: WdfDriverCreate failed\n");
+
+		// Cleanup tracing here because DriverContextCleanup will not be called
+		// as we have failed to create WDFDRIVER object itself.
+		WPP_CLEANUP(DriverObject);
+	}
+
+	return status;
+}
+
+
+
+/******************************************************************************
+ * PNP EVENT CALLBACKS
+ *****************************************************************************/
+
+/**
+ * Called by the framework in response to AddDevice call from the PnP manager.
+ * We create and initialize a WDF device object to represent a new instance of
+ * our device.
+ *	.
+ * Driver - Handle to a framework driver object created in DriverEntry
+ *
+ * DeviceInit - Pointer to a framework-allocated WDFDEVICE_INIT structure.
+ *
+ * Returns STATUS_SUCCESS if successful, another status otherwise.
+ */
+NTSTATUS RiffaEvtDeviceAdd(IN WDFDRIVER Driver, IN PWDFDEVICE_INIT DeviceInit) {
+	NTSTATUS status = STATUS_SUCCESS;
+	WDF_PNPPOWER_EVENT_CALLBACKS pnpPowerCallbacks;
+	WDF_OBJECT_ATTRIBUTES attributes;
+	WDF_IO_QUEUE_CONFIG queueConfig;
+	WDF_DMA_ENABLER_CONFIG dmaConfig;
+	WDF_INTERRUPT_CONFIG intrConfig;
+	WDFDEVICE  device;
+	PDEVICE_EXTENSION devExt = NULL;
+
+	UNREFERENCED_PARAMETER(Driver);
+
+	PAGED_CODE();
+
+	// Setup direct I/O for read & write operations
+	WdfDeviceInitSetIoType(DeviceInit, WdfDeviceIoDirect);
+
+	// Zero out the PnpPowerCallbacks structure.
+	WDF_PNPPOWER_EVENT_CALLBACKS_INIT(&pnpPowerCallbacks);
+
+	// Register the PnP Callbacks.
+	pnpPowerCallbacks.EvtDevicePrepareHardware = RiffaEvtDevicePrepareHardware;
+	pnpPowerCallbacks.EvtDeviceReleaseHardware = RiffaEvtDeviceReleaseHardware;
+	WdfDeviceInitSetPnpPowerEventCallbacks(DeviceInit, &pnpPowerCallbacks);
+
+	// Initialize FDO Request context.
+	WDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attributes, REQUEST_EXTENSION);
+	WdfDeviceInitSetRequestAttributes(DeviceInit, &attributes);
+
+	// Initialize FDO Attributes.
+	WDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attributes, DEVICE_EXTENSION);
+
+	// Create the device
+	status = WdfDeviceCreate(&DeviceInit, &attributes, &device);
+	if (!NT_SUCCESS(status)) {
+		// Device Initialization failed.
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: DeviceCreate failed\n");
+		return status;
+	}
+
+	// Get the DeviceExtension and initialize it. RiffaGetDeviceContext is an
+	// inline function defined by the WDF_DECLARE_CONTEXT_TYPE_WITH_NAME macro
+	// in the private header file. This function will do the type checking and
+	// return the device context. If you pass a wrong object a wrong object handle
+	// it will return NULL and assert if run under framework verifier mode.
+	devExt = RiffaGetDeviceContext(device);
+	memset(devExt->IntrData, 0, 2 * RIFFA_MAX_NUM_CHNLS * sizeof(INTR_CHNL_DIR_DATA));
+	memset(devExt->Chnl, 0, 2 * RIFFA_MAX_NUM_CHNLS * sizeof(CHNL_DIR_STATE));
+	devExt->Device = device;
+
+	// Create a new IO Queue for IRP_MJ_DEVICE_CONTROL requests.
+	WDF_IO_QUEUE_CONFIG_INIT(&queueConfig, WdfIoQueueDispatchParallel);
+	queueConfig.EvtIoDeviceControl = RiffaEvtIoDeviceControl;
+	status = WdfIoQueueCreate(device, &queueConfig, WDF_NO_OBJECT_ATTRIBUTES,
+		&devExt->IoctlQueue);
+	if(!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: WdfIoQueueCreate failed\n");
+		return status;
+	}
+
+	// Set the Ioctl Queue forwarding for IRP_MJ_DEVICE_CONTROL requests.
+	status = WdfDeviceConfigureRequestDispatching(device, devExt->IoctlQueue,
+		WdfRequestTypeDeviceControl);
+	if(!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: DeviceConfigureRequestDispatching failed\n");
+		return status;
+	}
+
+	// Create a WDFINTERRUPT object.
+	WDF_INTERRUPT_CONFIG_INIT(&intrConfig, RiffaEvtInterruptIsr, RiffaEvtInterruptDpc);
+	intrConfig.AutomaticSerialization = TRUE;
+	status = WdfInterruptCreate(device, &intrConfig, WDF_NO_OBJECT_ATTRIBUTES,
+		&devExt->Interrupt);
+	if(!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: WdfInterruptCreate failed\n");
+		return status;
+	}
+
+	// Create a new DMA Enabler instance. Use Scatter/Gather, 64-bit Addresses,
+	// Duplex-type profile, 4-byte alignment.
+	WdfDeviceSetAlignmentRequirement(device, FILE_LONG_ALIGNMENT);
+	WDF_DMA_ENABLER_CONFIG_INIT(&dmaConfig, WdfDmaProfileScatterGather64Duplex,
+		RIFFA_MAX_TNFR_LEN);
+	status = WdfDmaEnablerCreate(device, &dmaConfig, WDF_NO_OBJECT_ATTRIBUTES,
+		&devExt->DmaEnabler);
+	if (!NT_SUCCESS (status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: WdfDmaEnablerCreate failed\n");
+		return status;
+	}
+
+	// Tell the Framework that this device will need an interface
+	// NOTE: See the note in public.h concerning this GUID value.
+	status = WdfDeviceCreateDeviceInterface(device, &GUID_RIFFA_INTERFACE, NULL);
+	if (!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: DeviceCreateDeviceInterface failed\n");
+		return status;
+	}
+
+	return status;
+}
+
+
+
+/**
+ * Free all the resources allocated in DriverEntry.
+ *	.
+ * Driver - handle to a WDF Driver object.
+ */
+VOID RiffaEvtDriverContextCleanup(IN WDFDRIVER Driver) {
+	PAGED_CODE ();
+
+	WPP_CLEANUP(WdfDriverWdmGetDriverObject(Driver));
+}
+
+
+
+/**
+ * Performs whatever initialization is needed to setup the device, setting up
+ * a DMA channel or mapping any I/O port resources.  This will only be called
+ * as a device starts or restarts, not every time the device moves into the D0
+ * state.
+ *	.
+ * Device - A handle to the WDFDEVICE
+ *
+ * Resources - The raw PnP resources associated with the device.
+ *
+ * ResourcesTranslated - The translated PnP resources associated with the device.
+ *
+ * Returns STATUS_SUCCESS if successful, another status otherwise. Failure will
+ * result in the device stack being torn down.
+ */
+NTSTATUS RiffaEvtDevicePrepareHardware(WDFDEVICE Device, WDFCMRESLIST Resources,
+	WDFCMRESLIST ResourcesTranslated) {
+	NTSTATUS status;
+	PDEVICE_EXTENSION devExt;
+	PTIMER_EXTENSION timerExt;
+	WDF_TIMER_CONFIG timerConfig;
+	WDF_OBJECT_ATTRIBUTES attributes;
+	PCM_PARTIAL_RESOURCE_DESCRIPTOR desc;
+	BOOLEAN foundBar0 = FALSE;
+	UINT32 info;
+	UINT32 i;
+
+	UNREFERENCED_PARAMETER(Resources);
+
+	PAGED_CODE();
+
+	// Get the device extension
+	devExt = RiffaGetDeviceContext(Device);
+
+	// Parse the resource list and save the resource information.
+	for (i=0; i < WdfCmResourceListGetCount(ResourcesTranslated); i++) {
+		desc = WdfCmResourceListGetDescriptor(ResourcesTranslated, i);
+		if(!desc) {
+			DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+				"riffa: WdfResourceCmGetDescriptor failed\n");
+			return STATUS_DEVICE_CONFIGURATION_ERROR;
+		}
+
+		switch (desc->Type) {
+
+			case CmResourceTypeMemory:
+				if (!foundBar0 && desc->u.Memory.Length == 0x400) {
+					// Map in the Registers Memory resource: BAR0
+					devExt->Bar0Length = desc->u.Memory.Length;
+					devExt->Bar0 = (PULONG)MmMapIoSpace(desc->u.Memory.Start,
+						desc->u.Memory.Length, MmNonCached);
+					if (!devExt->Bar0) {
+						DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+							"riffa: unable to map BAR memory %08I64X, length %d",
+							desc->u.Memory.Start.QuadPart, desc->u.Memory.Length);
+						return STATUS_INSUFFICIENT_RESOURCES;
+					}
+					foundBar0 = TRUE;
+				}
+				break;
+
+			default:
+				break;
+		}
+	}
+
+	// Make sure we found BAR0
+	if (!foundBar0) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL, "riffa: missing BAR0\n");
+		return STATUS_DEVICE_CONFIGURATION_ERROR;
+	}
+
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+		"riffa: BAR0 address: %p\n", devExt->Bar0);
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+		"riffa: BAR0 length: %u\n", devExt->Bar0Length);
+
+	// Read the device ids
+	status = RiffaReadHardwareIds(devExt);
+	if(!NT_SUCCESS(status))
+		return status;
+
+	// Read the configuration register (also resets the device)
+	info = READ_REGISTER_ULONG(devExt->Bar0 + RIFFA_INFO_REG);
+	devExt->NumChnls = (info & 0xF);
+	devExt->MaxNumScatterGatherElems = RIFFA_MIN_NUM_SG_ELEMS*((info>>19) & 0xF);
+
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+		"riffa: found FPGA with name: %s\n", devExt->Name);
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+		"riffa: vendor id: 0x%04X\n", devExt->VendorId);
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+		"riffa: device id: 0x%04X\n", devExt->DeviceId);
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+		"riffa: number of channels: %d\n", (info & 0xF));
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+		"riffa: bus interface width: %d\n", ((info>>19) & 0xF)<<5);
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+		"riffa: bus master enabled: %d\n", ((info>>4) & 0x1));
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+		"riffa: negotiated link width: %d\n", ((info>>5) & 0x3F));
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+		"riffa: negotiated link rate: %d MTs\n", ((info>>11) & 0x3)*2500);
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+		"riffa: max downstream payload: %d bytes\n", 128<<((info>>13) & 0x7));
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+		"riffa: max upstream payload: %d bytes\n", 128<<((info>>16) & 0x7));
+
+	// Check for bus master enabled
+	if (((info>>4) & 0x1) != 1) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: bus master not enabled!\n");
+		return STATUS_DEVICE_CONFIGURATION_ERROR;
+	}
+
+	// Check for valid link parameters
+	if (((info>>5) & 0x3F) == 0 || ((info>>11) & 0x3) == 0) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: bad link parameters!\n");
+		return STATUS_DEVICE_CONFIGURATION_ERROR;
+	}
+
+	// Check for valid number of channels
+	if ((info & 0xF) == 0 || (info & 0xF) > RIFFA_MAX_NUM_CHNLS) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: bad number of channels!\n");
+		return STATUS_DEVICE_CONFIGURATION_ERROR;
+	}
+
+	// Check for valid bus width
+	if (((info>>19) & 0xF) == 0 || ((info>>19) & 0xF) > RIFFA_MAX_BUS_WIDTH_PARAM) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: bad bus width!\n");
+		return STATUS_DEVICE_CONFIGURATION_ERROR;
+	}
+
+    // Allocate common buffers, DMA transactions, spin locks, timers for each channel.
+	for (i = 0; i < devExt->NumChnls; i++) {
+		// Common buffer creation, not cached.
+		status = WdfCommonBufferCreate(devExt->DmaEnabler, RIFFA_MIN_SG_BUF_SIZE*((info>>19) & 0xF),
+			WDF_NO_OBJECT_ATTRIBUTES, &devExt->Chnl[i].CommonBuffer);
+		if (!NT_SUCCESS(status)) {
+			DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+				"riffa: WdfCommonBufferCreate failed\n");
+			return status;
+		}
+		devExt->Chnl[i].CommonBufferBase =
+			WdfCommonBufferGetAlignedVirtualAddress(devExt->Chnl[i].CommonBuffer);
+		devExt->Chnl[i].CommonBufferBaseLA =
+			WdfCommonBufferGetAlignedLogicalAddress(devExt->Chnl[i].CommonBuffer);
+
+		status = WdfCommonBufferCreate(devExt->DmaEnabler, RIFFA_MIN_SG_BUF_SIZE*((info>>19) & 0x1F),
+			WDF_NO_OBJECT_ATTRIBUTES, &devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].CommonBuffer);
+		if (!NT_SUCCESS(status)) {
+			DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+				"riffa: WdfCommonBufferCreate failed\n");
+			return status;
+		}
+		devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].CommonBufferBase =
+			WdfCommonBufferGetAlignedVirtualAddress(devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].CommonBuffer);
+		devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].CommonBufferBaseLA =
+			WdfCommonBufferGetAlignedLogicalAddress(devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].CommonBuffer);
+
+		// Since we are using sequential queue and processing one request at
+		// a time, we will create transaction objects upfront and reuse them
+		// to do DMA transfer. Transactions objects are parented to the DMA
+		// enabler object by default. They will be deleted along with the DMA
+		// enabler object. No need to delete them explicitly.
+		WDF_OBJECT_ATTRIBUTES_INIT(&attributes);
+		status = WdfDmaTransactionCreate(devExt->DmaEnabler, &attributes,
+			&devExt->Chnl[i].DmaTransaction);
+		if(!NT_SUCCESS(status)) {
+			DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+				"riffa: WdfDmaTransactionCreate failed\n");
+			return status;
+		}
+
+		WDF_OBJECT_ATTRIBUTES_INIT(&attributes);
+		status = WdfDmaTransactionCreate(devExt->DmaEnabler, &attributes,
+			&devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].DmaTransaction);
+		if(!NT_SUCCESS(status)) {
+			DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+				"riffa: WdfDmaTransactionCreate failed\n");
+			return status;
+		}
+
+		// Create spinlocks for each direction. Make the parent the IOCTL queue
+		// so that the spinlocks will be automatically deleted when the queue is.
+		WDF_OBJECT_ATTRIBUTES_INIT(&attributes);
+		attributes.ParentObject = devExt->IoctlQueue;
+		status = WdfSpinLockCreate(&attributes,
+			&devExt->Chnl[i].SpinLock);
+		if (!NT_SUCCESS(status)) {
+			DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+				"riffa: WdfSpinLockCreate failed\n");
+			return status;
+		}
+
+		WDF_OBJECT_ATTRIBUTES_INIT(&attributes);
+		attributes.ParentObject = devExt->IoctlQueue;
+		status = WdfSpinLockCreate(&attributes,
+			&devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].SpinLock);
+		if (!NT_SUCCESS(status)) {
+			DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+				"riffa: WdfSpinLockCreate failed\n");
+			return status;
+		}
+
+		// Create a timer for each direction. Set the parent as the IOCTL queue
+		// so that we can get the device extension and have the timer deleted
+		// when the queue is. Also set the timer's context to have the chnl num.
+		WDF_TIMER_CONFIG_INIT(&timerConfig, RiffaEvtTimerFunc);
+		WDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attributes, TIMER_EXTENSION);
+		attributes.ParentObject = devExt->IoctlQueue;
+		status = WdfTimerCreate(&timerConfig, &attributes,
+			&devExt->Chnl[i].Timer);
+		if (!NT_SUCCESS(status)) {
+			DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+				"riffa: WdfTimerCreate failed\n");
+			return status;
+		}
+		timerExt = RiffaGetTimerContext(devExt->Chnl[i].Timer);
+		timerExt->Chnl = i;
+
+		WDF_TIMER_CONFIG_INIT(&timerConfig, RiffaEvtTimerFunc);
+		WDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attributes, TIMER_EXTENSION);
+		attributes.ParentObject = devExt->IoctlQueue;
+		status = WdfTimerCreate(&timerConfig, &attributes,
+			&devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].Timer);
+		if (!NT_SUCCESS(status)) {
+			DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+				"riffa: WdfTimerCreate failed\n");
+			return status;
+		}
+		timerExt = RiffaGetTimerContext(devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].Timer);
+		timerExt->Chnl = RIFFA_MAX_NUM_CHNLS + i;
+	}
+
+	// Create spill buffer, not cached.
+	status = WdfCommonBufferCreate(devExt->DmaEnabler, RIFFA_SPILL_BUF_SIZE,
+		WDF_NO_OBJECT_ATTRIBUTES, &devExt->SpillBuffer);
+	if (!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: WdfCommonBufferCreate failed\n");
+		return status;
+	}
+	devExt->SpillBufferBase =
+		WdfCommonBufferGetAlignedVirtualAddress(devExt->SpillBuffer);
+	devExt->SpillBufferBaseLA =
+		WdfCommonBufferGetAlignedLogicalAddress(devExt->SpillBuffer);
+
+	return STATUS_SUCCESS;
+}
+
+
+
+/**
+ * Unmap the resources that were mapped in RiffaEvtDevicePrepareHardware.
+ * This will only be called when the device stopped for resource rebalance,
+ * surprise-removed or query-removed.
+ *	.
+ * Device - A handle to the WDFDEVICE
+ *
+ * ResourcesTranslated - The translated PnP resources associated with the device.
+ *
+ * Returns STATUS_SUCCESS if successful, another status otherwise. Failure will
+ * result in the device stack being torn down.
+ */
+NTSTATUS RiffaEvtDeviceReleaseHardware(IN WDFDEVICE Device, IN WDFCMRESLIST ResourcesTranslated) {
+	PDEVICE_EXTENSION devExt;
+	NTSTATUS status = STATUS_SUCCESS;
+
+	UNREFERENCED_PARAMETER(ResourcesTranslated);
+
+	PAGED_CODE();
+
+	// Get the device extension
+	devExt = RiffaGetDeviceContext(Device);
+
+	// Unmap the I/O address space BAR0
+	if (devExt->Bar0) {
+		MmUnmapIoSpace(devExt->Bar0, devExt->Bar0Length);
+		devExt->Bar0 = NULL;
+	}
+
+	return status;
+}
+
+
+
+/**
+ * Attempts to read the hardware ids (vendor id, device id, bus num,
+ * device num, function num) and set it in the PDEVICE_EXTENSION object.
+ *	.
+ * DevExt - Pointer to the Device Extension
+ *
+ * Returns STATUS_SUCCESS if successful, another status otherwise.
+ */
+NTSTATUS RiffaReadHardwareIds(IN PDEVICE_EXTENSION DevExt) {
+	NTSTATUS status;
+	PDEVICE_OBJECT pdo;
+	UINT32 length;
+	UINT32 pciBus;
+	UINT32 pciAddr;
+	USHORT pciDev;
+	USHORT pciFxn;
+	WCHAR hwIds[2048];
+	wchar_t * id;
+
+	// Initialize the values
+	DevExt->DeviceId = 0;
+	DevExt->VendorId = 0;
+	DevExt->Name[0] = 0;
+
+	// Get the PDO from our FDO.
+	pdo = WdfDeviceWdmGetPhysicalDevice(DevExt->Device);
+
+	// Read DevicePropertyBusNumber.
+	status = IoGetDeviceProperty(pdo, DevicePropertyBusNumber, sizeof(UINT32),
+		(PVOID)&pciBus, &length);
+	if(!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: IoGetDeviceProperty failed\n");
+		return status;
+	}
+
+	// Read DevicePropertyAddress (contains device and function).
+	status = IoGetDeviceProperty(pdo, DevicePropertyAddress, sizeof(UINT32),
+		(PVOID)&pciAddr, &length);
+	if(!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: IoGetDeviceProperty failed\n");
+		return status;
+	}
+
+	// Parse the function and device values and create a name.
+	pciFxn = (USHORT)((pciAddr) & 0x0000FFFF);
+	pciDev = (USHORT)(((pciAddr)>>16) & 0x0000FFFF);
+	sprintf_s(DevExt->Name, 16, "%02x:%02x:%01x", pciBus, pciDev, pciFxn);
+
+	// Read Device HardwareID. Should be something like:
+	// PCI\VEN_10B5&DEV_515A&SUBSYS_905610B5&REV_02
+	status = IoGetDeviceProperty(pdo, DevicePropertyHardwareID, 2048,
+		(PVOID)hwIds, &length);
+	if(!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: IoGetDeviceProperty failed\n");
+		return status;
+	}
+
+	// Null terminate the string.
+	hwIds[length] = 0; // Add null-char
+
+	// Search for the device id.
+	id = wcsstr(hwIds, L"DEV_");
+	if (id == NULL) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: bad DevicePropertyHardwareID, no device id in: %S\n", hwIds);
+		return STATUS_DEVICE_CONFIGURATION_ERROR;
+	}
+
+	// Null terminate after the 4 char id and convert into an int.
+	hwIds[((int)(id - hwIds)) + 8] = 0; // Add null-char
+	swscanf_s(id + 4, L"%x", &DevExt->DeviceId);
+
+	// Search for the vendor id.
+	id = wcsstr(hwIds, L"VEN_");
+	if (id == NULL) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: bad DevicePropertyHardwareID, no vendor id in: %S\n", hwIds);
+		return STATUS_DEVICE_CONFIGURATION_ERROR;
+	}
+	hwIds[((int)(id - hwIds)) + 8] = 0; // Add null-char
+	swscanf_s(id + 4, L"%x", &DevExt->VendorId);
+
+	return STATUS_SUCCESS;
+}
+
+
+
+/******************************************************************************
+ * INTERRUPT FUNCTIONS
+ *****************************************************************************/
+
+/**
+ * Interrupt handler for this driver. Called at DIRQL level when the
+ * device or another device sharing the same interrupt line asserts
+ * the interrupt. The driver first checks the device to make sure whether
+ * this interrupt is generated by its device and if so clear the interrupt
+ * register to disable further generation of interrupts and queue a
+ * DPC to do other I/O work related to interrupt - such as reading
+ * the device memory, starting a DMA transaction, coping it to
+ * the request buffer and completing the request, etc.
+ *	.
+ * Interupt - Handle to WDFINTERRUPT Object for this device.
+ *
+ * MessageID - MSI message ID (always 0 in this configuration)
+ *
+ * Returns TRUE if this device generated the interrupt, FALSE otherwise.
+ */
+BOOLEAN RiffaEvtInterruptIsr(IN WDFINTERRUPT Interrupt, IN ULONG MessageID) {
+	PDEVICE_EXTENSION devExt;
+	UINT32 vect0 = 0;
+	UINT32 vect1 = 0;
+	BOOLEAN recog = FALSE;
+
+	UNREFERENCED_PARAMETER(MessageID);
+
+	devExt = RiffaGetDeviceContext(WdfInterruptGetDevice(Interrupt));
+
+	// Read the interrupt register
+	vect0 = READ_REGISTER_ULONG(devExt->Bar0 + RIFFA_IRQ_0_REG);
+	if (devExt->NumChnls > 6)
+		vect1 = READ_REGISTER_ULONG(devExt->Bar0 + RIFFA_IRQ_1_REG);
+
+	// Process the interrupt vector(s)
+	recog = RiffaProcessInterrupt(devExt, 0, vect0);
+	if (devExt->NumChnls > 6)
+		recog = (recog | RiffaProcessInterrupt(devExt, 6, vect1));
+
+	// Queue a callback for the DPC if needed.
+	if (recog)
+		WdfInterruptQueueDpcForIsr(Interrupt);
+
+	return recog;
+}
+
+
+
+/**
+ * Processes the interrupt vector read from the device during the interrupt
+ * service routine. The vectors are organized from right to left (LSB to MSB) as:
+ * [ 0] TX_TXN			 for channel 0 in VECT_0, channel 6 in VECT_1
+ * [ 1] TX_SG_BUF_RECVD	 for channel 0 in VECT_0, channel 6 in VECT_1
+ * [ 2] TX_TXN_DONE		 for channel 0 in VECT_0, channel 6 in VECT_1
+ * [ 3] RX_SG_BUF_RECVD	 for channel 0 in VECT_0, channel 6 in VECT_1
+ * [ 4] RX_TXN_DONE		 for channel 0 in VECT_0, channel 6 in VECT_1
+ * ...
+ * [25] TX_TXN			 for channel 5 in VECT_0, channel 11 in VECT_1
+ * [26] TX_SG_BUF_RECVD	 for channel 5 in VECT_0, channel 11 in VECT_1
+ * [27] TX_TXN_DONE		 for channel 5 in VECT_0, channel 11 in VECT_1
+ * [28] RX_SG_BUF_RECVD	 for channel 5 in VECT_0, channel 11 in VECT_1
+ * [29] RX_TXN_DONE		 for channel 5 in VECT_0, channel 11 in VECT_1
+ * Positions 30 - 31 in both VECT_0 and VECT_1 are zero.
+ *	.
+ * DevExt - Pointer to the Device Extension
+ *
+ * Offset - Channel offset
+ *
+ * Vect - Interrupt vector
+ *
+ * Returns TRUE if a DPC should be queued to do more work, FALSE otherwise.
+ */
+BOOLEAN RiffaProcessInterrupt(IN PDEVICE_EXTENSION DevExt, IN UINT32 Offset,
+	IN UINT32 Vect) {
+	BOOLEAN queueDpc = FALSE;
+	UINT32 offlast;
+	UINT32 len;
+	int i;
+	int chnl;
+
+	if (Vect & 0xC0000000) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, received invalid interrupt:0x%08x\n", DevExt->Name, Vect);
+		return FALSE;
+	}
+
+	for (i = 0; i < 6 && (i+Offset) < DevExt->NumChnls; i++) {
+		chnl = i + Offset;
+
+		// New TX (PC receive) transaction.
+		if (Vect & (1<<((5*i)+0))) {
+			queueDpc = TRUE;
+			// Read the offset/last and length
+			offlast = READ_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(chnl, RIFFA_TX_OFFLAST_REG));
+			len = READ_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(chnl, RIFFA_TX_LEN_REG));
+			DevExt->IntrData[RIFFA_MAX_NUM_CHNLS + chnl].OffLast = offlast;
+			DevExt->IntrData[RIFFA_MAX_NUM_CHNLS + chnl].Length = len;
+			DevExt->IntrData[RIFFA_MAX_NUM_CHNLS + chnl].NewTxn = TRUE;
+		}
+
+		// TX (PC receive) scatter gather buffer is read.
+		if (Vect & (1<<((5*i)+1))) {
+			queueDpc = TRUE;
+			DevExt->IntrData[RIFFA_MAX_NUM_CHNLS + chnl].SgRead = TRUE;
+		}
+
+		// TX (PC receive) transaction done.
+		if (Vect & (1<<((5*i)+2))) {
+			queueDpc = TRUE;
+			DevExt->IntrData[RIFFA_MAX_NUM_CHNLS + chnl].Done = TRUE;
+		}
+
+		// RX (PC send) scatter gather buffer is read.
+		if (Vect & (1<<((5*i)+3))) {
+			queueDpc = TRUE;
+			DevExt->IntrData[chnl].SgRead = TRUE;
+		}
+
+		// RX (PC send) transaction done.
+		if (Vect & (1<<((5*i)+4))) {
+			queueDpc = TRUE;
+			DevExt->IntrData[chnl].Done = TRUE;
+		}
+	}
+
+	return queueDpc;
+}
+
+
+
+/**
+ * DPC callback for ISR. Please note that on a multiprocessor system,
+ * you could have more than one DPCs running simulataneously on
+ * multiple processors. So if you are accesing any global resources
+ * make sure to synchrnonize the accesses with a spinlock.
+ *	.
+ * Interupt - Handle to WDFINTERRUPT Object for this device.
+ *
+ * Device - WDFDEVICE object passed to InterruptCreate
+ */
+VOID RiffaEvtInterruptDpc(IN WDFINTERRUPT Interrupt, IN WDFDEVICE Device) {
+	NTSTATUS status;
+	BOOLEAN txnComplete;
+	BOOLEAN cont;
+	PDEVICE_EXTENSION devExt;
+	INTR_CHNL_DIR_DATA intrData[2 * RIFFA_MAX_NUM_CHNLS];
+	UINT32 chnl;
+	UINT32 tnfr;
+	UINT64 length;
+	LONG doneReqd;
+
+	UNREFERENCED_PARAMETER(Device);
+
+	devExt = RiffaGetDeviceContext(WdfInterruptGetDevice(Interrupt));
+
+	// Acquire this device's InterruptSpinLock.
+	WdfInterruptAcquireLock(Interrupt);
+
+	// Copy over the values and zero them out.
+	memcpy(&intrData, devExt->IntrData,
+		2 * RIFFA_MAX_NUM_CHNLS * sizeof(INTR_CHNL_DIR_DATA));
+	memset(devExt->IntrData, 0,
+		2 * RIFFA_MAX_NUM_CHNLS * sizeof(INTR_CHNL_DIR_DATA));
+
+	// Release our interrupt spinlock
+	WdfInterruptReleaseLock(Interrupt);
+
+	// Update state for each channel
+	for (chnl = 0; chnl < devExt->NumChnls; chnl++) {
+		// Send more scatter gather elements.
+		if (intrData[RIFFA_MAX_NUM_CHNLS + chnl].SgRead == TRUE) {
+			KdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+				"riffa: fpga:%s chnl:%d, recv sg buf read\n", devExt->Name, chnl));
+			RiffaProgramScatterGather(devExt, RIFFA_MAX_NUM_CHNLS + chnl);
+		}
+
+		// Finished with upstream transfer.
+		if (intrData[RIFFA_MAX_NUM_CHNLS + chnl].Done == TRUE) {
+			// Acquire the channel lock, check if request is null, release.
+			WdfSpinLockAcquire(devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].SpinLock);
+			cont = (devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].Request != NULL);
+			WdfSpinLockRelease(devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].SpinLock);
+			if (cont) {
+				// Check if we've requested a done (in the event of a split transaction)
+				doneReqd = InterlockedExchange(&devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].ReqdDone, 0);
+				// Indicate this DMA operation has completed. This might result in
+				// another transfer if there is still data to be transfered in the request.
+				txnComplete = WdfDmaTransactionDmaCompleted(
+					devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].DmaTransaction, &status);
+				if (txnComplete) {
+					// Read the actual transfer length
+					tnfr = READ_REGISTER_ULONG(devExt->Bar0 + CHNL_REG(chnl, RIFFA_TX_TNFR_LEN_REG));
+					KdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+						"riffa: fpga:%s chnl:%d, recv txn done\n", devExt->Name, chnl));
+					RiffaTransactionComplete(devExt, RIFFA_MAX_NUM_CHNLS + chnl, tnfr, status);
+				}
+				else {
+					if (doneReqd == 0) {
+						// Not complete and not expecting a done signal. Must be an error.
+						// End the transaction early. Read the actual transfer length
+						tnfr = READ_REGISTER_ULONG(devExt->Bar0 + CHNL_REG(chnl, RIFFA_TX_TNFR_LEN_REG));
+						KdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+							"riffa: fpga:%s chnl:%d, recv txn done\n", devExt->Name, chnl));
+						RiffaTransactionComplete(devExt, RIFFA_MAX_NUM_CHNLS + chnl, tnfr, STATUS_TRANSACTION_ABORTED);
+					}
+					else {
+						KdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+							"riffa: fpga:%s chnl:%d, recv txn split, registers remapped\n", devExt->Name, chnl));
+					}
+				}
+			}
+		}
+
+		// New upstream transfer.
+		if (intrData[RIFFA_MAX_NUM_CHNLS + chnl].NewTxn == TRUE) {
+			// If the user has already called the receive function, start the
+			// transaction. If not, set the transaction data and the "ready"
+			// bit so that when the user calls the receive function, the
+			// transaction can start.
+			devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].Length =
+				(((UINT64)intrData[RIFFA_MAX_NUM_CHNLS + chnl].Length)<<2);
+			devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].Offset =
+				(((UINT64)(intrData[RIFFA_MAX_NUM_CHNLS + chnl].OffLast>>1))<<2);
+			devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].Last =
+				(intrData[RIFFA_MAX_NUM_CHNLS + chnl].OffLast & 0x1);
+			KdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+				"riffa: fpga:%s chnl:%d, new recv txn (len:%u off:%u last:%d)\n",
+				devExt->Name, chnl, intrData[RIFFA_MAX_NUM_CHNLS + chnl].Length,
+				intrData[RIFFA_MAX_NUM_CHNLS + chnl].OffLast>>1,
+				intrData[RIFFA_MAX_NUM_CHNLS + chnl].OffLast & 0x1));
+			if (InterlockedExchange(&devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].Ready, 2) == 1) {
+				// Clear the "ready" bit and start the transaction
+				InterlockedExchange(&devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].Ready, 0);
+				RiffaStartRecvTransaction(devExt, RIFFA_MAX_NUM_CHNLS + chnl);
+			}
+		}
+
+		// Send more scatter gather elements.
+		if (intrData[chnl].SgRead == TRUE) {
+			KdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+				"riffa: fpga:%s chnl:%d, send sg buf read\n", devExt->Name, chnl));
+			RiffaProgramScatterGather(devExt, chnl);
+		}
+
+		// Finished with downstream transfer.
+		if (intrData[chnl].Done == TRUE) {
+			// Acquire the channel lock, check if request is null, release.
+			WdfSpinLockAcquire(devExt->Chnl[chnl].SpinLock);
+			cont = (devExt->Chnl[chnl].Request != NULL);
+			WdfSpinLockRelease(devExt->Chnl[chnl].SpinLock);
+			if (cont) {
+				// Check if we've requested a done (in the event of a split transaction)
+				doneReqd = InterlockedExchange(&devExt->Chnl[chnl].ReqdDone, 0);
+				// Indicate this DMA operation has completed. This may result in
+				// another transfer if there is still data to be transfered in the request.
+				txnComplete = WdfDmaTransactionDmaCompleted(
+					devExt->Chnl[chnl].DmaTransaction, &status);
+				if (txnComplete) {
+					// Read the actual transfer length
+					tnfr = READ_REGISTER_ULONG(devExt->Bar0 + CHNL_REG(chnl, RIFFA_RX_TNFR_LEN_REG));
+					KdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+						"riffa: fpga:%s chnl:%d, send txn done\n", devExt->Name, chnl));
+					RiffaTransactionComplete(devExt, chnl, tnfr, status);
+				}
+				else {
+					if (doneReqd == 0) {
+						// Not complete and not expecting a done signal. Must be an error.
+						// End the transaction early. Read the actual transfer length
+						tnfr = READ_REGISTER_ULONG(devExt->Bar0 + CHNL_REG(chnl, RIFFA_RX_TNFR_LEN_REG));
+						KdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+							"riffa: fpga:%s chnl:%d, send txn done\n", devExt->Name, chnl));
+						RiffaTransactionComplete(devExt, chnl, tnfr, STATUS_TRANSACTION_ABORTED);
+					}
+					else {
+						KdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+							"riffa: fpga:%s chnl:%d, send txn split, registers remapped\n", devExt->Name, chnl));
+					}
+				}
+			}
+		}
+	}
+}
+
+
+
+/******************************************************************************
+ * IOCTL FUNCTIONS
+ *****************************************************************************/
+
+/**
+ * This event is called when the framework receives IRP_MJ_DEVICE_CONTROL
+ * requests from the system.
+ *	.
+ * Queue - Handle to the framework queue object that is associated with the
+ * I/O request.
+ *
+ * Request - Handle to a framework request object.
+ *
+ * OutputBufferLength - Length of the request's output buffer,
+ * if an output buffer is available.
+ *
+ * InputBufferLength - Length of the request's input buffer,
+ * if an input buffer is available.
+ *
+ * IoControlCode - the driver-defined or system-defined I/O control code
+ * (IOCTL) that is associated with the request.
+ */
+VOID RiffaEvtIoDeviceControl(IN WDFQUEUE Queue, IN WDFREQUEST Request,
+	IN size_t OutputBufferLength, IN size_t InputBufferLength,
+	IN ULONG IoControlCode) {
+    PDEVICE_EXTENSION devExt;
+
+    devExt = RiffaGetDeviceContext(WdfIoQueueGetDevice(Queue));
+
+    // Determine which I/O control code was specified.
+    switch (IoControlCode) {
+
+    case IOCTL_RIFFA_SEND: // (METHOD_OUT_DIRECT)
+    	RiffaIoctlSend(devExt, Request, OutputBufferLength, InputBufferLength);
+		break;
+
+    case IOCTL_RIFFA_RECV: // (METHOD_OUT_DIRECT)
+    	RiffaIoctlRecv(devExt, Request, OutputBufferLength, InputBufferLength);
+		break;
+
+    case IOCTL_RIFFA_LIST: // (METHOD_OUT_DIRECT)
+    	RiffaIoctlList(devExt, Request, OutputBufferLength, InputBufferLength);
+		break;
+
+    case IOCTL_RIFFA_RESET: // (METHOD_OUT_DIRECT)
+    	RiffaIoctlReset(devExt, Request);
+		break;
+
+    default:
+        // The specified I/O control code is unrecognized by this driver.
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, invalid ioctl request type\n", devExt->Name);
+        WdfRequestCompleteWithInformation(Request, STATUS_INVALID_DEVICE_REQUEST, 0);
+        break;
+    }
+}
+
+
+/**
+ * Handles IRP_MJ_DEVICE_CONTROL requests for IOCTL_RIFFA_SEND.
+ *	.
+ * DevExt - Handle to the device extension object.
+ *
+ * Request - Handle to a framework request object.
+ *
+ * OutputBufferLength - Length of the request's output buffer,
+ * if an output buffer is available.
+ *
+ * InputBufferLength - Length of the request's input buffer,
+ * if an input buffer is available.
+ */
+VOID RiffaIoctlSend(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,
+	IN size_t OutputBufferLength, IN size_t InputBufferLength) {
+    NTSTATUS status = STATUS_SUCCESS;
+    PREQUEST_EXTENSION reqExt;
+    PRIFFA_FPGA_CHNL_IO io;
+	UINT64 length;
+	PCHAR buf = NULL;
+	LONG inUse;
+	size_t bufSize;
+
+	// Input should be non-zero
+	if(!InputBufferLength) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl send zero length input buffer\n", DevExt->Name);
+		WdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);
+		return;
+	}
+
+	// Get the input buffer
+	status = WdfRequestRetrieveInputBuffer(Request, 0, &buf, &bufSize);
+	if (!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl send WdfRequestRetrieveInputBuffer failed\n",
+			DevExt->Name);
+		WdfRequestCompleteWithInformation(Request, status, 0);
+		return;
+	}
+	if (bufSize < sizeof(RIFFA_FPGA_CHNL_IO)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl send input buffer too small to contain RIFFA_FPGA_CHNL_IO\n",
+			DevExt->Name);
+		WdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);
+		return;
+	}
+	io = (PRIFFA_FPGA_CHNL_IO)buf;
+
+	// Validate the length, last, chnl
+	length = (io->Length < (OutputBufferLength>>2) ? io->Length : (OutputBufferLength>>2));
+	if (io->Last > 1) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl send invalid last: %d\n", DevExt->Name, io->Last);
+		WdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);
+		return;
+	}
+	if (io->Chnl >= DevExt->NumChnls) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl send invalid channel: %d, device only has %d channel(s)\n",
+			DevExt->Name, io->Chnl, DevExt->NumChnls);
+		WdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);
+		return;
+	}
+
+	// Start a send transaction.
+	if (length) {
+		// Start a DMA transaction for sending.
+		DevExt->Chnl[io->Chnl].Timeout = io->Timeout;
+		DevExt->Chnl[io->Chnl].Length = (length<<2);
+		DevExt->Chnl[io->Chnl].SpillAfter = (length<<2);
+		DevExt->Chnl[io->Chnl].Offset = (io->Offset<<2);
+		DevExt->Chnl[io->Chnl].Last = io->Last;
+		DevExt->Chnl[io->Chnl].Provided = 0;
+		DevExt->Chnl[io->Chnl].ProvidedPrev = 0;
+		DevExt->Chnl[io->Chnl].Confirmed = 0;
+		DevExt->Chnl[io->Chnl].ConfirmedPrev = 0;
+		DevExt->Chnl[io->Chnl].ActiveCount = 0;
+		DevExt->Chnl[io->Chnl].Cancel = 0;
+		DevExt->Chnl[io->Chnl].Request = Request;
+		InterlockedExchange(&DevExt->Chnl[io->Chnl].ReqdDone, 0);
+		status = RiffaStartDmaTransaction(DevExt, io->Chnl, (length<<2),
+			0, WdfDmaDirectionWriteToDevice);
+		if (!NT_SUCCESS(status)) {
+			DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+				"riffa: fpga:%s, unable to start DMA transaction on channel: %d\n",
+				DevExt->Name, io->Chnl);
+			WdfRequestCompleteWithInformation(Request, status, 0);
+			return;
+		}
+		else {
+			// Mark the WDFREQUEST as cancellable.
+			//status = WdfRequestMarkCancelableEx(Request, RiffaEvtRequestCancel);
+			//if (!NT_SUCCESS(status)) {
+			//	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			//		"riffa: fpga:%s, ioctl send WdfRequestMarkCancelableEx failed\n",
+			//		DevExt->Name);
+			//	WdfRequestCompleteWithInformation(Request, status, 0);
+			//}
+			//else {
+				// Set the channel number in the request context for RiffaEvtRequestCancel.
+				reqExt = RiffaGetRequestContext(Request);
+				reqExt->Chnl = io->Chnl;
+			//}
+		}
+	}
+	else if (io->Last) {
+		// Program the device for zero length send (device RX) and complete
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl send zero length with last set\n", DevExt->Name);
+		RiffaProgramSend(DevExt, io->Chnl, (UINT32)length, io->Offset, io->Last);
+		WdfRequestCompleteWithInformation(Request, STATUS_SUCCESS, 0);
+	}
+	else {
+		// Invalid request, results in no send
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl send invalid, no length or last\n", DevExt->Name);
+		WdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);
+	}
+}
+
+
+
+/**
+ * Handles IRP_MJ_DEVICE_CONTROL requests for IOCTL_RIFFA_RECV.
+ *	.
+ * DevExt - Handle to the device extension object.
+ *
+ * Request - Handle to a framework request object.
+ *
+ * OutputBufferLength - Length of the request's output buffer,
+ * if an output buffer is available.
+ *
+ * InputBufferLength - Length of the request's input buffer,
+ * if an input buffer is available.
+ */
+VOID RiffaIoctlRecv(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,
+	IN size_t OutputBufferLength, IN size_t InputBufferLength) {
+    NTSTATUS status = STATUS_SUCCESS;
+	PREQUEST_EXTENSION reqExt;
+    PRIFFA_FPGA_CHNL_IO io;
+	UINT64 length;
+	PCHAR buf = NULL;
+	size_t bufSize;
+
+	// Input should be non-zero
+	if(!InputBufferLength) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl recv zero length input buffer\n", DevExt->Name);
+		WdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);
+		return;
+	}
+
+	// Get the input buffer
+	status = WdfRequestRetrieveInputBuffer(Request, 0, &buf, &bufSize);
+	if (!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl recv WdfRequestRetrieveInputBuffer failed\n",
+			DevExt->Name);
+		WdfRequestCompleteWithInformation(Request, status, 0);
+		return;
+	}
+	if (bufSize < sizeof(RIFFA_FPGA_CHNL_IO)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl recv input buffer too small to contain RIFFA_FPGA_CHNL_IO\n",
+			DevExt->Name);
+		WdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);
+		return;
+	}
+	io = (PRIFFA_FPGA_CHNL_IO)buf;
+
+	// Validate the length, chnl
+	length = (io->Length < (OutputBufferLength>>2) ? io->Length : (OutputBufferLength>>2));
+	if (io->Chnl >= DevExt->NumChnls) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl recv invalid channel: %d, device only has %d channel(s)\n",
+			DevExt->Name, io->Chnl, DevExt->NumChnls);
+		WdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);
+		return;
+	}
+
+	// Start a receive transaction. If an interrupt with the transaction
+	// info has already been received, start the transaction. If not, set
+	// this transaction request and the "ready" bit so that when the
+	// interrupt is received the transaction can start.
+	DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Timeout = io->Timeout;
+	DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Capacity = (length<<2);
+	DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Provided = 0;
+	DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].ProvidedPrev = 0;
+	DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Confirmed = 0;
+	DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].ConfirmedPrev = 0;
+	DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].ActiveCount = 0;
+	DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Cancel = 0;
+	DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Request = Request;
+	InterlockedExchange(&DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].ReqdDone, 0);
+	if (InterlockedExchange(&DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Ready, 1) == 2) {
+		// Clear the "ready" bit and start the transaction
+		InterlockedExchange(&DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Ready, 0);
+
+		// Start a recv transaction.
+		if (DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Length) {
+			// Calculate room in the user space buffer and what needs to be spilled
+			if (DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Capacity >
+					DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Offset) {
+				// Some (possibly all) of the data can fit in the user buffer.
+				DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].SpillAfter =
+					DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Capacity -
+					DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Offset;
+				length = (DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Capacity <
+					DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Length ?
+					DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Capacity :
+					DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Length);
+				status = RiffaStartDmaTransaction(DevExt, RIFFA_MAX_NUM_CHNLS + io->Chnl,
+					length + DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Offset,
+					DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Offset,
+					WdfDmaDirectionReadFromDevice);
+				if (!NT_SUCCESS(status)) {
+					DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+						"riffa: fpga:%s, unable to start DMA transaction on channel: %d\n",
+						DevExt->Name, io->Chnl);
+					WdfRequestCompleteWithInformation(Request, status, 0);
+					return;
+				}
+			}
+			else {
+				// No room in user buffer, spill everything
+				DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].SpillAfter = 0;
+				RiffaProgramScatterGather(DevExt, RIFFA_MAX_NUM_CHNLS + io->Chnl);
+			}
+		}
+		else if (DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Last) {
+			// Recognize zero length receive and complete
+			DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+				"riffa: fpga:%s, ioctl recv zero length with last set\n", DevExt->Name);
+			WdfRequestCompleteWithInformation(Request, STATUS_SUCCESS, 0);
+			return;
+		}
+		else {
+			// Invalid request, should never happen
+			DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+				"riffa: fpga:%s, ioctl recv invalid, no length or last\n", DevExt->Name);
+			WdfRequestCompleteWithInformation(Request, STATUS_CANCELLED, 0);
+			return;
+		}
+	}
+	else {
+		// Start the timer (if necessary)
+		if (DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Timeout > 0)
+			WdfTimerStart(DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Timer,
+				WDF_REL_TIMEOUT_IN_MS(DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Timeout));
+	}
+
+	// Mark the WDFREQUEST as cancellable.
+	//status = WdfRequestMarkCancelableEx(Request, RiffaEvtRequestCancel);
+	//if (!NT_SUCCESS(status)) {
+	//	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+	//		"riffa: fpga:%s, ioctl send WdfRequestMarkCancelableEx failed\n", DevExt->Name);
+	//	WdfRequestCompleteWithInformation(Request, status, 0);
+	//}
+	//else {
+		// Set the channel number in the request context for RiffaEvtRequestCancel.
+		reqExt = RiffaGetRequestContext(Request);
+		reqExt->Chnl = RIFFA_MAX_NUM_CHNLS + io->Chnl;
+	//}
+}
+
+
+
+/**
+ * Handles IRP_MJ_DEVICE_CONTROL requests for IOCTL_RIFFA_LIST.
+ *	.
+ * DevExt - Handle to the device extension object.
+ *
+ * Request - Handle to a framework request object.
+ *
+ * OutputBufferLength - Length of the request's output buffer,
+ * if an output buffer is available.
+ *
+ * InputBufferLength - Length of the request's input buffer,
+ * if an input buffer is available.
+ */
+VOID RiffaIoctlList(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,
+	IN size_t OutputBufferLength, IN size_t InputBufferLength) {
+    NTSTATUS status = STATUS_SUCCESS;
+    PRIFFA_FPGA_INFO info;
+	PCHAR buf = NULL;
+	size_t bufSize;
+	UINT32 i;
+
+	// Input should be non-zero
+	if(!InputBufferLength) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl list zero length input buffer\n", DevExt->Name);
+		WdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);
+		return;
+	}
+
+	// Get the input buffer
+	status = WdfRequestRetrieveInputBuffer(Request, 0, &buf, &bufSize);
+	if (!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl list WdfRequestRetrieveInputBuffer failed\n",
+			DevExt->Name);
+		WdfRequestCompleteWithInformation(Request, status, 0);
+		return;
+	}
+	if (bufSize < sizeof(UINT32)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl list input buffer too small to contain fpga id\n",
+			DevExt->Name);
+		WdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);
+		return;
+	}
+	i = *((UINT32 *)buf);
+
+	// Validate the index value
+	if (i >= RIFFA_MAX_NUM_FPGAS) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl list fpga id invalid\n", DevExt->Name);
+		WdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);
+		return;
+	}
+
+	// Output should be non-zero
+	if(!OutputBufferLength) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl list zero length output buffer\n", DevExt->Name);
+		WdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);
+		return;
+	}
+
+	// Get the output buffer
+	status = WdfRequestRetrieveOutputBuffer(Request, 0, &buf, &bufSize);
+	if (!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl list WdfRequestRetrieveOutputBuffer failed\n",
+			DevExt->Name);
+		WdfRequestCompleteWithInformation(Request, status, 0);
+		return;
+	}
+	if (bufSize < sizeof(RIFFA_FPGA_INFO)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s, ioctl list input buffer too small to contain RIFFA_FPGA_INFO\n",
+			DevExt->Name);
+		WdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);
+		return;
+	}
+	info = (PRIFFA_FPGA_INFO)buf;
+
+	// Fill in the information.
+	info->id[i] = i;
+	info->num_chnls[i] = DevExt->NumChnls;
+	strcpy_s(info->name[i], 16, DevExt->Name);
+	info->vendor_id[i] = DevExt->VendorId;
+	info->device_id[i] = DevExt->DeviceId;
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+		"riffa: fpga:%s, ioctl list completed successfully\n", DevExt->Name);
+	WdfRequestCompleteWithInformation(Request, status, 0);
+}
+
+
+
+/**
+ * Handles IRP_MJ_DEVICE_CONTROL requests for IOCTL_RIFFA_RESET.
+ *	.
+ * DevExt - Handle to the device extension object.
+ *
+ * Request - Handle to a framework request object.
+ *
+ * OutputBufferLength - Length of the request's output buffer,
+ * if an output buffer is available.
+ *
+ * InputBufferLength - Length of the request's input buffer,
+ * if an input buffer is available.
+ */
+VOID RiffaIoctlReset(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request) {
+	UINT32 i;
+
+	// Reset the device by reading the info/status register
+	READ_REGISTER_ULONG(DevExt->Bar0 + RIFFA_INFO_REG);
+
+	// Reset all the channels
+	for (i = 0; i < DevExt->NumChnls; i++) {
+		InterlockedExchange(&DevExt->Chnl[i].Ready, 0);
+		InterlockedExchange(&DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].Ready, 0);
+		InterlockedExchange(&DevExt->Chnl[i].ReqdDone, 0);
+		InterlockedExchange(&DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].ReqdDone, 0);
+		WdfTimerStop(DevExt->Chnl[i].Timer, FALSE);
+		WdfTimerStop(DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].Timer, FALSE);
+		DevExt->Chnl[i].ActiveCount = 0;
+		DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].ActiveCount = 0;
+		DevExt->Chnl[i].Cancel = 0;
+		DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].Cancel = 0;
+		WdfDmaTransactionRelease(DevExt->Chnl[i].DmaTransaction);
+		WdfDmaTransactionRelease(DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].DmaTransaction);
+		RiffaCompleteRequest(DevExt, i, STATUS_CANCELLED);
+		RiffaCompleteRequest(DevExt, RIFFA_MAX_NUM_CHNLS + i, STATUS_CANCELLED);
+	}
+
+	// Reset the interrupt data
+	memset(DevExt->IntrData, 0, 2 * RIFFA_MAX_NUM_CHNLS * sizeof(INTR_CHNL_DIR_DATA));
+
+	// Finish this request
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+		"riffa: fpga:%s, ioctl reset completed successfully\n", DevExt->Name);
+	WdfRequestCompleteWithInformation(Request, STATUS_SUCCESS, 0);
+}
+
+
+
+/******************************************************************************
+ * DMA ENTRY, EXIT, TIMER FUNCTIONS
+ *****************************************************************************/
+
+/**
+ * Called at the entry point of functions after the DMA has started. If the
+ * WDFREQUEST is still valid, increments the active count and returns TRUE. IF
+ * the WDFREQUEST is not valid (i.e. is NULL'd out), then the request has been
+ * cancelled (by timeout timer or by user process termination), and FALSE is
+ * returned (active count is not incremented).
+ *
+ * DevExt - Pointer to the Device Extension
+ *
+ * Chnl - Channel number on which the DMA is taking place
+ */
+BOOLEAN RiffaThreadEnter(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl) {
+	BOOLEAN cont;
+
+	// Acquire the channel lock, check if request is null, increment, release.
+	WdfSpinLockAcquire(DevExt->Chnl[Chnl].SpinLock);
+	cont = (DevExt->Chnl[Chnl].Request != NULL);
+	if (cont)
+		DevExt->Chnl[Chnl].ActiveCount++;
+	WdfSpinLockRelease(DevExt->Chnl[Chnl].SpinLock);
+
+	return cont;
+}
+
+
+
+/**
+ * Called at the exit of functions where RiffaThreadEnter was called, after the
+ * DMA has started. Decrements the active count. If this is the last thread, it
+ * checks to see if a cancel request was set. If so, cancels the request (if
+ * not already completed) and returns TRUE. Otherwise, returns FALSE.
+ *
+ * DevExt - Pointer to the Device Extension
+ *
+ * Chnl - Channel number on which the DMA is taking place
+ *
+ * IsSend - TRUE if the thread is operating on a send DMA, FALSE otherwise
+ */
+BOOLEAN RiffaThreadExit(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl) {
+	BOOLEAN completed = FALSE;
+
+	// Acquire the channel lock, decrement, check for last exiting thread and a
+	// cancel request, cancel if necessary, release.
+	WdfSpinLockAcquire(DevExt->Chnl[Chnl].SpinLock);
+	DevExt->Chnl[Chnl].ActiveCount--;
+	if (DevExt->Chnl[Chnl].ActiveCount == 0 && DevExt->Chnl[Chnl].Cancel == 1) {
+		completed = TRUE;
+		RiffaCompleteRequest(DevExt, Chnl, STATUS_CANCELLED);
+	}
+	WdfSpinLockRelease(DevExt->Chnl[Chnl].SpinLock);
+	return completed;
+}
+
+
+
+/**
+ * Called when the WDFREQUEST object for the specified channel should be
+ * completed with the specified status. The WDFREQUEST has been marked
+ * cancelable so it must first be unmarked cancelable. After completion, the
+ * pointer to the WDFREQUEST is NULL'd out to indicate that the WDFREQUEST is
+ * no longer valid.
+ *
+ * DevExt - Pointer to the Device Extension
+ *
+ * Chnl - Channel number on which the DMA is taking place
+ *
+ * Status - NTSTATUS to set for completion
+ */
+VOID RiffaCompleteRequest(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,
+	IN NTSTATUS Status) {
+	NTSTATUS status;
+	WDFREQUEST request;
+
+	if ((request = DevExt->Chnl[Chnl].Request) != NULL) {
+		DevExt->Chnl[Chnl].Request = NULL;
+		// Try to complete the request
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s chnl:%d, completing request\n",
+			DevExt->Name, (Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS));
+		//status = WdfRequestUnmarkCancelable(request);
+		//if (status != STATUS_CANCELLED) {
+			// Complete the request (nobody has done it yet)
+			WdfRequestCompleteWithInformation(request, Status,
+				(ULONG_PTR)(DevExt->Chnl[Chnl].ConfirmedPrev +
+				DevExt->Chnl[Chnl].Confirmed)>>2);
+		//}
+		//else {
+		//	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+		//		"riffa: fpga:%s chnl:%d, request already cancelled\n",
+		//		DevExt->Name, (Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS));
+		//}
+	}
+	else {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s chnl:%d, request already nulled out\n",
+			DevExt->Name, (Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS));
+	}
+}
+
+
+
+/**
+ * EvtRequestCancel handler for WDFREQUEST objects for IOCTL sends/receives.
+ * Called if the IO Manager or calling application needs to cancel the send.
+ * In practice this should only happen when the user application hangs and the
+ * user CTRL+C signals or Task Ends the application.
+ *
+ * Request - WDFREQUEST object from the IOCTL queue, representing the send
+ */
+VOID RiffaEvtRequestCancel(IN WDFREQUEST Request) {
+	PDEVICE_EXTENSION devExt;
+	PREQUEST_EXTENSION reqExt;
+	UINT32 chnl;
+	BOOLEAN canCancel;
+
+    devExt = RiffaGetDeviceContext(WdfIoQueueGetDevice(WdfRequestGetIoQueue(Request)));
+    reqExt = RiffaGetRequestContext(Request);
+
+	KdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+		"riffa: fpga:%s chnl:%d, cancel requested\n", devExt->Name,
+		(reqExt->Chnl >= RIFFA_MAX_NUM_CHNLS ? reqExt->Chnl - RIFFA_MAX_NUM_CHNLS : reqExt->Chnl)));
+
+	// Acquire the channel lock
+	WdfSpinLockAcquire(devExt->Chnl[reqExt->Chnl].SpinLock);
+
+	// See if we can cancel right now.
+	canCancel = (devExt->Chnl[reqExt->Chnl].ActiveCount == 0);
+	if (canCancel) {
+		// NULL out the request so that no other threads use it
+		devExt->Chnl[reqExt->Chnl].Request = NULL;
+	}
+	else {
+		// Set the cancel flag so that the last active thread cancels for us.
+		devExt->Chnl[reqExt->Chnl].Cancel = 1;
+	}
+
+	// Release the channel lock
+	WdfSpinLockRelease(devExt->Chnl[reqExt->Chnl].SpinLock);
+
+	// Cancel the request
+	if (canCancel) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s chnl:%d, request cancelled\n", devExt->Name,
+			(reqExt->Chnl >= RIFFA_MAX_NUM_CHNLS ? reqExt->Chnl - RIFFA_MAX_NUM_CHNLS : reqExt->Chnl));
+		InterlockedExchange(&devExt->Chnl[reqExt->Chnl].Ready, 0);
+		devExt->Chnl[reqExt->Chnl].ActiveCount = 0;
+		devExt->Chnl[reqExt->Chnl].Cancel = 0;
+		WdfDmaTransactionRelease(devExt->Chnl[reqExt->Chnl].DmaTransaction);
+		WdfTimerStop(devExt->Chnl[reqExt->Chnl].Timer, FALSE);
+		WdfRequestCompleteWithInformation(Request, STATUS_CANCELLED,
+			(ULONG_PTR)(devExt->Chnl[reqExt->Chnl].ConfirmedPrev +
+			devExt->Chnl[reqExt->Chnl].Confirmed)>>2);
+	}
+}
+
+
+
+/**
+ * Called when the WDFTIMER expires. Used to handle timeouts from IOCTL calls.
+ *
+ * Timer - WDFTIMER that expired
+ */
+VOID RiffaEvtTimerFunc(IN WDFTIMER Timer) {
+	PDEVICE_EXTENSION devExt;
+	PTIMER_EXTENSION timerExt;
+	WDFREQUEST request;
+	NTSTATUS status;
+	BOOLEAN canCancel;
+
+    timerExt = RiffaGetTimerContext(Timer);
+    devExt = RiffaGetDeviceContext(WdfIoQueueGetDevice(WdfTimerGetParentObject(Timer)));
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+		"riffa: fpga:%s chnl:%d, request timed out\n", devExt->Name,
+		(timerExt->Chnl >= RIFFA_MAX_NUM_CHNLS ? timerExt->Chnl - RIFFA_MAX_NUM_CHNLS : timerExt->Chnl));
+
+	// Acquire the channel lock
+	WdfSpinLockAcquire(devExt->Chnl[timerExt->Chnl].SpinLock);
+
+	// See if we can cancel right now.
+	request = devExt->Chnl[timerExt->Chnl].Request;
+	if (request == NULL) {
+		canCancel = FALSE;
+	}
+	else {
+		canCancel = (devExt->Chnl[timerExt->Chnl].ActiveCount == 0);
+		if (canCancel) {
+			// NULL out the request so that no other threads use it
+			devExt->Chnl[timerExt->Chnl].Request = NULL;
+		}
+		else {
+			// Set the cancel flag so that the last active thread cancels for us.
+			devExt->Chnl[timerExt->Chnl].Cancel = 1;
+		}
+	}
+
+	// Release the channel lock
+	WdfSpinLockRelease(devExt->Chnl[timerExt->Chnl].SpinLock);
+
+	// Cancel the request
+	if (canCancel) {
+		if (timerExt->Chnl < RIFFA_MAX_NUM_CHNLS) {
+			DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+				"riffa: fpga:%s chnl:%d, cancelling timed out send\n", devExt->Name, timerExt->Chnl);
+		}
+		else {
+			DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+				"riffa: fpga:%s chnl:%d, cancelling timed out recv\n", devExt->Name,
+				timerExt->Chnl - RIFFA_MAX_NUM_CHNLS);
+		}
+		//status = WdfRequestUnmarkCancelable(request);
+		//if (status != STATUS_CANCELLED) {
+			// Complete the request (nobody has done it yet)
+			InterlockedExchange(&devExt->Chnl[timerExt->Chnl].Ready, 0);
+			devExt->Chnl[timerExt->Chnl].ActiveCount = 0;
+			devExt->Chnl[timerExt->Chnl].Cancel = 0;
+			WdfDmaTransactionRelease(devExt->Chnl[timerExt->Chnl].DmaTransaction);
+			WdfTimerStop(devExt->Chnl[timerExt->Chnl].Timer, FALSE);
+			WdfRequestCompleteWithInformation(request, STATUS_CANCELLED,
+				(ULONG_PTR)(devExt->Chnl[timerExt->Chnl].ConfirmedPrev +
+				devExt->Chnl[timerExt->Chnl].Confirmed)>>2);
+		//}
+	}
+}
+
+
+/******************************************************************************
+ * DMA CALLBACKS
+ *****************************************************************************/
+
+/**
+ * Called after the user has called into the driver to receive data, from the
+ * interrupt DPC when it detects a data receive event. Both conditions must be
+ * met before this function will be called. The function initiates a receive
+ * DMA operation then provides scatter gather information if necessary.
+ *
+ * DevExt - Pointer to the Device Extension
+ *
+ * Chnl - Channel number on which the DMA is taking place
+ */
+VOID RiffaStartRecvTransaction(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl) {
+	NTSTATUS status;
+	UINT64 length;
+	BOOLEAN complete = FALSE;
+
+	// Stop the timer (if set)
+	WdfTimerStop(DevExt->Chnl[Chnl].Timer, FALSE);
+
+	// Check that the request has not been cancelled.
+	if (!RiffaThreadEnter(DevExt, Chnl))
+		return;
+
+	// Start a recv transaction.
+	if (DevExt->Chnl[Chnl].Length) {
+		// Calculate room in the user space buffer and what needs to be spilled
+		if (DevExt->Chnl[Chnl].Capacity > DevExt->Chnl[Chnl].Offset) {
+			// Some (possibly all) of the data can fit in the user buffer.
+			DevExt->Chnl[Chnl].SpillAfter =
+				DevExt->Chnl[Chnl].Capacity - DevExt->Chnl[Chnl].Offset;
+			length = (DevExt->Chnl[Chnl].Capacity < DevExt->Chnl[Chnl].Length ?
+				DevExt->Chnl[Chnl].Capacity : DevExt->Chnl[Chnl].Length);
+			status = RiffaStartDmaTransaction(DevExt, Chnl,
+				length + DevExt->Chnl[Chnl].Offset, DevExt->Chnl[Chnl].Offset,
+				WdfDmaDirectionReadFromDevice);
+			if (!NT_SUCCESS(status)) {
+				complete = TRUE;
+			}
+		}
+		else {
+			// No room in user buffer, spill everything
+			DevExt->Chnl[Chnl].SpillAfter = 0;
+			RiffaProgramScatterGather(DevExt, Chnl);
+		}
+	}
+	else if (DevExt->Chnl[Chnl].Last) {
+		// Recognize zero length receive and complete
+		status = STATUS_SUCCESS;
+		complete = TRUE;
+	}
+	else {
+		// Invalid request, should never happen
+		status = STATUS_CANCELLED;
+		complete = TRUE;
+	}
+
+	// Check for a cancel request and service it.
+	if (!RiffaThreadExit(DevExt, Chnl)) {
+		// Complete the request if necessary.
+		if (complete) {
+			RiffaCompleteRequest(DevExt, Chnl, status);
+		}
+	}
+}
+
+
+/**
+ * Starts a DMA transaction using the user pages specified in the IOCTL output
+ * buffer as the source/receptical. This will result in RiffaEvtProgramDma
+ * being called with the scatter gather list. If the amount of data to map is
+ * too large, Windows will break up the transaction into multiple transfers.
+ * Only a portion of the output buffer will be mapped each transfer (each call
+ * to RiffaEvtProgramDma). Returns the status after starting the DMA transaction.
+ *
+ * Request - Pointer to the WDFREQUEST that was passed to IOCTl
+ *
+ * DevExt - Pointer to the Device Extension
+ *
+ * Chnl - Channel number on which the DMA transaction should take place
+ *
+ * Length - Length (in bytes) of the DMA
+ *
+ * Offset - Offset (in bytes) from the start of the IOCTL output buffer where
+ * data should be read/written
+ *
+ * DmaDirection - Direction of the DMA
+ *
+ * Returns status after starting the DMA transaction.
+ */
+NTSTATUS RiffaStartDmaTransaction(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,
+	IN UINT64 Length, IN UINT64 Offset, IN WDF_DMA_DIRECTION DmaDirection) {
+	NTSTATUS status = STATUS_SUCCESS;
+    PMDL mdl;
+    PVOID vaddr;
+    UINT64 length;
+
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+		"riffa: fpga:%s chnl:%d, starting txn (len:%lld, off:%lld, isSend?:%d)\n",
+		DevExt->Name, (Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS),
+		Length>>2, Offset, DmaDirection == WdfDmaDirectionWriteToDevice);
+
+	// Get the user space memory.
+	status = WdfRequestRetrieveOutputWdmMdl(DevExt->Chnl[Chnl].Request, &mdl);
+	if (!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s chnl:%d, WdfRequestRetrieveOutputWdmMdl failed\n",
+			DevExt->Name, (Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS));
+		return status;
+	}
+	// Move the virtual address forward to the offset
+	vaddr = MmGetMdlVirtualAddress(mdl);
+	vaddr = ((UINT32 *)vaddr) + Offset;
+
+	// Reduce the length by the offset amount
+	length = MmGetMdlByteCount(mdl);
+	length = (Length < length ? Length : length);
+	length = length - Offset;
+
+	// Reuse the DMA Transaction
+	status = WdfDmaTransactionInitialize(DevExt->Chnl[Chnl].DmaTransaction,
+		RiffaEvtProgramDma, DmaDirection, mdl, vaddr, (size_t)length);
+	if(!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s chnl:%d, WdfDmaTransactionInitialize failed\n",
+			DevExt->Name, (Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS));
+		return status;
+	}
+
+	// Execute the transaction
+	status = WdfDmaTransactionExecute(DevExt->Chnl[Chnl].DmaTransaction,
+		(WDFCONTEXT)Chnl);
+	if (!NT_SUCCESS(status)) {
+		DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+			"riffa: fpga:%s chnl:%d, WdfDmaTransactionExecute failed\n",
+			DevExt->Name, (Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS));
+		WdfDmaTransactionRelease(DevExt->Chnl[Chnl].DmaTransaction);
+		return status;
+	}
+
+	return status;
+}
+
+
+
+/**
+ * Programs the device with scatter gather data. Will program the device with
+ * spill buffer data (as scatter gather buffers) if the DMA length will overrun
+ * the receptical user buffer.
+ *
+ * DevExt - Pointer to the Device Extension
+ *
+ * Chnl - Channel number on which the DMA transaction takes place
+ *
+ * IsSend - TRUE if the direction is a "send", FALSE otherwise
+ */
+VOID RiffaProgramScatterGather(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl) {
+	PSCATTER_GATHER_LIST sgList;
+	PULONG bufBase;
+	PHYSICAL_ADDRESS bufAddr;
+    UINT32 pos;
+    UINT32 i;
+    UINT64 provided;
+    UINT64 length;
+    UINT64 spillAfter;
+
+	// Stop the timer (if set)
+	WdfTimerStop(DevExt->Chnl[Chnl].Timer, FALSE);
+
+	// Check that the request has not been cancelled.
+	if (!RiffaThreadEnter(DevExt, Chnl))
+		return;
+
+	// OK, then get the variables.
+	sgList = DevExt->Chnl[Chnl].SgList;
+	bufBase = DevExt->Chnl[Chnl].CommonBufferBase;
+	bufAddr = DevExt->Chnl[Chnl].CommonBufferBaseLA;
+	pos = DevExt->Chnl[Chnl].SgPos;
+	provided = DevExt->Chnl[Chnl].Provided;
+	length = DevExt->Chnl[Chnl].Length;
+	spillAfter = DevExt->Chnl[Chnl].SpillAfter;
+
+    // Translate the System's SCATTER_GATHER_LIST elements
+    // into the device's scatter gather elements.
+	for (i = 0; i < DevExt->MaxNumScatterGatherElems && provided < spillAfter; i++, pos++) {
+		if (pos >= sgList->NumberOfElements)
+			break;
+		WRITE_REGISTER_ULONG(bufBase + (i*4) + 0, sgList->Elements[pos].Address.LowPart);
+		WRITE_REGISTER_ULONG(bufBase + (i*4) + 1, sgList->Elements[pos].Address.HighPart);
+		WRITE_REGISTER_ULONG(bufBase + (i*4) + 2, (sgList->Elements[pos].Length>>2)); // Words!
+		provided += sgList->Elements[pos].Length;
+	}
+
+	// Handle any spillage
+	if (provided >= spillAfter) {
+		for (; i < DevExt->MaxNumScatterGatherElems && provided < length; i++) {
+			WRITE_REGISTER_ULONG(bufBase + (i*4) + 0, DevExt->SpillBufferBaseLA.LowPart);
+			WRITE_REGISTER_ULONG(bufBase + (i*4) + 1, DevExt->SpillBufferBaseLA.HighPart);
+			WRITE_REGISTER_ULONG(bufBase + (i*4) + 2, (RIFFA_SPILL_BUF_SIZE>>2)); // Words!
+			provided += RIFFA_SPILL_BUF_SIZE;
+		}
+	}
+
+    // Update the data structures
+    DevExt->Chnl[Chnl].Confirmed += DevExt->Chnl[Chnl].ProvidedPrev;
+    DevExt->Chnl[Chnl].ProvidedPrev = provided - DevExt->Chnl[Chnl].Provided;
+	DevExt->Chnl[Chnl].Provided = provided;
+	DevExt->Chnl[Chnl].SgPos = pos;
+
+	if (i > 0) {
+		// Let the device know about the new scatter gather data.
+		if (Chnl < RIFFA_MAX_NUM_CHNLS) {
+			KdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+				"riffa: fpga:%s chnl:%d, sg buf for send txn: %d elements\n",
+				DevExt->Name, (Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS), i));
+			WRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl, RIFFA_RX_SG_ADDR_LO_REG), bufAddr.LowPart);
+			WRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl, RIFFA_RX_SG_ADDR_HI_REG), bufAddr.HighPart);
+			WRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl, RIFFA_RX_SG_LEN_REG), (i*4*4)>>2); // Words!
+		}
+		else {
+			KdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+				"riffa: fpga:%s chnl:%d, sg buf for recv txn: %d elements\n",
+				DevExt->Name, (Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS), i));
+			WRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl - RIFFA_MAX_NUM_CHNLS, RIFFA_TX_SG_ADDR_LO_REG), bufAddr.LowPart);
+			WRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl - RIFFA_MAX_NUM_CHNLS, RIFFA_TX_SG_ADDR_HI_REG), bufAddr.HighPart);
+			WRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl - RIFFA_MAX_NUM_CHNLS, RIFFA_TX_SG_LEN_REG), (i*4*4)>>2); // Words!
+		}
+	}
+	else if (provided < length) {
+		// Let the device know that no more scatter gather data will be provided
+		// until a "transfer done" signal is received. This is initiated differently
+		// for a send vs. a receive transaction.
+		InterlockedExchange(&DevExt->Chnl[Chnl].ReqdDone, 1);
+		if (Chnl < RIFFA_MAX_NUM_CHNLS) {
+			// Write the length to signal request for "done" signal after all the
+			// scatter gather regions have been used.
+		    WRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl, RIFFA_RX_LEN_REG),
+		    	(ULONG)(provided>>2));
+		}
+		else {
+			// Read the length to signal request for "done" signal after all the
+			// scatter gather regions have been used.
+			READ_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl - RIFFA_MAX_NUM_CHNLS, RIFFA_TX_LEN_REG));
+		}
+		if (Chnl < RIFFA_MAX_NUM_CHNLS) {
+			KdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+				"riffa: fpga:%s chnl:%d, splitting send txn\n", DevExt->Name, Chnl));
+		}
+		else {
+			KdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,
+				"riffa: fpga:%s chnl:%d, splitting recv txn\n", DevExt->Name, Chnl - RIFFA_MAX_NUM_CHNLS));
+		}
+	}
+
+	// Check for a cancel request and service it.
+	if (!RiffaThreadExit(DevExt, Chnl)) {
+		// Start the timer (if necessary)
+		if (DevExt->Chnl[Chnl].Timeout > 0)
+			WdfTimerStart(DevExt->Chnl[Chnl].Timer, WDF_REL_TIMEOUT_IN_MS(DevExt->Chnl[Chnl].Timeout));
+	}
+}
+
+
+
+/**
+ * Called after the last DMA transfer for the DMA transaction is completed.
+ * Sets the transferred bytes and completes the IOCTL call.
+ *
+ * DevExt - Pointer to the Device Extension
+ *
+ * Chnl - Channel number on which the DMA transaction takes place
+ *
+ * Transferred - Words transferred according to the hardware
+ *
+ * Status - Status after the last transfer has completed.
+ */
+VOID RiffaTransactionComplete(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,
+	IN UINT32 Transferred, IN NTSTATUS Status) {
+	BOOLEAN complete = FALSE;
+
+	// Stop the timer (if set)
+	WdfTimerStop(DevExt->Chnl[Chnl].Timer, FALSE);
+
+	// Check that the request has not been cancelled.
+	if (!RiffaThreadEnter(DevExt, Chnl))
+		return;
+
+	// Release the DMA Transaction
+	WdfDmaTransactionRelease(DevExt->Chnl[Chnl].DmaTransaction);
+	DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,
+		"riffa: fpga:%s chnl:%d, words transferred: %lu\n", DevExt->Name,
+		(Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS), Transferred);
+
+	if (Chnl < RIFFA_MAX_NUM_CHNLS) {
+		// Update the total confirmed data
+		DevExt->Chnl[Chnl].Confirmed = (((UINT64)Transferred)<<2);
+
+		// Complete the send request
+		complete = TRUE;
+	}
+	else {
+		// Complete or repeat
+		if (DevExt->Chnl[Chnl].Last || !NT_SUCCESS(Status)) {
+			// Update the total confirmed data
+			DevExt->Chnl[Chnl].Confirmed = (((UINT64)Transferred)<<2);
+
+			// Complete the receive request
+			complete = TRUE;
+		}
+		else {
+			// Not the "last" transaction. Save the transferred amount.
+			DevExt->Chnl[Chnl].ConfirmedPrev += (((UINT64)Transferred)<<2);
+			DevExt->Chnl[Chnl].Confirmed = 0;
+			DevExt->Chnl[Chnl].ProvidedPrev = 0;
+			DevExt->Chnl[Chnl].Provided = 0;
+
+			// Stay in the kernel and start another receive DMA transaction.
+			// If an interrupt with transaction info has already been received,
+			// start the transaction. If not, set the "ready" bit.
+			if (InterlockedExchange(&DevExt->Chnl[Chnl].Ready, 1)) {
+				// Clear the "ready" bit and start the transaction
+				InterlockedExchange(&DevExt->Chnl[Chnl].Ready, 0);
+				RiffaStartRecvTransaction(DevExt, Chnl);
+			}
+		}
+	}
+
+	// Check for a cancel request and service it.
+	if (!RiffaThreadExit(DevExt, Chnl)) {
+		// Complete the request if necessary.
+		if (complete) {
+			RiffaCompleteRequest(DevExt, Chnl, Status);
+		}
+	}
+}
+
+
+
+/**
+ * Programs the device for DMA send transactions. Note, that there is no way to
+ * program the device for receive transactions. Receive transactions can only
+ * be initiated from the device.
+ *
+ * DevExt - Pointer to the Device Extension
+ *
+ * Chnl - Channel number on which the DMA transaction takes place
+ *
+ * Length - Length (in words) of the DMA
+ *
+ * Offset - Offset (in words) to send to the device
+ *
+ * Last - 1 if this is the last transaction for the device, 0 otherwise
+ */
+VOID RiffaProgramSend(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl, IN UINT32 Length,
+	IN UINT32 Offset, IN UINT32 Last) {
+    UINT32 offlast;
+    UINT32 chnl;
+
+    // Let the device know about the new transfer.
+    offlast = ((Offset<<1) | (Last & 0x1));
+    chnl = (Chnl >= RIFFA_MAX_NUM_CHNLS ? Chnl - RIFFA_MAX_NUM_CHNLS : Chnl);
+    WRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(chnl, RIFFA_RX_OFFLAST_REG), offlast);
+    WRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(chnl, RIFFA_RX_LEN_REG), Length);
+}
+
+
+
+/**
+ * The framework calls a driver's EvtProgramDma event callback function
+ * when the driver calls WdfDmaTransactionExecute and the system has
+ * enough map registers to do the transfer. The callback function must
+ * program the hardware to start the transfer. A single transaction
+ * initiated by calling WdfDmaTransactionExecute may result in multiple
+ * calls to this function if the buffer is too large and there aren't
+ * enough map registers to do the whole transfer.
+ *
+ * Transaction - DMA transactions initialized and started in RiffaStartDmaTransaction
+ *
+ * Device - A handle to the WDFDEVICE
+ *
+ * Context - Value passed as the context parameter to WdfDmaTransactionExecute
+ *
+ * Direction - DMA direction of the transfer
+ *
+ * SgList - Scatter gather list of the mapped memory to use for transferring
+ *
+ * Returns TRUE
+ */
+BOOLEAN RiffaEvtProgramDma(IN WDFDMATRANSACTION Transaction, IN WDFDEVICE Device,
+	IN PVOID Context, IN WDF_DMA_DIRECTION Direction, IN PSCATTER_GATHER_LIST SgList) {
+    PDEVICE_EXTENSION devExt;
+	UINT32 chnl;
+
+    // Initialize variables and structures
+    devExt = RiffaGetDeviceContext(Device);
+	chnl = (UINT32)Context;
+
+	// Save the scatter gather list
+	devExt->Chnl[chnl].SgList = SgList;
+	devExt->Chnl[chnl].SgPos = 0;
+
+	if (Direction == WdfDmaDirectionWriteToDevice &&
+		WdfDmaTransactionGetBytesTransferred(Transaction) == 0) {
+		// Program the start of a new transfer.
+		RiffaProgramSend(devExt, chnl, (UINT32)(devExt->Chnl[chnl].Length>>2),
+			(UINT32)(devExt->Chnl[chnl].Offset>>2), devExt->Chnl[chnl].Last);
+	}
+
+	// Write the initial scatter gather data and notify the device.
+	RiffaProgramScatterGather(devExt, chnl);
+
+    return TRUE;
+}
+
diff --git a/driver/windows/sys/riffa.inx b/driver/windows/sys/riffa.inx
new file mode 100755
index 0000000..1d86c2a
--- /dev/null
+++ b/driver/windows/sys/riffa.inx
@@ -0,0 +1,108 @@
+
+[Version]
+Signature="$WINDOWS NT$"
+Class=FPGA
+ClassGuid={78A1C341-4539-11d3-B88D-00C04FAD5171}
+Provider=%UCSD%
+DriverVer=03/20/2003,6.00.3790
+CatalogFile=riffa.cat
+
+[DestinationDirs]
+DefaultDestDir = 12
+
+; ================= Class section =====================
+
+[ClassInstall32]
+Addreg=FPGAClassReg     
+
+[FPGAClassReg]
+HKR,,,0,%ClassName%
+HKR,,Icon,,-5
+HKR,,DeviceCharacteristics,0x10001,0x100     ;Use same security checks on relative opens
+HKR,,Security,,"D:P(A;;GA;;;WD)" ;Allow generic all access to all. 
+;HKR,,Security,,"D:P(A;;GA;;;SY)(A;;GA;;;BA)" ;Allow generic all access to system and built-in Admin. 
+
+; ================= Device Install section =====================
+
+[ControlFlags]
+ExcludeFromSelect=*
+
+[Manufacturer]
+%UCSD%=UCSD,NT$ARCH$
+
+[SourceDisksFiles]
+riffa.sys=1
+
+[SourceDisksNames]
+1=%DISK_NAME%,
+
+; For Win2K
+[UCSD]
+; DisplayName                        Section           DeviceId           CompatibleId
+; -----------                        -------           --------           ------------
+%RIFFA.XILINXDESC%%RIFFA.DEBUG%=     RIFFA_Inst,       PCI\VEN_10EE,      PCI\VEN_10EE
+%RIFFA.ALTERADESC%%RIFFA.DEBUG%=     RIFFA_Inst,       PCI\VEN_1172,      PCI\VEN_1172
+
+; For XP and later
+[UCSD.NT$ARCH$]
+; DisplayName                        Section           DeviceId           CompatibleId
+; -----------                        -------           --------           ------------
+%RIFFA.XILINXDESC%%RIFFA.DEBUG%=     RIFFA_Inst,       PCI\VEN_10EE,      PCI\VEN_10EE
+%RIFFA.ALTERADESC%%RIFFA.DEBUG%=     RIFFA_Inst,       PCI\VEN_1172,      PCI\VEN_1172
+
+[RIFFA_Inst.NT]
+CopyFiles=RIFFA.CopyFiles
+
+[RIFFA.CopyFiles]
+riffa.sys
+
+[RIFFA_Inst.NT.HW]
+AddReg=RIFFA.HwReg 
+
+[RIFFA.HwReg]
+HKR,"Interrupt Management",,0x00000010
+HKR,"Interrupt Management\MessageSignaledInterruptProperties",,0x00000010
+HKR,"Interrupt Management\MessageSignaledInterruptProperties",MSISupported,0x00010001,1
+
+[RIFFA_Inst.NT.Services]
+AddService=RIFFA,0x00000002,RIFFA_Service 
+
+[RIFFA_Service]
+DisplayName    = %RIFFA.SVCDESC%                            
+ServiceType    = 1                  ; SERVICE_KERNEL_DRIVER
+StartType      = 3                  ; SERVICE_DEMAND_START
+ErrorControl   = 1                  ; SERVICE_ERROR_NORMAL
+ServiceBinary  = %12%\riffa.sys                            
+AddReg         = RIFFA_Parameters_AddReg
+
+;-------------- Coinstaller installation
+[DestinationDirs]
+CoInstaller_CopyFiles = 11
+
+[RIFFA_Inst.NT.CoInstallers]
+AddReg=CoInstaller_AddReg
+CopyFiles=CoInstaller_CopyFiles
+
+[CoInstaller_CopyFiles]
+WdfCoInstaller$KMDFCOINSTALLERVERSION$.dll
+
+[SourceDisksFiles]
+WdfCoInstaller$KMDFCOINSTALLERVERSION$.dll=1 ; make sure the number matches with SourceDisksNames
+
+[CoInstaller_AddReg]
+HKR,,CoInstallers32,0x00010000, "WdfCoInstaller$KMDFCOINSTALLERVERSION$.dll,WdfCoInstaller"
+
+[RIFFA_Inst.NT.Wdf]
+KmdfService = RIFFA, RIFFA_wdfsect
+
+[RIFFA_wdfsect]
+KmdfLibraryVersion = $KMDFVERSION$
+
+[Strings]
+UCSD = "University of California, San Diego"
+ClassName = "RIFFA Devices"
+RIFFA.SVCDESC = "Driver Service for RIFFA FPGAs"
+RIFFA.XILINXDESC = "Xilinx(R) FPGA"
+RIFFA.ALTERADESC = "Altera(R) FPGA"
+DISK_NAME = "RIFFA Install Disk"
+
diff --git a/driver/windows/sys/riffa.rc b/driver/windows/sys/riffa.rc
new file mode 100755
index 0000000..8cc4895
--- /dev/null
+++ b/driver/windows/sys/riffa.rc
@@ -0,0 +1,15 @@
+#include <windows.h>
+
+#include <ntverp.h>
+
+#define VER_FILETYPE                VFT_DRV
+#define VER_FILESUBTYPE             VFT2_DRV_SYSTEM
+#define VER_FILEDESCRIPTION_STR     "WDF Driver for RIFFA"
+#define VER_INTERNALNAME_STR        "riffa.sys"
+#define VER_ORIGINALFILENAME_STR    "riffa.sys"
+
+#include "common.ver"
+
+
+
+
diff --git a/driver/windows/sys/riffa_driver.h b/driver/windows/sys/riffa_driver.h
new file mode 100755
index 0000000..7368e86
--- /dev/null
+++ b/driver/windows/sys/riffa_driver.h
@@ -0,0 +1,19 @@
+//
+// The following value is arbitrarily chosen from the space defined
+// by Microsoft as being "for non-Microsoft use"
+//
+//
+// {40d49fb9-6085-4e1d-8753-822be944d7bb}
+DEFINE_GUID (GUID_RIFFA_INTERFACE,
+   0x40d49fb9, 0x6085, 0x4e1d, 0x87, 0x53, 0x82, 0x2b, 0xe9, 0x44, 0xd7, 0xbb);
+
+// The IOCTL function codes from 0x800 to 0xFFF are for customer use.
+#define IOCTL_RIFFA_SEND \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x900, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)
+#define IOCTL_RIFFA_RECV \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x901, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)
+#define IOCTL_RIFFA_LIST \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x902, METHOD_OUT_DIRECT ,FILE_ANY_ACCESS)
+#define IOCTL_RIFFA_RESET \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x903, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)
+
diff --git a/driver/windows/sys/riffa_private.h b/driver/windows/sys/riffa_private.h
new file mode 100755
index 0000000..5dc0272
--- /dev/null
+++ b/driver/windows/sys/riffa_private.h
@@ -0,0 +1,187 @@
+#if !defined(_RIFFA_H_)
+#define _RIFFA_H_
+
+// Adjusts register offsets for each channel
+#define CHNL_REG(c, o) (((c)<<4) + o)
+
+// Register offsets
+#define RIFFA_RX_SG_LEN_REG			0x0
+#define RIFFA_RX_SG_ADDR_LO_REG		0x1
+#define RIFFA_RX_SG_ADDR_HI_REG		0x2
+#define RIFFA_RX_LEN_REG			0x3
+#define RIFFA_RX_OFFLAST_REG		0x4
+#define RIFFA_TX_SG_LEN_REG			0x5
+#define RIFFA_TX_SG_ADDR_LO_REG		0x6
+#define RIFFA_TX_SG_ADDR_HI_REG		0x7
+#define RIFFA_TX_LEN_REG			0x8
+#define RIFFA_TX_OFFLAST_REG		0x9
+#define RIFFA_INFO_REG				0xA
+#define RIFFA_IRQ_0_REG				0xB
+#define RIFFA_IRQ_1_REG				0xC
+#define RIFFA_RX_TNFR_LEN_REG		0xD
+#define RIFFA_TX_TNFR_LEN_REG		0xE
+
+// Size of common buffer for scatter gather elements
+#define RIFFA_MIN_SG_BUF_SIZE (4*1024)
+
+// Size of common buffer for receive data spill
+#define RIFFA_SPILL_BUF_SIZE (4*1024)
+
+// Maximum number of scatter gather elements for each transfer
+#define RIFFA_MIN_NUM_SG_ELEMS (200)
+
+// Maximum bus width (multiply by 32 to get bit width)
+#define RIFFA_MAX_BUS_WIDTH_PARAM (4)
+
+// Maximum DMA transfer size (in bytes).
+#define RIFFA_MAX_TNFR_LEN (0xFFFFFFFF)
+
+// Number of DMA channels supported
+#define RIFFA_MAX_NUM_CHNLS (12)
+
+// Maximum number of RIFFA FPGAs
+#define RIFFA_MAX_NUM_FPGAS (5)
+
+// The structure used to hold data transfer information
+typedef struct RIFFA_FPGA_CHNL_IO {
+	UINT32					Id;
+	UINT32					Chnl;
+	UINT32					Length;
+	UINT32					Offset;
+	UINT32					Last;
+	UINT64					Timeout;
+} RIFFA_FPGA_CHNL_IO, * PRIFFA_FPGA_CHNL_IO;
+
+// The structure used to hold FPGA information
+typedef struct RIFFA_FPGA_INFO {
+	UINT32					num_fpgas;
+	UINT32					id[RIFFA_MAX_NUM_FPGAS];
+	UINT32					num_chnls[RIFFA_MAX_NUM_FPGAS];
+	CHAR					name[RIFFA_MAX_NUM_FPGAS][16];
+	UINT32					vendor_id[RIFFA_MAX_NUM_FPGAS];
+	UINT32					device_id[RIFFA_MAX_NUM_FPGAS];
+} RIFFA_FPGA_INFO, * PRIFFA_FPGA_INFO;
+
+// Struct for holding DMA transaction state
+typedef struct CHNL_DIR_STATE {
+	LONG					Ready;
+	LONG					InUse;
+	LONG					ReqdDone;
+	UINT64					Length;
+	UINT64					Offset;
+	UINT32					Last;
+	UINT64					Timeout;
+	UINT64					Capacity;
+	UINT64					Provided;
+	UINT64					ProvidedPrev;
+	UINT64					Confirmed;
+	UINT64					ConfirmedPrev;
+	UINT64					SpillAfter;
+	PSCATTER_GATHER_LIST	SgList;
+	UINT32					SgPos;
+	UINT32					ActiveCount;
+	UINT32					Cancel;
+	WDFSPINLOCK				SpinLock;
+	WDFTIMER				Timer;
+	WDFREQUEST				Request;
+	WDFDMATRANSACTION 		DmaTransaction;
+	WDFCOMMONBUFFER 		CommonBuffer;
+	PULONG 					CommonBufferBase;
+	PHYSICAL_ADDRESS 		CommonBufferBaseLA;	// Logical Address
+} CHNL_DIR_STATE, *PCHNL_DIR_STATE;
+
+// Struct for holding interrupt signals and data
+typedef struct INTR_CHNL_DIR_DATA {
+	BOOLEAN 				NewTxn;
+	UINT32 					OffLast;
+	UINT32 					Length;
+	BOOLEAN 				SgRead;
+	BOOLEAN 				Done;
+} INTR_CHNL_DIR_DATA, *PINTR_CHNL_DIR_DATA;
+
+// The device extension for the device object
+typedef struct _DEVICE_EXTENSION {
+	WDFDEVICE 				Device;
+	PULONG 					Bar0;
+	UINT32 					Bar0Length;
+	UINT32					MaxNumScatterGatherElems;
+	WDFINTERRUPT 			Interrupt;
+	WDFDMAENABLER 			DmaEnabler;
+	WDFQUEUE 				IoctlQueue;
+	UINT32 					NumChnls;
+	UINT32 					VendorId;
+	UINT32 					DeviceId;
+	CHAR 					Name[16];
+	INTR_CHNL_DIR_DATA		IntrData[2 * RIFFA_MAX_NUM_CHNLS];	// Send is the first bank,
+	CHNL_DIR_STATE			Chnl[(2*RIFFA_MAX_NUM_CHNLS)];		// recv is the second bank
+	WDFCOMMONBUFFER 		SpillBuffer;
+	PUCHAR 					SpillBufferBase;
+	PHYSICAL_ADDRESS 		SpillBufferBaseLA;	// Logical Address
+} DEVICE_EXTENSION, *PDEVICE_EXTENSION;
+
+// The request extension for the request object
+typedef struct _REQUEST_EXTENSION {
+	UINT32 					Chnl;
+} REQUEST_EXTENSION, *PREQUEST_EXTENSION;
+
+// The timer extension for the timer object
+typedef struct _TIMER_EXTENSION {
+	UINT32 					Chnl;
+} TIMER_EXTENSION, *PTIMER_EXTENSION;
+
+// This will generate the function named RiffaGetDeviceContext to be used for
+// retreiving the DEVICE_EXTENSION pointer.
+WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(DEVICE_EXTENSION, RiffaGetDeviceContext)
+
+// This will generate the function named RiffaGetTimerContext to be used for
+// retreiving the TIMER_EXTENSION pointer.
+WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(TIMER_EXTENSION, RiffaGetTimerContext)
+
+// This will generate the function named RiffaGetRequestContext to be used for
+// retreiving the REQUEST_EXTENSION pointer.
+WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(REQUEST_EXTENSION, RiffaGetRequestContext)
+
+
+// Function prototypes
+DRIVER_INITIALIZE DriverEntry;
+
+EVT_WDF_DRIVER_DEVICE_ADD RiffaEvtDeviceAdd;
+EVT_WDF_OBJECT_CONTEXT_CLEANUP RiffaEvtDriverContextCleanup;
+
+EVT_WDF_DEVICE_PREPARE_HARDWARE RiffaEvtDevicePrepareHardware;
+EVT_WDF_DEVICE_RELEASE_HARDWARE RiffaEvtDeviceReleaseHardware;
+NTSTATUS RiffaReadHardwareIds(IN PDEVICE_EXTENSION DevExt);
+
+EVT_WDF_INTERRUPT_ISR RiffaEvtInterruptIsr;
+EVT_WDF_INTERRUPT_DPC RiffaEvtInterruptDpc;
+BOOLEAN RiffaProcessInterrupt(IN PDEVICE_EXTENSION DevExt, IN UINT32 Offset, IN UINT32 Vect);
+
+EVT_WDF_IO_QUEUE_IO_DEVICE_CONTROL  RiffaEvtIoDeviceControl;
+VOID RiffaIoctlSend(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,
+	IN size_t OutputBufferLength, IN size_t InputBufferLength);
+VOID RiffaIoctlRecv(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,
+	IN size_t OutputBufferLength, IN size_t InputBufferLength);
+VOID RiffaIoctlList(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,
+	IN size_t OutputBufferLength, IN size_t InputBufferLength);
+VOID RiffaIoctlReset(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request);
+
+BOOLEAN RiffaThreadEnter(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl);
+BOOLEAN RiffaThreadExit(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl);
+VOID RiffaCompleteRequest(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl, IN NTSTATUS Status);
+EVT_WDF_REQUEST_CANCEL RiffaEvtRequestCancel;
+EVT_WDF_TIMER RiffaEvtTimerFunc;
+
+VOID RiffaStartRecvTransaction(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl);
+NTSTATUS RiffaStartDmaTransaction(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,
+	IN UINT64 Length, IN UINT64 Offset, IN WDF_DMA_DIRECTION DmaDirection);
+VOID RiffaProgramScatterGather(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl);
+VOID RiffaTransactionComplete(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,
+	IN UINT32 Transferred, IN NTSTATUS Status);
+VOID RiffaProgramSend(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl, IN UINT32 Length,
+	IN UINT32 Offset, IN UINT32 Last);
+EVT_WDF_PROGRAM_DMA RiffaEvtProgramDma;
+
+#pragma warning(disable:4127) // avoid conditional expression is constant error with W4
+
+#endif
+
diff --git a/driver/windows/sys/sources b/driver/windows/sys/sources
new file mode 100755
index 0000000..4291c71
--- /dev/null
+++ b/driver/windows/sys/sources
@@ -0,0 +1,40 @@
+TARGETNAME=riffa
+TARGETTYPE=DRIVER
+
+
+KMDF_VERSION_MAJOR=1
+
+INF_NAME=riffa
+NTTARGETFILE0=$(OBJ_PATH)\$(O)\$(INF_NAME).inf
+NTTARGETFILE2=POST
+PASS0_BINPLACE=$(NTTARGETFILE0)
+
+TARGETLIBS=$(TARGETLIBS) \
+           $(DDK_LIB_PATH)\ntstrsafe.lib
+
+PRECOMPILED_INCLUDE=precomp.h
+PRECOMPILED_PCH=precomp.pch
+PRECOMPILED_OBJ=precomp.obj
+
+#C_DEFINES = $(C_DEFINES) -DASSOC_WRITE_REQUEST_WITH_DMA_TRANSACTION=1
+
+SOURCES= riffa.rc  \
+         riffa.c
+         
+# Generate WPP tracing code
+# $(SOURCES)   -- run software preprocessor on files listed in SOURCES
+# -km          -- use kernel mode
+# -func        -- define function we'll use for tracing
+#                 This would map all TraceEvents calls to 
+#                 DoTraceMessage.
+#
+RUN_WPP= $(SOURCES)                             \
+         -km                                    \
+         -func:TraceEvents(LEVEL,FLAGS,MSG,...) \
+         -gen:{km-WdfDefault.tpl}*.tmh
+         
+TARGET_DESTINATION=wdf
+
+# Temporarily excuse usage of serviceability impairing macros in code...
+ALLOW_DATE_TIME=1
+
diff --git a/driver/windows/sys/trace.h b/driver/windows/sys/trace.h
new file mode 100755
index 0000000..69ef125
--- /dev/null
+++ b/driver/windows/sys/trace.h
@@ -0,0 +1,31 @@
+#include <evntrace.h> // For TRACE_LEVEL definitions
+
+//
+// If software tracing is defined in the sources file..
+// WPP_DEFINE_CONTROL_GUID specifies the GUID used for this driver.
+// *** REPLACE THE GUID WITH YOUR OWN UNIQUE ID ***
+// WPP_DEFINE_BIT allows setting debug bit masks to selectively print.
+// The names defined in the WPP_DEFINE_BIT call define the actual names
+// that are used to control the level of tracing for the control guid
+// specified.
+//
+// Name of the logger is RIFFA and the guid is
+//   {CA630800-D4D4-4457-8983-DFBBFCAC5542}
+//   (0xca630800, 0xd4d4, 0x4457, 0x89, 0x83, 0xdf, 0xbb, 0xfc, 0xac, 0x55, 0x42);
+//
+
+#define WPP_CHECK_FOR_NULL_STRING  //to prevent exceptions due to NULL strings
+
+#define WPP_CONTROL_GUIDS \
+    WPP_DEFINE_CONTROL_GUID(RiffaTraceGuid, (ca630800, D4D4, 4457,8983, DFBBFCAC5542),\
+        WPP_DEFINE_BIT(DBG_INIT)             /* bit  0 = 0x00000001 */ \
+        WPP_DEFINE_BIT(DBG_PNP)              /* bit  1 = 0x00000002 */ \
+        /* You can have up to 32 defines. If you want more than that,\
+            you have to provide another trace control GUID */\
+        )
+
+
+#define WPP_LEVEL_FLAGS_LOGGER(lvl,flags) WPP_LEVEL_LOGGER(flags)
+#define WPP_LEVEL_FLAGS_ENABLED(lvl, flags) (WPP_LEVEL_ENABLED(flags) && WPP_CONTROL(WPP_BIT_ ## flags).Level  >= lvl)
+
+
diff --git a/driver/windows/win7install.bat b/driver/windows/win7install.bat
new file mode 100755
index 0000000..e799192
--- /dev/null
+++ b/driver/windows/win7install.bat
@@ -0,0 +1,8 @@
+@echo off
+
+set OLDDIR=%CD%
+set BDIR1=%CD%\sys\obj%_BUILDTYPE%_%DDK_TARGET_OS%_x86\i386
+set BDIR2=%CD%\sys\obj%_BUILDTYPE%_%DDK_TARGET_OS%_amd64\amd64
+chdir /d %CD%\install
+call install.bat %BDIR1% %BDIR2% %_BUILDTYPE%
+chdir /d %OLDDIR%
\ No newline at end of file
diff --git a/fpga/altera/de4/DE4Gen1x8If64/bit/DE4Gen1x8If64.sof b/fpga/altera/de4/DE4Gen1x8If64/bit/DE4Gen1x8If64.sof
new file mode 100644
index 0000000..5631564
Binary files /dev/null and b/fpga/altera/de4/DE4Gen1x8If64/bit/DE4Gen1x8If64.sof differ
diff --git a/fpga/altera/de4/DE4Gen1x8If64/constr/DE4Gen1x8If64.sdc b/fpga/altera/de4/DE4Gen1x8If64/constr/DE4Gen1x8If64.sdc
new file mode 100644
index 0000000..4894afc
--- /dev/null
+++ b/fpga/altera/de4/DE4Gen1x8If64/constr/DE4Gen1x8If64.sdc
@@ -0,0 +1,64 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            DE4Gen1x8If64.sdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Synopsys Design Constraints for the DE4 board.
+# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+# Oscillator clk (50 MHz Input)
+create_clock -name OSCILLATOR_CLK -period 20 [get_ports {OSC_50_BANK2}]
+
+# Refclk (100 MHz differential input)
+create_clock -period "100 MHz" -name {refclk} [get_ports {PCIE_REFCLK}]
+
+# 50 MHZ PLL Clock
+create_generated_clock -name clk50 -source [get_ports {OSC_50_BANK2}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[0]}]
+
+# 125 MHZ PLL Clock
+create_generated_clock -name clk125 -multiply_by 5 -divide_by 2 -source [get_ports {OSC_50_BANK2}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[1]}]
+
+# 250 MHZ PLL Clock
+create_generated_clock -name clk250 -multiply_by 5 -source [get_ports {OSC_50_BANK2}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[2]}]
+
+derive_pll_clocks 
+derive_clock_uncertainty
+
+# Imported from IP Compiler user guide
+set_clock_groups -exclusive -group [get_clocks { refclk*clkout }] -group [get_clocks { *div0*coreclkout}]
+set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }] -group [get_clocks { *central_clk_div1* }]
+
diff --git a/fpga/altera/de4/DE4Gen1x8If64/hdl/DE4Gen1x8If64.v b/fpga/altera/de4/DE4Gen1x8If64/hdl/DE4Gen1x8If64.v
new file mode 100644
index 0000000..1332ac4
--- /dev/null
+++ b/fpga/altera/de4/DE4Gen1x8If64/hdl/DE4Gen1x8If64.v
@@ -0,0 +1,417 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            DE4Gen1x8If64.v
+// Version:             
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Altera Stratix IV IP Compiler for PCI Express
+//                      module and the Terasic DE4 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`timescale 1ps / 1ps
+module DE4Gen1x8If64
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 12,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Quartus IP Library
+      parameter C_PCI_DATA_WIDTH = 64,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     input                    OSC_50_BANK2,
+     input                    OSC_50_BANK3,
+     input                    OSC_50_BANK4,
+     input                    OSC_50_BANK5,
+     input                    OSC_50_BANK6,
+     input                    PCIE_RESET_N,
+     input                    PCIE_REFCLK,
+     input [C_NUM_LANES-1:0]  PCIE_RX_IN,
+     output [C_NUM_LANES-1:0] PCIE_TX_OUT,
+     output [7:0]             LED
+     );
+
+    // ----------PLL Signals----------
+    wire                      clk50;
+    wire                      clk125;
+    wire                      clk250;
+    wire                      locked;
+    wire                      inclk0;
+
+    // ----------PCIe Core Signals----------
+    // ----------PCIe Clocks----------
+    wire                      pld_clk;
+    wire                      reconfig_clk;
+    wire                      core_clk_out;
+    wire                      fixedclk_serdes;
+    wire                      refclk;
+    wire                      rc_pll_locked;
+    wire                      cal_blk_clk;
+
+    // ----------PCIe Resets----------
+    wire [  4: 0]             pex_msi_num;
+    wire                      pll_powerdown;
+    wire                      reset_status;
+    wire                      crst;
+    wire                      npor;
+    wire                      srst;
+    wire                      gxb_powerdown;
+
+    // ----------PCIe Transaction layer configuration ----------
+    wire [  3: 0]             tl_cfg_add;
+    wire [ 31: 0]             tl_cfg_ctl;
+    wire                      tl_cfg_ctl_wr;
+    wire [ 52: 0]             tl_cfg_sts;
+    wire                      tl_cfg_sts_wr;
+    wire [ 19: 0]             ko_cpl_spc_vc0;
+    
+    // ----------PCIe Local Management Interface----------
+    wire                      lmi_ack;
+    wire [ 31: 0]             lmi_dout;
+    wire [ 11: 0]             lmi_addr;
+    wire [ 31: 0]             lmi_din;
+    wire                      lmi_rden;
+    wire                      lmi_wren;
+
+    // ----------PCIe Interrupt Interface   ----------
+    wire                      app_int_ack;
+    wire                      app_msi_ack;
+    wire                      app_int_sts;
+    wire                      app_msi_req;
+
+    // ----------PCIe Status Signals----------
+    wire                      hotrst_exit;
+    wire                      l2_exit;
+    wire [3:0]                lane_act;
+    wire [4:0]                ltssm;
+    wire                      pme_to_sr;
+    wire                      suc_spd_neg;
+
+    // ----------PCIe RX Interface----------
+    wire                      rx_st_mask0;
+    wire [  7: 0]             rx_st_bardec0;
+    wire [ 15: 0]             rx_st_be0;
+    wire [0:0]                rx_st_sop0;
+    wire [0:0]                rx_st_eop0;
+    wire [0:0]                rx_st_err0;
+    wire [0:0]                rx_st_valid0;
+    wire [0:0]                rx_st_empty0;
+    wire                      rx_st_ready0;
+    wire [C_PCI_DATA_WIDTH-1:0] rx_st_data0;
+
+    // ----------PCIe TX Interface----------
+    wire [0:0]                   tx_st_sop0;
+    wire [0:0]                   tx_st_eop0;
+    wire [0:0]                   tx_st_err0;
+    wire [0:0]                   tx_st_valid0;
+    wire [0:0]                   tx_st_empty0;
+    wire                         tx_st_ready0;
+    wire [C_PCI_DATA_WIDTH-1:0]  tx_st_data0;
+
+    // ----------ALTGX Signals----------
+    wire                         busy;
+    wire                         busy_altgxb_reconfig;
+    wire [33:0]                  reconfig_fromgxb;
+    wire [3:0]                   reconfig_togxb;
+
+    // ----------Resets ----------
+    reg [4:0]                    rRstCtr,_rRstCtr;
+    reg [2:0]                    rRstSync,_rRstSync;
+    wire                         wSyncRst;
+    
+    always @(*) begin
+        _rRstSync = {rRstSync[1:0], ~npor};
+        _rRstCtr = rRstCtr;
+        if (rRstSync[2]) begin
+            _rRstCtr = 0;
+        end else if (~rRstCtr[4]) begin
+            _rRstCtr = rRstCtr + 1;
+        end
+    end
+    
+    always @(posedge pld_clk) begin
+        rRstSync <= _rRstSync;
+        rRstCtr <= _rRstCtr;
+    end
+
+    assign wSyncRst = ~ rRstCtr[4];
+    assign srst = wSyncRst;
+    assign crst = wSyncRst;
+
+    // ----------PLL assignments----------
+    assign inclk0 = OSC_50_BANK2;
+    assign fixedclk_serdes = clk125;
+
+    assign reconfig_clk = clk50;
+
+    // ----------PCIe Resets----------
+    assign npor = PCIE_RESET_N;
+    assign gxb_powerdown = ~ npor;
+    assign pll_powerdown = ~ npor;
+    
+    // ----------PCIe Clocks / PLLs----------
+    assign refclk = PCIE_REFCLK;
+    assign pld_clk = core_clk_out;
+    assign cal_blk_clk = reconfig_clk;
+
+    // ----------ALTGX----------
+    assign busy = busy_altgxb_reconfig;
+
+    // -------------------- BEGIN ALTERA IP INSTANTIATION  --------------------
+    ALTPLL50I50O125O250O ALTPLL50I50O125O250O_inst
+        (
+         // Outputs
+         .c0                               (clk50),
+         .c1                               (clk125),
+         .c2                               (clk250),
+         .locked                           (locked),
+         // Inputs
+         .inclk0                           (inclk0));
+
+    ALTGXPCIeGen1x8
+        altgx_inst
+            (
+             // Outputs
+             .busy                           (busy),
+             .reconfig_togxb                 (reconfig_togxb[3:0]),
+             // Inputs
+             .reconfig_clk                   (reconfig_clk),
+             .reconfig_fromgxb               (reconfig_fromgxb[33:0]));
+
+    PCIeGen1x8If64 
+        pcie_inst
+            (
+             // Outputs
+             .app_int_ack                      (app_int_ack),
+             .app_msi_ack                      (app_msi_ack),
+             .core_clk_out                     (core_clk_out),
+             .hotrst_exit                      (hotrst_exit),
+             .l2_exit                          (l2_exit),
+             .lane_act                         (lane_act[3:0]),
+             .lmi_ack                          (lmi_ack),
+             .lmi_dout                         (lmi_dout[31:0]),
+             .ltssm                            (ltssm[4:0]),
+             .rc_pll_locked                    (rc_pll_locked),
+             .reconfig_fromgxb                 (reconfig_fromgxb[33:0]),
+             .reset_status                     (reset_status),
+             .rx_st_bardec0                    (rx_st_bardec0[7:0]),
+             .rx_st_be0                        (rx_st_be0[7:0]),
+             .rx_st_data0                      (rx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+             .rx_st_eop0                       (rx_st_eop0),
+             .rx_st_err0                       (rx_st_err0),
+             .rx_st_sop0                       (rx_st_sop0),
+             .rx_st_valid0                     (rx_st_valid0),
+             .suc_spd_neg                      (suc_spd_neg),// Gen 2 successful
+             .tl_cfg_add                       (tl_cfg_add[3:0]), 
+             .tl_cfg_ctl                       (tl_cfg_ctl[31:0]),
+             .tl_cfg_ctl_wr                    (tl_cfg_ctl_wr),
+             .tl_cfg_sts                       (tl_cfg_sts[52:0]),
+             .tl_cfg_sts_wr                    (tl_cfg_sts_wr),
+             .ko_cpl_spc_vc0                   (ko_cpl_spc_vc0),
+             .tx_out0                          (PCIE_TX_OUT[0]),
+             .tx_out1                          (PCIE_TX_OUT[1]),
+             .tx_out2                          (PCIE_TX_OUT[2]),
+             .tx_out3                          (PCIE_TX_OUT[3]),
+             .tx_out4                          (PCIE_TX_OUT[4]),
+             .tx_out5                          (PCIE_TX_OUT[5]),
+             .tx_out6                          (PCIE_TX_OUT[6]),
+             .tx_out7                          (PCIE_TX_OUT[7]),
+             .tx_st_ready0                     (tx_st_ready0),
+             // Inputs
+             .app_int_sts                      (app_int_sts),
+             .app_msi_num                      (5'b00000),
+             .app_msi_req                      (app_msi_req),
+             .app_msi_tc                       (3'b000),
+             .busy_altgxb_reconfig             (busy_altgxb_reconfig),
+             .cal_blk_clk                      (cal_blk_clk),
+             .crst                             (crst),
+             .fixedclk_serdes                  (fixedclk_serdes),
+             .gxb_powerdown                    (gxb_powerdown),
+             .pll_powerdown                    (pll_powerdown),
+             .lmi_addr                         (lmi_addr[11:0]),
+             .lmi_din                          (lmi_din[31:0]),
+             .lmi_rden                         (lmi_rden),
+             .lmi_wren                         (lmi_wren),
+             .npor                             (npor),
+             .pex_msi_num                      (pex_msi_num[4:0]),
+             .pld_clk                          (pld_clk),
+             .reconfig_clk                     (reconfig_clk),
+             .reconfig_togxb                   (reconfig_togxb[3:0]),
+             .refclk                           (refclk),
+             .rx_in0                           (PCIE_RX_IN[0]),
+             .rx_in1                           (PCIE_RX_IN[1]),
+             .rx_in2                           (PCIE_RX_IN[2]),
+             .rx_in3                           (PCIE_RX_IN[3]),
+             .rx_in4                           (PCIE_RX_IN[4]),
+             .rx_in5                           (PCIE_RX_IN[5]),
+             .rx_in6                           (PCIE_RX_IN[6]),
+             .rx_in7                           (PCIE_RX_IN[7]),
+             .rx_st_ready0                     (rx_st_ready0),
+             .srst                             (srst),
+             .tx_st_data0                      (tx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+             .tx_st_eop0                       (tx_st_eop0),
+             .tx_st_err0                       (tx_st_err0),
+             .tx_st_sop0                       (tx_st_sop0),
+             .tx_st_valid0                     (tx_st_valid0));
+
+    // -------------------- END ALTERA IP INSTANTIATION  --------------------
+    // -------------------- BEGIN RIFFA INSTANTAION --------------------
+
+    // ----------RIFFA channel interface----------
+    wire [C_NUM_CHNL-1:0]        chnl_rx_clk;
+    wire [C_NUM_CHNL-1:0]        chnl_rx;
+    wire [C_NUM_CHNL-1:0]        chnl_rx_ack;
+    wire [C_NUM_CHNL-1:0]        chnl_rx_last;
+    wire [(C_NUM_CHNL*32)-1:0]   chnl_rx_len;
+    wire [(C_NUM_CHNL*31)-1:0]   chnl_rx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_ren;
+    
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_clk;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_last;
+    wire [(C_NUM_CHNL*32)-1:0]               chnl_tx_len;
+    wire [(C_NUM_CHNL*31)-1:0]               chnl_tx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_ren;
+
+    wire                                     chnl_reset;
+    wire                                     chnl_clk;
+    wire                                     rst_out;
+
+    assign chnl_clk = pld_clk;
+    assign chnl_reset = rst_out;
+    
+    riffa_wrapper_de4
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .RX_ST_READY                   (rx_st_ready0),
+         .TX_ST_DATA                    (tx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (tx_st_valid0[0:0]),
+         .TX_ST_EOP                     (tx_st_eop0[0:0]),
+         .TX_ST_SOP                     (tx_st_sop0[0:0]),
+         .TX_ST_EMPTY                   (tx_st_empty0[0:0]),
+         .APP_MSI_REQ                   (app_msi_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .RX_ST_DATA                    (rx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (rx_st_eop0[0:0]),
+         .RX_ST_SOP                     (rx_st_sop0[0:0]),
+         .RX_ST_VALID                   (rx_st_valid0[0:0]),
+         .RX_ST_EMPTY                   (rx_st_empty0[0:0]),
+         .TX_ST_READY                   (tx_st_ready0),
+         .TL_CFG_CTL                    (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (ko_cpl_spc_vc0[7:0]),
+         .KO_CPL_SPC_DATA               (ko_cpl_spc_vc0[19:8]),
+         .APP_MSI_ACK                   (app_msi_ack),
+         .PLD_CLK                       (pld_clk),
+         .RESET_STATUS                  (reset_status),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+
+    // --------------------  END RIFFA INSTANTAION --------------------
+    // --------------------  BEGIN USER CODE  --------------------
+    genvar                                   i;
+    generate
+        for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
+            // Instantiate and assign modules to RIFFA channels. Users should 
+            // replace the chnl_tester instantiation with their own core.
+            chnl_tester 
+                 #(
+                   .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                   )
+            chnl_tester_i
+                 (
+
+                  .CLK(chnl_clk),
+                  .RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
+                  // Rx interface
+                  .CHNL_RX_CLK(chnl_rx_clk[i]), 
+                  .CHNL_RX(chnl_rx[i]), 
+                  .CHNL_RX_ACK(chnl_rx_ack[i]), 
+                  .CHNL_RX_LAST(chnl_rx_last[i]), 
+                  .CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]), 
+                  .CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
+                  // Tx interface
+                  .CHNL_TX_CLK(chnl_tx_clk[i]), 
+                  .CHNL_TX(chnl_tx[i]), 
+                  .CHNL_TX_ACK(chnl_tx_ack[i]), 
+                  .CHNL_TX_LAST(chnl_tx_last[i]), 
+                  .CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]), 
+                  .CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
+                  );    
+        end
+    endgenerate
+    // --------------------  END USER CODE  --------------------
+endmodule // DE4_PCIe
diff --git a/fpga/altera/de4/DE4Gen1x8If64/ip/README.txt b/fpga/altera/de4/DE4Gen1x8If64/ip/README.txt
new file mode 100644
index 0000000..e69de29
diff --git a/fpga/altera/de4/DE4Gen1x8If64/prj/DE4Gen1x8If64.qpf b/fpga/altera/de4/DE4Gen1x8If64/prj/DE4Gen1x8If64.qpf
new file mode 100644
index 0000000..9297a3f
--- /dev/null
+++ b/fpga/altera/de4/DE4Gen1x8If64/prj/DE4Gen1x8If64.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 16:41:16  June 09, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:41:16  June 09, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "DE4Gen1x8If64"
diff --git a/fpga/altera/de4/DE4Gen1x8If64/prj/DE4Gen1x8If64.qsf b/fpga/altera/de4/DE4Gen1x8If64/prj/DE4Gen1x8If64.qsf
new file mode 100644
index 0000000..9acc045
--- /dev/null
+++ b/fpga/altera/de4/DE4Gen1x8If64/prj/DE4Gen1x8If64.qsf
@@ -0,0 +1,277 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 11:42:13  March 24, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		DE4Gen1x8If64_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Stratix IV"
+set_global_assignment -name DEVICE EP4SGX230KF40C2
+set_global_assignment -name TOP_LEVEL_ENTITY DE4Gen1x8If64
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:42:13  MARCH 24, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION "14.1.0 SP0.19"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+################################################################################
+# Oscillators & External Clocks
+################################################################################
+
+set_location_assignment PIN_AC35 -to OSC_50_BANK2
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK2
+set_location_assignment PIN_AV22 -to OSC_50_BANK3
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK3
+set_location_assignment PIN_AV19 -to OSC_50_BANK4
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK4
+set_location_assignment PIN_AC6 -to OSC_50_BANK5
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK5
+set_location_assignment PIN_AB6 -to OSC_50_BANK6
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK6
+
+################################################################################
+# LED's
+################################################################################
+
+set_location_assignment PIN_V28 -to LED[0]
+set_location_assignment PIN_W28 -to LED[1]
+set_location_assignment PIN_R29 -to LED[2]
+set_location_assignment PIN_P29 -to LED[3]
+set_location_assignment PIN_N29 -to LED[4]
+set_location_assignment PIN_M29 -to LED[5]
+set_location_assignment PIN_M30 -to LED[6]
+set_location_assignment PIN_N30 -to LED[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[*]
+
+################################################################################
+# PCIE Connections
+################################################################################
+
+set_location_assignment PIN_AN38 -to PCIE_REFCLK
+set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK
+set_instance_assignment -name INPUT_TERMINATION OFF -to PCIE_REFCLK
+
+set_location_assignment PIN_AN39 -to "PCIE_REFCLK(n)"
+
+set_location_assignment PIN_V30 -to PCIE_RESET_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_RESET_N
+
+################################################################################
+#PCIE RX_IN 0
+################################################################################
+set_location_assignment PIN_AU38 -to PCIE_RX_IN[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[0]
+################################################################################
+#PCIE RX_IN 1
+################################################################################
+set_location_assignment PIN_AR38 -to PCIE_RX_IN[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[1]
+################################################################################
+#PCIE RX_IN 2
+################################################################################
+set_location_assignment PIN_AJ38 -to PCIE_RX_IN[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[2]
+################################################################################
+#PCIE RX_IN 3
+################################################################################
+set_location_assignment PIN_AG38 -to PCIE_RX_IN[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[3]
+################################################################################
+#PCIE RX_IN 4
+################################################################################
+set_location_assignment PIN_AE38 -to PCIE_RX_IN[4]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[4]
+################################################################################
+#PCIE RX_IN 5
+################################################################################
+set_location_assignment PIN_AC38 -to PCIE_RX_IN[5]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[5]
+################################################################################
+#PCIE RX_IN 6
+################################################################################
+set_location_assignment PIN_U38 -to PCIE_RX_IN[6]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[6]
+################################################################################
+#PCIE RX_IN 7
+################################################################################
+set_location_assignment PIN_R38 -to PCIE_RX_IN[7]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[7]
+################################################################################
+#PCIE TX_OUT 0
+################################################################################
+set_location_assignment PIN_AT36 -to PCIE_TX_OUT[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[0]
+################################################################################
+#PCIE TX_OUT 1
+################################################################################
+set_location_assignment PIN_AP36 -to PCIE_TX_OUT[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[1]
+################################################################################
+#PCIE TX_OUT 2
+################################################################################
+set_location_assignment PIN_AH36 -to PCIE_TX_OUT[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[2]
+################################################################################
+#PCIE TX_OUT 3
+################################################################################
+set_location_assignment PIN_AF36 -to PCIE_TX_OUT[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[3]
+################################################################################
+#PCIE TX_OUT 4
+################################################################################
+set_location_assignment PIN_AD36 -to PCIE_TX_OUT[4]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[4]
+################################################################################
+#PCIE TX_OUT 5
+################################################################################
+set_location_assignment PIN_AB36 -to PCIE_TX_OUT[5]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[5]
+################################################################################
+#PCIE TX_OUT 6
+################################################################################
+set_location_assignment PIN_T36 -to PCIE_TX_OUT[6]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[6]
+################################################################################
+#PCIE TX_OUT 7
+################################################################################
+set_location_assignment PIN_P36 -to PCIE_TX_OUT[7]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[7]
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+
+set_global_assignment -name SDC_FILE ../constr/DE4Gen1x8If64.sdc
+set_global_assignment -name VERILOG_FILE ../hdl/DE4Gen1x8If64.v
+set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de4.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ohtb.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
+set_global_assignment -name QIP_FILE ../ip/ALTGXPCIeGen1x8.qip
+set_global_assignment -name QIP_FILE ../ip/ALTPLL50I50O125O250O.qip
+set_global_assignment -name QIP_FILE ../ip/PCIeGen1x8If64.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/fpga/altera/de4/DE4Gen2x8If128/bit/README.txt b/fpga/altera/de4/DE4Gen2x8If128/bit/README.txt
new file mode 100644
index 0000000..e69de29
diff --git a/fpga/altera/de4/DE4Gen2x8If128/constr/DE4Gen2x8If128.sdc b/fpga/altera/de4/DE4Gen2x8If128/constr/DE4Gen2x8If128.sdc
new file mode 100644
index 0000000..ff4e3ef
--- /dev/null
+++ b/fpga/altera/de4/DE4Gen2x8If128/constr/DE4Gen2x8If128.sdc
@@ -0,0 +1,65 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            DE4Gen2x8If128.sdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Synopsys Design Constraints for the DE4 board.
+# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+# Oscillator clk (50 MHz Input)
+create_clock -name OSCILLATOR_CLK -period 20 [get_ports {OSC_50_BANK2}]
+
+# Refclk (100 MHz differential input)
+create_clock -period "100 MHz" -name {refclk} [get_ports {PCIE_REFCLK}]
+
+# 50 MHZ PLL Clock
+create_generated_clock -name clk50 -source [get_ports {OSC_50_BANK2}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[0]}]
+
+# 125 MHZ PLL Clock
+create_generated_clock -name clk125 -multiply_by 5 -divide_by 2 -source [get_ports {OSC_50_BANK2}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[1]}]
+
+# 250 MHZ PLL Clock
+create_generated_clock -name clk250 -multiply_by 5 -source [get_ports {OSC_50_BANK2}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[2]}]
+
+derive_pll_clocks 
+derive_clock_uncertainty
+
+
+# Imported from IP Compiler user guide
+set_clock_groups -exclusive -group [get_clocks { refclk*clkout }] -group [get_clocks { *div0*coreclkout}]
+set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }] -group [get_clocks { *central_clk_div1* }]
+
diff --git a/fpga/altera/de4/DE4Gen2x8If128/hdl/DE4Gen2x8If128.v b/fpga/altera/de4/DE4Gen2x8If128/hdl/DE4Gen2x8If128.v
new file mode 100644
index 0000000..387e440
--- /dev/null
+++ b/fpga/altera/de4/DE4Gen2x8If128/hdl/DE4Gen2x8If128.v
@@ -0,0 +1,402 @@
+//----------------------------------------------------------------------------
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            DE4Gen2x8If128.v
+// Version:             
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Altera Stratix IV IP Compiler for PCI Express
+//                      module and the Terasic DE4 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`timescale 1ps / 1ps
+module DE4Gen2x8If128
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Quartus IP Library
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     input                    OSC_50_BANK2,
+     input                    OSC_50_BANK3,
+     input                    OSC_50_BANK4,
+     input                    OSC_50_BANK5,
+     input                    OSC_50_BANK6,
+     input                    PCIE_RESET_N,
+     input                    PCIE_REFCLK,
+     input [C_NUM_LANES-1:0]  PCIE_RX_IN,
+     output [C_NUM_LANES-1:0] PCIE_TX_OUT,
+     output [7:0]             LED
+     );
+
+    // ----------PLL Signals----------
+    wire                      clk50;
+    wire                      clk125;
+    wire                      clk250;
+    wire                      locked;
+    wire                      inclk0;
+
+    // ----------PCIe Core Signals----------
+    // ----------PCIe Clocks----------
+    wire                      pld_clk;
+    wire                      reconfig_clk;
+    wire                      core_clk_out;
+    wire                      fixedclk_serdes;
+    wire                      refclk;
+    wire                      rc_pll_locked;
+    wire                      cal_blk_clk;
+
+    // ----------PCIe Resets----------
+    wire                      pll_powerdown;
+    wire                      reset_status;
+    wire                      crst;
+    wire                      npor;
+    wire                      srst;
+    wire                      gxb_powerdown;
+
+    // ----------PCIe Transaction layer configuration ----------
+    wire [  3: 0]             tl_cfg_add;
+    wire [ 31: 0]             tl_cfg_ctl;
+    wire                      tl_cfg_ctl_wr;
+    wire [ 52: 0]             tl_cfg_sts;
+    wire                      tl_cfg_sts_wr;
+    wire [ 19: 0]             ko_cpl_spc_vc0;
+    // ----------PCIe Interrupt Interface----------
+    wire                      app_int_ack;
+    wire                      app_msi_ack;
+    wire                      app_int_sts;
+    wire                      app_msi_req;
+
+    // ----------PCIe Status Signals----------
+    wire                      hotrst_exit;
+    wire                      l2_exit;
+    wire                      dlup_exit;
+    wire [3:0]                lane_act;
+    wire [4:0]                ltssm;
+    wire                      pme_to_sr;
+    wire                      suc_spd_neg;
+
+    // ----------PCIe RX Interface----------
+    wire                      rx_st_mask0;
+    wire [  7: 0]             rx_st_bardec0;
+    wire [ 15: 0]             rx_st_be0;
+    wire [0:0]                rx_st_sop0;
+    wire [0:0]                rx_st_eop0;
+    wire [0:0]                rx_st_err0;
+    wire [0:0]                rx_st_valid0;
+    wire [0:0]                rx_st_empty0;
+    wire                      rx_st_ready0;
+    wire [C_PCI_DATA_WIDTH-1:0] rx_st_data0;
+
+    // ----------PCIe TX Interface----------
+    wire [0:0]                  tx_st_sop0;
+    wire [0:0]                  tx_st_eop0;
+    wire [0:0]                  tx_st_err0;
+    wire [0:0]                  tx_st_valid0;
+    wire [0:0]                  tx_st_empty0;
+    wire                        tx_st_ready0;
+    wire [C_PCI_DATA_WIDTH-1:0] tx_st_data0;
+
+    // ----------ALTGX Signals----------
+    wire                        busy;
+    wire                        busy_altgxb_reconfig;
+    wire [33:0]                 reconfig_fromgxb;
+    wire [3:0]                  reconfig_togxb;
+
+    // ----------Resets ----------
+    reg [4:0]                   rPCIRstCtr=0,_rPCIRstCtr=0;
+    reg [2:0]                   rRstSync=0,_rRstSync=0;
+    wire                        wSyncRst;
+    always @(*) begin
+        _rRstSync = {rRstSync[1:0], ~npor};
+        _rPCIRstCtr = rPCIRstCtr;
+        if (rRstSync[2]) begin
+            _rPCIRstCtr = 0;
+        end else if (~rPCIRstCtr[4]) begin
+            _rPCIRstCtr = rPCIRstCtr + 1;
+        end
+    end
+    
+    always @(posedge pld_clk) begin
+        rRstSync <= _rRstSync;
+        rPCIRstCtr <= _rPCIRstCtr;
+    end
+
+    assign wSyncRst = ~ rPCIRstCtr[4];
+    assign srst = wSyncRst;
+    assign crst = wSyncRst;
+    
+    // ----------PLL assignments----------
+    assign inclk0 = OSC_50_BANK2;
+    assign fixedclk_serdes = clk125;
+    assign reconfig_clk = clk50;
+
+    // ----------PCIe Resets----------
+    assign npor = PCIE_RESET_N;
+    assign gxb_powerdown = ~ npor;
+    assign pll_powerdown = ~ npor;
+    
+    // ----------PCIe Clocks / PLLs----------
+    assign refclk = PCIE_REFCLK;
+    assign pld_clk = core_clk_out;
+    assign cal_blk_clk = reconfig_clk;
+
+    // ----------ALTGX----------
+    assign busy = busy_altgxb_reconfig;
+
+    // -------------------- BEGIN ALTERA IP INSTANTIATION  --------------------
+    ALTPLL50I50O125O250O ALTPLL50I50O125O250O_inst
+        (
+         // Outputs
+         .c0                               (clk50),
+         .c1                               (clk125),
+         .c2                               (clk250),
+         .locked                           (locked),
+         // Inputs
+         .inclk0                           (inclk0));
+
+    ALTGXPCIeGen2x8
+        altgx_inst
+            (
+             // Outputs
+             .busy                           (busy),
+             .reconfig_togxb                 (reconfig_togxb[3:0]),
+             // Inputs
+             .reconfig_clk                   (reconfig_clk),
+             .reconfig_fromgxb               (reconfig_fromgxb[33:0]));
+
+    PCIeGen2x8If128
+        pcie_inst
+            (
+             // Outputs
+             .app_int_ack                      (app_int_ack),
+             .app_msi_ack                      (app_msi_ack),
+             .core_clk_out                     (core_clk_out),
+             .hotrst_exit                      (hotrst_exit),
+             .l2_exit                          (l2_exit),
+             .dlup_exit                        (dlup_exit),
+             .lane_act                         (lane_act[3:0]),
+             .ltssm                            (ltssm[4:0]),
+             .rc_pll_locked                    (rc_pll_locked),
+             .reconfig_fromgxb                 (reconfig_fromgxb[33:0]),
+             .reset_status                     (reset_status),
+             .rx_st_bardec0                    (rx_st_bardec0[7:0]),
+             .rx_st_be0                        (rx_st_be0[7:0]),
+             .rx_st_data0                      (rx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+             .rx_st_eop0                       (rx_st_eop0),
+             .rx_st_err0                       (rx_st_err0),
+             .rx_st_sop0                       (rx_st_sop0),
+             .rx_st_empty0                     (rx_st_empty0),
+             .rx_st_valid0                     (rx_st_valid0),
+             .suc_spd_neg                      (suc_spd_neg),// Gen 2 successful
+             .tl_cfg_add                       (tl_cfg_add[3:0]), 
+             .tl_cfg_ctl                       (tl_cfg_ctl[31:0]),
+             .tl_cfg_ctl_wr                    (tl_cfg_ctl_wr),
+             .tl_cfg_sts                       (tl_cfg_sts[52:0]),
+             .tl_cfg_sts_wr                    (tl_cfg_sts_wr),
+             .ko_cpl_spc_vc0                   (ko_cpl_spc_vc0),
+             .tx_out0                          (PCIE_TX_OUT[0]),
+             .tx_out1                          (PCIE_TX_OUT[1]),
+             .tx_out2                          (PCIE_TX_OUT[2]),
+             .tx_out3                          (PCIE_TX_OUT[3]),
+             .tx_out4                          (PCIE_TX_OUT[4]),
+             .tx_out5                          (PCIE_TX_OUT[5]),
+             .tx_out6                          (PCIE_TX_OUT[6]),
+             .tx_out7                          (PCIE_TX_OUT[7]),
+             .tx_st_ready0                     (tx_st_ready0),
+             // Inputs
+             .app_int_sts                      (app_int_sts),
+             .app_msi_req                      (app_msi_req),
+             .busy_altgxb_reconfig             (busy_altgxb_reconfig),
+             .cal_blk_clk                      (cal_blk_clk),
+             .crst                             (crst),
+             .fixedclk_serdes                  (fixedclk_serdes),
+             .gxb_powerdown                    (gxb_powerdown),
+             .pll_powerdown                    (pll_powerdown),
+             .npor                             (npor),
+             .pld_clk                          (pld_clk),
+             .reconfig_clk                     (reconfig_clk),
+             .reconfig_togxb                   (reconfig_togxb[3:0]),
+             .refclk                           (refclk),
+             .rx_in0                           (PCIE_RX_IN[0]),
+             .rx_in1                           (PCIE_RX_IN[1]),
+             .rx_in2                           (PCIE_RX_IN[2]),
+             .rx_in3                           (PCIE_RX_IN[3]),
+             .rx_in4                           (PCIE_RX_IN[4]),
+             .rx_in5                           (PCIE_RX_IN[5]),
+             .rx_in6                           (PCIE_RX_IN[6]),
+             .rx_in7                           (PCIE_RX_IN[7]),
+             .rx_st_ready0                     (rx_st_ready0),
+             .srst                             (srst),
+             .tx_st_data0                      (tx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+             .tx_st_eop0                       (tx_st_eop0),
+             .tx_st_err0                       (1'b0),
+             .tx_st_sop0                       (tx_st_sop0),
+             .tx_st_empty0                     (tx_st_empty0),
+             .tx_st_valid0                     (tx_st_valid0));
+
+    // -------------------- END ALTERA IP INSTANTIATION  --------------------
+    // -------------------- BEGIN RIFFA INSTANTAION --------------------
+
+    // ----------RIFFA channel interface----------
+    wire [C_NUM_CHNL-1:0]        chnl_rx_clk;
+    wire [C_NUM_CHNL-1:0]        chnl_rx;
+    wire [C_NUM_CHNL-1:0]        chnl_rx_ack;
+    wire [C_NUM_CHNL-1:0]        chnl_rx_last;
+    wire [(C_NUM_CHNL*32)-1:0]   chnl_rx_len;
+    wire [(C_NUM_CHNL*31)-1:0]   chnl_rx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_ren;
+    
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_clk;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_last;
+    wire [(C_NUM_CHNL*32)-1:0]               chnl_tx_len;
+    wire [(C_NUM_CHNL*31)-1:0]               chnl_tx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_ren;
+
+    wire                                     chnl_reset;
+    wire                                     chnl_clk;
+    wire                                     rst_out;
+
+    assign chnl_clk = pld_clk;
+    assign chnl_reset = rst_out;
+    
+    riffa_wrapper_de4
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .RX_ST_READY                   (rx_st_ready0),
+         .TX_ST_DATA                    (tx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (tx_st_valid0[0:0]),
+         .TX_ST_EOP                     (tx_st_eop0[0:0]),
+         .TX_ST_SOP                     (tx_st_sop0[0:0]),
+         .TX_ST_EMPTY                   (tx_st_empty0[0:0]),
+         .APP_MSI_REQ                   (app_msi_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .RX_ST_DATA                    (rx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (rx_st_eop0[0:0]),
+         .RX_ST_SOP                     (rx_st_sop0[0:0]),
+         .RX_ST_VALID                   (rx_st_valid0[0:0]),
+         .RX_ST_EMPTY                   (rx_st_empty0[0:0]),
+         .TX_ST_READY                   (tx_st_ready0),
+         .TL_CFG_CTL                    (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER                (ko_cpl_spc_vc0[7:0]),
+         .KO_CPL_SPC_DATA                  (ko_cpl_spc_vc0[19:8]),
+         .APP_MSI_ACK                   (app_msi_ack),
+         .PLD_CLK                       (pld_clk),
+         .RESET_STATUS                  (reset_status),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+    
+    // --------------------  END RIFFA INSTANTAION --------------------
+    // --------------------  BEGIN USER CODE  --------------------
+    genvar                                   i;
+    generate
+        for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
+            // Instantiate and assign modules to RIFFA channels. Users should 
+            // replace the chnl_tester instantiation with their own core.
+            chnl_tester 
+                 #(
+                   .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                   )
+            chnl_tester_i
+                 (
+
+                  .CLK(chnl_clk),
+                  .RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
+                  // Rx interface
+                  .CHNL_RX_CLK(chnl_rx_clk[i]), 
+                  .CHNL_RX(chnl_rx[i]), 
+                  .CHNL_RX_ACK(chnl_rx_ack[i]), 
+                  .CHNL_RX_LAST(chnl_rx_last[i]), 
+                  .CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]), 
+                  .CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
+                  // Tx interface
+                  .CHNL_TX_CLK(chnl_tx_clk[i]), 
+                  .CHNL_TX(chnl_tx[i]), 
+                  .CHNL_TX_ACK(chnl_tx_ack[i]), 
+                  .CHNL_TX_LAST(chnl_tx_last[i]), 
+                  .CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]), 
+                  .CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
+                  );    
+        end
+    endgenerate
+    // --------------------  END USER CODE  --------------------
+endmodule // DE4Gen2x8If128
+
diff --git a/fpga/altera/de4/DE4Gen2x8If128/ip/README.txt b/fpga/altera/de4/DE4Gen2x8If128/ip/README.txt
new file mode 100644
index 0000000..e69de29
diff --git a/fpga/altera/de4/DE4Gen2x8If128/prj/DE4Gen2x8If128.qpf b/fpga/altera/de4/DE4Gen2x8If128/prj/DE4Gen2x8If128.qpf
new file mode 100644
index 0000000..45c54c7
--- /dev/null
+++ b/fpga/altera/de4/DE4Gen2x8If128/prj/DE4Gen2x8If128.qpf
@@ -0,0 +1,32 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.0.0 Build 200 06/17/2014 SJ Full Version
+# Date created = 14:57:09  July 21, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "14.0"
+DATE = "14:57:09  July 21, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "DE4Gen2x8If128"
+PROJECT_REVISION = "WAR"
diff --git a/fpga/altera/de4/DE4Gen2x8If128/prj/DE4Gen2x8If128.qsf b/fpga/altera/de4/DE4Gen2x8If128/prj/DE4Gen2x8If128.qsf
new file mode 100644
index 0000000..84445c7
--- /dev/null
+++ b/fpga/altera/de4/DE4Gen2x8If128/prj/DE4Gen2x8If128.qsf
@@ -0,0 +1,275 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 11:42:13  March 24, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		DE4Gen2x8If128_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Stratix IV"
+set_global_assignment -name DEVICE EP4SGX230KF40C2
+set_global_assignment -name TOP_LEVEL_ENTITY DE4Gen2x8If128
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:42:13  MARCH 24, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION "14.1.0 SP0.19"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+################################################################################
+# Oscillators & External Clocks
+################################################################################
+
+set_location_assignment PIN_AC35 -to OSC_50_BANK2
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK2
+set_location_assignment PIN_AV22 -to OSC_50_BANK3
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK3
+set_location_assignment PIN_AV19 -to OSC_50_BANK4
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK4
+set_location_assignment PIN_AC6 -to OSC_50_BANK5
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK5
+set_location_assignment PIN_AB6 -to OSC_50_BANK6
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK6
+################################################################################
+# LED's
+################################################################################
+
+set_location_assignment PIN_V28 -to LED[0]
+set_location_assignment PIN_W28 -to LED[1]
+set_location_assignment PIN_R29 -to LED[2]
+set_location_assignment PIN_P29 -to LED[3]
+set_location_assignment PIN_N29 -to LED[4]
+set_location_assignment PIN_M29 -to LED[5]
+set_location_assignment PIN_M30 -to LED[6]
+set_location_assignment PIN_N30 -to LED[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[*]
+
+################################################################################
+# PCIE Connections
+################################################################################
+
+
+set_location_assignment PIN_AN38 -to PCIE_REFCLK
+set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK
+set_instance_assignment -name INPUT_TERMINATION OFF -to PCIE_REFCLK
+
+set_location_assignment PIN_AN39 -to "PCIE_REFCLK(n)"
+
+set_location_assignment PIN_V30 -to PCIE_RESET_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_RESET_N
+
+################################################################################
+#PCIE RX_IN 0
+################################################################################
+set_location_assignment PIN_AU38 -to PCIE_RX_IN[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[0]
+################################################################################
+#PCIE RX_IN 1
+################################################################################
+set_location_assignment PIN_AR38 -to PCIE_RX_IN[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[1]
+################################################################################
+#PCIE RX_IN 2
+################################################################################
+set_location_assignment PIN_AJ38 -to PCIE_RX_IN[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[2]
+################################################################################
+#PCIE RX_IN 3
+################################################################################
+set_location_assignment PIN_AG38 -to PCIE_RX_IN[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[3]
+################################################################################
+#PCIE RX_IN 4
+################################################################################
+set_location_assignment PIN_AE38 -to PCIE_RX_IN[4]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[4]
+################################################################################
+#PCIE RX_IN 5
+################################################################################
+set_location_assignment PIN_AC38 -to PCIE_RX_IN[5]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[5]
+################################################################################
+#PCIE RX_IN 6
+################################################################################
+set_location_assignment PIN_U38 -to PCIE_RX_IN[6]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[6]
+################################################################################
+#PCIE RX_IN 7
+################################################################################
+set_location_assignment PIN_R38 -to PCIE_RX_IN[7]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[7]
+################################################################################
+#PCIE TX_OUT 0
+################################################################################
+set_location_assignment PIN_AT36 -to PCIE_TX_OUT[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[0]
+################################################################################
+#PCIE TX_OUT 1
+################################################################################
+set_location_assignment PIN_AP36 -to PCIE_TX_OUT[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[1]
+################################################################################
+#PCIE TX_OUT 2
+################################################################################
+set_location_assignment PIN_AH36 -to PCIE_TX_OUT[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[2]
+################################################################################
+#PCIE TX_OUT 3
+################################################################################
+set_location_assignment PIN_AF36 -to PCIE_TX_OUT[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[3]
+################################################################################
+#PCIE TX_OUT 4
+################################################################################
+set_location_assignment PIN_AD36 -to PCIE_TX_OUT[4]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[4]
+################################################################################
+#PCIE TX_OUT 5
+################################################################################
+set_location_assignment PIN_AB36 -to PCIE_TX_OUT[5]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[5]
+################################################################################
+#PCIE TX_OUT 6
+################################################################################
+set_location_assignment PIN_T36 -to PCIE_TX_OUT[6]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[6]
+################################################################################
+#PCIE TX_OUT 7
+################################################################################
+set_location_assignment PIN_P36 -to PCIE_TX_OUT[7]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[7]
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name SDC_FILE ../constr/DE4Gen2x8If128.sdc
+set_global_assignment -name VERILOG_FILE ../hdl/DE4Gen2x8If128.v
+set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de4.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ohtb.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
+set_global_assignment -name QIP_FILE ../ip/ALTGXPCIeGen2x8.qip
+set_global_assignment -name QIP_FILE ../ip/ALTPLL50I50O125O250O.qip
+set_global_assignment -name QIP_FILE ../ip/PCIeGen2x8If128.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/fpga/altera/de4/riffa_wrapper_de4.v b/fpga/altera/de4/riffa_wrapper_de4.v
new file mode 100644
index 0000000..d29a3b6
--- /dev/null
+++ b/fpga/altera/de4/riffa_wrapper_de4.v
@@ -0,0 +1,615 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            riffa_wrapper_de4.v
+// Version:             1.00a
+// Verilog Standard:    Verilog-2001
+// Description:         Wrapper file for all riffa logic for Altera DE4 boards
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`include "ultrascale.vh"
+`include "functions.vh"
+`timescale 1ps / 1ps
+module riffa_wrapper_de4
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Bit-Width from Quartus IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     // Interface: Altera RX 
+     input [C_PCI_DATA_WIDTH-1:0]                 RX_ST_DATA,
+     input [0:0]                                  RX_ST_EOP,
+     input [0:0]                                  RX_ST_SOP,
+     input [0:0]                                  RX_ST_VALID,
+     output                                       RX_ST_READY,
+     input [0:0]                                  RX_ST_EMPTY,
+
+     // Interface: Altera TX
+     output [C_PCI_DATA_WIDTH-1:0]                TX_ST_DATA,
+     output [0:0]                                 TX_ST_VALID,
+     input                                        TX_ST_READY,
+     output [0:0]                                 TX_ST_EOP,
+     output [0:0]                                 TX_ST_SOP,
+     output [0:0]                                 TX_ST_EMPTY,
+
+     // Interface: Altera Config
+     input [`SIG_CFG_CTL_W-1:0]                   TL_CFG_CTL,
+     input [`SIG_CFG_ADD_W-1:0]                   TL_CFG_ADD,
+     input [`SIG_CFG_STS_W-1:0]                   TL_CFG_STS,
+
+     // Interface: Altera Flow Control
+     input [`SIG_KO_CPLH_W-1:0]                   KO_CPL_SPC_HEADER,
+     input [`SIG_KO_CPLD_W-1:0]                   KO_CPL_SPC_DATA,
+    
+     // Interface: Altera Interrupt
+     input                                        APP_MSI_ACK,
+     output                                       APP_MSI_REQ,
+
+     // Interface: Altera CLK/RESET
+     input                                        PLD_CLK,
+     input                                        RESET_STATUS,
+    
+
+     // RIFFA Interface Signals
+     output                                       RST_OUT,
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_CLK, // Channel read clock
+     output [C_NUM_CHNL-1:0]                      CHNL_RX, // Channel read receive signal
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_ACK, // Channel read received signal
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_LAST, // Channel last read
+     output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
+     output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
+     output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   CHNL_RX_DATA, // Channel read data
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_DATA_VALID, // Channel read data valid
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_DATA_REN, // Channel read data has been recieved
+
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_CLK, // Channel write clock
+     input [C_NUM_CHNL-1:0]                       CHNL_TX, // Channel write receive signal
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_ACK, // Channel write acknowledgement signal
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_LAST, // Channel last write
+     input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]  CHNL_TX_LEN, // Channel write length (in 32 bit words)
+     input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]  CHNL_TX_OFF, // Channel write offset
+     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]    CHNL_TX_DATA, // Channel write data
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_DATA_VALID, // Channel write data valid
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_DATA_REN // Channel write data has been recieved
+
+     );
+    localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
+    localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
+    localparam C_VENDOR = "ALTERA";
+
+    localparam C_ALTERA_TX_READY_LATENCY = 2;
+    localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
+    localparam C_PIPELINE_OUTPUT = 1;
+    localparam C_PIPELINE_INPUT = 1;
+
+    wire                                          clk;
+    wire                                          rst_in;
+
+    // Interface: RXC Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxc_data;
+    wire                                          rxc_data_valid;
+    wire                                          rxc_data_start_flag;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxc_data_word_enable;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxc_meta_fdwbe;
+    wire                                          rxc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxc_meta_ldwbe;
+    wire [`SIG_TAG_W-1:0]                         rxc_meta_tag;
+    wire [`SIG_LOWADDR_W-1:0]                     rxc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        rxc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         rxc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     rxc_meta_bytes_remaining;
+    wire [`SIG_CPLID_W-1:0]                       rxc_meta_completer_id;
+    wire                                          rxc_meta_ep;
+
+    // Interface: RXR Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxr_data;
+    wire                                          rxr_data_valid;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxr_data_word_enable;
+    wire                                          rxr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxr_meta_fdwbe;
+    wire                                          rxr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxr_meta_ldwbe;
+    wire [`SIG_TC_W-1:0]                          rxr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        rxr_meta_attr;
+    wire [`SIG_TAG_W-1:0]                         rxr_meta_tag;
+    wire [`SIG_TYPE_W-1:0]                        rxr_meta_type;
+    wire [`SIG_ADDR_W-1:0]                        rxr_meta_addr;
+    wire [`SIG_BARDECODE_W-1:0]                   rxr_meta_bar_decoded;
+    wire [`SIG_REQID_W-1:0]                       rxr_meta_requester_id;
+    wire [`SIG_LEN_W-1:0]                         rxr_meta_length;
+    wire                                          rxr_meta_ep;
+    
+    // interface: TXC Engine
+    wire                                          txc_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txc_data;
+    wire                                          txc_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_start_offset;
+    wire                                          txc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_end_offset;
+    wire                                          txc_data_ready;
+
+    wire                                          txc_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txc_meta_fdwbe;
+    wire [`SIG_LBE_W-1:0]                         txc_meta_ldwbe;
+    wire [`SIG_LOWADDR_W-1:0]                     txc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        txc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         txc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     txc_meta_byte_count;
+    wire [`SIG_TAG_W-1:0]                         txc_meta_tag;
+    wire [`SIG_REQID_W-1:0]                       txc_meta_requester_id;
+    wire [`SIG_TC_W-1:0]                          txc_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txc_meta_attr;
+    wire                                          txc_meta_ep;
+    wire                                          txc_meta_ready;
+    wire                                          txc_sent;
+
+    // Interface: TXR Engine
+    wire                                          txr_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txr_data;
+    wire                                          txr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_start_offset;
+    wire                                          txr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_end_offset;
+    wire                                          txr_data_ready;
+
+    wire                                          txr_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txr_meta_fdwbe; 
+    wire [`SIG_LBE_W-1:0]                         txr_meta_ldwbe;
+    wire [`SIG_ADDR_W-1:0]                        txr_meta_addr;
+    wire [`SIG_LEN_W-1:0]                         txr_meta_length;
+    wire [`SIG_TAG_W-1:0]                         txr_meta_tag;
+    wire [`SIG_TC_W-1:0]                          txr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txr_meta_attr;
+    wire [`SIG_TYPE_W-1:0]                        txr_meta_type;
+    wire                                          txr_meta_ep;
+    wire                                          txr_meta_ready;
+    wire                                          txr_sent;
+
+    // Classic Interface Wires
+    wire                                          wRxTlpReady;
+    wire [C_PCI_DATA_WIDTH-1:0]                   wRxTlp;
+    wire                                          wRxTlpEndFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wRxTlpEndOffset;
+    wire                                          wRxTlpStartFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wRxTlpStartOffset;
+    wire                                          wRxTlpValid;
+    wire [`SIG_BARDECODE_W-1:0]                   wRxTlpBarDecode;
+    
+    wire                                          wTxTlpReady;
+    wire [C_PCI_DATA_WIDTH-1:0]                   wTxTlp;
+    wire                                          wTxTlpEndFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wTxTlpEndOffset;
+    wire                                          wTxTlpStartFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wTxTlpStartOffset;
+    wire                                          wTxTlpValid;
+    
+    // Unconnected Wires (Used in ultrascale interface)
+    // Interface: RQ (TXC)
+    wire                                          s_axis_rq_tlast_nc;
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_rq_tdata_nc;
+    wire [`SIG_RQ_TUSER_W-1:0]                    s_axis_rq_tuser_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_rq_tkeep_nc;
+    wire                                          s_axis_rq_tready_nc = 0;
+    wire                                          s_axis_rq_tvalid_nc;
+    // Interface: RC (RXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_rc_tdata_nc = 0;
+    wire [`SIG_RC_TUSER_W-1:0]                    m_axis_rc_tuser_nc = 0;
+    wire                                          m_axis_rc_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_rc_tkeep_nc = 0;
+    wire                                          m_axis_rc_tvalid_nc = 0;
+    wire                                          m_axis_rc_tready_nc;
+    // Interface: CQ (RXR)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_cq_tdata_nc = 0;
+    wire [`SIG_CQ_TUSER_W-1:0]                    m_axis_cq_tuser_nc = 0;
+    wire                                          m_axis_cq_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_cq_tkeep_nc = 0;
+    wire                                          m_axis_cq_tvalid_nc = 0;
+    wire                                          m_axis_cq_tready_nc = 0;
+    // Interface: CC (TXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_cc_tdata_nc;
+    wire [`SIG_CC_TUSER_W-1:0]                    s_axis_cc_tuser_nc;
+    wire                                          s_axis_cc_tlast_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_cc_tkeep_nc;
+    wire                                          s_axis_cc_tvalid_nc;
+    wire                                          s_axis_cc_tready_nc = 0;
+
+    // Interface: Configuration
+    wire                                          config_bus_master_enable;
+    wire [`SIG_CPLID_W-1:0]                       config_completer_id;
+    wire                                          config_cpl_boundary_sel;
+    wire                                          config_interrupt_msienable;
+    wire [`SIG_LINKRATE_W-1:0]                    config_link_rate;
+    wire [`SIG_LINKWIDTH_W-1:0]                   config_link_width;
+    wire [`SIG_MAXPAYLOAD_W-1:0]                  config_max_payload_size;
+    wire [`SIG_MAXREAD_W-1:0]                     config_max_read_request_size;
+    wire [`SIG_FC_CPLD_W-1:0]                     config_max_cpl_data;
+    wire [`SIG_FC_CPLH_W-1:0]                     config_max_cpl_hdr;
+
+    wire                                          intr_msi_request;
+    wire                                          intr_msi_rdy;
+
+    genvar                                        chnl;
+
+    assign clk = PLD_CLK;
+    assign rst_in = RESET_STATUS;
+
+    translation_altera
+        #(
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH))
+    trans
+        (
+         // Outputs
+         .RX_TLP                            (wRxTlp[C_PCI_DATA_WIDTH-1:0]),
+         .RX_TLP_VALID                      (wRxTlpValid),
+         .RX_TLP_START_FLAG                 (wRxTlpStartFlag),
+         .RX_TLP_START_OFFSET               (wRxTlpStartOffset[`SIG_OFFSET_W-1:0]),
+         .RX_TLP_END_FLAG                   (wRxTlpEndFlag),
+         .RX_TLP_END_OFFSET                 (wRxTlpEndOffset[`SIG_OFFSET_W-1:0]),
+         .RX_TLP_BAR_DECODE                 (wRxTlpBarDecode[`SIG_BARDECODE_W-1:0]),
+         .TX_TLP_READY                      (wTxTlpReady),
+         .CONFIG_COMPLETER_ID               (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE          (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH                 (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE                  (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE      (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE           (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE        (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL           (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA               (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR                (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+         .INTR_MSI_RDY                      (intr_msi_rdy),
+         // Inputs
+         .CLK                               (clk),
+         .RST_IN                            (rst_in),
+         .RX_TLP_READY                      (wRxTlpReady),
+         .TX_TLP                            (wTxTlp[C_PCI_DATA_WIDTH-1:0]),
+         .TX_TLP_VALID                      (wTxTlpValid),
+         .TX_TLP_START_FLAG                 (wTxTlpStartFlag),
+         .TX_TLP_START_OFFSET               (wTxTlpStartOffset[`SIG_OFFSET_W-1:0]),
+         .TX_TLP_END_FLAG                   (wTxTlpEndFlag),
+         .TX_TLP_END_OFFSET                 (wTxTlpEndOffset[`SIG_OFFSET_W-1:0]),
+         .INTR_MSI_REQUEST                  (intr_msi_request),
+         /*AUTOINST*/
+         // Outputs
+         .RX_ST_READY                   (RX_ST_READY),
+         .TX_ST_DATA                    (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (TX_ST_VALID[0:0]),
+         .TX_ST_EOP                     (TX_ST_EOP[0:0]),
+         .TX_ST_SOP                     (TX_ST_SOP[0:0]),
+         .TX_ST_EMPTY                   (TX_ST_EMPTY[0:0]),
+         .APP_MSI_REQ                   (APP_MSI_REQ),
+         // Inputs
+         .RX_ST_DATA                    (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (RX_ST_EOP[0:0]),
+         .RX_ST_SOP                     (RX_ST_SOP[0:0]),
+         .RX_ST_VALID                   (RX_ST_VALID[0:0]),
+         .RX_ST_EMPTY                   (RX_ST_EMPTY[0:0]),
+         .TX_ST_READY                   (TX_ST_READY),
+         .TL_CFG_CTL                    (TL_CFG_CTL[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (TL_CFG_ADD[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (TL_CFG_STS[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (KO_CPL_SPC_HEADER[`SIG_FC_CPLH_W-1:0]),
+         .KO_CPL_SPC_DATA               (KO_CPL_SPC_DATA[`SIG_FC_CPLD_W-1:0]),
+         .APP_MSI_ACK                   (APP_MSI_ACK));
+
+    engine_layer
+        #(// Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_BYTES/4),
+          .C_VENDOR                     (C_VENDOR))
+    engine_layer_inst
+        (// Outputs
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+         // Unconnected Outputs
+         .TX_TLP                        (wTxTlp),
+         .TX_TLP_VALID                  (wTxTlpValid),
+         .TX_TLP_START_FLAG             (wTxTlpStartFlag),
+         .TX_TLP_START_OFFSET           (wTxTlpStartOffset),
+         .TX_TLP_END_FLAG               (wTxTlpEndFlag),
+         .TX_TLP_END_OFFSET             (wTxTlpEndOffset),
+
+         .RX_TLP_READY                  (wRxTlpReady),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+         // Unconnected Inputs
+         .RX_TLP                        (wRxTlp),
+         .RX_TLP_VALID                  (wRxTlpValid),
+         .RX_TLP_START_FLAG             (wRxTlpStartFlag),
+         .RX_TLP_START_OFFSET           (wRxTlpStartOffset),
+         .RX_TLP_END_FLAG               (wRxTlpEndFlag),
+         .RX_TLP_END_OFFSET             (wRxTlpEndOffset),
+         .RX_TLP_BAR_DECODE             (wRxTlpBarDecode),
+
+         .TX_TLP_READY                  (wTxTlpReady),
+         // Outputs
+         .M_AXIS_CQ_TREADY              (m_axis_cq_tready_nc),
+         .M_AXIS_RC_TREADY              (m_axis_rc_tready_nc),
+         .S_AXIS_CC_TVALID              (s_axis_cc_tvalid_nc),
+         .S_AXIS_CC_TLAST               (s_axis_cc_tlast_nc),
+         .S_AXIS_CC_TDATA               (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (s_axis_rq_tvalid_nc),
+         .S_AXIS_RQ_TLAST               (s_axis_rq_tlast_nc),
+         .S_AXIS_RQ_TDATA               (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (m_axis_cq_tvalid_nc),
+         .M_AXIS_CQ_TLAST               (m_axis_cq_tlast_nc),
+         .M_AXIS_CQ_TDATA               (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (m_axis_rc_tvalid_nc),
+         .M_AXIS_RC_TLAST               (m_axis_rc_tlast_nc),
+         .M_AXIS_RC_TDATA               (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (s_axis_cc_tready_nc),
+         .S_AXIS_RQ_TREADY              (s_axis_rq_tready_nc)
+         /*AUTOINST*/);
+
+    riffa
+        #(.C_TAG_WIDTH                  (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_MAX_READ_REQ_BYTES         (C_MAX_READ_REQ_BYTES),
+          .C_VENDOR                     (C_VENDOR),
+          .C_FPGA_NAME                  (C_FPGA_NAME))
+    riffa_inst
+        (// Outputs
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+
+         .INTR_MSI_REQUEST              (intr_msi_request),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),         
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE      (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH             (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE              (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE  (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE       (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE    (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL       (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA           (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR            (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+        
+         .INTR_MSI_RDY                  (intr_msi_rdy),
+
+         /*AUTOINST*/
+         // Outputs
+         .RST_OUT                       (RST_OUT),
+         .CHNL_RX                       (CHNL_RX[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_RX_OFF                   (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_RX_DATA                  (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
+         // Inputs
+         .CHNL_RX_CLK                   (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (CHNL_TX[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_TX_OFF                   (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_TX_DATA                  (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("../../engine/" "../../riffa/" "../../trans")
+// End:
+
diff --git a/fpga/altera/de5/DE5Gen1x8If64/bit/DE5Gen1x8If64.sof b/fpga/altera/de5/DE5Gen1x8If64/bit/DE5Gen1x8If64.sof
new file mode 100644
index 0000000..8b379b7
Binary files /dev/null and b/fpga/altera/de5/DE5Gen1x8If64/bit/DE5Gen1x8If64.sof differ
diff --git a/fpga/altera/de5/DE5Gen1x8If64/constr/DE5Gen1x8If64.sdc b/fpga/altera/de5/DE5Gen1x8If64/constr/DE5Gen1x8If64.sdc
new file mode 100644
index 0000000..99c37a4
--- /dev/null
+++ b/fpga/altera/de5/DE5Gen1x8If64/constr/DE5Gen1x8If64.sdc
@@ -0,0 +1,95 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            DE5Gen1x8If64.sdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Synopsys Design Constraints for the DE5 board.
+# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}]
+create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}]
+
+################################################################################
+# 13.1 Workround for http://www.altera.com/support/kdb/solutions/rd12162013_581.html?GSA_pos=1&WT.oss_r=1&WT.oss=adce_off_r
+################################################################################
+
+# set_false_path -to [get_registers *|*.adce_off_r[0]]
+# set_false_path -to [get_registers *|*.adce_on_rr[0]]
+# set_false_path -to [get_registers *|reset_sync_pldclk_r[*]]
+
+################################################################################
+# End Workround 
+################################################################################
+
+derive_pll_clocks -create_base_clocks
+derive_clock_uncertainty
+
+################################################################################
+# Imports from Example Design
+################################################################################
+
+######################################################################
+# HIP Soft reset controller SDC constraints (Gen 3 only)
+set_false_path -to   [get_registers *altpcie_rs_serdes|fifo_err_sync_r[0]]
+set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*]
+
+# HIP testin pins SDC constraints
+set_false_path -from [get_pins -compatibility_mode *hip_ctrl*]
+
+######################################################################
+# Constraints for CV SIG asynchonous logic
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|test_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqout[*]}]
+                                                                                                                                                
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqber[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_lf[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_fs[*]}]
\ No newline at end of file
diff --git a/fpga/altera/de5/DE5Gen1x8If64/hdl/DE5Gen1x8If64.v b/fpga/altera/de5/DE5Gen1x8If64/hdl/DE5Gen1x8If64.v
new file mode 100644
index 0000000..1d1badb
--- /dev/null
+++ b/fpga/altera/de5/DE5Gen1x8If64/hdl/DE5Gen1x8If64.v
@@ -0,0 +1,523 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            DE5Gen1x8If64
+// Version:             
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Altera Stratix V Hard IP for PCI Express
+//                      module and the Terasic DE5 net Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`timescale 1ps / 1ps
+module DE5Gen1x8If64
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Quartus IP Library
+      parameter C_PCI_DATA_WIDTH = 64,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      )
+    (
+     // ----------LEDs----------
+     output [7:0]             LED,
+
+     // ----------PCIE----------
+     input                    PCIE_RESET_N,
+     input                    PCIE_REFCLK,
+
+     // ----------PCIE Serial RX----------
+     input [C_NUM_LANES-1:0]  PCIE_RX_IN,
+
+     // ----------PCIE Serial TX----------
+     output [C_NUM_LANES-1:0] PCIE_TX_OUT,
+
+     // ----------Oscillators----------
+     input                    OSC_BANK3D_50MHZ
+     );
+
+    wire                      npor;
+    wire                      pin_perst;
+
+    // ----------LMI Interface----------
+    wire [11:0]               lmi_addr;
+    wire [31:0]               lmi_din;
+    wire                      lmi_rden;
+    wire                      lmi_wren;
+    wire                      lmi_ack;
+    wire [31:0]               lmi_dout;
+
+    // ----------TL Config interface----------
+    wire [3:0]                tl_cfg_add;
+    wire [31:0]               tl_cfg_ctl;
+    wire [52:0]               tl_cfg_sts;
+
+    // ----------Rx/TX Interfaces----------
+    wire [0:0]                rx_st_sop;
+    wire [0:0]                rx_st_eop;
+    wire [0:0]                rx_st_err;
+    wire [0:0]                rx_st_valid;
+    wire [0:0]                rx_st_empty;
+    wire                      rx_st_ready;
+    wire [63:0]               rx_st_data;
+
+    wire [7:0]                rx_st_bar;
+    wire                      rx_st_mask;
+
+    wire [0:0]                tx_st_sop;
+    wire [0:0]                tx_st_eop;
+    wire [0:0]                tx_st_err;
+    wire [0:0]                tx_st_valid;
+    wire [0:0]                tx_st_empty;
+    wire                      tx_st_ready;
+    wire [63:0]               tx_st_data;
+
+    // ----------Clocks----------
+    wire                      pld_clk;
+    wire                      coreclkout_hip;
+    wire                      refclk;
+    wire                      pld_core_ready;
+    wire                      reset_status;
+    wire                      serdes_pll_locked;
+    wire                      pld_clk_inuse;
+
+    // ----------Reconfiguration busses----------
+    wire [699:0]              reconfig_to_xcvr;
+    wire [505:0]              reconfig_from_xcvr;
+
+    // ----------Interrupt Interfaces----------
+    wire                      app_int_sts;
+    wire [4:0]                app_msi_num;
+    wire                      app_msi_req;
+    wire [2:0]                app_msi_tc;
+    wire                      app_int_ack;
+    wire                      app_msi_ack;
+
+    // ----------Link status signals----------
+    wire                      derr_cor_ext_rcv;
+    wire                      derr_cor_ext_rpl;
+    wire                      derr_rpl;
+    wire                      dlup;
+    wire                      dlup_exit;
+    wire                      ev128ns;
+    wire                      ev1us;
+    wire                      hotrst_exit;
+    wire [3:0]                int_status;
+    wire                      l2_exit;
+    wire [3:0]                lane_act;
+    wire [4:0]                ltssmstate;
+    wire                      rx_par_err;
+    wire [1:0]                tx_par_err;
+    wire                      cfg_par_err;
+    wire [1:0]                currentspeed;
+    wire [7:0]                ko_cpl_spc_header;
+    wire [11:0]               ko_cpl_spc_data;
+
+    // ----------Link Status Signals (Driver)----------
+    wire                      derr_cor_ext_rcv_drv;
+    wire                      derr_cor_ext_rpl_drv;
+    wire                      derr_rpl_drv;
+    wire                      dlup_drv;
+    wire                      dlup_exit_drv;
+    wire                      ev128ns_drv;
+    wire                      ev1us_drv;
+    wire                      hotrst_exit_drv;
+    wire [3:0]                int_status_drv;
+    wire                      l2_exit_drv;
+    wire [3:0]                lane_act_drv;
+    wire [4:0]                ltssmstate_drv;
+    wire                      rx_par_err_drv;
+    wire [1:0]                tx_par_err_drv;
+    wire                      cfg_par_err_drv;
+    wire [7:0]                ko_cpl_spc_header_drv;
+    wire [11:0]               ko_cpl_spc_data_drv;
+
+
+    // ----------Reconfiguration Controller signals----------
+    wire                      reconfig_busy;
+    wire                      mgmt_clk_clk;
+    wire                      mgmt_rst_reset;
+
+    wire [6:0]                reconfig_mgmt_address;
+    wire                      reconfig_mgmt_read;
+    wire [31:0]               reconfig_mgmt_readdata;
+    wire                      reconfig_mgmt_waitrequest;
+    wire                      reconfig_mgmt_write;
+    wire [31:0]               reconfig_mgmt_writedata;
+
+    // ----------Reconfiguration Driver signals----------
+    wire                      reconfig_xcvr_clk;
+    wire                      reconfig_xcvr_rst;
+
+    wire [7:0]                rx_in;
+    wire [7:0]                tx_out;
+
+    // ----------Serial interfaces----------
+    assign rx_in = PCIE_RX_IN;
+    assign PCIE_TX_OUT = tx_out;
+
+    // ----------Clocks----------
+    assign pld_clk = coreclkout_hip;
+    assign mgmt_clk_clk = PCIE_REFCLK;
+    assign reconfig_xcvr_clk = PCIE_REFCLK;
+    assign refclk = PCIE_REFCLK;
+    assign pld_core_ready = serdes_pll_locked;
+    
+    // ----------Resets----------
+    assign reconfig_xcvr_rst = 1'b0;
+    assign mgmt_rst_reset = 1'b0;
+    assign pin_perst = PCIE_RESET_N;
+    assign npor = PCIE_RESET_N;
+
+    // ----------LED's----------
+    assign LED[7:0] = 8'hff;
+
+    // -------------------- BEGIN ALTERA IP INSTANTIATION  --------------------
+    // Transciever driver (Required for Gen1)
+    altpcie_reconfig_driver 
+        #(.number_of_reconfig_interfaces(10),
+          .gen123_lane_rate_mode_hwtcl("Gen1 (2.5 Gbps)"), // This must be changed between generations
+          .INTENDED_DEVICE_FAMILY("Stratix V"))
+    XCVRDriverGen1x8_inst
+        (
+         // Outputs
+         .reconfig_mgmt_address            (reconfig_mgmt_address[6:0]),
+         .reconfig_mgmt_read               (reconfig_mgmt_read),
+         .reconfig_mgmt_write              (reconfig_mgmt_write),
+         .reconfig_mgmt_writedata          (reconfig_mgmt_writedata[31:0]),
+        
+         // Inputs
+         .pld_clk                          (pld_clk),
+        
+         .reconfig_xcvr_rst                (reconfig_xcvr_rst),
+         .reconfig_mgmt_readdata           (reconfig_mgmt_readdata[31:0]),
+         .reconfig_mgmt_waitrequest        (reconfig_mgmt_waitrequest),
+         .reconfig_xcvr_clk                (reconfig_xcvr_clk),
+         .reconfig_busy                    (reconfig_busy),
+
+         // Link Status signals
+         .derr_cor_ext_rcv_drv             (derr_cor_ext_rcv_drv),
+         .derr_cor_ext_rpl_drv             (derr_cor_ext_rpl_drv),
+         .derr_rpl_drv                     (derr_rpl_drv),
+         .dlup_drv                         (dlup_drv),
+         .dlup_exit_drv                    (dlup_exit_drv),
+         .ev128ns_drv                      (ev128ns_drv),
+         .ev1us_drv                        (ev1us_drv),
+         .hotrst_exit_drv                  (hotrst_exit_drv),
+         .int_status_drv                   (int_status_drv[3:0]),
+         .l2_exit_drv                      (l2_exit_drv),
+         .lane_act_drv                     (lane_act_drv[3:0]),
+         .ltssmstate_drv                   (ltssmstate_drv[4:0]),
+         .rx_par_err_drv                   (rx_par_err_drv),
+         .tx_par_err_drv                   (tx_par_err_drv[1:0]),
+         .cfg_par_err_drv                  (cfg_par_err_drv),
+         .ko_cpl_spc_header_drv            (ko_cpl_spc_header_drv[7:0]),
+         .ko_cpl_spc_data_drv              (ko_cpl_spc_data_drv[11:0]),
+         .currentspeed                     (currentspeed[1:0]));
+
+    assign derr_cor_ext_rcv_drv = derr_cor_ext_rcv;
+    assign derr_cor_ext_rpl_drv = derr_cor_ext_rpl;
+    assign derr_rpl_drv = derr_rpl;
+    assign dlup_drv = dlup;
+    assign dlup_exit_drv = dlup_exit;
+    assign ev128ns_drv = ev128ns;
+    assign ev1us_drv = ev1us;
+    assign hotrst_exit_drv = hotrst_exit;
+    assign int_status_drv = int_status;
+    assign l2_exit_drv = l2_exit;
+    assign lane_act_drv = lane_act;
+    assign ltssmstate_drv = ltssmstate;
+    assign rx_par_err_drv = rx_par_err;
+    assign tx_par_err_drv = tx_par_err;
+    assign cfg_par_err_drv = cfg_par_err;
+    assign ko_cpl_spc_header_drv = ko_cpl_spc_header;
+    assign ko_cpl_spc_data_drv = ko_cpl_spc_data;
+
+    XCVRCtrlGen1x8 XCVRCtrlGen1x8_inst
+        (
+         // Outputs
+         .reconfig_busy                    (reconfig_busy),
+         .reconfig_mgmt_readdata           (reconfig_mgmt_readdata[31:0]),
+         .reconfig_mgmt_waitrequest        (reconfig_mgmt_waitrequest),
+         .reconfig_to_xcvr                 (reconfig_to_xcvr[699:0]),
+         // Inputs
+         .mgmt_clk_clk                     (mgmt_clk_clk),
+         .mgmt_rst_reset                   (mgmt_rst_reset),
+         .reconfig_mgmt_address            (reconfig_mgmt_address[6:0]),
+         .reconfig_mgmt_read               (reconfig_mgmt_read),
+         .reconfig_mgmt_write              (reconfig_mgmt_write),
+         .reconfig_mgmt_writedata          (reconfig_mgmt_writedata[31:0]),
+         .reconfig_from_xcvr               (reconfig_from_xcvr[459:0]));
+
+
+    // PCIE Core
+    PCIeGen1x8If64 PCIeGen1x8If64_inst
+        (
+         // Outputs
+         // Local Management Interface
+         .lmi_ack                          (lmi_ack),
+         .lmi_dout                         (lmi_dout[31:0]),
+         .tl_cfg_add                       (tl_cfg_add[3:0]),
+         .tl_cfg_ctl                       (tl_cfg_ctl[31:0]),
+         .tl_cfg_sts                       (tl_cfg_sts[52:0]),
+         
+         // RX Interface      
+         .rx_st_sop                        (rx_st_sop[0:0]),
+         .rx_st_eop                        (rx_st_eop[0:0]),
+         .rx_st_err                        (rx_st_err[0:0]),
+         .rx_st_valid                      (rx_st_valid[0:0]),
+         .rx_st_data                       (rx_st_data[63:0]),
+         .rx_st_bar                        (rx_st_bar[7:0]),
+         // TX Interface      
+         .tx_st_ready                      (tx_st_ready),
+         
+         .coreclkout_hip                   (coreclkout_hip),
+         .reset_status                     (reset_status),
+         .serdes_pll_locked                (serdes_pll_locked),
+         .pld_clk_inuse                    (pld_clk_inuse),
+
+         // Reconfiguration Interface
+         .reconfig_from_xcvr               (reconfig_from_xcvr[459:0]),
+         
+         .tx_out0                          (tx_out[0]),
+         .tx_out1                          (tx_out[1]),
+         .tx_out2                          (tx_out[2]),
+         .tx_out3                          (tx_out[3]),
+         .tx_out4                          (tx_out[4]),
+         .tx_out5                          (tx_out[5]),
+         .tx_out6                          (tx_out[6]),
+         .tx_out7                          (tx_out[7]),
+
+         .app_int_ack                      (app_int_ack),
+         .app_msi_ack                      (app_msi_ack),
+
+         // Link status signals
+         .derr_cor_ext_rcv                 (derr_cor_ext_rcv),
+         .derr_cor_ext_rpl                 (derr_cor_ext_rpl),
+         .derr_rpl                         (derr_rpl),
+         .dlup                             (dlup),
+         .dlup_exit                        (dlup_exit),
+         .ev128ns                          (ev128ns),
+         .ev1us                            (ev1us),
+         .hotrst_exit                      (hotrst_exit),
+         .int_status                       (int_status[3:0]),
+         .l2_exit                          (l2_exit),
+         .lane_act                         (lane_act[3:0]),
+         .ltssmstate                       (ltssmstate[4:0]),
+         .rx_par_err                       (rx_par_err),
+         .tx_par_err                       (tx_par_err[1:0]),
+         .cfg_par_err                      (cfg_par_err),
+         .ko_cpl_spc_header                (ko_cpl_spc_header[7:0]),
+         .ko_cpl_spc_data                  (ko_cpl_spc_data[11:0]),
+         .currentspeed                     (currentspeed[1:0]),
+         
+         // Inputs
+         // Resets
+         .npor                             (npor),
+         .pin_perst                        (pin_perst),
+
+         // Clocks
+         .pld_clk                          (pld_clk),
+         .refclk                           (refclk),
+         .pld_core_ready                   (pld_core_ready),
+
+         // Local management Interface
+         .lmi_addr                         (lmi_addr[11:0]),
+         .lmi_din                          (lmi_din[31:0]),
+         .lmi_rden                         (lmi_rden),
+         .lmi_wren                         (lmi_wren),
+         
+         // RX Interface
+         .rx_st_ready                      (rx_st_ready),
+         .rx_st_mask                       (rx_st_mask),
+
+         // TX Interface
+         .tx_st_sop                        (tx_st_sop[0:0]),
+         .tx_st_eop                        (tx_st_eop[0:0]),
+         .tx_st_err                        (tx_st_err[0:0]),
+         .tx_st_valid                      (tx_st_valid[0:0]),
+         .tx_st_data                       (tx_st_data[63:0]),
+
+         // Reconfiguration Interface
+         .reconfig_to_xcvr                 (reconfig_to_xcvr[699:0]),
+
+         // RX Serial interface
+         .rx_in0                           (rx_in[0]),
+         .rx_in1                           (rx_in[1]),
+         .rx_in2                           (rx_in[2]),
+         .rx_in3                           (rx_in[3]),
+         .rx_in4                           (rx_in[4]),
+         .rx_in5                           (rx_in[5]),
+         .rx_in6                           (rx_in[6]),
+         .rx_in7                           (rx_in[7]),
+
+         // Interrupt Interface
+         .app_int_sts                      (app_int_sts),
+         .app_msi_num                      (app_msi_num[4:0]),
+         .app_msi_req                      (app_msi_req),
+         .app_msi_tc                       (app_msi_tc[2:0]),
+         .simu_mode_pipe                   (1'b0));
+
+    // -------------------- END ALTERA IP INSTANTIATION  --------------------
+    // -------------------- BEGIN RIFFA INSTANTAION --------------------
+
+    // RIFFA channel interface
+    wire                      rst_out;
+    wire [C_NUM_CHNL-1:0]     chnl_rx_clk;
+    wire [C_NUM_CHNL-1:0]     chnl_rx;
+    wire [C_NUM_CHNL-1:0]     chnl_rx_ack;
+    wire [C_NUM_CHNL-1:0]     chnl_rx_last;
+    wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len;
+    wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_ren;
+    
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_clk;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_last;
+    wire [(C_NUM_CHNL*32)-1:0]               chnl_tx_len;
+    wire [(C_NUM_CHNL*31)-1:0]               chnl_tx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_ren;
+
+    wire                                     chnl_reset;
+    wire                                     chnl_clk;
+    wire                                     riffa_reset;
+    wire                                     riffa_clk;
+
+    assign chnl_clk = pld_clk;
+    assign chnl_reset = rst_out;
+    
+    riffa_wrapper_de5
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .RX_ST_READY                   (rx_st_ready),
+         .TX_ST_DATA                    (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (tx_st_valid[0:0]),
+         .TX_ST_EOP                     (tx_st_eop[0:0]),
+         .TX_ST_SOP                     (tx_st_sop[0:0]),
+         .TX_ST_EMPTY                   (tx_st_empty[0:0]),
+         .APP_MSI_REQ                   (app_msi_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .RX_ST_DATA                    (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (rx_st_eop[0:0]),
+         .RX_ST_SOP                     (rx_st_sop[0:0]),
+         .RX_ST_VALID                   (rx_st_valid[0:0]),
+         .RX_ST_EMPTY                   (rx_st_empty[0:0]),
+         .TX_ST_READY                   (tx_st_ready),
+         .TL_CFG_CTL                    (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]),
+         .KO_CPL_SPC_DATA               (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]),
+         .APP_MSI_ACK                   (app_msi_ack),
+         .PLD_CLK                       (pld_clk),
+         .RESET_STATUS                  (reset_status),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+
+    // --------------------  END RIFFA INSTANTAION --------------------
+    // --------------------  BEGIN USER CODE  --------------------
+    genvar                                   i;
+    generate
+        for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
+            // Instantiate and assign modules to RIFFA channels. Users should 
+            // replace the chnl_tester instantiation with their own core.
+            chnl_tester 
+                 #(
+                   .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                   )
+            chnl_tester_i
+                 (
+
+                  .CLK(chnl_clk),
+                  .RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
+                  // Rx interface
+                  .CHNL_RX_CLK(chnl_rx_clk[i]), 
+                  .CHNL_RX(chnl_rx[i]), 
+                  .CHNL_RX_ACK(chnl_rx_ack[i]), 
+                  .CHNL_RX_LAST(chnl_rx_last[i]), 
+                  .CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]), 
+                  .CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
+                  // Tx interface
+                  .CHNL_TX_CLK(chnl_tx_clk[i]), 
+                  .CHNL_TX(chnl_tx[i]), 
+                  .CHNL_TX_ACK(chnl_tx_ack[i]), 
+                  .CHNL_TX_LAST(chnl_tx_last[i]), 
+                  .CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]), 
+                  .CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
+                  );    
+        end
+    endgenerate
+    // --------------------  END USER CODE  --------------------
+endmodule
diff --git a/fpga/altera/de5/DE5Gen1x8If64/prj/DE5Gen1x8If64.qpf b/fpga/altera/de5/DE5Gen1x8If64/prj/DE5Gen1x8If64.qpf
new file mode 100644
index 0000000..cc8c63f
--- /dev/null
+++ b/fpga/altera/de5/DE5Gen1x8If64/prj/DE5Gen1x8If64.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 16:27:01  June 09, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:27:01  June 09, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "DE5Gen1x8If64"
diff --git a/fpga/altera/de5/DE5Gen1x8If64/prj/DE5Gen1x8If64.qsf b/fpga/altera/de5/DE5Gen1x8If64/prj/DE5Gen1x8If64.qsf
new file mode 100644
index 0000000..99e4f55
--- /dev/null
+++ b/fpga/altera/de5/DE5Gen1x8If64/prj/DE5Gen1x8If64.qsf
@@ -0,0 +1,476 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 11:03:06  March 21, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		DE5Gen1x8If64_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Stratix V"
+set_global_assignment -name DEVICE 5SGXEA7N2F45C2
+set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen1x8If64
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06  MARCH 21, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
+
+################################################################################
+# Timing SDC Files
+################################################################################
+
+################################################################################
+# PCIE Connections
+################################################################################
+# PCIe clk (100 MHz)
+set_location_assignment PIN_AK38 -to PCIE_REFCLK
+set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK
+
+set_location_assignment PIN_AK39 -to "PCIE_REFCLK(n)"
+set_instance_assignment -name IO_STANDARD HCSL -to "PCIE_REFCLK(n)"
+
+set_location_assignment PIN_AU33 -to PCIE_RESET_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_RESET_N
+
+################################################################################
+#PCIE Pins
+################################################################################
+# Settings from SV PCIE User Guide (AV-ST)
+# 100 Ohm Termination 
+# 1.5V PCML 
+# XCVR_VCCR_VCCT_VOLTAGE 0_9V (GEN 1/2 CMU)
+# XCVR_VCCA_VOLTAGE 2_5V (GEN 1/2 CMU)
+# We use CMU PLL's (http://www.altera.com/literature/hb/stratix-v/stx5_52003.pdf)
+
+################################################################################
+#PCIE RX_IN 0
+################################################################################
+
+set_location_assignment PIN_BB43 -to PCIE_RX_IN[0]
+set_location_assignment PIN_BB44 -to "PCIE_RX_IN[0](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[0]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[0](n)"
+
+################################################################################
+#PCIE RX_IN 1
+################################################################################
+
+set_location_assignment PIN_BA41 -to PCIE_RX_IN[1]
+set_location_assignment PIN_BA42 -to "PCIE_RX_IN[1](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[1]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[1](n)"
+
+################################################################################
+#PCIE RX_IN 2
+################################################################################
+
+set_location_assignment PIN_AW41 -to PCIE_RX_IN[2]
+set_location_assignment PIN_AW42 -to "PCIE_RX_IN[2](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[2]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[2](n)"
+
+################################################################################
+#PCIE RX_IN 3
+################################################################################
+
+set_location_assignment PIN_AY43 -to PCIE_RX_IN[3]
+set_location_assignment PIN_AY44 -to "PCIE_RX_IN[3](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[3]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[3](n)"
+
+################################################################################
+#PCIE RX_IN 4
+################################################################################
+
+set_location_assignment PIN_AT43 -to PCIE_RX_IN[4]
+set_location_assignment PIN_AT44 -to "PCIE_RX_IN[4](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[4]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[4](n)"
+
+################################################################################
+#PCIE RX_IN 5
+################################################################################
+
+set_location_assignment PIN_AP43 -to PCIE_RX_IN[5]
+set_location_assignment PIN_AP44 -to "PCIE_RX_IN[5](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[5]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[5](n)"
+
+################################################################################
+#PCIE RX_IN 6
+################################################################################
+
+set_location_assignment PIN_AM43 -to PCIE_RX_IN[6]
+set_location_assignment PIN_AM44 -to "PCIE_RX_IN[6](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[6]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[6](n)"
+
+################################################################################
+#PCIE RX_IN 7
+################################################################################
+
+set_location_assignment PIN_AK43 -to PCIE_RX_IN[7]
+set_location_assignment PIN_AK44 -to "PCIE_RX_IN[7](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[7]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[7](n)"
+
+################################################################################
+#PCIE TX_OUT 0
+################################################################################
+set_location_assignment PIN_AY39 -to PCIE_TX_OUT[0]
+set_location_assignment PIN_AY40 -to "PCIE_TX_OUT[0](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[0]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[0](n)"
+
+################################################################################
+#PCIE TX_OUT 1
+################################################################################
+set_location_assignment PIN_AV39 -to PCIE_TX_OUT[1]
+set_location_assignment PIN_AV40 -to "PCIE_TX_OUT[1](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[1]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[1](n)"
+
+################################################################################
+#PCIE TX_OUT 2
+################################################################################
+set_location_assignment PIN_AT39 -to PCIE_TX_OUT[2]
+set_location_assignment PIN_AT40 -to "PCIE_TX_OUT[2](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[2]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[2](n)"
+
+################################################################################
+#PCIE TX_OUT 3
+################################################################################
+set_location_assignment PIN_AU41 -to PCIE_TX_OUT[3]
+set_location_assignment PIN_AU42 -to "PCIE_TX_OUT[3](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[3]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[3](n)"
+
+################################################################################
+#PCIE TX_OUT 4
+################################################################################
+set_location_assignment PIN_AN41 -to PCIE_TX_OUT[4]
+set_location_assignment PIN_AN42 -to "PCIE_TX_OUT[4](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[4]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[4](n)"
+
+################################################################################
+#PCIE TX_OUT 5
+################################################################################
+set_location_assignment PIN_AL41 -to PCIE_TX_OUT[5]
+set_location_assignment PIN_AL42 -to "PCIE_TX_OUT[5](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[5]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[5](n)"
+
+################################################################################
+#PCIE TX_OUT 6
+################################################################################
+set_location_assignment PIN_AJ41 -to PCIE_TX_OUT[6]
+set_location_assignment PIN_AJ42 -to "PCIE_TX_OUT[6](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[6]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[6](n)"
+
+################################################################################
+#PCIE TX_OUT 7
+################################################################################
+
+set_location_assignment PIN_AG41 -to PCIE_TX_OUT[7]
+set_location_assignment PIN_AG42 -to "PCIE_TX_OUT[7](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[7]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[7](n)"
+
+################################################################################
+# LED's
+################################################################################
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7]
+
+set_location_assignment PIN_AW37 -to LED[0]
+set_location_assignment PIN_AV37 -to LED[1]
+set_location_assignment PIN_BB36 -to LED[2]
+set_location_assignment PIN_BB39 -to LED[3]
+set_location_assignment PIN_AH15 -to LED[4]
+set_location_assignment PIN_AH13 -to LED[5]
+set_location_assignment PIN_AJ13 -to LED[6]
+set_location_assignment PIN_AJ14 -to LED[7]
+
+################################################################################
+# OSCILLATORS
+################################################################################
+
+set_location_assignment PIN_BC28 -to OSC_BANK3D_50MHZ
+set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_BANK3D_50MHZ
+
+################################################################################
+# End Custom Instantiations
+################################################################################
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name SDC_FILE ../constr/DE5Gen1x8If64.sdc
+set_global_assignment -name SIP_FILE ../ip/XCVRCtrlGen1x8.sip
+set_global_assignment -name QIP_FILE ../ip/XCVRCtrlGen1x8.qip
+set_global_assignment -name SIP_FILE ../ip/PCIeGen1x8If64.sip
+set_global_assignment -name QIP_FILE ../ip/PCIeGen1x8If64.qip
+set_global_assignment -name VERILOG_FILE ../hdl/DE5Gen1x8If64.v
+set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ohtb.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/fpga/altera/de5/DE5Gen2x8If128/bit/DE5Gen2x8If128.sof b/fpga/altera/de5/DE5Gen2x8If128/bit/DE5Gen2x8If128.sof
new file mode 100644
index 0000000..b187da0
Binary files /dev/null and b/fpga/altera/de5/DE5Gen2x8If128/bit/DE5Gen2x8If128.sof differ
diff --git a/fpga/altera/de5/DE5Gen2x8If128/constr/DE5Gen2x8If128.sdc b/fpga/altera/de5/DE5Gen2x8If128/constr/DE5Gen2x8If128.sdc
new file mode 100644
index 0000000..60c7923
--- /dev/null
+++ b/fpga/altera/de5/DE5Gen2x8If128/constr/DE5Gen2x8If128.sdc
@@ -0,0 +1,96 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            DE5Gen2x8If128.sdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Synopsys Design Constraints for the DE5 board.
+# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}]
+create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}]
+
+################################################################################
+# 13.1 Workround for http://www.altera.com/support/kdb/solutions/rd12162013_581.html?GSA_pos=1&WT.oss_r=1&WT.oss=adce_off_r
+################################################################################
+
+set_false_path -to [get_registers *|*.adce_off_r[0]]
+set_false_path -to [get_registers *|*.adce_on_rr[0]]
+set_false_path -to [get_registers *|reset_sync_pldclk_r[*]]
+
+################################################################################
+# End Workround 
+################################################################################
+
+derive_pll_clocks -create_base_clocks
+derive_clock_uncertainty
+
+################################################################################
+# Imports from Example Design (altera/13.1/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/)
+################################################################################
+
+######################################################################
+# HIP Soft reset controller SDC constraints
+set_false_path -to   [get_registers *altpcie_rs_serdes|fifo_err_sync_r[0]]
+set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*]
+
+# HIP testin pins SDC constraints
+set_false_path -from [get_pins -compatibility_mode *hip_ctrl*]
+
+######################################################################
+# Constraints for CV SIG asynchonous logic
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|test_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqout[*]}]
+                                                                                                                                                
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqber[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_lf[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_fs[*]}]
\ No newline at end of file
diff --git a/fpga/altera/de5/DE5Gen2x8If128/hdl/DE5Gen2x8If128.v b/fpga/altera/de5/DE5Gen2x8If128/hdl/DE5Gen2x8If128.v
new file mode 100644
index 0000000..b16ce4c
--- /dev/null
+++ b/fpga/altera/de5/DE5Gen2x8If128/hdl/DE5Gen2x8If128.v
@@ -0,0 +1,526 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            DE5Gen2x8If128
+// Version:             
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Altera Stratix V Hard IP for PCI Express
+//                      module and the Terasic DE5 net Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`timescale 1ps / 1ps
+module DE5Gen2x8If128
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Quartus IP Library
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     // ----------LEDs----------
+     output [7:0]             LED,
+
+     // ----------PCIE----------
+     input                    PCIE_RESET_N,
+     input                    PCIE_REFCLK,
+
+     // ----------PCIE Serial RX----------
+     input [C_NUM_LANES-1:0]  PCIE_RX_IN,
+
+     // ----------PCIE Serial TX----------
+     output [C_NUM_LANES-1:0] PCIE_TX_OUT,
+
+     // ----------Oscillators----------
+     input                    OSC_BANK3D_50MHZ
+     );
+
+    wire                      npor;
+    wire                      pin_perst;
+
+    // ----------LMI Interface----------
+    wire [11:0]               lmi_addr;
+    wire [31:0]               lmi_din;
+    wire                      lmi_rden;
+    wire                      lmi_wren;
+    wire                      lmi_ack;
+    wire [31:0]               lmi_dout;
+
+    // ----------TL Config interface----------
+    wire [3:0]                tl_cfg_add;
+    wire [31:0]               tl_cfg_ctl;
+    wire [52:0]               tl_cfg_sts;
+
+    // ----------Rx/TX Interfaces----------
+    wire [0:0]                rx_st_sop;
+    wire [0:0]                rx_st_eop;
+    wire [0:0]                rx_st_err;
+    wire [0:0]                rx_st_valid;
+    wire [0:0]                rx_st_empty;
+    wire                      rx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0] rx_st_data;
+
+    wire [7:0]                  rx_st_bar;
+    wire                        rx_st_mask;
+
+    wire [0:0]                  tx_st_sop;
+    wire [0:0]                  tx_st_eop;
+    wire [0:0]                  tx_st_err;
+    wire [0:0]                  tx_st_valid;
+    wire [0:0]                  tx_st_empty;
+    wire                        tx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0] tx_st_data;
+
+    // ----------Clocks----------
+    wire                        pld_clk;
+    wire                        coreclkout_hip;
+    wire                        refclk;
+    wire                        pld_core_ready;
+    wire                        reset_status;
+    wire                        serdes_pll_locked;
+    wire                        pld_clk_inuse;
+
+    // ----------Reconfiguration busses----------
+    wire [699:0]                reconfig_to_xcvr;
+    wire [505:0]                reconfig_from_xcvr;
+
+    // ----------Interrupt Interfaces----------
+    wire                        app_int_sts;
+    wire [4:0]                  app_msi_num;
+    wire                        app_msi_req;
+    wire [2:0]                  app_msi_tc;
+    wire                        app_int_ack;
+    wire                        app_msi_ack;
+
+    // ----------Link status signals----------
+    wire                        derr_cor_ext_rcv;
+    wire                        derr_cor_ext_rpl;
+    wire                        derr_rpl;
+    wire                        dlup;
+    wire                        dlup_exit;
+    wire                        ev128ns;
+    wire                        ev1us;
+    wire                        hotrst_exit;
+    wire [3:0]                  int_status;
+    wire                        l2_exit;
+    wire [3:0]                  lane_act;
+    wire [4:0]                  ltssmstate;
+    wire                        rx_par_err;
+    wire [1:0]                  tx_par_err;
+    wire                        cfg_par_err;
+    wire [1:0]                  currentspeed;
+    wire [7:0]                  ko_cpl_spc_header;
+    wire [11:0]                 ko_cpl_spc_data;
+
+    // ----------Link Status Signals (Driver)----------
+    wire                        derr_cor_ext_rcv_drv;
+    wire                        derr_cor_ext_rpl_drv;
+    wire                        derr_rpl_drv;
+    wire                        dlup_drv;
+    wire                        dlup_exit_drv;
+    wire                        ev128ns_drv;
+    wire                        ev1us_drv;
+    wire                        hotrst_exit_drv;
+    wire [3:0]                  int_status_drv;
+    wire                        l2_exit_drv;
+    wire [3:0]                  lane_act_drv;
+    wire [4:0]                  ltssmstate_drv;
+    wire                        rx_par_err_drv;
+    wire [1:0]                  tx_par_err_drv;
+    wire                        cfg_par_err_drv;
+    wire [7:0]                  ko_cpl_spc_header_drv;
+    wire [11:0]                 ko_cpl_spc_data_drv;
+
+
+    // ----------Reconfiguration Controller signals----------
+    wire                        reconfig_busy;
+    wire                        mgmt_clk_clk;
+    wire                        mgmt_rst_reset;
+
+    wire [6:0]                  reconfig_mgmt_address;
+    wire                        reconfig_mgmt_read;
+    wire [31:0]                 reconfig_mgmt_readdata;
+    wire                        reconfig_mgmt_waitrequest;
+    wire                        reconfig_mgmt_write;
+    wire [31:0]                 reconfig_mgmt_writedata;
+
+    // ----------Reconfiguration Driver signals----------
+    wire                        reconfig_xcvr_clk;
+    wire                        reconfig_xcvr_rst;
+
+    wire [7:0]                  rx_in;
+    wire [7:0]                  tx_out;
+
+    // ----------Serial interfaces----------
+    assign rx_in = PCIE_RX_IN;
+    assign PCIE_TX_OUT = tx_out;
+
+    // ----------Clocks----------
+    assign pld_clk = coreclkout_hip;
+    assign mgmt_clk_clk = PCIE_REFCLK;
+    assign reconfig_xcvr_clk = PCIE_REFCLK;
+    assign refclk = PCIE_REFCLK;
+    assign pld_core_ready = serdes_pll_locked;
+    
+    // ----------Resets----------
+    assign reconfig_xcvr_rst = 1'b0;
+    assign mgmt_rst_reset = 1'b0;
+    assign pin_perst = PCIE_RESET_N;
+    assign npor = PCIE_RESET_N;
+
+    // ----------LED's----------
+    assign LED[7:0] = 8'hff;
+
+    // -------------------- BEGIN ALTERA IP INSTANTIATION  --------------------
+    // Transciever driver (Required for Gen1)
+    altpcie_reconfig_driver 
+        #(.number_of_reconfig_interfaces(10),
+          .gen123_lane_rate_mode_hwtcl("Gen2 (5.0 Gbps)"),
+          .INTENDED_DEVICE_FAMILY("Stratix V"))
+    XCVRDriverGen2x8_inst
+        (
+         // Outputs
+         .reconfig_mgmt_address            (reconfig_mgmt_address[6:0]),
+         .reconfig_mgmt_read               (reconfig_mgmt_read),
+         .reconfig_mgmt_write              (reconfig_mgmt_write),
+         .reconfig_mgmt_writedata          (reconfig_mgmt_writedata[31:0]),
+        
+         .cal_busy_in                      (),
+         // Inputs
+         .pld_clk                          (pld_clk),
+        
+         .reconfig_xcvr_rst                (reconfig_xcvr_rst),
+         .reconfig_mgmt_readdata           (reconfig_mgmt_readdata[31:0]),
+         .reconfig_mgmt_waitrequest        (reconfig_mgmt_waitrequest),
+         .reconfig_xcvr_clk                (reconfig_xcvr_clk),
+         .reconfig_busy                    (reconfig_busy),
+
+         // Link Status signals
+         .derr_cor_ext_rcv_drv             (derr_cor_ext_rcv_drv),
+         .derr_cor_ext_rpl_drv             (derr_cor_ext_rpl_drv),
+         .derr_rpl_drv                     (derr_rpl_drv),
+         .dlup_drv                         (dlup_drv),
+         .dlup_exit_drv                    (dlup_exit_drv),
+         .ev128ns_drv                      (ev128ns_drv),
+         .ev1us_drv                        (ev1us_drv),
+         .hotrst_exit_drv                  (hotrst_exit_drv),
+         .int_status_drv                   (int_status_drv[3:0]),
+         .l2_exit_drv                      (l2_exit_drv),
+         .lane_act_drv                     (lane_act_drv[3:0]),
+         .ltssmstate_drv                   (ltssmstate_drv[4:0]),
+         .rx_par_err_drv                   (rx_par_err_drv),
+         .tx_par_err_drv                   (tx_par_err_drv[1:0]),
+         .cfg_par_err_drv                  (cfg_par_err_drv),
+         .ko_cpl_spc_header_drv            (ko_cpl_spc_header_drv[7:0]),
+         .ko_cpl_spc_data_drv              (ko_cpl_spc_data_drv[11:0]),
+         .currentspeed                     (currentspeed[1:0]));
+
+    assign derr_cor_ext_rcv_drv = derr_cor_ext_rcv;
+    assign derr_cor_ext_rpl_drv = derr_cor_ext_rpl;
+    assign derr_rpl_drv = derr_rpl;
+    assign dlup_drv = dlup;
+    assign dlup_exit_drv = dlup_exit;
+    assign ev128ns_drv = ev128ns;
+    assign ev1us_drv = ev1us;
+    assign hotrst_exit_drv = hotrst_exit;
+    assign int_status_drv = int_status;
+    assign l2_exit_drv = l2_exit;
+    assign lane_act_drv = lane_act;
+    assign ltssmstate_drv = ltssmstate;
+    assign rx_par_err_drv = rx_par_err;
+    assign tx_par_err_drv = tx_par_err;
+    assign cfg_par_err_drv = cfg_par_err;
+    assign ko_cpl_spc_header_drv = ko_cpl_spc_header;
+    assign ko_cpl_spc_data_drv = ko_cpl_spc_data;
+
+    XCVRCtrlGen2x8 XCVRCtrlGen2x8_inst
+        (
+         // Outputs
+         .reconfig_busy                    (reconfig_busy),
+         .reconfig_mgmt_readdata           (reconfig_mgmt_readdata[31:0]),
+         .reconfig_mgmt_waitrequest        (reconfig_mgmt_waitrequest),
+         .reconfig_to_xcvr                 (reconfig_to_xcvr[699:0]),
+         // Inputs
+         .mgmt_clk_clk                     (mgmt_clk_clk),
+         .mgmt_rst_reset                   (mgmt_rst_reset),
+         .reconfig_mgmt_address            (reconfig_mgmt_address[6:0]),
+         .reconfig_mgmt_read               (reconfig_mgmt_read),
+         .reconfig_mgmt_write              (reconfig_mgmt_write),
+         .reconfig_mgmt_writedata          (reconfig_mgmt_writedata[31:0]),
+         .reconfig_from_xcvr               (reconfig_from_xcvr[459:0]));
+
+
+    // PCIE Core
+    PCIeGen2x8If128 PCIeGen2x8If128_inst
+        (
+         // Outputs
+         // Local Management Interface
+         .lmi_ack                          (lmi_ack),
+         .lmi_dout                         (lmi_dout[31:0]),
+         .tl_cfg_add                       (tl_cfg_add[3:0]),
+         .tl_cfg_ctl                       (tl_cfg_ctl[31:0]),
+         .tl_cfg_sts                       (tl_cfg_sts[52:0]),
+         
+         // RX Interface      
+         .rx_st_sop                        (rx_st_sop[0:0]),
+         .rx_st_eop                        (rx_st_eop[0:0]),
+         .rx_st_err                        (rx_st_err[0:0]),
+         .rx_st_valid                      (rx_st_valid[0:0]),
+         .rx_st_empty                      (rx_st_empty[0:0]),
+         .rx_st_data                       (rx_st_data[127:0]),
+         .rx_st_bar                        (rx_st_bar[7:0]),
+         // TX Interface      
+         .tx_st_ready                      (tx_st_ready),
+         
+         .coreclkout_hip                   (coreclkout_hip),
+         .reset_status                     (reset_status),
+         .serdes_pll_locked                (serdes_pll_locked),
+         .pld_clk_inuse                    (pld_clk_inuse),
+
+         // Reconfiguration Interface
+         .reconfig_from_xcvr               (reconfig_from_xcvr[459:0]),
+         
+         .tx_out0                          (tx_out[0]),
+         .tx_out1                          (tx_out[1]),
+         .tx_out2                          (tx_out[2]),
+         .tx_out3                          (tx_out[3]),
+         .tx_out4                          (tx_out[4]),
+         .tx_out5                          (tx_out[5]),
+         .tx_out6                          (tx_out[6]),
+         .tx_out7                          (tx_out[7]),
+
+         .app_int_ack                      (app_int_ack),
+         .app_msi_ack                      (app_msi_ack),
+
+         // Link status signals
+         .derr_cor_ext_rcv                 (derr_cor_ext_rcv),
+         .derr_cor_ext_rpl                 (derr_cor_ext_rpl),
+         .derr_rpl                         (derr_rpl),
+         .dlup                             (dlup),
+         .dlup_exit                        (dlup_exit),
+         .ev128ns                          (ev128ns),
+         .ev1us                            (ev1us),
+         .hotrst_exit                      (hotrst_exit),
+         .int_status                       (int_status[3:0]),
+         .l2_exit                          (l2_exit),
+         .lane_act                         (lane_act[3:0]),
+         .ltssmstate                       (ltssmstate[4:0]),
+         .rx_par_err                       (rx_par_err),
+         .tx_par_err                       (tx_par_err[1:0]),
+         .cfg_par_err                      (cfg_par_err),
+         .ko_cpl_spc_header                (ko_cpl_spc_header[7:0]),
+         .ko_cpl_spc_data                  (ko_cpl_spc_data[11:0]),
+         .currentspeed                     (currentspeed[1:0]),
+         
+         // Inputs
+         // Resets
+         .npor                             (npor),
+         .pin_perst                        (pin_perst),
+
+         // Clocks
+         .pld_clk                          (pld_clk),
+         .refclk                           (refclk),
+         .pld_core_ready                   (pld_core_ready),
+
+         // Local management Interface
+         .lmi_addr                         (lmi_addr[11:0]),
+         .lmi_din                          (lmi_din[31:0]),
+         .lmi_rden                         (lmi_rden),
+         .lmi_wren                         (lmi_wren),
+         
+         // RX Interface
+         .rx_st_ready                      (rx_st_ready),
+         .rx_st_mask                       (rx_st_mask),
+
+         // TX Interface
+         .tx_st_sop                        (tx_st_sop[0:0]),
+         .tx_st_eop                        (tx_st_eop[0:0]),
+         .tx_st_err                        (tx_st_err[0:0]),
+         .tx_st_valid                      (tx_st_valid[0:0]),
+         .tx_st_empty                      (tx_st_empty[0:0]),
+         .tx_st_data                       (tx_st_data[127:0]),
+
+         // Reconfiguration Interface
+         .reconfig_to_xcvr                 (reconfig_to_xcvr[699:0]),
+
+         // RX Serial interface
+         .rx_in0                           (rx_in[0]),
+         .rx_in1                           (rx_in[1]),
+         .rx_in2                           (rx_in[2]),
+         .rx_in3                           (rx_in[3]),
+         .rx_in4                           (rx_in[4]),
+         .rx_in5                           (rx_in[5]),
+         .rx_in6                           (rx_in[6]),
+         .rx_in7                           (rx_in[7]),
+
+         // Interrupt Interface
+         .app_int_sts                      (app_int_sts),
+         .app_msi_num                      (app_msi_num[4:0]),
+         .app_msi_req                      (app_msi_req),
+         .app_msi_tc                       (app_msi_tc[2:0]),
+         .simu_mode_pipe                   (1'b0));
+    
+    // -------------------- END ALTERA IP INSTANTIATION  --------------------
+    // -------------------- BEGIN RIFFA INSTANTAION --------------------
+
+    // RIFFA channel interface
+    wire                        rst_out;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_clk;
+    wire [C_NUM_CHNL-1:0]       chnl_rx;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_ack;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_last;
+    wire [(C_NUM_CHNL*32)-1:0]  chnl_rx_len;
+    wire [(C_NUM_CHNL*31)-1:0]  chnl_rx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_ren;
+    
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_clk;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_last;
+    wire [(C_NUM_CHNL*32)-1:0]               chnl_tx_len;
+    wire [(C_NUM_CHNL*31)-1:0]               chnl_tx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_ren;
+
+    wire                                     chnl_reset;
+    wire                                     chnl_clk;
+    wire                                     riffa_reset;
+    wire                                     riffa_clk;
+
+    assign chnl_clk = pld_clk;
+    assign chnl_reset = rst_out;
+    
+    riffa_wrapper_de5
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .RX_ST_READY                   (rx_st_ready),
+         .TX_ST_DATA                    (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (tx_st_valid[0:0]),
+         .TX_ST_EOP                     (tx_st_eop[0:0]),
+         .TX_ST_SOP                     (tx_st_sop[0:0]),
+         .TX_ST_EMPTY                   (tx_st_empty[0:0]),
+         .APP_MSI_REQ                   (app_msi_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .RX_ST_DATA                    (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (rx_st_eop[0:0]),
+         .RX_ST_SOP                     (rx_st_sop[0:0]),
+         .RX_ST_VALID                   (rx_st_valid[0:0]),
+         .RX_ST_EMPTY                   (rx_st_empty[0:0]),
+         .TX_ST_READY                   (tx_st_ready),
+         .TL_CFG_CTL                    (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]),
+         .KO_CPL_SPC_DATA               (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]),
+         .APP_MSI_ACK                   (app_msi_ack),
+         .PLD_CLK                       (pld_clk),
+         .RESET_STATUS                  (reset_status),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+
+    // --------------------  END RIFFA INSTANTAION --------------------
+    // --------------------  BEGIN USER CODE  --------------------
+    genvar                                   i;
+    generate
+        for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
+            // Instantiate and assign modules to RIFFA channels. Users should 
+            // replace the chnl_tester instantiation with their own core.
+            chnl_tester 
+                 #(
+                   .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                   )
+            chnl_tester_i
+                 (
+
+                  .CLK(chnl_clk),
+                  .RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
+                  // Rx interface
+                  .CHNL_RX_CLK(chnl_rx_clk[i]), 
+                  .CHNL_RX(chnl_rx[i]), 
+                  .CHNL_RX_ACK(chnl_rx_ack[i]), 
+                  .CHNL_RX_LAST(chnl_rx_last[i]), 
+                  .CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]), 
+                  .CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
+                  // Tx interface
+                  .CHNL_TX_CLK(chnl_tx_clk[i]), 
+                  .CHNL_TX(chnl_tx[i]), 
+                  .CHNL_TX_ACK(chnl_tx_ack[i]), 
+                  .CHNL_TX_LAST(chnl_tx_last[i]), 
+                  .CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]), 
+                  .CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
+                  );    
+        end
+    endgenerate
+    // --------------------  END USER CODE  --------------------
+endmodule
diff --git a/fpga/altera/de5/DE5Gen2x8If128/prj/DE5Gen2x8If128.qpf b/fpga/altera/de5/DE5Gen2x8If128/prj/DE5Gen2x8If128.qpf
new file mode 100644
index 0000000..ea19b9e
--- /dev/null
+++ b/fpga/altera/de5/DE5Gen2x8If128/prj/DE5Gen2x8If128.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 16:15:54  June 09, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:15:54  June 09, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "DE5Gen2x8If128"
diff --git a/fpga/altera/de5/DE5Gen2x8If128/prj/DE5Gen2x8If128.qsf b/fpga/altera/de5/DE5Gen2x8If128/prj/DE5Gen2x8If128.qsf
new file mode 100644
index 0000000..9c632a7
--- /dev/null
+++ b/fpga/altera/de5/DE5Gen2x8If128/prj/DE5Gen2x8If128.qsf
@@ -0,0 +1,501 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 11:03:06  March 21, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		DE5Gen2x8If128_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Stratix V"
+set_global_assignment -name DEVICE 5SGXEA7N2F45C2
+set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen2x8If128
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06  MARCH 21, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
+
+################################################################################
+# Timing SDC Files
+################################################################################
+
+################################################################################
+# PCIE Connections
+################################################################################
+# PCIe clk (100 MHz)
+set_location_assignment PIN_AK38 -to PCIE_REFCLK
+set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK
+
+set_location_assignment PIN_AU33 -to PCIE_RESET_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_RESET_N
+
+################################################################################
+#PCIE Pins
+################################################################################
+# Settings from SV PCIE User Guide (AV-ST)
+# - 1.5V PCML 
+# - XCVR_VCCR_VCCT_VOLTAGE 1_0V 
+# - XCVR_VCCA_VOLTAGE 3_0V 
+# (SV User guide recommends VCCR/VCCT = 0_9 and VCCA = 2_5 , but link does not 
+# train correctly if these settings are used)
+# 
+# We use CMU PLL's (http://www.altera.com/literature/hb/stratix-v/stx5_52003.pdf)
+# Errata: http://www.altera.com/support/kdb/solutions/rd10112012_529.html
+################################################################################
+# Gloabal PCIE assignments (Use if signal problems exist)
+################################################################################
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[*]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[*]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[*]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[*](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[*]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[*]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[*](n)"
+
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_TX_OUT[*]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_TX_OUT[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_TX_OUT[*]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_TX_OUT[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_TX_OUT[*]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_TX_OUT[*](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_TX_OUT[*]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_TX_OUT[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_TX_OUT[*]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_TX_OUT[*](n)"
+
+################################################################################
+#PCIE RX_IN 0
+################################################################################
+
+set_location_assignment PIN_BB43 -to PCIE_RX_IN[0]
+set_location_assignment PIN_BB44 -to "PCIE_RX_IN[0](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[0]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[0](n)"
+
+################################################################################
+#PCIE RX_IN 1
+################################################################################
+
+set_location_assignment PIN_BA41 -to PCIE_RX_IN[1]
+set_location_assignment PIN_BA42 -to "PCIE_RX_IN[1](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[1]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[1](n)"
+
+################################################################################
+#PCIE RX_IN 2
+################################################################################
+
+set_location_assignment PIN_AW41 -to PCIE_RX_IN[2]
+set_location_assignment PIN_AW42 -to "PCIE_RX_IN[2](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[2]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[2](n)"
+
+################################################################################
+#PCIE RX_IN 3
+################################################################################
+
+set_location_assignment PIN_AY43 -to PCIE_RX_IN[3]
+set_location_assignment PIN_AY44 -to "PCIE_RX_IN[3](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[3]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[3](n)"
+
+################################################################################
+#PCIE RX_IN 4
+################################################################################
+
+set_location_assignment PIN_AT43 -to PCIE_RX_IN[4]
+set_location_assignment PIN_AT44 -to "PCIE_RX_IN[4](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[4]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[4](n)"
+
+################################################################################
+#PCIE RX_IN 5
+################################################################################
+
+set_location_assignment PIN_AP43 -to PCIE_RX_IN[5]
+set_location_assignment PIN_AP44 -to "PCIE_RX_IN[5](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[5]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[5](n)"
+
+################################################################################
+#PCIE RX_IN 6
+################################################################################
+
+set_location_assignment PIN_AM43 -to PCIE_RX_IN[6]
+set_location_assignment PIN_AM44 -to "PCIE_RX_IN[6](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[6]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[6](n)"
+
+################################################################################
+#PCIE RX_IN 7
+################################################################################
+
+set_location_assignment PIN_AK43 -to PCIE_RX_IN[7]
+set_location_assignment PIN_AK44 -to "PCIE_RX_IN[7](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[7]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[7](n)"
+
+################################################################################
+#PCIE TX_OUT 0
+################################################################################
+set_location_assignment PIN_AY39 -to PCIE_TX_OUT[0]
+set_location_assignment PIN_AY40 -to "PCIE_TX_OUT[0](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[0]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[0](n)"
+
+################################################################################
+#PCIE TX_OUT 1
+################################################################################
+set_location_assignment PIN_AV39 -to PCIE_TX_OUT[1]
+set_location_assignment PIN_AV40 -to "PCIE_TX_OUT[1](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[1]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[1](n)"
+
+################################################################################
+#PCIE TX_OUT 2
+################################################################################
+set_location_assignment PIN_AT39 -to PCIE_TX_OUT[2]
+set_location_assignment PIN_AT40 -to "PCIE_TX_OUT[2](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[2]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[2](n)"
+
+################################################################################
+#PCIE TX_OUT 3
+################################################################################
+set_location_assignment PIN_AU41 -to PCIE_TX_OUT[3]
+set_location_assignment PIN_AU42 -to "PCIE_TX_OUT[3](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[3]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[3](n)"
+
+################################################################################
+#PCIE TX_OUT 4
+################################################################################
+set_location_assignment PIN_AN41 -to PCIE_TX_OUT[4]
+set_location_assignment PIN_AN42 -to "PCIE_TX_OUT[4](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[4]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[4](n)"
+
+################################################################################
+#PCIE TX_OUT 5
+################################################################################
+set_location_assignment PIN_AL41 -to PCIE_TX_OUT[5]
+set_location_assignment PIN_AL42 -to "PCIE_TX_OUT[5](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[5]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[5](n)"
+
+################################################################################
+#PCIE TX_OUT 6
+################################################################################
+set_location_assignment PIN_AJ41 -to PCIE_TX_OUT[6]
+set_location_assignment PIN_AJ42 -to "PCIE_TX_OUT[6](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[6]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[6](n)"
+
+################################################################################
+#PCIE TX_OUT 7
+################################################################################
+
+set_location_assignment PIN_AG41 -to PCIE_TX_OUT[7]
+set_location_assignment PIN_AG42 -to "PCIE_TX_OUT[7](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[7]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[7](n)"
+
+################################################################################
+# LED's
+################################################################################
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7]
+
+set_location_assignment PIN_AW37 -to LED[0]
+set_location_assignment PIN_AV37 -to LED[1]
+set_location_assignment PIN_BB36 -to LED[2]
+set_location_assignment PIN_BB39 -to LED[3]
+set_location_assignment PIN_AH15 -to LED[4]
+set_location_assignment PIN_AH13 -to LED[5]
+set_location_assignment PIN_AJ13 -to LED[6]
+set_location_assignment PIN_AJ14 -to LED[7]
+
+################################################################################
+# OSCILLATORS
+################################################################################
+
+set_location_assignment PIN_BC28 -to OSC_BANK3D_50MHZ
+set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_BANK3D_50MHZ
+
+################################################################################
+# End Custom Instantiations
+################################################################################
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name SDC_FILE ../constr/DE5Gen2x8If128.sdc
+set_global_assignment -name VERILOG_FILE ../hdl/DE5Gen2x8If128.v
+set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ohtb.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
+set_global_assignment -name QIP_FILE ../ip/PCIeGen2x8If128.qip
+set_global_assignment -name SIP_FILE ../ip/PCIeGen2x8If128.sip
+set_global_assignment -name QIP_FILE ../ip/XCVRCtrlGen2x8.qip
+set_global_assignment -name SIP_FILE ../ip/XCVRCtrlGen2x8.sip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/fpga/altera/de5/DE5Gen3x4If128/bit/DE5Gen3x4If128.sof b/fpga/altera/de5/DE5Gen3x4If128/bit/DE5Gen3x4If128.sof
new file mode 100644
index 0000000..6606a2a
Binary files /dev/null and b/fpga/altera/de5/DE5Gen3x4If128/bit/DE5Gen3x4If128.sof differ
diff --git a/fpga/altera/de5/DE5Gen3x4If128/constr/DE5Gen3x4If128.sdc b/fpga/altera/de5/DE5Gen3x4If128/constr/DE5Gen3x4If128.sdc
new file mode 100644
index 0000000..837f2b5
--- /dev/null
+++ b/fpga/altera/de5/DE5Gen3x4If128/constr/DE5Gen3x4If128.sdc
@@ -0,0 +1,97 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            DE5Gen3x4If128.sdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Synopsys Design Constraints for the DE5 board.
+# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}]
+
+create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}]
+
+################################################################################
+# 13.1 Workround for http://www.altera.com/support/kdb/solutions/rd12162013_581.html?GSA_pos=1&WT.oss_r=1&WT.oss=adce_off_r
+################################################################################
+
+set_false_path -to [get_registers *|*.adce_off_r[0]]
+set_false_path -to [get_registers *|*.adce_on_rr[0]]
+set_false_path -to [get_registers *|reset_sync_pldclk_r[*]]
+
+################################################################################
+# End Workround 
+################################################################################
+
+derive_pll_clocks -create_base_clocks
+derive_clock_uncertainty
+
+################################################################################
+# Imports from Example Design (altera/13.1/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/)
+################################################################################
+
+######################################################################
+# HIP Soft reset controller SDC constraints
+set_false_path -to   [get_registers *altpcie_rs_serdes|fifo_err_sync_r[0]]
+set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*]
+
+# HIP testin pins SDC constraints
+set_false_path -from [get_pins -compatibility_mode *hip_ctrl*]
+
+######################################################################
+# Constraints for CV SIG asynchonous logic
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|test_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqout[*]}]
+                                                                                                                                                
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqber[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_lf[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_fs[*]}]
\ No newline at end of file
diff --git a/fpga/altera/de5/DE5Gen3x4If128/hdl/DE5Gen3x4If128.v b/fpga/altera/de5/DE5Gen3x4If128/hdl/DE5Gen3x4If128.v
new file mode 100644
index 0000000..263f2af
--- /dev/null
+++ b/fpga/altera/de5/DE5Gen3x4If128/hdl/DE5Gen3x4If128.v
@@ -0,0 +1,520 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            DE5Gen3x4If128
+// Version:             
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Altera Stratix V Hard IP for PCI Express
+//                      module and the Terasic DE5 net Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`timescale 1ps / 1ps
+module DE5Gen3x4If128
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Quartus IP Library
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     // ----------LEDs----------
+     output [7:0]             LED,
+
+     // ----------PCIE----------
+     input                    PCIE_RESET_N,
+     input                    PCIE_REFCLK,
+
+     // ----------PCIE Serial RX----------
+     input [C_NUM_LANES-1:0]  PCIE_RX_IN,
+
+     // ----------PCIE Serial TX----------
+     output [C_NUM_LANES-1:0] PCIE_TX_OUT,
+
+     // ----------Oscillators----------
+     input                    OSC_BANK3D_50MHZ
+     );
+
+    wire                      npor;
+    wire                      pin_perst;
+
+    // ----------LMI Interface----------
+    wire [11:0]               lmi_addr;
+    wire [31:0]               lmi_din;
+    wire                      lmi_rden;
+    wire                      lmi_wren;
+    wire                      lmi_ack;
+    wire [31:0]               lmi_dout;
+
+    // ----------TL Config interface----------
+    wire [3:0]                tl_cfg_add;
+    wire [31:0]               tl_cfg_ctl;
+    wire [52:0]               tl_cfg_sts;
+
+    // ----------Rx/TX Interfaces----------
+    wire [0:0]                rx_st_sop;
+    wire [0:0]                rx_st_eop;
+    wire [0:0]                rx_st_err;
+    wire [0:0]                rx_st_valid;
+    wire [0:0]                rx_st_empty;
+    wire                      rx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0] rx_st_data;
+
+    wire [7:0]                  rx_st_bar;
+    wire                        rx_st_mask;
+
+    wire [0:0]                  tx_st_sop;
+    wire [0:0]                  tx_st_eop;
+    wire [0:0]                  tx_st_err;
+    wire [0:0]                  tx_st_valid;
+    wire [0:0]                  tx_st_empty;
+    wire                        tx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0] tx_st_data;
+
+    // ----------Clocks----------
+    wire                        pld_clk;
+    wire                        coreclkout_hip;
+    wire                        refclk;
+    wire                        pld_core_ready;
+    wire                        reset_status;
+    wire                        serdes_pll_locked;
+    wire                        pld_clk_inuse;
+
+    // ----------Reconfiguration busses----------
+    wire [699:0]                reconfig_to_xcvr;
+    wire [505:0]                reconfig_from_xcvr;
+
+    // ----------Interrupt Interfaces----------
+    wire                        app_int_sts;
+    wire [4:0]                  app_msi_num;
+    wire                        app_msi_req;
+    wire [2:0]                  app_msi_tc;
+    wire                        app_int_ack;
+    wire                        app_msi_ack;
+
+    // ----------Link status signals----------
+    wire                        derr_cor_ext_rcv;
+    wire                        derr_cor_ext_rpl;
+    wire                        derr_rpl;
+    wire                        dlup;
+    wire                        dlup_exit;
+    wire                        ev128ns;
+    wire                        ev1us;
+    wire                        hotrst_exit;
+    wire [3:0]                  int_status;
+    wire                        l2_exit;
+    wire [3:0]                  lane_act;
+    wire [4:0]                  ltssmstate;
+    wire                        rx_par_err;
+    wire [1:0]                  tx_par_err;
+    wire                        cfg_par_err;
+    wire [1:0]                  currentspeed;
+    wire [7:0]                  ko_cpl_spc_header;
+    wire [11:0]                 ko_cpl_spc_data;
+
+    // ----------Link Status Signals (Driver)----------
+    wire                        derr_cor_ext_rcv_drv;
+    wire                        derr_cor_ext_rpl_drv;
+    wire                        derr_rpl_drv;
+    wire                        dlup_drv;
+    wire                        dlup_exit_drv;
+    wire                        ev128ns_drv;
+    wire                        ev1us_drv;
+    wire                        hotrst_exit_drv;
+    wire [3:0]                  int_status_drv;
+    wire                        l2_exit_drv;
+    wire [3:0]                  lane_act_drv;
+    wire [4:0]                  ltssmstate_drv;
+    wire                        rx_par_err_drv;
+    wire [1:0]                  tx_par_err_drv;
+    wire                        cfg_par_err_drv;
+    wire [7:0]                  ko_cpl_spc_header_drv;
+    wire [11:0]                 ko_cpl_spc_data_drv;
+
+
+    // ----------Reconfiguration Controller signals----------
+    wire                        reconfig_busy;
+    wire                        mgmt_clk_clk;
+    wire                        mgmt_rst_reset;
+
+    wire [6:0]                  reconfig_mgmt_address;
+    wire                        reconfig_mgmt_read;
+    wire [31:0]                 reconfig_mgmt_readdata;
+    wire                        reconfig_mgmt_waitrequest;
+    wire                        reconfig_mgmt_write;
+    wire [31:0]                 reconfig_mgmt_writedata;
+
+    // ----------Reconfiguration Driver signals----------
+    wire                        reconfig_xcvr_clk;
+    wire                        reconfig_xcvr_rst;
+
+    wire [7:0]                  rx_in;
+    wire [7:0]                  tx_out;
+
+    // ----------Serial interfaces----------
+    assign rx_in = PCIE_RX_IN;
+    assign PCIE_TX_OUT = tx_out;
+
+    // ----------Clocks----------
+    assign pld_clk = coreclkout_hip;
+    assign mgmt_clk_clk = PCIE_REFCLK;
+    assign reconfig_xcvr_clk = PCIE_REFCLK;
+    assign refclk = PCIE_REFCLK;
+    assign pld_core_ready = serdes_pll_locked;
+    
+    // ----------Resets----------
+    assign reconfig_xcvr_rst = 1'b0;
+    assign mgmt_rst_reset = 1'b0;
+    assign pin_perst = PCIE_RESET_N;
+    assign npor = PCIE_RESET_N;
+
+    // ----------LED's----------
+    assign LED[7:0] = 8'hff;
+
+    // -------------------- BEGIN ALTERA IP INSTANTIATION  --------------------
+    // Transciever driver (Required for Gen1)
+   // Transciever driver (Required for Gen3)
+   altpcie_reconfig_driver 
+     #(.number_of_reconfig_interfaces(6),
+       .gen123_lane_rate_mode_hwtcl("Gen3 (8.0 Gbps)"),
+       .INTENDED_DEVICE_FAMILY("Stratix V"))
+   XCVRDriverGen3x4_inst
+     (
+      // Outputs
+      .reconfig_mgmt_address            (reconfig_mgmt_address[6:0]),
+      .reconfig_mgmt_read               (reconfig_mgmt_read),
+      .reconfig_mgmt_write              (reconfig_mgmt_write),
+      .reconfig_mgmt_writedata          (reconfig_mgmt_writedata[31:0]),
+      
+      // Inputs
+      .pld_clk                          (pld_clk),
+      
+      .reconfig_xcvr_rst                (reconfig_xcvr_rst),
+      .reconfig_mgmt_readdata           (reconfig_mgmt_readdata[31:0]),
+      .reconfig_mgmt_waitrequest        (reconfig_mgmt_waitrequest),
+      .reconfig_xcvr_clk                (reconfig_xcvr_clk),
+      .reconfig_busy                    (reconfig_busy),
+
+      // Link Status signals
+      .derr_cor_ext_rcv_drv             (derr_cor_ext_rcv_drv),
+      .derr_cor_ext_rpl_drv             (derr_cor_ext_rpl_drv),
+      .derr_rpl_drv                     (derr_rpl_drv),
+      .dlup_drv                         (dlup_drv),
+      .dlup_exit_drv                    (dlup_exit_drv),
+      .ev128ns_drv                      (ev128ns_drv),
+      .ev1us_drv                        (ev1us_drv),
+      .hotrst_exit_drv                  (hotrst_exit_drv),
+      .int_status_drv                   (int_status_drv[3:0]),
+      .l2_exit_drv                      (l2_exit_drv),
+      .lane_act_drv                     (lane_act_drv[3:0]),
+      .ltssmstate_drv                   (ltssmstate_drv[4:0]),
+      .rx_par_err_drv                   (rx_par_err_drv),
+      .tx_par_err_drv                   (tx_par_err_drv[1:0]),
+      .cfg_par_err_drv                  (cfg_par_err_drv),
+      .ko_cpl_spc_header_drv            (ko_cpl_spc_header_drv[7:0]),
+      .ko_cpl_spc_data_drv              (ko_cpl_spc_data_drv[11:0]),
+      .currentspeed                     (currentspeed[1:0]));
+
+    assign derr_cor_ext_rcv_drv = derr_cor_ext_rcv;
+    assign derr_cor_ext_rpl_drv = derr_cor_ext_rpl;
+    assign derr_rpl_drv = derr_rpl;
+    assign dlup_drv = dlup;
+    assign dlup_exit_drv = dlup_exit;
+    assign ev128ns_drv = ev128ns;
+    assign ev1us_drv = ev1us;
+    assign hotrst_exit_drv = hotrst_exit;
+    assign int_status_drv = int_status;
+    assign l2_exit_drv = l2_exit;
+    assign lane_act_drv = lane_act;
+    assign ltssmstate_drv = ltssmstate;
+    assign rx_par_err_drv = rx_par_err;
+    assign tx_par_err_drv = tx_par_err;
+    assign cfg_par_err_drv = cfg_par_err;
+    assign ko_cpl_spc_header_drv = ko_cpl_spc_header;
+    assign ko_cpl_spc_data_drv = ko_cpl_spc_data;
+
+    XCVRCtrlGen3x4 XCVRCtrlGen3x4_inst
+        (
+         // Outputs
+         .reconfig_busy                    (reconfig_busy),
+         .reconfig_mgmt_readdata           (reconfig_mgmt_readdata[31:0]),
+         .reconfig_mgmt_waitrequest        (reconfig_mgmt_waitrequest),
+         .reconfig_to_xcvr                 (reconfig_to_xcvr[699:0]),
+         // Inputs
+         .mgmt_clk_clk                     (mgmt_clk_clk),
+         .mgmt_rst_reset                   (mgmt_rst_reset),
+         .reconfig_mgmt_address            (reconfig_mgmt_address[6:0]),
+         .reconfig_mgmt_read               (reconfig_mgmt_read),
+         .reconfig_mgmt_write              (reconfig_mgmt_write),
+         .reconfig_mgmt_writedata          (reconfig_mgmt_writedata[31:0]),
+         .reconfig_from_xcvr               (reconfig_from_xcvr[459:0]));
+
+
+    // PCIE Core
+    PCIeGen3x4If128 PCIeGen3x4If128_inst
+        (
+         // Outputs
+         // Local Management Interface
+         .lmi_ack                          (lmi_ack),
+         .lmi_dout                         (lmi_dout[31:0]),
+         .tl_cfg_add                       (tl_cfg_add[3:0]),
+         .tl_cfg_ctl                       (tl_cfg_ctl[31:0]),
+         .tl_cfg_sts                       (tl_cfg_sts[52:0]),
+         
+         // RX Interface      
+         .rx_st_sop                        (rx_st_sop[0:0]),
+         .rx_st_eop                        (rx_st_eop[0:0]),
+         .rx_st_err                        (rx_st_err[0:0]),
+         .rx_st_valid                      (rx_st_valid[0:0]),
+         .rx_st_empty                      (rx_st_empty[0:0]),
+         .rx_st_data                       (rx_st_data[127:0]),
+         .rx_st_bar                        (rx_st_bar[7:0]),
+         // TX Interface      
+         .tx_st_ready                      (tx_st_ready),
+         
+         .coreclkout_hip                   (coreclkout_hip),
+         .reset_status                     (reset_status),
+         .serdes_pll_locked                (serdes_pll_locked),
+         .pld_clk_inuse                    (pld_clk_inuse),
+
+         // Reconfiguration Interface
+         .reconfig_from_xcvr               (reconfig_from_xcvr[459:0]),
+         
+         .tx_out0                          (tx_out[0]),
+         .tx_out1                          (tx_out[1]),
+         .tx_out2                          (tx_out[2]),
+         .tx_out3                          (tx_out[3]),
+
+
+         .app_int_ack                      (app_int_ack),
+         .app_msi_ack                      (app_msi_ack),
+
+         // Link status signals
+         .derr_cor_ext_rcv                 (derr_cor_ext_rcv),
+         .derr_cor_ext_rpl                 (derr_cor_ext_rpl),
+         .derr_rpl                         (derr_rpl),
+         .dlup                             (dlup),
+         .dlup_exit                        (dlup_exit),
+         .ev128ns                          (ev128ns),
+         .ev1us                            (ev1us),
+         .hotrst_exit                      (hotrst_exit),
+         .int_status                       (int_status[3:0]),
+         .l2_exit                          (l2_exit),
+         .lane_act                         (lane_act[3:0]),
+         .ltssmstate                       (ltssmstate[4:0]),
+         .rx_par_err                       (rx_par_err),
+         .tx_par_err                       (tx_par_err[1:0]),
+         .cfg_par_err                      (cfg_par_err),
+         .ko_cpl_spc_header                (ko_cpl_spc_header[7:0]),
+         .ko_cpl_spc_data                  (ko_cpl_spc_data[11:0]),
+         .currentspeed                     (currentspeed[1:0]),
+         
+         // Inputs
+         // Resets
+         .npor                             (npor),
+         .pin_perst                        (pin_perst),
+
+         // Clocks
+         .pld_clk                          (pld_clk),
+         .refclk                           (refclk),
+         .pld_core_ready                   (pld_core_ready),
+
+         // Local management Interface
+         .lmi_addr                         (lmi_addr[11:0]),
+         .lmi_din                          (lmi_din[31:0]),
+         .lmi_rden                         (lmi_rden),
+         .lmi_wren                         (lmi_wren),
+         
+         // RX Interface
+         .rx_st_ready                      (rx_st_ready),
+         .rx_st_mask                       (rx_st_mask),
+
+         // TX Interface
+         .tx_st_sop                        (tx_st_sop[0:0]),
+         .tx_st_eop                        (tx_st_eop[0:0]),
+         .tx_st_err                        (tx_st_err[0:0]),
+         .tx_st_valid                      (tx_st_valid[0:0]),
+         .tx_st_empty                      (tx_st_empty[0:0]),
+         .tx_st_data                       (tx_st_data[127:0]),
+
+         // Reconfiguration Interface
+         .reconfig_to_xcvr                 (reconfig_to_xcvr[699:0]),
+
+         // RX Serial interface
+         .rx_in0                           (rx_in[0]),
+         .rx_in1                           (rx_in[1]),
+         .rx_in2                           (rx_in[2]),
+         .rx_in3                           (rx_in[3]),
+
+
+         // Interrupt Interface
+         .app_int_sts                      (app_int_sts),
+         .app_msi_num                      (app_msi_num[4:0]),
+         .app_msi_req                      (app_msi_req),
+         .app_msi_tc                       (app_msi_tc[2:0]),
+         .simu_mode_pipe                   (1'b0));
+    
+    // -------------------- END ALTERA IP INSTANTIATION  --------------------
+    // -------------------- BEGIN RIFFA INSTANTAION --------------------
+
+    // RIFFA channel interface
+    wire                        rst_out;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_clk;
+    wire [C_NUM_CHNL-1:0]       chnl_rx;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_ack;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_last;
+    wire [(C_NUM_CHNL*32)-1:0]  chnl_rx_len;
+    wire [(C_NUM_CHNL*31)-1:0]  chnl_rx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_ren;
+    
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_clk;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_last;
+    wire [(C_NUM_CHNL*32)-1:0]               chnl_tx_len;
+    wire [(C_NUM_CHNL*31)-1:0]               chnl_tx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_ren;
+
+    wire                                     chnl_reset;
+    wire                                     chnl_clk;
+    wire                                     riffa_reset;
+    wire                                     riffa_clk;
+
+    assign chnl_clk = pld_clk;
+    assign chnl_reset = rst_out;
+    
+    riffa_wrapper_de5
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))/* TODO: Standardize*/
+    riffa
+        (
+         // Outputs
+         .RX_ST_READY                   (rx_st_ready),
+         .TX_ST_DATA                    (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (tx_st_valid[0:0]),
+         .TX_ST_EOP                     (tx_st_eop[0:0]),
+         .TX_ST_SOP                     (tx_st_sop[0:0]),
+         .TX_ST_EMPTY                   (tx_st_empty[0:0]),
+         .APP_MSI_REQ                   (app_msi_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .RX_ST_DATA                    (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (rx_st_eop[0:0]),
+         .RX_ST_SOP                     (rx_st_sop[0:0]),
+         .RX_ST_VALID                   (rx_st_valid[0:0]),
+         .RX_ST_EMPTY                   (rx_st_empty[0:0]),
+         .TX_ST_READY                   (tx_st_ready),
+         .TL_CFG_CTL                    (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]),
+         .KO_CPL_SPC_DATA               (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]),
+         .APP_MSI_ACK                   (app_msi_ack),
+         .PLD_CLK                       (pld_clk),
+         .RESET_STATUS                  (reset_status),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+
+    // --------------------  END RIFFA INSTANTAION --------------------
+    // --------------------  BEGIN USER CODE  --------------------
+    genvar                                   i;
+    generate
+        for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
+            // Instantiate and assign modules to RIFFA channels. Users should 
+            // replace the chnl_tester instantiation with their own core.
+            chnl_tester 
+                 #(
+                   .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                   )
+            chnl_tester_i
+                 (
+
+                  .CLK(chnl_clk),
+                  .RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
+                  // Rx interface
+                  .CHNL_RX_CLK(chnl_rx_clk[i]), 
+                  .CHNL_RX(chnl_rx[i]), 
+                  .CHNL_RX_ACK(chnl_rx_ack[i]), 
+                  .CHNL_RX_LAST(chnl_rx_last[i]), 
+                  .CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]), 
+                  .CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
+                  // Tx interface
+                  .CHNL_TX_CLK(chnl_tx_clk[i]), 
+                  .CHNL_TX(chnl_tx[i]), 
+                  .CHNL_TX_ACK(chnl_tx_ack[i]), 
+                  .CHNL_TX_LAST(chnl_tx_last[i]), 
+                  .CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]), 
+                  .CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
+                  );    
+        end
+    endgenerate
+    // --------------------  END USER CODE  --------------------
+endmodule
diff --git a/fpga/altera/de5/DE5Gen3x4If128/prj/DE5Gen3x4If128.qpf b/fpga/altera/de5/DE5Gen3x4If128/prj/DE5Gen3x4If128.qpf
new file mode 100644
index 0000000..b4e1f62
--- /dev/null
+++ b/fpga/altera/de5/DE5Gen3x4If128/prj/DE5Gen3x4If128.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 16:21:12  June 09, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:21:12  June 09, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "DE5Gen3x4If128"
diff --git a/fpga/altera/de5/DE5Gen3x4If128/prj/DE5Gen3x4If128.qsf b/fpga/altera/de5/DE5Gen3x4If128/prj/DE5Gen3x4If128.qsf
new file mode 100644
index 0000000..df45d97
--- /dev/null
+++ b/fpga/altera/de5/DE5Gen3x4If128/prj/DE5Gen3x4If128.qsf
@@ -0,0 +1,572 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 11:03:06  March 21, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		DE5Gen3x4If128_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Stratix V"
+set_global_assignment -name DEVICE 5SGXEA7N2F45C2
+set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen3x4If128
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06  MARCH 21, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
+
+################################################################################
+# Timing SDC Files
+################################################################################
+
+################################################################################
+# PCIE Connections
+################################################################################
+# PCIe clk (100 MHz)
+set_location_assignment PIN_AK38 -to PCIE_REFCLK
+
+set_location_assignment PIN_AK39 -to "PCIE_REFCLK(n)"
+
+set_location_assignment PIN_AU33 -to PCIE_RESET_N
+
+
+################################################################################
+#PCIE Pins
+################################################################################
+# Settings from SV PCIE User Guide (AV-ST)
+# 100 Ohm Termination 
+# 1.5V PCML 
+# XCVR_VCCR_VCCT_VOLTAGE 1_0V 
+# XCVR_VCCA_VOLTAGE 3_0V
+# We use CMU PLL's (http://www.altera.com/literature/hb/stratix-v/stx5_52003.pdf)
+# http://www.altera.com/support/kdb/downloads/rd08232012_334/quartusii-12.0sp2-2.dp9-readme.txt
+# Errata: http://www.altera.com/support/kdb/solutions/rd10112012_529.html
+
+################################################################################
+# Gloabal PCIE assignments (Use if signal problems exist)
+################################################################################
+
+################################################################################
+#PCIE RX_IN 0
+################################################################################
+
+set_location_assignment PIN_BB43 -to PCIE_RX_IN[0]
+set_location_assignment PIN_BB44 -to "PCIE_RX_IN[0](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 1
+################################################################################
+
+set_location_assignment PIN_BA41 -to PCIE_RX_IN[1]
+set_location_assignment PIN_BA42 -to "PCIE_RX_IN[1](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 2
+################################################################################
+
+set_location_assignment PIN_AW41 -to PCIE_RX_IN[2]
+set_location_assignment PIN_AW42 -to "PCIE_RX_IN[2](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 3
+################################################################################
+
+set_location_assignment PIN_AY43 -to PCIE_RX_IN[3]
+set_location_assignment PIN_AY44 -to "PCIE_RX_IN[3](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 4
+################################################################################
+
+# set_location_assignment PIN_AT43 -to PCIE_RX_IN[4]
+# set_location_assignment PIN_AT44 -to "PCIE_RX_IN[4](n)"
+
+
+
+################################################################################
+#PCIE RX_IN 5
+################################################################################
+
+# set_location_assignment PIN_AP43 -to PCIE_RX_IN[5]
+# set_location_assignment PIN_AP44 -to "PCIE_RX_IN[5](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 6
+################################################################################
+
+# set_location_assignment PIN_AM43 -to PCIE_RX_IN[6]
+# set_location_assignment PIN_AM44 -to "PCIE_RX_IN[6](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 7
+################################################################################
+
+# set_location_assignment PIN_AK43 -to PCIE_RX_IN[7]
+# set_location_assignment PIN_AK44 -to "PCIE_RX_IN[7](n)"
+
+
+
+
+################################################################################
+#PCIE TX_OUT 0
+################################################################################
+set_location_assignment PIN_AY39 -to PCIE_TX_OUT[0]
+set_location_assignment PIN_AY40 -to "PCIE_TX_OUT[0](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 1
+################################################################################
+set_location_assignment PIN_AV39 -to PCIE_TX_OUT[1]
+set_location_assignment PIN_AV40 -to "PCIE_TX_OUT[1](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 2
+################################################################################
+set_location_assignment PIN_AT39 -to PCIE_TX_OUT[2]
+set_location_assignment PIN_AT40 -to "PCIE_TX_OUT[2](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 3
+################################################################################
+set_location_assignment PIN_AU41 -to PCIE_TX_OUT[3]
+set_location_assignment PIN_AU42 -to "PCIE_TX_OUT[3](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 4
+################################################################################
+# set_location_assignment PIN_AN41 -to PCIE_TX_OUT[4]
+# set_location_assignment PIN_AN42 -to "PCIE_TX_OUT[4](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 5
+################################################################################
+# set_location_assignment PIN_AL41 -to PCIE_TX_OUT[5]
+# set_location_assignment PIN_AL42 -to "PCIE_TX_OUT[5](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 6
+################################################################################
+# set_location_assignment PIN_AJ41 -to PCIE_TX_OUT[6]
+# set_location_assignment PIN_AJ42 -to "PCIE_TX_OUT[6](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 7
+################################################################################
+
+# set_location_assignment PIN_AG41 -to PCIE_TX_OUT[7]
+# set_location_assignment PIN_AG42 -to "PCIE_TX_OUT[7](n)"
+
+
+
+################################################################################
+# LED's
+################################################################################
+
+set_location_assignment PIN_AW37 -to LED[0]
+set_location_assignment PIN_AV37 -to LED[1]
+set_location_assignment PIN_BB36 -to LED[2]
+set_location_assignment PIN_BB39 -to LED[3]
+set_location_assignment PIN_AH15 -to LED[4]
+set_location_assignment PIN_AH13 -to LED[5]
+set_location_assignment PIN_AJ13 -to LED[6]
+set_location_assignment PIN_AJ14 -to LED[7]
+
+################################################################################
+# OSCILLATORS
+################################################################################
+
+set_location_assignment PIN_BC28 -to OSC_BANK3D_50MHZ
+
+################################################################################
+# End Custom Instantiations
+################################################################################
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK
+set_instance_assignment -name IO_STANDARD HCSL -to "PCIE_REFCLK(n)"
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_RESET_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_wake
+set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_smbclk
+set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_smbdata
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[0]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[0]
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[1]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[1]
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[2]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[2]
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[3]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[3]
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[3](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[4]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[4]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[5]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[5]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[6]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[6]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[7]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[7]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[0]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[1]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[2]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[3]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[3](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[4]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[4]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[4]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[4]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[4](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[4](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[4](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[4](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[5]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[5]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[5]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[5]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[5](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[5](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[5](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[5](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[6]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[6]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[6]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[6]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[6](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[6](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[6](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[6](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[7]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[7]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[7]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[7]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[7](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[7](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[7](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_BANK3D_50MHZ
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name SDC_FILE ../constr/DE5Gen3x4If128.sdc
+set_global_assignment -name VERILOG_FILE ../hdl/DE5Gen3x4If128.v
+set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ohtb.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
+set_global_assignment -name SIP_FILE ../ip/XCVRCtrlGen3x4.sip
+set_global_assignment -name QIP_FILE ../ip/XCVRCtrlGen3x4.qip
+set_global_assignment -name QIP_FILE ../ip/PCIeGen3x4If128.qip
+set_global_assignment -name SIP_FILE ../ip/PCIeGen3x4If128.sip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/fpga/altera/de5/riffa_wrapper_de5.v b/fpga/altera/de5/riffa_wrapper_de5.v
new file mode 100644
index 0000000..e258c32
--- /dev/null
+++ b/fpga/altera/de5/riffa_wrapper_de5.v
@@ -0,0 +1,614 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            riffa_wrapper_de5.v
+// Version:             1.00a
+// Verilog Standard:    Verilog-2001
+// Description:         Wrapper file for all riffa logic for Altera DE5 boards
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`include "ultrascale.vh"
+`include "functions.vh"
+`timescale 1ps / 1ps
+module riffa_wrapper_de5
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Bit-Width from Quartus IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     // Interface: Altera RX 
+     input [C_PCI_DATA_WIDTH-1:0]                 RX_ST_DATA,
+     input [0:0]                                  RX_ST_EOP,
+     input [0:0]                                  RX_ST_SOP,
+     input [0:0]                                  RX_ST_VALID,
+     output                                       RX_ST_READY,
+     input [0:0]                                  RX_ST_EMPTY,
+
+     // Interface: Altera TX
+     output [C_PCI_DATA_WIDTH-1:0]                TX_ST_DATA,
+     output [0:0]                                 TX_ST_VALID,
+     input                                        TX_ST_READY,
+     output [0:0]                                 TX_ST_EOP,
+     output [0:0]                                 TX_ST_SOP,
+     output [0:0]                                 TX_ST_EMPTY,
+
+     // Interface: Altera Config
+     input [`SIG_CFG_CTL_W-1:0]                   TL_CFG_CTL,
+     input [`SIG_CFG_ADD_W-1:0]                   TL_CFG_ADD,
+     input [`SIG_CFG_STS_W-1:0]                   TL_CFG_STS,
+
+     // Interface: Altera Flow Control
+     input [`SIG_KO_CPLH_W-1:0]                   KO_CPL_SPC_HEADER,
+     input [`SIG_KO_CPLD_W-1:0]                   KO_CPL_SPC_DATA,
+    
+     // Interface: Altera Interrupt
+     input                                        APP_MSI_ACK,
+     output                                       APP_MSI_REQ,
+
+     // Interface: Altera CLK/RESET
+     input                                        PLD_CLK,
+     input                                        RESET_STATUS,
+
+     // RIFFA Interface Signals
+     output                                       RST_OUT,
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_CLK, // Channel read clock
+     output [C_NUM_CHNL-1:0]                      CHNL_RX, // Channel read receive signal
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_ACK, // Channel read received signal
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_LAST, // Channel last read
+     output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
+     output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
+     output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   CHNL_RX_DATA, // Channel read data
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_DATA_VALID, // Channel read data valid
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_DATA_REN, // Channel read data has been recieved
+
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_CLK, // Channel write clock
+     input [C_NUM_CHNL-1:0]                       CHNL_TX, // Channel write receive signal
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_ACK, // Channel write acknowledgement signal
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_LAST, // Channel last write
+     input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]  CHNL_TX_LEN, // Channel write length (in 32 bit words)
+     input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]  CHNL_TX_OFF, // Channel write offset
+     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]    CHNL_TX_DATA, // Channel write data
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_DATA_VALID, // Channel write data valid
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_DATA_REN // Channel write data has been recieved
+
+     );
+    localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
+    localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
+    localparam C_VENDOR = "ALTERA";
+
+    localparam C_ALTERA_TX_READY_LATENCY = 2;
+    localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
+    localparam C_PIPELINE_OUTPUT = 1;
+    localparam C_PIPELINE_INPUT = 1;
+
+    wire                                          clk;
+    wire                                          rst_in;
+
+    // Interface: RXC Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxc_data;
+    wire                                          rxc_data_valid;
+    wire                                          rxc_data_start_flag;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxc_data_word_enable;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxc_meta_fdwbe;
+    wire                                          rxc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxc_meta_ldwbe;
+    wire [`SIG_TAG_W-1:0]                         rxc_meta_tag;
+    wire [`SIG_LOWADDR_W-1:0]                     rxc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        rxc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         rxc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     rxc_meta_bytes_remaining;
+    wire [`SIG_CPLID_W-1:0]                       rxc_meta_completer_id;
+    wire                                          rxc_meta_ep;
+
+    // Interface: RXR Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxr_data;
+    wire                                          rxr_data_valid;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxr_data_word_enable;
+    wire                                          rxr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxr_meta_fdwbe;
+    wire                                          rxr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxr_meta_ldwbe;
+    wire [`SIG_TC_W-1:0]                          rxr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        rxr_meta_attr;
+    wire [`SIG_TAG_W-1:0]                         rxr_meta_tag;
+    wire [`SIG_TYPE_W-1:0]                        rxr_meta_type;
+    wire [`SIG_ADDR_W-1:0]                        rxr_meta_addr;
+    wire [`SIG_BARDECODE_W-1:0]                   rxr_meta_bar_decoded;
+    wire [`SIG_REQID_W-1:0]                       rxr_meta_requester_id;
+    wire [`SIG_LEN_W-1:0]                         rxr_meta_length;
+    wire                                          rxr_meta_ep;
+    
+    // interface: TXC Engine
+    wire                                          txc_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txc_data;
+    wire                                          txc_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_start_offset;
+    wire                                          txc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_end_offset;
+    wire                                          txc_data_ready;
+
+    wire                                          txc_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txc_meta_fdwbe;
+    wire [`SIG_LBE_W-1:0]                         txc_meta_ldwbe;
+    wire [`SIG_LOWADDR_W-1:0]                     txc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        txc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         txc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     txc_meta_byte_count;
+    wire [`SIG_TAG_W-1:0]                         txc_meta_tag;
+    wire [`SIG_REQID_W-1:0]                       txc_meta_requester_id;
+    wire [`SIG_TC_W-1:0]                          txc_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txc_meta_attr;
+    wire                                          txc_meta_ep;
+    wire                                          txc_meta_ready;
+    wire                                          txc_sent;
+
+    // Interface: TXR Engine
+    wire                                          txr_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txr_data;
+    wire                                          txr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_start_offset;
+    wire                                          txr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_end_offset;
+    wire                                          txr_data_ready;
+
+    wire                                          txr_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txr_meta_fdwbe; 
+    wire [`SIG_LBE_W-1:0]                         txr_meta_ldwbe;
+    wire [`SIG_ADDR_W-1:0]                        txr_meta_addr;
+    wire [`SIG_LEN_W-1:0]                         txr_meta_length;
+    wire [`SIG_TAG_W-1:0]                         txr_meta_tag;
+    wire [`SIG_TC_W-1:0]                          txr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txr_meta_attr;
+    wire [`SIG_TYPE_W-1:0]                        txr_meta_type;
+    wire                                          txr_meta_ep;
+    wire                                          txr_meta_ready;
+    wire                                          txr_sent;
+
+    // Classic Interface Wires
+    wire                                          wRxTlpReady;
+    wire [C_PCI_DATA_WIDTH-1:0]                   wRxTlp;
+    wire                                          wRxTlpEndFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wRxTlpEndOffset;
+    wire                                          wRxTlpStartFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wRxTlpStartOffset;
+    wire                                          wRxTlpValid;
+    wire [`SIG_BARDECODE_W-1:0]                   wRxTlpBarDecode;
+    
+    wire                                          wTxTlpReady;
+    wire [C_PCI_DATA_WIDTH-1:0]                   wTxTlp;
+    wire                                          wTxTlpEndFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wTxTlpEndOffset;
+    wire                                          wTxTlpStartFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wTxTlpStartOffset;
+    wire                                          wTxTlpValid;
+    
+    // Unconnected Wires (Used in ultrascale interface)
+    // Interface: RQ (TXC)
+    wire                                          s_axis_rq_tlast_nc;
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_rq_tdata_nc;
+    wire [`SIG_RQ_TUSER_W-1:0]                    s_axis_rq_tuser_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_rq_tkeep_nc;
+    wire                                          s_axis_rq_tready_nc = 0;
+    wire                                          s_axis_rq_tvalid_nc;
+    // Interface: RC (RXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_rc_tdata_nc = 0;
+    wire [`SIG_RC_TUSER_W-1:0]                    m_axis_rc_tuser_nc = 0;
+    wire                                          m_axis_rc_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_rc_tkeep_nc = 0;
+    wire                                          m_axis_rc_tvalid_nc = 0;
+    wire                                          m_axis_rc_tready_nc;
+    // Interface: CQ (RXR)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_cq_tdata_nc = 0;
+    wire [`SIG_CQ_TUSER_W-1:0]                    m_axis_cq_tuser_nc = 0;
+    wire                                          m_axis_cq_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_cq_tkeep_nc = 0;
+    wire                                          m_axis_cq_tvalid_nc = 0;
+    wire                                          m_axis_cq_tready_nc = 0;
+    // Interface: CC (TXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_cc_tdata_nc;
+    wire [`SIG_CC_TUSER_W-1:0]                    s_axis_cc_tuser_nc;
+    wire                                          s_axis_cc_tlast_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_cc_tkeep_nc;
+    wire                                          s_axis_cc_tvalid_nc;
+    wire                                          s_axis_cc_tready_nc = 0;
+
+    // Interface: Configuration
+    wire                                          config_bus_master_enable;
+    wire [`SIG_CPLID_W-1:0]                       config_completer_id;
+    wire                                          config_cpl_boundary_sel;
+    wire                                          config_interrupt_msienable;
+    wire [`SIG_LINKRATE_W-1:0]                    config_link_rate;
+    wire [`SIG_LINKWIDTH_W-1:0]                   config_link_width;
+    wire [`SIG_MAXPAYLOAD_W-1:0]                  config_max_payload_size;
+    wire [`SIG_MAXREAD_W-1:0]                     config_max_read_request_size;
+    wire [`SIG_FC_CPLD_W-1:0]                     config_max_cpl_data;
+    wire [`SIG_FC_CPLH_W-1:0]                     config_max_cpl_hdr;
+
+    wire                                          intr_msi_request;
+    wire                                          intr_msi_rdy;
+
+    genvar                                        chnl;
+
+    assign clk = PLD_CLK;
+    assign rst_in = RESET_STATUS;
+
+    translation_altera
+        #(
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH))
+    trans
+        (
+         // Outputs
+         .RX_TLP                            (wRxTlp[C_PCI_DATA_WIDTH-1:0]),
+         .RX_TLP_VALID                      (wRxTlpValid),
+         .RX_TLP_START_FLAG                 (wRxTlpStartFlag),
+         .RX_TLP_START_OFFSET               (wRxTlpStartOffset[`SIG_OFFSET_W-1:0]),
+         .RX_TLP_END_FLAG                   (wRxTlpEndFlag),
+         .RX_TLP_END_OFFSET                 (wRxTlpEndOffset[`SIG_OFFSET_W-1:0]),
+         .RX_TLP_BAR_DECODE                 (wRxTlpBarDecode[`SIG_BARDECODE_W-1:0]),
+         .TX_TLP_READY                      (wTxTlpReady),
+         .CONFIG_COMPLETER_ID               (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE          (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH                 (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE                  (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE      (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE           (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE        (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL           (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA               (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR                (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+         .INTR_MSI_RDY                      (intr_msi_rdy),
+         // Inputs
+         .CLK                               (clk),
+         .RST_IN                            (rst_in),
+         .RX_TLP_READY                      (wRxTlpReady),
+         .TX_TLP                            (wTxTlp[C_PCI_DATA_WIDTH-1:0]),
+         .TX_TLP_VALID                      (wTxTlpValid),
+         .TX_TLP_START_FLAG                 (wTxTlpStartFlag),
+         .TX_TLP_START_OFFSET               (wTxTlpStartOffset[`SIG_OFFSET_W-1:0]),
+         .TX_TLP_END_FLAG                   (wTxTlpEndFlag),
+         .TX_TLP_END_OFFSET                 (wTxTlpEndOffset[`SIG_OFFSET_W-1:0]),
+         .INTR_MSI_REQUEST                  (intr_msi_request),
+         /*AUTOINST*/
+         // Outputs
+         .RX_ST_READY                   (RX_ST_READY),
+         .TX_ST_DATA                    (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (TX_ST_VALID[0:0]),
+         .TX_ST_EOP                     (TX_ST_EOP[0:0]),
+         .TX_ST_SOP                     (TX_ST_SOP[0:0]),
+         .TX_ST_EMPTY                   (TX_ST_EMPTY[0:0]),
+         .APP_MSI_REQ                   (APP_MSI_REQ),
+         // Inputs
+         .RX_ST_DATA                    (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (RX_ST_EOP[0:0]),
+         .RX_ST_SOP                     (RX_ST_SOP[0:0]),
+         .RX_ST_VALID                   (RX_ST_VALID[0:0]),
+         .RX_ST_EMPTY                   (RX_ST_EMPTY[0:0]),
+         .TX_ST_READY                   (TX_ST_READY),
+         .TL_CFG_CTL                    (TL_CFG_CTL[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (TL_CFG_ADD[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (TL_CFG_STS[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (KO_CPL_SPC_HEADER[`SIG_FC_CPLH_W-1:0]),
+         .KO_CPL_SPC_DATA               (KO_CPL_SPC_DATA[`SIG_FC_CPLD_W-1:0]),
+         .APP_MSI_ACK                   (APP_MSI_ACK));
+
+    engine_layer
+        #(// Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_BYTES/4),
+          .C_VENDOR                     (C_VENDOR))
+    engine_layer_inst
+        (// Outputs
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+         // Unconnected Outputs
+         .TX_TLP                        (wTxTlp),
+         .TX_TLP_VALID                  (wTxTlpValid),
+         .TX_TLP_START_FLAG             (wTxTlpStartFlag),
+         .TX_TLP_START_OFFSET           (wTxTlpStartOffset),
+         .TX_TLP_END_FLAG               (wTxTlpEndFlag),
+         .TX_TLP_END_OFFSET             (wTxTlpEndOffset),
+
+         .RX_TLP_READY                  (wRxTlpReady),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+         // Unconnected Inputs
+         .RX_TLP                        (wRxTlp),
+         .RX_TLP_VALID                  (wRxTlpValid),
+         .RX_TLP_START_FLAG             (wRxTlpStartFlag),
+         .RX_TLP_START_OFFSET           (wRxTlpStartOffset),
+         .RX_TLP_END_FLAG               (wRxTlpEndFlag),
+         .RX_TLP_END_OFFSET             (wRxTlpEndOffset),
+         .RX_TLP_BAR_DECODE             (wRxTlpBarDecode),
+
+         .TX_TLP_READY                  (wTxTlpReady),
+         // Outputs
+         .M_AXIS_CQ_TREADY              (m_axis_cq_tready_nc),
+         .M_AXIS_RC_TREADY              (m_axis_rc_tready_nc),
+         .S_AXIS_CC_TVALID              (s_axis_cc_tvalid_nc),
+         .S_AXIS_CC_TLAST               (s_axis_cc_tlast_nc),
+         .S_AXIS_CC_TDATA               (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (s_axis_rq_tvalid_nc),
+         .S_AXIS_RQ_TLAST               (s_axis_rq_tlast_nc),
+         .S_AXIS_RQ_TDATA               (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (m_axis_cq_tvalid_nc),
+         .M_AXIS_CQ_TLAST               (m_axis_cq_tlast_nc),
+         .M_AXIS_CQ_TDATA               (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (m_axis_rc_tvalid_nc),
+         .M_AXIS_RC_TLAST               (m_axis_rc_tlast_nc),
+         .M_AXIS_RC_TDATA               (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (s_axis_cc_tready_nc),
+         .S_AXIS_RQ_TREADY              (s_axis_rq_tready_nc)
+         /*AUTOINST*/);
+
+    riffa
+        #(.C_TAG_WIDTH                  (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_MAX_READ_REQ_BYTES         (C_MAX_READ_REQ_BYTES),
+          .C_VENDOR                     (C_VENDOR),
+          .C_FPGA_NAME                  (C_FPGA_NAME))
+    riffa_inst
+        (// Outputs
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+
+         .INTR_MSI_REQUEST              (intr_msi_request),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),         
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE      (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH             (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE              (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE  (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE       (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE    (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL       (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA           (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR            (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+        
+         .INTR_MSI_RDY                  (intr_msi_rdy),
+
+         /*AUTOINST*/
+         // Outputs
+         .RST_OUT                       (RST_OUT),
+         .CHNL_RX                       (CHNL_RX[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_RX_OFF                   (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_RX_DATA                  (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
+         // Inputs
+         .CHNL_RX_CLK                   (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (CHNL_TX[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_TX_OFF                   (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_TX_DATA                  (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("../../engine/" "../../riffa/" "../../trans")
+// End:
+
diff --git a/fpga/altera/de5_qsys/DE5Gen1x8If64/bit/DE5Gen1x8If64.sof b/fpga/altera/de5_qsys/DE5Gen1x8If64/bit/DE5Gen1x8If64.sof
new file mode 100644
index 0000000..8b379b7
Binary files /dev/null and b/fpga/altera/de5_qsys/DE5Gen1x8If64/bit/DE5Gen1x8If64.sof differ
diff --git a/fpga/altera/de5_qsys/DE5Gen1x8If64/constr/DE5Gen1x8If64.sdc b/fpga/altera/de5_qsys/DE5Gen1x8If64/constr/DE5Gen1x8If64.sdc
new file mode 100644
index 0000000..e64e921
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen1x8If64/constr/DE5Gen1x8If64.sdc
@@ -0,0 +1,95 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            DE5Gen1x8If64.sdc (Qsys)
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Synopsys Design Constraints for the DE5 board.
+# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}]
+create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}]
+
+################################################################################
+# 13.1 Workround for http://www.altera.com/support/kdb/solutions/rd12162013_581.html?GSA_pos=1&WT.oss_r=1&WT.oss=adce_off_r
+################################################################################
+
+# set_false_path -to [get_registers *|*.adce_off_r[0]]
+# set_false_path -to [get_registers *|*.adce_on_rr[0]]
+# set_false_path -to [get_registers *|reset_sync_pldclk_r[*]]
+
+################################################################################
+# End Workround 
+################################################################################
+
+derive_pll_clocks -create_base_clocks
+derive_clock_uncertainty
+
+################################################################################
+# Imports from Example Design (altera/13.1/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/)
+################################################################################
+
+######################################################################
+# HIP Soft reset controller SDC constraints (Gen 3 only)
+set_false_path -to   [get_registers *altpcie_rs_serdes|fifo_err_sync_r[0]]
+set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*]
+
+# HIP testin pins SDC constraints
+set_false_path -from [get_pins -compatibility_mode *hip_ctrl*]
+
+######################################################################
+# Constraints for CV SIG asynchonous logic
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|test_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqout[*]}]
+                                                                                                                                                
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqber[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_lf[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_fs[*]}]
\ No newline at end of file
diff --git a/fpga/altera/de5_qsys/DE5Gen1x8If64/hdl/DE5Gen1x8If64.v b/fpga/altera/de5_qsys/DE5Gen1x8If64/hdl/DE5Gen1x8If64.v
new file mode 100644
index 0000000..37063f4
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen1x8If64/hdl/DE5Gen1x8If64.v
@@ -0,0 +1,369 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            DE5Gen1x8If64.v
+// Version:             
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Altera Stratix V Avalong Streaming Interface to PCI
+//                      Express module and the Terasic DE5 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`timescale 1ps / 1ps
+module DE5Gen1x8If64
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 12,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Quartus IP Library
+      parameter C_PCI_DATA_WIDTH = 64,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      )
+    (
+     // ----------LEDs----------
+     output [7:0]            LED,
+
+     // ----------PCIE----------
+     input                   PCIE_RESET_N,
+     input                   PCIE_REFCLK,
+
+     // ----------PCIE Serial RX----------
+     input [C_NUM_LANES-1:0] PCIE_RX_IN,
+
+     // ----------PCIE Serial TX----------
+     output [C_NUM_LANES-1:0]  PCIE_TX_OUT,
+
+     // ----------Oscillators----------
+     input                   OSC_BANK3D_50MHZ
+     );
+
+    wire                     npor;
+    wire                     pin_perst;
+
+    // ----------TL Config interface----------
+    wire [3:0]               tl_cfg_add;
+    wire [31:0]              tl_cfg_ctl;
+    wire [52:0]              tl_cfg_sts;
+
+    // ----------Rx/TX Interfaces----------
+    wire [0:0]               rx_st_sop;
+    wire [0:0]               rx_st_eop;
+    wire [0:0]               rx_st_err;
+    wire [0:0]               rx_st_valid;
+    wire                     rx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0] rx_st_data;
+    wire [0:0]                  rx_st_empty;
+    
+    wire [0:0]                  tx_st_sop;
+    wire [0:0]                  tx_st_eop;
+    wire [0:0]                  tx_st_err;
+    wire [0:0]                  tx_st_valid;
+    wire                        tx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0] tx_st_data;
+    wire [0:0]                  tx_st_empty;
+    
+    // ----------Clocks & Locks----------
+    wire                        pld_clk;
+    wire                        coreclkout_hip;
+    wire                        refclk;
+    wire                        pld_core_ready;
+    wire                        reset_status;
+    wire                        serdes_pll_locked;
+
+    // ----------Interrupt Interfaces----------
+    wire                        app_msi_req;
+    wire                        app_msi_ack;
+    
+    // ----------Reconfiguration Controller signals----------
+    wire                        mgmt_clk_clk;
+    wire                        mgmt_rst_reset;
+
+    // ----------Reconfiguration Driver Signals----------
+    wire                        reconfig_xcvr_clk;
+    wire                        reconfig_xcvr_rst;
+
+    wire [7:0]                  rx_in;
+    wire [7:0]                  tx_out;
+    
+    // ------------Status Interface------------
+    wire                        derr_cor_ext_rcv;
+    wire                        derr_cor_ext_rpl;
+    wire                        derr_rpl;
+    wire                        dlup;
+    wire                        dlup_exit;
+    wire                        ev128ns;
+    wire                        ev1us;
+    wire                        hotrst_exit;
+    wire [3:0]                  int_status;
+    wire                        l2_exit;
+    wire [3:0]                  lane_act;
+    wire [4:0]                  ltssmstate;
+    wire                        rx_par_err;
+    wire [1:0]                  tx_par_err;
+    wire                        cfg_par_err;
+    wire [7:0]                  ko_cpl_spc_header;
+    wire [11:0]                 ko_cpl_spc_data;
+
+    // ----------Clocks----------
+    assign pld_clk = coreclkout_hip;
+    assign mgmt_clk_clk = PCIE_REFCLK;
+    assign reconfig_xcvr_clk = PCIE_REFCLK;
+    assign refclk = PCIE_REFCLK;
+    assign pld_core_ready = serdes_pll_locked;
+    
+    // ----------Resets----------
+    assign reconfig_xcvr_rst = 1'b0;
+    assign mgmt_rst_reset = 1'b0;
+    assign pin_perst = PCIE_RESET_N;
+    assign npor = PCIE_RESET_N;
+
+    // ----------LED's----------
+    assign LED[7:0] = 8'hff;
+    QSysDE5Gen1x8If64
+        pcie_system_inst
+            (
+             // Outputs
+             .rx_st_startofpacket              (rx_st_sop[0:0]),
+             .rx_st_endofpacket                (rx_st_eop[0:0]),
+             .rx_st_valid                      (rx_st_valid[0:0]),
+             .rx_st_data                       (rx_st_data[63:0]),
+             .tx_st_ready                      (tx_st_ready),
+             .pciehip_reset_status             (reset_status),
+             .pciehip_serdes_pll_locked        (serdes_pll_locked),
+             .pciecfg_tl_cfg_add               (tl_cfg_add[3:0]),
+             .pciecfg_tl_cfg_ctl               (tl_cfg_ctl[31:0]),
+             .pciecfg_tl_cfg_sts               (tl_cfg_sts[52:0]),
+             .pciecoreclk_clk                  (coreclkout_hip),
+             .pcieserial_tx_out0               (PCIE_TX_OUT[0]),
+             .pcieserial_tx_out1               (PCIE_TX_OUT[1]),
+             .pcieserial_tx_out2               (PCIE_TX_OUT[2]),
+             .pcieserial_tx_out3               (PCIE_TX_OUT[3]),
+             .pcieserial_tx_out4               (PCIE_TX_OUT[4]),
+             .pcieserial_tx_out5               (PCIE_TX_OUT[5]),
+             .pcieserial_tx_out6               (PCIE_TX_OUT[6]),
+             .pcieserial_tx_out7               (PCIE_TX_OUT[7]),
+             .pciemsi_app_int_ack              (app_int_ack),
+             .pciemsi_app_msi_ack              (app_msi_ack),
+             .pciestat_derr_cor_ext_rcv        (derr_cor_ext_rcv),
+             .pciestat_derr_cor_ext_rpl        (derr_cor_ext_rpl),
+             .pciestat_derr_rpl                (derr_rpl),
+             .pciestat_dlup                    (dlup),
+             .pciestat_dlup_exit               (dlup_exit),
+             .pciestat_ev128ns                 (ev128ns),
+             .pciestat_ev1us                   (ev1us),
+             .pciestat_hotrst_exit             (hotrst_exit),
+             .pciestat_int_status              (int_status),
+             .pciestat_l2_exit                 (l2_exit),
+             .pciestat_lane_act                (lane_act),
+             .pciestat_ltssmstate              (ltssmstate),
+             .pciestat_rx_par_err              (rx_par_err),
+             .pciestat_tx_par_err              (tx_par_err),
+             .pciestat_cfg_par_err             (cfg_par_err),
+             .pciestat_ko_cpl_spc_header       (ko_cpl_spc_header),
+             .pciestat_ko_cpl_spc_data         (ko_cpl_spc_data),
+             // Inputs
+             .rx_st_ready                      (rx_st_ready),
+             .tx_st_startofpacket              (tx_st_sop[0:0]),
+             .tx_st_endofpacket                (tx_st_eop[0:0]),
+             .tx_st_valid                      (tx_st_valid[0:0]),
+             .tx_st_data                       (tx_st_data[63:0]),
+             .pciehip_pld_core_ready           (pld_core_ready),
+             .pcienpor_npor                    (npor),
+             .pcienpor_pin_perst               (pin_perst),
+             .pcierefclk_clk                   (refclk),
+             .reconfigrefclk_clk               (reconfig_xcvr_clk),
+             .pciepld_clk                      (pld_clk),
+             .reconfigrst_reset                (reconfig_xcvr_rst),
+             .mgmtrst_reset                    (mgmt_rst_reset),
+             .mgmtclk_clk                      (mgmt_clk_clk),
+             .reconfigpldclk_clk               (pld_clk),
+             .pcieserial_rx_in0                (PCIE_RX_IN[0]),
+             .pcieserial_rx_in1                (PCIE_RX_IN[1]),
+             .pcieserial_rx_in2                (PCIE_RX_IN[2]),
+             .pcieserial_rx_in3                (PCIE_RX_IN[3]),
+             .pcieserial_rx_in4                (PCIE_RX_IN[4]),
+             .pcieserial_rx_in5                (PCIE_RX_IN[5]),
+             .pcieserial_rx_in6                (PCIE_RX_IN[6]),
+             .pcieserial_rx_in7                (PCIE_RX_IN[7]),
+             .pciemsi_app_msi_req              (app_msi_req),
+             .drvstat_derr_cor_ext_rcv         (derr_cor_ext_rcv),
+             .drvstat_derr_cor_ext_rpl         (derr_cor_ext_rpl),
+             .drvstat_derr_rpl                 (derr_rpl),
+             .drvstat_dlup                     (dlup),
+             .drvstat_dlup_exit                (dlup_exit),
+             .drvstat_ev128ns                  (ev128ns),
+             .drvstat_ev1us                    (ev1us),
+             .drvstat_hotrst_exit              (hotrst_exit),
+             .drvstat_int_status               (int_status),
+             .drvstat_l2_exit                  (l2_exit),
+             .drvstat_lane_act                 (lane_act),
+             .drvstat_ltssmstate               (ltssmstate),
+             .drvstat_rx_par_err               (rx_par_err),
+             .drvstat_tx_par_err               (tx_par_err),
+             .drvstat_cfg_par_err              (cfg_par_err),
+             .drvstat_ko_cpl_spc_header        (ko_cpl_spc_header),
+             .drvstat_ko_cpl_spc_data          (ko_cpl_spc_data));
+
+    // -------------------- END ALTERA IP INSTANTIATION  --------------------
+    // -------------------- BEGIN RIFFA INSTANTAION --------------------
+
+    // RIFFA channel interface
+    wire                        rst_out;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_clk;
+    wire [C_NUM_CHNL-1:0]       chnl_rx;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_ack;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_last;
+    wire [(C_NUM_CHNL*32)-1:0]  chnl_rx_len;
+    wire [(C_NUM_CHNL*31)-1:0]  chnl_rx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_ren;
+    
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_clk;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_last;
+    wire [(C_NUM_CHNL*32)-1:0]               chnl_tx_len;
+    wire [(C_NUM_CHNL*31)-1:0]               chnl_tx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_ren;
+
+    wire                                     chnl_reset;
+    wire                                     chnl_clk;
+    wire                                     riffa_reset;
+    wire                                     riffa_clk;
+    assign riffa_reset = reset_status;
+    assign riffa_clk = pld_clk;
+    assign chnl_clk = pld_clk;
+    assign chnl_reset = rst_out;
+    
+    riffa_wrapper_de5
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .RX_ST_READY                   (rx_st_ready),
+         .TX_ST_DATA                    (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (tx_st_valid[0:0]),
+         .TX_ST_EOP                     (tx_st_eop[0:0]),
+         .TX_ST_SOP                     (tx_st_sop[0:0]),
+         .TX_ST_EMPTY                   (tx_st_empty[0:0]),
+         .APP_MSI_REQ                   (app_msi_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .RX_ST_DATA                    (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (rx_st_eop[0:0]),
+         .RX_ST_SOP                     (rx_st_sop[0:0]),
+         .RX_ST_VALID                   (rx_st_valid[0:0]),
+         .RX_ST_EMPTY                   (rx_st_empty[0:0]),
+         .TX_ST_READY                   (tx_st_ready),
+         .TL_CFG_CTL                    (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]),
+         .KO_CPL_SPC_DATA               (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]),
+         .APP_MSI_ACK                   (app_msi_ack),
+         .PLD_CLK                       (pld_clk),
+         .RESET_STATUS                  (reset_status),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+
+    // --------------------  END RIFFA INSTANTAION --------------------
+    // --------------------  BEGIN USER CODE  --------------------
+    genvar                                   i;
+    generate
+        for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
+            // Instantiate and assign modules to RIFFA channels. Users should 
+            // replace the chnl_tester instantiation with their own core.
+            chnl_tester 
+                 #(
+                   .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                   )
+            chnl_tester_i
+                 (
+
+                  .CLK(chnl_clk),
+                  .RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
+                  // Rx interface
+                  .CHNL_RX_CLK(chnl_rx_clk[i]), 
+                  .CHNL_RX(chnl_rx[i]), 
+                  .CHNL_RX_ACK(chnl_rx_ack[i]), 
+                  .CHNL_RX_LAST(chnl_rx_last[i]), 
+                  .CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]), 
+                  .CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
+                  // Tx interface
+                  .CHNL_TX_CLK(chnl_tx_clk[i]), 
+                  .CHNL_TX(chnl_tx[i]), 
+                  .CHNL_TX_ACK(chnl_tx_ack[i]), 
+                  .CHNL_TX_LAST(chnl_tx_last[i]), 
+                  .CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]), 
+                  .CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
+                  );    
+        end
+    endgenerate
+    // --------------------  END USER CODE  --------------------
+endmodule
diff --git a/fpga/altera/de5_qsys/DE5Gen1x8If64/ip/.qsys_edit/QSysDE5Gen1x8If64_schematic.nlv b/fpga/altera/de5_qsys/DE5Gen1x8If64/ip/.qsys_edit/QSysDE5Gen1x8If64_schematic.nlv
new file mode 100644
index 0000000..e69de29
diff --git a/fpga/altera/de5_qsys/DE5Gen1x8If64/ip/.qsys_edit/filters.xml b/fpga/altera/de5_qsys/DE5Gen1x8If64/ip/.qsys_edit/filters.xml
new file mode 100644
index 0000000..095b97a
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen1x8If64/ip/.qsys_edit/filters.xml
@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="14.1" />
diff --git a/fpga/altera/de5_qsys/DE5Gen1x8If64/ip/.qsys_edit/preferences.xml b/fpga/altera/de5_qsys/DE5Gen1x8If64/ip/.qsys_edit/preferences.xml
new file mode 100644
index 0000000..6552856
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen1x8If64/ip/.qsys_edit/preferences.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <debug showDebugMenu="0" />
+ <systemtable filter="All Interfaces">
+  <columns>
+   <connections preferredWidth="143" />
+   <irq preferredWidth="34" />
+  </columns>
+ </systemtable>
+ <library expandedCategories="Project,Library" />
+ <window width="1682" height="1050" x="-1" y="0" />
+</preferences>
diff --git a/fpga/altera/de5_qsys/DE5Gen1x8If64/ip/QSysDE5Gen1x8If64.qsys b/fpga/altera/de5_qsys/DE5Gen1x8If64/ip/QSysDE5Gen1x8If64.qsys
new file mode 100644
index 0000000..f16dc27
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen1x8If64/ip/QSysDE5Gen1x8If64.qsys
@@ -0,0 +1,664 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Stratix V";
+         type = "String";
+      }
+   }
+   element PCIeGen1x8If64
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element XCVRCtrlGen1x8
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element XCVRDrvGen1x8
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element clk_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="5SGXEA7N2F45C2" />
+ <parameter name="deviceFamily" value="Stratix V" />
+ <parameter name="deviceSpeedGrade" value="2_H2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="drvstat"
+   internal="XCVRDrvGen1x8.hip_status_drv"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="mgmtclk"
+   internal="XCVRCtrlGen1x8.mgmt_clk_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="mgmtrst"
+   internal="XCVRCtrlGen1x8.mgmt_rst_reset"
+   type="reset"
+   dir="end" />
+ <interface
+   name="pciecfg"
+   internal="PCIeGen1x8If64.config_tl"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pciecoreclk"
+   internal="PCIeGen1x8If64.coreclkout_hip"
+   type="clock"
+   dir="start" />
+ <interface
+   name="pciehip"
+   internal="PCIeGen1x8If64.hip_rst"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pciemsi"
+   internal="PCIeGen1x8If64.int_msi"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pcienpor"
+   internal="PCIeGen1x8If64.npor"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pciepld"
+   internal="PCIeGen1x8If64.pld_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="pcierefclk"
+   internal="PCIeGen1x8If64.refclk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="pcieserial"
+   internal="PCIeGen1x8If64.hip_serial"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pciestat"
+   internal="PCIeGen1x8If64.hip_status"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reconfigpldclk"
+   internal="XCVRDrvGen1x8.pld_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="reconfigrefclk"
+   internal="XCVRDrvGen1x8.reconfig_xcvr_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="reconfigrst"
+   internal="XCVRDrvGen1x8.reconfig_xcvr_rst"
+   type="reset"
+   dir="end" />
+ <interface name="reset" internal="clk_0.clk_in_reset" />
+ <interface
+   name="rx_st"
+   internal="PCIeGen1x8If64.rx_st"
+   type="avalon_streaming"
+   dir="start" />
+ <interface
+   name="tx_st"
+   internal="PCIeGen1x8If64.tx_st"
+   type="avalon_streaming"
+   dir="end" />
+ <module
+   name="PCIeGen1x8If64"
+   kind="altera_pcie_sv_hip_ast"
+   version="14.1"
+   enabled="1">
+  <parameter name="INTENDED_DEVICE_FAMILY" value="Stratix V" />
+  <parameter name="advanced_default_hwtcl_atomic_malformed" value="true" />
+  <parameter name="advanced_default_hwtcl_atomic_op_completer_32bit" value="false" />
+  <parameter name="advanced_default_hwtcl_atomic_op_completer_64bit" value="false" />
+  <parameter name="advanced_default_hwtcl_atomic_op_routing" value="false" />
+  <parameter name="advanced_default_hwtcl_bridge_port_ssid_support" value="false" />
+  <parameter name="advanced_default_hwtcl_bridge_port_vga_enable" value="false" />
+  <parameter name="advanced_default_hwtcl_bypass_cdc" value="false" />
+  <parameter name="advanced_default_hwtcl_cas_completer_128bit" value="false" />
+  <parameter name="advanced_default_hwtcl_cdc_dummy_insert_limit" value="11" />
+  <parameter name="advanced_default_hwtcl_d0_pme" value="false" />
+  <parameter name="advanced_default_hwtcl_d1_pme" value="false" />
+  <parameter name="advanced_default_hwtcl_d1_support" value="false" />
+  <parameter name="advanced_default_hwtcl_d2_pme" value="false" />
+  <parameter name="advanced_default_hwtcl_d2_support" value="false" />
+  <parameter name="advanced_default_hwtcl_d3_cold_pme" value="false" />
+  <parameter name="advanced_default_hwtcl_d3_hot_pme" value="false" />
+  <parameter name="advanced_default_hwtcl_data_pack_rx" value="disable" />
+  <parameter name="advanced_default_hwtcl_deskew_comma" value="com_deskw" />
+  <parameter name="advanced_default_hwtcl_device_number" value="0" />
+  <parameter name="advanced_default_hwtcl_disable_link_x2_support" value="false" />
+  <parameter name="advanced_default_hwtcl_disable_snoop_packet" value="false" />
+  <parameter name="advanced_default_hwtcl_ei_delay_powerdown_count" value="10" />
+  <parameter name="advanced_default_hwtcl_eie_before_nfts_count" value="4" />
+  <parameter
+     name="advanced_default_hwtcl_enable_adapter_half_rate_mode"
+     value="false" />
+  <parameter name="advanced_default_hwtcl_enable_l1_aspm" value="false" />
+  <parameter name="advanced_default_hwtcl_enable_rx_buffer_checking" value="false" />
+  <parameter name="advanced_default_hwtcl_extended_format_field" value="false" />
+  <parameter name="advanced_default_hwtcl_extended_tag_reset" value="false" />
+  <parameter name="advanced_default_hwtcl_fc_init_timer" value="1024" />
+  <parameter name="advanced_default_hwtcl_flow_control_timeout_count" value="200" />
+  <parameter name="advanced_default_hwtcl_flow_control_update_count" value="30" />
+  <parameter name="advanced_default_hwtcl_flr_capability" value="false" />
+  <parameter name="advanced_default_hwtcl_gen2_diffclock_nfts_count" value="255" />
+  <parameter name="advanced_default_hwtcl_gen2_sameclock_nfts_count" value="255" />
+  <parameter name="advanced_default_hwtcl_hot_plug_support" value="0" />
+  <parameter name="advanced_default_hwtcl_interrupt_pin" value="inta" />
+  <parameter name="advanced_default_hwtcl_l01_entry_latency" value="31" />
+  <parameter name="advanced_default_hwtcl_l0_exit_latency_diffclock" value="6" />
+  <parameter name="advanced_default_hwtcl_l0_exit_latency_sameclock" value="6" />
+  <parameter name="advanced_default_hwtcl_l1_exit_latency_diffclock" value="0" />
+  <parameter name="advanced_default_hwtcl_l1_exit_latency_sameclock" value="0" />
+  <parameter name="advanced_default_hwtcl_low_priority_vc" value="single_vc" />
+  <parameter name="advanced_default_hwtcl_ltr_mechanism" value="false" />
+  <parameter name="advanced_default_hwtcl_ltssm_1ms_timeout" value="disable" />
+  <parameter name="advanced_default_hwtcl_ltssm_freqlocked_check" value="disable" />
+  <parameter name="advanced_default_hwtcl_maximum_current" value="0" />
+  <parameter name="advanced_default_hwtcl_no_command_completed" value="true" />
+  <parameter name="advanced_default_hwtcl_no_soft_reset" value="false" />
+  <parameter name="advanced_default_hwtcl_pclk_out_sel" value="pclk" />
+  <parameter name="advanced_default_hwtcl_pipex1_debug_sel" value="disable" />
+  <parameter name="advanced_default_hwtcl_register_pipe_signals" value="false" />
+  <parameter name="advanced_default_hwtcl_reserved_debug" value="0" />
+  <parameter
+     name="advanced_default_hwtcl_retry_buffer_last_active_address"
+     value="2047" />
+  <parameter name="advanced_default_hwtcl_rx_l0s_count_idl" value="0" />
+  <parameter name="advanced_default_hwtcl_set_l0s" value="0" />
+  <parameter name="advanced_default_hwtcl_skp_os_gen3_count" value="0" />
+  <parameter name="advanced_default_hwtcl_skp_os_schedule_count" value="0" />
+  <parameter name="advanced_default_hwtcl_ssid" value="0" />
+  <parameter name="advanced_default_hwtcl_ssvid" value="0" />
+  <parameter name="advanced_default_hwtcl_tph_completer" value="false" />
+  <parameter name="advanced_default_hwtcl_tx_cdc_almost_empty" value="5" />
+  <parameter name="advanced_default_hwtcl_vc0_clk_enable" value="true" />
+  <parameter name="advanced_default_hwtcl_wrong_device_id" value="disable" />
+  <parameter name="advanced_default_parameter_override" value="0" />
+  <parameter name="ast_width_hwtcl" value="Avalon-ST 64-bit" />
+  <parameter name="bar0_size_mask_hwtcl" value="10" />
+  <parameter name="bar0_type_hwtcl" value="2" />
+  <parameter name="bar1_size_mask_hwtcl" value="0" />
+  <parameter name="bar1_type_hwtcl" value="0" />
+  <parameter name="bar2_size_mask_hwtcl" value="0" />
+  <parameter name="bar2_type_hwtcl" value="0" />
+  <parameter name="bar3_size_mask_hwtcl" value="0" />
+  <parameter name="bar3_type_hwtcl" value="0" />
+  <parameter name="bar4_size_mask_hwtcl" value="0" />
+  <parameter name="bar4_type_hwtcl" value="0" />
+  <parameter name="bar5_size_mask_hwtcl" value="0" />
+  <parameter name="bar5_type_hwtcl" value="0" />
+  <parameter name="change_deemphasis_hwtcl" value="0" />
+  <parameter name="class_code_hwtcl" value="0" />
+  <parameter name="completion_timeout_hwtcl" value="ABCD" />
+  <parameter name="design_environment_hwtcl" value="QSYS" />
+  <parameter name="device_id_hwtcl" value="1" />
+  <parameter name="dll_active_report_support_hwtcl" value="0" />
+  <parameter name="ecrc_check_capable_hwtcl" value="0" />
+  <parameter name="ecrc_gen_capable_hwtcl" value="0" />
+  <parameter name="enable_completion_timeout_disable_hwtcl" value="1" />
+  <parameter name="enable_function_msix_support_hwtcl" value="0" />
+  <parameter name="enable_pcisigtest_hwtcl" value="0" />
+  <parameter name="enable_pipe32_phyip_ser_driver_hwtcl" value="0" />
+  <parameter name="enable_pipe32_sim_hwtcl" value="0" />
+  <parameter name="enable_power_on_rst_pulse_hwtcl" value="0" />
+  <parameter name="enable_slot_register_hwtcl" value="0" />
+  <parameter name="enable_tl_only_sim_hwtcl" value="0" />
+  <parameter name="endpoint_l0_latency_hwtcl" value="0" />
+  <parameter name="endpoint_l1_latency_hwtcl" value="0" />
+  <parameter name="expansion_base_address_register_hwtcl" value="0" />
+  <parameter name="extend_tag_field_hwtcl" value="64" />
+  <parameter name="fixed_preset_on" value="0" />
+  <parameter name="force_hrc" value="0" />
+  <parameter name="force_src" value="0" />
+  <parameter name="full_swing_hwtcl" value="35" />
+  <parameter name="gen123_lane_rate_mode_hwtcl" value="Gen1 (2.5 Gbps)" />
+  <parameter name="gen3_coeff_10_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_nxtber_less_hwtcl">g3_coeff_10_nxtber_less</parameter>
+  <parameter name="gen3_coeff_10_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_nxtber_more_hwtcl">g3_coeff_10_nxtber_more</parameter>
+  <parameter name="gen3_coeff_10_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_sel_hwtcl" value="preset_10" />
+  <parameter name="gen3_coeff_11_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_nxtber_less_hwtcl">g3_coeff_11_nxtber_less</parameter>
+  <parameter name="gen3_coeff_11_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_nxtber_more_hwtcl">g3_coeff_11_nxtber_more</parameter>
+  <parameter name="gen3_coeff_11_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_sel_hwtcl" value="preset_11" />
+  <parameter name="gen3_coeff_12_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_nxtber_less_hwtcl">g3_coeff_12_nxtber_less</parameter>
+  <parameter name="gen3_coeff_12_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_nxtber_more_hwtcl">g3_coeff_12_nxtber_more</parameter>
+  <parameter name="gen3_coeff_12_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_sel_hwtcl" value="preset_12" />
+  <parameter name="gen3_coeff_13_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_nxtber_less_hwtcl">g3_coeff_13_nxtber_less</parameter>
+  <parameter name="gen3_coeff_13_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_nxtber_more_hwtcl">g3_coeff_13_nxtber_more</parameter>
+  <parameter name="gen3_coeff_13_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_sel_hwtcl" value="preset_13" />
+  <parameter name="gen3_coeff_14_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_nxtber_less_hwtcl">g3_coeff_14_nxtber_less</parameter>
+  <parameter name="gen3_coeff_14_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_nxtber_more_hwtcl">g3_coeff_14_nxtber_more</parameter>
+  <parameter name="gen3_coeff_14_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_sel_hwtcl" value="preset_14" />
+  <parameter name="gen3_coeff_15_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_nxtber_less_hwtcl">g3_coeff_15_nxtber_less</parameter>
+  <parameter name="gen3_coeff_15_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_nxtber_more_hwtcl">g3_coeff_15_nxtber_more</parameter>
+  <parameter name="gen3_coeff_15_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_sel_hwtcl" value="preset_15" />
+  <parameter name="gen3_coeff_16_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_nxtber_less_hwtcl">g3_coeff_16_nxtber_less</parameter>
+  <parameter name="gen3_coeff_16_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_nxtber_more_hwtcl">g3_coeff_16_nxtber_more</parameter>
+  <parameter name="gen3_coeff_16_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_sel_hwtcl" value="preset_16" />
+  <parameter name="gen3_coeff_17_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_nxtber_less_hwtcl">g3_coeff_17_nxtber_less</parameter>
+  <parameter name="gen3_coeff_17_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_nxtber_more_hwtcl">g3_coeff_17_nxtber_more</parameter>
+  <parameter name="gen3_coeff_17_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_sel_hwtcl" value="preset_17" />
+  <parameter name="gen3_coeff_18_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_nxtber_less_hwtcl">g3_coeff_18_nxtber_less</parameter>
+  <parameter name="gen3_coeff_18_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_nxtber_more_hwtcl">g3_coeff_18_nxtber_more</parameter>
+  <parameter name="gen3_coeff_18_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_sel_hwtcl" value="preset_18" />
+  <parameter name="gen3_coeff_19_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_nxtber_less_hwtcl">g3_coeff_19_nxtber_less</parameter>
+  <parameter name="gen3_coeff_19_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_nxtber_more_hwtcl">g3_coeff_19_nxtber_more</parameter>
+  <parameter name="gen3_coeff_19_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_sel_hwtcl" value="preset_19" />
+  <parameter name="gen3_coeff_1_ber_meas_hwtcl" value="2" />
+  <parameter name="gen3_coeff_1_hwtcl" value="7" />
+  <parameter name="gen3_coeff_1_nxtber_less_hwtcl">g3_coeff_1_nxtber_less</parameter>
+  <parameter name="gen3_coeff_1_nxtber_less_ptr_hwtcl" value="1" />
+  <parameter name="gen3_coeff_1_nxtber_more_hwtcl">g3_coeff_1_nxtber_more</parameter>
+  <parameter name="gen3_coeff_1_nxtber_more_ptr_hwtcl" value="1" />
+  <parameter name="gen3_coeff_1_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_1_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_1_sel_hwtcl" value="preset_1" />
+  <parameter name="gen3_coeff_20_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_nxtber_less_hwtcl">g3_coeff_20_nxtber_less</parameter>
+  <parameter name="gen3_coeff_20_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_nxtber_more_hwtcl">g3_coeff_20_nxtber_more</parameter>
+  <parameter name="gen3_coeff_20_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_sel_hwtcl" value="preset_20" />
+  <parameter name="gen3_coeff_21_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_nxtber_less_hwtcl">g3_coeff_21_nxtber_less</parameter>
+  <parameter name="gen3_coeff_21_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_nxtber_more_hwtcl">g3_coeff_21_nxtber_more</parameter>
+  <parameter name="gen3_coeff_21_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_sel_hwtcl" value="preset_21" />
+  <parameter name="gen3_coeff_22_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_nxtber_less_hwtcl">g3_coeff_22_nxtber_less</parameter>
+  <parameter name="gen3_coeff_22_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_nxtber_more_hwtcl">g3_coeff_22_nxtber_more</parameter>
+  <parameter name="gen3_coeff_22_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_sel_hwtcl" value="preset_22" />
+  <parameter name="gen3_coeff_23_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_nxtber_less_hwtcl">g3_coeff_23_nxtber_less</parameter>
+  <parameter name="gen3_coeff_23_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_nxtber_more_hwtcl">g3_coeff_23_nxtber_more</parameter>
+  <parameter name="gen3_coeff_23_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_sel_hwtcl" value="preset_23" />
+  <parameter name="gen3_coeff_24_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_nxtber_less_hwtcl">g3_coeff_24_nxtber_less</parameter>
+  <parameter name="gen3_coeff_24_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_nxtber_more_hwtcl">g3_coeff_24_nxtber_more</parameter>
+  <parameter name="gen3_coeff_24_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_sel_hwtcl" value="preset_24" />
+  <parameter name="gen3_coeff_2_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_nxtber_less_hwtcl">g3_coeff_2_nxtber_less</parameter>
+  <parameter name="gen3_coeff_2_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_nxtber_more_hwtcl">g3_coeff_2_nxtber_more</parameter>
+  <parameter name="gen3_coeff_2_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_sel_hwtcl" value="preset_2" />
+  <parameter name="gen3_coeff_3_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_nxtber_less_hwtcl">g3_coeff_3_nxtber_less</parameter>
+  <parameter name="gen3_coeff_3_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_nxtber_more_hwtcl">g3_coeff_3_nxtber_more</parameter>
+  <parameter name="gen3_coeff_3_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_sel_hwtcl" value="preset_3" />
+  <parameter name="gen3_coeff_4_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_nxtber_less_hwtcl">g3_coeff_4_nxtber_less</parameter>
+  <parameter name="gen3_coeff_4_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_nxtber_more_hwtcl">g3_coeff_4_nxtber_more</parameter>
+  <parameter name="gen3_coeff_4_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_sel_hwtcl" value="preset_4" />
+  <parameter name="gen3_coeff_5_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_nxtber_less_hwtcl">g3_coeff_5_nxtber_less</parameter>
+  <parameter name="gen3_coeff_5_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_nxtber_more_hwtcl">g3_coeff_5_nxtber_more</parameter>
+  <parameter name="gen3_coeff_5_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_sel_hwtcl" value="preset_5" />
+  <parameter name="gen3_coeff_6_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_nxtber_less_hwtcl">g3_coeff_6_nxtber_less</parameter>
+  <parameter name="gen3_coeff_6_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_nxtber_more_hwtcl">g3_coeff_6_nxtber_more</parameter>
+  <parameter name="gen3_coeff_6_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_sel_hwtcl" value="preset_6" />
+  <parameter name="gen3_coeff_7_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_nxtber_less_hwtcl">g3_coeff_7_nxtber_less</parameter>
+  <parameter name="gen3_coeff_7_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_nxtber_more_hwtcl">g3_coeff_7_nxtber_more</parameter>
+  <parameter name="gen3_coeff_7_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_sel_hwtcl" value="preset_7" />
+  <parameter name="gen3_coeff_8_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_nxtber_less_hwtcl">g3_coeff_8_nxtber_less</parameter>
+  <parameter name="gen3_coeff_8_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_nxtber_more_hwtcl">g3_coeff_8_nxtber_more</parameter>
+  <parameter name="gen3_coeff_8_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_sel_hwtcl" value="preset_8" />
+  <parameter name="gen3_coeff_9_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_nxtber_less_hwtcl">g3_coeff_9_nxtber_less</parameter>
+  <parameter name="gen3_coeff_9_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_nxtber_more_hwtcl">g3_coeff_9_nxtber_more</parameter>
+  <parameter name="gen3_coeff_9_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_sel_hwtcl" value="preset_9" />
+  <parameter name="gen3_full_swing_hwtcl" value="35" />
+  <parameter name="gen3_low_freq_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_10_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_11_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_1_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_2_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_3_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_4_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_5_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_6_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_7_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_8_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_9_hwtcl" value="0" />
+  <parameter name="gen3_rxfreqlock_counter_hwtcl" value="0" />
+  <parameter name="hip_reconfig_hwtcl" value="0" />
+  <parameter name="hip_tag_checking_hwtcl" value="1" />
+  <parameter name="hwtcl_override_g2_txvod" value="1" />
+  <parameter name="hwtcl_override_g3rxcoef" value="0" />
+  <parameter name="hwtcl_override_g3txcoef" value="0" />
+  <parameter name="in_cvp_mode_hwtcl" value="0" />
+  <parameter name="io_window_addr_width_hwtcl" value="0" />
+  <parameter name="lane_mask_hwtcl" value="x8" />
+  <parameter name="low_latency_mode_hwtcl" value="0" />
+  <parameter name="max_payload_size_hwtcl" value="256" />
+  <parameter name="msi_64bit_addressing_capable_hwtcl" value="true" />
+  <parameter name="msi_masking_capable_hwtcl" value="false" />
+  <parameter name="msi_multi_message_capable_hwtcl" value="1" />
+  <parameter name="msi_support_hwtcl" value="true" />
+  <parameter name="msix_pba_bir_hwtcl" value="0" />
+  <parameter name="msix_pba_offset_hwtcl" value="0" />
+  <parameter name="msix_table_bir_hwtcl" value="0" />
+  <parameter name="msix_table_offset_hwtcl" value="0" />
+  <parameter name="msix_table_size_hwtcl" value="0" />
+  <parameter name="multiple_packets_per_cycle_hwtcl" value="0" />
+  <parameter name="override_rxbuffer_cred_preset" value="0" />
+  <parameter name="override_tbpartner_driver_setting_hwtcl" value="0" />
+  <parameter name="pcie_inspector_hwtcl" value="0" />
+  <parameter name="pcie_qsys" value="1" />
+  <parameter name="pcie_spec_version_hwtcl" value="2.1" />
+  <parameter name="pll_refclk_freq_hwtcl" value="100 MHz" />
+  <parameter name="port_link_number_hwtcl" value="1" />
+  <parameter name="port_type_hwtcl" value="Native endpoint" />
+  <parameter name="prefetchable_mem_window_addr_width_hwtcl" value="0" />
+  <parameter name="revision_id_hwtcl" value="1" />
+  <parameter name="rpre_emph_a_val_hwtcl" value="9" />
+  <parameter name="rpre_emph_b_val_hwtcl" value="0" />
+  <parameter name="rpre_emph_c_val_hwtcl" value="16" />
+  <parameter name="rpre_emph_d_val_hwtcl" value="13" />
+  <parameter name="rpre_emph_e_val_hwtcl" value="5" />
+  <parameter name="rvod_sel_a_val_hwtcl" value="42" />
+  <parameter name="rvod_sel_b_val_hwtcl" value="38" />
+  <parameter name="rvod_sel_c_val_hwtcl" value="38" />
+  <parameter name="rvod_sel_d_val_hwtcl" value="43" />
+  <parameter name="rvod_sel_e_val_hwtcl" value="15" />
+  <parameter name="rxbuffer_rxreq_hwtcl" value="Minimum" />
+  <parameter name="serial_sim_hwtcl" value="1" />
+  <parameter name="set_pld_clk_x1_625MHz_hwtcl" value="0" />
+  <parameter name="slot_number_hwtcl" value="0" />
+  <parameter name="slot_power_limit_hwtcl" value="0" />
+  <parameter name="slot_power_scale_hwtcl" value="0" />
+  <parameter name="slotclkcfg_hwtcl" value="1" />
+  <parameter name="subsystem_device_id_hwtcl" value="0" />
+  <parameter name="subsystem_vendor_id_hwtcl" value="0" />
+  <parameter name="surprise_down_error_support_hwtcl" value="0" />
+  <parameter name="tlp_insp_trg_dw0_hwtcl" value="2049" />
+  <parameter name="tlp_insp_trg_dw1_hwtcl" value="0" />
+  <parameter name="tlp_insp_trg_dw2_hwtcl" value="0" />
+  <parameter name="tlp_insp_trg_dw3_hwtcl" value="0" />
+  <parameter name="tlp_inspector_hwtcl" value="0" />
+  <parameter name="tlp_inspector_use_signal_probe_hwtcl" value="0" />
+  <parameter name="track_rxfc_cplbuf_ovf_hwtcl" value="0" />
+  <parameter name="use_aer_hwtcl" value="0" />
+  <parameter name="use_ast_parity" value="0" />
+  <parameter name="use_atx_pll_hwtcl" value="0" />
+  <parameter name="use_config_bypass_hwtcl" value="0" />
+  <parameter name="use_crc_forwarding_hwtcl" value="0" />
+  <parameter name="use_cvp_update_core_pof_hwtcl" value="0" />
+  <parameter name="use_pci_ext_hwtcl" value="0" />
+  <parameter name="use_pcie_ext_hwtcl" value="0" />
+  <parameter name="use_rx_st_be_hwtcl" value="0" />
+  <parameter name="use_tx_cons_cred_sel_hwtcl" value="0" />
+  <parameter name="user_id_hwtcl" value="0" />
+  <parameter name="vendor_id_hwtcl" value="4466" />
+  <parameter name="vsec_id_hwtcl" value="40960" />
+  <parameter name="vsec_rev_hwtcl" value="0" />
+ </module>
+ <module
+   name="XCVRCtrlGen1x8"
+   kind="alt_xcvr_reconfig"
+   version="14.1"
+   enabled="1">
+  <parameter name="ber_en" value="0" />
+  <parameter name="device_family" value="Stratix V" />
+  <parameter name="enable_adce" value="0" />
+  <parameter name="enable_analog" value="1" />
+  <parameter name="enable_dcd" value="0" />
+  <parameter name="enable_dcd_power_up" value="1" />
+  <parameter name="enable_dfe" value="0" />
+  <parameter name="enable_eyemon" value="0" />
+  <parameter name="enable_mif" value="0" />
+  <parameter name="enable_offset" value="1" />
+  <parameter name="gui_cal_status_port" value="false" />
+  <parameter name="gui_enable_pll" value="0" />
+  <parameter name="gui_split_sizes" value="" />
+  <parameter name="number_of_reconfig_interfaces" value="10" />
+ </module>
+ <module
+   name="XCVRDrvGen1x8"
+   kind="altera_pcie_reconfig_driver"
+   version="14.1"
+   enabled="1">
+  <parameter name="INTENDED_DEVICE_FAMILY" value="Stratix V" />
+  <parameter name="enable_cal_busy_hwtcl" value="0" />
+  <parameter name="gen123_lane_rate_mode_hwtcl" value="Gen1 (2.5 Gbps)" />
+  <parameter name="number_of_reconfig_interfaces" value="10" />
+ </module>
+ <module name="clk_0" kind="clock_source" version="14.1" enabled="0">
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <connection
+   kind="avalon"
+   version="14.1"
+   start="XCVRDrvGen1x8.reconfig_mgmt"
+   end="XCVRCtrlGen1x8.reconfig_mgmt">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="XCVRDrvGen1x8.hip_currentspeed"
+   end="PCIeGen1x8If64.hip_currentspeed">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="XCVRDrvGen1x8.reconfig_busy"
+   end="XCVRCtrlGen1x8.reconfig_busy">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="XCVRCtrlGen1x8.reconfig_from_xcvr"
+   end="PCIeGen1x8If64.reconfig_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="XCVRCtrlGen1x8.reconfig_to_xcvr"
+   end="PCIeGen1x8If64.reconfig_to_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/fpga/altera/de5_qsys/DE5Gen1x8If64/ip/README.txt b/fpga/altera/de5_qsys/DE5Gen1x8If64/ip/README.txt
new file mode 100644
index 0000000..e69de29
diff --git a/fpga/altera/de5_qsys/DE5Gen1x8If64/prj/DE5Gen1x8If64.qpf b/fpga/altera/de5_qsys/DE5Gen1x8If64/prj/DE5Gen1x8If64.qpf
new file mode 100644
index 0000000..cc8c63f
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen1x8If64/prj/DE5Gen1x8If64.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 16:27:01  June 09, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:27:01  June 09, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "DE5Gen1x8If64"
diff --git a/fpga/altera/de5_qsys/DE5Gen1x8If64/prj/DE5Gen1x8If64.qsf b/fpga/altera/de5_qsys/DE5Gen1x8If64/prj/DE5Gen1x8If64.qsf
new file mode 100644
index 0000000..093d85d
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen1x8If64/prj/DE5Gen1x8If64.qsf
@@ -0,0 +1,474 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 11:03:06  March 21, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		DE5Gen1x8If64_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Stratix V"
+set_global_assignment -name DEVICE 5SGXEA7N2F45C2
+set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen1x8If64
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06  MARCH 21, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION "14.1.0 SP0.19"
+
+################################################################################
+# Timing SDC Files
+################################################################################
+
+################################################################################
+# PCIE Connections
+################################################################################
+# PCIe clk (100 MHz)
+set_location_assignment PIN_AK38 -to PCIE_REFCLK
+set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK
+
+set_location_assignment PIN_AK39 -to "PCIE_REFCLK(n)"
+set_instance_assignment -name IO_STANDARD HCSL -to "PCIE_REFCLK(n)"
+
+set_location_assignment PIN_AU33 -to PCIE_RESET_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_RESET_N
+
+################################################################################
+#PCIE Pins
+################################################################################
+# Settings from SV PCIE User Guide (AV-ST)
+# 100 Ohm Termination 
+# 1.5V PCML 
+# XCVR_VCCR_VCCT_VOLTAGE 0_9V (GEN 1/2 CMU)
+# XCVR_VCCA_VOLTAGE 2_5V (GEN 1/2 CMU)
+# We use CMU PLL's (http://www.altera.com/literature/hb/stratix-v/stx5_52003.pdf)
+
+################################################################################
+#PCIE RX_IN 0
+################################################################################
+
+set_location_assignment PIN_BB43 -to PCIE_RX_IN[0]
+set_location_assignment PIN_BB44 -to "PCIE_RX_IN[0](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[0]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[0](n)"
+
+################################################################################
+#PCIE RX_IN 1
+################################################################################
+
+set_location_assignment PIN_BA41 -to PCIE_RX_IN[1]
+set_location_assignment PIN_BA42 -to "PCIE_RX_IN[1](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[1]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[1](n)"
+
+################################################################################
+#PCIE RX_IN 2
+################################################################################
+
+set_location_assignment PIN_AW41 -to PCIE_RX_IN[2]
+set_location_assignment PIN_AW42 -to "PCIE_RX_IN[2](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[2]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[2](n)"
+
+################################################################################
+#PCIE RX_IN 3
+################################################################################
+
+set_location_assignment PIN_AY43 -to PCIE_RX_IN[3]
+set_location_assignment PIN_AY44 -to "PCIE_RX_IN[3](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[3]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[3](n)"
+
+################################################################################
+#PCIE RX_IN 4
+################################################################################
+
+set_location_assignment PIN_AT43 -to PCIE_RX_IN[4]
+set_location_assignment PIN_AT44 -to "PCIE_RX_IN[4](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[4]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[4](n)"
+
+################################################################################
+#PCIE RX_IN 5
+################################################################################
+
+set_location_assignment PIN_AP43 -to PCIE_RX_IN[5]
+set_location_assignment PIN_AP44 -to "PCIE_RX_IN[5](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[5]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[5](n)"
+
+################################################################################
+#PCIE RX_IN 6
+################################################################################
+
+set_location_assignment PIN_AM43 -to PCIE_RX_IN[6]
+set_location_assignment PIN_AM44 -to "PCIE_RX_IN[6](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[6]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[6](n)"
+
+################################################################################
+#PCIE RX_IN 7
+################################################################################
+
+set_location_assignment PIN_AK43 -to PCIE_RX_IN[7]
+set_location_assignment PIN_AK44 -to "PCIE_RX_IN[7](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[7]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[7](n)"
+
+################################################################################
+#PCIE TX_OUT 0
+################################################################################
+set_location_assignment PIN_AY39 -to PCIE_TX_OUT[0]
+set_location_assignment PIN_AY40 -to "PCIE_TX_OUT[0](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[0]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[0](n)"
+
+################################################################################
+#PCIE TX_OUT 1
+################################################################################
+set_location_assignment PIN_AV39 -to PCIE_TX_OUT[1]
+set_location_assignment PIN_AV40 -to "PCIE_TX_OUT[1](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[1]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[1](n)"
+
+################################################################################
+#PCIE TX_OUT 2
+################################################################################
+set_location_assignment PIN_AT39 -to PCIE_TX_OUT[2]
+set_location_assignment PIN_AT40 -to "PCIE_TX_OUT[2](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[2]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[2](n)"
+
+################################################################################
+#PCIE TX_OUT 3
+################################################################################
+set_location_assignment PIN_AU41 -to PCIE_TX_OUT[3]
+set_location_assignment PIN_AU42 -to "PCIE_TX_OUT[3](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[3]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[3](n)"
+
+################################################################################
+#PCIE TX_OUT 4
+################################################################################
+set_location_assignment PIN_AN41 -to PCIE_TX_OUT[4]
+set_location_assignment PIN_AN42 -to "PCIE_TX_OUT[4](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[4]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[4](n)"
+
+################################################################################
+#PCIE TX_OUT 5
+################################################################################
+set_location_assignment PIN_AL41 -to PCIE_TX_OUT[5]
+set_location_assignment PIN_AL42 -to "PCIE_TX_OUT[5](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[5]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[5](n)"
+
+################################################################################
+#PCIE TX_OUT 6
+################################################################################
+set_location_assignment PIN_AJ41 -to PCIE_TX_OUT[6]
+set_location_assignment PIN_AJ42 -to "PCIE_TX_OUT[6](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[6]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[6](n)"
+
+################################################################################
+#PCIE TX_OUT 7
+################################################################################
+
+set_location_assignment PIN_AG41 -to PCIE_TX_OUT[7]
+set_location_assignment PIN_AG42 -to "PCIE_TX_OUT[7](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[7]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[7](n)"
+
+################################################################################
+# LED's
+################################################################################
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7]
+
+set_location_assignment PIN_AW37 -to LED[0]
+set_location_assignment PIN_AV37 -to LED[1]
+set_location_assignment PIN_BB36 -to LED[2]
+set_location_assignment PIN_BB39 -to LED[3]
+set_location_assignment PIN_AH15 -to LED[4]
+set_location_assignment PIN_AH13 -to LED[5]
+set_location_assignment PIN_AJ13 -to LED[6]
+set_location_assignment PIN_AJ14 -to LED[7]
+
+################################################################################
+# OSCILLATORS
+################################################################################
+
+set_location_assignment PIN_BC28 -to OSC_BANK3D_50MHZ
+set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_BANK3D_50MHZ
+
+################################################################################
+# End Custom Instantiations
+################################################################################
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name SDC_FILE ../constr/DE5Gen1x8If64.sdc
+set_global_assignment -name QSYS_FILE ../ip/QSysDE5Gen1x8If64.qsys
+set_global_assignment -name VERILOG_FILE ../hdl/DE5Gen1x8If64.v
+set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ohtb.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/fpga/altera/de5_qsys/DE5Gen2x8If128/bit/DE5Gen2x8If128.sof b/fpga/altera/de5_qsys/DE5Gen2x8If128/bit/DE5Gen2x8If128.sof
new file mode 100644
index 0000000..b187da0
Binary files /dev/null and b/fpga/altera/de5_qsys/DE5Gen2x8If128/bit/DE5Gen2x8If128.sof differ
diff --git a/fpga/altera/de5_qsys/DE5Gen2x8If128/constr/DE5Gen2x8If128.sdc b/fpga/altera/de5_qsys/DE5Gen2x8If128/constr/DE5Gen2x8If128.sdc
new file mode 100644
index 0000000..e55fcbb
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen2x8If128/constr/DE5Gen2x8If128.sdc
@@ -0,0 +1,96 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            DE5Gen2x8If128.sdc (Qsys)
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Synopsys Design Constraints for the DE5 board.
+# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}]
+create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}]
+
+################################################################################
+# 13.1 Workround for http://www.altera.com/support/kdb/solutions/rd12162013_581.html?GSA_pos=1&WT.oss_r=1&WT.oss=adce_off_r
+################################################################################
+
+set_false_path -to [get_registers *|*.adce_off_r[0]]
+set_false_path -to [get_registers *|*.adce_on_rr[0]]
+set_false_path -to [get_registers *|reset_sync_pldclk_r[*]]
+
+################################################################################
+# End Workround 
+################################################################################
+
+derive_pll_clocks -create_base_clocks
+derive_clock_uncertainty
+
+################################################################################
+# Imports from Example Design (altera/13.1/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/)
+################################################################################
+
+######################################################################
+# HIP Soft reset controller SDC constraints
+set_false_path -to   [get_registers *altpcie_rs_serdes|fifo_err_sync_r[0]]
+set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*]
+
+# HIP testin pins SDC constraints
+set_false_path -from [get_pins -compatibility_mode *hip_ctrl*]
+
+######################################################################
+# Constraints for CV SIG asynchonous logic
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|test_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqout[*]}]
+                                                                                                                                                
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqber[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_lf[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_fs[*]}]
\ No newline at end of file
diff --git a/fpga/altera/de5_qsys/DE5Gen2x8If128/hdl/DE5Gen2x8If128.v b/fpga/altera/de5_qsys/DE5Gen2x8If128/hdl/DE5Gen2x8If128.v
new file mode 100644
index 0000000..694ed33
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen2x8If128/hdl/DE5Gen2x8If128.v
@@ -0,0 +1,368 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            DE5Gen2x8If128.v
+// Version:             
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Altera Stratix V Avalong Streaming Interface to PCI
+//                      Express module and the Terasic DE5 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`timescale 1ps / 1ps
+module DE5Gen2x8If128
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 12,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Quartus IP Library
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      )
+    (
+     // ----------LEDs----------
+     output [7:0]            LED,
+
+     // ----------PCIE----------
+     input                   PCIE_RESET_N,
+     input                   PCIE_REFCLK,
+
+     // ----------PCIE Serial RX----------
+     input [C_NUM_LANES-1:0] PCIE_RX_IN,
+
+     // ----------PCIE Serial TX----------
+     output [C_NUM_LANES-1:0]  PCIE_TX_OUT,
+
+     // ----------Oscillators----------
+     input                   OSC_BANK3D_50MHZ
+     );
+
+    wire                     npor;
+    wire                     pin_perst;
+
+    // ----------TL Config interface----------
+    wire [3:0]               tl_cfg_add;
+    wire [31:0]              tl_cfg_ctl;
+    wire [52:0]              tl_cfg_sts;
+
+    // ----------Rx/TX Interfaces----------
+    wire [0:0]               rx_st_sop;
+    wire [0:0]               rx_st_eop;
+    wire [0:0]               rx_st_err;
+    wire [0:0]               rx_st_valid;
+    wire [0:0]               rx_st_empty;
+    wire                     rx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0]              rx_st_data;
+
+    wire [0:0]               tx_st_sop;
+    wire [0:0]               tx_st_eop;
+    wire [0:0]               tx_st_err;
+    wire [0:0]               tx_st_valid;
+    wire                     tx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0]              tx_st_data;
+    wire [0:0]               tx_st_empty;
+
+    // ----------Clocks & Locks----------
+    wire                     pld_clk;
+    wire                     coreclkout_hip;
+    wire                     refclk;
+    wire                     pld_core_ready;
+    wire                     reset_status;
+    wire                     serdes_pll_locked;
+
+    // ----------Interrupt Interfaces----------
+    wire                     app_msi_req;
+    wire                     app_msi_ack;
+    
+    // ----------Reconfiguration Controller signals----------
+    wire                     mgmt_clk_clk;
+    wire                     mgmt_rst_reset;
+
+    // ----------Reconfiguration Driver Signals----------
+    wire                     reconfig_xcvr_clk;
+    wire                     reconfig_xcvr_rst;
+
+    wire [7:0]               rx_in;
+    wire [7:0]               tx_out;
+    
+    // ------------Status Interface------------
+    wire                     derr_cor_ext_rcv;
+    wire                     derr_cor_ext_rpl;
+    wire                     derr_rpl;
+    wire                     dlup;
+    wire                     dlup_exit;
+    wire                     ev128ns;
+    wire                     ev1us;
+    wire                     hotrst_exit;
+    wire [3:0]               int_status;
+    wire                     l2_exit;
+    wire [3:0]               lane_act;
+    wire [4:0]               ltssmstate;
+    wire                     rx_par_err;
+    wire [1:0]               tx_par_err;
+    wire                     cfg_par_err;
+    wire [7:0]               ko_cpl_spc_header;
+    wire [11:0]              ko_cpl_spc_data;
+
+    // ----------Clocks----------
+    assign pld_clk = coreclkout_hip;
+    assign mgmt_clk_clk = PCIE_REFCLK;
+    assign reconfig_xcvr_clk = PCIE_REFCLK;
+    assign refclk = PCIE_REFCLK;
+    assign pld_core_ready = serdes_pll_locked;
+    
+    // ----------Resets----------
+    assign reconfig_xcvr_rst = 1'b0;
+    assign mgmt_rst_reset = 1'b0;
+    assign pin_perst = PCIE_RESET_N;
+    assign npor = PCIE_RESET_N;
+
+    // ----------LED's----------
+    assign LED[7:0] = 8'hff;
+
+   // -------------------- BEGIN ALTERA IP INSTANTIATION  --------------------//
+   QSysDE5Gen2x8If128
+     pcie_system_inst
+     (
+      // Outputs
+      .rx_st_startofpacket              (rx_st_sop[0:0]),
+      .rx_st_endofpacket                (rx_st_eop[0:0]),
+      .rx_st_valid                      (rx_st_valid[0:0]),
+      .rx_st_empty                      (rx_st_empty[0:0]),
+      .rx_st_data                       (rx_st_data[127:0]),
+      .tx_st_ready                      (tx_st_ready),
+      .pciehip_reset_status             (reset_status),
+      .pciehip_serdes_pll_locked        (serdes_pll_locked),
+      .pciecfg_tl_cfg_add               (tl_cfg_add[3:0]),
+      .pciecfg_tl_cfg_ctl               (tl_cfg_ctl[31:0]),
+      .pciecfg_tl_cfg_sts               (tl_cfg_sts[52:0]),
+      .pciecoreclk_clk                  (coreclkout_hip),
+      .pcieserial_tx_out0               (PCIE_TX_OUT[0]),
+      .pcieserial_tx_out1               (PCIE_TX_OUT[1]),
+      .pcieserial_tx_out2               (PCIE_TX_OUT[2]),
+      .pcieserial_tx_out3               (PCIE_TX_OUT[3]),
+      .pcieserial_tx_out4               (PCIE_TX_OUT[4]),
+      .pcieserial_tx_out5               (PCIE_TX_OUT[5]),
+      .pcieserial_tx_out6               (PCIE_TX_OUT[6]),
+      .pcieserial_tx_out7               (PCIE_TX_OUT[7]),
+      .pciemsi_app_msi_ack              (app_msi_ack),
+      .pciestat_derr_cor_ext_rcv        (derr_cor_ext_rcv),
+      .pciestat_derr_cor_ext_rpl        (derr_cor_ext_rpl),
+      .pciestat_derr_rpl                (derr_rpl),
+      .pciestat_dlup                    (dlup),
+      .pciestat_dlup_exit               (dlup_exit),
+      .pciestat_ev128ns                 (ev128ns),
+      .pciestat_ev1us                   (ev1us),
+      .pciestat_hotrst_exit             (hotrst_exit),
+      .pciestat_int_status              (int_status),
+      .pciestat_l2_exit                 (l2_exit),
+      .pciestat_lane_act                (lane_act),
+      .pciestat_ltssmstate              (ltssmstate),
+      .pciestat_rx_par_err              (rx_par_err),
+      .pciestat_tx_par_err              (tx_par_err),
+      .pciestat_cfg_par_err             (cfg_par_err),
+      .pciestat_ko_cpl_spc_header       (ko_cpl_spc_header),
+      .pciestat_ko_cpl_spc_data         (ko_cpl_spc_data),
+      // Inputs
+      .rx_st_ready                      (rx_st_ready),
+      .tx_st_startofpacket              (tx_st_sop[0:0]),
+      .tx_st_endofpacket                (tx_st_eop[0:0]),
+      .tx_st_valid                      (tx_st_valid[0:0]),
+      .tx_st_empty                      (tx_st_empty[0:0]),
+      .tx_st_data                       (tx_st_data[127:0]),
+      .pciehip_pld_core_ready           (pld_core_ready),
+      .pcienpor_npor                    (npor),
+      .pcienpor_pin_perst               (pin_perst),
+      .pcierefclk_clk                   (refclk),
+      .reconfigrefclk_clk               (reconfig_xcvr_clk),
+      .pciepld_clk                      (pld_clk),
+      .reconfigrst_reset                (reconfig_xcvr_rst),
+      .mgmtrst_reset                    (mgmt_rst_reset),
+      .mgmtclk_clk                      (mgmt_clk_clk),
+      .reconfigpldclk_clk               (pld_clk),
+      .pcieserial_rx_in0                (PCIE_RX_IN[0]),
+      .pcieserial_rx_in1                (PCIE_RX_IN[1]),
+      .pcieserial_rx_in2                (PCIE_RX_IN[2]),
+      .pcieserial_rx_in3                (PCIE_RX_IN[3]),
+      .pcieserial_rx_in4                (PCIE_RX_IN[4]),
+      .pcieserial_rx_in5                (PCIE_RX_IN[5]),
+      .pcieserial_rx_in6                (PCIE_RX_IN[6]),
+      .pcieserial_rx_in7                (PCIE_RX_IN[7]),
+      .pciemsi_app_msi_req              (app_msi_req),
+      .drvstat_derr_cor_ext_rcv         (derr_cor_ext_rcv),
+      .drvstat_derr_cor_ext_rpl         (derr_cor_ext_rpl),
+      .drvstat_derr_rpl                 (derr_rpl),
+      .drvstat_dlup                     (dlup),
+      .drvstat_dlup_exit                (dlup_exit),
+      .drvstat_ev128ns                  (ev128ns),
+      .drvstat_ev1us                    (ev1us),
+      .drvstat_hotrst_exit              (hotrst_exit),
+      .drvstat_int_status               (int_status),
+      .drvstat_l2_exit                  (l2_exit),
+      .drvstat_lane_act                 (lane_act),
+      .drvstat_ltssmstate               (ltssmstate),
+      .drvstat_rx_par_err               (rx_par_err),
+      .drvstat_tx_par_err               (tx_par_err),
+      .drvstat_cfg_par_err              (cfg_par_err),
+      .drvstat_ko_cpl_spc_header        (ko_cpl_spc_header),
+      .drvstat_ko_cpl_spc_data          (ko_cpl_spc_data));
+
+    // -------------------- END ALTERA IP INSTANTIATION  --------------------
+    // -------------------- BEGIN RIFFA INSTANTAION --------------------
+
+    // RIFFA channel interface
+    wire                     rst_out;
+    wire [C_NUM_CHNL-1:0]    chnl_rx_clk;
+    wire [C_NUM_CHNL-1:0]    chnl_rx;
+    wire [C_NUM_CHNL-1:0]    chnl_rx_ack;
+    wire [C_NUM_CHNL-1:0]    chnl_rx_last;
+    wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len;
+    wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_ren;
+    
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_clk;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_last;
+    wire [(C_NUM_CHNL*32)-1:0]               chnl_tx_len;
+    wire [(C_NUM_CHNL*31)-1:0]               chnl_tx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_ren;
+
+    wire                                     chnl_reset;
+    wire                                     chnl_clk;
+    assign chnl_clk = pld_clk;
+    assign chnl_reset = rst_out;
+    
+    riffa_wrapper_de5
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .RX_ST_READY                   (rx_st_ready),
+         .TX_ST_DATA                    (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (tx_st_valid[0:0]),
+         .TX_ST_EOP                     (tx_st_eop[0:0]),
+         .TX_ST_SOP                     (tx_st_sop[0:0]),
+         .TX_ST_EMPTY                   (tx_st_empty[0:0]),
+         .APP_MSI_REQ                   (app_msi_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .RX_ST_DATA                    (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (rx_st_eop[0:0]),
+         .RX_ST_SOP                     (rx_st_sop[0:0]),
+         .RX_ST_VALID                   (rx_st_valid[0:0]),
+         .RX_ST_EMPTY                   (rx_st_empty[0:0]),
+         .TX_ST_READY                   (tx_st_ready),
+         .TL_CFG_CTL                    (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]),
+         .KO_CPL_SPC_DATA               (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]),
+         .APP_MSI_ACK                   (app_msi_ack),
+         .PLD_CLK                       (pld_clk),
+         .RESET_STATUS                  (reset_status),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+
+    // --------------------  END RIFFA INSTANTAION --------------------
+    // --------------------  BEGIN USER CODE  --------------------
+    genvar                                   i;
+    generate
+        for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
+            // Instantiate and assign modules to RIFFA channels. Users should 
+            // replace the chnl_tester instantiation with their own core.
+            chnl_tester 
+                 #(
+                   .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                   )
+            chnl_tester_i
+                 (
+
+                  .CLK(chnl_clk),
+                  .RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
+                  // Rx interface
+                  .CHNL_RX_CLK(chnl_rx_clk[i]), 
+                  .CHNL_RX(chnl_rx[i]), 
+                  .CHNL_RX_ACK(chnl_rx_ack[i]), 
+                  .CHNL_RX_LAST(chnl_rx_last[i]), 
+                  .CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]), 
+                  .CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
+                  // Tx interface
+                  .CHNL_TX_CLK(chnl_tx_clk[i]), 
+                  .CHNL_TX(chnl_tx[i]), 
+                  .CHNL_TX_ACK(chnl_tx_ack[i]), 
+                  .CHNL_TX_LAST(chnl_tx_last[i]), 
+                  .CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]), 
+                  .CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
+                  );    
+        end
+    endgenerate
+    // --------------------  END USER CODE  --------------------
+endmodule
diff --git a/fpga/altera/de5_qsys/DE5Gen2x8If128/ip/QSysDE5Gen2x8If128.qsys b/fpga/altera/de5_qsys/DE5Gen2x8If128/ip/QSysDE5Gen2x8If128.qsys
new file mode 100644
index 0000000..413bacf
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen2x8If128/ip/QSysDE5Gen2x8If128.qsys
@@ -0,0 +1,664 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Stratix V";
+         type = "String";
+      }
+   }
+   element PCIeGen2x8If128
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element XCVRCtrlGen2x8
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element XCVRDrvGen2x8
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element clk_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="5SGXEA7N2F45C2" />
+ <parameter name="deviceFamily" value="Stratix V" />
+ <parameter name="deviceSpeedGrade" value="2_H2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="drvstat"
+   internal="XCVRDrvGen2x8.hip_status_drv"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="mgmtclk"
+   internal="XCVRCtrlGen2x8.mgmt_clk_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="mgmtrst"
+   internal="XCVRCtrlGen2x8.mgmt_rst_reset"
+   type="reset"
+   dir="end" />
+ <interface
+   name="pciecfg"
+   internal="PCIeGen2x8If128.config_tl"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pciecoreclk"
+   internal="PCIeGen2x8If128.coreclkout_hip"
+   type="clock"
+   dir="start" />
+ <interface
+   name="pciehip"
+   internal="PCIeGen2x8If128.hip_rst"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pciemsi"
+   internal="PCIeGen2x8If128.int_msi"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pcienpor"
+   internal="PCIeGen2x8If128.npor"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pciepld"
+   internal="PCIeGen2x8If128.pld_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="pcierefclk"
+   internal="PCIeGen2x8If128.refclk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="pcieserial"
+   internal="PCIeGen2x8If128.hip_serial"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pciestat"
+   internal="PCIeGen2x8If128.hip_status"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reconfigpldclk"
+   internal="XCVRDrvGen2x8.pld_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="reconfigrefclk"
+   internal="XCVRDrvGen2x8.reconfig_xcvr_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="reconfigrst"
+   internal="XCVRDrvGen2x8.reconfig_xcvr_rst"
+   type="reset"
+   dir="end" />
+ <interface name="reset" internal="clk_0.clk_in_reset" />
+ <interface
+   name="rx_st"
+   internal="PCIeGen2x8If128.rx_st"
+   type="avalon_streaming"
+   dir="start" />
+ <interface
+   name="tx_st"
+   internal="PCIeGen2x8If128.tx_st"
+   type="avalon_streaming"
+   dir="end" />
+ <module
+   name="PCIeGen2x8If128"
+   kind="altera_pcie_sv_hip_ast"
+   version="14.1"
+   enabled="1">
+  <parameter name="INTENDED_DEVICE_FAMILY" value="Stratix V" />
+  <parameter name="advanced_default_hwtcl_atomic_malformed" value="true" />
+  <parameter name="advanced_default_hwtcl_atomic_op_completer_32bit" value="false" />
+  <parameter name="advanced_default_hwtcl_atomic_op_completer_64bit" value="false" />
+  <parameter name="advanced_default_hwtcl_atomic_op_routing" value="false" />
+  <parameter name="advanced_default_hwtcl_bridge_port_ssid_support" value="false" />
+  <parameter name="advanced_default_hwtcl_bridge_port_vga_enable" value="false" />
+  <parameter name="advanced_default_hwtcl_bypass_cdc" value="false" />
+  <parameter name="advanced_default_hwtcl_cas_completer_128bit" value="false" />
+  <parameter name="advanced_default_hwtcl_cdc_dummy_insert_limit" value="11" />
+  <parameter name="advanced_default_hwtcl_d0_pme" value="false" />
+  <parameter name="advanced_default_hwtcl_d1_pme" value="false" />
+  <parameter name="advanced_default_hwtcl_d1_support" value="false" />
+  <parameter name="advanced_default_hwtcl_d2_pme" value="false" />
+  <parameter name="advanced_default_hwtcl_d2_support" value="false" />
+  <parameter name="advanced_default_hwtcl_d3_cold_pme" value="false" />
+  <parameter name="advanced_default_hwtcl_d3_hot_pme" value="false" />
+  <parameter name="advanced_default_hwtcl_data_pack_rx" value="disable" />
+  <parameter name="advanced_default_hwtcl_deskew_comma" value="com_deskw" />
+  <parameter name="advanced_default_hwtcl_device_number" value="0" />
+  <parameter name="advanced_default_hwtcl_disable_link_x2_support" value="false" />
+  <parameter name="advanced_default_hwtcl_disable_snoop_packet" value="false" />
+  <parameter name="advanced_default_hwtcl_ei_delay_powerdown_count" value="10" />
+  <parameter name="advanced_default_hwtcl_eie_before_nfts_count" value="4" />
+  <parameter
+     name="advanced_default_hwtcl_enable_adapter_half_rate_mode"
+     value="false" />
+  <parameter name="advanced_default_hwtcl_enable_l1_aspm" value="false" />
+  <parameter name="advanced_default_hwtcl_enable_rx_buffer_checking" value="false" />
+  <parameter name="advanced_default_hwtcl_extended_format_field" value="false" />
+  <parameter name="advanced_default_hwtcl_extended_tag_reset" value="false" />
+  <parameter name="advanced_default_hwtcl_fc_init_timer" value="1024" />
+  <parameter name="advanced_default_hwtcl_flow_control_timeout_count" value="200" />
+  <parameter name="advanced_default_hwtcl_flow_control_update_count" value="30" />
+  <parameter name="advanced_default_hwtcl_flr_capability" value="false" />
+  <parameter name="advanced_default_hwtcl_gen2_diffclock_nfts_count" value="255" />
+  <parameter name="advanced_default_hwtcl_gen2_sameclock_nfts_count" value="255" />
+  <parameter name="advanced_default_hwtcl_hot_plug_support" value="0" />
+  <parameter name="advanced_default_hwtcl_interrupt_pin" value="inta" />
+  <parameter name="advanced_default_hwtcl_l01_entry_latency" value="31" />
+  <parameter name="advanced_default_hwtcl_l0_exit_latency_diffclock" value="6" />
+  <parameter name="advanced_default_hwtcl_l0_exit_latency_sameclock" value="6" />
+  <parameter name="advanced_default_hwtcl_l1_exit_latency_diffclock" value="0" />
+  <parameter name="advanced_default_hwtcl_l1_exit_latency_sameclock" value="0" />
+  <parameter name="advanced_default_hwtcl_low_priority_vc" value="single_vc" />
+  <parameter name="advanced_default_hwtcl_ltr_mechanism" value="false" />
+  <parameter name="advanced_default_hwtcl_ltssm_1ms_timeout" value="disable" />
+  <parameter name="advanced_default_hwtcl_ltssm_freqlocked_check" value="disable" />
+  <parameter name="advanced_default_hwtcl_maximum_current" value="0" />
+  <parameter name="advanced_default_hwtcl_no_command_completed" value="true" />
+  <parameter name="advanced_default_hwtcl_no_soft_reset" value="false" />
+  <parameter name="advanced_default_hwtcl_pclk_out_sel" value="pclk" />
+  <parameter name="advanced_default_hwtcl_pipex1_debug_sel" value="disable" />
+  <parameter name="advanced_default_hwtcl_register_pipe_signals" value="false" />
+  <parameter name="advanced_default_hwtcl_reserved_debug" value="0" />
+  <parameter
+     name="advanced_default_hwtcl_retry_buffer_last_active_address"
+     value="2047" />
+  <parameter name="advanced_default_hwtcl_rx_l0s_count_idl" value="0" />
+  <parameter name="advanced_default_hwtcl_set_l0s" value="0" />
+  <parameter name="advanced_default_hwtcl_skp_os_gen3_count" value="0" />
+  <parameter name="advanced_default_hwtcl_skp_os_schedule_count" value="0" />
+  <parameter name="advanced_default_hwtcl_ssid" value="0" />
+  <parameter name="advanced_default_hwtcl_ssvid" value="0" />
+  <parameter name="advanced_default_hwtcl_tph_completer" value="false" />
+  <parameter name="advanced_default_hwtcl_tx_cdc_almost_empty" value="5" />
+  <parameter name="advanced_default_hwtcl_vc0_clk_enable" value="true" />
+  <parameter name="advanced_default_hwtcl_wrong_device_id" value="disable" />
+  <parameter name="advanced_default_parameter_override" value="0" />
+  <parameter name="ast_width_hwtcl" value="Avalon-ST 128-bit" />
+  <parameter name="bar0_size_mask_hwtcl" value="10" />
+  <parameter name="bar0_type_hwtcl" value="2" />
+  <parameter name="bar1_size_mask_hwtcl" value="0" />
+  <parameter name="bar1_type_hwtcl" value="0" />
+  <parameter name="bar2_size_mask_hwtcl" value="0" />
+  <parameter name="bar2_type_hwtcl" value="0" />
+  <parameter name="bar3_size_mask_hwtcl" value="0" />
+  <parameter name="bar3_type_hwtcl" value="0" />
+  <parameter name="bar4_size_mask_hwtcl" value="0" />
+  <parameter name="bar4_type_hwtcl" value="0" />
+  <parameter name="bar5_size_mask_hwtcl" value="0" />
+  <parameter name="bar5_type_hwtcl" value="0" />
+  <parameter name="change_deemphasis_hwtcl" value="0" />
+  <parameter name="class_code_hwtcl" value="0" />
+  <parameter name="completion_timeout_hwtcl" value="ABCD" />
+  <parameter name="design_environment_hwtcl" value="QSYS" />
+  <parameter name="device_id_hwtcl" value="1" />
+  <parameter name="dll_active_report_support_hwtcl" value="0" />
+  <parameter name="ecrc_check_capable_hwtcl" value="0" />
+  <parameter name="ecrc_gen_capable_hwtcl" value="0" />
+  <parameter name="enable_completion_timeout_disable_hwtcl" value="1" />
+  <parameter name="enable_function_msix_support_hwtcl" value="0" />
+  <parameter name="enable_pcisigtest_hwtcl" value="0" />
+  <parameter name="enable_pipe32_phyip_ser_driver_hwtcl" value="0" />
+  <parameter name="enable_pipe32_sim_hwtcl" value="0" />
+  <parameter name="enable_power_on_rst_pulse_hwtcl" value="0" />
+  <parameter name="enable_slot_register_hwtcl" value="0" />
+  <parameter name="enable_tl_only_sim_hwtcl" value="0" />
+  <parameter name="endpoint_l0_latency_hwtcl" value="0" />
+  <parameter name="endpoint_l1_latency_hwtcl" value="0" />
+  <parameter name="expansion_base_address_register_hwtcl" value="0" />
+  <parameter name="extend_tag_field_hwtcl" value="64" />
+  <parameter name="fixed_preset_on" value="0" />
+  <parameter name="force_hrc" value="0" />
+  <parameter name="force_src" value="0" />
+  <parameter name="full_swing_hwtcl" value="35" />
+  <parameter name="gen123_lane_rate_mode_hwtcl" value="Gen2 (5.0 Gbps)" />
+  <parameter name="gen3_coeff_10_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_nxtber_less_hwtcl">g3_coeff_10_nxtber_less</parameter>
+  <parameter name="gen3_coeff_10_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_nxtber_more_hwtcl">g3_coeff_10_nxtber_more</parameter>
+  <parameter name="gen3_coeff_10_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_sel_hwtcl" value="preset_10" />
+  <parameter name="gen3_coeff_11_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_nxtber_less_hwtcl">g3_coeff_11_nxtber_less</parameter>
+  <parameter name="gen3_coeff_11_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_nxtber_more_hwtcl">g3_coeff_11_nxtber_more</parameter>
+  <parameter name="gen3_coeff_11_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_sel_hwtcl" value="preset_11" />
+  <parameter name="gen3_coeff_12_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_nxtber_less_hwtcl">g3_coeff_12_nxtber_less</parameter>
+  <parameter name="gen3_coeff_12_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_nxtber_more_hwtcl">g3_coeff_12_nxtber_more</parameter>
+  <parameter name="gen3_coeff_12_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_sel_hwtcl" value="preset_12" />
+  <parameter name="gen3_coeff_13_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_nxtber_less_hwtcl">g3_coeff_13_nxtber_less</parameter>
+  <parameter name="gen3_coeff_13_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_nxtber_more_hwtcl">g3_coeff_13_nxtber_more</parameter>
+  <parameter name="gen3_coeff_13_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_sel_hwtcl" value="preset_13" />
+  <parameter name="gen3_coeff_14_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_nxtber_less_hwtcl">g3_coeff_14_nxtber_less</parameter>
+  <parameter name="gen3_coeff_14_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_nxtber_more_hwtcl">g3_coeff_14_nxtber_more</parameter>
+  <parameter name="gen3_coeff_14_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_sel_hwtcl" value="preset_14" />
+  <parameter name="gen3_coeff_15_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_nxtber_less_hwtcl">g3_coeff_15_nxtber_less</parameter>
+  <parameter name="gen3_coeff_15_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_nxtber_more_hwtcl">g3_coeff_15_nxtber_more</parameter>
+  <parameter name="gen3_coeff_15_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_sel_hwtcl" value="preset_15" />
+  <parameter name="gen3_coeff_16_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_nxtber_less_hwtcl">g3_coeff_16_nxtber_less</parameter>
+  <parameter name="gen3_coeff_16_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_nxtber_more_hwtcl">g3_coeff_16_nxtber_more</parameter>
+  <parameter name="gen3_coeff_16_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_sel_hwtcl" value="preset_16" />
+  <parameter name="gen3_coeff_17_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_nxtber_less_hwtcl">g3_coeff_17_nxtber_less</parameter>
+  <parameter name="gen3_coeff_17_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_nxtber_more_hwtcl">g3_coeff_17_nxtber_more</parameter>
+  <parameter name="gen3_coeff_17_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_sel_hwtcl" value="preset_17" />
+  <parameter name="gen3_coeff_18_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_nxtber_less_hwtcl">g3_coeff_18_nxtber_less</parameter>
+  <parameter name="gen3_coeff_18_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_nxtber_more_hwtcl">g3_coeff_18_nxtber_more</parameter>
+  <parameter name="gen3_coeff_18_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_sel_hwtcl" value="preset_18" />
+  <parameter name="gen3_coeff_19_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_nxtber_less_hwtcl">g3_coeff_19_nxtber_less</parameter>
+  <parameter name="gen3_coeff_19_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_nxtber_more_hwtcl">g3_coeff_19_nxtber_more</parameter>
+  <parameter name="gen3_coeff_19_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_sel_hwtcl" value="preset_19" />
+  <parameter name="gen3_coeff_1_ber_meas_hwtcl" value="2" />
+  <parameter name="gen3_coeff_1_hwtcl" value="7" />
+  <parameter name="gen3_coeff_1_nxtber_less_hwtcl">g3_coeff_1_nxtber_less</parameter>
+  <parameter name="gen3_coeff_1_nxtber_less_ptr_hwtcl" value="1" />
+  <parameter name="gen3_coeff_1_nxtber_more_hwtcl">g3_coeff_1_nxtber_more</parameter>
+  <parameter name="gen3_coeff_1_nxtber_more_ptr_hwtcl" value="1" />
+  <parameter name="gen3_coeff_1_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_1_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_1_sel_hwtcl" value="preset_1" />
+  <parameter name="gen3_coeff_20_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_nxtber_less_hwtcl">g3_coeff_20_nxtber_less</parameter>
+  <parameter name="gen3_coeff_20_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_nxtber_more_hwtcl">g3_coeff_20_nxtber_more</parameter>
+  <parameter name="gen3_coeff_20_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_sel_hwtcl" value="preset_20" />
+  <parameter name="gen3_coeff_21_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_nxtber_less_hwtcl">g3_coeff_21_nxtber_less</parameter>
+  <parameter name="gen3_coeff_21_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_nxtber_more_hwtcl">g3_coeff_21_nxtber_more</parameter>
+  <parameter name="gen3_coeff_21_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_sel_hwtcl" value="preset_21" />
+  <parameter name="gen3_coeff_22_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_nxtber_less_hwtcl">g3_coeff_22_nxtber_less</parameter>
+  <parameter name="gen3_coeff_22_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_nxtber_more_hwtcl">g3_coeff_22_nxtber_more</parameter>
+  <parameter name="gen3_coeff_22_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_sel_hwtcl" value="preset_22" />
+  <parameter name="gen3_coeff_23_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_nxtber_less_hwtcl">g3_coeff_23_nxtber_less</parameter>
+  <parameter name="gen3_coeff_23_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_nxtber_more_hwtcl">g3_coeff_23_nxtber_more</parameter>
+  <parameter name="gen3_coeff_23_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_sel_hwtcl" value="preset_23" />
+  <parameter name="gen3_coeff_24_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_nxtber_less_hwtcl">g3_coeff_24_nxtber_less</parameter>
+  <parameter name="gen3_coeff_24_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_nxtber_more_hwtcl">g3_coeff_24_nxtber_more</parameter>
+  <parameter name="gen3_coeff_24_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_sel_hwtcl" value="preset_24" />
+  <parameter name="gen3_coeff_2_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_nxtber_less_hwtcl">g3_coeff_2_nxtber_less</parameter>
+  <parameter name="gen3_coeff_2_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_nxtber_more_hwtcl">g3_coeff_2_nxtber_more</parameter>
+  <parameter name="gen3_coeff_2_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_sel_hwtcl" value="preset_2" />
+  <parameter name="gen3_coeff_3_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_nxtber_less_hwtcl">g3_coeff_3_nxtber_less</parameter>
+  <parameter name="gen3_coeff_3_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_nxtber_more_hwtcl">g3_coeff_3_nxtber_more</parameter>
+  <parameter name="gen3_coeff_3_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_sel_hwtcl" value="preset_3" />
+  <parameter name="gen3_coeff_4_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_nxtber_less_hwtcl">g3_coeff_4_nxtber_less</parameter>
+  <parameter name="gen3_coeff_4_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_nxtber_more_hwtcl">g3_coeff_4_nxtber_more</parameter>
+  <parameter name="gen3_coeff_4_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_sel_hwtcl" value="preset_4" />
+  <parameter name="gen3_coeff_5_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_nxtber_less_hwtcl">g3_coeff_5_nxtber_less</parameter>
+  <parameter name="gen3_coeff_5_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_nxtber_more_hwtcl">g3_coeff_5_nxtber_more</parameter>
+  <parameter name="gen3_coeff_5_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_sel_hwtcl" value="preset_5" />
+  <parameter name="gen3_coeff_6_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_nxtber_less_hwtcl">g3_coeff_6_nxtber_less</parameter>
+  <parameter name="gen3_coeff_6_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_nxtber_more_hwtcl">g3_coeff_6_nxtber_more</parameter>
+  <parameter name="gen3_coeff_6_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_sel_hwtcl" value="preset_6" />
+  <parameter name="gen3_coeff_7_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_nxtber_less_hwtcl">g3_coeff_7_nxtber_less</parameter>
+  <parameter name="gen3_coeff_7_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_nxtber_more_hwtcl">g3_coeff_7_nxtber_more</parameter>
+  <parameter name="gen3_coeff_7_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_sel_hwtcl" value="preset_7" />
+  <parameter name="gen3_coeff_8_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_nxtber_less_hwtcl">g3_coeff_8_nxtber_less</parameter>
+  <parameter name="gen3_coeff_8_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_nxtber_more_hwtcl">g3_coeff_8_nxtber_more</parameter>
+  <parameter name="gen3_coeff_8_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_sel_hwtcl" value="preset_8" />
+  <parameter name="gen3_coeff_9_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_nxtber_less_hwtcl">g3_coeff_9_nxtber_less</parameter>
+  <parameter name="gen3_coeff_9_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_nxtber_more_hwtcl">g3_coeff_9_nxtber_more</parameter>
+  <parameter name="gen3_coeff_9_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_sel_hwtcl" value="preset_9" />
+  <parameter name="gen3_full_swing_hwtcl" value="35" />
+  <parameter name="gen3_low_freq_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_10_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_11_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_1_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_2_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_3_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_4_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_5_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_6_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_7_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_8_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_9_hwtcl" value="0" />
+  <parameter name="gen3_rxfreqlock_counter_hwtcl" value="0" />
+  <parameter name="hip_reconfig_hwtcl" value="0" />
+  <parameter name="hip_tag_checking_hwtcl" value="1" />
+  <parameter name="hwtcl_override_g2_txvod" value="1" />
+  <parameter name="hwtcl_override_g3rxcoef" value="0" />
+  <parameter name="hwtcl_override_g3txcoef" value="0" />
+  <parameter name="in_cvp_mode_hwtcl" value="0" />
+  <parameter name="io_window_addr_width_hwtcl" value="0" />
+  <parameter name="lane_mask_hwtcl" value="x8" />
+  <parameter name="low_latency_mode_hwtcl" value="0" />
+  <parameter name="max_payload_size_hwtcl" value="256" />
+  <parameter name="msi_64bit_addressing_capable_hwtcl" value="true" />
+  <parameter name="msi_masking_capable_hwtcl" value="false" />
+  <parameter name="msi_multi_message_capable_hwtcl" value="1" />
+  <parameter name="msi_support_hwtcl" value="true" />
+  <parameter name="msix_pba_bir_hwtcl" value="0" />
+  <parameter name="msix_pba_offset_hwtcl" value="0" />
+  <parameter name="msix_table_bir_hwtcl" value="0" />
+  <parameter name="msix_table_offset_hwtcl" value="0" />
+  <parameter name="msix_table_size_hwtcl" value="0" />
+  <parameter name="multiple_packets_per_cycle_hwtcl" value="0" />
+  <parameter name="override_rxbuffer_cred_preset" value="0" />
+  <parameter name="override_tbpartner_driver_setting_hwtcl" value="0" />
+  <parameter name="pcie_inspector_hwtcl" value="0" />
+  <parameter name="pcie_qsys" value="1" />
+  <parameter name="pcie_spec_version_hwtcl" value="2.1" />
+  <parameter name="pll_refclk_freq_hwtcl" value="100 MHz" />
+  <parameter name="port_link_number_hwtcl" value="1" />
+  <parameter name="port_type_hwtcl" value="Native endpoint" />
+  <parameter name="prefetchable_mem_window_addr_width_hwtcl" value="0" />
+  <parameter name="revision_id_hwtcl" value="1" />
+  <parameter name="rpre_emph_a_val_hwtcl" value="9" />
+  <parameter name="rpre_emph_b_val_hwtcl" value="0" />
+  <parameter name="rpre_emph_c_val_hwtcl" value="16" />
+  <parameter name="rpre_emph_d_val_hwtcl" value="13" />
+  <parameter name="rpre_emph_e_val_hwtcl" value="5" />
+  <parameter name="rvod_sel_a_val_hwtcl" value="42" />
+  <parameter name="rvod_sel_b_val_hwtcl" value="38" />
+  <parameter name="rvod_sel_c_val_hwtcl" value="38" />
+  <parameter name="rvod_sel_d_val_hwtcl" value="43" />
+  <parameter name="rvod_sel_e_val_hwtcl" value="15" />
+  <parameter name="rxbuffer_rxreq_hwtcl" value="Minimum" />
+  <parameter name="serial_sim_hwtcl" value="1" />
+  <parameter name="set_pld_clk_x1_625MHz_hwtcl" value="0" />
+  <parameter name="slot_number_hwtcl" value="0" />
+  <parameter name="slot_power_limit_hwtcl" value="0" />
+  <parameter name="slot_power_scale_hwtcl" value="0" />
+  <parameter name="slotclkcfg_hwtcl" value="1" />
+  <parameter name="subsystem_device_id_hwtcl" value="0" />
+  <parameter name="subsystem_vendor_id_hwtcl" value="0" />
+  <parameter name="surprise_down_error_support_hwtcl" value="0" />
+  <parameter name="tlp_insp_trg_dw0_hwtcl" value="2049" />
+  <parameter name="tlp_insp_trg_dw1_hwtcl" value="0" />
+  <parameter name="tlp_insp_trg_dw2_hwtcl" value="0" />
+  <parameter name="tlp_insp_trg_dw3_hwtcl" value="0" />
+  <parameter name="tlp_inspector_hwtcl" value="0" />
+  <parameter name="tlp_inspector_use_signal_probe_hwtcl" value="0" />
+  <parameter name="track_rxfc_cplbuf_ovf_hwtcl" value="0" />
+  <parameter name="use_aer_hwtcl" value="0" />
+  <parameter name="use_ast_parity" value="0" />
+  <parameter name="use_atx_pll_hwtcl" value="0" />
+  <parameter name="use_config_bypass_hwtcl" value="0" />
+  <parameter name="use_crc_forwarding_hwtcl" value="0" />
+  <parameter name="use_cvp_update_core_pof_hwtcl" value="0" />
+  <parameter name="use_pci_ext_hwtcl" value="0" />
+  <parameter name="use_pcie_ext_hwtcl" value="0" />
+  <parameter name="use_rx_st_be_hwtcl" value="0" />
+  <parameter name="use_tx_cons_cred_sel_hwtcl" value="0" />
+  <parameter name="user_id_hwtcl" value="0" />
+  <parameter name="vendor_id_hwtcl" value="4466" />
+  <parameter name="vsec_id_hwtcl" value="40960" />
+  <parameter name="vsec_rev_hwtcl" value="0" />
+ </module>
+ <module
+   name="XCVRCtrlGen2x8"
+   kind="alt_xcvr_reconfig"
+   version="14.1"
+   enabled="1">
+  <parameter name="ber_en" value="0" />
+  <parameter name="device_family" value="Stratix V" />
+  <parameter name="enable_adce" value="0" />
+  <parameter name="enable_analog" value="1" />
+  <parameter name="enable_dcd" value="0" />
+  <parameter name="enable_dcd_power_up" value="1" />
+  <parameter name="enable_dfe" value="0" />
+  <parameter name="enable_eyemon" value="0" />
+  <parameter name="enable_mif" value="0" />
+  <parameter name="enable_offset" value="1" />
+  <parameter name="gui_cal_status_port" value="false" />
+  <parameter name="gui_enable_pll" value="0" />
+  <parameter name="gui_split_sizes" value="" />
+  <parameter name="number_of_reconfig_interfaces" value="10" />
+ </module>
+ <module
+   name="XCVRDrvGen2x8"
+   kind="altera_pcie_reconfig_driver"
+   version="14.1"
+   enabled="1">
+  <parameter name="INTENDED_DEVICE_FAMILY" value="Stratix V" />
+  <parameter name="enable_cal_busy_hwtcl" value="0" />
+  <parameter name="gen123_lane_rate_mode_hwtcl" value="Gen2 (5.0 Gbps)" />
+  <parameter name="number_of_reconfig_interfaces" value="10" />
+ </module>
+ <module name="clk_0" kind="clock_source" version="14.1" enabled="0">
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <connection
+   kind="avalon"
+   version="14.1"
+   start="XCVRDrvGen2x8.reconfig_mgmt"
+   end="XCVRCtrlGen2x8.reconfig_mgmt">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="XCVRDrvGen2x8.hip_currentspeed"
+   end="PCIeGen2x8If128.hip_currentspeed">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="XCVRDrvGen2x8.reconfig_busy"
+   end="XCVRCtrlGen2x8.reconfig_busy">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="XCVRCtrlGen2x8.reconfig_from_xcvr"
+   end="PCIeGen2x8If128.reconfig_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="XCVRCtrlGen2x8.reconfig_to_xcvr"
+   end="PCIeGen2x8If128.reconfig_to_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/fpga/altera/de5_qsys/DE5Gen2x8If128/ip/README.txt b/fpga/altera/de5_qsys/DE5Gen2x8If128/ip/README.txt
new file mode 100644
index 0000000..e69de29
diff --git a/fpga/altera/de5_qsys/DE5Gen2x8If128/prj/DE5Gen2x8If128.qpf b/fpga/altera/de5_qsys/DE5Gen2x8If128/prj/DE5Gen2x8If128.qpf
new file mode 100644
index 0000000..ea19b9e
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen2x8If128/prj/DE5Gen2x8If128.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 16:15:54  June 09, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:15:54  June 09, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "DE5Gen2x8If128"
diff --git a/fpga/altera/de5_qsys/DE5Gen2x8If128/prj/DE5Gen2x8If128.qsf b/fpga/altera/de5_qsys/DE5Gen2x8If128/prj/DE5Gen2x8If128.qsf
new file mode 100644
index 0000000..640b545
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen2x8If128/prj/DE5Gen2x8If128.qsf
@@ -0,0 +1,497 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 11:03:06  March 21, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		DE5Gen2x8If128_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Stratix V"
+set_global_assignment -name DEVICE 5SGXEA7N2F45C2
+set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen2x8If128
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06  MARCH 21, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION "14.1.0 SP0.19"
+
+################################################################################
+# Timing SDC Files
+################################################################################
+
+################################################################################
+# PCIE Connections
+################################################################################
+# PCIe clk (100 MHz)
+set_location_assignment PIN_AK38 -to PCIE_REFCLK
+set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK
+
+set_location_assignment PIN_AU33 -to PCIE_RESET_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_RESET_N
+
+################################################################################
+#PCIE Pins
+################################################################################
+# Settings from SV PCIE User Guide (AV-ST)
+# - 1.5V PCML 
+# - XCVR_VCCR_VCCT_VOLTAGE 1_0V 
+# - XCVR_VCCA_VOLTAGE 3_0V 
+# (SV User guide recommends VCCR/VCCT = 0_9 and VCCA = 2_5 , but link does not 
+# train correctly if these settings are used)
+# 
+# We use CMU PLL's (http://www.altera.com/literature/hb/stratix-v/stx5_52003.pdf)
+# Errata: http://www.altera.com/support/kdb/solutions/rd10112012_529.html
+################################################################################
+# Gloabal PCIE assignments (Use if signal problems exist)
+################################################################################
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[*]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[*]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[*]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[*](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[*]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[*]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[*](n)"
+
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_TX_OUT[*]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_TX_OUT[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_TX_OUT[*]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_TX_OUT[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_TX_OUT[*]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_TX_OUT[*](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_TX_OUT[*]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_TX_OUT[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_TX_OUT[*]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_TX_OUT[*](n)"
+
+################################################################################
+#PCIE RX_IN 0
+################################################################################
+
+set_location_assignment PIN_BB43 -to PCIE_RX_IN[0]
+set_location_assignment PIN_BB44 -to "PCIE_RX_IN[0](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[0]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[0](n)"
+
+################################################################################
+#PCIE RX_IN 1
+################################################################################
+
+set_location_assignment PIN_BA41 -to PCIE_RX_IN[1]
+set_location_assignment PIN_BA42 -to "PCIE_RX_IN[1](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[1]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[1](n)"
+
+################################################################################
+#PCIE RX_IN 2
+################################################################################
+
+set_location_assignment PIN_AW41 -to PCIE_RX_IN[2]
+set_location_assignment PIN_AW42 -to "PCIE_RX_IN[2](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[2]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[2](n)"
+
+################################################################################
+#PCIE RX_IN 3
+################################################################################
+
+set_location_assignment PIN_AY43 -to PCIE_RX_IN[3]
+set_location_assignment PIN_AY44 -to "PCIE_RX_IN[3](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[3]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[3](n)"
+
+################################################################################
+#PCIE RX_IN 4
+################################################################################
+
+set_location_assignment PIN_AT43 -to PCIE_RX_IN[4]
+set_location_assignment PIN_AT44 -to "PCIE_RX_IN[4](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[4]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[4](n)"
+
+################################################################################
+#PCIE RX_IN 5
+################################################################################
+
+set_location_assignment PIN_AP43 -to PCIE_RX_IN[5]
+set_location_assignment PIN_AP44 -to "PCIE_RX_IN[5](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[5]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[5](n)"
+
+################################################################################
+#PCIE RX_IN 6
+################################################################################
+
+set_location_assignment PIN_AM43 -to PCIE_RX_IN[6]
+set_location_assignment PIN_AM44 -to "PCIE_RX_IN[6](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[6]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[6](n)"
+
+################################################################################
+#PCIE RX_IN 7
+################################################################################
+
+set_location_assignment PIN_AK43 -to PCIE_RX_IN[7]
+set_location_assignment PIN_AK44 -to "PCIE_RX_IN[7](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[7]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[7](n)"
+
+################################################################################
+#PCIE TX_OUT 0
+################################################################################
+set_location_assignment PIN_AY39 -to PCIE_TX_OUT[0]
+set_location_assignment PIN_AY40 -to "PCIE_TX_OUT[0](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[0]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[0](n)"
+
+################################################################################
+#PCIE TX_OUT 1
+################################################################################
+set_location_assignment PIN_AV39 -to PCIE_TX_OUT[1]
+set_location_assignment PIN_AV40 -to "PCIE_TX_OUT[1](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[1]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[1](n)"
+
+################################################################################
+#PCIE TX_OUT 2
+################################################################################
+set_location_assignment PIN_AT39 -to PCIE_TX_OUT[2]
+set_location_assignment PIN_AT40 -to "PCIE_TX_OUT[2](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[2]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[2](n)"
+
+################################################################################
+#PCIE TX_OUT 3
+################################################################################
+set_location_assignment PIN_AU41 -to PCIE_TX_OUT[3]
+set_location_assignment PIN_AU42 -to "PCIE_TX_OUT[3](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[3]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[3](n)"
+
+################################################################################
+#PCIE TX_OUT 4
+################################################################################
+set_location_assignment PIN_AN41 -to PCIE_TX_OUT[4]
+set_location_assignment PIN_AN42 -to "PCIE_TX_OUT[4](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[4]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[4](n)"
+
+################################################################################
+#PCIE TX_OUT 5
+################################################################################
+set_location_assignment PIN_AL41 -to PCIE_TX_OUT[5]
+set_location_assignment PIN_AL42 -to "PCIE_TX_OUT[5](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[5]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[5](n)"
+
+################################################################################
+#PCIE TX_OUT 6
+################################################################################
+set_location_assignment PIN_AJ41 -to PCIE_TX_OUT[6]
+set_location_assignment PIN_AJ42 -to "PCIE_TX_OUT[6](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[6]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[6](n)"
+
+################################################################################
+#PCIE TX_OUT 7
+################################################################################
+
+set_location_assignment PIN_AG41 -to PCIE_TX_OUT[7]
+set_location_assignment PIN_AG42 -to "PCIE_TX_OUT[7](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[7]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[7](n)"
+
+################################################################################
+# LED's
+################################################################################
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7]
+
+set_location_assignment PIN_AW37 -to LED[0]
+set_location_assignment PIN_AV37 -to LED[1]
+set_location_assignment PIN_BB36 -to LED[2]
+set_location_assignment PIN_BB39 -to LED[3]
+set_location_assignment PIN_AH15 -to LED[4]
+set_location_assignment PIN_AH13 -to LED[5]
+set_location_assignment PIN_AJ13 -to LED[6]
+set_location_assignment PIN_AJ14 -to LED[7]
+
+################################################################################
+# OSCILLATORS
+################################################################################
+
+set_location_assignment PIN_BC28 -to OSC_BANK3D_50MHZ
+set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_BANK3D_50MHZ
+
+################################################################################
+# End Custom Instantiations
+################################################################################
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name QSYS_FILE ../ip/QSysDE5Gen2x8If128.qsys
+set_global_assignment -name SDC_FILE ../constr/DE5Gen2x8If128.sdc
+set_global_assignment -name VERILOG_FILE ../hdl/DE5Gen2x8If128.v
+set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ohtb.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/fpga/altera/de5_qsys/DE5Gen3x4If128/bit/DE5Gen3x4If128.sof b/fpga/altera/de5_qsys/DE5Gen3x4If128/bit/DE5Gen3x4If128.sof
new file mode 100644
index 0000000..6606a2a
Binary files /dev/null and b/fpga/altera/de5_qsys/DE5Gen3x4If128/bit/DE5Gen3x4If128.sof differ
diff --git a/fpga/altera/de5_qsys/DE5Gen3x4If128/constr/DE5Gen3x4If128.sdc b/fpga/altera/de5_qsys/DE5Gen3x4If128/constr/DE5Gen3x4If128.sdc
new file mode 100644
index 0000000..40681b9
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen3x4If128/constr/DE5Gen3x4If128.sdc
@@ -0,0 +1,97 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            DE5Gen3x4If128.sdc (Qsys)
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Synopsys Design Constraints for the DE5 board.
+# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}]
+
+create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}]
+
+################################################################################
+# 13.1 Workround for http://www.altera.com/support/kdb/solutions/rd12162013_581.html?GSA_pos=1&WT.oss_r=1&WT.oss=adce_off_r
+################################################################################
+
+set_false_path -to [get_registers *|*.adce_off_r[0]]
+set_false_path -to [get_registers *|*.adce_on_rr[0]]
+set_false_path -to [get_registers *|reset_sync_pldclk_r[*]]
+
+################################################################################
+# End Workround 
+################################################################################
+
+derive_pll_clocks -create_base_clocks
+derive_clock_uncertainty
+
+################################################################################
+# Imports from Example Design (altera/13.1/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/)
+################################################################################
+
+######################################################################
+# HIP Soft reset controller SDC constraints
+set_false_path -to   [get_registers *altpcie_rs_serdes|fifo_err_sync_r[0]]
+set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*]
+
+# HIP testin pins SDC constraints
+set_false_path -from [get_pins -compatibility_mode *hip_ctrl*]
+
+######################################################################
+# Constraints for CV SIG asynchonous logic
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|test_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqout[*]}]
+                                                                                                                                                
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqber[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_lf[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_fs[*]}]
\ No newline at end of file
diff --git a/fpga/altera/de5_qsys/DE5Gen3x4If128/hdl/DE5Gen3x4If128.v b/fpga/altera/de5_qsys/DE5Gen3x4If128/hdl/DE5Gen3x4If128.v
new file mode 100644
index 0000000..4d35901
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen3x4If128/hdl/DE5Gen3x4If128.v
@@ -0,0 +1,364 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            DE5Gen3x4If128.v
+// Version:             
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Altera Stratix V Avalong Streaming Interface to PCI
+//                      Express module and the Terasic DE5 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`timescale 1ps / 1ps
+module DE5Gen3x4If128
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 12,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  4,
+      // Settings from Quartus IP Library
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     // ----------LEDs----------
+     output [7:0]            LED,
+
+     // ----------PCIE----------
+     input                   PCIE_RESET_N,
+     input                   PCIE_REFCLK,
+
+     // ----------PCIE Serial RX----------
+     input [C_NUM_LANES-1:0] PCIE_RX_IN,
+
+     // ----------PCIE Serial TX----------
+     output [C_NUM_LANES-1:0]  PCIE_TX_OUT,
+
+     // ----------Oscillators----------
+     input                   OSC_BANK3D_50MHZ
+     );
+
+    wire                     npor;
+    wire                     pin_perst;
+
+    // ----------TL Config interface----------
+    wire [3:0]               tl_cfg_add;
+    wire [31:0]              tl_cfg_ctl;
+    wire [52:0]              tl_cfg_sts;
+
+    // ----------Rx/TX Interfaces----------
+    wire [0:0]               rx_st_sop;
+    wire [0:0]               rx_st_eop;
+    wire [0:0]               rx_st_err;
+    wire [0:0]               rx_st_valid;
+    wire [0:0]               rx_st_empty;
+    wire                     rx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0]              rx_st_data;
+
+    wire [0:0]               tx_st_sop;
+    wire [0:0]               tx_st_eop;
+    wire [0:0]               tx_st_err;
+    wire [0:0]               tx_st_valid;
+    wire                     tx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0]              tx_st_data;
+    wire [0:0]               tx_st_empty;
+
+    // ----------Clocks & Locks----------
+    wire                     pld_clk;
+    wire                     coreclkout_hip;
+    wire                     refclk;
+    wire                     pld_core_ready;
+    wire                     reset_status;
+    wire                     serdes_pll_locked;
+
+    // ----------Interrupt Interfaces----------
+    wire                     app_msi_req;
+    wire                     app_msi_ack;
+    
+    // ----------Reconfiguration Controller signals----------
+    wire                     mgmt_clk_clk;
+    wire                     mgmt_rst_reset;
+
+    // ----------Reconfiguration Driver Signals----------
+    wire                     reconfig_xcvr_clk;
+    wire                     reconfig_xcvr_rst;
+
+    wire [7:0]               rx_in;
+    wire [7:0]               tx_out;
+    
+    // ------------Status Interface------------
+    wire                     derr_cor_ext_rcv;
+    wire                     derr_cor_ext_rpl;
+    wire                     derr_rpl;
+    wire                     dlup;
+    wire                     dlup_exit;
+    wire                     ev128ns;
+    wire                     ev1us;
+    wire                     hotrst_exit;
+    wire [3:0]               int_status;
+    wire                     l2_exit;
+    wire [3:0]               lane_act;
+    wire [4:0]               ltssmstate;
+    wire                     rx_par_err;
+    wire [1:0]               tx_par_err;
+    wire                     cfg_par_err;
+    wire [7:0]               ko_cpl_spc_header;
+    wire [11:0]              ko_cpl_spc_data;
+
+    // ----------Clocks----------
+    assign pld_clk = coreclkout_hip;
+    assign mgmt_clk_clk = PCIE_REFCLK;
+    assign reconfig_xcvr_clk = PCIE_REFCLK;
+    assign refclk = PCIE_REFCLK;
+    assign pld_core_ready = serdes_pll_locked;
+    
+    // ----------Resets----------
+    assign reconfig_xcvr_rst = 1'b0;
+    assign mgmt_rst_reset = 1'b0;
+    assign pin_perst = PCIE_RESET_N;
+    assign npor = PCIE_RESET_N;
+
+    // ----------LED's----------
+    assign LED[7:0] = 8'hff;
+
+   // -------------------- BEGIN ALTERA IP INSTANTIATION  --------------------//
+   QSysDE5Gen3x4If128
+     pcie_system_inst
+     (
+      // Outputs
+      .rx_st_startofpacket              (rx_st_sop[0:0]),
+      .rx_st_endofpacket                (rx_st_eop[0:0]),
+      .rx_st_valid                      (rx_st_valid[0:0]),
+      .rx_st_empty                      (rx_st_empty[0:0]),
+      .rx_st_data                       (rx_st_data[127:0]),
+      .tx_st_ready                      (tx_st_ready),
+      .pciehip_reset_status             (reset_status),
+      .pciehip_serdes_pll_locked        (serdes_pll_locked),
+      .pciecfg_tl_cfg_add               (tl_cfg_add[3:0]),
+      .pciecfg_tl_cfg_ctl               (tl_cfg_ctl[31:0]),
+      .pciecfg_tl_cfg_sts               (tl_cfg_sts[52:0]),
+      .pciecoreclk_clk                  (coreclkout_hip),
+      .pcieserial_tx_out0               (PCIE_TX_OUT[0]),
+      .pcieserial_tx_out1               (PCIE_TX_OUT[1]),
+      .pcieserial_tx_out2               (PCIE_TX_OUT[2]),
+      .pcieserial_tx_out3               (PCIE_TX_OUT[3]),
+      .pciemsi_app_msi_ack              (app_msi_ack),
+      .pciestat_derr_cor_ext_rcv        (derr_cor_ext_rcv),
+      .pciestat_derr_cor_ext_rpl        (derr_cor_ext_rpl),
+      .pciestat_derr_rpl                (derr_rpl),
+      .pciestat_dlup                    (dlup),
+      .pciestat_dlup_exit               (dlup_exit),
+      .pciestat_ev128ns                 (ev128ns),
+      .pciestat_ev1us                   (ev1us),
+      .pciestat_hotrst_exit             (hotrst_exit),
+      .pciestat_int_status              (int_status),
+      .pciestat_l2_exit                 (l2_exit),
+      .pciestat_lane_act                (lane_act),
+      .pciestat_ltssmstate              (ltssmstate),
+      .pciestat_rx_par_err              (rx_par_err),
+      .pciestat_tx_par_err              (tx_par_err),
+      .pciestat_cfg_par_err             (cfg_par_err),
+      .pciestat_ko_cpl_spc_header       (ko_cpl_spc_header),
+      .pciestat_ko_cpl_spc_data         (ko_cpl_spc_data),
+      // Inputs
+      .rx_st_ready                      (rx_st_ready),
+      .tx_st_startofpacket              (tx_st_sop[0:0]),
+      .tx_st_endofpacket                (tx_st_eop[0:0]),
+      .tx_st_valid                      (tx_st_valid[0:0]),
+      .tx_st_empty                      (tx_st_empty[0:0]),
+      .tx_st_data                       (tx_st_data[127:0]),
+      .pciehip_pld_core_ready           (pld_core_ready),
+      .pcienpor_npor                    (npor),
+      .pcienpor_pin_perst               (pin_perst),
+      .pcierefclk_clk                   (refclk),
+      .reconfigrefclk_clk               (reconfig_xcvr_clk),
+      .pciepld_clk                      (pld_clk),
+      .reconfigrst_reset                (reconfig_xcvr_rst),
+      .mgmtrst_reset                    (mgmt_rst_reset),
+      .mgmtclk_clk                      (mgmt_clk_clk),
+      .reconfigpldclk_clk               (pld_clk),
+      .pcieserial_rx_in0                (PCIE_RX_IN[0]),
+      .pcieserial_rx_in1                (PCIE_RX_IN[1]),
+      .pcieserial_rx_in2                (PCIE_RX_IN[2]),
+      .pcieserial_rx_in3                (PCIE_RX_IN[3]),
+      .pciemsi_app_msi_req              (app_msi_req),
+      .drvstat_derr_cor_ext_rcv         (derr_cor_ext_rcv),
+      .drvstat_derr_cor_ext_rpl         (derr_cor_ext_rpl),
+      .drvstat_derr_rpl                 (derr_rpl),
+      .drvstat_dlup                     (dlup),
+      .drvstat_dlup_exit                (dlup_exit),
+      .drvstat_ev128ns                  (ev128ns),
+      .drvstat_ev1us                    (ev1us),
+      .drvstat_hotrst_exit              (hotrst_exit),
+      .drvstat_int_status               (int_status),
+      .drvstat_l2_exit                  (l2_exit),
+      .drvstat_lane_act                 (lane_act),
+      .drvstat_ltssmstate               (ltssmstate),
+      .drvstat_rx_par_err               (rx_par_err),
+      .drvstat_tx_par_err               (tx_par_err),
+      .drvstat_cfg_par_err              (cfg_par_err),
+      .drvstat_ko_cpl_spc_header        (ko_cpl_spc_header),
+      .drvstat_ko_cpl_spc_data          (ko_cpl_spc_data));
+
+    // -------------------- END ALTERA IP INSTANTIATION  --------------------
+    // -------------------- BEGIN RIFFA INSTANTAION --------------------
+
+    // RIFFA channel interface
+    wire                     rst_out;
+    wire [C_NUM_CHNL-1:0]    chnl_rx_clk;
+    wire [C_NUM_CHNL-1:0]    chnl_rx;
+    wire [C_NUM_CHNL-1:0]    chnl_rx_ack;
+    wire [C_NUM_CHNL-1:0]    chnl_rx_last;
+    wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len;
+    wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_ren;
+    
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_clk;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_last;
+    wire [(C_NUM_CHNL*32)-1:0]               chnl_tx_len;
+    wire [(C_NUM_CHNL*31)-1:0]               chnl_tx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_ren;
+
+    wire                                     chnl_reset;
+    wire                                     chnl_clk;
+    wire                                     riffa_reset;
+    wire                                     riffa_clk;
+    assign riffa_reset = reset_status;
+    assign riffa_clk = pld_clk;
+    assign chnl_clk = pld_clk;
+    assign chnl_reset = rst_out;
+    
+    riffa_wrapper_de5
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (/*AUTOINST*/
+         // Outputs
+         .RX_ST_READY                   (rx_st_ready),
+         .TX_ST_DATA                    (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (tx_st_valid[0:0]),
+         .TX_ST_EOP                     (tx_st_eop[0:0]),
+         .TX_ST_SOP                     (tx_st_sop[0:0]),
+         .TX_ST_EMPTY                   (tx_st_empty[0:0]),
+         .APP_MSI_REQ                   (app_msi_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .RX_ST_DATA                    (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (rx_st_eop[0:0]),
+         .RX_ST_SOP                     (rx_st_sop[0:0]),
+         .RX_ST_VALID                   (rx_st_valid[0:0]),
+         .RX_ST_EMPTY                   (rx_st_empty[0:0]),
+         .TX_ST_READY                   (tx_st_ready),
+         .TL_CFG_CTL                    (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]),
+         .KO_CPL_SPC_DATA               (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]),
+         .APP_MSI_ACK                   (app_msi_ack),
+         .PLD_CLK                       (pld_clk),
+         .RESET_STATUS                  (reset_status),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+
+    // --------------------  END RIFFA INSTANTAION --------------------
+    // --------------------  BEGIN USER CODE  --------------------
+    genvar                                   i;
+    generate
+        for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
+            // Instantiate and assign modules to RIFFA channels. Users should 
+            // replace the chnl_tester instantiation with their own core.
+            chnl_tester 
+                 #(
+                   .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                   )
+            chnl_tester_i
+                 (
+
+                  .CLK(chnl_clk),
+                  .RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
+                  // Rx interface
+                  .CHNL_RX_CLK(chnl_rx_clk[i]), 
+                  .CHNL_RX(chnl_rx[i]), 
+                  .CHNL_RX_ACK(chnl_rx_ack[i]), 
+                  .CHNL_RX_LAST(chnl_rx_last[i]), 
+                  .CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]), 
+                  .CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
+                  // Tx interface
+                  .CHNL_TX_CLK(chnl_tx_clk[i]), 
+                  .CHNL_TX(chnl_tx[i]), 
+                  .CHNL_TX_ACK(chnl_tx_ack[i]), 
+                  .CHNL_TX_LAST(chnl_tx_last[i]), 
+                  .CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]), 
+                  .CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
+                  );    
+        end
+    endgenerate
+    // --------------------  END USER CODE  --------------------
+endmodule
diff --git a/fpga/altera/de5_qsys/DE5Gen3x4If128/ip/QSysDE5Gen3x4If128.qsys b/fpga/altera/de5_qsys/DE5Gen3x4If128/ip/QSysDE5Gen3x4If128.qsys
new file mode 100644
index 0000000..1a95179
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen3x4If128/ip/QSysDE5Gen3x4If128.qsys
@@ -0,0 +1,664 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Stratix V";
+         type = "String";
+      }
+   }
+   element PCIeGen3x4If128
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element XCVRCtrlGen3x4
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element XCVRDrvGen3x4
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element clk_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="5SGXEA7N2F45C2" />
+ <parameter name="deviceFamily" value="Stratix V" />
+ <parameter name="deviceSpeedGrade" value="2_H2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="drvstat"
+   internal="XCVRDrvGen3x4.hip_status_drv"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="mgmtclk"
+   internal="XCVRCtrlGen3x4.mgmt_clk_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="mgmtrst"
+   internal="XCVRCtrlGen3x4.mgmt_rst_reset"
+   type="reset"
+   dir="end" />
+ <interface
+   name="pciecfg"
+   internal="PCIeGen3x4If128.config_tl"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pciecoreclk"
+   internal="PCIeGen3x4If128.coreclkout_hip"
+   type="clock"
+   dir="start" />
+ <interface
+   name="pciehip"
+   internal="PCIeGen3x4If128.hip_rst"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pciemsi"
+   internal="PCIeGen3x4If128.int_msi"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pcienpor"
+   internal="PCIeGen3x4If128.npor"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pciepld"
+   internal="PCIeGen3x4If128.pld_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="pcierefclk"
+   internal="PCIeGen3x4If128.refclk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="pcieserial"
+   internal="PCIeGen3x4If128.hip_serial"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pciestat"
+   internal="PCIeGen3x4If128.hip_status"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reconfigpldclk"
+   internal="XCVRDrvGen3x4.pld_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="reconfigrefclk"
+   internal="XCVRDrvGen3x4.reconfig_xcvr_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="reconfigrst"
+   internal="XCVRDrvGen3x4.reconfig_xcvr_rst"
+   type="reset"
+   dir="end" />
+ <interface name="reset" internal="clk_0.clk_in_reset" />
+ <interface
+   name="rx_st"
+   internal="PCIeGen3x4If128.rx_st"
+   type="avalon_streaming"
+   dir="start" />
+ <interface
+   name="tx_st"
+   internal="PCIeGen3x4If128.tx_st"
+   type="avalon_streaming"
+   dir="end" />
+ <module
+   name="PCIeGen3x4If128"
+   kind="altera_pcie_sv_hip_ast"
+   version="14.1"
+   enabled="1">
+  <parameter name="INTENDED_DEVICE_FAMILY" value="Stratix V" />
+  <parameter name="advanced_default_hwtcl_atomic_malformed" value="true" />
+  <parameter name="advanced_default_hwtcl_atomic_op_completer_32bit" value="false" />
+  <parameter name="advanced_default_hwtcl_atomic_op_completer_64bit" value="false" />
+  <parameter name="advanced_default_hwtcl_atomic_op_routing" value="false" />
+  <parameter name="advanced_default_hwtcl_bridge_port_ssid_support" value="false" />
+  <parameter name="advanced_default_hwtcl_bridge_port_vga_enable" value="false" />
+  <parameter name="advanced_default_hwtcl_bypass_cdc" value="false" />
+  <parameter name="advanced_default_hwtcl_cas_completer_128bit" value="false" />
+  <parameter name="advanced_default_hwtcl_cdc_dummy_insert_limit" value="11" />
+  <parameter name="advanced_default_hwtcl_d0_pme" value="false" />
+  <parameter name="advanced_default_hwtcl_d1_pme" value="false" />
+  <parameter name="advanced_default_hwtcl_d1_support" value="false" />
+  <parameter name="advanced_default_hwtcl_d2_pme" value="false" />
+  <parameter name="advanced_default_hwtcl_d2_support" value="false" />
+  <parameter name="advanced_default_hwtcl_d3_cold_pme" value="false" />
+  <parameter name="advanced_default_hwtcl_d3_hot_pme" value="false" />
+  <parameter name="advanced_default_hwtcl_data_pack_rx" value="disable" />
+  <parameter name="advanced_default_hwtcl_deskew_comma" value="com_deskw" />
+  <parameter name="advanced_default_hwtcl_device_number" value="0" />
+  <parameter name="advanced_default_hwtcl_disable_link_x2_support" value="false" />
+  <parameter name="advanced_default_hwtcl_disable_snoop_packet" value="false" />
+  <parameter name="advanced_default_hwtcl_ei_delay_powerdown_count" value="10" />
+  <parameter name="advanced_default_hwtcl_eie_before_nfts_count" value="4" />
+  <parameter
+     name="advanced_default_hwtcl_enable_adapter_half_rate_mode"
+     value="false" />
+  <parameter name="advanced_default_hwtcl_enable_l1_aspm" value="false" />
+  <parameter name="advanced_default_hwtcl_enable_rx_buffer_checking" value="false" />
+  <parameter name="advanced_default_hwtcl_extended_format_field" value="false" />
+  <parameter name="advanced_default_hwtcl_extended_tag_reset" value="false" />
+  <parameter name="advanced_default_hwtcl_fc_init_timer" value="1024" />
+  <parameter name="advanced_default_hwtcl_flow_control_timeout_count" value="200" />
+  <parameter name="advanced_default_hwtcl_flow_control_update_count" value="30" />
+  <parameter name="advanced_default_hwtcl_flr_capability" value="false" />
+  <parameter name="advanced_default_hwtcl_gen2_diffclock_nfts_count" value="255" />
+  <parameter name="advanced_default_hwtcl_gen2_sameclock_nfts_count" value="255" />
+  <parameter name="advanced_default_hwtcl_hot_plug_support" value="0" />
+  <parameter name="advanced_default_hwtcl_interrupt_pin" value="inta" />
+  <parameter name="advanced_default_hwtcl_l01_entry_latency" value="31" />
+  <parameter name="advanced_default_hwtcl_l0_exit_latency_diffclock" value="6" />
+  <parameter name="advanced_default_hwtcl_l0_exit_latency_sameclock" value="6" />
+  <parameter name="advanced_default_hwtcl_l1_exit_latency_diffclock" value="0" />
+  <parameter name="advanced_default_hwtcl_l1_exit_latency_sameclock" value="0" />
+  <parameter name="advanced_default_hwtcl_low_priority_vc" value="single_vc" />
+  <parameter name="advanced_default_hwtcl_ltr_mechanism" value="false" />
+  <parameter name="advanced_default_hwtcl_ltssm_1ms_timeout" value="disable" />
+  <parameter name="advanced_default_hwtcl_ltssm_freqlocked_check" value="disable" />
+  <parameter name="advanced_default_hwtcl_maximum_current" value="0" />
+  <parameter name="advanced_default_hwtcl_no_command_completed" value="true" />
+  <parameter name="advanced_default_hwtcl_no_soft_reset" value="false" />
+  <parameter name="advanced_default_hwtcl_pclk_out_sel" value="pclk" />
+  <parameter name="advanced_default_hwtcl_pipex1_debug_sel" value="disable" />
+  <parameter name="advanced_default_hwtcl_register_pipe_signals" value="false" />
+  <parameter name="advanced_default_hwtcl_reserved_debug" value="0" />
+  <parameter
+     name="advanced_default_hwtcl_retry_buffer_last_active_address"
+     value="2047" />
+  <parameter name="advanced_default_hwtcl_rx_l0s_count_idl" value="0" />
+  <parameter name="advanced_default_hwtcl_set_l0s" value="0" />
+  <parameter name="advanced_default_hwtcl_skp_os_gen3_count" value="0" />
+  <parameter name="advanced_default_hwtcl_skp_os_schedule_count" value="0" />
+  <parameter name="advanced_default_hwtcl_ssid" value="0" />
+  <parameter name="advanced_default_hwtcl_ssvid" value="0" />
+  <parameter name="advanced_default_hwtcl_tph_completer" value="false" />
+  <parameter name="advanced_default_hwtcl_tx_cdc_almost_empty" value="5" />
+  <parameter name="advanced_default_hwtcl_vc0_clk_enable" value="true" />
+  <parameter name="advanced_default_hwtcl_wrong_device_id" value="disable" />
+  <parameter name="advanced_default_parameter_override" value="0" />
+  <parameter name="ast_width_hwtcl" value="Avalon-ST 128-bit" />
+  <parameter name="bar0_size_mask_hwtcl" value="10" />
+  <parameter name="bar0_type_hwtcl" value="2" />
+  <parameter name="bar1_size_mask_hwtcl" value="0" />
+  <parameter name="bar1_type_hwtcl" value="0" />
+  <parameter name="bar2_size_mask_hwtcl" value="0" />
+  <parameter name="bar2_type_hwtcl" value="0" />
+  <parameter name="bar3_size_mask_hwtcl" value="0" />
+  <parameter name="bar3_type_hwtcl" value="0" />
+  <parameter name="bar4_size_mask_hwtcl" value="0" />
+  <parameter name="bar4_type_hwtcl" value="0" />
+  <parameter name="bar5_size_mask_hwtcl" value="0" />
+  <parameter name="bar5_type_hwtcl" value="0" />
+  <parameter name="change_deemphasis_hwtcl" value="0" />
+  <parameter name="class_code_hwtcl" value="0" />
+  <parameter name="completion_timeout_hwtcl" value="ABCD" />
+  <parameter name="design_environment_hwtcl" value="QSYS" />
+  <parameter name="device_id_hwtcl" value="1" />
+  <parameter name="dll_active_report_support_hwtcl" value="0" />
+  <parameter name="ecrc_check_capable_hwtcl" value="0" />
+  <parameter name="ecrc_gen_capable_hwtcl" value="0" />
+  <parameter name="enable_completion_timeout_disable_hwtcl" value="1" />
+  <parameter name="enable_function_msix_support_hwtcl" value="0" />
+  <parameter name="enable_pcisigtest_hwtcl" value="0" />
+  <parameter name="enable_pipe32_phyip_ser_driver_hwtcl" value="0" />
+  <parameter name="enable_pipe32_sim_hwtcl" value="0" />
+  <parameter name="enable_power_on_rst_pulse_hwtcl" value="0" />
+  <parameter name="enable_slot_register_hwtcl" value="0" />
+  <parameter name="enable_tl_only_sim_hwtcl" value="0" />
+  <parameter name="endpoint_l0_latency_hwtcl" value="0" />
+  <parameter name="endpoint_l1_latency_hwtcl" value="0" />
+  <parameter name="expansion_base_address_register_hwtcl" value="0" />
+  <parameter name="extend_tag_field_hwtcl" value="64" />
+  <parameter name="fixed_preset_on" value="0" />
+  <parameter name="force_hrc" value="0" />
+  <parameter name="force_src" value="0" />
+  <parameter name="full_swing_hwtcl" value="35" />
+  <parameter name="gen123_lane_rate_mode_hwtcl" value="Gen3 (8.0 Gbps)" />
+  <parameter name="gen3_coeff_10_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_nxtber_less_hwtcl">g3_coeff_10_nxtber_less</parameter>
+  <parameter name="gen3_coeff_10_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_nxtber_more_hwtcl">g3_coeff_10_nxtber_more</parameter>
+  <parameter name="gen3_coeff_10_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_10_sel_hwtcl" value="preset_10" />
+  <parameter name="gen3_coeff_11_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_nxtber_less_hwtcl">g3_coeff_11_nxtber_less</parameter>
+  <parameter name="gen3_coeff_11_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_nxtber_more_hwtcl">g3_coeff_11_nxtber_more</parameter>
+  <parameter name="gen3_coeff_11_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_11_sel_hwtcl" value="preset_11" />
+  <parameter name="gen3_coeff_12_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_nxtber_less_hwtcl">g3_coeff_12_nxtber_less</parameter>
+  <parameter name="gen3_coeff_12_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_nxtber_more_hwtcl">g3_coeff_12_nxtber_more</parameter>
+  <parameter name="gen3_coeff_12_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_12_sel_hwtcl" value="preset_12" />
+  <parameter name="gen3_coeff_13_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_nxtber_less_hwtcl">g3_coeff_13_nxtber_less</parameter>
+  <parameter name="gen3_coeff_13_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_nxtber_more_hwtcl">g3_coeff_13_nxtber_more</parameter>
+  <parameter name="gen3_coeff_13_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_13_sel_hwtcl" value="preset_13" />
+  <parameter name="gen3_coeff_14_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_nxtber_less_hwtcl">g3_coeff_14_nxtber_less</parameter>
+  <parameter name="gen3_coeff_14_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_nxtber_more_hwtcl">g3_coeff_14_nxtber_more</parameter>
+  <parameter name="gen3_coeff_14_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_14_sel_hwtcl" value="preset_14" />
+  <parameter name="gen3_coeff_15_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_nxtber_less_hwtcl">g3_coeff_15_nxtber_less</parameter>
+  <parameter name="gen3_coeff_15_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_nxtber_more_hwtcl">g3_coeff_15_nxtber_more</parameter>
+  <parameter name="gen3_coeff_15_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_15_sel_hwtcl" value="preset_15" />
+  <parameter name="gen3_coeff_16_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_nxtber_less_hwtcl">g3_coeff_16_nxtber_less</parameter>
+  <parameter name="gen3_coeff_16_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_nxtber_more_hwtcl">g3_coeff_16_nxtber_more</parameter>
+  <parameter name="gen3_coeff_16_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_16_sel_hwtcl" value="preset_16" />
+  <parameter name="gen3_coeff_17_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_nxtber_less_hwtcl">g3_coeff_17_nxtber_less</parameter>
+  <parameter name="gen3_coeff_17_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_nxtber_more_hwtcl">g3_coeff_17_nxtber_more</parameter>
+  <parameter name="gen3_coeff_17_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_17_sel_hwtcl" value="preset_17" />
+  <parameter name="gen3_coeff_18_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_nxtber_less_hwtcl">g3_coeff_18_nxtber_less</parameter>
+  <parameter name="gen3_coeff_18_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_nxtber_more_hwtcl">g3_coeff_18_nxtber_more</parameter>
+  <parameter name="gen3_coeff_18_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_18_sel_hwtcl" value="preset_18" />
+  <parameter name="gen3_coeff_19_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_nxtber_less_hwtcl">g3_coeff_19_nxtber_less</parameter>
+  <parameter name="gen3_coeff_19_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_nxtber_more_hwtcl">g3_coeff_19_nxtber_more</parameter>
+  <parameter name="gen3_coeff_19_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_19_sel_hwtcl" value="preset_19" />
+  <parameter name="gen3_coeff_1_ber_meas_hwtcl" value="2" />
+  <parameter name="gen3_coeff_1_hwtcl" value="7" />
+  <parameter name="gen3_coeff_1_nxtber_less_hwtcl">g3_coeff_1_nxtber_less</parameter>
+  <parameter name="gen3_coeff_1_nxtber_less_ptr_hwtcl" value="1" />
+  <parameter name="gen3_coeff_1_nxtber_more_hwtcl">g3_coeff_1_nxtber_more</parameter>
+  <parameter name="gen3_coeff_1_nxtber_more_ptr_hwtcl" value="1" />
+  <parameter name="gen3_coeff_1_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_1_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_1_sel_hwtcl" value="preset_1" />
+  <parameter name="gen3_coeff_20_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_nxtber_less_hwtcl">g3_coeff_20_nxtber_less</parameter>
+  <parameter name="gen3_coeff_20_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_nxtber_more_hwtcl">g3_coeff_20_nxtber_more</parameter>
+  <parameter name="gen3_coeff_20_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_20_sel_hwtcl" value="preset_20" />
+  <parameter name="gen3_coeff_21_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_nxtber_less_hwtcl">g3_coeff_21_nxtber_less</parameter>
+  <parameter name="gen3_coeff_21_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_nxtber_more_hwtcl">g3_coeff_21_nxtber_more</parameter>
+  <parameter name="gen3_coeff_21_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_21_sel_hwtcl" value="preset_21" />
+  <parameter name="gen3_coeff_22_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_nxtber_less_hwtcl">g3_coeff_22_nxtber_less</parameter>
+  <parameter name="gen3_coeff_22_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_nxtber_more_hwtcl">g3_coeff_22_nxtber_more</parameter>
+  <parameter name="gen3_coeff_22_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_22_sel_hwtcl" value="preset_22" />
+  <parameter name="gen3_coeff_23_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_nxtber_less_hwtcl">g3_coeff_23_nxtber_less</parameter>
+  <parameter name="gen3_coeff_23_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_nxtber_more_hwtcl">g3_coeff_23_nxtber_more</parameter>
+  <parameter name="gen3_coeff_23_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_23_sel_hwtcl" value="preset_23" />
+  <parameter name="gen3_coeff_24_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_nxtber_less_hwtcl">g3_coeff_24_nxtber_less</parameter>
+  <parameter name="gen3_coeff_24_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_nxtber_more_hwtcl">g3_coeff_24_nxtber_more</parameter>
+  <parameter name="gen3_coeff_24_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_24_sel_hwtcl" value="preset_24" />
+  <parameter name="gen3_coeff_2_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_nxtber_less_hwtcl">g3_coeff_2_nxtber_less</parameter>
+  <parameter name="gen3_coeff_2_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_nxtber_more_hwtcl">g3_coeff_2_nxtber_more</parameter>
+  <parameter name="gen3_coeff_2_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_2_sel_hwtcl" value="preset_2" />
+  <parameter name="gen3_coeff_3_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_nxtber_less_hwtcl">g3_coeff_3_nxtber_less</parameter>
+  <parameter name="gen3_coeff_3_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_nxtber_more_hwtcl">g3_coeff_3_nxtber_more</parameter>
+  <parameter name="gen3_coeff_3_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_3_sel_hwtcl" value="preset_3" />
+  <parameter name="gen3_coeff_4_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_nxtber_less_hwtcl">g3_coeff_4_nxtber_less</parameter>
+  <parameter name="gen3_coeff_4_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_nxtber_more_hwtcl">g3_coeff_4_nxtber_more</parameter>
+  <parameter name="gen3_coeff_4_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_4_sel_hwtcl" value="preset_4" />
+  <parameter name="gen3_coeff_5_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_nxtber_less_hwtcl">g3_coeff_5_nxtber_less</parameter>
+  <parameter name="gen3_coeff_5_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_nxtber_more_hwtcl">g3_coeff_5_nxtber_more</parameter>
+  <parameter name="gen3_coeff_5_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_5_sel_hwtcl" value="preset_5" />
+  <parameter name="gen3_coeff_6_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_nxtber_less_hwtcl">g3_coeff_6_nxtber_less</parameter>
+  <parameter name="gen3_coeff_6_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_nxtber_more_hwtcl">g3_coeff_6_nxtber_more</parameter>
+  <parameter name="gen3_coeff_6_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_6_sel_hwtcl" value="preset_6" />
+  <parameter name="gen3_coeff_7_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_nxtber_less_hwtcl">g3_coeff_7_nxtber_less</parameter>
+  <parameter name="gen3_coeff_7_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_nxtber_more_hwtcl">g3_coeff_7_nxtber_more</parameter>
+  <parameter name="gen3_coeff_7_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_7_sel_hwtcl" value="preset_7" />
+  <parameter name="gen3_coeff_8_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_nxtber_less_hwtcl">g3_coeff_8_nxtber_less</parameter>
+  <parameter name="gen3_coeff_8_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_nxtber_more_hwtcl">g3_coeff_8_nxtber_more</parameter>
+  <parameter name="gen3_coeff_8_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_8_sel_hwtcl" value="preset_8" />
+  <parameter name="gen3_coeff_9_ber_meas_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_nxtber_less_hwtcl">g3_coeff_9_nxtber_less</parameter>
+  <parameter name="gen3_coeff_9_nxtber_less_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_nxtber_more_hwtcl">g3_coeff_9_nxtber_more</parameter>
+  <parameter name="gen3_coeff_9_nxtber_more_ptr_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_preset_hint_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_reqber_hwtcl" value="0" />
+  <parameter name="gen3_coeff_9_sel_hwtcl" value="preset_9" />
+  <parameter name="gen3_full_swing_hwtcl" value="35" />
+  <parameter name="gen3_low_freq_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_10_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_11_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_1_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_2_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_3_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_4_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_5_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_6_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_7_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_8_hwtcl" value="0" />
+  <parameter name="gen3_preset_coeff_9_hwtcl" value="0" />
+  <parameter name="gen3_rxfreqlock_counter_hwtcl" value="0" />
+  <parameter name="hip_reconfig_hwtcl" value="0" />
+  <parameter name="hip_tag_checking_hwtcl" value="1" />
+  <parameter name="hwtcl_override_g2_txvod" value="1" />
+  <parameter name="hwtcl_override_g3rxcoef" value="0" />
+  <parameter name="hwtcl_override_g3txcoef" value="0" />
+  <parameter name="in_cvp_mode_hwtcl" value="0" />
+  <parameter name="io_window_addr_width_hwtcl" value="0" />
+  <parameter name="lane_mask_hwtcl" value="x4" />
+  <parameter name="low_latency_mode_hwtcl" value="0" />
+  <parameter name="max_payload_size_hwtcl" value="256" />
+  <parameter name="msi_64bit_addressing_capable_hwtcl" value="true" />
+  <parameter name="msi_masking_capable_hwtcl" value="false" />
+  <parameter name="msi_multi_message_capable_hwtcl" value="1" />
+  <parameter name="msi_support_hwtcl" value="true" />
+  <parameter name="msix_pba_bir_hwtcl" value="0" />
+  <parameter name="msix_pba_offset_hwtcl" value="0" />
+  <parameter name="msix_table_bir_hwtcl" value="0" />
+  <parameter name="msix_table_offset_hwtcl" value="0" />
+  <parameter name="msix_table_size_hwtcl" value="0" />
+  <parameter name="multiple_packets_per_cycle_hwtcl" value="0" />
+  <parameter name="override_rxbuffer_cred_preset" value="0" />
+  <parameter name="override_tbpartner_driver_setting_hwtcl" value="0" />
+  <parameter name="pcie_inspector_hwtcl" value="0" />
+  <parameter name="pcie_qsys" value="1" />
+  <parameter name="pcie_spec_version_hwtcl" value="3.0" />
+  <parameter name="pll_refclk_freq_hwtcl" value="100 MHz" />
+  <parameter name="port_link_number_hwtcl" value="1" />
+  <parameter name="port_type_hwtcl" value="Native endpoint" />
+  <parameter name="prefetchable_mem_window_addr_width_hwtcl" value="0" />
+  <parameter name="revision_id_hwtcl" value="1" />
+  <parameter name="rpre_emph_a_val_hwtcl" value="9" />
+  <parameter name="rpre_emph_b_val_hwtcl" value="0" />
+  <parameter name="rpre_emph_c_val_hwtcl" value="16" />
+  <parameter name="rpre_emph_d_val_hwtcl" value="13" />
+  <parameter name="rpre_emph_e_val_hwtcl" value="5" />
+  <parameter name="rvod_sel_a_val_hwtcl" value="42" />
+  <parameter name="rvod_sel_b_val_hwtcl" value="38" />
+  <parameter name="rvod_sel_c_val_hwtcl" value="38" />
+  <parameter name="rvod_sel_d_val_hwtcl" value="43" />
+  <parameter name="rvod_sel_e_val_hwtcl" value="15" />
+  <parameter name="rxbuffer_rxreq_hwtcl" value="Minimum" />
+  <parameter name="serial_sim_hwtcl" value="1" />
+  <parameter name="set_pld_clk_x1_625MHz_hwtcl" value="0" />
+  <parameter name="slot_number_hwtcl" value="0" />
+  <parameter name="slot_power_limit_hwtcl" value="0" />
+  <parameter name="slot_power_scale_hwtcl" value="0" />
+  <parameter name="slotclkcfg_hwtcl" value="1" />
+  <parameter name="subsystem_device_id_hwtcl" value="0" />
+  <parameter name="subsystem_vendor_id_hwtcl" value="0" />
+  <parameter name="surprise_down_error_support_hwtcl" value="0" />
+  <parameter name="tlp_insp_trg_dw0_hwtcl" value="2049" />
+  <parameter name="tlp_insp_trg_dw1_hwtcl" value="0" />
+  <parameter name="tlp_insp_trg_dw2_hwtcl" value="0" />
+  <parameter name="tlp_insp_trg_dw3_hwtcl" value="0" />
+  <parameter name="tlp_inspector_hwtcl" value="0" />
+  <parameter name="tlp_inspector_use_signal_probe_hwtcl" value="0" />
+  <parameter name="track_rxfc_cplbuf_ovf_hwtcl" value="0" />
+  <parameter name="use_aer_hwtcl" value="0" />
+  <parameter name="use_ast_parity" value="0" />
+  <parameter name="use_atx_pll_hwtcl" value="0" />
+  <parameter name="use_config_bypass_hwtcl" value="0" />
+  <parameter name="use_crc_forwarding_hwtcl" value="0" />
+  <parameter name="use_cvp_update_core_pof_hwtcl" value="0" />
+  <parameter name="use_pci_ext_hwtcl" value="0" />
+  <parameter name="use_pcie_ext_hwtcl" value="0" />
+  <parameter name="use_rx_st_be_hwtcl" value="0" />
+  <parameter name="use_tx_cons_cred_sel_hwtcl" value="0" />
+  <parameter name="user_id_hwtcl" value="0" />
+  <parameter name="vendor_id_hwtcl" value="4466" />
+  <parameter name="vsec_id_hwtcl" value="40960" />
+  <parameter name="vsec_rev_hwtcl" value="0" />
+ </module>
+ <module
+   name="XCVRCtrlGen3x4"
+   kind="alt_xcvr_reconfig"
+   version="14.1"
+   enabled="1">
+  <parameter name="ber_en" value="0" />
+  <parameter name="device_family" value="Stratix V" />
+  <parameter name="enable_adce" value="1" />
+  <parameter name="enable_analog" value="1" />
+  <parameter name="enable_dcd" value="0" />
+  <parameter name="enable_dcd_power_up" value="1" />
+  <parameter name="enable_dfe" value="0" />
+  <parameter name="enable_eyemon" value="0" />
+  <parameter name="enable_mif" value="0" />
+  <parameter name="enable_offset" value="1" />
+  <parameter name="gui_cal_status_port" value="false" />
+  <parameter name="gui_enable_pll" value="0" />
+  <parameter name="gui_split_sizes" value="" />
+  <parameter name="number_of_reconfig_interfaces" value="6" />
+ </module>
+ <module
+   name="XCVRDrvGen3x4"
+   kind="altera_pcie_reconfig_driver"
+   version="14.1"
+   enabled="1">
+  <parameter name="INTENDED_DEVICE_FAMILY" value="Stratix V" />
+  <parameter name="enable_cal_busy_hwtcl" value="0" />
+  <parameter name="gen123_lane_rate_mode_hwtcl" value="Gen3 (8.0 Gbps)" />
+  <parameter name="number_of_reconfig_interfaces" value="6" />
+ </module>
+ <module name="clk_0" kind="clock_source" version="14.1" enabled="0">
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <connection
+   kind="avalon"
+   version="14.1"
+   start="XCVRDrvGen3x4.reconfig_mgmt"
+   end="XCVRCtrlGen3x4.reconfig_mgmt">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="XCVRDrvGen3x4.hip_currentspeed"
+   end="PCIeGen3x4If128.hip_currentspeed">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="XCVRDrvGen3x4.reconfig_busy"
+   end="XCVRCtrlGen3x4.reconfig_busy">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="XCVRCtrlGen3x4.reconfig_from_xcvr"
+   end="PCIeGen3x4If128.reconfig_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="XCVRCtrlGen3x4.reconfig_to_xcvr"
+   end="PCIeGen3x4If128.reconfig_to_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/fpga/altera/de5_qsys/DE5Gen3x4If128/ip/README.txt b/fpga/altera/de5_qsys/DE5Gen3x4If128/ip/README.txt
new file mode 100644
index 0000000..e69de29
diff --git a/fpga/altera/de5_qsys/DE5Gen3x4If128/prj/DE5Gen3x4If128.qpf b/fpga/altera/de5_qsys/DE5Gen3x4If128/prj/DE5Gen3x4If128.qpf
new file mode 100644
index 0000000..b4e1f62
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen3x4If128/prj/DE5Gen3x4If128.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 16:21:12  June 09, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:21:12  June 09, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "DE5Gen3x4If128"
diff --git a/fpga/altera/de5_qsys/DE5Gen3x4If128/prj/DE5Gen3x4If128.qsf b/fpga/altera/de5_qsys/DE5Gen3x4If128/prj/DE5Gen3x4If128.qsf
new file mode 100644
index 0000000..7235927
--- /dev/null
+++ b/fpga/altera/de5_qsys/DE5Gen3x4If128/prj/DE5Gen3x4If128.qsf
@@ -0,0 +1,569 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 11:03:06  March 21, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		DE5Gen3x4If128_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Stratix V"
+set_global_assignment -name DEVICE 5SGXEA7N2F45C2
+set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen3x4If128
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06  MARCH 21, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION "14.1.0 SP0.19"
+
+################################################################################
+# Timing SDC Files
+################################################################################
+
+################################################################################
+# PCIE Connections
+################################################################################
+# PCIe clk (100 MHz)
+set_location_assignment PIN_AK38 -to PCIE_REFCLK
+
+set_location_assignment PIN_AK39 -to "PCIE_REFCLK(n)"
+
+set_location_assignment PIN_AU33 -to PCIE_RESET_N
+
+
+################################################################################
+#PCIE Pins
+################################################################################
+# Settings from SV PCIE User Guide (AV-ST)
+# 100 Ohm Termination 
+# 1.5V PCML 
+# XCVR_VCCR_VCCT_VOLTAGE 1_0V 
+# XCVR_VCCA_VOLTAGE 3_0V
+# We use CMU PLL's (http://www.altera.com/literature/hb/stratix-v/stx5_52003.pdf)
+# http://www.altera.com/support/kdb/downloads/rd08232012_334/quartusii-12.0sp2-2.dp9-readme.txt
+# Errata: http://www.altera.com/support/kdb/solutions/rd10112012_529.html
+
+################################################################################
+# Gloabal PCIE assignments (Use if signal problems exist)
+################################################################################
+
+################################################################################
+#PCIE RX_IN 0
+################################################################################
+
+set_location_assignment PIN_BB43 -to PCIE_RX_IN[0]
+set_location_assignment PIN_BB44 -to "PCIE_RX_IN[0](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 1
+################################################################################
+
+set_location_assignment PIN_BA41 -to PCIE_RX_IN[1]
+set_location_assignment PIN_BA42 -to "PCIE_RX_IN[1](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 2
+################################################################################
+
+set_location_assignment PIN_AW41 -to PCIE_RX_IN[2]
+set_location_assignment PIN_AW42 -to "PCIE_RX_IN[2](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 3
+################################################################################
+
+set_location_assignment PIN_AY43 -to PCIE_RX_IN[3]
+set_location_assignment PIN_AY44 -to "PCIE_RX_IN[3](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 4
+################################################################################
+
+# set_location_assignment PIN_AT43 -to PCIE_RX_IN[4]
+# set_location_assignment PIN_AT44 -to "PCIE_RX_IN[4](n)"
+
+
+
+################################################################################
+#PCIE RX_IN 5
+################################################################################
+
+# set_location_assignment PIN_AP43 -to PCIE_RX_IN[5]
+# set_location_assignment PIN_AP44 -to "PCIE_RX_IN[5](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 6
+################################################################################
+
+# set_location_assignment PIN_AM43 -to PCIE_RX_IN[6]
+# set_location_assignment PIN_AM44 -to "PCIE_RX_IN[6](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 7
+################################################################################
+
+# set_location_assignment PIN_AK43 -to PCIE_RX_IN[7]
+# set_location_assignment PIN_AK44 -to "PCIE_RX_IN[7](n)"
+
+
+
+
+################################################################################
+#PCIE TX_OUT 0
+################################################################################
+set_location_assignment PIN_AY39 -to PCIE_TX_OUT[0]
+set_location_assignment PIN_AY40 -to "PCIE_TX_OUT[0](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 1
+################################################################################
+set_location_assignment PIN_AV39 -to PCIE_TX_OUT[1]
+set_location_assignment PIN_AV40 -to "PCIE_TX_OUT[1](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 2
+################################################################################
+set_location_assignment PIN_AT39 -to PCIE_TX_OUT[2]
+set_location_assignment PIN_AT40 -to "PCIE_TX_OUT[2](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 3
+################################################################################
+set_location_assignment PIN_AU41 -to PCIE_TX_OUT[3]
+set_location_assignment PIN_AU42 -to "PCIE_TX_OUT[3](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 4
+################################################################################
+# set_location_assignment PIN_AN41 -to PCIE_TX_OUT[4]
+# set_location_assignment PIN_AN42 -to "PCIE_TX_OUT[4](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 5
+################################################################################
+# set_location_assignment PIN_AL41 -to PCIE_TX_OUT[5]
+# set_location_assignment PIN_AL42 -to "PCIE_TX_OUT[5](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 6
+################################################################################
+# set_location_assignment PIN_AJ41 -to PCIE_TX_OUT[6]
+# set_location_assignment PIN_AJ42 -to "PCIE_TX_OUT[6](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 7
+################################################################################
+
+# set_location_assignment PIN_AG41 -to PCIE_TX_OUT[7]
+# set_location_assignment PIN_AG42 -to "PCIE_TX_OUT[7](n)"
+
+
+
+################################################################################
+# LED's
+################################################################################
+
+set_location_assignment PIN_AW37 -to LED[0]
+set_location_assignment PIN_AV37 -to LED[1]
+set_location_assignment PIN_BB36 -to LED[2]
+set_location_assignment PIN_BB39 -to LED[3]
+set_location_assignment PIN_AH15 -to LED[4]
+set_location_assignment PIN_AH13 -to LED[5]
+set_location_assignment PIN_AJ13 -to LED[6]
+set_location_assignment PIN_AJ14 -to LED[7]
+
+################################################################################
+# OSCILLATORS
+################################################################################
+
+set_location_assignment PIN_BC28 -to OSC_BANK3D_50MHZ
+
+################################################################################
+# End Custom Instantiations
+################################################################################
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK
+set_instance_assignment -name IO_STANDARD HCSL -to "PCIE_REFCLK(n)"
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_RESET_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_wake
+set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_smbclk
+set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_smbdata
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[0]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[0]
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[1]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[1]
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[2]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[2]
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[3]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[3]
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[3](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[4]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[4]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[5]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[5]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[6]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[6]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[7]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[7]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[0]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[1]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[2]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[3]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[3](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[4]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[4]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[4]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[4]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[4](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[4](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[4](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[4](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[5]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[5]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[5]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[5]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[5](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[5](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[5](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[5](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[6]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[6]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[6]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[6]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[6](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[6](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[6](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[6](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[7]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[7]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[7]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[7]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[7](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[7](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[7](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_BANK3D_50MHZ
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name SDC_FILE ../constr/DE5Gen3x4If128.sdc
+set_global_assignment -name QSYS_FILE ../ip/QSysDE5Gen3x4If128.qsys
+set_global_assignment -name VERILOG_FILE ../hdl/DE5Gen3x4If128.v
+set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ohtb.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/fpga/altera/de5_qsys/riffa_wrapper_de5.v b/fpga/altera/de5_qsys/riffa_wrapper_de5.v
new file mode 100644
index 0000000..b289dd3
--- /dev/null
+++ b/fpga/altera/de5_qsys/riffa_wrapper_de5.v
@@ -0,0 +1,614 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            riffa_wrapper_de5.v
+// Version:             1.00a
+// Verilog Standard:    Verilog-2001
+// Description:         Wrapper file for all riffa logic for Altera DE5 boards
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`include "ultrascale.vh"
+`include "functions.vh"
+`timescale 1ps / 1ps
+module riffa_wrapper_de5
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Bit-Width from Quartus IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     // Interface: Altera RX 
+     input [C_PCI_DATA_WIDTH-1:0]                 RX_ST_DATA,
+     input [0:0]                                  RX_ST_EOP, // TODO: Should be 2 bits wide in 256-bit interface
+     input [0:0]                                  RX_ST_SOP, // TODO: Should be 2 bits wide in 256-bit interface
+     input [0:0]                                  RX_ST_VALID,
+     output                                       RX_ST_READY,
+     input [0:0]                                  RX_ST_EMPTY,
+
+     // Interface: Altera TX
+     output [C_PCI_DATA_WIDTH-1:0]                TX_ST_DATA,
+     output [0:0]                                 TX_ST_VALID,
+     input                                        TX_ST_READY,
+     output [0:0]                                 TX_ST_EOP,
+     output [0:0]                                 TX_ST_SOP,
+     output [0:0]                                 TX_ST_EMPTY,
+
+     // Interface: Altera Config
+     input [`SIG_CFG_CTL_W-1:0]                   TL_CFG_CTL,
+     input [`SIG_CFG_ADD_W-1:0]                   TL_CFG_ADD,
+     input [`SIG_CFG_STS_W-1:0]                   TL_CFG_STS,
+
+     // Interface: Altera Flow Control
+     input [`SIG_KO_CPLH_W-1:0]                   KO_CPL_SPC_HEADER,
+     input [`SIG_KO_CPLD_W-1:0]                   KO_CPL_SPC_DATA,
+    
+     // Interface: Altera Interrupt
+     input                                        APP_MSI_ACK,
+     output                                       APP_MSI_REQ,
+
+     // Interface: Altera CLK/RESET
+     input                                        PLD_CLK,
+     input                                        RESET_STATUS,
+    
+
+     // RIFFA Interface Signals
+     output                                       RST_OUT,
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_CLK, // Channel read clock
+     output [C_NUM_CHNL-1:0]                      CHNL_RX, // Channel read receive signal
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_ACK, // Channel read received signal
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_LAST, // Channel last read
+     output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
+     output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
+     output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   CHNL_RX_DATA, // Channel read data
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_DATA_VALID, // Channel read data valid
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_DATA_REN, // Channel read data has been recieved
+
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_CLK, // Channel write clock
+     input [C_NUM_CHNL-1:0]                       CHNL_TX, // Channel write receive signal
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_ACK, // Channel write acknowledgement signal
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_LAST, // Channel last write
+     input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]  CHNL_TX_LEN, // Channel write length (in 32 bit words)
+     input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]  CHNL_TX_OFF, // Channel write offset
+     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]    CHNL_TX_DATA, // Channel write data
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_DATA_VALID, // Channel write data valid
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_DATA_REN // Channel write data has been recieved
+     );
+    localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
+    localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
+    localparam C_VENDOR = "ALTERA";
+    
+    localparam C_ALTERA_TX_READY_LATENCY = 2;
+    localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
+    localparam C_PIPELINE_OUTPUT = 1;
+    localparam C_PIPELINE_INPUT = 1;
+
+    wire                                          clk;
+    wire                                          rst_in;
+
+    // Interface: RXC Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxc_data;
+    wire                                          rxc_data_valid;
+    wire                                          rxc_data_start_flag;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxc_data_word_enable;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxc_meta_fdwbe;
+    wire                                          rxc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxc_meta_ldwbe;
+    wire [`SIG_TAG_W-1:0]                         rxc_meta_tag;
+    wire [`SIG_LOWADDR_W-1:0]                     rxc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        rxc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         rxc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     rxc_meta_bytes_remaining;
+    wire [`SIG_CPLID_W-1:0]                       rxc_meta_completer_id;
+    wire                                          rxc_meta_ep;
+
+    // Interface: RXR Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxr_data;
+    wire                                          rxr_data_valid;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxr_data_word_enable;
+    wire                                          rxr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxr_meta_fdwbe;
+    wire                                          rxr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxr_meta_ldwbe;
+    wire [`SIG_TC_W-1:0]                          rxr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        rxr_meta_attr;
+    wire [`SIG_TAG_W-1:0]                         rxr_meta_tag;
+    wire [`SIG_TYPE_W-1:0]                        rxr_meta_type;
+    wire [`SIG_ADDR_W-1:0]                        rxr_meta_addr;
+    wire [`SIG_BARDECODE_W-1:0]                   rxr_meta_bar_decoded;
+    wire [`SIG_REQID_W-1:0]                       rxr_meta_requester_id;
+    wire [`SIG_LEN_W-1:0]                         rxr_meta_length;
+    wire                                          rxr_meta_ep;
+    
+    // interface: TXC Engine
+    wire                                          txc_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txc_data;
+    wire                                          txc_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_start_offset;
+    wire                                          txc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_end_offset;
+    wire                                          txc_data_ready;
+
+    wire                                          txc_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txc_meta_fdwbe;
+    wire [`SIG_LBE_W-1:0]                         txc_meta_ldwbe;
+    wire [`SIG_LOWADDR_W-1:0]                     txc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        txc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         txc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     txc_meta_byte_count;
+    wire [`SIG_TAG_W-1:0]                         txc_meta_tag;
+    wire [`SIG_REQID_W-1:0]                       txc_meta_requester_id;
+    wire [`SIG_TC_W-1:0]                          txc_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txc_meta_attr;
+    wire                                          txc_meta_ep;
+    wire                                          txc_meta_ready;
+    wire                                          txc_sent;
+
+    // Interface: TXR Engine
+    wire                                          txr_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txr_data;
+    wire                                          txr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_start_offset;
+    wire                                          txr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_end_offset;
+    wire                                          txr_data_ready;
+
+    wire                                          txr_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txr_meta_fdwbe; 
+    wire [`SIG_LBE_W-1:0]                         txr_meta_ldwbe;
+    wire [`SIG_ADDR_W-1:0]                        txr_meta_addr;
+    wire [`SIG_LEN_W-1:0]                         txr_meta_length;
+    wire [`SIG_TAG_W-1:0]                         txr_meta_tag;
+    wire [`SIG_TC_W-1:0]                          txr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txr_meta_attr;
+    wire [`SIG_TYPE_W-1:0]                        txr_meta_type;
+    wire                                          txr_meta_ep;
+    wire                                          txr_meta_ready;
+    wire                                          txr_sent;
+
+    // Classic Interface Wires
+    wire                                          wRxTlpReady;
+    wire [C_PCI_DATA_WIDTH-1:0]                   wRxTlp;
+    wire                                          wRxTlpEndFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wRxTlpEndOffset;
+    wire                                          wRxTlpStartFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wRxTlpStartOffset;
+    wire                                          wRxTlpValid;
+    wire [`SIG_BARDECODE_W-1:0]                   wRxTlpBarDecode;
+    
+    wire                                          wTxTlpReady;
+    wire [C_PCI_DATA_WIDTH-1:0]                   wTxTlp;
+    wire                                          wTxTlpEndFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wTxTlpEndOffset;
+    wire                                          wTxTlpStartFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wTxTlpStartOffset;
+    wire                                          wTxTlpValid;
+    
+    // Unconnected Wires (Used in ultrascale interface)
+    // Interface: RQ (TXC)
+    wire                                          s_axis_rq_tlast_nc;
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_rq_tdata_nc;
+    wire [`SIG_RQ_TUSER_W-1:0]                    s_axis_rq_tuser_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_rq_tkeep_nc;
+    wire                                          s_axis_rq_tready_nc = 0;
+    wire                                          s_axis_rq_tvalid_nc;
+    // Interface: RC (RXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_rc_tdata_nc = 0;
+    wire [`SIG_RC_TUSER_W-1:0]                    m_axis_rc_tuser_nc = 0;
+    wire                                          m_axis_rc_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_rc_tkeep_nc = 0;
+    wire                                          m_axis_rc_tvalid_nc = 0;
+    wire                                          m_axis_rc_tready_nc;
+    // Interface: CQ (RXR)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_cq_tdata_nc = 0;
+    wire [`SIG_CQ_TUSER_W-1:0]                    m_axis_cq_tuser_nc = 0;
+    wire                                          m_axis_cq_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_cq_tkeep_nc = 0;
+    wire                                          m_axis_cq_tvalid_nc = 0;
+    wire                                          m_axis_cq_tready_nc = 0;
+    // Interface: CC (TXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_cc_tdata_nc;
+    wire [`SIG_CC_TUSER_W-1:0]                    s_axis_cc_tuser_nc;
+    wire                                          s_axis_cc_tlast_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_cc_tkeep_nc;
+    wire                                          s_axis_cc_tvalid_nc;
+    wire                                          s_axis_cc_tready_nc = 0;
+
+    // Interface: Configuration
+    wire                                          config_bus_master_enable;
+    wire [`SIG_CPLID_W-1:0]                       config_completer_id;
+    wire                                          config_cpl_boundary_sel;
+    wire                                          config_interrupt_msienable;
+    wire [`SIG_LINKRATE_W-1:0]                    config_link_rate;
+    wire [`SIG_LINKWIDTH_W-1:0]                   config_link_width;
+    wire [`SIG_MAXPAYLOAD_W-1:0]                  config_max_payload_size;
+    wire [`SIG_MAXREAD_W-1:0]                     config_max_read_request_size;
+    wire [`SIG_FC_CPLD_W-1:0]                     config_max_cpl_data;
+    wire [`SIG_FC_CPLH_W-1:0]                     config_max_cpl_hdr;
+
+    wire                                          intr_msi_request;
+    wire                                          intr_msi_rdy;
+
+    genvar                                        chnl;
+
+    assign clk = PLD_CLK;
+    assign rst_in = RESET_STATUS;
+
+    translation_altera
+        #(
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH))
+    trans
+        (
+         // Outputs
+         .RX_TLP                            (wRxTlp[C_PCI_DATA_WIDTH-1:0]),
+         .RX_TLP_VALID                      (wRxTlpValid),
+         .RX_TLP_START_FLAG                 (wRxTlpStartFlag),
+         .RX_TLP_START_OFFSET               (wRxTlpStartOffset[`SIG_OFFSET_W-1:0]),
+         .RX_TLP_END_FLAG                   (wRxTlpEndFlag),
+         .RX_TLP_END_OFFSET                 (wRxTlpEndOffset[`SIG_OFFSET_W-1:0]),
+         .RX_TLP_BAR_DECODE                 (wRxTlpBarDecode[`SIG_BARDECODE_W-1:0]),
+         .TX_TLP_READY                      (wTxTlpReady),
+         .CONFIG_COMPLETER_ID               (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE          (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH                 (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE                  (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE      (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE           (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE        (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL           (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA               (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR                (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+         .INTR_MSI_RDY                      (intr_msi_rdy),
+         // Inputs
+         .CLK                               (clk),
+         .RST_IN                            (rst_in),
+         .RX_TLP_READY                      (wRxTlpReady),
+         .TX_TLP                            (wTxTlp[C_PCI_DATA_WIDTH-1:0]),
+         .TX_TLP_VALID                      (wTxTlpValid),
+         .TX_TLP_START_FLAG                 (wTxTlpStartFlag),
+         .TX_TLP_START_OFFSET               (wTxTlpStartOffset[`SIG_OFFSET_W-1:0]),
+         .TX_TLP_END_FLAG                   (wTxTlpEndFlag),
+         .TX_TLP_END_OFFSET                 (wTxTlpEndOffset[`SIG_OFFSET_W-1:0]),
+         .INTR_MSI_REQUEST                  (intr_msi_request),
+         /*AUTOINST*/
+         // Outputs
+         .RX_ST_READY                   (RX_ST_READY),
+         .TX_ST_DATA                    (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (TX_ST_VALID[0:0]),
+         .TX_ST_EOP                     (TX_ST_EOP[0:0]),
+         .TX_ST_SOP                     (TX_ST_SOP[0:0]),
+         .TX_ST_EMPTY                   (TX_ST_EMPTY[0:0]),
+         .APP_MSI_REQ                   (APP_MSI_REQ),
+         // Inputs
+         .RX_ST_DATA                    (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (RX_ST_EOP[0:0]),
+         .RX_ST_SOP                     (RX_ST_SOP[0:0]),
+         .RX_ST_VALID                   (RX_ST_VALID[0:0]),
+         .RX_ST_EMPTY                   (RX_ST_EMPTY[0:0]),
+         .TX_ST_READY                   (TX_ST_READY),
+         .TL_CFG_CTL                    (TL_CFG_CTL[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (TL_CFG_ADD[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (TL_CFG_STS[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (KO_CPL_SPC_HEADER[`SIG_FC_CPLH_W-1:0]),
+         .KO_CPL_SPC_DATA               (KO_CPL_SPC_DATA[`SIG_FC_CPLD_W-1:0]),
+         .APP_MSI_ACK                   (APP_MSI_ACK));
+
+    engine_layer
+        #(// Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_BYTES/4),
+          .C_VENDOR                     (C_VENDOR))
+    engine_layer_inst
+        (// Outputs
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+         // Unconnected Outputs
+         .TX_TLP                        (wTxTlp),
+         .TX_TLP_VALID                  (wTxTlpValid),
+         .TX_TLP_START_FLAG             (wTxTlpStartFlag),
+         .TX_TLP_START_OFFSET           (wTxTlpStartOffset),
+         .TX_TLP_END_FLAG               (wTxTlpEndFlag),
+         .TX_TLP_END_OFFSET             (wTxTlpEndOffset),
+
+         .RX_TLP_READY                  (wRxTlpReady),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+         // Unconnected Inputs
+         .RX_TLP                        (wRxTlp),
+         .RX_TLP_VALID                  (wRxTlpValid),
+         .RX_TLP_START_FLAG             (wRxTlpStartFlag),
+         .RX_TLP_START_OFFSET           (wRxTlpStartOffset),
+         .RX_TLP_END_FLAG               (wRxTlpEndFlag),
+         .RX_TLP_END_OFFSET             (wRxTlpEndOffset),
+         .RX_TLP_BAR_DECODE             (wRxTlpBarDecode),
+
+         .TX_TLP_READY                  (wTxTlpReady),
+         // Outputs
+         .M_AXIS_CQ_TREADY              (m_axis_cq_tready_nc),
+         .M_AXIS_RC_TREADY              (m_axis_rc_tready_nc),
+         .S_AXIS_CC_TVALID              (s_axis_cc_tvalid_nc),
+         .S_AXIS_CC_TLAST               (s_axis_cc_tlast_nc),
+         .S_AXIS_CC_TDATA               (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (s_axis_rq_tvalid_nc),
+         .S_AXIS_RQ_TLAST               (s_axis_rq_tlast_nc),
+         .S_AXIS_RQ_TDATA               (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (m_axis_cq_tvalid_nc),
+         .M_AXIS_CQ_TLAST               (m_axis_cq_tlast_nc),
+         .M_AXIS_CQ_TDATA               (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (m_axis_rc_tvalid_nc),
+         .M_AXIS_RC_TLAST               (m_axis_rc_tlast_nc),
+         .M_AXIS_RC_TDATA               (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (s_axis_cc_tready_nc),
+         .S_AXIS_RQ_TREADY              (s_axis_rq_tready_nc)
+         /*AUTOINST*/);
+
+    riffa
+        #(.C_TAG_WIDTH                  (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_MAX_READ_REQ_BYTES         (C_MAX_READ_REQ_BYTES),
+          .C_VENDOR                     (C_VENDOR),
+          .C_FPGA_NAME                  (C_FPGA_NAME))
+    riffa_inst
+        (// Outputs
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+
+         .INTR_MSI_REQUEST              (intr_msi_request),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),         
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE      (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH             (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE              (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE  (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE       (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE    (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL       (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA           (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR            (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+        
+         .INTR_MSI_RDY                  (intr_msi_rdy),
+
+         /*AUTOINST*/
+         // Outputs
+         .RST_OUT                       (RST_OUT),
+         .CHNL_RX                       (CHNL_RX[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_RX_OFF                   (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_RX_DATA                  (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
+         // Inputs
+         .CHNL_RX_CLK                   (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (CHNL_TX[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_TX_OFF                   (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_TX_DATA                  (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("../../engine/" "../../riffa/" "../../trans")
+// End:
+
diff --git a/fpga/riffa_hdl/altera.vh b/fpga/riffa_hdl/altera.vh
new file mode 100644
index 0000000..0c4d1da
--- /dev/null
+++ b/fpga/riffa_hdl/altera.vh
@@ -0,0 +1,68 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            altera.vh
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The altera.vh file is a header file that defines
+// various ALTERA-specific primitives.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`ifndef __ALTERA_VH
+`define __ALTERA_VH 1
+
+`define TLCFG_DEVCTL_I `SIG_CFG_ADD_W'h0 
+`define TLCFG_LNKCTL_I `SIG_CFG_ADD_W'h2
+`define TLCFG_PRMCMD_I `SIG_CFG_ADD_W'h3
+`define TLCFG_MSICSR_I `SIG_CFG_ADD_W'hD
+`define TLCFG_BUSDEV_I `SIG_CFG_ADD_W'hF
+
+`define TLSTS_LWIDTH_R 40:35
+`define TLSTS_LRATE_R 34:31
+
+`define TLCTL_MAXREQ_R 30:28
+`define TLCTL_MAXPAY_R 23:21
+`define TLCTL_RCB_R 19:19
+`define TLCTL_BUSMSTR_R 10:10
+`define TLCTL_MSIENABLE_R 0:0
+`define TLCTL_BUSDEV_R 12:0
+
+`define SIG_CFG_STS_W 53
+`define SIG_CFG_CTL_W 32
+`define SIG_CFG_ADD_W 4
+
+`define SIG_KO_CPLD_W 12
+`define SIG_KO_CPLH_W 8
+`endif
diff --git a/fpga/riffa_hdl/async_fifo.v b/fpga/riffa_hdl/async_fifo.v
new file mode 100644
index 0000000..62b98b0
--- /dev/null
+++ b/fpga/riffa_hdl/async_fifo.v
@@ -0,0 +1,311 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			async_fifo.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Asynchronous capable parameterized FIFO. As with all
+// traditional FIFOs, the RD_DATA will be valid one cycle following a RD_EN 
+// assertion. RD_EMPTY will remain low until the cycle following the last RD_EN 
+// assertion. Note, that RD_EMPTY may actually be high on the same cycle that 
+// RD_DATA contains valid data.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+// Additional Comments: Based on design by CE Cummings in Simulation and 
+// Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer 
+// Comparisons
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+module async_fifo #(
+	parameter C_WIDTH = 32,	// Data bus width
+	parameter C_DEPTH = 1024,	// Depth of the FIFO
+	// Local parameters
+	parameter C_REAL_DEPTH = 2**clog2(C_DEPTH),
+	parameter C_DEPTH_BITS = clog2(C_REAL_DEPTH),
+	parameter C_DEPTH_P1_BITS = clog2(C_REAL_DEPTH+1)
+)
+(
+	input RD_CLK,							// Read clock
+	input RD_RST,							// Read synchronous reset
+	input WR_CLK,						 	// Write clock
+	input WR_RST,							// Write synchronous reset
+	input [C_WIDTH-1:0] WR_DATA, 			// Write data input (WR_CLK)
+	input WR_EN, 							// Write enable, high active (WR_CLK)
+	output [C_WIDTH-1:0] RD_DATA, 			// Read data output (RD_CLK)
+	input RD_EN,							// Read enable, high active (RD_CLK)
+	output WR_FULL, 						// Full condition (WR_CLK)
+	output RD_EMPTY 						// Empty condition (RD_CLK)
+);
+
+`include "functions.vh"
+
+wire						wCmpEmpty;
+wire						wCmpFull;
+wire	[C_DEPTH_BITS-1:0]	wWrPtr;
+wire	[C_DEPTH_BITS-1:0]	wRdPtr;
+wire	[C_DEPTH_BITS-1:0]	wWrPtrP1;
+wire	[C_DEPTH_BITS-1:0]	wRdPtrP1;
+
+
+// Memory block (synthesis attributes applied to this module will
+// determine the memory option).
+ram_2clk_1w_1r #(.C_RAM_WIDTH(C_WIDTH), .C_RAM_DEPTH(C_REAL_DEPTH)) mem (
+	.CLKA(WR_CLK),
+	.ADDRA(wWrPtr),
+	.WEA(WR_EN & !WR_FULL),
+	.DINA(WR_DATA),
+	.CLKB(RD_CLK),
+	.ADDRB(wRdPtr),
+	.DOUTB(RD_DATA)
+);
+
+
+// Compare the pointers.
+async_cmp #(.C_DEPTH_BITS(C_DEPTH_BITS)) asyncCompare (
+	.WR_RST(WR_RST),
+	.WR_CLK(WR_CLK),
+	.RD_RST(RD_RST),
+	.RD_CLK(RD_CLK),
+	.RD_VALID(RD_EN & !RD_EMPTY),
+	.WR_VALID(WR_EN & !WR_FULL),
+	.EMPTY(wCmpEmpty), 
+	.FULL(wCmpFull),
+	.WR_PTR(wWrPtr), 
+	.WR_PTR_P1(wWrPtrP1), 
+	.RD_PTR(wRdPtr), 
+	.RD_PTR_P1(wRdPtrP1)
+);
+
+
+// Calculate empty
+rd_ptr_empty #(.C_DEPTH_BITS(C_DEPTH_BITS)) rdPtrEmpty (
+	.RD_EMPTY(RD_EMPTY), 
+	.RD_PTR(wRdPtr),
+	.RD_PTR_P1(wRdPtrP1),
+	.CMP_EMPTY(wCmpEmpty), 
+	.RD_EN(RD_EN),
+	.RD_CLK(RD_CLK), 
+	.RD_RST(RD_RST)
+);
+
+
+// Calculate full
+wr_ptr_full #(.C_DEPTH_BITS(C_DEPTH_BITS)) wrPtrFull (
+	.WR_CLK(WR_CLK), 
+	.WR_RST(WR_RST),
+	.WR_EN(WR_EN),
+	.WR_FULL(WR_FULL), 
+	.WR_PTR(wWrPtr),
+	.WR_PTR_P1(wWrPtrP1),
+	.CMP_FULL(wCmpFull)
+);
+ 
+endmodule
+
+
+module async_cmp #(
+  parameter C_DEPTH_BITS = 4,
+  // Local parameters
+  parameter N = C_DEPTH_BITS-1
+)
+(
+	input WR_RST,
+	input WR_CLK,
+	input RD_RST,
+	input RD_CLK,
+	input RD_VALID,
+	input WR_VALID,
+	output EMPTY, 
+	output FULL, 
+	input [C_DEPTH_BITS-1:0] WR_PTR, 
+	input [C_DEPTH_BITS-1:0] RD_PTR, 
+	input [C_DEPTH_BITS-1:0] WR_PTR_P1, 
+	input [C_DEPTH_BITS-1:0] RD_PTR_P1
+);
+  
+reg				rDir=0;
+wire			wDirSet = (  (WR_PTR[N]^RD_PTR[N-1]) & ~(WR_PTR[N-1]^RD_PTR[N]));
+wire			wDirClr = ((~(WR_PTR[N]^RD_PTR[N-1]) &  (WR_PTR[N-1]^RD_PTR[N])) | WR_RST);
+
+reg				rRdValid=0;
+reg				rEmpty=1;
+reg				rFull=0;
+wire			wATBEmpty = ((WR_PTR == RD_PTR_P1) && (RD_VALID | rRdValid));
+wire			wATBFull = ((WR_PTR_P1 == RD_PTR) && WR_VALID);
+wire			wEmpty = ((WR_PTR == RD_PTR) && !rDir);
+wire			wFull = ((WR_PTR == RD_PTR) && rDir);
+
+assign EMPTY = wATBEmpty || rEmpty;
+assign FULL  = wATBFull || rFull;
+
+always @(posedge wDirSet or posedge wDirClr)
+if (wDirClr) 
+	rDir <= 1'b0;
+else
+	rDir <= 1'b1;
+
+always @(posedge RD_CLK) begin
+	rEmpty <= (RD_RST ? 1'd1 : wEmpty);
+	rRdValid <= (RD_RST ? 1'd0 : RD_VALID);
+end
+
+always @(posedge WR_CLK) begin
+	rFull <= (WR_RST ? 1'd0 : wFull);
+end
+
+endmodule 
+ 
+ 
+module rd_ptr_empty #(
+	parameter C_DEPTH_BITS = 4
+)
+(
+	input RD_CLK, 
+	input RD_RST,
+	input RD_EN, 
+	output RD_EMPTY,
+	output [C_DEPTH_BITS-1:0] RD_PTR,
+	output [C_DEPTH_BITS-1:0] RD_PTR_P1,
+	input CMP_EMPTY 
+);
+
+reg							rEmpty=1;
+reg							rEmpty2=1;
+reg		[C_DEPTH_BITS-1:0]	rRdPtr=0;
+reg		[C_DEPTH_BITS-1:0]	rRdPtrP1=0;
+reg		[C_DEPTH_BITS-1:0]	rBin=0;
+reg		[C_DEPTH_BITS-1:0]	rBinP1=1;
+wire	[C_DEPTH_BITS-1:0]	wGrayNext;
+wire	[C_DEPTH_BITS-1:0]	wGrayNextP1;
+wire	[C_DEPTH_BITS-1:0]	wBinNext;
+wire	[C_DEPTH_BITS-1:0]	wBinNextP1;
+
+assign RD_EMPTY = rEmpty;
+assign RD_PTR = rRdPtr;
+assign RD_PTR_P1 = rRdPtrP1;
+
+// Gray coded pointer
+always @(posedge RD_CLK or posedge RD_RST) begin
+	if (RD_RST) begin
+		rBin <= #1 0;
+		rBinP1 <= #1 1;
+		rRdPtr <= #1 0;
+		rRdPtrP1 <= #1 0;
+	end
+	else begin
+		rBin <= #1 wBinNext;
+		rBinP1 <= #1 wBinNextP1;
+		rRdPtr <= #1 wGrayNext;
+		rRdPtrP1 <= #1 wGrayNextP1;
+	end
+end
+
+// Increment the binary count if not empty
+assign wBinNext = (!rEmpty ? rBin + RD_EN : rBin);
+assign wBinNextP1 = (!rEmpty ? rBinP1 + RD_EN : rBinP1);
+assign wGrayNext = ((wBinNext>>1) ^ wBinNext); // binary-to-gray conversion
+assign wGrayNextP1 = ((wBinNextP1>>1) ^ wBinNextP1); // binary-to-gray conversion
+
+always @(posedge RD_CLK) begin
+	if (CMP_EMPTY)
+		{rEmpty, rEmpty2} <= #1 2'b11;
+	else
+		{rEmpty, rEmpty2} <= #1 {rEmpty2, CMP_EMPTY};
+end
+
+endmodule
+ 
+ 
+module wr_ptr_full #(
+	parameter C_DEPTH_BITS = 4
+)
+(
+	input WR_CLK, 
+	input WR_RST,
+	input WR_EN,
+	output WR_FULL, 
+	output [C_DEPTH_BITS-1:0] WR_PTR, 
+	output [C_DEPTH_BITS-1:0] WR_PTR_P1, 
+	input CMP_FULL
+);
+
+reg							rFull=0;
+reg							rFull2=0;
+reg		[C_DEPTH_BITS-1:0]	rPtr=0;
+reg		[C_DEPTH_BITS-1:0]	rPtrP1=0;
+reg		[C_DEPTH_BITS-1:0]	rBin=0;
+reg		[C_DEPTH_BITS-1:0]	rBinP1=1;
+wire	[C_DEPTH_BITS-1:0]	wGrayNext;
+wire	[C_DEPTH_BITS-1:0]	wGrayNextP1;
+wire	[C_DEPTH_BITS-1:0]	wBinNext;
+wire	[C_DEPTH_BITS-1:0]	wBinNextP1;
+
+assign WR_FULL = rFull;
+assign WR_PTR = rPtr;
+assign WR_PTR_P1 = rPtrP1;
+
+// Gray coded pointer
+always @(posedge WR_CLK or posedge WR_RST) begin
+	if (WR_RST) begin
+		rBin <= #1 0;
+		rBinP1 <= #1 1;
+		rPtr <= #1 0;
+		rPtrP1 <= #1 0;
+	end
+	else begin
+		rBin <= #1 wBinNext;
+		rBinP1 <= #1 wBinNextP1;
+		rPtr <= #1 wGrayNext;
+		rPtrP1 <= #1 wGrayNextP1;
+	end
+end
+
+// Increment the binary count if not full
+assign wBinNext = (!rFull ? rBin + WR_EN : rBin);
+assign wBinNextP1 = (!rFull ? rBinP1 + WR_EN : rBinP1);
+assign wGrayNext = ((wBinNext>>1) ^ wBinNext); // binary-to-gray conversion
+assign wGrayNextP1 = ((wBinNextP1>>1) ^ wBinNextP1); // binary-to-gray conversion
+
+always @(posedge WR_CLK) begin
+	if (WR_RST) 
+		{rFull, rFull2} <= #1 2'b00;
+	else if (CMP_FULL) 
+		{rFull, rFull2} <= #1 2'b11;
+	else
+		{rFull, rFull2} <= #1 {rFull2, CMP_FULL};
+end
+
+endmodule
+
diff --git a/fpga/riffa_hdl/async_fifo_fwft.v b/fpga/riffa_hdl/async_fifo_fwft.v
new file mode 100644
index 0000000..36b4e76
--- /dev/null
+++ b/fpga/riffa_hdl/async_fifo_fwft.v
@@ -0,0 +1,138 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			async_fifo_fwft.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			An asynchronous capable parameterized FIFO. As with all
+// first word fall through FIFOs, the RD_DATA will be valid when RD_EMPTY is 
+// low. Asserting RD_EN will consume the current RD_DATA value and cause the 
+// next value (if it exists) to appear on RD_DATA on the following cycle. Be sure 
+// to check if RD_EMPTY is low each cycle to determine if RD_DATA is valid.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+module async_fifo_fwft #(
+	parameter C_WIDTH = 32,	// Data bus width
+	parameter C_DEPTH = 1024,	// Depth of the FIFO
+	// Local parameters
+	parameter C_REAL_DEPTH = 2**clog2(C_DEPTH),
+	parameter C_DEPTH_BITS = clog2s(C_REAL_DEPTH),
+	parameter C_DEPTH_P1_BITS = clog2s(C_REAL_DEPTH+1)
+)
+(
+	input RD_CLK,							// Read clock
+	input RD_RST,							// Read synchronous reset
+	input WR_CLK,						 	// Write clock
+	input WR_RST,							// Write synchronous reset
+	input [C_WIDTH-1:0] WR_DATA, 			// Write data input (WR_CLK)
+	input WR_EN, 							// Write enable, high active (WR_CLK)
+	output [C_WIDTH-1:0] RD_DATA, 			// Read data output (RD_CLK)
+	input RD_EN,							// Read enable, high active (RD_CLK)
+	output WR_FULL, 						// Full condition (WR_CLK)
+	output RD_EMPTY 						// Empty condition (RD_CLK)
+);
+
+`include "functions.vh"
+
+reg		[C_WIDTH-1:0]			rData=0;
+reg		[C_WIDTH-1:0]			rCache=0;
+reg		[1:0]					rCount=0;
+reg								rFifoDataValid=0;
+reg								rDataValid=0;
+reg								rCacheValid=0;
+wire	[C_WIDTH-1:0]			wData;
+wire							wEmpty;
+wire							wRen = RD_EN || (rCount < 2'd2);
+
+
+assign RD_DATA = rData;
+assign RD_EMPTY = !rDataValid;
+
+
+// Wrapped non-FWFT FIFO (synthesis attributes applied to this module will
+// determine the memory option).
+async_fifo #(.C_WIDTH(C_WIDTH), .C_DEPTH(C_DEPTH)) fifo (
+	.WR_CLK(WR_CLK),
+	.WR_RST(WR_RST),
+	.RD_CLK(RD_CLK),
+	.RD_RST(RD_RST),
+	.WR_EN(WR_EN),
+	.WR_DATA(WR_DATA),
+	.WR_FULL(WR_FULL),
+	.RD_EN(wRen),
+	.RD_DATA(wData),
+	.RD_EMPTY(wEmpty)
+);
+
+always @ (posedge RD_CLK) begin
+	if (RD_RST) begin
+		rCount <= #1 0;
+		rDataValid <= #1 0;
+		rCacheValid <= #1 0;
+		rFifoDataValid <= #1 0;
+	end
+	else begin
+		// Keep track of the count
+		rCount <= #1 rCount + (wRen & !wEmpty) - (!RD_EMPTY & RD_EN);
+
+		// Signals when wData from FIFO is valid
+		rFifoDataValid <= #1 (wRen & !wEmpty);
+
+		// Keep rData up to date
+		if (rFifoDataValid) begin
+			if (RD_EN | !rDataValid) begin
+				rData <= #1 wData;
+				rDataValid <= #1 1'd1;
+				rCacheValid <= #1 1'd0;
+			end
+			else begin
+				rCacheValid <= #1 1'd1;
+			end
+			rCache  <= #1 wData;
+		end
+		else begin
+			if (RD_EN | !rDataValid) begin
+				rData <= #1 rCache;
+				rDataValid <= #1 rCacheValid;
+				rCacheValid <= #1 1'd0;
+			end
+		end
+	end
+end
+ 
+endmodule
+ 
diff --git a/fpga/riffa_hdl/channel.v b/fpga/riffa_hdl/channel.v
new file mode 100644
index 0000000..c8fdb06
--- /dev/null
+++ b/fpga/riffa_hdl/channel.v
@@ -0,0 +1,352 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+`include "riffa.vh"
+module channel
+    #(
+      parameter C_DATA_WIDTH = 128,
+      parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+      parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
+      )
+    (
+     input                         CLK,
+     input                         RST,
+     input [2:0]                   CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+     input [2:0]                   CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
+
+     input [31:0]                  PIO_DATA, // Single word programmed I/O data
+     input [C_DATA_WIDTH-1:0]      ENG_DATA, // Main incoming data 
+
+     output                        SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
+     input                         SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
+     input                         SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
+     input                         SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
+
+     output                        SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
+     input                         SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
+     input                         SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
+     input                         SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
+
+     input                         TXN_RX_LEN_VALID, // Read transaction length valid
+     input                         TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
+     output [31:0]                 TXN_RX_DONE_LEN, // Read transaction actual transfer length
+     output                        TXN_RX_DONE, // Read transaction done
+     input                         TXN_RX_DONE_ACK, // Read transaction actual transfer length read
+
+     output                        TXN_TX, // Write transaction notification
+     input                         TXN_TX_ACK, // Write transaction acknowledged
+     output [31:0]                 TXN_TX_LEN, // Write transaction length
+     output [31:0]                 TXN_TX_OFF_LAST, // Write transaction offset/last
+     output [31:0]                 TXN_TX_DONE_LEN, // Write transaction actual transfer length
+     output                        TXN_TX_DONE, // Write transaction done
+     input                         TXN_TX_DONE_ACK, // Write transaction actual transfer length read
+
+     output                        RX_REQ, // Read request
+     input                         RX_REQ_ACK, // Read request accepted
+     output [1:0]                  RX_REQ_TAG, // Read request data tag 
+     output [63:0]                 RX_REQ_ADDR, // Read request address
+     output [9:0]                  RX_REQ_LEN, // Read request length
+
+     output                        TX_REQ, // Outgoing write request
+     input                         TX_REQ_ACK, // Outgoing write request acknowledged
+     output [63:0]                 TX_ADDR, // Outgoing write high address
+     output [9:0]                  TX_LEN, // Outgoing write length (in 32 bit words)
+     output [C_DATA_WIDTH-1:0]     TX_DATA, // Outgoing write data
+     input                         TX_DATA_REN, // Outgoing write data read enable
+     input                         TX_SENT, // Outgoing write complete
+
+     input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
+     input                         MAIN_DONE, // Main incoming data complete
+     input                         MAIN_ERR, // Main incoming data completed with error
+
+     input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
+     input                         SG_RX_DONE, // Scatter gather for RX incoming data complete
+     input                         SG_RX_ERR, // Scatter gather for RX incoming data completed with error
+
+     input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
+     input                         SG_TX_DONE, // Scatter gather for TX incoming data complete
+     input                         SG_TX_ERR, // Scatter gather for TX incoming data completed with error
+
+     input                         CHNL_RX_CLK, // Channel read clock
+     output                        CHNL_RX, // Channel read receive signal
+     input                         CHNL_RX_ACK, // Channle read received signal
+     output                        CHNL_RX_LAST, // Channel last read
+     output [31:0]                 CHNL_RX_LEN, // Channel read length
+     output [30:0]                 CHNL_RX_OFF, // Channel read offset
+     output [C_DATA_WIDTH-1:0]     CHNL_RX_DATA, // Channel read data
+     output                        CHNL_RX_DATA_VALID, // Channel read data valid
+     input                         CHNL_RX_DATA_REN, // Channel read data has been recieved
+
+     input                         CHNL_TX_CLK, // Channel write clock
+     input                         CHNL_TX, // Channel write receive signal
+     output                        CHNL_TX_ACK, // Channel write acknowledgement signal
+     input                         CHNL_TX_LAST, // Channel last write
+     input [31:0]                  CHNL_TX_LEN, // Channel write length (in 32 bit words)
+     input [30:0]                  CHNL_TX_OFF, // Channel write offset
+     input [C_DATA_WIDTH-1:0]      CHNL_TX_DATA, // Channel write data
+     input                         CHNL_TX_DATA_VALID, // Channel write data valid
+     output                        CHNL_TX_DATA_REN                         // Channel write data has been recieved
+     );
+    generate
+        if(C_DATA_WIDTH == 32) begin
+            channel_32 
+                #(
+                  .C_DATA_WIDTH(C_DATA_WIDTH), 
+                  .C_MAX_READ_REQ(C_MAX_READ_REQ)
+                  )
+            channel 
+                (/*AUTOINST*/
+                 // Outputs
+                 .SG_RX_BUF_RECVD           (SG_RX_BUF_RECVD),
+                 .SG_TX_BUF_RECVD           (SG_TX_BUF_RECVD),
+                 .TXN_RX_DONE_LEN           (TXN_RX_DONE_LEN[31:0]),
+                 .TXN_RX_DONE               (TXN_RX_DONE),
+                 .TXN_TX                    (TXN_TX),
+                 .TXN_TX_LEN                (TXN_TX_LEN[31:0]),
+                 .TXN_TX_OFF_LAST           (TXN_TX_OFF_LAST[31:0]),
+                 .TXN_TX_DONE_LEN           (TXN_TX_DONE_LEN[31:0]),
+                 .TXN_TX_DONE               (TXN_TX_DONE),
+                 .RX_REQ                    (RX_REQ),
+                 .RX_REQ_TAG                (RX_REQ_TAG[1:0]),
+                 .RX_REQ_ADDR               (RX_REQ_ADDR[63:0]),
+                 .RX_REQ_LEN                (RX_REQ_LEN[9:0]),
+                 .TX_REQ                    (TX_REQ),
+                 .TX_ADDR                   (TX_ADDR[63:0]),
+                 .TX_LEN                    (TX_LEN[9:0]),
+                 .TX_DATA                   (TX_DATA[C_DATA_WIDTH-1:0]),
+                 .CHNL_RX                   (CHNL_RX),
+                 .CHNL_RX_LAST              (CHNL_RX_LAST),
+                 .CHNL_RX_LEN               (CHNL_RX_LEN[31:0]),
+                 .CHNL_RX_OFF               (CHNL_RX_OFF[30:0]),
+                 .CHNL_RX_DATA              (CHNL_RX_DATA[C_DATA_WIDTH-1:0]),
+                 .CHNL_RX_DATA_VALID        (CHNL_RX_DATA_VALID),
+                 .CHNL_TX_ACK               (CHNL_TX_ACK),
+                 .CHNL_TX_DATA_REN          (CHNL_TX_DATA_REN),
+                 // Inputs
+                 .CLK                       (CLK),
+                 .RST                       (RST),
+                 .CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
+                 .CONFIG_MAX_PAYLOAD_SIZE   (CONFIG_MAX_PAYLOAD_SIZE[2:0]),
+                 .PIO_DATA                  (PIO_DATA[31:0]),
+                 .ENG_DATA                  (ENG_DATA[C_DATA_WIDTH-1:0]),
+                 .SG_RX_BUF_LEN_VALID       (SG_RX_BUF_LEN_VALID),
+                 .SG_RX_BUF_ADDR_HI_VALID   (SG_RX_BUF_ADDR_HI_VALID),
+                 .SG_RX_BUF_ADDR_LO_VALID   (SG_RX_BUF_ADDR_LO_VALID),
+                 .SG_TX_BUF_LEN_VALID       (SG_TX_BUF_LEN_VALID),
+                 .SG_TX_BUF_ADDR_HI_VALID   (SG_TX_BUF_ADDR_HI_VALID),
+                 .SG_TX_BUF_ADDR_LO_VALID   (SG_TX_BUF_ADDR_LO_VALID),
+                 .TXN_RX_LEN_VALID          (TXN_RX_LEN_VALID),
+                 .TXN_RX_OFF_LAST_VALID     (TXN_RX_OFF_LAST_VALID),
+                 .TXN_RX_DONE_ACK           (TXN_RX_DONE_ACK),
+                 .TXN_TX_ACK                (TXN_TX_ACK),
+                 .TXN_TX_DONE_ACK           (TXN_TX_DONE_ACK),
+                 .RX_REQ_ACK                (RX_REQ_ACK),
+                 .TX_REQ_ACK                (TX_REQ_ACK),
+                 .TX_DATA_REN               (TX_DATA_REN),
+                 .TX_SENT                   (TX_SENT),
+                 .MAIN_DATA_EN              (MAIN_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
+                 .MAIN_DONE                 (MAIN_DONE),
+                 .MAIN_ERR                  (MAIN_ERR),
+                 .SG_RX_DATA_EN             (SG_RX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
+                 .SG_RX_DONE                (SG_RX_DONE),
+                 .SG_RX_ERR                 (SG_RX_ERR),
+                 .SG_TX_DATA_EN             (SG_TX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
+                 .SG_TX_DONE                (SG_TX_DONE),
+                 .SG_TX_ERR                 (SG_TX_ERR),
+                 .CHNL_RX_CLK               (CHNL_RX_CLK),
+                 .CHNL_RX_ACK               (CHNL_RX_ACK),
+                 .CHNL_RX_DATA_REN          (CHNL_RX_DATA_REN),
+                 .CHNL_TX_CLK               (CHNL_TX_CLK),
+                 .CHNL_TX                   (CHNL_TX),
+                 .CHNL_TX_LAST              (CHNL_TX_LAST),
+                 .CHNL_TX_LEN               (CHNL_TX_LEN[31:0]),
+                 .CHNL_TX_OFF               (CHNL_TX_OFF[30:0]),
+                 .CHNL_TX_DATA              (CHNL_TX_DATA[C_DATA_WIDTH-1:0]),
+                 .CHNL_TX_DATA_VALID        (CHNL_TX_DATA_VALID));
+        end else if(C_DATA_WIDTH == 64) begin
+            channel_64 
+                #(
+                  .C_DATA_WIDTH(C_DATA_WIDTH), 
+                  .C_MAX_READ_REQ(C_MAX_READ_REQ)
+                  )
+            channel 
+                (/*AUTOINST*/
+                 // Outputs
+                 .SG_RX_BUF_RECVD           (SG_RX_BUF_RECVD),
+                 .SG_TX_BUF_RECVD           (SG_TX_BUF_RECVD),
+                 .TXN_RX_DONE_LEN           (TXN_RX_DONE_LEN[31:0]),
+                 .TXN_RX_DONE               (TXN_RX_DONE),
+                 .TXN_TX                    (TXN_TX),
+                 .TXN_TX_LEN                (TXN_TX_LEN[31:0]),
+                 .TXN_TX_OFF_LAST           (TXN_TX_OFF_LAST[31:0]),
+                 .TXN_TX_DONE_LEN           (TXN_TX_DONE_LEN[31:0]),
+                 .TXN_TX_DONE               (TXN_TX_DONE),
+                 .RX_REQ                    (RX_REQ),
+                 .RX_REQ_TAG                (RX_REQ_TAG[1:0]),
+                 .RX_REQ_ADDR               (RX_REQ_ADDR[63:0]),
+                 .RX_REQ_LEN                (RX_REQ_LEN[9:0]),
+                 .TX_REQ                    (TX_REQ),
+                 .TX_ADDR                   (TX_ADDR[63:0]),
+                 .TX_LEN                    (TX_LEN[9:0]),
+                 .TX_DATA                   (TX_DATA[C_DATA_WIDTH-1:0]),
+                 .CHNL_RX                   (CHNL_RX),
+                 .CHNL_RX_LAST              (CHNL_RX_LAST),
+                 .CHNL_RX_LEN               (CHNL_RX_LEN[31:0]),
+                 .CHNL_RX_OFF               (CHNL_RX_OFF[30:0]),
+                 .CHNL_RX_DATA              (CHNL_RX_DATA[C_DATA_WIDTH-1:0]),
+                 .CHNL_RX_DATA_VALID        (CHNL_RX_DATA_VALID),
+                 .CHNL_TX_ACK               (CHNL_TX_ACK),
+                 .CHNL_TX_DATA_REN          (CHNL_TX_DATA_REN),
+                 // Inputs
+                 .CLK                       (CLK),
+                 .RST                       (RST),
+                 .CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
+                 .CONFIG_MAX_PAYLOAD_SIZE   (CONFIG_MAX_PAYLOAD_SIZE[2:0]),
+                 .PIO_DATA                  (PIO_DATA[31:0]),
+                 .ENG_DATA                  (ENG_DATA[C_DATA_WIDTH-1:0]),
+                 .SG_RX_BUF_LEN_VALID       (SG_RX_BUF_LEN_VALID),
+                 .SG_RX_BUF_ADDR_HI_VALID   (SG_RX_BUF_ADDR_HI_VALID),
+                 .SG_RX_BUF_ADDR_LO_VALID   (SG_RX_BUF_ADDR_LO_VALID),
+                 .SG_TX_BUF_LEN_VALID       (SG_TX_BUF_LEN_VALID),
+                 .SG_TX_BUF_ADDR_HI_VALID   (SG_TX_BUF_ADDR_HI_VALID),
+                 .SG_TX_BUF_ADDR_LO_VALID   (SG_TX_BUF_ADDR_LO_VALID),
+                 .TXN_RX_LEN_VALID          (TXN_RX_LEN_VALID),
+                 .TXN_RX_OFF_LAST_VALID     (TXN_RX_OFF_LAST_VALID),
+                 .TXN_RX_DONE_ACK           (TXN_RX_DONE_ACK),
+                 .TXN_TX_ACK                (TXN_TX_ACK),
+                 .TXN_TX_DONE_ACK           (TXN_TX_DONE_ACK),
+                 .RX_REQ_ACK                (RX_REQ_ACK),
+                 .TX_REQ_ACK                (TX_REQ_ACK),
+                 .TX_DATA_REN               (TX_DATA_REN),
+                 .TX_SENT                   (TX_SENT),
+                 .MAIN_DATA_EN              (MAIN_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
+                 .MAIN_DONE                 (MAIN_DONE),
+                 .MAIN_ERR                  (MAIN_ERR),
+                 .SG_RX_DATA_EN             (SG_RX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
+                 .SG_RX_DONE                (SG_RX_DONE),
+                 .SG_RX_ERR                 (SG_RX_ERR),
+                 .SG_TX_DATA_EN             (SG_TX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
+                 .SG_TX_DONE                (SG_TX_DONE),
+                 .SG_TX_ERR                 (SG_TX_ERR),
+                 .CHNL_RX_CLK               (CHNL_RX_CLK),
+                 .CHNL_RX_ACK               (CHNL_RX_ACK),
+                 .CHNL_RX_DATA_REN          (CHNL_RX_DATA_REN),
+                 .CHNL_TX_CLK               (CHNL_TX_CLK),
+                 .CHNL_TX                   (CHNL_TX),
+                 .CHNL_TX_LAST              (CHNL_TX_LAST),
+                 .CHNL_TX_LEN               (CHNL_TX_LEN[31:0]),
+                 .CHNL_TX_OFF               (CHNL_TX_OFF[30:0]),
+                 .CHNL_TX_DATA              (CHNL_TX_DATA[C_DATA_WIDTH-1:0]),
+                 .CHNL_TX_DATA_VALID        (CHNL_TX_DATA_VALID));
+        end else if(C_DATA_WIDTH == 128) begin
+            channel_128
+                #(
+                  .C_DATA_WIDTH(C_DATA_WIDTH), 
+                  .C_MAX_READ_REQ(C_MAX_READ_REQ)
+                  )
+            channel 
+                (/*AUTOINST*/
+                 // Outputs
+                 .SG_RX_BUF_RECVD           (SG_RX_BUF_RECVD),
+                 .SG_TX_BUF_RECVD           (SG_TX_BUF_RECVD),
+                 .TXN_RX_DONE_LEN           (TXN_RX_DONE_LEN[31:0]),
+                 .TXN_RX_DONE               (TXN_RX_DONE),
+                 .TXN_TX                    (TXN_TX),
+                 .TXN_TX_LEN                (TXN_TX_LEN[31:0]),
+                 .TXN_TX_OFF_LAST           (TXN_TX_OFF_LAST[31:0]),
+                 .TXN_TX_DONE_LEN           (TXN_TX_DONE_LEN[31:0]),
+                 .TXN_TX_DONE               (TXN_TX_DONE),
+                 .RX_REQ                    (RX_REQ),
+                 .RX_REQ_TAG                (RX_REQ_TAG[1:0]),
+                 .RX_REQ_ADDR               (RX_REQ_ADDR[63:0]),
+                 .RX_REQ_LEN                (RX_REQ_LEN[9:0]),
+                 .TX_REQ                    (TX_REQ),
+                 .TX_ADDR                   (TX_ADDR[63:0]),
+                 .TX_LEN                    (TX_LEN[9:0]),
+                 .TX_DATA                   (TX_DATA[C_DATA_WIDTH-1:0]),
+                 .CHNL_RX                   (CHNL_RX),
+                 .CHNL_RX_LAST              (CHNL_RX_LAST),
+                 .CHNL_RX_LEN               (CHNL_RX_LEN[31:0]),
+                 .CHNL_RX_OFF               (CHNL_RX_OFF[30:0]),
+                 .CHNL_RX_DATA              (CHNL_RX_DATA[C_DATA_WIDTH-1:0]),
+                 .CHNL_RX_DATA_VALID        (CHNL_RX_DATA_VALID),
+                 .CHNL_TX_ACK               (CHNL_TX_ACK),
+                 .CHNL_TX_DATA_REN          (CHNL_TX_DATA_REN),
+                 // Inputs
+                 .CLK                       (CLK),
+                 .RST                       (RST),
+                 .CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
+                 .CONFIG_MAX_PAYLOAD_SIZE   (CONFIG_MAX_PAYLOAD_SIZE[2:0]),
+                 .PIO_DATA                  (PIO_DATA[31:0]),
+                 .ENG_DATA                  (ENG_DATA[C_DATA_WIDTH-1:0]),
+                 .SG_RX_BUF_LEN_VALID       (SG_RX_BUF_LEN_VALID),
+                 .SG_RX_BUF_ADDR_HI_VALID   (SG_RX_BUF_ADDR_HI_VALID),
+                 .SG_RX_BUF_ADDR_LO_VALID   (SG_RX_BUF_ADDR_LO_VALID),
+                 .SG_TX_BUF_LEN_VALID       (SG_TX_BUF_LEN_VALID),
+                 .SG_TX_BUF_ADDR_HI_VALID   (SG_TX_BUF_ADDR_HI_VALID),
+                 .SG_TX_BUF_ADDR_LO_VALID   (SG_TX_BUF_ADDR_LO_VALID),
+                 .TXN_RX_LEN_VALID          (TXN_RX_LEN_VALID),
+                 .TXN_RX_OFF_LAST_VALID     (TXN_RX_OFF_LAST_VALID),
+                 .TXN_RX_DONE_ACK           (TXN_RX_DONE_ACK),
+                 .TXN_TX_ACK                (TXN_TX_ACK),
+                 .TXN_TX_DONE_ACK           (TXN_TX_DONE_ACK),
+                 .RX_REQ_ACK                (RX_REQ_ACK),
+                 .TX_REQ_ACK                (TX_REQ_ACK),
+                 .TX_DATA_REN               (TX_DATA_REN),
+                 .TX_SENT                   (TX_SENT),
+                 .MAIN_DATA_EN              (MAIN_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
+                 .MAIN_DONE                 (MAIN_DONE),
+                 .MAIN_ERR                  (MAIN_ERR),
+                 .SG_RX_DATA_EN             (SG_RX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
+                 .SG_RX_DONE                (SG_RX_DONE),
+                 .SG_RX_ERR                 (SG_RX_ERR),
+                 .SG_TX_DATA_EN             (SG_TX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
+                 .SG_TX_DONE                (SG_TX_DONE),
+                 .SG_TX_ERR                 (SG_TX_ERR),
+                 .CHNL_RX_CLK               (CHNL_RX_CLK),
+                 .CHNL_RX_ACK               (CHNL_RX_ACK),
+                 .CHNL_RX_DATA_REN          (CHNL_RX_DATA_REN),
+                 .CHNL_TX_CLK               (CHNL_TX_CLK),
+                 .CHNL_TX                   (CHNL_TX),
+                 .CHNL_TX_LAST              (CHNL_TX_LAST),
+                 .CHNL_TX_LEN               (CHNL_TX_LEN[31:0]),
+                 .CHNL_TX_OFF               (CHNL_TX_OFF[30:0]),
+                 .CHNL_TX_DATA              (CHNL_TX_DATA[C_DATA_WIDTH-1:0]),
+                 .CHNL_TX_DATA_VALID        (CHNL_TX_DATA_VALID));
+        end 
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "import")
+// End:
diff --git a/fpga/riffa_hdl/channel_128.v b/fpga/riffa_hdl/channel_128.v
new file mode 100644
index 0000000..145430f
--- /dev/null
+++ b/fpga/riffa_hdl/channel_128.v
@@ -0,0 +1,255 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			channel_128.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Represents a RIFFA channel. Contains a RX port and a 
+// TX port.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+module channel_128 #(
+	parameter C_DATA_WIDTH = 9'd128,
+	parameter C_MAX_READ_REQ = 2,					// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+	// Local parameters
+	parameter C_RX_FIFO_DEPTH = 1024,
+	parameter C_TX_FIFO_DEPTH = 512,
+	parameter C_SG_FIFO_DEPTH = 1024,
+	parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
+)
+(
+	input CLK,
+	input RST,
+	input [2:0] CONFIG_MAX_READ_REQUEST_SIZE,		// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+	input [2:0] CONFIG_MAX_PAYLOAD_SIZE,			// Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
+
+	input [31:0] PIO_DATA,							// Single word programmed I/O data
+	input [C_DATA_WIDTH-1:0] ENG_DATA,				// Main incoming data 
+
+	output SG_RX_BUF_RECVD,							// Scatter gather RX buffer completely read (ready for next if applicable)
+	input SG_RX_BUF_LEN_VALID,						// Scatter gather RX buffer length valid
+	input SG_RX_BUF_ADDR_HI_VALID,					// Scatter gather RX buffer high address valid
+	input SG_RX_BUF_ADDR_LO_VALID,					// Scatter gather RX buffer low address valid
+
+	output SG_TX_BUF_RECVD,							// Scatter gather TX buffer completely read (ready for next if applicable)
+	input SG_TX_BUF_LEN_VALID,						// Scatter gather TX buffer length valid
+	input SG_TX_BUF_ADDR_HI_VALID,					// Scatter gather TX buffer high address valid
+	input SG_TX_BUF_ADDR_LO_VALID,					// Scatter gather TX buffer low address valid
+
+	input TXN_RX_LEN_VALID,							// Read transaction length valid
+	input TXN_RX_OFF_LAST_VALID,					// Read transaction offset/last valid
+	output [31:0] TXN_RX_DONE_LEN,					// Read transaction actual transfer length
+	output TXN_RX_DONE,								// Read transaction done
+	input TXN_RX_DONE_ACK,							// Read transaction actual transfer length read
+
+	output TXN_TX,									// Write transaction notification
+	input TXN_TX_ACK,								// Write transaction acknowledged
+	output [31:0] TXN_TX_LEN,						// Write transaction length
+	output [31:0] TXN_TX_OFF_LAST,					// Write transaction offset/last
+	output [31:0] TXN_TX_DONE_LEN,					// Write transaction actual transfer length
+	output TXN_TX_DONE,								// Write transaction done
+	input TXN_TX_DONE_ACK,							// Write transaction actual transfer length read
+
+	output RX_REQ,									// Read request
+	input RX_REQ_ACK,								// Read request accepted
+	output [1:0] RX_REQ_TAG,						// Read request data tag 
+	output [63:0] RX_REQ_ADDR,						// Read request address
+	output [9:0] RX_REQ_LEN,						// Read request length
+
+	output TX_REQ,									// Outgoing write request
+	input TX_REQ_ACK,								// Outgoing write request acknowledged
+	output [63:0] TX_ADDR,							// Outgoing write high address
+	output [9:0] TX_LEN,							// Outgoing write length (in 32 bit words)
+	output [C_DATA_WIDTH-1:0] TX_DATA,				// Outgoing write data
+	input TX_DATA_REN,								// Outgoing write data read enable
+	input TX_SENT,									// Outgoing write complete
+
+	input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN,		// Main incoming data enable
+	input MAIN_DONE,								// Main incoming data complete
+	input MAIN_ERR,									// Main incoming data completed with error
+
+	input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN,	// Scatter gather for RX incoming data enable
+	input SG_RX_DONE,								// Scatter gather for RX incoming data complete
+	input SG_RX_ERR,								// Scatter gather for RX incoming data completed with error
+
+	input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN,	// Scatter gather for TX incoming data enable
+	input SG_TX_DONE,								// Scatter gather for TX incoming data complete
+	input SG_TX_ERR,								// Scatter gather for TX incoming data completed with error
+
+	input CHNL_RX_CLK,									// Channel read clock
+	output CHNL_RX,									// Channel read receive signal
+	input CHNL_RX_ACK,								// Channle read received signal
+	output CHNL_RX_LAST,							// Channel last read
+	output [31:0] CHNL_RX_LEN,						// Channel read length
+	output [30:0] CHNL_RX_OFF,						// Channel read offset
+	output [C_DATA_WIDTH-1:0] CHNL_RX_DATA,			// Channel read data
+	output CHNL_RX_DATA_VALID,						// Channel read data valid
+	input CHNL_RX_DATA_REN, 						// Channel read data has been recieved
+
+	input CHNL_TX_CLK,								// Channel write clock
+	input CHNL_TX,									// Channel write receive signal
+	output CHNL_TX_ACK,								// Channel write acknowledgement signal
+	input CHNL_TX_LAST,								// Channel last write
+	input [31:0] CHNL_TX_LEN,						// Channel write length (in 32 bit words)
+	input [30:0] CHNL_TX_OFF,						// Channel write offset
+	input [C_DATA_WIDTH-1:0] CHNL_TX_DATA,			// Channel write data
+	input CHNL_TX_DATA_VALID,						// Channel write data valid
+	output CHNL_TX_DATA_REN							// Channel write data has been recieved
+);
+
+`include "functions.vh"
+
+
+wire	[C_DATA_WIDTH-1:0]	wTxSgData;
+wire						wTxSgDataEmpty;
+wire						wTxSgDataRen;
+wire						wTxSgDataErr;
+wire						wTxSgDataRst;
+
+
+// Receiving port (data to the channel)
+rx_port_128 #(
+	.C_DATA_WIDTH(C_DATA_WIDTH), 
+	.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH), 
+	.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
+	.C_MAX_READ_REQ(C_MAX_READ_REQ)
+) rxPort (
+	.RST(RST), 
+	.CLK(CLK), 
+	.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE), 
+	
+	.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
+	.SG_RX_BUF_DATA(PIO_DATA),
+	.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
+	.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
+	.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
+	
+	.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
+	.SG_TX_BUF_DATA(PIO_DATA),
+	.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
+	.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
+	.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
+	
+	.SG_DATA(wTxSgData),
+	.SG_DATA_EMPTY(wTxSgDataEmpty),
+	.SG_DATA_REN(wTxSgDataRen),
+	.SG_RST(wTxSgDataRst),
+	.SG_ERR(wTxSgDataErr),
+	
+	.TXN_DATA(PIO_DATA), 
+	.TXN_LEN_VALID(TXN_RX_LEN_VALID), 
+	.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID), 
+	.TXN_DONE_LEN(TXN_RX_DONE_LEN),
+	.TXN_DONE(TXN_RX_DONE),
+	.TXN_DONE_ACK(TXN_RX_DONE_ACK),
+	
+	.RX_REQ(RX_REQ),
+	.RX_REQ_ACK(RX_REQ_ACK),
+	.RX_REQ_TAG(RX_REQ_TAG),
+	.RX_REQ_ADDR(RX_REQ_ADDR),
+	.RX_REQ_LEN(RX_REQ_LEN),
+
+	.MAIN_DATA(ENG_DATA),
+	.MAIN_DATA_EN(MAIN_DATA_EN), 
+	.MAIN_DONE(MAIN_DONE), 
+	.MAIN_ERR(MAIN_ERR),
+	
+	.SG_RX_DATA(ENG_DATA),
+	.SG_RX_DATA_EN(SG_RX_DATA_EN), 
+	.SG_RX_DONE(SG_RX_DONE), 
+	.SG_RX_ERR(SG_RX_ERR),
+
+	.SG_TX_DATA(ENG_DATA),
+	.SG_TX_DATA_EN(SG_TX_DATA_EN), 
+	.SG_TX_DONE(SG_TX_DONE), 
+	.SG_TX_ERR(SG_TX_ERR),
+
+	.CHNL_CLK(CHNL_RX_CLK), 
+	.CHNL_RX(CHNL_RX), 
+	.CHNL_RX_ACK(CHNL_RX_ACK), 
+	.CHNL_RX_LAST(CHNL_RX_LAST), 
+	.CHNL_RX_LEN(CHNL_RX_LEN), 
+	.CHNL_RX_OFF(CHNL_RX_OFF), 
+	.CHNL_RX_DATA(CHNL_RX_DATA), 
+	.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID), 
+	.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
+);
+
+
+// Sending port (data from the channel)
+tx_port_128 #(
+	.C_DATA_WIDTH(C_DATA_WIDTH), 
+	.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
+) txPort (
+	.CLK(CLK), 
+	.RST(RST), 
+	.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE), 
+	
+	.TXN(TXN_TX),
+	.TXN_ACK(TXN_TX_ACK),
+	.TXN_LEN(TXN_TX_LEN),
+	.TXN_OFF_LAST(TXN_TX_OFF_LAST),
+	.TXN_DONE_LEN(TXN_TX_DONE_LEN),
+	.TXN_DONE(TXN_TX_DONE),
+	.TXN_DONE_ACK(TXN_TX_DONE_ACK),
+	
+	.SG_DATA(wTxSgData),
+	.SG_DATA_EMPTY(wTxSgDataEmpty),
+	.SG_DATA_REN(wTxSgDataRen),
+	.SG_RST(wTxSgDataRst),
+	.SG_ERR(wTxSgDataErr),
+	
+	.TX_REQ(TX_REQ), 
+	.TX_REQ_ACK(TX_REQ_ACK),
+	.TX_ADDR(TX_ADDR), 
+	.TX_LEN(TX_LEN), 
+	.TX_DATA(TX_DATA),
+	.TX_DATA_REN(TX_DATA_REN), 
+	.TX_SENT(TX_SENT),
+
+	.CHNL_CLK(CHNL_TX_CLK), 
+	.CHNL_TX(CHNL_TX), 
+	.CHNL_TX_ACK(CHNL_TX_ACK),
+	.CHNL_TX_LAST(CHNL_TX_LAST), 
+	.CHNL_TX_LEN(CHNL_TX_LEN), 
+	.CHNL_TX_OFF(CHNL_TX_OFF), 
+	.CHNL_TX_DATA(CHNL_TX_DATA), 
+	.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID), 
+	.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
+);
+
+endmodule
diff --git a/fpga/riffa_hdl/channel_32.v b/fpga/riffa_hdl/channel_32.v
new file mode 100644
index 0000000..0caf62e
--- /dev/null
+++ b/fpga/riffa_hdl/channel_32.v
@@ -0,0 +1,255 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			channel_32.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Represents a RIFFA channel. Contains a RX port and a 
+// TX port.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+module channel_32 #(
+	parameter C_DATA_WIDTH = 9'd32,
+	parameter C_MAX_READ_REQ = 2,					// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+	// Local parameters
+	parameter C_RX_FIFO_DEPTH = 1024,
+	parameter C_TX_FIFO_DEPTH = 512,
+	parameter C_SG_FIFO_DEPTH = 1024,
+	parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
+)
+(
+	input CLK,
+	input RST,
+	input [2:0] CONFIG_MAX_READ_REQUEST_SIZE,		// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+	input [2:0] CONFIG_MAX_PAYLOAD_SIZE,			// Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
+
+	input [31:0] PIO_DATA,							// Single word programmed I/O data
+	input [C_DATA_WIDTH-1:0] ENG_DATA,				// Main incoming data 
+
+	output SG_RX_BUF_RECVD,							// Scatter gather RX buffer completely read (ready for next if applicable)
+	input SG_RX_BUF_LEN_VALID,						// Scatter gather RX buffer length valid
+	input SG_RX_BUF_ADDR_HI_VALID,					// Scatter gather RX buffer high address valid
+	input SG_RX_BUF_ADDR_LO_VALID,					// Scatter gather RX buffer low address valid
+
+	output SG_TX_BUF_RECVD,							// Scatter gather TX buffer completely read (ready for next if applicable)
+	input SG_TX_BUF_LEN_VALID,						// Scatter gather TX buffer length valid
+	input SG_TX_BUF_ADDR_HI_VALID,					// Scatter gather TX buffer high address valid
+	input SG_TX_BUF_ADDR_LO_VALID,					// Scatter gather TX buffer low address valid
+
+	input TXN_RX_LEN_VALID,							// Read transaction length valid
+	input TXN_RX_OFF_LAST_VALID,					// Read transaction offset/last valid
+	output [31:0] TXN_RX_DONE_LEN,					// Read transaction actual transfer length
+	output TXN_RX_DONE,								// Read transaction done
+	input TXN_RX_DONE_ACK,							// Read transaction actual transfer length read
+
+	output TXN_TX,									// Write transaction notification
+	input TXN_TX_ACK,								// Write transaction acknowledged
+	output [31:0] TXN_TX_LEN,						// Write transaction length
+	output [31:0] TXN_TX_OFF_LAST,					// Write transaction offset/last
+	output [31:0] TXN_TX_DONE_LEN,					// Write transaction actual transfer length
+	output TXN_TX_DONE,								// Write transaction done
+	input TXN_TX_DONE_ACK,							// Write transaction actual transfer length read
+
+	output RX_REQ,									// Read request
+	input RX_REQ_ACK,								// Read request accepted
+	output [1:0] RX_REQ_TAG,						// Read request data tag 
+	output [63:0] RX_REQ_ADDR,						// Read request address
+	output [9:0] RX_REQ_LEN,						// Read request length
+
+	output TX_REQ,									// Outgoing write request
+	input TX_REQ_ACK,								// Outgoing write request acknowledged
+	output [63:0] TX_ADDR,							// Outgoing write high address
+	output [9:0] TX_LEN,							// Outgoing write length (in 32 bit words)
+	output [C_DATA_WIDTH-1:0] TX_DATA,				// Outgoing write data
+	input TX_DATA_REN,								// Outgoing write data read enable
+	input TX_SENT,									// Outgoing write complete
+
+	input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN,		// Main incoming data enable
+	input MAIN_DONE,								// Main incoming data complete
+	input MAIN_ERR,									// Main incoming data completed with error
+
+	input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN,	// Scatter gather for RX incoming data enable
+	input SG_RX_DONE,								// Scatter gather for RX incoming data complete
+	input SG_RX_ERR,								// Scatter gather for RX incoming data completed with error
+
+	input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN,	// Scatter gather for TX incoming data enable
+	input SG_TX_DONE,								// Scatter gather for TX incoming data complete
+	input SG_TX_ERR,								// Scatter gather for TX incoming data completed with error
+
+	input CHNL_RX_CLK,									// Channel read clock
+	output CHNL_RX,									// Channel read receive signal
+	input CHNL_RX_ACK,								// Channle read received signal
+	output CHNL_RX_LAST,							// Channel last read
+	output [31:0] CHNL_RX_LEN,						// Channel read length
+	output [30:0] CHNL_RX_OFF,						// Channel read offset
+	output [C_DATA_WIDTH-1:0] CHNL_RX_DATA,			// Channel read data
+	output CHNL_RX_DATA_VALID,						// Channel read data valid
+	input CHNL_RX_DATA_REN, 						// Channel read data has been recieved
+
+	input CHNL_TX_CLK,								// Channel write clock
+	input CHNL_TX,									// Channel write receive signal
+	output CHNL_TX_ACK,								// Channel write acknowledgement signal
+	input CHNL_TX_LAST,								// Channel last write
+	input [31:0] CHNL_TX_LEN,						// Channel write length (in 32 bit words)
+	input [30:0] CHNL_TX_OFF,						// Channel write offset
+	input [C_DATA_WIDTH-1:0] CHNL_TX_DATA,			// Channel write data
+	input CHNL_TX_DATA_VALID,						// Channel write data valid
+	output CHNL_TX_DATA_REN							// Channel write data has been recieved
+);
+
+`include "functions.vh"
+
+
+wire	[C_DATA_WIDTH-1:0]	wTxSgData;
+wire						wTxSgDataEmpty;
+wire						wTxSgDataRen;
+wire						wTxSgDataErr;
+wire						wTxSgDataRst;
+
+
+// Receiving port (data to the channel)
+rx_port_32 #(
+	.C_DATA_WIDTH(C_DATA_WIDTH), 
+	.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH), 
+	.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
+	.C_MAX_READ_REQ(C_MAX_READ_REQ)
+) rxPort (
+	.RST(RST), 
+	.CLK(CLK), 
+	.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE), 
+	
+	.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
+	.SG_RX_BUF_DATA(PIO_DATA),
+	.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
+	.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
+	.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
+	
+	.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
+	.SG_TX_BUF_DATA(PIO_DATA),
+	.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
+	.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
+	.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
+	
+	.SG_DATA(wTxSgData),
+	.SG_DATA_EMPTY(wTxSgDataEmpty),
+	.SG_DATA_REN(wTxSgDataRen),
+	.SG_RST(wTxSgDataRst),
+	.SG_ERR(wTxSgDataErr),
+	
+	.TXN_DATA(PIO_DATA), 
+	.TXN_LEN_VALID(TXN_RX_LEN_VALID), 
+	.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID), 
+	.TXN_DONE_LEN(TXN_RX_DONE_LEN),
+	.TXN_DONE(TXN_RX_DONE),
+	.TXN_DONE_ACK(TXN_RX_DONE_ACK),
+	
+	.RX_REQ(RX_REQ),
+	.RX_REQ_ACK(RX_REQ_ACK),
+	.RX_REQ_TAG(RX_REQ_TAG),
+	.RX_REQ_ADDR(RX_REQ_ADDR),
+	.RX_REQ_LEN(RX_REQ_LEN),
+
+	.MAIN_DATA(ENG_DATA),
+	.MAIN_DATA_EN(MAIN_DATA_EN), 
+	.MAIN_DONE(MAIN_DONE), 
+	.MAIN_ERR(MAIN_ERR),
+	
+	.SG_RX_DATA(ENG_DATA),
+	.SG_RX_DATA_EN(SG_RX_DATA_EN), 
+	.SG_RX_DONE(SG_RX_DONE), 
+	.SG_RX_ERR(SG_RX_ERR),
+
+	.SG_TX_DATA(ENG_DATA),
+	.SG_TX_DATA_EN(SG_TX_DATA_EN), 
+	.SG_TX_DONE(SG_TX_DONE), 
+	.SG_TX_ERR(SG_TX_ERR),
+
+	.CHNL_CLK(CHNL_RX_CLK), 
+	.CHNL_RX(CHNL_RX), 
+	.CHNL_RX_ACK(CHNL_RX_ACK), 
+	.CHNL_RX_LAST(CHNL_RX_LAST), 
+	.CHNL_RX_LEN(CHNL_RX_LEN), 
+	.CHNL_RX_OFF(CHNL_RX_OFF), 
+	.CHNL_RX_DATA(CHNL_RX_DATA), 
+	.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID), 
+	.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
+);
+
+
+// Sending port (data from the channel)
+tx_port_32 #(
+	.C_DATA_WIDTH(C_DATA_WIDTH), 
+	.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
+) txPort (
+	.CLK(CLK), 
+	.RST(RST), 
+	.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE), 
+	
+	.TXN(TXN_TX),
+	.TXN_ACK(TXN_TX_ACK),
+	.TXN_LEN(TXN_TX_LEN),
+	.TXN_OFF_LAST(TXN_TX_OFF_LAST),
+	.TXN_DONE_LEN(TXN_TX_DONE_LEN),
+	.TXN_DONE(TXN_TX_DONE),
+	.TXN_DONE_ACK(TXN_TX_DONE_ACK),
+	
+	.SG_DATA(wTxSgData),
+	.SG_DATA_EMPTY(wTxSgDataEmpty),
+	.SG_DATA_REN(wTxSgDataRen),
+	.SG_RST(wTxSgDataRst),
+	.SG_ERR(wTxSgDataErr),
+	
+	.TX_REQ(TX_REQ), 
+	.TX_REQ_ACK(TX_REQ_ACK),
+	.TX_ADDR(TX_ADDR), 
+	.TX_LEN(TX_LEN), 
+	.TX_DATA(TX_DATA),
+	.TX_DATA_REN(TX_DATA_REN), 
+	.TX_SENT(TX_SENT),
+
+	.CHNL_CLK(CHNL_TX_CLK), 
+	.CHNL_TX(CHNL_TX), 
+	.CHNL_TX_ACK(CHNL_TX_ACK),
+	.CHNL_TX_LAST(CHNL_TX_LAST), 
+	.CHNL_TX_LEN(CHNL_TX_LEN), 
+	.CHNL_TX_OFF(CHNL_TX_OFF), 
+	.CHNL_TX_DATA(CHNL_TX_DATA), 
+	.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID), 
+	.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
+);
+
+endmodule
diff --git a/fpga/riffa_hdl/channel_64.v b/fpga/riffa_hdl/channel_64.v
new file mode 100644
index 0000000..389b1bc
--- /dev/null
+++ b/fpga/riffa_hdl/channel_64.v
@@ -0,0 +1,255 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			channel_64.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Represents a RIFFA channel. Contains a RX port and a 
+// TX port.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+module channel_64 #(
+	parameter C_DATA_WIDTH = 9'd64,
+	parameter C_MAX_READ_REQ = 2,					// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+	// Local parameters
+	parameter C_RX_FIFO_DEPTH = 1024,
+	parameter C_TX_FIFO_DEPTH = 512,
+	parameter C_SG_FIFO_DEPTH = 1024,
+	parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
+)
+(
+	input CLK,
+	input RST,
+	input [2:0] CONFIG_MAX_READ_REQUEST_SIZE,		// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+	input [2:0] CONFIG_MAX_PAYLOAD_SIZE,			// Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
+
+	input [31:0] PIO_DATA,							// Single word programmed I/O data
+	input [C_DATA_WIDTH-1:0] ENG_DATA,				// Main incoming data 
+
+	output SG_RX_BUF_RECVD,							// Scatter gather RX buffer completely read (ready for next if applicable)
+	input SG_RX_BUF_LEN_VALID,						// Scatter gather RX buffer length valid
+	input SG_RX_BUF_ADDR_HI_VALID,					// Scatter gather RX buffer high address valid
+	input SG_RX_BUF_ADDR_LO_VALID,					// Scatter gather RX buffer low address valid
+
+	output SG_TX_BUF_RECVD,							// Scatter gather TX buffer completely read (ready for next if applicable)
+	input SG_TX_BUF_LEN_VALID,						// Scatter gather TX buffer length valid
+	input SG_TX_BUF_ADDR_HI_VALID,					// Scatter gather TX buffer high address valid
+	input SG_TX_BUF_ADDR_LO_VALID,					// Scatter gather TX buffer low address valid
+
+	input TXN_RX_LEN_VALID,							// Read transaction length valid
+	input TXN_RX_OFF_LAST_VALID,					// Read transaction offset/last valid
+	output [31:0] TXN_RX_DONE_LEN,					// Read transaction actual transfer length
+	output TXN_RX_DONE,								// Read transaction done
+	input TXN_RX_DONE_ACK,							// Read transaction actual transfer length read
+
+	output TXN_TX,									// Write transaction notification
+	input TXN_TX_ACK,								// Write transaction acknowledged
+	output [31:0] TXN_TX_LEN,						// Write transaction length
+	output [31:0] TXN_TX_OFF_LAST,					// Write transaction offset/last
+	output [31:0] TXN_TX_DONE_LEN,					// Write transaction actual transfer length
+	output TXN_TX_DONE,								// Write transaction done
+	input TXN_TX_DONE_ACK,							// Write transaction actual transfer length read
+
+	output RX_REQ,									// Read request
+	input RX_REQ_ACK,								// Read request accepted
+	output [1:0] RX_REQ_TAG,						// Read request data tag 
+	output [63:0] RX_REQ_ADDR,						// Read request address
+	output [9:0] RX_REQ_LEN,						// Read request length
+
+	output TX_REQ,									// Outgoing write request
+	input TX_REQ_ACK,								// Outgoing write request acknowledged
+	output [63:0] TX_ADDR,							// Outgoing write high address
+	output [9:0] TX_LEN,							// Outgoing write length (in 32 bit words)
+	output [C_DATA_WIDTH-1:0] TX_DATA,				// Outgoing write data
+	input TX_DATA_REN,								// Outgoing write data read enable
+	input TX_SENT,									// Outgoing write complete
+
+	input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN,		// Main incoming data enable
+	input MAIN_DONE,								// Main incoming data complete
+	input MAIN_ERR,									// Main incoming data completed with error
+
+	input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN,	// Scatter gather for RX incoming data enable
+	input SG_RX_DONE,								// Scatter gather for RX incoming data complete
+	input SG_RX_ERR,								// Scatter gather for RX incoming data completed with error
+
+	input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN,	// Scatter gather for TX incoming data enable
+	input SG_TX_DONE,								// Scatter gather for TX incoming data complete
+	input SG_TX_ERR,								// Scatter gather for TX incoming data completed with error
+
+	input CHNL_RX_CLK,									// Channel read clock
+	output CHNL_RX,									// Channel read receive signal
+	input CHNL_RX_ACK,								// Channle read received signal
+	output CHNL_RX_LAST,							// Channel last read
+	output [31:0] CHNL_RX_LEN,						// Channel read length
+	output [30:0] CHNL_RX_OFF,						// Channel read offset
+	output [C_DATA_WIDTH-1:0] CHNL_RX_DATA,			// Channel read data
+	output CHNL_RX_DATA_VALID,						// Channel read data valid
+	input CHNL_RX_DATA_REN, 						// Channel read data has been recieved
+
+	input CHNL_TX_CLK,								// Channel write clock
+	input CHNL_TX,									// Channel write receive signal
+	output CHNL_TX_ACK,								// Channel write acknowledgement signal
+	input CHNL_TX_LAST,								// Channel last write
+	input [31:0] CHNL_TX_LEN,						// Channel write length (in 32 bit words)
+	input [30:0] CHNL_TX_OFF,						// Channel write offset
+	input [C_DATA_WIDTH-1:0] CHNL_TX_DATA,			// Channel write data
+	input CHNL_TX_DATA_VALID,						// Channel write data valid
+	output CHNL_TX_DATA_REN							// Channel write data has been recieved
+);
+
+`include "functions.vh"
+
+
+wire	[C_DATA_WIDTH-1:0]	wTxSgData;
+wire						wTxSgDataEmpty;
+wire						wTxSgDataRen;
+wire						wTxSgDataErr;
+wire						wTxSgDataRst;
+
+
+// Receiving port (data to the channel)
+rx_port_64 #(
+	.C_DATA_WIDTH(C_DATA_WIDTH), 
+	.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH), 
+	.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
+	.C_MAX_READ_REQ(C_MAX_READ_REQ)
+) rxPort (
+	.RST(RST), 
+	.CLK(CLK), 
+	.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE), 
+	
+	.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
+	.SG_RX_BUF_DATA(PIO_DATA),
+	.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
+	.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
+	.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
+	
+	.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
+	.SG_TX_BUF_DATA(PIO_DATA),
+	.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
+	.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
+	.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
+	
+	.SG_DATA(wTxSgData),
+	.SG_DATA_EMPTY(wTxSgDataEmpty),
+	.SG_DATA_REN(wTxSgDataRen),
+	.SG_RST(wTxSgDataRst),
+	.SG_ERR(wTxSgDataErr),
+	
+	.TXN_DATA(PIO_DATA), 
+	.TXN_LEN_VALID(TXN_RX_LEN_VALID), 
+	.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID), 
+	.TXN_DONE_LEN(TXN_RX_DONE_LEN),
+	.TXN_DONE(TXN_RX_DONE),
+	.TXN_DONE_ACK(TXN_RX_DONE_ACK),
+	
+	.RX_REQ(RX_REQ),
+	.RX_REQ_ACK(RX_REQ_ACK),
+	.RX_REQ_TAG(RX_REQ_TAG),
+	.RX_REQ_ADDR(RX_REQ_ADDR),
+	.RX_REQ_LEN(RX_REQ_LEN),
+
+	.MAIN_DATA(ENG_DATA),
+	.MAIN_DATA_EN(MAIN_DATA_EN), 
+	.MAIN_DONE(MAIN_DONE), 
+	.MAIN_ERR(MAIN_ERR),
+	
+	.SG_RX_DATA(ENG_DATA),
+	.SG_RX_DATA_EN(SG_RX_DATA_EN), 
+	.SG_RX_DONE(SG_RX_DONE), 
+	.SG_RX_ERR(SG_RX_ERR),
+
+	.SG_TX_DATA(ENG_DATA),
+	.SG_TX_DATA_EN(SG_TX_DATA_EN), 
+	.SG_TX_DONE(SG_TX_DONE), 
+	.SG_TX_ERR(SG_TX_ERR),
+
+	.CHNL_CLK(CHNL_RX_CLK), 
+	.CHNL_RX(CHNL_RX), 
+	.CHNL_RX_ACK(CHNL_RX_ACK), 
+	.CHNL_RX_LAST(CHNL_RX_LAST), 
+	.CHNL_RX_LEN(CHNL_RX_LEN), 
+	.CHNL_RX_OFF(CHNL_RX_OFF), 
+	.CHNL_RX_DATA(CHNL_RX_DATA), 
+	.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID), 
+	.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
+);
+
+
+// Sending port (data from the channel)
+tx_port_64 #(
+	.C_DATA_WIDTH(C_DATA_WIDTH), 
+	.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
+) txPort (
+	.CLK(CLK), 
+	.RST(RST), 
+	.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE), 
+	
+	.TXN(TXN_TX),
+	.TXN_ACK(TXN_TX_ACK),
+	.TXN_LEN(TXN_TX_LEN),
+	.TXN_OFF_LAST(TXN_TX_OFF_LAST),
+	.TXN_DONE_LEN(TXN_TX_DONE_LEN),
+	.TXN_DONE(TXN_TX_DONE),
+	.TXN_DONE_ACK(TXN_TX_DONE_ACK),
+	
+	.SG_DATA(wTxSgData),
+	.SG_DATA_EMPTY(wTxSgDataEmpty),
+	.SG_DATA_REN(wTxSgDataRen),
+	.SG_RST(wTxSgDataRst),
+	.SG_ERR(wTxSgDataErr),
+	
+	.TX_REQ(TX_REQ), 
+	.TX_REQ_ACK(TX_REQ_ACK),
+	.TX_ADDR(TX_ADDR), 
+	.TX_LEN(TX_LEN), 
+	.TX_DATA(TX_DATA),
+	.TX_DATA_REN(TX_DATA_REN), 
+	.TX_SENT(TX_SENT),
+
+	.CHNL_CLK(CHNL_TX_CLK), 
+	.CHNL_TX(CHNL_TX), 
+	.CHNL_TX_ACK(CHNL_TX_ACK),
+	.CHNL_TX_LAST(CHNL_TX_LAST), 
+	.CHNL_TX_LEN(CHNL_TX_LEN), 
+	.CHNL_TX_OFF(CHNL_TX_OFF), 
+	.CHNL_TX_DATA(CHNL_TX_DATA), 
+	.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID), 
+	.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
+);
+
+endmodule
diff --git a/fpga/riffa_hdl/chnl_tester.v b/fpga/riffa_hdl/chnl_tester.v
new file mode 100644
index 0000000..aaf8759
--- /dev/null
+++ b/fpga/riffa_hdl/chnl_tester.v
@@ -0,0 +1,159 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			chnl_tester.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Sample RIFFA channel user module. Designed to exercise
+// 						the RIFFA TX and RX interfaces. Receives data on the
+//						RX interface and saves the last value received. Sends
+//						the same amount of data back on the TX interface. The
+//						returned data starts with the last value received, 
+//						resets and increments to end with a value equal to the
+//						number of (4 byte) words sent back on the TX interface.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+module chnl_tester #(
+	parameter C_PCI_DATA_WIDTH = 9'd32
+)
+(
+	input CLK,
+	input RST,
+	output CHNL_RX_CLK, 
+	input CHNL_RX, 
+	output CHNL_RX_ACK, 
+	input CHNL_RX_LAST, 
+	input [31:0] CHNL_RX_LEN, 
+	input [30:0] CHNL_RX_OFF, 
+	input [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA, 
+	input CHNL_RX_DATA_VALID, 
+	output CHNL_RX_DATA_REN,
+	
+	output CHNL_TX_CLK, 
+	output CHNL_TX, 
+	input CHNL_TX_ACK, 
+	output CHNL_TX_LAST, 
+	output [31:0] CHNL_TX_LEN, 
+	output [30:0] CHNL_TX_OFF, 
+	output [C_PCI_DATA_WIDTH-1:0] CHNL_TX_DATA, 
+	output CHNL_TX_DATA_VALID, 
+	input CHNL_TX_DATA_REN
+);
+
+reg [C_PCI_DATA_WIDTH-1:0] rData={C_PCI_DATA_WIDTH{1'b0}};
+reg [31:0] rLen=0;
+reg [31:0] rCount=0;
+reg [1:0] rState=0;
+
+assign CHNL_RX_CLK = CLK;
+assign CHNL_RX_ACK = (rState == 2'd1);
+assign CHNL_RX_DATA_REN = (rState == 2'd1);
+
+assign CHNL_TX_CLK = CLK;
+assign CHNL_TX = (rState == 2'd3);
+assign CHNL_TX_LAST = 1'd1;
+assign CHNL_TX_LEN = rLen; // in words
+assign CHNL_TX_OFF = 0;
+assign CHNL_TX_DATA = rData;
+assign CHNL_TX_DATA_VALID = (rState == 2'd3);
+
+always @(posedge CLK or posedge RST) begin
+	if (RST) begin
+		rLen <= #1 0;
+		rCount <= #1 0;
+		rState <= #1 0;
+		rData <= #1 0;
+	end
+	else begin
+		case (rState)
+		
+		2'd0: begin // Wait for start of RX, save length
+			if (CHNL_RX) begin
+				rLen <= #1 CHNL_RX_LEN;
+				rCount <= #1 0;
+				rState <= #1 2'd1;
+			end
+		end
+		
+		2'd1: begin // Wait for last data in RX, save value
+			if (CHNL_RX_DATA_VALID) begin
+				rData <= #1 CHNL_RX_DATA;
+				rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);
+			end
+			if (rCount >= rLen)
+				rState <= #1 2'd2;
+		end
+
+		2'd2: begin // Prepare for TX
+			rCount <= #1 (C_PCI_DATA_WIDTH/32);
+			rState <= #1 2'd3;
+		end
+
+		2'd3: begin // Start TX with save length and data value
+			if (CHNL_TX_DATA_REN & CHNL_TX_DATA_VALID) begin
+				rData <= #1 {rCount + 4, rCount + 3, rCount + 2, rCount + 1};
+				rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);
+				if (rCount >= rLen)
+					rState <= #1 2'd0;
+			end
+		end
+		
+		endcase
+	end
+end
+
+/*
+wire [35:0] wControl0;
+chipscope_icon_1 cs_icon(
+	.CONTROL0(wControl0)
+);
+
+chipscope_ila_t8_512 a0(
+	.CLK(CLK), 
+	.CONTROL(wControl0), 
+	.TRIG0({3'd0, (rCount >= 800), CHNL_RX, CHNL_RX_DATA_VALID, rState}),
+	.DATA({442'd0,
+			CHNL_TX_DATA_REN, // 1
+			CHNL_TX_ACK, // 1
+			CHNL_RX_DATA, // 64
+			CHNL_RX_DATA_VALID, // 1
+			CHNL_RX, // 1
+			rState}) // 2
+);
+*/
+
+endmodule
diff --git a/fpga/riffa_hdl/counter.v b/fpga/riffa_hdl/counter.v
new file mode 100644
index 0000000..bdb8c35
--- /dev/null
+++ b/fpga/riffa_hdl/counter.v
@@ -0,0 +1,72 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			counter.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description: A simple up-counter. The maximum value is the largest expected
+// value. The counter will not pass the SAT_VALUE. If the SAT_VALUE > MAX_VALUE,
+// the counter will roll over and never stop. On RST_IN, the counter
+// synchronously resets to the RST_VALUE
+// Author:				Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "functions.vh"
+module counter
+    #(parameter C_MAX_VALUE = 10,
+      parameter C_SAT_VALUE = 10,
+      parameter C_RST_VALUE = 0)
+    (
+     input                              CLK,
+     input                              RST_IN,
+
+     input                              ENABLE,
+     output [clog2s(C_MAX_VALUE+1)-1:0] VALUE
+     );
+    wire                                wEnable;
+    reg [clog2s(C_MAX_VALUE+1)-1:0]     wCtrValue;
+    reg [clog2s(C_MAX_VALUE+1)-1:0]     rCtrValue;
+    /* verilator lint_off WIDTH */
+    assign wEnable = ENABLE & (C_SAT_VALUE > rCtrValue);
+    /* verilator lint_on WIDTH */
+    assign VALUE = rCtrValue;
+    always @(posedge CLK) begin
+        if(RST_IN) begin
+            rCtrValue <= C_RST_VALUE;
+        end else if(wEnable) begin
+            rCtrValue <= rCtrValue + 1;
+        end
+    end
+endmodule
diff --git a/fpga/riffa_hdl/cross_domain_signal.v b/fpga/riffa_hdl/cross_domain_signal.v
new file mode 100644
index 0000000..4a90e28
--- /dev/null
+++ b/fpga/riffa_hdl/cross_domain_signal.v
@@ -0,0 +1,62 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			cross_domain_signal.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Send a signal from clock domain A into clock domain B
+// and get the signal back into clock domain A. Domain A can know roughly when 
+// the signal is received domain B. 
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+
+`timescale 1ns/1ns
+module cross_domain_signal (
+	input CLK_A,		// Clock for domain A
+	input CLK_A_SEND,	// Signal from domain A to domain B
+	output CLK_A_RECV,	// Signal from domain B received in domain A 
+	input CLK_B,		// Clock for domain B
+	output CLK_B_RECV,	// Signal from domain A received in domain B
+	input CLK_B_SEND	// Signal from domain B to domain A
+);
+
+
+// Sync level signals across domains.
+syncff sigAtoB (.CLK(CLK_B), .IN_ASYNC(CLK_A_SEND), .OUT_SYNC(CLK_B_RECV));
+syncff sigBtoA (.CLK(CLK_A), .IN_ASYNC(CLK_B_SEND), .OUT_SYNC(CLK_A_RECV));
+
+
+endmodule
diff --git a/fpga/riffa_hdl/demux.v b/fpga/riffa_hdl/demux.v
new file mode 100644
index 0000000..64c5f7c
--- /dev/null
+++ b/fpga/riffa_hdl/demux.v
@@ -0,0 +1,61 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			demux.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			A simple demultiplexer
+// Author:				Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "functions.vh"
+module demux
+    #(
+      parameter C_OUTPUTS = 12,
+      parameter C_WIDTH = 1
+      )
+    (
+     input [C_WIDTH-1:0]            WR_DATA,// Inputs
+     input [clog2s(C_OUTPUTS)-1:0]  WR_SEL,// Selector
+     output [C_OUTPUTS*C_WIDTH-1:0] RD_DATA// Outputs
+     );
+    genvar                          i;
+    reg [C_OUTPUTS*C_WIDTH-1:0]     _rOut;
+    assign RD_DATA = _rOut;
+    always @(*) begin
+        _rOut = 0;
+        _rOut[C_WIDTH*WR_SEL +: C_WIDTH] = WR_DATA;
+    end
+endmodule
diff --git a/fpga/riffa_hdl/engine_layer.v b/fpga/riffa_hdl/engine_layer.v
new file mode 100644
index 0000000..5bab9c6
--- /dev/null
+++ b/fpga/riffa_hdl/engine_layer.v
@@ -0,0 +1,475 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            engine_layer.v
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The engine layer encapsulates the RX and TX engines.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "trellis.vh"
+`include "ultrascale.vh"
+module engine_layer
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_LOG_NUM_TAGS=6,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 0,
+      parameter C_MAX_PAYLOAD_DWORDS = 64,
+      parameter C_VENDOR="ULTRASCALE"
+      )
+    (
+     // Interface: Clocks
+     input                                    CLK,
+
+     // Interface: Resets
+     input                                    RST_IN,
+
+     // Interface: Configuration 
+     input [`SIG_CPLID_W-1:0]                 CONFIG_COMPLETER_ID,
+    
+     // Interface: RX Classic
+     input [C_PCI_DATA_WIDTH-1:0]             RX_TLP,
+     input                                    RX_TLP_VALID,
+     input                                    RX_TLP_START_FLAG,
+     input [`SIG_OFFSET_W-1:0]                RX_TLP_START_OFFSET,
+     input                                    RX_TLP_END_FLAG,
+     input [`SIG_OFFSET_W-1:0]                RX_TLP_END_OFFSET,
+     input [`SIG_BARDECODE_W-1:0]             RX_TLP_BAR_DECODE,
+     output                                   RX_TLP_READY,
+
+     // Interface: TX Classic
+     input                                    TX_TLP_READY,
+     output [C_PCI_DATA_WIDTH-1:0]            TX_TLP,
+     output                                   TX_TLP_VALID,
+     output                                   TX_TLP_START_FLAG,
+     output [`SIG_OFFSET_W-1:0]               TX_TLP_START_OFFSET,
+     output                                   TX_TLP_END_FLAG,
+     output [`SIG_OFFSET_W-1:0]               TX_TLP_END_OFFSET,
+
+     //Interface: CQ Ultrascale (RXR)
+     input                                    M_AXIS_CQ_TVALID,
+     input                                    M_AXIS_CQ_TLAST,
+     input [C_PCI_DATA_WIDTH-1:0]             M_AXIS_CQ_TDATA,
+     input [(C_PCI_DATA_WIDTH/32)-1:0]        M_AXIS_CQ_TKEEP,
+     input [`SIG_CQ_TUSER_W-1:0]              M_AXIS_CQ_TUSER,
+     output                                   M_AXIS_CQ_TREADY,
+
+     //Interface: RC Ultrascale (RXC)
+     input                                    M_AXIS_RC_TVALID,
+     input                                    M_AXIS_RC_TLAST,
+     input [C_PCI_DATA_WIDTH-1:0]             M_AXIS_RC_TDATA,
+     input [(C_PCI_DATA_WIDTH/32)-1:0]        M_AXIS_RC_TKEEP,
+     input [`SIG_RC_TUSER_W-1:0]              M_AXIS_RC_TUSER,
+     output                                   M_AXIS_RC_TREADY,
+
+     //Interface: CC Ultrascale (TXC)
+     input                                    S_AXIS_CC_TREADY,
+     output                                   S_AXIS_CC_TVALID,
+     output                                   S_AXIS_CC_TLAST,
+     output [C_PCI_DATA_WIDTH-1:0]            S_AXIS_CC_TDATA,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]       S_AXIS_CC_TKEEP,
+     output [`SIG_CC_TUSER_W-1:0]             S_AXIS_CC_TUSER,
+    
+     //Interface: RQ Ultrascale (TXR) 
+     input                                    S_AXIS_RQ_TREADY,
+     output                                   S_AXIS_RQ_TVALID,
+     output                                   S_AXIS_RQ_TLAST,
+     output [C_PCI_DATA_WIDTH-1:0]            S_AXIS_RQ_TDATA,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]       S_AXIS_RQ_TKEEP,
+     output [`SIG_RQ_TUSER_W-1:0]             S_AXIS_RQ_TUSER,
+
+     // Interface: RXC Engine
+     output [C_PCI_DATA_WIDTH-1:0]            RXC_DATA,
+     output                                   RXC_DATA_VALID,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]       RXC_DATA_WORD_ENABLE,
+     output                                   RXC_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
+     output                                   RXC_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
+
+     output [`SIG_LBE_W-1:0]                  RXC_META_LDWBE,
+     output [`SIG_FBE_W-1:0]                  RXC_META_FDWBE,
+     output [`SIG_TAG_W-1:0]                  RXC_META_TAG,
+     output [`SIG_LOWADDR_W-1:0]              RXC_META_ADDR,
+     output [`SIG_TYPE_W-1:0]                 RXC_META_TYPE,
+     output [`SIG_LEN_W-1:0]                  RXC_META_LENGTH,
+     output [`SIG_BYTECNT_W-1:0]                 RXC_META_BYTES_REMAINING,
+     output [`SIG_CPLID_W-1:0]                RXC_META_COMPLETER_ID,
+     output                                   RXC_META_EP,
+
+     // Interface: RXR Engine
+     output [C_PCI_DATA_WIDTH-1:0]            RXR_DATA,
+     output                                   RXR_DATA_VALID,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]       RXR_DATA_WORD_ENABLE,
+     output                                   RXR_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
+     output                                   RXR_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
+     
+     output [`SIG_FBE_W-1:0]                  RXR_META_FDWBE,
+     output [`SIG_LBE_W-1:0]                  RXR_META_LDWBE,
+     output [`SIG_TC_W-1:0]                   RXR_META_TC,
+     output [`SIG_ATTR_W-1:0]                 RXR_META_ATTR,
+     output [`SIG_TAG_W-1:0]                  RXR_META_TAG,
+     output [`SIG_TYPE_W-1:0]                 RXR_META_TYPE,
+     output [`SIG_ADDR_W-1:0]                 RXR_META_ADDR,
+     output [`SIG_BARDECODE_W-1:0]            RXR_META_BAR_DECODED,
+     output [`SIG_REQID_W-1:0]                RXR_META_REQUESTER_ID,
+     output [`SIG_LEN_W-1:0]                  RXR_META_LENGTH,
+     output                                   RXR_META_EP,
+    
+     // Interface: TXC Engine
+     input                                    TXC_DATA_VALID,
+     input [C_PCI_DATA_WIDTH-1:0]             TXC_DATA,
+     input                                    TXC_DATA_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXC_DATA_START_OFFSET,
+     input                                    TXC_DATA_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXC_DATA_END_OFFSET,
+     output                                   TXC_DATA_READY,
+
+     input                                    TXC_META_VALID,
+     input [`SIG_FBE_W-1:0]                   TXC_META_FDWBE,
+     input [`SIG_LBE_W-1:0]                   TXC_META_LDWBE,
+     input [`SIG_LOWADDR_W-1:0]               TXC_META_ADDR,
+     input [`SIG_TYPE_W-1:0]                  TXC_META_TYPE,
+     input [`SIG_LEN_W-1:0]                   TXC_META_LENGTH,
+     input [`SIG_BYTECNT_W-1:0]                  TXC_META_BYTE_COUNT,
+     input [`SIG_TAG_W-1:0]                   TXC_META_TAG,
+     input [`SIG_REQID_W-1:0]                 TXC_META_REQUESTER_ID,
+     input [`SIG_TC_W-1:0]                    TXC_META_TC,
+     input [`SIG_ATTR_W-1:0]                  TXC_META_ATTR,
+     input                                    TXC_META_EP,
+     output                                   TXC_META_READY,
+     output                                   TXC_SENT,
+
+     // Interface: TXR Engine
+     input                                    TXR_DATA_VALID,
+     input [C_PCI_DATA_WIDTH-1:0]             TXR_DATA,
+     input                                    TXR_DATA_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_START_OFFSET,
+     input                                    TXR_DATA_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_END_OFFSET,
+     output                                   TXR_DATA_READY,
+
+     input                                    TXR_META_VALID,
+     input [`SIG_FBE_W-1:0]                   TXR_META_FDWBE, 
+     input [`SIG_LBE_W-1:0]                   TXR_META_LDWBE,
+     input [`SIG_ADDR_W-1:0]                  TXR_META_ADDR,
+     input [`SIG_LEN_W-1:0]                   TXR_META_LENGTH,
+     input [`SIG_TAG_W-1:0]                   TXR_META_TAG,
+     input [`SIG_TC_W-1:0]                    TXR_META_TC,
+     input [`SIG_ATTR_W-1:0]                  TXR_META_ATTR,
+     input [`SIG_TYPE_W-1:0]                  TXR_META_TYPE,
+     input                                    TXR_META_EP,
+     output                                   TXR_META_READY,
+     output                                   TXR_SENT
+     );
+
+    generate
+        /* verilator lint_off WIDTH */
+        if(C_VENDOR != "ULTRASCALE") begin
+            assign M_AXIS_CQ_TREADY = 0;
+            assign M_AXIS_RC_TREADY = 0;
+            assign S_AXIS_CC_TVALID = 0;
+            assign S_AXIS_CC_TLAST = 0;
+            assign S_AXIS_CC_TDATA = 0;
+            assign S_AXIS_CC_TKEEP = 0;
+            assign S_AXIS_CC_TUSER = 0;
+            
+            assign S_AXIS_RQ_TVALID = 0;
+            assign S_AXIS_RQ_TLAST = 0;
+            assign S_AXIS_RQ_TDATA = 0;
+            assign S_AXIS_RQ_TKEEP = 0;
+            assign S_AXIS_RQ_TUSER = 0;
+
+        /* verilator lint_on WIDTH */
+	        rx_engine_classic
+	            #(/*AUTOINSTPARAM*/
+                  // Parameters
+                  .C_VENDOR             (C_VENDOR),
+                  .C_PCI_DATA_WIDTH     (C_PCI_DATA_WIDTH),
+                  .C_LOG_NUM_TAGS       (C_LOG_NUM_TAGS))
+	        rx_engine_classic_inst
+	            (/*AUTOINST*/
+                 // Outputs
+                 .RX_TLP_READY          (RX_TLP_READY),
+                 .RXC_DATA              (RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
+                 .RXC_DATA_VALID        (RXC_DATA_VALID),
+                 .RXC_DATA_WORD_ENABLE  (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXC_DATA_START_FLAG   (RXC_DATA_START_FLAG),
+                 .RXC_DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXC_DATA_END_FLAG     (RXC_DATA_END_FLAG),
+                 .RXC_DATA_END_OFFSET   (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXC_META_LDWBE        (RXC_META_LDWBE[`SIG_LBE_W-1:0]),
+                 .RXC_META_FDWBE        (RXC_META_FDWBE[`SIG_FBE_W-1:0]),
+                 .RXC_META_TAG          (RXC_META_TAG[`SIG_TAG_W-1:0]),
+                 .RXC_META_ADDR         (RXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
+                 .RXC_META_TYPE         (RXC_META_TYPE[`SIG_TYPE_W-1:0]),
+                 .RXC_META_LENGTH       (RXC_META_LENGTH[`SIG_LEN_W-1:0]),
+                 .RXC_META_BYTES_REMAINING(RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:0]),
+                 .RXC_META_COMPLETER_ID (RXC_META_COMPLETER_ID[`SIG_CPLID_W-1:0]),
+                 .RXC_META_EP           (RXC_META_EP),
+                 .RXR_DATA              (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
+                 .RXR_DATA_VALID        (RXR_DATA_VALID),
+                 .RXR_DATA_WORD_ENABLE  (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXR_DATA_START_FLAG   (RXR_DATA_START_FLAG),
+                 .RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXR_DATA_END_FLAG     (RXR_DATA_END_FLAG),
+                 .RXR_DATA_END_OFFSET   (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXR_META_FDWBE        (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
+                 .RXR_META_LDWBE        (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
+                 .RXR_META_TC           (RXR_META_TC[`SIG_TC_W-1:0]),
+                 .RXR_META_ATTR         (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
+                 .RXR_META_TAG          (RXR_META_TAG[`SIG_TAG_W-1:0]),
+                 .RXR_META_TYPE         (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
+                 .RXR_META_ADDR         (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
+                 .RXR_META_BAR_DECODED  (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
+                 .RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
+                 .RXR_META_LENGTH       (RXR_META_LENGTH[`SIG_LEN_W-1:0]),
+                 .RXR_META_EP           (RXR_META_EP),
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST_IN                (RST_IN),
+                 .RX_TLP                (RX_TLP[C_PCI_DATA_WIDTH-1:0]),
+                 .RX_TLP_VALID          (RX_TLP_VALID),
+                 .RX_TLP_START_FLAG     (RX_TLP_START_FLAG),
+                 .RX_TLP_START_OFFSET   (RX_TLP_START_OFFSET[`SIG_OFFSET_W-1:0]),
+                 .RX_TLP_END_FLAG       (RX_TLP_END_FLAG),
+                 .RX_TLP_END_OFFSET     (RX_TLP_END_OFFSET[`SIG_OFFSET_W-1:0]),
+                 .RX_TLP_BAR_DECODE     (RX_TLP_BAR_DECODE[`SIG_BARDECODE_W-1:0]));
+
+	        tx_engine_classic
+	            #(/*AUTOINSTPARAM*/
+                  // Parameters
+                  .C_PCI_DATA_WIDTH     (C_PCI_DATA_WIDTH),
+                  .C_PIPELINE_INPUT     (C_PIPELINE_INPUT),
+                  .C_PIPELINE_OUTPUT    (C_PIPELINE_OUTPUT),
+                  .C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
+                  .C_VENDOR             (C_VENDOR))
+	        tx_engine_classic_inst
+	            (/*AUTOINST*/
+                 // Outputs
+                 .TX_TLP                (TX_TLP[C_PCI_DATA_WIDTH-1:0]),
+                 .TX_TLP_VALID          (TX_TLP_VALID),
+                 .TX_TLP_START_FLAG     (TX_TLP_START_FLAG),
+                 .TX_TLP_START_OFFSET   (TX_TLP_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TX_TLP_END_FLAG       (TX_TLP_END_FLAG),
+                 .TX_TLP_END_OFFSET     (TX_TLP_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TXC_DATA_READY        (TXC_DATA_READY),
+                 .TXC_META_READY        (TXC_META_READY),
+                 .TXC_SENT              (TXC_SENT),
+                 .TXR_DATA_READY        (TXR_DATA_READY),
+                 .TXR_META_READY        (TXR_META_READY),
+                 .TXR_SENT              (TXR_SENT),
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST_IN                (RST_IN),
+                 .CONFIG_COMPLETER_ID   (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
+                 .TX_TLP_READY          (TX_TLP_READY),
+                 .TXC_DATA_VALID        (TXC_DATA_VALID),
+                 .TXC_DATA              (TXC_DATA[C_PCI_DATA_WIDTH-1:0]),
+                 .TXC_DATA_START_FLAG   (TXC_DATA_START_FLAG),
+                 .TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TXC_DATA_END_FLAG     (TXC_DATA_END_FLAG),
+                 .TXC_DATA_END_OFFSET   (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TXC_META_VALID        (TXC_META_VALID),
+                 .TXC_META_FDWBE        (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
+                 .TXC_META_LDWBE        (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
+                 .TXC_META_ADDR         (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
+                 .TXC_META_TYPE         (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
+                 .TXC_META_LENGTH       (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
+                 .TXC_META_BYTE_COUNT   (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
+                 .TXC_META_TAG          (TXC_META_TAG[`SIG_TAG_W-1:0]),
+                 .TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
+                 .TXC_META_TC           (TXC_META_TC[`SIG_TC_W-1:0]),
+                 .TXC_META_ATTR         (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
+                 .TXC_META_EP           (TXC_META_EP),
+                 .TXR_DATA_VALID        (TXR_DATA_VALID),
+                 .TXR_DATA              (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
+                 .TXR_DATA_START_FLAG   (TXR_DATA_START_FLAG),
+                 .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TXR_DATA_END_FLAG     (TXR_DATA_END_FLAG),
+                 .TXR_DATA_END_OFFSET   (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TXR_META_VALID        (TXR_META_VALID),
+                 .TXR_META_FDWBE        (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
+                 .TXR_META_LDWBE        (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
+                 .TXR_META_ADDR         (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
+                 .TXR_META_LENGTH       (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
+                 .TXR_META_TAG          (TXR_META_TAG[`SIG_TAG_W-1:0]),
+                 .TXR_META_TC           (TXR_META_TC[`SIG_TC_W-1:0]),
+                 .TXR_META_ATTR         (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
+                 .TXR_META_TYPE         (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
+                 .TXR_META_EP           (TXR_META_EP));
+
+        end else begin 
+
+            assign TX_TLP = 0;
+            assign TX_TLP_VALID = 0;
+            assign TX_TLP_START_FLAG = 0;
+            assign TX_TLP_START_OFFSET = 0;
+            assign TX_TLP_END_FLAG = 0;
+            assign TX_TLP_END_OFFSET = 0;
+            assign RX_TLP_READY = 0;
+	        rx_engine_ultrascale
+	            #(/*AUTOINSTPARAM*/
+                  // Parameters
+                  .C_PCI_DATA_WIDTH     (C_PCI_DATA_WIDTH))
+	        rx_engine_ultrascale_inst
+	            (/*AUTOINST*/
+                 // Outputs
+                 .M_AXIS_CQ_TREADY      (M_AXIS_CQ_TREADY),
+                 .M_AXIS_RC_TREADY      (M_AXIS_RC_TREADY),
+                 .RXC_DATA              (RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
+                 .RXC_DATA_VALID        (RXC_DATA_VALID),
+                 .RXC_DATA_WORD_ENABLE  (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXC_DATA_START_FLAG   (RXC_DATA_START_FLAG),
+                 .RXC_DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXC_DATA_END_FLAG     (RXC_DATA_END_FLAG),
+                 .RXC_DATA_END_OFFSET   (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXC_META_LDWBE        (RXC_META_LDWBE[`SIG_LBE_W-1:0]),
+                 .RXC_META_FDWBE        (RXC_META_FDWBE[`SIG_FBE_W-1:0]),
+                 .RXC_META_TAG          (RXC_META_TAG[`SIG_TAG_W-1:0]),
+                 .RXC_META_ADDR         (RXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
+                 .RXC_META_TYPE         (RXC_META_TYPE[`SIG_TYPE_W-1:0]),
+                 .RXC_META_LENGTH       (RXC_META_LENGTH[`SIG_LEN_W-1:0]),
+                 .RXC_META_BYTES_REMAINING(RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:0]),
+                 .RXC_META_COMPLETER_ID (RXC_META_COMPLETER_ID[`SIG_CPLID_W-1:0]),
+                 .RXC_META_EP           (RXC_META_EP),
+                 .RXR_DATA              (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
+                 .RXR_DATA_VALID        (RXR_DATA_VALID),
+                 .RXR_DATA_WORD_ENABLE  (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXR_DATA_START_FLAG   (RXR_DATA_START_FLAG),
+                 .RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXR_DATA_END_FLAG     (RXR_DATA_END_FLAG),
+                 .RXR_DATA_END_OFFSET   (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXR_META_FDWBE        (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
+                 .RXR_META_LDWBE        (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
+                 .RXR_META_TC           (RXR_META_TC[`SIG_TC_W-1:0]),
+                 .RXR_META_ATTR         (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
+                 .RXR_META_TAG          (RXR_META_TAG[`SIG_TAG_W-1:0]),
+                 .RXR_META_TYPE         (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
+                 .RXR_META_ADDR         (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
+                 .RXR_META_BAR_DECODED  (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
+                 .RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
+                 .RXR_META_LENGTH       (RXR_META_LENGTH[`SIG_LEN_W-1:0]),
+                 .RXR_META_EP           (RXR_META_EP),
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST_IN                (RST_IN),
+                 .M_AXIS_CQ_TVALID      (M_AXIS_CQ_TVALID),
+                 .M_AXIS_CQ_TLAST       (M_AXIS_CQ_TLAST),
+                 .M_AXIS_CQ_TDATA       (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
+                 .M_AXIS_CQ_TKEEP       (M_AXIS_CQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .M_AXIS_CQ_TUSER       (M_AXIS_CQ_TUSER[`SIG_CQ_TUSER_W-1:0]),
+                 .M_AXIS_RC_TVALID      (M_AXIS_RC_TVALID),
+                 .M_AXIS_RC_TLAST       (M_AXIS_RC_TLAST),
+                 .M_AXIS_RC_TDATA       (M_AXIS_RC_TDATA[C_PCI_DATA_WIDTH-1:0]),
+                 .M_AXIS_RC_TKEEP       (M_AXIS_RC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .M_AXIS_RC_TUSER       (M_AXIS_RC_TUSER[`SIG_RC_TUSER_W-1:0]));
+
+	        tx_engine_ultrascale
+	            #(/*AUTOINSTPARAM*/
+                  // Parameters
+                  .C_PCI_DATA_WIDTH     (C_PCI_DATA_WIDTH),
+                  .C_PIPELINE_INPUT     (C_PIPELINE_INPUT),
+                  .C_PIPELINE_OUTPUT    (C_PIPELINE_OUTPUT),
+                  .C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS))
+	        tx_engine_ultrascale_inst
+	            (/*AUTOINST*/
+                 // Outputs
+                 .S_AXIS_CC_TVALID      (S_AXIS_CC_TVALID),
+                 .S_AXIS_CC_TLAST       (S_AXIS_CC_TLAST),
+                 .S_AXIS_CC_TDATA       (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
+                 .S_AXIS_CC_TKEEP       (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .S_AXIS_CC_TUSER       (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
+                 .TXC_DATA_READY        (TXC_DATA_READY),
+                 .TXC_META_READY        (TXC_META_READY),
+                 .TXC_SENT              (TXC_SENT),
+                 .S_AXIS_RQ_TVALID      (S_AXIS_RQ_TVALID),
+                 .S_AXIS_RQ_TLAST       (S_AXIS_RQ_TLAST),
+                 .S_AXIS_RQ_TDATA       (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
+                 .S_AXIS_RQ_TKEEP       (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .S_AXIS_RQ_TUSER       (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),
+                 .TXR_DATA_READY        (TXR_DATA_READY),
+                 .TXR_META_READY        (TXR_META_READY),
+                 .TXR_SENT              (TXR_SENT),
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST_IN                (RST_IN),
+                 .CONFIG_COMPLETER_ID   (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
+                 .S_AXIS_CC_TREADY      (S_AXIS_CC_TREADY),
+                 .TXC_DATA_VALID        (TXC_DATA_VALID),
+                 .TXC_DATA              (TXC_DATA[C_PCI_DATA_WIDTH-1:0]),
+                 .TXC_DATA_START_FLAG   (TXC_DATA_START_FLAG),
+                 .TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TXC_DATA_END_FLAG     (TXC_DATA_END_FLAG),
+                 .TXC_DATA_END_OFFSET   (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TXC_META_VALID        (TXC_META_VALID),
+                 .TXC_META_FDWBE        (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
+                 .TXC_META_LDWBE        (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
+                 .TXC_META_ADDR         (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
+                 .TXC_META_TYPE         (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
+                 .TXC_META_LENGTH       (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
+                 .TXC_META_BYTE_COUNT   (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
+                 .TXC_META_TAG          (TXC_META_TAG[`SIG_TAG_W-1:0]),
+                 .TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
+                 .TXC_META_TC           (TXC_META_TC[`SIG_TC_W-1:0]),
+                 .TXC_META_ATTR         (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
+                 .TXC_META_EP           (TXC_META_EP),
+                 .S_AXIS_RQ_TREADY      (S_AXIS_RQ_TREADY),
+                 .TXR_DATA_VALID        (TXR_DATA_VALID),
+                 .TXR_DATA              (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
+                 .TXR_DATA_START_FLAG   (TXR_DATA_START_FLAG),
+                 .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TXR_DATA_END_FLAG     (TXR_DATA_END_FLAG),
+                 .TXR_DATA_END_OFFSET   (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TXR_META_VALID        (TXR_META_VALID),
+                 .TXR_META_FDWBE        (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
+                 .TXR_META_LDWBE        (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
+                 .TXR_META_ADDR         (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
+                 .TXR_META_LENGTH       (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
+                 .TXR_META_TAG          (TXR_META_TAG[`SIG_TAG_W-1:0]),
+                 .TXR_META_TC           (TXR_META_TC[`SIG_TC_W-1:0]),
+                 .TXR_META_ATTR         (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
+                 .TXR_META_TYPE         (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
+                 .TXR_META_EP           (TXR_META_EP));
+        end
+    endgenerate
+endmodule // engine_layer
+// Local Variables:
+// verilog-library-directories:("." "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/")
+// End:
diff --git a/fpga/riffa_hdl/ff.v b/fpga/riffa_hdl/ff.v
new file mode 100644
index 0000000..89904f9
--- /dev/null
+++ b/fpga/riffa_hdl/ff.v
@@ -0,0 +1,53 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			ff.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			A D/Q flip flop.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+module ff
+    (
+     input      CLK,
+     input      D,
+     output reg Q
+     );
+    always @ (posedge CLK) begin 
+	    Q <= #1 D; 
+    end
+endmodule
diff --git a/fpga/riffa_hdl/fifo.v b/fpga/riffa_hdl/fifo.v
new file mode 100644
index 0000000..d9d0ff0
--- /dev/null
+++ b/fpga/riffa_hdl/fifo.v
@@ -0,0 +1,219 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			fifo.v
+// Version:				1.00
+// Verilog Standard:	Verilog-2001
+// Description: Standard 0-delay fifo implementation. Takes WR_DATA on WR_READY
+// and WR_VALID. RD_DATA is read on RD_READY and RD_VALID
+// Author:				Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "functions.vh"
+module fifo 
+    #(
+      parameter C_WIDTH = 32,   // Data bus width
+      parameter C_DEPTH = 1024, // Depth of the FIFO
+      parameter C_DELAY = 2
+      )
+    (
+     input                CLK, // Clock
+     input                RST, // Sync reset, active high
+
+     input [C_WIDTH-1:0]  WR_DATA, // Write data input
+     input                WR_VALID, // Write enable, high active
+     output               WR_READY, // ~Full condition
+
+     output [C_WIDTH-1:0] RD_DATA, // Read data output
+     input                RD_READY, // Read enable, high active
+     output               RD_VALID // ~Empty condition
+     );
+
+    // Local parameters
+    localparam C_POW2_DEPTH = 2**clog2(C_DEPTH);
+    localparam C_DEPTH_WIDTH = clog2s(C_POW2_DEPTH);
+
+    wire [C_DELAY:0]      wDelayTaps;
+    wire                  wDelayWrEn;
+    wire                  wWrEn;
+    wire                  wRdEn;
+    wire                  wRdRdy;
+    
+    wire                  wRdEnInternal;
+    wire                  wRdEnExternal;
+    wire                  wEmptyNow;
+    wire                  wEmptyNext;
+
+    wire                  wOutputEmpty;
+    
+    wire                  wFullNow;
+    wire                  wFullNext;
+    
+    reg                   rValid;
+    reg [C_DEPTH_WIDTH:0] rWrPtr,_rWrPtr;
+    reg [C_DEPTH_WIDTH:0] rWrPtrPlus1, _rWrPtrPlus1;
+    reg [C_DEPTH_WIDTH:0] rRdPtr,_rRdPtr;
+    reg [C_DEPTH_WIDTH:0] rRdPtrPlus1,_rRdPtrPlus1;
+    reg                   rFull,_rFull;
+    reg                   rEmpty,_rEmpty;
+
+    assign wRdEnInternal = ~wEmptyNow & ~rValid; // Read enable to propogate data to the BRAM output
+    assign wRdEnExternal = RD_READY & !rEmpty;   // Read enable to change data on the output
+    assign wRdEn = wRdEnInternal | wRdEnExternal;
+    assign wRdRdy = RD_READY & rValid; // Read Data already on the output bus
+
+    assign wWrEn = WR_VALID & !rFull;
+
+    assign wEmptyNow = (rRdPtr == rWrPtr); 
+    assign wEmptyNext = (wRdEn & ~wWrEn & (rWrPtr == rRdPtrPlus1));
+
+    assign wFullNow = (rRdPtr[C_DEPTH_WIDTH-1:0] == rWrPtr[C_DEPTH_WIDTH-1:0]) & 
+                      (rWrPtr[C_DEPTH_WIDTH] != rRdPtr[C_DEPTH_WIDTH]);
+    assign wFullNext = wWrEn & ~wRdEn & (rWrPtrPlus1[C_DEPTH_WIDTH-1:0] == rRdPtr[C_DEPTH_WIDTH-1:0]) & 
+                       (rWrPtrPlus1[C_DEPTH_WIDTH] != rRdPtr[C_DEPTH_WIDTH]);
+
+    // Calculate empty
+    assign RD_VALID = rValid;
+
+    always @ (posedge CLK) begin
+        rEmpty <= #1 (RST ? 1'd1 : _rEmpty);
+    end
+
+    always @ (*) begin
+        _rEmpty = (wEmptyNow & ~wWrEn) | wEmptyNext;
+    end
+
+    always @(posedge CLK) begin
+        if(RST) begin
+            rValid <= #1 0;
+        end else if(wRdEn | wRdRdy) begin
+            rValid <= #1 ~(wEmptyNow);
+        end
+    end
+
+    // Write pointer logic.
+    always @ (posedge CLK) begin
+        if (RST) begin
+            rWrPtr <= #1 0;
+            rWrPtrPlus1 <= #1 1;
+        end else begin
+            rWrPtr <= #1 _rWrPtr;
+            rWrPtrPlus1 <= #1 _rWrPtrPlus1;
+        end
+    end
+
+    always @ (*) begin
+        if (wWrEn) begin
+            _rWrPtr = rWrPtrPlus1;
+            _rWrPtrPlus1 = rWrPtrPlus1 + 1'd1;
+        end else begin
+            _rWrPtr = rWrPtr;
+            _rWrPtrPlus1 = rWrPtrPlus1;
+        end
+    end
+
+    // Read pointer logic.
+    always @ (posedge CLK) begin
+        if (RST) begin
+            rRdPtr <= #1 0;
+            rRdPtrPlus1 <= #1 1;
+        end else begin
+            rRdPtr <= #1 _rRdPtr;
+            rRdPtrPlus1 <= #1 _rRdPtrPlus1;
+        end
+    end
+
+    always @ (*) begin
+        if (wRdEn) begin
+            _rRdPtr = rRdPtrPlus1;
+            _rRdPtrPlus1 = rRdPtrPlus1 + 1'd1;
+        end else begin
+            _rRdPtr = rRdPtr;
+            _rRdPtrPlus1 = rRdPtrPlus1;
+        end
+    end
+
+
+    // Calculate full
+    assign WR_READY = ~rFull;
+
+    always @ (posedge CLK) begin
+        rFull <= #1 (RST ? 1'd0 : _rFull);
+    end
+
+    always @ (*) begin
+        _rFull = wFullNow | wFullNext;
+    end
+
+    // Memory block (synthesis attributes applied to this module will
+    // determine the memory option).
+    scsdpram
+        #(
+          .C_WIDTH(C_WIDTH), 
+          .C_DEPTH(C_POW2_DEPTH)
+          /*AUTOINSTPARAM*/) 
+    mem 
+        (
+         .WR1_EN                        (wWrEn),
+         .WR1_ADDR                      (rWrPtr[C_DEPTH_WIDTH-1:0]),
+         .WR1_DATA                      (WR_DATA),
+
+         .RD1_EN                        (wRdEn),
+         .RD1_ADDR                      (rRdPtr[C_DEPTH_WIDTH-1:0]),
+         .RD1_DATA                      (RD_DATA),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK));
+
+    shiftreg
+        #(
+          // Parameters
+          .C_DEPTH          (C_DELAY),
+          .C_WIDTH          (1'b1)
+          /*AUTOINSTPARAM*/)
+    shiftreg_wr_delay_inst
+        (
+         // Outputs
+         .RD_DATA                       (wDelayTaps),
+         // Inputs
+         .RST_IN                        (RST),
+         .WR_DATA                       (wWrEn),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK));
+
+
+endmodule
+
diff --git a/fpga/riffa_hdl/fifo_packer_128.v b/fpga/riffa_hdl/fifo_packer_128.v
new file mode 100644
index 0000000..f5b0b68
--- /dev/null
+++ b/fpga/riffa_hdl/fifo_packer_128.v
@@ -0,0 +1,126 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			fifo_packer_128.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Packs 32, 64, or 96 bit received data into a 128 bit wide  
+// FIFO. Assumes the FIFO always has room to accommodate the data.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+// Additional Comments: 
+//-----------------------------------------------------------------------------
+
+`timescale 1ns/1ns
+module fifo_packer_128 (
+	input CLK,
+	input RST,
+	input [127:0] DATA_IN,		// Incoming data
+	input [2:0] DATA_IN_EN,		// Incoming data enable
+	input DATA_IN_DONE,			// Incoming data packet end
+	input DATA_IN_ERR,			// Incoming data error
+	input DATA_IN_FLUSH,		// End of incoming data
+	output [127:0] PACKED_DATA,	// Outgoing data
+	output PACKED_WEN,			// Outgoing data write enable
+	output PACKED_DATA_DONE,	// End of outgoing data packet
+	output PACKED_DATA_ERR,		// Error in outgoing data
+	output PACKED_DATA_FLUSHED	// End of outgoing data
+);
+
+reg		[2:0]		rPackedCount=0, _rPackedCount=0;
+reg					rPackedDone=0, _rPackedDone=0;
+reg					rPackedErr=0, _rPackedErr=0;
+reg					rPackedFlush=0, _rPackedFlush=0;
+reg					rPackedFlushed=0, _rPackedFlushed=0;
+reg		[223:0]		rPackedData=224'd0, _rPackedData=224'd0;
+reg		[127:0]		rDataIn=128'd0, _rDataIn=128'd0;
+reg		[2:0]		rDataInEn=0, _rDataInEn=0;
+reg		[127:0]		rDataMasked=128'd0, _rDataMasked=128'd0;
+reg		[2:0]		rDataMaskedEn=0, _rDataMaskedEn=0;
+
+
+assign PACKED_DATA = rPackedData[127:0];
+assign PACKED_WEN = rPackedCount[2];
+assign PACKED_DATA_DONE = rPackedDone;
+assign PACKED_DATA_ERR = rPackedErr;
+assign PACKED_DATA_FLUSHED = rPackedFlushed;
+
+
+// Buffers input data until 4 words are available, then writes 4 words out.
+wire [127:0] wMask = {128{1'b1}}<<(32*rDataInEn);
+wire [127:0] wDataMasked = ~wMask & rDataIn;
+always @ (posedge CLK) begin
+	rPackedCount <= #1 (RST ? 3'd0 : _rPackedCount);
+	rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
+	rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
+	rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
+	rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
+	rPackedData <= #1 (RST ? 224'd0 : _rPackedData);
+	rDataIn <= #1 _rDataIn;
+	rDataInEn <= #1 (RST ? 3'd0 : _rDataInEn);
+	rDataMasked <= #1 _rDataMasked;
+	rDataMaskedEn <= #1 (RST ? 3'd0 : _rDataMaskedEn);
+end
+
+always @ (*) begin
+	// Buffer and mask the input data.
+	_rDataIn = DATA_IN;
+	_rDataInEn = DATA_IN_EN;
+	_rDataMasked = wDataMasked;
+	_rDataMaskedEn = rDataInEn;
+
+	// Count what's in our buffer. When we reach 4 words, 4 words will be written
+	// out. If flush is requested, write out whatever remains.
+	if (rPackedFlush && (rPackedCount[1] | rPackedCount[0]))
+		_rPackedCount = 4;
+	else
+		_rPackedCount = rPackedCount + rDataMaskedEn - {rPackedCount[2], 2'd0};
+	
+	// Shift data into and out of our buffer as we receive and write out data.
+	if (rDataMaskedEn != 3'd0)
+		_rPackedData = ((rPackedData>>(32*{rPackedCount[2], 2'd0})) | (rDataMasked<<(32*rPackedCount[1:0])));
+	else
+		_rPackedData = (rPackedData>>(32*{rPackedCount[2], 2'd0}));
+
+	// Track done/error/flush signals.
+	_rPackedDone = DATA_IN_DONE;
+	_rPackedErr = DATA_IN_ERR;
+	_rPackedFlush = DATA_IN_FLUSH;
+	_rPackedFlushed = rPackedFlush;
+end
+
+
+
+endmodule
diff --git a/fpga/riffa_hdl/fifo_packer_32.v b/fpga/riffa_hdl/fifo_packer_32.v
new file mode 100644
index 0000000..eb00128
--- /dev/null
+++ b/fpga/riffa_hdl/fifo_packer_32.v
@@ -0,0 +1,101 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			fifo_packer_32.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Packs 32 bit received data into a 32 bit wide FIFO. 
+// Assumes the FIFO always has room to accommodate the data.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+// Additional Comments: 
+//-----------------------------------------------------------------------------
+
+`timescale 1ns/1ns
+module fifo_packer_32 (
+	input CLK,
+	input RST,
+	input [31:0] DATA_IN,		// Incoming data
+	input DATA_IN_EN,			// Incoming data enable
+	input DATA_IN_DONE,			// Incoming data packet end
+	input DATA_IN_ERR,			// Incoming data error
+	input DATA_IN_FLUSH,		// End of incoming data
+	output [31:0] PACKED_DATA,	// Outgoing data
+	output PACKED_WEN,			// Outgoing data write enable
+	output PACKED_DATA_DONE,	// End of outgoing data packet
+	output PACKED_DATA_ERR,		// Error in outgoing data
+	output PACKED_DATA_FLUSHED	// End of outgoing data
+);
+
+reg					rPackedDone=0, _rPackedDone=0;
+reg					rPackedErr=0, _rPackedErr=0;
+reg					rPackedFlush=0, _rPackedFlush=0;
+reg					rPackedFlushed=0, _rPackedFlushed=0;
+reg		[31:0]		rDataIn=64'd0, _rDataIn=64'd0;
+reg					rDataInEn=0, _rDataInEn=0;
+
+
+assign PACKED_DATA = rDataIn;
+assign PACKED_WEN = rDataInEn;
+assign PACKED_DATA_DONE = rPackedDone;
+assign PACKED_DATA_ERR = rPackedErr;
+assign PACKED_DATA_FLUSHED = rPackedFlushed;
+
+
+// Buffers input data to ease timing.
+always @ (posedge CLK) begin
+	rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
+	rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
+	rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
+	rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
+	rDataIn <= #1 _rDataIn;
+	rDataInEn <= #1 (RST ? 1'd0 : _rDataInEn);
+end
+
+always @ (*) begin
+	// Buffer and mask the input data.
+	_rDataIn = DATA_IN;
+	_rDataInEn = DATA_IN_EN;
+
+	// Track done/error/flush signals.
+	_rPackedDone = DATA_IN_DONE;
+	_rPackedErr = DATA_IN_ERR;
+	_rPackedFlush = DATA_IN_FLUSH;
+	_rPackedFlushed = rPackedFlush;
+end
+
+
+
+endmodule
diff --git a/fpga/riffa_hdl/fifo_packer_64.v b/fpga/riffa_hdl/fifo_packer_64.v
new file mode 100644
index 0000000..b2a86f9
--- /dev/null
+++ b/fpga/riffa_hdl/fifo_packer_64.v
@@ -0,0 +1,126 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			fifo_packer_64.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Packs 32 or 64 bit received data into a 64 bit wide FIFO. 
+// Assumes the FIFO always has room to accommodate the data.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+// Additional Comments: 
+//-----------------------------------------------------------------------------
+
+`timescale 1ns/1ns
+module fifo_packer_64 (
+	input CLK,
+	input RST,
+	input [63:0] DATA_IN,		// Incoming data
+	input [1:0] DATA_IN_EN,		// Incoming data enable
+	input DATA_IN_DONE,			// Incoming data packet end
+	input DATA_IN_ERR,			// Incoming data error
+	input DATA_IN_FLUSH,		// End of incoming data
+	output [63:0] PACKED_DATA,	// Outgoing data
+	output PACKED_WEN,			// Outgoing data write enable
+	output PACKED_DATA_DONE,	// End of outgoing data packet
+	output PACKED_DATA_ERR,		// Error in outgoing data
+	output PACKED_DATA_FLUSHED	// End of outgoing data
+);
+
+reg		[1:0]		rPackedCount=0, _rPackedCount=0;
+reg					rPackedDone=0, _rPackedDone=0;
+reg					rPackedErr=0, _rPackedErr=0;
+reg					rPackedFlush=0, _rPackedFlush=0;
+reg					rPackedFlushed=0, _rPackedFlushed=0;
+reg		[95:0]		rPackedData=96'd0, _rPackedData=96'd0;
+reg		[63:0]		rDataIn=64'd0, _rDataIn=64'd0;
+reg		[1:0]		rDataInEn=0, _rDataInEn=0;
+reg		[63:0]		rDataMasked=64'd0, _rDataMasked=64'd0;
+reg		[1:0]		rDataMaskedEn=0, _rDataMaskedEn=0;
+
+
+assign PACKED_DATA = rPackedData[63:0];
+assign PACKED_WEN = rPackedCount[1];
+assign PACKED_DATA_DONE = rPackedDone;
+assign PACKED_DATA_ERR = rPackedErr;
+assign PACKED_DATA_FLUSHED = rPackedFlushed;
+
+
+// Buffers input data until 2 words are available, then writes 2 words out.
+wire [63:0] wMask = {64{1'b1}}<<(32*rDataInEn);
+wire [63:0]	wDataMasked = ~wMask & rDataIn;
+always @ (posedge CLK) begin
+	rPackedCount <= #1 (RST ? 2'd0 : _rPackedCount);
+	rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
+	rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
+	rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
+	rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
+	rPackedData <= #1 (RST ? 96'd0 : _rPackedData);
+	rDataIn <= #1 _rDataIn;
+	rDataInEn <= #1 (RST ? 2'd0 : _rDataInEn);
+	rDataMasked <= #1 _rDataMasked;
+	rDataMaskedEn <= #1 (RST ? 2'd0 : _rDataMaskedEn);
+end
+
+always @ (*) begin
+	// Buffer and mask the input data.
+	_rDataIn = DATA_IN;
+	_rDataInEn = DATA_IN_EN;
+	_rDataMasked = wDataMasked;
+	_rDataMaskedEn = rDataInEn;
+
+	// Count what's in our buffer. When we reach 2 words, 2 words will be written
+	// out. If flush is requested, write out whatever remains.
+	if (rPackedFlush && rPackedCount[0])
+		_rPackedCount = 2;
+	else
+		_rPackedCount = rPackedCount + rDataMaskedEn - {rPackedCount[1], 1'd0};
+	
+	// Shift data into and out of our buffer as we receive and write out data.
+	if (rDataMaskedEn != 2'd0)
+		_rPackedData = ((rPackedData>>(32*{rPackedCount[1], 1'd0})) | (rDataMasked<<(32*rPackedCount[0])));
+	else
+		_rPackedData = (rPackedData>>(32*{rPackedCount[1], 1'd0}));
+
+	// Track done/error/flush signals.
+	_rPackedDone = DATA_IN_DONE;
+	_rPackedErr = DATA_IN_ERR;
+	_rPackedFlush = DATA_IN_FLUSH;
+	_rPackedFlushed = rPackedFlush;
+end
+
+
+
+endmodule
diff --git a/fpga/riffa_hdl/functions.vh b/fpga/riffa_hdl/functions.vh
new file mode 100644
index 0000000..271975c
--- /dev/null
+++ b/fpga/riffa_hdl/functions.vh
@@ -0,0 +1,35 @@
+`ifndef __FUNCTIONS_VH
+`define __FUNCTIONS_VH 1
+function integer clog2;
+	input [31:0] v;
+	reg [31:0] value;
+	begin
+		value = v;
+		if (value == 1) begin
+			clog2 = 0;
+		end
+		else begin
+			value = value-1;
+			for (clog2=0; value>0; clog2=clog2+1)
+				value = value>>1;
+		end
+	end
+endfunction
+// clog2s -- calculate the ceiling log2 value, min return is 1 (safe).
+function integer clog2s;
+	input [31:0] v;
+	reg [31:0] value;
+	begin
+		value = v;
+		if (value == 1) begin
+			clog2s = 1;
+		end
+		else begin
+			value = value-1;
+			for (clog2s=0; value>0; clog2s=clog2s+1)
+				value = value>>1;
+		end
+	end
+endfunction
+
+`endif
diff --git a/fpga/riffa_hdl/interrupt.v b/fpga/riffa_hdl/interrupt.v
new file mode 100644
index 0000000..954b798
--- /dev/null
+++ b/fpga/riffa_hdl/interrupt.v
@@ -0,0 +1,187 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			interrupt.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Manages the interrupt vector and sends interrupts.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`define S_INTR_IDLE		2'd0
+`define S_INTR_INTR		2'd1
+`define S_INTR_CLR_0	2'd2
+`define S_INTR_CLR_1	2'd3
+
+`timescale 1ns/1ns
+module interrupt #(
+	parameter C_NUM_CHNL = 4'd12
+)
+(
+	input CLK,
+	input RST,
+	input [C_NUM_CHNL-1:0] RX_SG_BUF_RECVD,	// The scatter gather data for a rx_port transaction has been read
+	input [C_NUM_CHNL-1:0] RX_TXN_DONE,		// The rx_port transaction is done
+	input [C_NUM_CHNL-1:0] TX_TXN,			// New tx_port transaction
+	input [C_NUM_CHNL-1:0] TX_SG_BUF_RECVD,	// The scatter gather data for a tx_port transaction has been read
+	input [C_NUM_CHNL-1:0] TX_TXN_DONE,		// The tx_port transaction is done
+	input VECT_0_RST,						// Interrupt vector 0 reset
+	input VECT_1_RST,						// Interrupt vector 1 reset
+	input [31:0] VECT_RST,					// Interrupt vector reset value
+	output [31:0] VECT_0,					// Interrupt vector 0
+	output [31:0] VECT_1,					// Interrupt vector 1
+	input INTR_LEGACY_CLR,					// Pulsed high to ack the legacy interrupt and clear it
+	input CONFIG_INTERRUPT_MSIENABLE,		// 1 if MSI interrupts are enable, 0 if only legacy are supported
+	input INTR_MSI_RDY,		 				// High when interrupt is able to be sent
+	output INTR_MSI_REQUEST					// High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_REQUEST are high, interrupt is sent
+);
+
+reg		[1:0]		rState=0;
+reg		[31:0]		rVect0=0;
+reg		[31:0]		rVect1=0;
+wire	[31:0]		wVect0;
+wire	[31:0]		wVect1;
+wire				wIntr = (rState == `S_INTR_INTR);
+wire				wIntrDone;
+
+assign VECT_0 = rVect0;
+assign VECT_1 = rVect1;
+
+// Align the input signals to the interrupt vector. 
+// VECT_0/VECT_1 are organized from right to left (LSB to MSB) as:
+// [ 0] TX_TXN			for channel 0 in VECT_0, channel 6 in VECT_1
+// [ 1] TX_SG_BUF_RECVD	for channel 0 in VECT_0, channel 6 in VECT_1
+// [ 2] TX_TXN_DONE		for channel 0 in VECT_0, channel 6 in VECT_1
+// [ 3] RX_SG_BUF_RECVD	for channel 0 in VECT_0, channel 6 in VECT_1
+// [ 4] RX_TXN_DONE		for channel 0 in VECT_0, channel 6 in VECT_1
+// ...
+// [25] TX_TXN			for channel 5 in VECT_0, channel 11 in VECT_1
+// [26] TX_SG_BUF_RECVD	for channel 5 in VECT_0, channel 11 in VECT_1
+// [27] TX_TXN_DONE		for channel 5 in VECT_0, channel 11 in VECT_1
+// [28] RX_SG_BUF_RECVD	for channel 5 in VECT_0, channel 11 in VECT_1
+// [29] RX_TXN_DONE		for channel 5 in VECT_0, channel 11 in VECT_1
+// Positions 30 - 31 in both VECT_0 and VECT_1 are zero.
+
+genvar i;
+generate
+	for (i = 0; i < C_NUM_CHNL; i = i + 1) begin: vectMap
+		if (i < 6) begin : vectMap0
+			assign wVect0[(5*i)+0] = TX_TXN[i];
+			assign wVect0[(5*i)+1] = TX_SG_BUF_RECVD[i];
+			assign wVect0[(5*i)+2] = TX_TXN_DONE[i];
+			assign wVect0[(5*i)+3] = RX_SG_BUF_RECVD[i];
+			assign wVect0[(5*i)+4] = RX_TXN_DONE[i];
+		end
+		else begin : vectMap1
+			assign wVect1[(5*(i-6))+0] = TX_TXN[i];
+			assign wVect1[(5*(i-6))+1] = TX_SG_BUF_RECVD[i];
+			assign wVect1[(5*(i-6))+2] = TX_TXN_DONE[i];
+			assign wVect1[(5*(i-6))+3] = RX_SG_BUF_RECVD[i];
+			assign wVect1[(5*(i-6))+4] = RX_TXN_DONE[i];
+		end	
+	end
+	for (i = C_NUM_CHNL; i < 12; i = i + 1) begin: vectZero
+		if (i < 6) begin : vectZero0
+			assign wVect0[(5*i)+0] = 1'b0;
+			assign wVect0[(5*i)+1] = 1'b0;
+			assign wVect0[(5*i)+2] = 1'b0;
+			assign wVect0[(5*i)+3] = 1'b0;
+			assign wVect0[(5*i)+4] = 1'b0;
+		end
+		else begin : vectZero1
+			assign wVect1[(5*(i-6))+0] = 1'b0;
+			assign wVect1[(5*(i-6))+1] = 1'b0;
+			assign wVect1[(5*(i-6))+2] = 1'b0;
+			assign wVect1[(5*(i-6))+3] = 1'b0;
+			assign wVect1[(5*(i-6))+4] = 1'b0;
+		end	
+	end
+	assign wVect0[30] = 1'b0;
+	assign wVect0[31] = 1'b0;
+	assign wVect1[30] = 1'b0;
+	assign wVect1[31] = 1'b0;
+endgenerate
+
+// Interrupt controller
+interrupt_controller intrCtlr (
+	.CLK(CLK),
+	.RST(RST),
+	.INTR(wIntr),
+	.INTR_LEGACY_CLR(INTR_LEGACY_CLR),
+	.INTR_DONE(wIntrDone),
+	.CFG_INTERRUPT_ASSERT(),
+	.CONFIG_INTERRUPT_MSIENABLE(CONFIG_INTERRUPT_MSIENABLE),
+	.INTR_MSI_RDY(INTR_MSI_RDY),
+	.INTR_MSI_REQUEST(INTR_MSI_REQUEST)
+);
+
+// Update the interrupt vector when new signals come in (pulse in) and on reset.
+always @(posedge CLK) begin
+	if (RST) begin
+		rVect0 <= #1 0;
+		rVect1 <= #1 0;
+	end 
+	else begin
+		if (VECT_0_RST) begin
+			rVect0 <= #1 (wVect0 | (rVect0 & ~VECT_RST));
+			rVect1 <= #1 (wVect1 | rVect1);
+		end
+		else if (VECT_1_RST) begin
+			rVect0 <= #1 (wVect0 | rVect0);
+			rVect1 <= #1 (wVect1 | (rVect1 & ~VECT_RST));
+		end
+		else begin
+			rVect0 <= #1 (wVect0 | rVect0);
+			rVect1 <= #1 (wVect1 | rVect1);
+		end
+	end
+end	
+
+// Fire the interrupt when we have a non-zero vector.
+always @(posedge CLK) begin
+	if (RST) begin
+		rState <= #1 `S_INTR_IDLE;
+	end
+	else begin
+		case (rState)
+		`S_INTR_IDLE :	rState <= #1 ((rVect0 | rVect1) == 0 ? `S_INTR_IDLE : `S_INTR_INTR);
+		`S_INTR_INTR :	rState <= #1 (wIntrDone ? `S_INTR_CLR_0 : `S_INTR_INTR);
+		`S_INTR_CLR_0 :	rState <= #1 (VECT_0_RST ? (C_NUM_CHNL > 6 ? `S_INTR_CLR_1 : `S_INTR_IDLE) : `S_INTR_CLR_0);
+		`S_INTR_CLR_1 :	rState <= #1 (VECT_1_RST ? `S_INTR_IDLE : `S_INTR_CLR_1);
+		endcase
+	end
+end	
+
+endmodule
diff --git a/fpga/riffa_hdl/interrupt_controller.v b/fpga/riffa_hdl/interrupt_controller.v
new file mode 100644
index 0000000..9528ce4
--- /dev/null
+++ b/fpga/riffa_hdl/interrupt_controller.v
@@ -0,0 +1,155 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			interrupt_controller.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Signals an interrupt on the Xilnx PCIe Endpoint 
+// 						interface. Supports single vector MSI or legacy based
+// 						interrupts. 
+//						When INTR is pulsed high, the interrupt will be issued
+//						as soon as possible. If using legacy interrupts, the 
+//						initial interrupt must be cleared by another request
+//						(typically a PIO read or write request to the 
+//						endpoint at some predetermined BAR address). Receipt of
+//						the "clear" acknowledgment should cause INTR_LEGACY_CLR 
+// 						input to pulse high. Thus completing the legacy 
+//						interrupt cycle. If using MSI interrupts, no such
+//						acknowldegment is necessary.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`define S_INTRCTLR_IDLE				3'd0
+`define S_INTRCLTR_WORKING			3'd1
+`define S_INTRCLTR_COMPLETE			3'd2
+`define S_INTRCLTR_CLEAR_LEGACY		3'd3
+`define S_INTRCLTR_CLEARING_LEGACY	3'd4
+`define S_INTRCLTR_DONE				3'd5
+
+`timescale 1ns/1ns
+module interrupt_controller (
+	input CLK,						// System clock
+	input RST,						// Async reset
+	input INTR,						// Pulsed high to request an interrupt
+	input INTR_LEGACY_CLR,			// Pulsed high to ack the legacy interrupt and clear it
+	output INTR_DONE,				// Pulsed high to signal interrupt sent
+	input CONFIG_INTERRUPT_MSIENABLE,	// 1 if MSI interrupts are enable, 0 if only legacy are supported
+	output CFG_INTERRUPT_ASSERT,	// Legacy interrupt message type
+	input INTR_MSI_RDY,		// High when interrupt is able to be sent
+	output INTR_MSI_REQUEST			// High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_REQUEST are high, interrupt is sent
+);
+
+reg		[2:0]	rState=`S_INTRCTLR_IDLE;
+reg		[2:0]	rStateNext=`S_INTRCTLR_IDLE;
+reg				rIntr=0;
+reg				rIntrAssert=0;
+
+assign INTR_DONE = (rState == `S_INTRCLTR_DONE);
+assign INTR_MSI_REQUEST = rIntr;
+assign CFG_INTERRUPT_ASSERT = rIntrAssert;
+
+// Control sending interrupts.
+always @(*) begin
+	case (rState)
+
+	`S_INTRCTLR_IDLE : begin
+		if (INTR) begin
+			rIntr = 1;
+			rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
+			rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);
+		end 
+		else begin
+			rIntr = 0;
+			rIntrAssert = 0;
+			rStateNext = `S_INTRCTLR_IDLE;
+		end
+	end
+
+	`S_INTRCLTR_WORKING : begin
+		rIntr = 1;
+		rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
+		rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);
+	end
+
+	`S_INTRCLTR_COMPLETE : begin
+		rIntr = 0;
+		rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
+		rStateNext = (CONFIG_INTERRUPT_MSIENABLE ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEAR_LEGACY);
+	end
+
+	`S_INTRCLTR_CLEAR_LEGACY : begin
+		if (INTR_LEGACY_CLR) begin
+			rIntr = 1;
+			rIntrAssert = 0;
+			rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);
+		end 
+		else begin
+			rIntr = 0;
+			rIntrAssert = 1;
+			rStateNext = `S_INTRCLTR_CLEAR_LEGACY;
+		end
+	end
+
+	`S_INTRCLTR_CLEARING_LEGACY : begin
+		rIntr = 1;
+		rIntrAssert = 0;
+		rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);
+	end
+
+	`S_INTRCLTR_DONE : begin
+		rIntr = 0;
+		rIntrAssert = 0;
+		rStateNext = `S_INTRCTLR_IDLE;
+	end
+	
+	default: begin
+		rIntr = 0;
+		rIntrAssert = 0;
+		rStateNext = `S_INTRCTLR_IDLE;
+	end
+	
+	endcase
+end
+
+// Update the state.
+always @(posedge CLK) begin
+	if (RST)
+		rState <= #1 `S_INTRCTLR_IDLE;
+	else
+		rState <= #1 rStateNext;
+end
+
+endmodule
+
diff --git a/fpga/riffa_hdl/mux.v b/fpga/riffa_hdl/mux.v
new file mode 100644
index 0000000..8350c8d
--- /dev/null
+++ b/fpga/riffa_hdl/mux.v
@@ -0,0 +1,126 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			mux.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			A simple multiplexer
+// Author:				Dustin Richmond (@darichmond)
+// TODO:                Remove C_CLOG_NUM_INPUTS
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "functions.vh"
+module mux
+    #(
+      parameter C_NUM_INPUTS = 4,
+      parameter C_CLOG_NUM_INPUTS = 2,
+      parameter C_WIDTH = 32,
+      parameter C_MUX_TYPE = "SELECT"
+      )
+    (
+     input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
+     input [C_CLOG_NUM_INPUTS-1:0]      MUX_SELECT,
+     output [C_WIDTH-1:0]               MUX_OUTPUT
+     );
+    generate
+        if(C_MUX_TYPE == "SELECT") begin
+            mux_select
+                #(/*AUTOINSTPARAM*/
+                  // Parameters
+                  .C_NUM_INPUTS             (C_NUM_INPUTS),
+                  .C_CLOG_NUM_INPUTS        (C_CLOG_NUM_INPUTS),
+                  .C_WIDTH                  (C_WIDTH))
+            mux_select_inst
+                (/*AUTOINST*/
+                 // Outputs
+                 .MUX_OUTPUT            (MUX_OUTPUT[C_WIDTH-1:0]),
+                 // Inputs
+                 .MUX_INPUTS            (MUX_INPUTS[(C_NUM_INPUTS)*C_WIDTH-1:0]),
+                 .MUX_SELECT            (MUX_SELECT[C_CLOG_NUM_INPUTS-1:0]));
+        end else if (C_MUX_TYPE == "SHIFT") begin
+            mux_shift
+                #(/*AUTOINSTPARAM*/
+                  // Parameters
+                  .C_NUM_INPUTS             (C_NUM_INPUTS),
+                  .C_CLOG_NUM_INPUTS        (C_CLOG_NUM_INPUTS),
+                  .C_WIDTH                  (C_WIDTH))
+            mux_shift_inst
+                (/*AUTOINST*/
+                 // Outputs
+                 .MUX_OUTPUT            (MUX_OUTPUT[C_WIDTH-1:0]),
+                 // Inputs
+                 .MUX_INPUTS            (MUX_INPUTS[(C_NUM_INPUTS)*C_WIDTH-1:0]),
+                 .MUX_SELECT            (MUX_SELECT[C_CLOG_NUM_INPUTS-1:0]));
+        end
+    endgenerate
+endmodule
+
+module mux_select
+    #(
+      parameter C_NUM_INPUTS = 4,
+      parameter C_CLOG_NUM_INPUTS = 2,
+      parameter C_WIDTH = 32
+      )
+    (
+     input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
+     input [C_CLOG_NUM_INPUTS-1:0]      MUX_SELECT,
+     output [C_WIDTH-1:0]               MUX_OUTPUT
+     );
+    genvar                              i;
+    wire [C_WIDTH-1:0]                  wMuxInputs[C_NUM_INPUTS-1:0];
+    assign MUX_OUTPUT = wMuxInputs[MUX_SELECT];
+    generate
+        for (i = 0; i < C_NUM_INPUTS ; i = i + 1) begin : gen_muxInputs_array
+            assign wMuxInputs[i] = MUX_INPUTS[i*C_WIDTH +: C_WIDTH];
+        end
+    endgenerate
+endmodule
+
+module mux_shift
+    #(
+      parameter C_NUM_INPUTS = 4,
+      parameter C_CLOG_NUM_INPUTS = 2,
+      parameter C_WIDTH = 32
+      )
+    (
+     input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
+     input [C_CLOG_NUM_INPUTS-1:0]      MUX_SELECT,
+     output [C_WIDTH-1:0]               MUX_OUTPUT
+     );
+    genvar                              i;
+    wire [C_WIDTH*C_NUM_INPUTS-1:0]     wMuxInputs;
+    assign wMuxInputs = MUX_INPUTS >> MUX_SELECT;   
+    assign MUX_OUTPUT = wMuxInputs[C_WIDTH-1:0];
+endmodule
diff --git a/fpga/riffa_hdl/offset_flag_to_one_hot.v b/fpga/riffa_hdl/offset_flag_to_one_hot.v
new file mode 100644
index 0000000..2b18d70
--- /dev/null
+++ b/fpga/riffa_hdl/offset_flag_to_one_hot.v
@@ -0,0 +1,58 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            offset_flag_to_one_hot.v
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The offset_flag_to_one_hot module takes a data offset,
+// and offset_enable and computes the 1-hot encoding of the offset when enabled
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "trellis.vh"
+module offset_flag_to_one_hot
+    #(
+      parameter C_WIDTH = 4
+      )
+    (
+     input [clog2s(C_WIDTH)-1:0] WR_OFFSET,
+     input                       WR_FLAG,
+     output [C_WIDTH-1:0]        RD_ONE_HOT
+     );
+
+    assign RD_ONE_HOT = {{(C_WIDTH-1){1'b0}},WR_FLAG} << WR_OFFSET;
+endmodule
+
+
diff --git a/fpga/riffa_hdl/offset_to_mask.v b/fpga/riffa_hdl/offset_to_mask.v
new file mode 100644
index 0000000..79cb33c
--- /dev/null
+++ b/fpga/riffa_hdl/offset_to_mask.v
@@ -0,0 +1,94 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+`include "functions.vh"
+module offset_to_mask
+    #(parameter C_MASK_SWAP = 1,
+      parameter C_MASK_WIDTH = 4)
+    (
+     input                            OFFSET_ENABLE,
+     input [clog2s(C_MASK_WIDTH)-1:0] OFFSET,
+     output [C_MASK_WIDTH-1:0]        MASK
+     );
+
+    reg [7:0]                         _rMask,_rMaskSwap; 
+    wire [3:0]                        wSelect;
+    assign wSelect = {OFFSET_ENABLE,{{(3-clog2s(C_MASK_WIDTH)){1'b0}},OFFSET}};
+    assign MASK = (C_MASK_SWAP)? _rMaskSwap[7 -: C_MASK_WIDTH]: _rMask[C_MASK_WIDTH-1:0];
+    always @(*) begin
+        _rMask = 0;
+        _rMaskSwap = 0;
+        /* verilator lint_off CASEX */
+        casex(wSelect)
+            default: begin
+                _rMask = 8'b1111_1111;
+                _rMaskSwap = 8'b1111_1111;
+            end
+            4'b1000: begin
+                _rMask = 8'b0000_0001;
+                _rMaskSwap = 8'b1111_1111;
+            end
+            4'b1001: begin
+                _rMask = 8'b0000_0011;
+                _rMaskSwap = 8'b0111_1111;
+            end
+            4'b1010: begin
+                _rMask = 8'b0000_0111;
+                _rMaskSwap = 8'b0011_1111;
+            end
+            4'b1011: begin
+                _rMask = 8'b0000_1111;
+                _rMaskSwap = 8'b0001_1111;
+            end
+            4'b1100: begin
+                _rMask = 8'b0001_1111;
+                _rMaskSwap = 8'b0000_1111;
+            end
+            4'b1101: begin
+                _rMask = 8'b0011_1111;
+                _rMaskSwap = 8'b0000_0111;
+            end
+            4'b1110: begin
+                _rMask = 8'b0111_1111;
+                _rMaskSwap = 8'b0000_0011;
+            end
+            4'b1111: begin
+                _rMask = 8'b1111_1111;
+                _rMaskSwap = 8'b0000_0001;
+            end
+        endcase // casez ({OFFSET_MASK,OFFSET})
+
+        /* verilator lint_on CASEX */
+    end
+endmodule
diff --git a/fpga/riffa_hdl/one_hot_mux.v b/fpga/riffa_hdl/one_hot_mux.v
new file mode 100644
index 0000000..da8df2e
--- /dev/null
+++ b/fpga/riffa_hdl/one_hot_mux.v
@@ -0,0 +1,102 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			one_hot_mux.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			A mux module, where the output select is a one-hot bus
+// Author:				Dustin Richmond
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "functions.vh"
+module one_hot_mux
+    #(parameter C_DATA_WIDTH = 1,
+      parameter C_SELECT_WIDTH = 2,
+      parameter C_AGGREGATE_WIDTH = C_SELECT_WIDTH*C_DATA_WIDTH
+      )
+    (
+     input [C_SELECT_WIDTH-1:0]    ONE_HOT_SELECT,
+     input [C_AGGREGATE_WIDTH-1:0] ONE_HOT_INPUTS,
+     output [C_DATA_WIDTH-1:0]     ONE_HOT_OUTPUT);
+
+    genvar                         i;
+
+    wire [C_DATA_WIDTH-1:0]        wOneHotInputs[(1<<C_SELECT_WIDTH):1];
+    reg [C_DATA_WIDTH-1:0]         _rOneHotOutput;
+
+    assign ONE_HOT_OUTPUT = _rOneHotOutput;
+    generate
+        for( i = 0 ; i < C_SELECT_WIDTH; i = i + 1 ) begin : gen_input_array
+            assign wOneHotInputs[(1<<i)] = ONE_HOT_INPUTS[C_DATA_WIDTH*i +: C_DATA_WIDTH];
+        end
+        if(C_SELECT_WIDTH == 1) begin
+            always @(*) begin
+                _rOneHotOutput = wOneHotInputs[1];
+            end
+        end else if(C_SELECT_WIDTH == 2) begin
+            always @(*) begin
+                case(ONE_HOT_SELECT)
+                    2'b01: _rOneHotOutput = wOneHotInputs[1];
+                    2'b10: _rOneHotOutput = wOneHotInputs[2];
+                    default:_rOneHotOutput = wOneHotInputs[1];
+                endcase // case (ONE_HOT_SELECT)
+            end
+        end else if( C_SELECT_WIDTH == 4) begin
+            always @(*) begin
+                case(ONE_HOT_SELECT)
+                    4'b0001: _rOneHotOutput = wOneHotInputs[1];
+                    4'b0010: _rOneHotOutput = wOneHotInputs[2];
+                    4'b0100: _rOneHotOutput = wOneHotInputs[4];
+                    4'b1000: _rOneHotOutput = wOneHotInputs[8];
+                    default:_rOneHotOutput = wOneHotInputs[1];
+                endcase // case (ONE_HOT_SELECT)
+            end
+        end else if( C_SELECT_WIDTH == 8) begin
+            always @(*) begin
+                case(ONE_HOT_SELECT)
+                    8'b00000001: _rOneHotOutput = wOneHotInputs[1];
+                    8'b00000010: _rOneHotOutput = wOneHotInputs[2];
+                    8'b00000100: _rOneHotOutput = wOneHotInputs[4];
+                    8'b00001000: _rOneHotOutput = wOneHotInputs[8];
+                    8'b00010000: _rOneHotOutput = wOneHotInputs[16];
+                    8'b00100000: _rOneHotOutput = wOneHotInputs[32];
+                    8'b01000000: _rOneHotOutput = wOneHotInputs[64];
+                    8'b10000000: _rOneHotOutput = wOneHotInputs[128];
+                    default:_rOneHotOutput = wOneHotInputs[1];
+                endcase // case (ONE_HOT_SELECT)
+            end
+        end 
+    endgenerate
+endmodule
diff --git a/fpga/riffa_hdl/pipeline.v b/fpga/riffa_hdl/pipeline.v
new file mode 100644
index 0000000..7d8ae23
--- /dev/null
+++ b/fpga/riffa_hdl/pipeline.v
@@ -0,0 +1,284 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			pipeline.v
+// Version:				1.00
+// Verilog Standard:	Verilog-2001
+// Description: Standard 0-delay pipeline implementation. Takes WR_DATA on
+// WR_READY and WR_VALID. RD_DATA is read on RD_READY and
+// RD_VALID. C_DEPTH specifies the latency between RD and WR ports
+// Author:				Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+module pipeline
+    #(
+      parameter C_DEPTH = 10,
+      parameter C_WIDTH = 10,
+      parameter C_USE_MEMORY = 1
+      )
+    (
+     input                CLK,
+     input                RST_IN,
+
+     input [C_WIDTH-1:0]  WR_DATA,
+     input                WR_DATA_VALID,
+     output               WR_DATA_READY,
+
+     output [C_WIDTH-1:0] RD_DATA,
+     output               RD_DATA_VALID,
+     input                RD_DATA_READY
+     );
+
+    generate
+        if (C_USE_MEMORY & C_DEPTH > 2) begin
+            mem_pipeline
+                #(
+                  .C_PIPELINE_INPUT     (1),
+                  .C_PIPELINE_OUTPUT    (1),
+                  /*AUTOINSTPARAM*/
+                  // Parameters
+                  .C_DEPTH              (C_DEPTH),
+                  .C_WIDTH              (C_WIDTH))
+            pipeline_inst
+                (/*AUTOINST*/
+                 // Outputs
+                 .WR_DATA_READY         (WR_DATA_READY),
+                 .RD_DATA               (RD_DATA[C_WIDTH-1:0]),
+                 .RD_DATA_VALID         (RD_DATA_VALID),
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST_IN                (RST_IN),
+                 .WR_DATA               (WR_DATA[C_WIDTH-1:0]),
+                 .WR_DATA_VALID         (WR_DATA_VALID),
+                 .RD_DATA_READY         (RD_DATA_READY));
+            
+        end else begin
+            reg_pipeline
+                #(/*AUTOINSTPARAM*/
+                  // Parameters
+                  .C_DEPTH              (C_DEPTH),
+                  .C_WIDTH              (C_WIDTH))
+            pipeline_inst
+                (/*AUTOINST*/
+                 // Outputs
+                 .WR_DATA_READY         (WR_DATA_READY),
+                 .RD_DATA               (RD_DATA[C_WIDTH-1:0]),
+                 .RD_DATA_VALID         (RD_DATA_VALID),
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST_IN                (RST_IN),
+                 .WR_DATA               (WR_DATA[C_WIDTH-1:0]),
+                 .WR_DATA_VALID         (WR_DATA_VALID),
+                 .RD_DATA_READY         (RD_DATA_READY));
+        end
+    endgenerate
+endmodule // pipeline
+
+module mem_pipeline
+    #(
+      parameter C_DEPTH = 10,
+      parameter C_WIDTH = 10,
+      parameter C_PIPELINE_INPUT = 0,
+      parameter C_PIPELINE_OUTPUT = 1
+      )
+    (
+     input                CLK,
+     input                RST_IN,
+
+     input [C_WIDTH-1:0]  WR_DATA,
+     input                WR_DATA_VALID,
+     output               WR_DATA_READY,
+
+     output [C_WIDTH-1:0] RD_DATA,
+     output               RD_DATA_VALID,
+     input                RD_DATA_READY
+     );
+
+    localparam C_INPUT_REGISTERS = C_PIPELINE_INPUT?1:0;
+    localparam C_OUTPUT_REGISTERS = C_PIPELINE_OUTPUT?1:0;
+    
+    wire                  RST;
+    
+    wire [C_WIDTH-1:0]    wRdData;
+    wire                  wRdDataValid;
+    wire                  wRdDataReady;
+
+    wire [C_WIDTH-1:0]    wWrData;
+    wire                  wWrDataValid;
+    wire                  wWrDataReady;
+
+    assign RST = RST_IN;
+
+    reg_pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_INPUT_REGISTERS),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_WIDTH                      (C_WIDTH))
+    reg_in
+        (
+         // Outputs
+         .RD_DATA                       (wRdData),
+         .RD_DATA_VALID                 (wRdDataValid),
+         // Inputs
+         .RD_DATA_READY                 (wRdDataReady),
+         /*AUTOINST*/
+         // Outputs
+         .WR_DATA_READY                 (WR_DATA_READY),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .WR_DATA                       (WR_DATA[C_WIDTH-1:0]),
+         .WR_DATA_VALID                 (WR_DATA_VALID));
+    
+    fifo
+        #(
+          // Parameters
+          .C_WIDTH                      (C_WIDTH),
+          .C_DEPTH                      (C_DEPTH - C_PIPELINE_INPUT - C_PIPELINE_OUTPUT),
+          .C_DELAY                      (C_DEPTH - C_PIPELINE_INPUT - C_PIPELINE_OUTPUT)
+          /*AUTOINSTPARAM*/)
+    fifo_inst
+        (
+         // Outputs
+         .RD_DATA                       (wWrData),
+         .WR_READY                      (wRdDataReady),
+         .RD_VALID                      (wWrDataValid),
+         // Inputs
+         .WR_DATA                       (wRdData),
+         .WR_VALID                      (wRdDataValid),
+         .RD_READY                      (wWrDataReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST                           (RST));
+
+    reg_pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_OUTPUT_REGISTERS),
+          .C_WIDTH                      (C_WIDTH)
+          /*AUTOINSTPARAM*/)
+    reg_OUT
+        (
+         // Outputs
+         .WR_DATA_READY                 (wWrDataReady),
+         // Inputs
+         .WR_DATA                       (wWrData),
+         .WR_DATA_VALID                 (wWrDataValid),
+         /*AUTOINST*/
+         // Outputs
+         .RD_DATA                       (RD_DATA[C_WIDTH-1:0]),
+         .RD_DATA_VALID                 (RD_DATA_VALID),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .RD_DATA_READY                 (RD_DATA_READY));
+
+endmodule // mem_pipeline
+
+/* verilator lint_off UNOPTFLAT */
+module reg_pipeline
+    #(
+      parameter C_DEPTH = 10,
+      parameter C_WIDTH = 10
+      )
+    (
+     input                CLK,
+     input                RST_IN,
+
+     input [C_WIDTH-1:0]  WR_DATA,
+     input                WR_DATA_VALID,
+     output               WR_DATA_READY,
+
+     output [C_WIDTH-1:0] RD_DATA,
+     output               RD_DATA_VALID,
+     input                RD_DATA_READY
+     );
+
+    genvar                i;
+
+    wire                  wReady [C_DEPTH:0];
+    
+    reg [C_WIDTH-1:0]     _rData [C_DEPTH:1], rData [C_DEPTH:0];
+    reg                   _rValid [C_DEPTH:1], rValid [C_DEPTH:0];
+
+    // Read interface
+    assign wReady[C_DEPTH] = RD_DATA_READY;
+    assign RD_DATA = rData[C_DEPTH];
+    assign RD_DATA_VALID = rValid[C_DEPTH];
+
+    // Write interface
+    assign WR_DATA_READY = wReady[0];
+    always @(*) begin
+        rData[0] = WR_DATA;
+        rValid[0] = WR_DATA_VALID;
+    end
+
+    generate
+        for( i = 1 ; i <= C_DEPTH; i = i + 1 ) begin : gen_stages
+            assign #1 wReady[i-1] =  ~rValid[i] | wReady[i];
+
+            // Data Registers
+            always @(*) begin
+                _rData[i] = rData[i-1];
+            end
+
+            // Enable the data register when the corresponding stage is ready
+            always @(posedge CLK) begin
+                if(wReady[i-1]) begin
+                    rData[i] <= #1 _rData[i];
+                end
+            end
+
+            // Valid Registers
+            always @(*) begin
+                if(RST_IN) begin
+                    _rValid[i] = 1'b0;
+                end else begin
+                    _rValid[i] = rValid[i-1] | (rValid[i] & ~wReady[i]);
+                end
+            end
+
+            // Always enable the valid registers
+            always @(posedge CLK) begin
+                rValid[i] <= #1 _rValid[i];
+            end
+
+        end
+    endgenerate
+endmodule
+/* verilator lint_on UNOPTFLAT */
diff --git a/fpga/riffa_hdl/ram_1clk_1w_1r.v b/fpga/riffa_hdl/ram_1clk_1w_1r.v
new file mode 100644
index 0000000..820b16e
--- /dev/null
+++ b/fpga/riffa_hdl/ram_1clk_1w_1r.v
@@ -0,0 +1,70 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            ram_1clk_1w_1r.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         An inferrable RAM module. Single clock, 1 write port, 1 
+//                      read port. In Xilinx designs, specify RAM_STYLE="BLOCK" 
+//                      to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use 
+//                      LUT memory.
+// Author:              Matt Jacobsen
+// History:             @mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "functions.vh"
+module ram_1clk_1w_1r
+    #(
+      parameter C_RAM_WIDTH = 32,
+      parameter C_RAM_DEPTH = 1024
+      )
+    (
+     input                           CLK,
+     input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
+     input                           WEA,
+     input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
+     input [C_RAM_WIDTH-1:0]         DINA,
+     output [C_RAM_WIDTH-1:0]        DOUTB
+     );
+    localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
+    reg [C_RAM_WIDTH-1:0]            rRAM [C_RAM_DEPTH-1:0];
+    reg [C_RAM_WIDTH-1:0]            rDout;
+    assign DOUTB = rDout;
+    always @(posedge CLK) begin
+        if (WEA)
+            rRAM[ADDRA] <= #1 DINA;
+        rDout <= #1 rRAM[ADDRB];
+    end    
+endmodule
diff --git a/fpga/riffa_hdl/ram_2clk_1w_1r.v b/fpga/riffa_hdl/ram_2clk_1w_1r.v
new file mode 100644
index 0000000..cfd7dac
--- /dev/null
+++ b/fpga/riffa_hdl/ram_2clk_1w_1r.v
@@ -0,0 +1,74 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            ram_2clk_1w_1r.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         An inferrable RAM module. Dual clocks, 1 write port, 1 
+//                      read port. In Xilinx designs, specify RAM_STYLE="BLOCK" 
+//                      to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use 
+//                      LUT memory.
+// Author:              Matt Jacobsen
+// History:             @mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "functions.vh"
+module ram_2clk_1w_1r 
+    #(
+      parameter C_RAM_WIDTH = 32,
+      parameter C_RAM_DEPTH = 1024
+      )
+    (
+     input                           CLKA,
+     input                           CLKB,
+     input                           WEA,
+     input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
+     input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
+     input [C_RAM_WIDTH-1:0]         DINA,
+     output [C_RAM_WIDTH-1:0]        DOUTB
+     );
+    //Local parameters
+    localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
+    reg [C_RAM_WIDTH-1:0]            rRAM [C_RAM_DEPTH-1:0];
+    reg [C_RAM_WIDTH-1:0]            rDout;   
+    assign DOUTB = rDout;
+    always @(posedge CLKA) begin
+        if (WEA)
+            rRAM[ADDRA] <= #1 DINA;
+    end
+    always @(posedge CLKB) begin
+        rDout <= #1 rRAM[ADDRB];
+    end
+endmodule
diff --git a/fpga/riffa_hdl/recv_credit_flow_ctrl.v b/fpga/riffa_hdl/recv_credit_flow_ctrl.v
new file mode 100644
index 0000000..d09b576
--- /dev/null
+++ b/fpga/riffa_hdl/recv_credit_flow_ctrl.v
@@ -0,0 +1,108 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            recv_credit_flow_ctrl.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:     Monitors the receive completion credits for headers and
+//          data to make sure the rx_port modules don't request too 
+//          much data from the root complex, as this could result in
+//          some data being dropped/lost.
+// Author:      Matt Jacobsen
+// Author:      Dustin Richmond
+// History:     @mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+module recv_credit_flow_ctrl
+    (
+     input        CLK,
+     input        RST,
+     input [2:0]  CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+     input [11:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
+     input [7:0]  CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
+     input        CONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=128 bytes)w
+     input        RX_ENG_RD_DONE, // Read completed
+     input        TX_ENG_RD_REQ_SENT, // Read completion request issued
+     output       RXBUF_SPACE_AVAIL // High if enough read completion credits exist to make a read completion request
+     );
+
+    reg           rCreditAvail=0;
+    reg           rCplDAvail=0;
+    reg           rCplHAvail=0;
+    reg [12:0]    rMaxRecv=0;
+    reg [11:0]    rCplDAmt=0;
+    reg [7:0]     rCplHAmt=0;
+    reg [11:0]    rCplD=0;
+    reg [7:0]     rCplH=0;
+
+    reg           rInfHCred; // TODO: Altera uses sideband signals (would have been more convenient, thanks Xilinx!)
+    reg           rInfDCred; // TODO: Altera uses sideband signals (would have been more convenient, thanks Xilinx!)
+    
+
+    assign RXBUF_SPACE_AVAIL = rCreditAvail;
+
+    // Determine the completions required for a max read completion request.
+    always @(posedge CLK) begin
+        rInfHCred <= (CONFIG_MAX_CPL_HDR == 0);
+        rInfDCred <= (CONFIG_MAX_CPL_DATA == 0);
+        rMaxRecv <= #1 (13'd128<<CONFIG_MAX_READ_REQUEST_SIZE);
+        rCplHAmt <= #1 (rMaxRecv>>({2'b11, CONFIG_CPL_BOUNDARY_SEL}));
+        rCplDAmt <= #1 (rMaxRecv>>4);
+        rCplHAvail <= #1 (rCplH <= CONFIG_MAX_CPL_HDR);
+        rCplDAvail <= #1 (rCplD <= CONFIG_MAX_CPL_DATA);
+        rCreditAvail <= #1 ((rCplHAvail|rInfHCred) & (rCplDAvail | rInfDCred));
+    end
+
+    // Count the number of outstanding read completion requests.
+    always @ (posedge CLK) begin
+        if (RST) begin
+            rCplH <= #1 0;
+            rCplD <= #1 0;
+        end
+        else if (RX_ENG_RD_DONE & TX_ENG_RD_REQ_SENT) begin
+            rCplH <= #1 rCplH;
+            rCplD <= #1 rCplD;
+        end
+        else if (TX_ENG_RD_REQ_SENT) begin
+            rCplH <= #1 rCplH + rCplHAmt;
+            rCplD <= #1 rCplD + rCplDAmt;
+        end
+        else if (RX_ENG_RD_DONE) begin
+            rCplH <= #1 rCplH - rCplHAmt;
+            rCplD <= #1 rCplD - rCplDAmt;
+        end
+    end
+
+endmodule
diff --git a/fpga/riffa_hdl/register.v b/fpga/riffa_hdl/register.v
new file mode 100644
index 0000000..0b46cd4
--- /dev/null
+++ b/fpga/riffa_hdl/register.v
@@ -0,0 +1,67 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			register.v
+// Version:				1.00
+// Verilog Standard:	Verilog-2001
+// Description:         A simple parameterized register
+// Author:				Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+module register
+    #(parameter C_WIDTH = 1,
+      parameter C_VALUE = 0
+      )
+    (input CLK,
+     input                RST_IN,
+     output [C_WIDTH-1:0] RD_DATA,
+     input [C_WIDTH-1:0]  WR_DATA,
+     input                WR_EN
+     );
+
+    reg [C_WIDTH-1:0]     rData;
+
+    assign RD_DATA = rData;
+    always @(posedge CLK) begin
+        if(RST_IN) begin
+            rData <= C_VALUE;
+        end else if(WR_EN) begin
+            rData <= WR_DATA;
+        end 
+    end
+
+endmodule
+
+
diff --git a/fpga/riffa_hdl/registers.v b/fpga/riffa_hdl/registers.v
new file mode 100644
index 0000000..93d7318
--- /dev/null
+++ b/fpga/riffa_hdl/registers.v
@@ -0,0 +1,567 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+module registers
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_NUM_CHNL = 12,
+      parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes)
+      parameter C_VENDOR = "ALTERA",
+      parameter C_NUM_VECTORS = 2,
+      parameter C_VECTOR_WIDTH = 32,
+      parameter C_FPGA_NAME = "FPGA",
+      parameter C_PIPELINE_OUTPUT= 1,
+      parameter C_PIPELINE_INPUT= 1
+      )
+    (
+     // Interface: Clocks
+     input                                     CLK,
+
+     // Interface: Resets
+     input                                     RST_IN,
+
+     // Interface: RXR Engine
+     input [C_PCI_DATA_WIDTH-1:0]              RXR_DATA,
+     input                                     RXR_DATA_VALID,
+     input                                     RXR_DATA_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   RXR_DATA_START_OFFSET,
+     input [`SIG_FBE_W-1:0]                    RXR_META_FDWBE,
+     input                                     RXR_DATA_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   RXR_DATA_END_OFFSET,
+     input [`SIG_LBE_W-1:0]                    RXR_META_LDWBE,
+     input [`SIG_TC_W-1:0]                     RXR_META_TC,
+     input [`SIG_ATTR_W-1:0]                   RXR_META_ATTR,
+     input [`SIG_TAG_W-1:0]                    RXR_META_TAG,
+     input [`SIG_TYPE_W-1:0]                   RXR_META_TYPE,
+     input [`SIG_ADDR_W-1:0]                   RXR_META_ADDR,
+     input [`SIG_BARDECODE_W-1:0]              RXR_META_BAR_DECODED,
+     input [`SIG_REQID_W-1:0]                  RXR_META_REQUESTER_ID,
+     input [`SIG_LEN_W-1:0]                    RXR_META_LENGTH,
+
+     // Interface: TXC Engine
+     output                                    TXC_DATA_VALID,
+     output [C_PCI_DATA_WIDTH-1:0]             TXC_DATA,
+     output                                    TXC_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXC_DATA_START_OFFSET,
+     output                                    TXC_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXC_DATA_END_OFFSET,
+     input                                     TXC_DATA_READY,
+    
+     output                                    TXC_META_VALID,
+     output [`SIG_FBE_W-1:0]                   TXC_META_FDWBE,
+     output [`SIG_LBE_W-1:0]                   TXC_META_LDWBE,
+     output [`SIG_LOWADDR_W-1:0]               TXC_META_ADDR,
+     output [`SIG_TYPE_W-1:0]                  TXC_META_TYPE,
+     output [`SIG_LEN_W-1:0]                   TXC_META_LENGTH,
+     output [`SIG_BYTECNT_W-1:0]               TXC_META_BYTE_COUNT,
+     output [`SIG_TAG_W-1:0]                   TXC_META_TAG,
+     output [`SIG_REQID_W-1:0]                 TXC_META_REQUESTER_ID,
+     output [`SIG_TC_W-1:0]                    TXC_META_TC,
+     output [`SIG_ATTR_W-1:0]                  TXC_META_ATTR,
+     output                                    TXC_META_EP,
+     input                                     TXC_META_READY,
+
+     // Interface: Channel - WR
+     output [31:0]                             CHNL_REQ_DATA, 
+
+     output [C_NUM_CHNL-1:0]                   CHNL_SGRX_LEN_VALID,
+     output [C_NUM_CHNL-1:0]                   CHNL_SGRX_ADDRLO_VALID,
+     output [C_NUM_CHNL-1:0]                   CHNL_SGRX_ADDRHI_VALID,
+     output [C_NUM_CHNL-1:0]                   CHNL_SGTX_LEN_VALID,
+     output [C_NUM_CHNL-1:0]                   CHNL_SGTX_ADDRLO_VALID,
+     output [C_NUM_CHNL-1:0]                   CHNL_SGTX_ADDRHI_VALID,
+     output [C_NUM_CHNL-1:0]                   CHNL_RX_LEN_VALID,
+     output [C_NUM_CHNL-1:0]                   CHNL_RX_OFFLAST_VALID,
+    
+     // Interface: Channel - RD
+     input [(`SIG_TXRLEN_W*C_NUM_CHNL)-1:0]    CHNL_TX_REQLEN,
+     input [(`SIG_OFFLAST_W*C_NUM_CHNL)-1:0]   CHNL_TX_OFFLAST,
+     input [(`SIG_TXDONELEN_W*C_NUM_CHNL)-1:0] CHNL_TX_DONELEN,
+     input [(`SIG_RXDONELEN_W*C_NUM_CHNL)-1:0] CHNL_RX_DONELEN,
+     input [`SIG_CORESETTINGS_W-1:0]           CORE_SETTINGS, 
+     output [C_NUM_CHNL-1:0]                   CHNL_TX_LEN_READY,
+     output [C_NUM_CHNL-1:0]                   CHNL_TX_OFFLAST_READY,
+     output                                    CORE_SETTINGS_READY,
+     output [C_NUM_VECTORS-1:0]                INTR_VECTOR_READY,
+     output [C_NUM_CHNL-1:0]                   CHNL_TX_DONE_READY,
+     output [C_NUM_CHNL-1:0]                   CHNL_RX_DONE_READY,
+     output                                    CHNL_NAME_READY,
+
+     // Interface: Interrupt Vectors
+     input [C_NUM_VECTORS*C_VECTOR_WIDTH-1:0]  INTR_VECTOR
+     );
+
+    localparam C_ADDR_RANGE = 256;
+    localparam C_ARRAY_LENGTH = (32*C_ADDR_RANGE)/C_PCI_DATA_WIDTH;
+    localparam C_NAME_WIDTH = 32;
+    localparam C_FIELDS_WIDTH = 4;
+    localparam C_OUTPUT_STAGES = C_PIPELINE_OUTPUT > 0 ? 1:0;
+    localparam C_INPUT_STAGES = C_PIPELINE_INPUT > 0 ? 1:0;
+    localparam C_TXC_REGISTER_WIDTH = C_PCI_DATA_WIDTH + 2*(1 + clog2(C_PCI_DATA_WIDTH/32) + `SIG_FBE_W) + `SIG_LOWADDR_W + `SIG_TYPE_W + `SIG_LEN_W + `SIG_BYTECNT_W + `SIG_TAG_W + `SIG_REQID_W + `SIG_TC_W + `SIG_ATTR_W + 1;
+    localparam C_RXR_REGISTER_WIDTH = C_PCI_DATA_WIDTH + 2*(1 + clog2(C_PCI_DATA_WIDTH/32) + `SIG_FBE_W) + `SIG_ADDR_W + `SIG_TYPE_W + `SIG_LEN_W + `SIG_TAG_W + `SIG_REQID_W + `SIG_TC_W + `SIG_ATTR_W;
+    
+    // The Mem/IO read/write address space should be at least 8 bits wide. This 
+    // means we'll need at least 10 bits of BAR 0, at least 1024 bytes. The bottom
+    // two bits must always be zero (i.e. all addresses are 4 byte word aligned).
+    // The Mem/IO read/write address space is partitioned as illustrated below.
+    // {CHANNEL_NUM} {DATA_OFFSETS} {ZERO}
+    // ------4-------------4-----------2--
+    // The lower 2 bits are always zero. The middle 4 bits are used according to
+    // the listing below. The top 4 bits differentiate between channels for values
+    // defined in the table below.
+    // 0000 = Length of SG buffer for RX transaction                        (Write only)
+    // 0001 = PC low address of SG buffer for RX transaction                (Write only)
+    // 0010 = PC high address of SG buffer for RX transaction               (Write only)
+    // 0011 = Transfer length for RX transaction                            (Write only)
+    // 0100 = Offset/Last for RX transaction                                (Write only)
+    // 0101 = Length of SG buffer for TX transaction                        (Write only)
+    // 0110 = PC low address of SG buffer for TX transaction                (Write only)
+    // 0111 = PC high address of SG buffer for TX transaction               (Write only)
+    // 1000 = Transfer length for TX transaction                            (Read only) (ACK'd on read)
+    // 1001 = Offset/Last for TX transaction                                (Read only)
+    // 1010 = Link rate, link width, bus master enabled, number of channels (Read only)
+    // 1011 = Interrupt vector 1                                            (Read only) (Reset on read)
+    // 1100 = Interrupt vector 2                                            (Read only) (Reset on read)
+    // 1101 = Transferred length for RX transaction                         (Read only) (ACK'd on read)
+    // 1110 = Transferred length for TX transaction                         (Read only) (ACK'd on read)
+    // 1111 = Name of FPGA                                                  (Read only)
+
+    wire [31:0]                                __wRdMemory[C_ADDR_RANGE-1:0];
+    wire [32*C_ADDR_RANGE-1:0]                 _wRdMemory;
+    wire [C_PCI_DATA_WIDTH-1:0]                wRdMemory[C_ARRAY_LENGTH-1:0];
+
+    wire [C_PCI_DATA_WIDTH-1:0]                wRxrData;
+    wire                                       wRxrDataValid;
+    wire                                       wRxrDataStartFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]     wRxrDataStartOffset;
+    wire [`SIG_FBE_W-1:0]                      wRxrMetaFdwbe;
+    wire                                       wRxrDataEndFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]     wRxrDataEndOffset;
+    wire [`SIG_LBE_W-1:0]                      wRxrMetaLdwbe;
+    wire [`SIG_TC_W-1:0]                       wRxrMetaTc;
+    wire [`SIG_ATTR_W-1:0]                     wRxrMetaAttr;
+    wire [`SIG_TAG_W-1:0]                      wRxrMetaTag;
+    wire [`SIG_TYPE_W-1:0]                     wRxrMetaType;
+    wire [`SIG_ADDR_W-1:0]                     wRxrMetaAddr;
+    wire [`SIG_REQID_W-1:0]                    wRxrMetaRequesterId;
+    wire [`SIG_LEN_W-1:0]                      wRxrMetaLength;
+    
+    wire [C_PCI_DATA_WIDTH-1:0]                wTxcData;
+    wire                                       wTxcDataValid;
+    wire                                       wTxcDataStartFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]     wTxcDataStartOffset;
+    wire [`SIG_FBE_W-1:0]                      wTxcMetaFdwbe;
+    wire                                       wTxcDataEndFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]     wTxcDataEndOffset;
+    wire [`SIG_LBE_W-1:0]                      wTxcMetaLdwbe;
+    wire [`SIG_LOWADDR_W-1:0]                  wTxcMetaAddr;
+    wire [`SIG_TYPE_W-1:0]                     wTxcMetaType;
+    wire [`SIG_LEN_W-1:0]                      wTxcMetaLength;
+    wire [`SIG_BYTECNT_W-1:0]                  wTxcMetaByteCount;
+    wire [`SIG_TAG_W-1:0]                      wTxcMetaTag;
+    wire [`SIG_REQID_W-1:0]                    wTxcMetaRequesterId;
+    wire [`SIG_TC_W-1:0]                       wTxcMetaTc;
+    wire [`SIG_ATTR_W-1:0]                     wTxcMetaAttr;
+    wire                                       wTxcMetaEp;
+    wire                                       wTxcDataReady;
+
+    wire [clog2s(C_NUM_CHNL)-1:0]              wReqChnl;
+    wire [C_FIELDS_WIDTH-1:0]                  wReqField;
+    wire [(1<<C_FIELDS_WIDTH)-1:0]             wReqFieldDemux;
+
+    wire [C_NUM_CHNL-1:0]                      wChnlSgrxLenValid;
+    wire [C_NUM_CHNL-1:0]                      wChnlSgrxAddrLowValid;
+    wire [C_NUM_CHNL-1:0]                      wChnlSgrxAddrHiValid;
+    wire [C_NUM_CHNL-1:0]                      wChnlSgtxLenValid;
+    wire [C_NUM_CHNL-1:0]                      wChnlSgtxAddrLowValid;
+    wire [C_NUM_CHNL-1:0]                      wChnlSgtxAddrHiValid;
+    wire [C_NUM_CHNL-1:0]                      wChnlRxLenValid;
+    wire [C_NUM_CHNL-1:0]                      wChnlRxOfflastValid;
+
+    wire [C_NUM_CHNL-1:0]                      wChnlTxLenReady;
+    wire [C_NUM_CHNL-1:0]                      wChnlTxOfflastReady;
+    wire [`SIG_CORESETTINGS_W-1:0]             wCoreSettings;
+    wire                                       wCoreSettingsReady;
+    wire [C_NUM_VECTORS - 1 : 0]               wInterVectorReady;
+    wire [C_NUM_CHNL-1:0]                      wChnlTxDoneReady;
+    wire [C_NUM_CHNL-1:0]                      wChnlRxDoneReady;
+    wire                                       wChnlNameReady;
+
+    wire [31:0]                                wChnlReqData;
+
+    genvar                                     addr;
+    genvar                                     channel;
+    genvar                                     vector;
+
+    assign wReqChnl = wRxrMetaAddr[(C_FIELDS_WIDTH + 2) +:clog2s(C_NUM_CHNL)];
+    assign wReqField = wRxrMetaAddr[2 +: C_FIELDS_WIDTH];
+    assign wChnlReqData[31:0] = wRxrData[32*wRxrDataStartOffset +: 32];
+    
+    /* verilator lint_off WIDTH */
+    assign __wRdMemory[`ADDR_CORESETTINGS] = CORE_SETTINGS;
+    assign __wRdMemory[`ADDR_INTR_VECTOR_0] = INTR_VECTOR[C_VECTOR_WIDTH*0 +: C_VECTOR_WIDTH];
+    assign __wRdMemory[`ADDR_INTR_VECTOR_1] = INTR_VECTOR[C_VECTOR_WIDTH*1 +: C_VECTOR_WIDTH];
+    assign __wRdMemory[`ADDR_FPGA_NAME] = {"    ",C_FPGA_NAME};
+    /* verilator lint_on WIDTH */
+    assign wTxcData = {{(C_PCI_DATA_WIDTH-32){1'b0}},__wRdMemory[{wReqChnl,wReqField}]};
+    assign wTxcDataValid = wRxrDataValid & wRxrMetaType == `TRLS_REQ_RD;
+    assign wTxcDataStartFlag = 1;
+    assign wTxcDataStartOffset = 0;
+    assign wTxcMetaFdwbe = 4'b1111;
+    assign wTxcDataEndFlag = 1;
+    assign wTxcDataEndOffset = 0;
+    assign wTxcMetaLdwbe = 4'b0000;
+    assign wTxcMetaAddr = wRxrMetaAddr[`SIG_LOWADDR_W-1:0];
+    assign wTxcMetaType = `TRLS_CPL_WD;
+    assign wTxcMetaLength = 1;
+    assign wTxcMetaByteCount = 4;
+    assign wTxcMetaTag = wRxrMetaTag;
+    assign wTxcMetaRequesterId = wRxrMetaRequesterId;
+    assign wTxcMetaTc = wRxrMetaTc;
+    assign wTxcMetaAttr = wRxrMetaAttr;
+    assign wTxcMetaEp = 0;
+
+    generate            
+        for(channel = 0; channel < C_NUM_CHNL ; channel = channel + 1) begin : gen__wRdMemory
+            
+            assign __wRdMemory[{channel[27:0] , `ADDR_TX_LEN}] = CHNL_TX_REQLEN[32*channel +: 32];
+            assign __wRdMemory[{channel[27:0] , `ADDR_TX_OFFLAST}] = CHNL_TX_OFFLAST[32*channel +: 32];
+            assign __wRdMemory[{channel[27:0] , `ADDR_RX_LEN_XFERD}] = CHNL_RX_DONELEN[32*channel +: 32];            
+            assign __wRdMemory[{channel[27:0] , `ADDR_TX_LEN_XFERD}] = CHNL_TX_DONELEN[32*channel +: 32];
+        end
+        for(addr = 0 ; addr < C_ADDR_RANGE ; addr = addr + 1) begin : gen_wRdMemory
+            assign _wRdMemory[(addr*32) +: 32] = __wRdMemory[addr];
+        end
+        for(addr = 0 ; addr < C_ARRAY_LENGTH ; addr = addr + 1) begin : genwRdMemory
+            assign wRdMemory[addr]  = _wRdMemory[(addr*C_PCI_DATA_WIDTH) +: C_PCI_DATA_WIDTH];
+        end
+    endgenerate
+
+    assign wChnlNameReady = wReqFieldDemux[`ADDR_FPGA_NAME];
+    assign wCoreSettingsReady = wReqFieldDemux[`ADDR_CORESETTINGS];
+    assign wInterVectorReady[0] = wReqFieldDemux[`ADDR_INTR_VECTOR_0];
+    assign wInterVectorReady[1] = wReqFieldDemux[`ADDR_INTR_VECTOR_1];
+    assign TXC_META_VALID = TXC_DATA_VALID;
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_INPUT_STAGES),
+          .C_WIDTH                      (C_RXR_REGISTER_WIDTH),
+          .C_USE_MEMORY                 (0)
+          /*AUTOINSTPARAM*/)
+    rxr_input_register
+        (// Outputs
+         .WR_DATA_READY                 (),// Unconnected
+         .RD_DATA                       ({wRxrData,
+                                          wRxrDataStartFlag, wRxrDataStartOffset, wRxrMetaFdwbe,
+                                          wRxrDataEndFlag, wRxrDataEndOffset, wRxrMetaLdwbe,
+                                          wRxrMetaAddr, wRxrMetaType, wRxrMetaLength, 
+                                          wRxrMetaTag, wRxrMetaRequesterId, wRxrMetaTc, wRxrMetaAttr}),
+         .RD_DATA_VALID                 (wRxrDataValid),
+         // Inputs
+         .WR_DATA                       ({RXR_DATA, 
+                                          RXR_DATA_START_FLAG, RXR_DATA_START_OFFSET, RXR_META_FDWBE,
+                                          RXR_DATA_END_FLAG, RXR_DATA_END_OFFSET, RXR_META_LDWBE,
+                                          RXR_META_ADDR, RXR_META_TYPE, RXR_META_LENGTH,
+                                          RXR_META_TAG, RXR_META_REQUESTER_ID, RXR_META_TC, RXR_META_ATTR}),
+         .WR_DATA_VALID                 (RXR_DATA_VALID),
+         .RD_DATA_READY                 (1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    demux
+        #(
+          // Parameters
+          .C_OUTPUTS                    (1<<C_FIELDS_WIDTH),
+          .C_WIDTH                      (1)
+          /*AUTOINSTPARAM*/)
+    field_demux
+        (
+         // Outputs
+         .RD_DATA                      (wReqFieldDemux),
+         // Inputs
+         .WR_DATA                      (wRxrDataValid),
+         .WR_SEL                       (wReqField)
+         /*AUTOINST*/);
+
+    demux
+        #(
+          // Parameters
+          .C_OUTPUTS                    (C_NUM_CHNL),
+          .C_WIDTH                      (1)
+          /*AUTOINSTPARAM*/)
+    tx_len_ready_demux
+        (
+         // Outputs
+         .RD_DATA                      (wChnlTxLenReady),
+         // Inputs
+         .WR_DATA                      (wReqFieldDemux[`ADDR_TX_LEN]),
+         .WR_SEL                       (wReqChnl)
+         /*AUTOINST*/);
+
+    demux
+        #(
+          // Parameters
+          .C_OUTPUTS                    (C_NUM_CHNL),
+          .C_WIDTH                      (1)
+          /*AUTOINSTPARAM*/)
+    tx_offlast_ready_demux
+        (
+         // Outputs
+         .RD_DATA                      (wChnlTxOfflastReady),
+         // Inputs
+         .WR_DATA                      (wReqFieldDemux[`ADDR_TX_OFFLAST]),
+         .WR_SEL                       (wReqChnl)
+         /*AUTOINST*/);
+    
+    demux
+        #(
+          // Parameters
+          .C_OUTPUTS                    (C_NUM_CHNL),
+          .C_WIDTH                      (1)
+          /*AUTOINSTPARAM*/)
+    rxdone_demux
+        (
+         // Outputs
+         .RD_DATA                      (wChnlRxDoneReady),
+         // Inputs
+         .WR_DATA                      (wReqFieldDemux[`ADDR_RX_LEN_XFERD]),
+         .WR_SEL                       (wReqChnl)
+         /*AUTOINST*/);
+
+    demux
+        #(
+          // Parameters
+          .C_OUTPUTS                    (C_NUM_CHNL),
+          .C_WIDTH                      (1)
+          /*AUTOINSTPARAM*/)
+    txdone_demux
+        (
+         // Outputs
+         .RD_DATA                      (wChnlTxDoneReady),
+         // Inputs
+         .WR_DATA                      (wReqFieldDemux[`ADDR_TX_LEN_XFERD]),
+         .WR_SEL                       (wReqChnl)
+         /*AUTOINST*/);
+    demux
+        #(
+          // Parameters
+          .C_OUTPUTS                    (C_NUM_CHNL),
+          .C_WIDTH                      (1)
+          /*AUTOINSTPARAM*/)
+    rx_len_demux
+        (
+         // Outputs
+         .RD_DATA                      (wChnlRxLenValid),
+         // Inputs
+         .WR_DATA                      (wReqFieldDemux[`ADDR_RX_LEN]),
+         .WR_SEL                       (wReqChnl)
+         /*AUTOINST*/);
+
+    demux
+        #(
+          // Parameters
+          .C_OUTPUTS                    (C_NUM_CHNL),
+          .C_WIDTH                      (1)
+          /*AUTOINSTPARAM*/)
+    rx_offlast_demux
+        (
+         // Outputs
+         .RD_DATA                      (wChnlRxOfflastValid),
+         // Inputs
+         .WR_DATA                      (wReqFieldDemux[`ADDR_RX_OFFLAST]),
+         .WR_SEL                       (wReqChnl)
+         /*AUTOINST*/);
+
+    demux
+        #(
+          // Parameters
+          .C_OUTPUTS                    (C_NUM_CHNL),
+          .C_WIDTH                      (1)
+          /*AUTOINSTPARAM*/)
+    sgtx_addrhi_demux
+        (
+         // Outputs
+         .RD_DATA                      (wChnlSgtxAddrHiValid),
+         // Inputs
+         .WR_DATA                      (wReqFieldDemux[`ADDR_SGTX_ADDRHI]),
+         .WR_SEL                       (wReqChnl)
+         /*AUTOINST*/);
+
+    demux
+        #(
+          // Parameters
+          .C_OUTPUTS                    (C_NUM_CHNL),
+          .C_WIDTH                      (1)
+          /*AUTOINSTPARAM*/)
+    sgtx_addrlo_demux
+        (
+         // Outputs
+         .RD_DATA                      (wChnlSgtxAddrLowValid),
+         // Inputs
+         .WR_DATA                      (wReqFieldDemux[`ADDR_SGTX_ADDRLO]),
+         .WR_SEL                       (wReqChnl)
+         /*AUTOINST*/);
+
+    demux
+        #(
+          // Parameters
+          .C_OUTPUTS                    (C_NUM_CHNL),
+          .C_WIDTH                      (1)
+          /*AUTOINSTPARAM*/)
+    sgtxlen_demux
+        (
+         // Outputs
+         .RD_DATA                      (wChnlSgtxLenValid),
+         // Inputs
+         .WR_DATA                      (wReqFieldDemux[`ADDR_SGTX_LEN]),
+         .WR_SEL                       (wReqChnl)
+         /*AUTOINST*/);
+
+    demux
+        #(
+          // Parameters
+          .C_OUTPUTS                    (C_NUM_CHNL),
+          .C_WIDTH                      (1)
+          /*AUTOINSTPARAM*/)
+    sgrx_addrhi_demux
+        (
+         // Outputs
+         .RD_DATA                      (wChnlSgrxAddrHiValid),
+         // Inputs
+         .WR_DATA                      (wReqFieldDemux[`ADDR_SGRX_ADDRHI]),
+         .WR_SEL                       (wReqChnl)
+         /*AUTOINST*/);
+
+    demux
+        #(
+          // Parameters
+          .C_OUTPUTS                    (C_NUM_CHNL),
+          .C_WIDTH                      (1)
+          /*AUTOINSTPARAM*/)
+    sgrx_addrlo_demux
+        (
+         // Outputs
+         .RD_DATA                      (wChnlSgrxAddrLowValid),
+         // Inputs
+         .WR_DATA                      (wReqFieldDemux[`ADDR_SGRX_ADDRLO]),
+         .WR_SEL                       (wReqChnl)
+         /*AUTOINST*/);
+
+    demux
+        #(
+          // Parameters
+          .C_OUTPUTS                    (C_NUM_CHNL),
+          .C_WIDTH                      (1)
+          /*AUTOINSTPARAM*/)
+    sgrxlen_demux
+        (
+         // Outputs
+         .RD_DATA                      (wChnlSgrxLenValid),
+         // Inputs
+         .WR_DATA                      (wReqFieldDemux[`ADDR_SGRX_LEN]),
+         .WR_SEL                       (wReqChnl)
+         /*AUTOINST*/);
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_OUTPUT_STAGES),
+          .C_WIDTH                      (12*C_NUM_CHNL + C_NUM_VECTORS + 2 + 32),
+          .C_USE_MEMORY                 (0)
+          /*AUTOINSTPARAM*/)
+    chnl_output_register
+        (
+         // Outputs
+         .WR_DATA_READY                 (),// Unconnected
+         .RD_DATA                       ({CHNL_TX_LEN_READY, CHNL_TX_OFFLAST_READY, CORE_SETTINGS_READY,
+                                          INTR_VECTOR_READY, CHNL_TX_DONE_READY, CHNL_RX_DONE_READY, 
+                                          CHNL_NAME_READY,CHNL_SGRX_LEN_VALID, CHNL_SGRX_ADDRLO_VALID, CHNL_SGRX_ADDRHI_VALID,
+                                          CHNL_SGTX_LEN_VALID, CHNL_SGTX_ADDRLO_VALID, CHNL_SGTX_ADDRHI_VALID,
+                                          CHNL_RX_LEN_VALID, CHNL_RX_OFFLAST_VALID,
+                                          CHNL_REQ_DATA}),
+         .RD_DATA_VALID                 (),
+         // Inputs
+         .WR_DATA                       ({wChnlTxLenReady, wChnlTxOfflastReady, wCoreSettingsReady,
+                                          wInterVectorReady, wChnlTxDoneReady, wChnlRxDoneReady, 
+                                          wChnlNameReady,wChnlSgrxLenValid,wChnlSgrxAddrLowValid,wChnlSgrxAddrHiValid,
+                                          wChnlSgtxLenValid,wChnlSgtxAddrLowValid,wChnlSgtxAddrHiValid,
+                                          wChnlRxLenValid,wChnlRxOfflastValid,
+                                          wChnlReqData}),
+         .WR_DATA_VALID                 (1),
+         .RD_DATA_READY                 (1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_OUTPUT_STAGES),
+          .C_WIDTH                      (C_TXC_REGISTER_WIDTH),
+          .C_USE_MEMORY                 (0)
+          /*AUTOINSTPARAM*/)
+    txc_output_register
+        (
+         // Outputs
+         .WR_DATA_READY                 (),// Unconnected
+         .RD_DATA                       ({TXC_DATA, 
+                                          TXC_DATA_START_FLAG, TXC_DATA_START_OFFSET, TXC_META_FDWBE,
+                                          TXC_DATA_END_FLAG, TXC_DATA_END_OFFSET, TXC_META_LDWBE,
+                                          TXC_META_ADDR, TXC_META_TYPE, TXC_META_LENGTH, TXC_META_BYTE_COUNT,
+                                          TXC_META_TAG, TXC_META_REQUESTER_ID, TXC_META_TC, TXC_META_ATTR,
+                                          TXC_META_EP}),
+         .RD_DATA_VALID                 (TXC_DATA_VALID),
+         // Inputs
+         .WR_DATA                       ({wTxcData, 
+                                          wTxcDataStartFlag, wTxcDataStartOffset, wTxcMetaFdwbe,
+                                          wTxcDataEndFlag, wTxcDataEndOffset, wTxcMetaLdwbe,
+                                          wTxcMetaAddr, wTxcMetaType, wTxcMetaLength, wTxcMetaByteCount,
+                                          wTxcMetaTag, wTxcMetaRequesterId, wTxcMetaTc, wTxcMetaAttr,
+                                          wTxcMetaEp}),
+         .WR_DATA_VALID                 (wTxcDataValid),
+         .RD_DATA_READY                 (TXC_DATA_READY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../common/")
+// End:
diff --git a/fpga/riffa_hdl/reorder_queue.v b/fpga/riffa_hdl/reorder_queue.v
new file mode 100644
index 0000000..9c44322
--- /dev/null
+++ b/fpga/riffa_hdl/reorder_queue.v
@@ -0,0 +1,303 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    19:27:32 06/14/2012 
+// Design Name: 
+// Module Name:    reorder_queue
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description:
+// Reorders downstream TLPs to output in increasing tag sequence. Input packets
+// are stored in RAM and then read out when all previous sequence numbers have
+// arrived and been read out. This module also provides the next available tag
+// for the TX engine to use when sending memory request TLPs.
+//
+// Dependencies: 
+// reorder_queue_input.v
+// reorder_queue_output.v
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+`include "trellis.vh"
+`timescale 1ns / 1ps
+module reorder_queue 
+    #(
+      parameter C_PCI_DATA_WIDTH = 9'd128,
+      parameter C_NUM_CHNL = 4'd12,
+      parameter C_MAX_READ_REQ_BYTES = 512,            // Max size of read requests (in bytes)
+      parameter C_TAG_WIDTH = 5,                       // Number of outstanding requests 
+      // Local parameters
+      parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
+      parameter C_PCI_DATA_COUNT_WIDTH = clog2(C_PCI_DATA_WORD+1),
+      parameter C_NUM_TAGS = 2**C_TAG_WIDTH,
+      parameter C_DW_PER_TAG = C_MAX_READ_REQ_BYTES/4,
+      parameter C_TAG_DW_COUNT_WIDTH = clog2s(C_DW_PER_TAG+1),
+      parameter C_DATA_ADDR_STRIDE_WIDTH = clog2s(C_DW_PER_TAG/C_PCI_DATA_WORD), // div by C_PCI_DATA_WORD b/c there are C_PCI_DATA_WORD RAMs
+      parameter C_DATA_ADDR_WIDTH = C_TAG_WIDTH + C_DATA_ADDR_STRIDE_WIDTH
+      )
+    (
+     input                                            CLK, // Clock
+     input                                            RST, // Synchronous reset
+     input                                            VALID, // Valid input packet
+     input [C_PCI_DATA_WIDTH-1:0]                     DATA, // Input packet payload
+     input [(C_PCI_DATA_WIDTH/32)-1:0]                DATA_EN, // Input packet payload data enable
+     input                                            DATA_START_FLAG, // Input packet payload
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]          DATA_START_OFFSET, // Input packet payload data enable count
+     input                                            DATA_END_FLAG, // Input packet payload
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]          DATA_END_OFFSET, // Input packet payload data enable count
+     input                                            DONE, // Input packet done
+     input                                            ERR, // Input packet has error
+     input [C_TAG_WIDTH-1:0]                          TAG, // Input packet tag (external tag)
+
+     input [5:0]                                      INT_TAG, // Internal tag to exchange with external
+     input                                            INT_TAG_VALID, // High to signal tag exchange 
+     output [C_TAG_WIDTH-1:0]                         EXT_TAG, // External tag to provide in exchange for internal tag
+     output                                           EXT_TAG_VALID, // High to signal external tag is valid
+
+     output [C_PCI_DATA_WIDTH-1:0]                    ENG_DATA, // Engine data 
+     output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] MAIN_DATA_EN, // Main data enable
+     output [C_NUM_CHNL-1:0]                          MAIN_DONE, // Main data complete
+     output [C_NUM_CHNL-1:0]                          MAIN_ERR, // Main data completed with error
+     output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_RX_DATA_EN, // Scatter gather for RX data enable
+     output [C_NUM_CHNL-1:0]                          SG_RX_DONE, // Scatter gather for RX data complete
+     output [C_NUM_CHNL-1:0]                          SG_RX_ERR, // Scatter gather for RX data completed with error
+     output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_TX_DATA_EN, // Scatter gather for TX data enable
+     output [C_NUM_CHNL-1:0]                          SG_TX_DONE, // Scatter gather for TX data complete
+     output [C_NUM_CHNL-1:0]                          SG_TX_ERR                             // Scatter gather for TX data completed with error
+     );
+
+
+    wire [(C_DATA_ADDR_WIDTH*C_PCI_DATA_WORD)-1:0]    wWrDataAddr;
+    wire [C_PCI_DATA_WIDTH-1:0]                       wWrData;
+    wire [C_PCI_DATA_WORD-1:0]                        wWrDataEn;
+
+    wire [C_TAG_WIDTH-1:0]                            wWrPktTag;
+    wire [C_TAG_DW_COUNT_WIDTH-1:0]                   wWrPktWords;
+    wire                                              wWrPktWordsLTE1;
+    wire                                              wWrPktWordsLTE2;
+    wire                                              wWrPktValid;
+    wire                                              wWrPktDone;
+    wire                                              wWrPktErr;
+
+    wire [C_DATA_ADDR_WIDTH-1:0]                      wRdDataAddr;
+    wire [C_PCI_DATA_WIDTH-1:0]                       wRdData;
+
+    wire [C_TAG_WIDTH-1:0]                            wRdPktTag;
+    wire [(1+1+1+1+C_TAG_DW_COUNT_WIDTH)-1:0]         wRdPktInfo;
+
+    wire [5:0]                                        wRdTagMap;
+
+    wire [C_NUM_TAGS-1:0]                             wFinish;
+    wire [C_NUM_TAGS-1:0]                             wClear;
+
+    reg [C_TAG_WIDTH-1:0]                             rPos=0;
+    reg                                               rValid=0;
+    reg [C_NUM_TAGS-1:0]                              rFinished=0;
+    reg [C_NUM_TAGS-1:0]                              rUse=0;
+    reg [C_NUM_TAGS-1:0]                              rUsing=0;
+
+    assign EXT_TAG = rPos;
+    assign EXT_TAG_VALID = rValid;
+
+    // Move through tag/slot/bucket space.
+    always @ (posedge CLK) begin
+        if (RST) begin
+            rPos <= #1 0;
+            rUse <= #1 0;
+            rValid <= #1 0;
+        end
+        else begin
+            if (INT_TAG_VALID & EXT_TAG_VALID) begin
+                rPos <= #1 rPos + 1'd1;
+                rUse <= #1 1<<rPos;
+                rValid <= #1 !rUsing[rPos + 1'd1];
+            end
+            else begin
+                rUse <= #1 0;
+                rValid <= #1 !rUsing[rPos];
+            end
+        end
+    end
+
+
+    // Update tag/slot/bucket status.
+    always @ (posedge CLK) begin
+        if (RST) begin
+            rUsing <= #1 0;
+            rFinished <= #1 0;
+        end
+        else begin
+            rUsing <= #1 (rUsing | rUse) & ~wClear;
+            rFinished <= #1 (rFinished | wFinish) & ~wClear;
+        end
+    end
+
+
+    genvar r;
+    generate
+        for (r = 0; r < C_PCI_DATA_WORD; r = r + 1) begin : rams
+            // RAMs for packet reordering.
+            (* RAM_STYLE="BLOCK" *)
+            ram_1clk_1w_1r 
+                 #(.C_RAM_WIDTH(32), 
+                   .C_RAM_DEPTH(C_NUM_TAGS*C_DW_PER_TAG/C_PCI_DATA_WORD)
+                   ) 
+            ram 
+                 (
+                  .CLK(CLK),
+                  .ADDRA(wWrDataAddr[C_DATA_ADDR_WIDTH*r +:C_DATA_ADDR_WIDTH]),
+                  .WEA(wWrDataEn[r]),
+                  .DINA(wWrData[32*r +:32]),
+                  .ADDRB(wRdDataAddr),
+                  .DOUTB(wRdData[32*r +:32])
+                  );
+        end
+    endgenerate
+
+
+    // RAM for bucket done, err, final DW count
+    (* RAM_STYLE="DISTRIBUTED" *)
+    ram_1clk_1w_1r 
+        #(.C_RAM_WIDTH(1 + 1 + 1 + 1 + C_TAG_DW_COUNT_WIDTH), 
+          .C_RAM_DEPTH(C_NUM_TAGS)) 
+    pktRam 
+        (
+         .CLK(CLK),
+         .ADDRA(wWrPktTag),
+         .WEA((wWrPktDone | wWrPktErr) & wWrPktValid),
+         .DINA({wWrPktDone, wWrPktErr, wWrPktWordsLTE2, wWrPktWordsLTE1, wWrPktWords}),
+         .ADDRB(wRdPktTag),
+         .DOUTB(wRdPktInfo)
+         );
+
+
+    // RAM for tag map
+    (* RAM_STYLE="DISTRIBUTED" *)
+    ram_1clk_1w_1r 
+        #(.C_RAM_WIDTH(6), 
+          .C_RAM_DEPTH(C_NUM_TAGS)) 
+    mapRam 
+        (
+         .CLK(CLK),
+         .ADDRA(rPos),
+         .WEA(INT_TAG_VALID & EXT_TAG_VALID),
+         .DINA(INT_TAG),
+         .ADDRB(wRdPktTag),
+         .DOUTB(wRdTagMap)
+         );
+
+
+    // Demux input data into the correct slot/bucket.
+    reorder_queue_input 
+        #(
+          .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
+          .C_TAG_WIDTH(C_TAG_WIDTH),
+          .C_TAG_DW_COUNT_WIDTH(C_TAG_DW_COUNT_WIDTH),
+          .C_DATA_ADDR_STRIDE_WIDTH(C_DATA_ADDR_STRIDE_WIDTH),
+          .C_DATA_ADDR_WIDTH(C_DATA_ADDR_WIDTH)
+          ) 
+    data_input 
+        (
+         .CLK(CLK),
+         .RST(RST),
+         .VALID(VALID),
+         .DATA_START_FLAG               (DATA_START_FLAG),
+         .DATA_START_OFFSET             (DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .DATA_END_FLAG                 (DATA_END_FLAG),
+         .DATA_END_OFFSET               (DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .DATA                          (DATA),
+         .DATA_EN                       (DATA_EN),
+         .DONE(DONE),
+         .ERR(ERR),
+         .TAG(TAG),
+         .TAG_FINISH(wFinish),
+         .TAG_CLEAR(wClear),
+         .STORED_DATA_ADDR(wWrDataAddr),
+         .STORED_DATA(wWrData),
+         .STORED_DATA_EN(wWrDataEn),
+         .PKT_VALID(wWrPktValid),
+         .PKT_TAG(wWrPktTag),
+         .PKT_WORDS(wWrPktWords),
+         .PKT_WORDS_LTE1(wWrPktWordsLTE1),
+         .PKT_WORDS_LTE2(wWrPktWordsLTE2),
+         .PKT_DONE(wWrPktDone),
+         .PKT_ERR(wWrPktErr)
+         );
+
+
+    // Output packets in increasing tag order.
+    reorder_queue_output 
+        #(
+          .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
+          .C_NUM_CHNL(C_NUM_CHNL),
+          .C_TAG_WIDTH(C_TAG_WIDTH),
+          .C_TAG_DW_COUNT_WIDTH(C_TAG_DW_COUNT_WIDTH),
+          .C_DATA_ADDR_STRIDE_WIDTH(C_DATA_ADDR_STRIDE_WIDTH),
+          .C_DATA_ADDR_WIDTH(C_DATA_ADDR_WIDTH)
+          ) 
+    data_output 
+        (
+         .CLK(CLK),
+         .RST(RST),
+         .DATA_ADDR(wRdDataAddr),
+         .DATA(wRdData),
+         .TAG_FINISHED(rFinished),
+         .TAG_CLEAR(wClear),
+         .TAG(wRdPktTag),
+         .TAG_MAPPED(wRdTagMap),
+         .PKT_WORDS(wRdPktInfo[0 +:C_TAG_DW_COUNT_WIDTH]),
+         .PKT_WORDS_LTE1(wRdPktInfo[C_TAG_DW_COUNT_WIDTH]),
+         .PKT_WORDS_LTE2(wRdPktInfo[C_TAG_DW_COUNT_WIDTH+1]),
+         .PKT_ERR(wRdPktInfo[C_TAG_DW_COUNT_WIDTH+2]),
+         .PKT_DONE(wRdPktInfo[C_TAG_DW_COUNT_WIDTH+3]),
+         .ENG_DATA(ENG_DATA),
+         .MAIN_DATA_EN(MAIN_DATA_EN),
+         .MAIN_DONE(MAIN_DONE),
+         .MAIN_ERR(MAIN_ERR),
+         .SG_RX_DATA_EN(SG_RX_DATA_EN),
+         .SG_RX_DONE(SG_RX_DONE),
+         .SG_RX_ERR(SG_RX_ERR),
+         .SG_TX_DATA_EN(SG_TX_DATA_EN),
+         .SG_TX_DONE(SG_TX_DONE),
+         .SG_TX_ERR(SG_TX_ERR)
+         );
+endmodule
diff --git a/fpga/riffa_hdl/reorder_queue_input.v b/fpga/riffa_hdl/reorder_queue_input.v
new file mode 100644
index 0000000..e3a4af5
--- /dev/null
+++ b/fpga/riffa_hdl/reorder_queue_input.v
@@ -0,0 +1,330 @@
+`include "trellis.vh"
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    19:27:32 06/14/2012 
+// Design Name: 
+// Module Name:    reorder_queue_input
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description:
+// Demuxes input TLPs into the appropriate slot/bucket/RAM-position according 
+// to its tag.
+//
+// Dependencies: 
+// reorder_queue.v
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module reorder_queue_input 
+    #(
+	  parameter C_PCI_DATA_WIDTH = 9'd128,
+	  parameter C_TAG_WIDTH = 5, 											// Number of outstanding requests 
+	  parameter C_TAG_DW_COUNT_WIDTH = 8,									// Width of max count DWs per packet
+	  parameter C_DATA_ADDR_STRIDE_WIDTH = 5,								// Width of max num stored data addr positions per tag
+	  parameter C_DATA_ADDR_WIDTH = 10,									// Width of stored data address
+	  // Local parameters
+	  parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
+	  parameter C_PCI_DATA_WORD_WIDTH = clog2s(C_PCI_DATA_WORD),
+	  parameter C_PCI_DATA_COUNT_WIDTH = clog2s(C_PCI_DATA_WORD+1),
+	  parameter C_NUM_TAGS = 2**C_TAG_WIDTH
+      )
+    (
+	 input                                            CLK, // Clock
+	 input                                            RST, // Synchronous reset
+	 input                                            VALID, // Valid input packet
+     input [C_PCI_DATA_WIDTH-1:0]                     DATA, // Input packet payload data enable
+     input [(C_PCI_DATA_WIDTH/32)-1:0]                DATA_EN, // Input packet payload data enable
+     input                                            DATA_START_FLAG, // Input packet payload
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]          DATA_START_OFFSET, // Input packet payload data enable count
+     input                                            DATA_END_FLAG, // Input packet payload
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]          DATA_END_OFFSET, // Input packet payload data enable count
+	 input                                            DONE, // Input packet done
+	 input                                            ERR, // Input packet has error
+	 input [C_TAG_WIDTH-1:0]                          TAG, // Input packet tag (external tag)
+
+	 output [C_NUM_TAGS-1:0]                          TAG_FINISH, // Bitmap of tags to finish
+	 input [C_NUM_TAGS-1:0]                           TAG_CLEAR, // Bitmap of tags to clear
+
+	 output [(C_DATA_ADDR_WIDTH*C_PCI_DATA_WORD)-1:0] STORED_DATA_ADDR, // Address of stored packet data for RAMs
+	 output [C_PCI_DATA_WIDTH-1:0]                    STORED_DATA, // Stored packet data for RAMs
+	 output [C_PCI_DATA_WORD-1:0]                     STORED_DATA_EN, // Stored packet data enable for RAMs
+	 output                                           PKT_VALID, // Valid flag for packet data
+	 output [C_TAG_WIDTH-1:0]                         PKT_TAG, // Tag for stored packet data
+	 output [C_TAG_DW_COUNT_WIDTH-1:0]                PKT_WORDS, // Total count of stored packet payload in DWs
+	 output                                           PKT_WORDS_LTE1, // True if total count of stored packet payload is <= 4 DWs
+	 output                                           PKT_WORDS_LTE2, // True if total count of stored packet payload is <= 8 DWs
+	 output                                           PKT_DONE, // Stored packet done flag
+	 output                                           PKT_ERR														// Stored packet error flag
+     );
+
+    wire [C_PCI_DATA_COUNT_WIDTH-1:0]                 wDECount;
+    wire [C_PCI_DATA_WORD-1:0]                        wDE;
+    wire [C_PCI_DATA_WIDTH-1:0]                       wData;
+    wire [C_PCI_DATA_WORD-1:0]                        wStartMask;
+    wire [C_PCI_DATA_WORD-1:0]                        wEndMask;
+
+    reg [5:0]                                         rValid=0;
+    reg [(C_PCI_DATA_WIDTH*5)-1:0]                    rData=0;
+    reg [(C_PCI_DATA_WORD*3)-1:0]                     rDE=0;
+    reg [(C_PCI_DATA_COUNT_WIDTH*2)-1:0]              rDECount=0;
+    reg [5:0]                                         rDone=0;
+    reg [5:0]                                         rErr=0;
+    reg [(C_TAG_WIDTH*6)-1:0]                         rTag=0;
+
+    reg [C_PCI_DATA_WORD-1:0]                         rDEShift=0;
+    reg [(C_PCI_DATA_WORD*2)-1:0]                     rDEShifted=0;
+
+    reg                                               rCountValid=0;
+    reg [C_NUM_TAGS-1:0]                              rCountRst=0;
+    reg [C_NUM_TAGS-1:0]                              rValidCount=0;
+
+    reg                                               rUseCurrCount=0;
+    reg                                               rUsePrevCount=0;
+    reg [C_TAG_DW_COUNT_WIDTH-1:0]                    rPrevCount=0;
+    reg [C_TAG_DW_COUNT_WIDTH-1:0]                    rCount=0;
+    wire [C_TAG_DW_COUNT_WIDTH-1:0]                   wCount;
+    wire [C_TAG_DW_COUNT_WIDTH-1:0]                   wCountClr = wCount & {C_TAG_DW_COUNT_WIDTH{rCountValid}};
+    reg [(C_TAG_DW_COUNT_WIDTH*3)-1:0]                rWords=0;
+    reg [C_PCI_DATA_WORD_WIDTH-1:0]                   rShift=0;
+    reg [C_PCI_DATA_WORD_WIDTH-1:0]                   rShifted=0;
+
+    reg                                               rPosValid=0;
+    reg [C_NUM_TAGS-1:0]                              rPosRst=0;
+    reg [C_NUM_TAGS-1:0]                              rValidPos=0;
+
+    reg                                               rUseCurrPos=0;
+    reg                                               rUsePrevPos=0;
+    reg [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] rPrevPos=0;
+    reg [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] rPosNow=0;
+    reg [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] rPos=0;
+    wire [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] wPos;
+    wire [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] wPosClr = wPos & {C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD{rPosValid}};
+
+    reg [(C_DATA_ADDR_WIDTH*C_PCI_DATA_WORD)-1:0]         rAddr=0;
+    reg [(C_PCI_DATA_WORD_WIDTH+5)-1:0]                   rShiftUp=0;
+    reg [(C_PCI_DATA_WORD_WIDTH+5)-1:0]                   rShiftDown=0;
+    reg [C_DATA_ADDR_WIDTH-1:0]                           rBaseAddr=0;
+    reg [C_PCI_DATA_WIDTH-1:0]                            rDataShifted=0;
+    reg                                                   rLTE1Pkt=0;
+    reg                                                   rLTE2Pkt=0;
+
+    reg [C_NUM_TAGS-1:0]                                  rFinish=0;
+
+    wire [31:0]                                           wZero=32'd0;
+    integer                                               i;
+    
+    assign wDE = DATA_EN >> (DATA_START_FLAG ? DATA_START_OFFSET : 0);/* TODO: Could move this to the RX Engine*/
+    assign wData = DATA >> (DATA_START_FLAG ? {DATA_START_OFFSET,5'b0} : 0);
+    generate
+        if(C_PCI_DATA_WIDTH == 32) begin
+            assign wDECount = VALID ? 1 : 0;
+        end
+        if(C_PCI_DATA_WIDTH == 64) begin
+            assign wDECount = VALID ? DATA_EN[1] + DATA_EN[0] : 0;
+        end
+        if(C_PCI_DATA_WIDTH == 128) begin
+            assign wDECount = VALID ? DATA_EN[3] + DATA_EN[2] + DATA_EN[1] + DATA_EN[0] : 0;
+        end
+        if(C_PCI_DATA_WIDTH == 256) begin
+            assign wDECount = VALID ? DATA_EN[7] + DATA_EN[6] + DATA_EN[5] + DATA_EN[4] +
+                              DATA_EN[3] + DATA_EN[2] + DATA_EN[1] + DATA_EN[0] : 0;
+        end
+    endgenerate
+    
+    assign TAG_FINISH = rFinish;
+
+    assign STORED_DATA_ADDR = rAddr;
+    assign STORED_DATA = rDataShifted;
+    assign STORED_DATA_EN = rDEShifted[1*C_PCI_DATA_WORD +:C_PCI_DATA_WORD];
+
+    assign PKT_VALID = rValid[5];
+    assign PKT_TAG = rTag[5*C_TAG_WIDTH +:C_TAG_WIDTH];
+    assign PKT_WORDS = rWords[2*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH];
+    assign PKT_WORDS_LTE1 = rLTE1Pkt;
+    assign PKT_WORDS_LTE2 = rLTE2Pkt;
+    assign PKT_DONE = rDone[5];
+    assign PKT_ERR = rErr[5];
+
+
+    // Pipeline the input and intermediate data
+    always @ (posedge CLK) begin
+	    if (RST) begin
+		    rValid <= #1 0;
+		    rTag <= #1 0;
+	    end
+	    else begin
+		    rValid <= #1 (rValid<<1) | VALID;
+		    rTag <= #1 (rTag<<C_TAG_WIDTH) | TAG;
+	    end
+	    rData <= #1 (rData<<C_PCI_DATA_WIDTH) | wData;
+	    rDE <= #1 (rDE<<C_PCI_DATA_WORD) | wDE;//DATA_EN;
+	    rDECount <= #1 (rDECount<<C_PCI_DATA_COUNT_WIDTH) | wDECount;//DATA_EN_COUNT;
+	    rDone <= #1 (rDone<<1) | DONE;
+	    rErr <= #1 (rErr<<1) | ERR;
+	    
+	    rDEShifted <= #1 (rDEShifted<<C_PCI_DATA_WORD) | rDEShift;
+	    rWords <= #1 (rWords<<C_TAG_DW_COUNT_WIDTH) | rCount;
+	    rShifted <= #1 (rShifted<<C_PCI_DATA_WORD_WIDTH) | rShift;
+    end
+
+
+    // Input processing pipeline
+    always @ (posedge CLK) begin
+	    // STAGE 0: Register the incoming data
+
+	    // STAGE 1: Request existing count from RAM
+	    // To cover the gap b/t reads and writes to RAM, next cycle we might need 
+	    // to use the existing or even the previous rCount value if the tags match.
+	    rUseCurrCount <= #1 (rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[1*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[1]);
+	    rUsePrevCount <= #1 (rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[2]);
+	    rPrevCount <= #1 rCount;
+	    // See if we need to reset the count
+	    rCountValid <= #1 (RST ? 1'd0 : rCountRst>>rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]);
+	    rValidCount <= #1 (RST ? 0 : rValid[0]<<rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]);
+	    
+	    // STAGE 2: Calculate new count (saves next cycle)
+	    if (rUseCurrCount) begin
+		    rShift <= #1 rCount[0 +:C_PCI_DATA_WORD_WIDTH];
+		    rCount <= #1 rCount + rDECount[1*C_PCI_DATA_COUNT_WIDTH +:C_PCI_DATA_COUNT_WIDTH];
+	    end
+	    else if (rUsePrevCount) begin
+		    rShift <= #1 rPrevCount[0 +:C_PCI_DATA_WORD_WIDTH];
+		    rCount <= #1 rPrevCount + rDECount[1*C_PCI_DATA_COUNT_WIDTH +:C_PCI_DATA_COUNT_WIDTH];
+	    end
+	    else begin
+		    rShift <= #1 wCountClr[0 +:C_PCI_DATA_WORD_WIDTH];
+		    rCount <= #1 wCountClr + rDECount[1*C_PCI_DATA_COUNT_WIDTH +:C_PCI_DATA_COUNT_WIDTH];
+	    end
+	    
+	    // STAGE 3: Request existing positions from RAM
+	    // Barrel shift the DE
+	    rDEShift <= #1 (rDE[2*C_PCI_DATA_WORD +:C_PCI_DATA_WORD]<<rShift) | 
+		            (rDE[2*C_PCI_DATA_WORD +:C_PCI_DATA_WORD]>>(C_PCI_DATA_WORD-rShift));
+	    // To cover the gap b/t reads and writes to RAM, next cycle we might need 
+	    // to use the existing or even the previous rPos values if the tags match.
+	    rUseCurrPos <= #1 (rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[3*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[3]);
+	    rUsePrevPos <= #1 (rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[4]);
+	    for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
+		    rPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1 
+			     (RST ? wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] : rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);
+	    end
+	    // See if we need to reset the positions
+	    rPosValid <= #1 (RST ? 1'd0 : rPosRst>>rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]);
+	    rValidPos <= #1 (RST ? 0 : rValid[2]<<rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]);
+
+	    // STAGE 4: Calculate new positions (saves next cycle)
+	    if (rUseCurrPos) begin
+		    for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
+			    rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1 
+				     (RST ? 
+                      wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] : 
+                      rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);
+                
+			    rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1 
+				     (RST ? 
+                      wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] : 
+                      rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] + rDEShift[i]);
+		    end
+	    end
+	    else if (rUsePrevPos) begin
+		    for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
+			    rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1 
+				     (RST ? 
+                      wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] : 
+                      rPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);
+			    rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1 
+				     (RST ? 
+                      wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] : 
+                      rPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] + rDEShift[i]);
+		    end
+	    end
+	    else begin
+		    for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
+			    rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1 
+				     (RST ? 
+                      wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] : 
+                      wPosClr[i*C_DATA_ADDR_STRIDE_WIDTH +:C_DATA_ADDR_STRIDE_WIDTH]);
+			    rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1 
+				      (RST ? 
+                       wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] : 
+                       wPosClr[i*C_DATA_ADDR_STRIDE_WIDTH +:C_DATA_ADDR_STRIDE_WIDTH] + rDEShift[i]);
+		    end
+	    end
+	    // Calculate the base address offset
+	    rBaseAddr <= #1 rTag[3*C_TAG_WIDTH +:C_TAG_WIDTH]<<C_DATA_ADDR_STRIDE_WIDTH;
+	    // Calculate the shift amounts for barrel shifting payload data
+	    rShiftUp <= #1 rShifted[0*C_PCI_DATA_WORD_WIDTH +:C_PCI_DATA_WORD_WIDTH]<<5;
+	    rShiftDown <= #1 (C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0] - rShifted[0*C_PCI_DATA_WORD_WIDTH +:C_PCI_DATA_WORD_WIDTH])<<5;
+
+	    // STAGE 5: Prepare to write data, final info
+	    for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
+		    rAddr[C_DATA_ADDR_WIDTH*i +:C_DATA_ADDR_WIDTH] <= #1 
+			     rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] + rBaseAddr;
+	    end
+	    rDataShifted <= #1 (rData[4*C_PCI_DATA_WIDTH +:C_PCI_DATA_WIDTH]<<rShiftUp) | 
+		                (rData[4*C_PCI_DATA_WIDTH +:C_PCI_DATA_WIDTH]>>rShiftDown);
+	    rLTE1Pkt <= #1 (rWords[1*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH] <= C_PCI_DATA_WORD);
+	    rLTE2Pkt <= #1 (rWords[1*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH] <= (C_PCI_DATA_WORD*2));
+	    rFinish <= #1 (rValid[4] & (rDone[4] | rErr[4]))<<rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH];
+
+	    // STAGE 6: Write data, final info
+    end
+
+
+    // Reset the count and positions when needed
+    always @ (posedge CLK) begin
+	    if (RST) begin
+		    rCountRst <= #1 0;
+		    rPosRst <= #1 0;
+	    end
+	    else begin
+		    rCountRst <= #1 (rCountRst | rValidCount) & ~TAG_CLEAR;
+		    rPosRst <= #1 (rPosRst | rValidPos) & ~TAG_CLEAR;
+	    end
+    end
+
+
+    // RAM for counts
+    (* RAM_STYLE="DISTRIBUTED" *)
+    ram_1clk_1w_1r 
+        #(
+          .C_RAM_WIDTH(C_TAG_DW_COUNT_WIDTH), 
+          .C_RAM_DEPTH(C_NUM_TAGS)) 
+    countRam 
+        (
+	     .CLK(CLK),
+	     .ADDRA(rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]),
+	     .WEA(rValid[2]),
+	     .DINA(rCount),
+	     .ADDRB(rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]),
+	     .DOUTB(wCount)
+         );
+
+
+    // RAM for positions
+    (* RAM_STYLE="DISTRIBUTED" *)
+    ram_1clk_1w_1r 
+        #(
+          .C_RAM_WIDTH(C_PCI_DATA_WORD*C_DATA_ADDR_STRIDE_WIDTH), 
+          .C_RAM_DEPTH(C_NUM_TAGS)) 
+    posRam 
+        (
+	     .CLK(CLK),
+	     .ADDRA(rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH]),
+	     .WEA(rValid[4]),
+	     .DINA(rPos),
+	     .ADDRB(rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]),
+	     .DOUTB(wPos)
+         );
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "registers/" "../common/")
+// End:
diff --git a/fpga/riffa_hdl/reorder_queue_output.v b/fpga/riffa_hdl/reorder_queue_output.v
new file mode 100644
index 0000000..4db76ba
--- /dev/null
+++ b/fpga/riffa_hdl/reorder_queue_output.v
@@ -0,0 +1,291 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    19:27:32 06/14/2012 
+// Design Name: 
+// Module Name:    reorder_queue_output
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description:
+// Outputs stored TLPs in increasing tag order.
+//
+// Dependencies: 
+// reorder_queue.v
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+`include "trellis.vh"
+module reorder_queue_output #(
+    parameter C_PCI_DATA_WIDTH = 9'd128,
+    parameter C_NUM_CHNL = 4'd12,
+    parameter C_TAG_WIDTH = 5, 						// Number of outstanding requests 
+    parameter C_TAG_DW_COUNT_WIDTH = 8,				// Width of max count DWs per packet
+    parameter C_DATA_ADDR_STRIDE_WIDTH = 5,			// Width of max num stored data addr positions per tag
+    parameter C_DATA_ADDR_WIDTH = 10,				// Width of stored data address
+    // Local parameters
+    parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
+    parameter C_PCI_DATA_WORD_WIDTH = clog2s(C_PCI_DATA_WORD),
+    parameter C_PCI_DATA_COUNT_WIDTH = clog2s(C_PCI_DATA_WORD+1),
+    parameter C_NUM_TAGS = 2**C_TAG_WIDTH
+    )
+   (
+    input 					     CLK, // Clock
+    input 					     RST, // Synchronous reset
+    output [C_DATA_ADDR_WIDTH-1:0] 		     DATA_ADDR, // Address of stored packet data
+    input [C_PCI_DATA_WIDTH-1:0] 		     DATA, // Stored packet data
+    input [C_NUM_TAGS-1:0] 			     TAG_FINISHED, // Bitmap of finished tags
+    output [C_NUM_TAGS-1:0] 			     TAG_CLEAR, // Bitmap of tags to clear
+    output [C_TAG_WIDTH-1:0] 			     TAG, // Tag for which to retrieve packet data
+    input [5:0] 				     TAG_MAPPED, // Mapped tag (i.e. internal tag)
+    input [C_TAG_DW_COUNT_WIDTH-1:0] 		     PKT_WORDS, // Total count of packet payload in DWs
+    input 					     PKT_WORDS_LTE1, // True if total count of packet payload is <= 4 DWs
+    input 					     PKT_WORDS_LTE2, // True if total count of packet payload is <= 8 DWs
+    input 					     PKT_DONE, // Packet done flag
+    input 					     PKT_ERR, // Packet error flag
+
+    output [C_PCI_DATA_WIDTH-1:0] 		     ENG_DATA, // Engine data 
+    output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] MAIN_DATA_EN, // Main data enable
+    output [C_NUM_CHNL-1:0] 			     MAIN_DONE, // Main data complete
+    output [C_NUM_CHNL-1:0] 			     MAIN_ERR, // Main data completed with error
+    output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_RX_DATA_EN, // Scatter gather for RX data enable
+    output [C_NUM_CHNL-1:0] 			     SG_RX_DONE, // Scatter gather for RX data complete
+    output [C_NUM_CHNL-1:0] 			     SG_RX_ERR, // Scatter gather for RX data completed with error
+    output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_TX_DATA_EN, // Scatter gather for TX data enable
+    output [C_NUM_CHNL-1:0] 			     SG_TX_DONE, // Scatter gather for TX data complete
+    output [C_NUM_CHNL-1:0] 			     SG_TX_ERR								// Scatter gather for TX data completed with error
+    );
+
+
+   reg [1:0] 					     rState=0;
+   reg [C_DATA_ADDR_WIDTH-1:0] 			     rDataAddr=0;
+   reg [C_PCI_DATA_WIDTH-1:0] 			     rData=0;
+
+   reg 						     rTagFinished=0;
+   reg [C_NUM_TAGS-1:0] 			     rClear=0;
+
+   reg [C_TAG_WIDTH-1:0] 			     rTag=0;
+   reg [C_TAG_WIDTH-1:0] 			     rTagCurr=0;
+   wire [C_TAG_WIDTH-1:0] 			     wTagNext = rTag + 1'd1;
+
+   reg [5:0] 					     rShift;
+   reg 						     rDone=0;
+   reg 						     rDoneLast=0;
+   reg 						     rErr=0;
+   reg 						     rErrLast=0;
+   reg [C_PCI_DATA_COUNT_WIDTH-1:0] 		     rDE=0;
+   reg [C_TAG_DW_COUNT_WIDTH-1:0] 		     rWords=0;
+   reg 						     rLTE2Pkts=0;
+
+   reg [C_PCI_DATA_WIDTH-1:0] 			     rDataOut={C_PCI_DATA_WIDTH{1'b0}};
+   reg [(3*16*C_PCI_DATA_COUNT_WIDTH)-1:0] 	     rDEOut={3*16*C_PCI_DATA_COUNT_WIDTH{1'd0}};
+   reg [(3*16)-1:0] 				     rDoneOut={3*16{1'd0}};
+   reg [(3*16)-1:0] 				     rErrOut={3*16{1'd0}};
+
+
+   assign DATA_ADDR = rDataAddr;
+   assign TAG = rTag;
+   assign TAG_CLEAR = rClear;
+
+   assign ENG_DATA = rDataOut;
+
+   assign MAIN_DATA_EN = rDEOut[(0*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
+   assign MAIN_DONE = rDoneOut[(0*16) +:C_NUM_CHNL];
+   assign MAIN_ERR = rErrOut[(0*16) +:C_NUM_CHNL];
+
+   assign SG_RX_DATA_EN = rDEOut[(1*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
+   assign SG_RX_DONE = rDoneOut[(1*16) +:C_NUM_CHNL];
+   assign SG_RX_ERR = rErrOut[(1*16) +:C_NUM_CHNL];
+
+   assign SG_TX_DATA_EN = rDEOut[(2*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
+   assign SG_TX_DONE = rDoneOut[(2*16) +:C_NUM_CHNL];
+   assign SG_TX_ERR = rErrOut[(2*16) +:C_NUM_CHNL];
+
+
+   // Output completed data in increasing tag order, avoid stalls if possible
+   always @ (posedge CLK) begin
+      if (RST) begin
+	      rState <= #1 0;
+	      rTag <= #1 0;
+	      rDataAddr <= #1 0;
+	      rDone <= #1 0;
+	      rErr <= #1 0;
+	      rDE <= #1 0;
+	      rClear <= #1 0;
+	      rTagFinished <= #1 0;
+          rShift <= 0; // Added
+      end
+      else begin
+	 rTagFinished <= #1 TAG_FINISHED[rTag];
+	 case (rState)
+	   
+	   2'd0: begin // Request initial data and final info, output nothing
+	      rDone <= #1 0;
+	      rErr <= #1 0;
+	      rDE <= #1 0;
+	      rClear <= #1 0;
+	      if (rTagFinished) begin
+		 rTag <= #1 wTagNext;
+		 rTagCurr <= #1 rTag;
+		 rDataAddr <= #1 rDataAddr + 1'd1;
+		 rState <= #1 2'd2;
+	      end
+	      else begin
+		 rState <= #1 2'd0;
+	      end
+	   end
+
+	   2'd1: begin // Request initial data and final info, output last data
+	      rDone <= #1 rDoneLast;
+	      rErr <= #1 rErrLast;
+	      rDE <= #1 rWords[C_PCI_DATA_COUNT_WIDTH-1:0];
+	      rClear <= #1 1<<rTagCurr; // Clear the tag
+	      if (rTagFinished) begin
+		 rTag <= #1 wTagNext;
+		 rTagCurr <= #1 rTag;
+		 rDataAddr <= #1 rDataAddr + 1'd1;
+		 rState <= #1 2'd2;
+	      end
+	      else begin
+		 rState <= #1 2'd0;
+	      end
+	   end
+
+	   2'd2: begin // Initial data now available, output data
+	      rShift <= #1 TAG_MAPPED;
+	      rDoneLast <= #1 PKT_DONE;
+	      rErrLast <= #1 PKT_ERR;
+	      rWords <= #1 PKT_WORDS - C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
+	      rLTE2Pkts <= #1 (PKT_WORDS <= (C_PCI_DATA_WORD*3));
+	      if (PKT_WORDS_LTE1) begin // Guessed wrong, no addl data, need to reset
+		 rDone <= #1 PKT_DONE;
+		 rErr <= #1 PKT_ERR;
+		 rDE <= #1 PKT_WORDS[C_PCI_DATA_COUNT_WIDTH-1:0];
+		 rClear <= #1 1<<rTagCurr; // Clear the tag
+		 rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH; // rTag is already on the next
+		 rState <= #1 2'd0;
+	      end
+	      else if (PKT_WORDS_LTE2) begin // Guessed right, end of data, output last and continue
+		 rDone <= #1 0;
+		 rErr <= #1 0;
+		 rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
+		 rClear <= #1 0;
+		 rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH; // rTag is already on the next
+		 rState <= #1 2'd1;
+	      end
+	      else begin // Guessed right, more data, output it and continue
+		 rDone <= #1 0;
+		 rErr <= #1 0;
+		 rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
+		 rClear <= #1 0;
+		 rDataAddr <= #1 rDataAddr + 1'd1;
+		 rState <= #1 2'd3;
+	      end
+	   end
+
+	   2'd3: begin // Next data now available, output data
+	      rDone <= #1 0;
+	      rErr <= #1 0;
+	      rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
+	      rWords <= #1 rWords - C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
+	      rLTE2Pkts <= #1 (rWords <= (C_PCI_DATA_WORD*3));
+	      if (rLTE2Pkts) begin // End of data, output last and continue
+		 rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH; // rTag is already on the next
+		 rState <= #1 2'd1;
+	      end
+	      else begin // More data, output it and continue
+		 rDataAddr <= #1 rDataAddr + 1'd1;
+		 rState <= #1 2'd3;
+	      end
+	   end
+
+	 endcase
+      end
+   end
+
+
+   // Output the data
+   always @ (posedge CLK) begin
+      rData <= #1 DATA;
+      rDataOut <= #1 rData;
+      if (RST) begin
+	 rDEOut <= #1 0;
+	 rDoneOut <= #1 0;
+	 rErrOut <= #1 0;
+      end
+      else begin
+	 rDEOut <= #1 rDE<<(C_PCI_DATA_COUNT_WIDTH*rShift);
+	 rDoneOut <= #1 (rDone | rErr)<<rShift;
+	 rErrOut <= #1 rErr<<rShift;
+      end
+   end
+
+
+   /*
+    wire [35:0] wControl0;
+    chipscope_icon_1 cs_icon(
+    .CONTROL0(wControl0)
+    );
+
+    chipscope_ila_t8_512 a0(
+    .CLK(DVI_CLK), 
+    .CONTROL(wControl0), 
+    .TRIG0({wFifoFull, wFifoEmpty, rState, rPrevDVI_VS, DVI_DE, DVI_HS, DVI_VS}),
+    .DATA({457'd0,
+    rCount, // 21
+    rFrameCount, // 21
+    wCapture, // 1
+    RD_EN, // 1
+    RD_EMPTY, // 1
+    EOF, // 1
+    wPackerFull, // 1
+    wFifoFull, // 1
+    wFifoEmpty, // 1
+    rState, // 2
+    rPrevDVI_VS, // 1
+    DVI_DE, // 1
+    DVI_HS, // 1
+    DVI_VS}) // 1
+    );
+    */
+
+endmodule
diff --git a/fpga/riffa_hdl/riffa.v b/fpga/riffa_hdl/riffa.v
new file mode 100644
index 0000000..a3dc4c4
--- /dev/null
+++ b/fpga/riffa_hdl/riffa.v
@@ -0,0 +1,590 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`timescale 1ns/1ns
+module riffa
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_NUM_CHNL = 12,
+      parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes)
+      parameter C_TAG_WIDTH = 5, // Number of outstanding requests 
+      parameter C_VENDOR = "ALTERA",
+      parameter C_FPGA_NAME = "FPGA",
+      parameter C_DEPTH_PACKETS = 10
+      )
+    (
+     input                                      CLK,
+     input                                      RST_IN,
+     output                                     RST_OUT,
+    
+     // Interface: RXC Engine
+     input [C_PCI_DATA_WIDTH-1:0]               RXC_DATA,
+     input                                      RXC_DATA_VALID,
+     input [(C_PCI_DATA_WIDTH/32)-1:0]          RXC_DATA_WORD_ENABLE,
+     input                                      RXC_DATA_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]    RXC_DATA_START_OFFSET,
+     input                                      RXC_DATA_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]    RXC_DATA_END_OFFSET,
+
+     input [`SIG_LBE_W-1:0]                     RXC_META_LDWBE,
+     input [`SIG_FBE_W-1:0]                     RXC_META_FDWBE,
+     input [`SIG_TAG_W-1:0]                     RXC_META_TAG,
+     input [`SIG_LOWADDR_W-1:0]                 RXC_META_ADDR,
+     input [`SIG_TYPE_W-1:0]                    RXC_META_TYPE,
+     input [`SIG_LEN_W-1:0]                     RXC_META_LENGTH,
+     input [`SIG_BYTECNT_W-1:0]                 RXC_META_BYTES_REMAINING,
+     input [`SIG_CPLID_W-1:0]                   RXC_META_COMPLETER_ID,
+     input                                      RXC_META_EP,
+
+     // Interface: RXR Engine
+     input [C_PCI_DATA_WIDTH-1:0]               RXR_DATA,
+     input                                      RXR_DATA_VALID,
+     input [(C_PCI_DATA_WIDTH/32)-1:0]          RXR_DATA_WORD_ENABLE,
+     input                                      RXR_DATA_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]    RXR_DATA_START_OFFSET,
+     input                                      RXR_DATA_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]    RXR_DATA_END_OFFSET,
+    
+     input [`SIG_FBE_W-1:0]                     RXR_META_FDWBE,
+     input [`SIG_LBE_W-1:0]                     RXR_META_LDWBE,
+     input [`SIG_TC_W-1:0]                      RXR_META_TC,
+     input [`SIG_ATTR_W-1:0]                    RXR_META_ATTR,
+     input [`SIG_TAG_W-1:0]                     RXR_META_TAG,
+     input [`SIG_TYPE_W-1:0]                    RXR_META_TYPE,
+     input [`SIG_ADDR_W-1:0]                    RXR_META_ADDR,
+     input [`SIG_BARDECODE_W-1:0]               RXR_META_BAR_DECODED,
+     input [`SIG_REQID_W-1:0]                   RXR_META_REQUESTER_ID,
+     input [`SIG_LEN_W-1:0]                     RXR_META_LENGTH,
+     input                                      RXR_META_EP,
+    
+     // Interface: TXC Engine
+     output [C_PCI_DATA_WIDTH-1:0]              TXC_DATA,
+     output                                     TXC_DATA_VALID,
+     output                                     TXC_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   TXC_DATA_START_OFFSET,
+     output                                     TXC_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   TXC_DATA_END_OFFSET,
+     input                                      TXC_DATA_READY,
+
+     output                                     TXC_META_VALID,
+     output [`SIG_FBE_W-1:0]                    TXC_META_FDWBE,
+     output [`SIG_LBE_W-1:0]                    TXC_META_LDWBE,
+     output [`SIG_LOWADDR_W-1:0]                TXC_META_ADDR,
+     output [`SIG_TYPE_W-1:0]                   TXC_META_TYPE,
+     output [`SIG_LEN_W-1:0]                    TXC_META_LENGTH,
+     output [`SIG_BYTECNT_W-1:0]                TXC_META_BYTE_COUNT,
+     output [`SIG_TAG_W-1:0]                    TXC_META_TAG,
+     output [`SIG_REQID_W-1:0]                  TXC_META_REQUESTER_ID,
+     output [`SIG_TC_W-1:0]                     TXC_META_TC,
+     output [`SIG_ATTR_W-1:0]                   TXC_META_ATTR,
+     output                                     TXC_META_EP,
+     input                                      TXC_META_READY,
+     input                                      TXC_SENT,
+
+     // Interface: TXR Engine
+     output                                     TXR_DATA_VALID,
+     output [C_PCI_DATA_WIDTH-1:0]              TXR_DATA,
+     output                                     TXR_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   TXR_DATA_START_OFFSET,
+     output                                     TXR_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   TXR_DATA_END_OFFSET,
+     input                                      TXR_DATA_READY,
+
+     output                                     TXR_META_VALID,
+     output [`SIG_FBE_W-1:0]                    TXR_META_FDWBE, 
+     output [`SIG_LBE_W-1:0]                    TXR_META_LDWBE,
+     output [`SIG_ADDR_W-1:0]                   TXR_META_ADDR,
+     output [`SIG_LEN_W-1:0]                    TXR_META_LENGTH,
+     output [`SIG_TAG_W-1:0]                    TXR_META_TAG,
+     output [`SIG_TC_W-1:0]                     TXR_META_TC,
+     output [`SIG_ATTR_W-1:0]                   TXR_META_ATTR,
+     output [`SIG_TYPE_W-1:0]                   TXR_META_TYPE,
+     output                                     TXR_META_EP,
+     input                                      TXR_META_READY,
+     input                                      TXR_SENT,
+
+     // Interface: Configuration 
+     input [`SIG_CPLID_W-1:0]                   CONFIG_COMPLETER_ID,
+     input                                      CONFIG_BUS_MASTER_ENABLE, 
+     input [`SIG_LINKWIDTH_W-1:0]               CONFIG_LINK_WIDTH,
+     input [`SIG_LINKRATE_W-1:0]                CONFIG_LINK_RATE,
+     input [`SIG_MAXREAD_W-1:0]                 CONFIG_MAX_READ_REQUEST_SIZE, 
+     input [`SIG_MAXPAYLOAD_W-1:0]              CONFIG_MAX_PAYLOAD_SIZE,
+     input [`SIG_FC_CPLD_W-1:0]                 CONFIG_MAX_CPL_DATA, // Receive credit limit for data
+     input [`SIG_FC_CPLH_W-1:0]                 CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
+     input                                      CONFIG_INTERRUPT_MSIENABLE,
+     input                                      CONFIG_CPL_BOUNDARY_SEL,
+     // Interrupt Request
+     input                                      INTR_MSI_RDY, // High when interrupt is able to be sent
+     output                                     INTR_MSI_REQUEST, // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_RE
+
+     input [C_NUM_CHNL-1:0]                     CHNL_RX_CLK, 
+     output [C_NUM_CHNL-1:0]                    CHNL_RX, 
+     input [C_NUM_CHNL-1:0]                     CHNL_RX_ACK, 
+     output [C_NUM_CHNL-1:0]                    CHNL_RX_LAST, 
+     output [(C_NUM_CHNL*32)-1:0]               CHNL_RX_LEN, 
+     output [(C_NUM_CHNL*31)-1:0]               CHNL_RX_OFF, 
+     output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, 
+     output [C_NUM_CHNL-1:0]                    CHNL_RX_DATA_VALID, 
+     input [C_NUM_CHNL-1:0]                     CHNL_RX_DATA_REN,
+    
+     input [C_NUM_CHNL-1:0]                     CHNL_TX_CLK, 
+     input [C_NUM_CHNL-1:0]                     CHNL_TX, 
+     output [C_NUM_CHNL-1:0]                    CHNL_TX_ACK,
+     input [C_NUM_CHNL-1:0]                     CHNL_TX_LAST, 
+     input [(C_NUM_CHNL*32)-1:0]                CHNL_TX_LEN, 
+     input [(C_NUM_CHNL*31)-1:0]                CHNL_TX_OFF, 
+     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]  CHNL_TX_DATA, 
+     input [C_NUM_CHNL-1:0]                     CHNL_TX_DATA_VALID, 
+     output [C_NUM_CHNL-1:0]                    CHNL_TX_DATA_REN
+
+     );
+    localparam C_MAX_READ_REQ = clog2s(C_MAX_READ_REQ_BYTES)-7;    // Max read: 000=128B; 001=256B; 010=512B; 011=1024B; 100=2048B; 101=4096B
+    localparam C_NUM_CHNL_WIDTH = clog2s(C_NUM_CHNL);
+    localparam C_PCI_DATA_WORD_WIDTH = clog2s((C_PCI_DATA_WIDTH/32)+1);
+    localparam C_NUM_VECTORS = 2;
+    localparam C_VECTOR_WIDTH = 32;
+
+    // Interface: Reorder Buffer Output
+    wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngMainDataEn; // Start offset and end offset
+    wire [C_PCI_DATA_WIDTH-1:0]                   wRxEngData;
+    wire [C_NUM_CHNL-1:0]                         wRxEngMainDone;
+    wire [C_NUM_CHNL-1:0]                         wRxEngMainErr;
+
+    // Interface: Reorder Buffer to SG RX engines    
+    wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngSgRxDataEn;
+    wire [C_NUM_CHNL-1:0]                         wRxEngSgRxDone;
+    wire [C_NUM_CHNL-1:0]                         wRxEngSgRxErr;
+    
+    // Interface: Reorder Buffer to SG TX engines    
+    wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngSgTxDataEn;
+    wire [C_NUM_CHNL-1:0]                         wRxEngSgTxDone;
+    wire [C_NUM_CHNL-1:0]                         wRxEngSgTxErr;
+
+    // Interface: Channel TX Write
+    wire [C_NUM_CHNL-1:0]                         wTxEngWrReq;
+    wire [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]           wTxEngWrAddr;
+    wire [(C_NUM_CHNL*`SIG_LEN_W)-1:0]            wTxEngWrLen;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]      wTxEngWrData;
+    wire [C_NUM_CHNL-1:0]                         wTxEngWrDataRen;
+    wire [C_NUM_CHNL-1:0]                         wTxEngWrAck; 
+    wire [C_NUM_CHNL-1:0]                         wTxEngWrSent;
+
+    // Interface: Channel TX Read
+    wire [C_NUM_CHNL-1:0]                         wTxEngRdReq;
+    wire [(C_NUM_CHNL*2)-1:0]                     wTxEngRdSgChnl;
+    wire [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]           wTxEngRdAddr;
+    wire [(C_NUM_CHNL*`SIG_LEN_W)-1:0]            wTxEngRdLen;
+    wire [C_NUM_CHNL-1:0]                         wTxEngRdAck;
+
+    // Interface: Channel Interrupts
+    wire [C_NUM_CHNL-1:0]                         wChnlSgRxBufRecvd;
+    wire [C_NUM_CHNL-1:0]                         wChnlRxDone;
+    wire [C_NUM_CHNL-1:0]                         wChnlTxRequest;
+    wire [C_NUM_CHNL-1:0]                         wChnlTxDone;
+    wire [C_NUM_CHNL-1:0]                         wChnlSgTxBufRecvd;
+
+    wire                                          wInternalTagValid;
+    wire [5:0]                                    wInternalTag;
+    wire                                          wExternalTagValid;
+    wire [C_TAG_WIDTH-1:0]                        wExternalTag;
+
+    // Interface: Channel - PIO Read
+    wire [C_NUM_CHNL-1:0]                         wChnlTxLenReady;
+    wire [(`SIG_TXRLEN_W*C_NUM_CHNL)-1:0]         wChnlTxReqLen;
+    wire [C_NUM_CHNL-1:0]                         wChnlTxOfflastReady;
+    wire [(`SIG_OFFLAST_W*C_NUM_CHNL)-1:0]        wChnlTxOfflast;
+    wire                                          wCoreSettingsReady;
+    wire [`SIG_CORESETTINGS_W-1:0]                wCoreSettings;
+    wire [C_NUM_VECTORS-1:0]                      wIntrVectorReady;
+    wire [C_NUM_VECTORS*C_VECTOR_WIDTH-1:0]       wIntrVector;
+    wire [C_NUM_CHNL-1:0]                         wChnlTxDoneReady;
+    wire [(`SIG_TXDONELEN_W*C_NUM_CHNL)-1:0]      wChnlTxDoneLen;
+    wire [C_NUM_CHNL-1:0]                         wChnlRxDoneReady;
+    wire [(`SIG_RXDONELEN_W*C_NUM_CHNL)-1:0]      wChnlRxDoneLen;
+    wire                                          wChnlNameReady;
+
+    // Interface: Channel - PIO Write
+    wire [31:0]                                   wChnlReqData; 
+    wire [C_NUM_CHNL-1:0]                         wChnlSgRxLenValid;
+    wire [C_NUM_CHNL-1:0]                         wChnlSgRxAddrLoValid;
+    wire [C_NUM_CHNL-1:0]                         wChnlSgRxAddrHiValid;
+    wire [C_NUM_CHNL-1:0]                         wChnlSgTxLenValid;
+    wire [C_NUM_CHNL-1:0]                         wChnlSgTxAddrLoValid;
+    wire [C_NUM_CHNL-1:0]                         wChnlSgTxAddrHiValid;
+    wire [C_NUM_CHNL-1:0]                         wChnlRxLenValid;
+    wire [C_NUM_CHNL-1:0]                         wChnlRxOfflastValid;
+
+    wire                                          wRxBufSpaceAvail;
+    wire                                          wTxEngRdReqSent;
+    wire                                          wRxEngRdComplete;
+
+    reg [4:0]                                     rWideRst;
+    reg                                           rRst;
+
+    genvar                                        i;
+
+    assign wRxEngRdComplete = RXC_DATA_END_FLAG & RXC_DATA_VALID & 
+                              (RXC_META_LENGTH >= RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:2]);// TODO: Retime (if possible)
+
+    assign wCoreSettings = {9'd0, C_PCI_DATA_WIDTH[8:5], CONFIG_MAX_PAYLOAD_SIZE, CONFIG_MAX_READ_REQUEST_SIZE, CONFIG_LINK_RATE[1:0], CONFIG_LINK_WIDTH, CONFIG_BUS_MASTER_ENABLE, C_NUM_CHNL[3:0]};
+    
+    assign RST_OUT = rRst;
+    always @ (posedge CLK) begin
+        rRst <= #1 rWideRst[4]; 
+        if (RST_IN | (wCoreSettingsReady /*& wRxEngReqRdDone*/)) // TODO: 
+            rWideRst <= #1 5'b11111;
+        else 
+            rWideRst <= (rWideRst<<1);
+    end
+
+    reorder_queue 
+        #( 
+           .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
+           .C_NUM_CHNL(C_NUM_CHNL),
+           .C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),
+           .C_TAG_WIDTH(C_TAG_WIDTH)
+           ) 
+    reorderQueue 
+        (
+         .RST                           (rRst),
+         .VALID                         (RXC_DATA_VALID),
+         .DATA_START_FLAG               (RXC_DATA_START_FLAG),
+         .DATA_START_OFFSET             (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .DATA_END_FLAG                 (RXC_DATA_END_FLAG),
+         .DATA_END_OFFSET               (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .DATA                          (RXC_DATA),
+         .DATA_EN                       (RXC_DATA_WORD_ENABLE),
+         .DONE                          (wRxEngRdComplete),
+         .ERR                           (RXC_META_EP),
+         .TAG                           (RXC_META_TAG[C_TAG_WIDTH-1:0]), 
+         .INT_TAG                       (wInternalTag),
+         .INT_TAG_VALID                 (wInternalTagValid),
+         .EXT_TAG                       (wExternalTag),
+         .EXT_TAG_VALID                 (wExternalTagValid),
+         .ENG_DATA                      (wRxEngData), 
+         .MAIN_DATA_EN                  (wRxEngMainDataEn),
+         .MAIN_DONE                     (wRxEngMainDone),
+         .MAIN_ERR                      (wRxEngMainErr),
+         .SG_RX_DATA_EN                 (wRxEngSgRxDataEn),
+         .SG_RX_DONE                    (wRxEngSgRxDone),
+         .SG_RX_ERR                     (wRxEngSgRxErr),
+         .SG_TX_DATA_EN                 (wRxEngSgTxDataEn), 
+         .SG_TX_DONE                    (wRxEngSgTxDone), 
+         .SG_TX_ERR                     (wRxEngSgTxErr),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK));
+
+    registers
+        #(// Parameters
+          .C_PIPELINE_OUTPUT            (1),
+          .C_PIPELINE_INPUT             (1),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_MAX_READ_REQ_BYTES         (C_MAX_READ_REQ_BYTES),
+          .C_VENDOR                     (C_VENDOR),
+          .C_NUM_VECTORS                (C_NUM_VECTORS),
+          .C_VECTOR_WIDTH               (C_VECTOR_WIDTH),
+          .C_FPGA_NAME                  (C_FPGA_NAME))
+    reg_inst
+        (// Outputs
+         // Write Interfaces
+         .CHNL_REQ_DATA                 (wChnlReqData[31:0]),
+         .CHNL_SGRX_LEN_VALID           (wChnlSgRxLenValid),
+         .CHNL_SGRX_ADDRLO_VALID        (wChnlSgRxAddrLoValid),
+         .CHNL_SGRX_ADDRHI_VALID        (wChnlSgRxAddrHiValid),
+         .CHNL_SGTX_LEN_VALID           (wChnlSgTxLenValid),
+         .CHNL_SGTX_ADDRLO_VALID        (wChnlSgTxAddrLoValid),
+         .CHNL_SGTX_ADDRHI_VALID        (wChnlSgTxAddrHiValid),
+         .CHNL_RX_LEN_VALID             (wChnlRxLenValid),
+         .CHNL_RX_OFFLAST_VALID         (wChnlRxOfflastValid),
+         // Read Interfaces
+         .CHNL_TX_LEN_READY             (wChnlTxLenReady),
+         .CHNL_TX_OFFLAST_READY         (wChnlTxOfflastReady),
+         .CORE_SETTINGS_READY           (wCoreSettingsReady),
+         .INTR_VECTOR_READY             (wIntrVectorReady),
+         .CHNL_TX_DONE_READY            (wChnlTxDoneReady),
+         .CHNL_RX_DONE_READY            (wChnlRxDoneReady),
+         .CHNL_NAME_READY               (wChnlNameReady), // TODO: Could do this on a per-channel basis
+         // Inputs
+         // Read Data
+         .CORE_SETTINGS                 (wCoreSettings),
+         .CHNL_TX_REQLEN                (wChnlTxReqLen),
+         .CHNL_TX_OFFLAST               (wChnlTxOfflast),
+         .CHNL_TX_DONELEN               (wChnlTxDoneLen),
+         .CHNL_RX_DONELEN               (wChnlRxDoneLen),
+         .INTR_VECTOR                   (wIntrVector),
+         .RST_IN                        (rRst),
+         /*AUTOINST*/
+         // Outputs
+         .TXC_DATA_VALID                (TXC_DATA_VALID),
+         .TXC_DATA                      (TXC_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_START_FLAG           (TXC_DATA_START_FLAG),
+         .TXC_DATA_START_OFFSET         (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (TXC_DATA_END_FLAG),
+         .TXC_DATA_END_OFFSET           (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (TXC_META_VALID),
+         .TXC_META_FDWBE                (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (TXC_META_TAG[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (TXC_META_TC[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (TXC_META_EP),
+         // Inputs
+         .CLK                           (CLK),
+         .RXR_DATA                      (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_VALID                (RXR_DATA_VALID),
+         .RXR_DATA_START_FLAG           (RXR_DATA_START_FLAG),
+         .RXR_DATA_START_OFFSET         (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
+         .RXR_DATA_END_FLAG             (RXR_DATA_END_FLAG),
+         .RXR_DATA_END_OFFSET           (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_LDWBE                (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (RXR_META_TC[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (RXR_META_TAG[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (RXR_META_LENGTH[`SIG_LEN_W-1:0]),
+         .TXC_DATA_READY                (TXC_DATA_READY),
+         .TXC_META_READY                (TXC_META_READY));
+    
+    // Track receive buffer flow control credits (header & Data)
+    recv_credit_flow_ctrl rc_fc 
+        (
+         // Outputs
+         .RXBUF_SPACE_AVAIL             (wRxBufSpaceAvail),
+         // Inputs
+         .RX_ENG_RD_DONE                (wRxEngRdComplete),
+         .TX_ENG_RD_REQ_SENT            (wTxEngRdReqSent),
+         .RST                           (rRst),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .CONFIG_MAX_READ_REQUEST_SIZE  (CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
+         .CONFIG_MAX_CPL_DATA           (CONFIG_MAX_CPL_DATA[11:0]),
+         .CONFIG_MAX_CPL_HDR            (CONFIG_MAX_CPL_HDR[7:0]),
+         .CONFIG_CPL_BOUNDARY_SEL       (CONFIG_CPL_BOUNDARY_SEL));
+    // Connect the interrupt vector and controller.
+    interrupt 
+        #(
+          .C_NUM_CHNL                   (C_NUM_CHNL)
+          ) 
+    intr 
+        (// Inputs
+         .RST                           (rRst),
+         .RX_SG_BUF_RECVD               (wChnlSgRxBufRecvd),
+         .RX_TXN_DONE                   (wChnlRxDone),
+         .TX_TXN                        (wChnlTxRequest),
+         .TX_SG_BUF_RECVD               (wChnlSgTxBufRecvd),
+         .TX_TXN_DONE                   (wChnlTxDone),
+         .VECT_0_RST                    (wIntrVectorReady[0]),
+         .VECT_1_RST                    (wIntrVectorReady[1]),
+         .VECT_RST                      (TXC_DATA[31:0]),
+         .VECT_0                        (wIntrVector[31:0]),
+         .VECT_1                        (wIntrVector[63:32]),
+         .INTR_LEGACY_CLR               (1'd0),
+         /*AUTOINST*/
+         // Outputs
+         .INTR_MSI_REQUEST              (INTR_MSI_REQUEST),
+         // Inputs
+         .CLK                           (CLK),
+         .CONFIG_INTERRUPT_MSIENABLE    (CONFIG_INTERRUPT_MSIENABLE),
+         .INTR_MSI_RDY                  (INTR_MSI_RDY));
+
+
+    tx_multiplexer
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_TAG_WIDTH                  (C_TAG_WIDTH),
+          .C_VENDOR                     (C_VENDOR),
+          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS))
+    tx_mux_inst
+        (
+         // Outputs
+         .WR_DATA_REN                   (wTxEngWrDataRen[C_NUM_CHNL-1:0]),
+         .WR_ACK                        (wTxEngWrAck[C_NUM_CHNL-1:0]),
+         .RD_ACK                        (wTxEngRdAck[C_NUM_CHNL-1:0]),
+         .INT_TAG                       (wInternalTag[5:0]),
+         .INT_TAG_VALID                 (wInternalTagValid),
+         .TX_ENG_RD_REQ_SENT            (wTxEngRdReqSent),
+         // Inputs
+         .RST_IN                        (rRst),
+         .WR_REQ                        (wTxEngWrReq[C_NUM_CHNL-1:0]),
+         .WR_ADDR                       (wTxEngWrAddr[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
+         .WR_LEN                        (wTxEngWrLen[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
+         .WR_DATA                       (wTxEngWrData[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .WR_SENT                       (wTxEngWrSent[C_NUM_CHNL-1:0]),
+         .RD_REQ                        (wTxEngRdReq[C_NUM_CHNL-1:0]),
+         .RD_SG_CHNL                    (wTxEngRdSgChnl[(C_NUM_CHNL*2)-1:0]),
+         .RD_ADDR                       (wTxEngRdAddr[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
+         .RD_LEN                        (wTxEngRdLen[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
+         .EXT_TAG                       (wExternalTag[C_TAG_WIDTH-1:0]),
+         .EXT_TAG_VALID                 (wExternalTagValid),
+         .RXBUF_SPACE_AVAIL             (wRxBufSpaceAvail),
+         /*AUTOINST*/
+         // Outputs
+         .TXR_DATA_VALID                (TXR_DATA_VALID),
+         .TXR_DATA                      (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (TXR_DATA_START_FLAG),
+         .TXR_DATA_START_OFFSET         (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (TXR_DATA_END_FLAG),
+         .TXR_DATA_END_OFFSET           (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (TXR_META_VALID),
+         .TXR_META_FDWBE                (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (TXR_META_TAG[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (TXR_META_TC[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (TXR_META_EP),
+         // Inputs
+         .CLK                           (CLK),
+         .TXR_DATA_READY                (TXR_DATA_READY),
+         .TXR_META_READY                (TXR_META_READY),
+         .TXR_SENT                      (TXR_SENT));
+    
+    // Generate and link up the channels.
+    generate
+        for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : channels
+            channel 
+                 #(
+                   .C_DATA_WIDTH(C_PCI_DATA_WIDTH), 
+                   .C_MAX_READ_REQ(C_MAX_READ_REQ)
+                   )
+            channel 
+                 (
+                  .RST(rRst),
+                  .CLK(CLK), 
+                  .CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE), 
+                  .CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE), 
+
+                  .PIO_DATA(wChnlReqData), 
+                  .ENG_DATA(wRxEngData), 
+                
+                  .SG_RX_BUF_RECVD(wChnlSgRxBufRecvd[i]),
+                  .SG_TX_BUF_RECVD(wChnlSgTxBufRecvd[i]),
+                  .TXN_TX(wChnlTxRequest[i]),
+                  .TXN_TX_DONE(wChnlTxDone[i]),
+                  .TXN_RX_DONE(wChnlRxDone[i]),
+                
+                  .SG_RX_BUF_LEN_VALID(wChnlSgRxLenValid[i]),
+                  .SG_RX_BUF_ADDR_HI_VALID(wChnlSgRxAddrHiValid[i]),
+                  .SG_RX_BUF_ADDR_LO_VALID(wChnlSgRxAddrLoValid[i]),
+                
+                  .SG_TX_BUF_LEN_VALID(wChnlSgTxLenValid[i]),
+                  .SG_TX_BUF_ADDR_HI_VALID(wChnlSgTxAddrHiValid[i]),
+                  .SG_TX_BUF_ADDR_LO_VALID(wChnlSgTxAddrLoValid[i]),
+                
+                  .TXN_RX_LEN_VALID(wChnlRxLenValid[i]), 
+                  .TXN_RX_OFF_LAST_VALID(wChnlRxOfflastValid[i]), 
+                  .TXN_RX_DONE_LEN(wChnlRxDoneLen[(`SIG_RXDONELEN_W*i) +: `SIG_RXDONELEN_W]),
+                  .TXN_RX_DONE_ACK(wChnlRxDoneReady[i]),
+                
+                  .TXN_TX_ACK(wChnlTxLenReady[i]), // ACK'd on length read
+                  .TXN_TX_LEN(wChnlTxReqLen[(`SIG_TXRLEN_W*i) +: `SIG_TXRLEN_W]),
+                  .TXN_TX_OFF_LAST(wChnlTxOfflast[(`SIG_OFFLAST_W*i) +: `SIG_OFFLAST_W]),
+                  .TXN_TX_DONE_LEN(wChnlTxDoneLen[(`SIG_TXDONELEN_W*i) +:`SIG_TXDONELEN_W]),
+                  .TXN_TX_DONE_ACK(wChnlTxDoneReady[i]),
+                
+                  .RX_REQ(wTxEngRdReq[i]),
+                  .RX_REQ_ACK(wTxEngRdAck[i]),
+                  .RX_REQ_TAG(wTxEngRdSgChnl[(2*i) +:2]),// TODO: `SIG_INTERNALTAG_W
+                  .RX_REQ_ADDR(wTxEngRdAddr[(`SIG_ADDR_W*i) +:`SIG_ADDR_W]),
+                  .RX_REQ_LEN(wTxEngRdLen[(`SIG_LEN_W*i) +:`SIG_LEN_W]),
+
+                  .TX_REQ(wTxEngWrReq[i]), 
+                  .TX_REQ_ACK(wTxEngWrAck[i]),
+                  .TX_ADDR(wTxEngWrAddr[(`SIG_ADDR_W*i) +: `SIG_ADDR_W]), 
+                  .TX_LEN(wTxEngWrLen[(`SIG_LEN_W*i) +: `SIG_LEN_W]), 
+                  .TX_DATA(wTxEngWrData[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
+                  .TX_DATA_REN(wTxEngWrDataRen[i]), 
+                  .TX_SENT(wTxEngWrSent[i]),
+                
+                  .MAIN_DATA_EN(wRxEngMainDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]), 
+                  .MAIN_DONE(wRxEngMainDone[i]), 
+                  .MAIN_ERR(wRxEngMainErr[i]),
+                
+                  .SG_RX_DATA_EN(wRxEngSgRxDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),  
+                  .SG_RX_DONE(wRxEngSgRxDone[i]), 
+                  .SG_RX_ERR(wRxEngSgRxErr[i]),
+
+                  .SG_TX_DATA_EN(wRxEngSgTxDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]), 
+                  .SG_TX_DONE(wRxEngSgTxDone[i]), 
+                  .SG_TX_ERR(wRxEngSgTxErr[i]),
+
+                  .CHNL_RX_CLK(CHNL_RX_CLK[i]), 
+                  .CHNL_RX(CHNL_RX[i]), 
+                  .CHNL_RX_ACK(CHNL_RX_ACK[i]), 
+                  .CHNL_RX_LAST(CHNL_RX_LAST[i]), 
+                  .CHNL_RX_LEN(CHNL_RX_LEN[(32*i) +:32]), 
+                  .CHNL_RX_OFF(CHNL_RX_OFF[(31*i) +:31]), 
+                  .CHNL_RX_DATA(CHNL_RX_DATA[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID[i]), 
+                  .CHNL_RX_DATA_REN(CHNL_RX_DATA_REN[i]),
+
+                  .CHNL_TX_CLK(CHNL_TX_CLK[i]), 
+                  .CHNL_TX(CHNL_TX[i]), 
+                  .CHNL_TX_ACK(CHNL_TX_ACK[i]),
+                  .CHNL_TX_LAST(CHNL_TX_LAST[i]), 
+                  .CHNL_TX_LEN(CHNL_TX_LEN[(32*i) +:32]), 
+                  .CHNL_TX_OFF(CHNL_TX_OFF[(31*i) +:31]), 
+                  .CHNL_TX_DATA(CHNL_TX_DATA[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID[i]), 
+                  .CHNL_TX_DATA_REN(CHNL_TX_DATA_REN[i])
+                  );
+
+        end
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "registers/" "import")
+// End:
+
diff --git a/fpga/riffa_hdl/riffa.vh b/fpga/riffa_hdl/riffa.vh
new file mode 100644
index 0000000..16c1677
--- /dev/null
+++ b/fpga/riffa_hdl/riffa.vh
@@ -0,0 +1,79 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            riffa.vh
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The riffa.vh file is a header file that defines
+// various RIFFA-specific primitives.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`ifndef __RIFFA_VH
+`define __RIFFA_VH 1
+`include "widths.vh"
+
+// User Interface Signals
+`define SIG_CHNL_OFFSET_W 31
+`define SIG_CHNL_LENGTH_W 32
+`define SIG_CHNL_LAST_W 1
+
+// Engine/Channel interface signals
+`define SIG_TXRLEN_W 32
+`define SIG_OFFLAST_W 32
+`define SIG_LAST_W 1
+`define SIG_TXDONELEN_W 32
+`define SIG_RXDONELEN_W 32
+`define SIG_CORESETTINGS_W 32
+
+// Writable addresses
+`define ADDR_SGRX_LEN 4'b0000
+`define ADDR_SGRX_ADDRLO 4'b0001
+`define ADDR_SGRX_ADDRHI 4'b0010
+`define ADDR_RX_LEN 4'b0011
+`define ADDR_RX_OFFLAST 4'b0100
+`define ADDR_SGTX_LEN 4'b0101
+`define ADDR_SGTX_ADDRLO 4'b0110
+`define ADDR_SGTX_ADDRHI 4'b0111
+// Readable Addresses
+`define ADDR_TX_LEN 4'b1000
+`define ADDR_TX_OFFLAST 4'b1001
+`define ADDR_CORESETTINGS 4'b1010
+`define ADDR_INTR_VECTOR_0 4'b1011
+`define ADDR_INTR_VECTOR_1 4'b1100
+`define ADDR_RX_LEN_XFERD 4'b1101
+`define ADDR_TX_LEN_XFERD 4'b1110
+`define ADDR_FPGA_NAME 4'b1111
+
+`endif
diff --git a/fpga/riffa_hdl/rotate.v b/fpga/riffa_hdl/rotate.v
new file mode 100644
index 0000000..ebdcdf4
--- /dev/null
+++ b/fpga/riffa_hdl/rotate.v
@@ -0,0 +1,74 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			rotate.v
+// Version:				1.00
+// Verilog Standard:	Verilog-2001
+// Description:			A simple module to perform to rotate the input data
+// Author:				Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "functions.vh"
+module rotate
+    #(
+      parameter C_DIRECTION = "LEFT",
+      parameter C_WIDTH = 4
+      )
+    (
+     input [C_WIDTH-1:0]        WR_DATA,
+     input [clog2s(C_WIDTH)-1:0] WR_SHIFTAMT,
+     output [C_WIDTH-1:0]       RD_DATA
+     );
+
+    wire [2*C_WIDTH-1:0]        wPreShiftR;
+    wire [2*C_WIDTH-1:0]        wPreShiftL;
+
+    wire [2*C_WIDTH-1:0]        wShiftR;
+    wire [2*C_WIDTH-1:0]        wShiftL;
+
+    assign wPreShiftL = {WR_DATA,WR_DATA};
+    assign wPreShiftR = {WR_DATA,WR_DATA};
+
+    assign wShiftL = wPreShiftL << WR_SHIFTAMT;
+    assign wShiftR = wPreShiftR >> WR_SHIFTAMT;
+
+    generate
+        if(C_DIRECTION == "LEFT") begin
+            assign RD_DATA = wShiftL[2*C_WIDTH-1:C_WIDTH];
+        end else if (C_DIRECTION == "RIGHT") begin
+            assign RD_DATA = wShiftR[C_WIDTH-1:0];
+        end
+    endgenerate
+endmodule
diff --git a/fpga/riffa_hdl/rx_engine_classic.v b/fpga/riffa_hdl/rx_engine_classic.v
new file mode 100644
index 0000000..62c57b6
--- /dev/null
+++ b/fpga/riffa_hdl/rx_engine_classic.v
@@ -0,0 +1,445 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            rx_engine_classic.v
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The RX Engine (Classic) takes a single stream of TLP
+// packets and provides the request packets on the RXR Interface, and the 
+// completion packets on the RXC Interface.
+// This Engine is capable of operating at "line rate".
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "trellis.vh"
+`include "tlp.vh"
+module rx_engine_classic
+    #(
+      parameter C_VENDOR = "ALTERA",
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_LOG_NUM_TAGS=6
+      )
+    (
+     // Interface: Clocks
+     input                                    CLK,
+
+     // Interface: Resets
+     input                                    RST_IN,
+
+     // Interface: RX Classic
+     input [C_PCI_DATA_WIDTH-1:0]             RX_TLP,
+     input                                    RX_TLP_VALID,
+     output                                   RX_TLP_READY,
+     input                                    RX_TLP_START_FLAG,
+     input [`SIG_OFFSET_W-1:0]                RX_TLP_START_OFFSET,
+     input                                    RX_TLP_END_FLAG,
+     input [`SIG_OFFSET_W-1:0]                RX_TLP_END_OFFSET,
+     input [`SIG_BARDECODE_W-1:0]             RX_TLP_BAR_DECODE,
+    
+     // Interface: RXC Engine
+     output [C_PCI_DATA_WIDTH-1:0]            RXC_DATA,
+     output                                   RXC_DATA_VALID,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]       RXC_DATA_WORD_ENABLE,
+     output                                   RXC_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
+     output                                   RXC_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
+
+     output [`SIG_LBE_W-1:0]                  RXC_META_LDWBE,
+     output [`SIG_FBE_W-1:0]                  RXC_META_FDWBE,
+     output [`SIG_TAG_W-1:0]                  RXC_META_TAG,
+     output [`SIG_LOWADDR_W-1:0]              RXC_META_ADDR,
+     output [`SIG_TYPE_W-1:0]                 RXC_META_TYPE,
+     output [`SIG_LEN_W-1:0]                  RXC_META_LENGTH,
+     output [`SIG_BYTECNT_W-1:0]              RXC_META_BYTES_REMAINING,
+     output [`SIG_CPLID_W-1:0]                RXC_META_COMPLETER_ID,
+     output                                   RXC_META_EP,
+
+     // Interface: RXR Engine
+     output [C_PCI_DATA_WIDTH-1:0]            RXR_DATA,
+     output                                   RXR_DATA_VALID,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]       RXR_DATA_WORD_ENABLE,
+     output                                   RXR_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
+     output                                   RXR_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
+    
+     output [`SIG_FBE_W-1:0]                  RXR_META_FDWBE,
+     output [`SIG_LBE_W-1:0]                  RXR_META_LDWBE,
+     output [`SIG_TC_W-1:0]                   RXR_META_TC,
+     output [`SIG_ATTR_W-1:0]                 RXR_META_ATTR,
+     output [`SIG_TAG_W-1:0]                  RXR_META_TAG,
+     output [`SIG_TYPE_W-1:0]                 RXR_META_TYPE,
+     output [`SIG_ADDR_W-1:0]                 RXR_META_ADDR,
+     output [`SIG_BARDECODE_W-1:0]            RXR_META_BAR_DECODED,
+     output [`SIG_REQID_W-1:0]                RXR_META_REQUESTER_ID,
+     output [`SIG_LEN_W-1:0]                  RXR_META_LENGTH,
+     output                                   RXR_META_EP
+     );
+    localparam C_RX_PIPELINE_DEPTH = 4;
+
+    wire [C_PCI_DATA_WIDTH-1:0]               _RXC_DATA;
+    wire [C_PCI_DATA_WIDTH-1:0]               _RXR_DATA;
+    wire [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] wRxSrData;
+    wire [C_RX_PIPELINE_DEPTH:0]                        wRxSrSop;
+    wire [C_RX_PIPELINE_DEPTH:0]                        wRxSrEop;
+    wire [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    wRxSrEoff;
+    wire [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    wRxSrSoff;
+    wire [C_RX_PIPELINE_DEPTH:0]                        wRxSrDataValid;
+
+    generate
+        if(C_VENDOR == "XILINX") begin : xilinx_data
+            if(C_PCI_DATA_WIDTH == 128) begin : x_be_swap128
+                assign RXC_DATA = {_RXC_DATA[103:96], _RXC_DATA[111:104], _RXC_DATA[119:112], _RXC_DATA[127:120],
+                                   _RXC_DATA[71:64], _RXC_DATA[79:72], _RXC_DATA[87:80], _RXC_DATA[95:88],
+                                   _RXC_DATA[39:32], _RXC_DATA[47:40], _RXC_DATA[55:48], _RXC_DATA[63:56],
+                                   _RXC_DATA[07:00], _RXC_DATA[15:08], _RXC_DATA[23:16], _RXC_DATA[31:24]};
+                assign RXR_DATA = {_RXR_DATA[103:96], _RXR_DATA[111:104], _RXR_DATA[119:112], _RXR_DATA[127:120],
+                                   _RXR_DATA[71:64], _RXR_DATA[79:72], _RXR_DATA[87:80], _RXR_DATA[95:88],
+                                   _RXR_DATA[39:32], _RXR_DATA[47:40], _RXR_DATA[55:48], _RXR_DATA[63:56],
+                                   _RXR_DATA[07:00], _RXR_DATA[15:08], _RXR_DATA[23:16], _RXR_DATA[31:24]};
+            end else if(C_PCI_DATA_WIDTH == 64) begin: x_be_swap64
+                assign RXC_DATA = {_RXC_DATA[39:32], _RXC_DATA[47:40], _RXC_DATA[55:48], _RXC_DATA[63:56],
+                                   _RXC_DATA[07:00], _RXC_DATA[15:08], _RXC_DATA[23:16], _RXC_DATA[31:24]};
+                assign RXR_DATA = {_RXR_DATA[39:32], _RXR_DATA[47:40], _RXR_DATA[55:48], _RXR_DATA[63:56],
+                                   _RXR_DATA[07:00], _RXR_DATA[15:08], _RXR_DATA[23:16], _RXR_DATA[31:24]};
+            end else if(C_PCI_DATA_WIDTH == 32) begin: x_be_swap32
+                assign RXC_DATA = {_RXC_DATA[07:00], _RXC_DATA[15:08], _RXC_DATA[23:16], _RXC_DATA[31:24]};
+                assign RXR_DATA = {_RXR_DATA[07:00], _RXR_DATA[15:08], _RXR_DATA[23:16], _RXR_DATA[31:24]};
+            end
+        end else begin : altera_data
+            assign RXC_DATA = _RXC_DATA;
+            assign RXR_DATA = _RXR_DATA;
+        end
+    endgenerate
+
+    assign RX_TLP_READY = 1'b1;
+    // Shift register for input data with output taps for each delayed
+    // cycle.  Shared by RXC and RXR engines.
+    shiftreg
+        #(
+          // Parameters
+          .C_DEPTH                    (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                    (C_PCI_DATA_WIDTH))
+    data_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                     (wRxSrData),
+         // Inputs
+         .WR_DATA                     (RX_TLP),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    // Start Flag Shift Register. Data enables are derived from the
+    // taps on this shift register.
+    shiftreg 
+        #(
+          // Parameters
+          .C_DEPTH                     (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                    (1'b1))
+    sop_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                      (wRxSrSop),
+         // Inputs
+         .WR_DATA                       (RX_TLP_START_FLAG & RX_TLP_VALID),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    // Start Flag Shift Register. Data enables are derived from the
+    // taps on this shift register.
+    shiftreg 
+        #(
+          // Parameters
+          .C_DEPTH                    (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                    (1'b1))
+    valid_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                      (wRxSrDataValid),
+         // Inputs
+         .WR_DATA                       (RX_TLP_VALID),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+
+    // End Flag Shift Register. Data valid is deasserted based on the
+    // taps in this register
+    shiftreg 
+        #(
+          // Parameters
+          .C_DEPTH                     (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                    (1'b1))
+    eop_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                      (wRxSrEop),
+         // Inputs
+         .WR_DATA                       (RX_TLP_END_FLAG & RX_TLP_VALID),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    // End Flag Shift Register. Data valid is deasserted based on the
+    // taps in this register
+    shiftreg 
+        #(
+          // Parameters
+          .C_DEPTH                     (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                    (`SIG_OFFSET_W))
+    eoff_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                      (wRxSrEoff),
+         // Inputs
+         .WR_DATA                       (RX_TLP_END_OFFSET),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    // End Flag Shift Register. Data valid is deasserted based on the
+    // taps in this register
+    shiftreg 
+        #(
+          // Parameters
+          .C_DEPTH                     (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                     (`SIG_OFFSET_W))
+    soff_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                      (wRxSrSoff),
+         // Inputs
+         .WR_DATA                      (RX_TLP_START_OFFSET),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    generate
+        if(C_VENDOR == "XILINX" && C_PCI_DATA_WIDTH == 128) begin
+            
+            rxr_engine_128
+                #(/*AUTOINSTPARAM*/
+                  // Parameters
+                  .C_PCI_DATA_WIDTH     (C_PCI_DATA_WIDTH),
+                  .C_RX_PIPELINE_DEPTH  (C_RX_PIPELINE_DEPTH))
+            rxr_engine_inst
+                (
+                 // Inputs
+                 .RX_SR_DATA            (wRxSrData),
+                 .RX_SR_EOP             (wRxSrEop),
+                 .RX_SR_END_OFFSET      (wRxSrEoff),
+                 .RX_SR_SOP             (wRxSrSop),
+                 .RX_SR_START_OFFSET    (wRxSrSoff),
+                 .RX_SR_VALID           (wRxSrDataValid),
+                 // Outputs
+                 .RXR_DATA              (_RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
+                 /*AUTOINST*/
+                 // Outputs
+                 .RXR_DATA_VALID        (RXR_DATA_VALID),
+                 .RXR_DATA_WORD_ENABLE  (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXR_DATA_START_FLAG   (RXR_DATA_START_FLAG),
+                 .RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXR_DATA_END_FLAG     (RXR_DATA_END_FLAG),
+                 .RXR_DATA_END_OFFSET   (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXR_META_FDWBE        (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
+                 .RXR_META_LDWBE        (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
+                 .RXR_META_TC           (RXR_META_TC[`SIG_TC_W-1:0]),
+                 .RXR_META_ATTR         (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
+                 .RXR_META_TAG          (RXR_META_TAG[`SIG_TAG_W-1:0]),
+                 .RXR_META_TYPE         (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
+                 .RXR_META_ADDR         (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
+                 .RXR_META_BAR_DECODED  (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
+                 .RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
+                 .RXR_META_LENGTH       (RXR_META_LENGTH[`SIG_LEN_W-1:0]),
+                 .RXR_META_EP           (RXR_META_EP),
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST_IN                (RST_IN),
+                 .RX_TLP                (RX_TLP[C_PCI_DATA_WIDTH-1:0]),
+                 .RX_TLP_VALID          (RX_TLP_VALID),
+                 .RX_TLP_START_FLAG     (RX_TLP_START_FLAG),
+                 .RX_TLP_START_OFFSET   (RX_TLP_START_OFFSET[`SIG_OFFSET_W-1:0]),
+                 .RX_TLP_END_FLAG       (RX_TLP_END_FLAG),
+                 .RX_TLP_END_OFFSET     (RX_TLP_END_OFFSET[`SIG_OFFSET_W-1:0]),
+                 .RX_TLP_BAR_DECODE     (RX_TLP_BAR_DECODE[`SIG_BARDECODE_W-1:0]));
+
+            rxc_engine_128
+                #(/*AUTOINSTPARAM*/
+                  // Parameters
+                  .C_PCI_DATA_WIDTH     (C_PCI_DATA_WIDTH),
+                  .C_RX_PIPELINE_DEPTH  (C_RX_PIPELINE_DEPTH))
+            rxc_engine_inst
+                (
+                 // Inputs
+                 .RX_SR_DATA            (wRxSrData),
+                 .RX_SR_EOP             (wRxSrEop),
+                 .RX_SR_END_OFFSET      (wRxSrEoff),
+                 .RX_SR_SOP             (wRxSrSop),
+                 .RX_SR_START_OFFSET    (wRxSrSoff),
+                 .RX_SR_VALID           (wRxSrDataValid),
+                 // Outputs
+                 .RXC_DATA              (_RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
+                 /*AUTOINST*/
+                 // Outputs
+                 .RXC_DATA_VALID        (RXC_DATA_VALID),
+                 .RXC_DATA_WORD_ENABLE  (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXC_DATA_START_FLAG   (RXC_DATA_START_FLAG),
+                 .RXC_DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXC_DATA_END_FLAG     (RXC_DATA_END_FLAG),
+                 .RXC_DATA_END_OFFSET   (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXC_META_LDWBE        (RXC_META_LDWBE[`SIG_LBE_W-1:0]),
+                 .RXC_META_FDWBE        (RXC_META_FDWBE[`SIG_FBE_W-1:0]),
+                 .RXC_META_TAG          (RXC_META_TAG[`SIG_TAG_W-1:0]),
+                 .RXC_META_ADDR         (RXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
+                 .RXC_META_TYPE         (RXC_META_TYPE[`SIG_TYPE_W-1:0]),
+                 .RXC_META_LENGTH       (RXC_META_LENGTH[`SIG_LEN_W-1:0]),
+                 .RXC_META_BYTES_REMAINING(RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:0]),
+                 .RXC_META_COMPLETER_ID (RXC_META_COMPLETER_ID[`SIG_CPLID_W-1:0]),
+                 .RXC_META_EP           (RXC_META_EP),
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST_IN                (RST_IN),
+                 .RX_TLP                (RX_TLP[C_PCI_DATA_WIDTH-1:0]),
+                 .RX_TLP_VALID          (RX_TLP_VALID),
+                 .RX_TLP_START_FLAG     (RX_TLP_START_FLAG),
+                 .RX_TLP_START_OFFSET   (RX_TLP_START_OFFSET[`SIG_OFFSET_W-1:0]),
+                 .RX_TLP_END_FLAG       (RX_TLP_END_FLAG),
+                 .RX_TLP_END_OFFSET     (RX_TLP_END_OFFSET[`SIG_OFFSET_W-1:0]),
+                 .RX_TLP_BAR_DECODE     (RX_TLP_BAR_DECODE[`SIG_BARDECODE_W-1:0]));
+        end else begin // if (C_VENDOR != "XILINX" & C_PCI_DATA_WIDTH !=128)
+            rxr_engine_classic
+                #(
+                  // Parameters
+                  .C_VENDOR                        (C_VENDOR),
+                  .C_PCI_DATA_WIDTH                (C_PCI_DATA_WIDTH),
+                  .C_RX_PIPELINE_DEPTH             (C_RX_PIPELINE_DEPTH))
+            rxr_engine_inst
+                (
+                 // Inputs
+                 .RX_SR_DATA                       (wRxSrData),
+                 .RX_SR_EOP                        (wRxSrEop),
+                 .RX_SR_END_OFFSET                 (wRxSrEoff),
+                 .RX_SR_SOP                        (wRxSrSop),
+                 .RX_SR_VALID                      (wRxSrDataValid),
+                 // Outputs
+                 .RXR_DATA                      (_RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
+                 /*AUTOINST*/
+                 // Outputs
+                 .RXR_DATA_VALID        (RXR_DATA_VALID),
+                 .RXR_DATA_WORD_ENABLE  (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXR_DATA_START_FLAG   (RXR_DATA_START_FLAG),
+                 .RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXR_DATA_END_FLAG     (RXR_DATA_END_FLAG),
+                 .RXR_DATA_END_OFFSET   (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXR_META_FDWBE        (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
+                 .RXR_META_LDWBE        (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
+                 .RXR_META_TC           (RXR_META_TC[`SIG_TC_W-1:0]),
+                 .RXR_META_ATTR         (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
+                 .RXR_META_TAG          (RXR_META_TAG[`SIG_TAG_W-1:0]),
+                 .RXR_META_TYPE         (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
+                 .RXR_META_ADDR         (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
+                 .RXR_META_BAR_DECODED  (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
+                 .RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
+                 .RXR_META_LENGTH       (RXR_META_LENGTH[`SIG_LEN_W-1:0]),
+                 .RXR_META_EP           (RXR_META_EP),
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST_IN                (RST_IN),
+                 .RX_TLP                (RX_TLP[C_PCI_DATA_WIDTH-1:0]),
+                 .RX_TLP_VALID          (RX_TLP_VALID),
+                 .RX_TLP_START_FLAG     (RX_TLP_START_FLAG),
+                 .RX_TLP_START_OFFSET   (RX_TLP_START_OFFSET[`SIG_OFFSET_W-1:0]),
+                 .RX_TLP_END_FLAG       (RX_TLP_END_FLAG),
+                 .RX_TLP_END_OFFSET     (RX_TLP_END_OFFSET[`SIG_OFFSET_W-1:0]),
+                 .RX_TLP_BAR_DECODE     (RX_TLP_BAR_DECODE[`SIG_BARDECODE_W-1:0]));
+
+            rxc_engine_classic
+                #(
+                  // Parameters
+                  .C_VENDOR                        (C_VENDOR),
+                  .C_PCI_DATA_WIDTH                (C_PCI_DATA_WIDTH),
+                  .C_RX_PIPELINE_DEPTH             (C_RX_PIPELINE_DEPTH))
+            rxc_engine_inst
+                (
+                 // Inputs
+                 .RX_SR_DATA                       (wRxSrData),
+                 .RX_SR_EOP                        (wRxSrEop),
+                 .RX_SR_END_OFFSET                 (wRxSrEoff),
+                 .RX_SR_SOP                        (wRxSrSop),
+                 .RX_SR_VALID                      (wRxSrDataValid),
+                 // Outputs
+                 .RXC_DATA                      (_RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
+                 /*AUTOINST*/
+                 // Outputs
+                 .RXC_DATA_VALID        (RXC_DATA_VALID),
+                 .RXC_DATA_WORD_ENABLE  (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXC_DATA_START_FLAG   (RXC_DATA_START_FLAG),
+                 .RXC_DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXC_DATA_END_FLAG     (RXC_DATA_END_FLAG),
+                 .RXC_DATA_END_OFFSET   (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .RXC_META_LDWBE        (RXC_META_LDWBE[`SIG_LBE_W-1:0]),
+                 .RXC_META_FDWBE        (RXC_META_FDWBE[`SIG_FBE_W-1:0]),
+                 .RXC_META_TAG          (RXC_META_TAG[`SIG_TAG_W-1:0]),
+                 .RXC_META_ADDR         (RXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
+                 .RXC_META_TYPE         (RXC_META_TYPE[`SIG_TYPE_W-1:0]),
+                 .RXC_META_LENGTH       (RXC_META_LENGTH[`SIG_LEN_W-1:0]),
+                 .RXC_META_BYTES_REMAINING(RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:0]),
+                 .RXC_META_COMPLETER_ID (RXC_META_COMPLETER_ID[`SIG_CPLID_W-1:0]),
+                 .RXC_META_EP           (RXC_META_EP),
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST_IN                (RST_IN),
+                 .RX_TLP                (RX_TLP[C_PCI_DATA_WIDTH-1:0]),
+                 .RX_TLP_VALID          (RX_TLP_VALID),
+                 .RX_TLP_START_FLAG     (RX_TLP_START_FLAG),
+                 .RX_TLP_START_OFFSET   (RX_TLP_START_OFFSET[`SIG_OFFSET_W-1:0]),
+                 .RX_TLP_END_FLAG       (RX_TLP_END_FLAG),
+                 .RX_TLP_END_OFFSET     (RX_TLP_END_OFFSET[`SIG_OFFSET_W-1:0]),
+                 .RX_TLP_BAR_DECODE     (RX_TLP_BAR_DECODE[`SIG_BARDECODE_W-1:0]));
+        end // else: !if(C_VENDOR != "XILINX" & C_PCI_DATA_WIDTH !=128)
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../common/")
+// End:
diff --git a/fpga/riffa_hdl/rx_engine_ultrascale.v b/fpga/riffa_hdl/rx_engine_ultrascale.v
new file mode 100644
index 0000000..1985333
--- /dev/null
+++ b/fpga/riffa_hdl/rx_engine_ultrascale.v
@@ -0,0 +1,190 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            rx_engine_ultrascale.v
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The RX Engine (Ultrascale) takes a the two streams of
+// AXI from the Xilinx endpoint packets and provides the request packets on the
+// RXR Interface, and the completion packets on the RXC Interface.
+// This Engine is capable of operating at "line rate".
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "ultrascale.vh"
+`include "trellis.vh"
+module rx_engine_ultrascale
+    #(parameter C_PCI_DATA_WIDTH = 128
+      )
+    (
+     // Interface: Clocks
+     input                                    CLK,
+
+     // Interface: Resets
+     input                                    RST_IN,
+
+     // Interface: CQ
+     input                                    M_AXIS_CQ_TVALID,
+     input                                    M_AXIS_CQ_TLAST,
+     input [C_PCI_DATA_WIDTH-1:0]             M_AXIS_CQ_TDATA,
+     input [(C_PCI_DATA_WIDTH/32)-1:0]        M_AXIS_CQ_TKEEP,
+     input [`SIG_CQ_TUSER_W-1:0]              M_AXIS_CQ_TUSER,
+     output                                   M_AXIS_CQ_TREADY,
+    
+     // Interface: RC
+     input                                    M_AXIS_RC_TVALID,
+     input                                    M_AXIS_RC_TLAST,
+     input [C_PCI_DATA_WIDTH-1:0]             M_AXIS_RC_TDATA,
+     input [(C_PCI_DATA_WIDTH/32)-1:0]        M_AXIS_RC_TKEEP,
+     input [`SIG_RC_TUSER_W-1:0]              M_AXIS_RC_TUSER,
+     output                                   M_AXIS_RC_TREADY,
+
+     // Interface: RXC Engine
+     output [C_PCI_DATA_WIDTH-1:0]            RXC_DATA,
+     output                                   RXC_DATA_VALID,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]       RXC_DATA_WORD_ENABLE,
+     output                                   RXC_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
+     output                                   RXC_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
+
+     output [`SIG_LBE_W-1:0]                  RXC_META_LDWBE,
+     output [`SIG_FBE_W-1:0]                  RXC_META_FDWBE,
+     output [`SIG_TAG_W-1:0]                  RXC_META_TAG,
+     output [`SIG_LOWADDR_W-1:0]              RXC_META_ADDR,
+     output [`SIG_TYPE_W-1:0]                 RXC_META_TYPE,
+     output [`SIG_LEN_W-1:0]                  RXC_META_LENGTH,
+     output [`SIG_BYTECNT_W-1:0]              RXC_META_BYTES_REMAINING,
+     output [`SIG_CPLID_W-1:0]                RXC_META_COMPLETER_ID,
+     output                                   RXC_META_EP,
+
+     // Interface: RXR Engine
+     output [C_PCI_DATA_WIDTH-1:0]            RXR_DATA,
+     output                                   RXR_DATA_VALID,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]       RXR_DATA_WORD_ENABLE,
+     output                                   RXR_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
+     output                                   RXR_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
+    
+     output [`SIG_FBE_W-1:0]                  RXR_META_FDWBE,
+     output [`SIG_LBE_W-1:0]                  RXR_META_LDWBE,
+     output [`SIG_TC_W-1:0]                   RXR_META_TC,
+     output [`SIG_ATTR_W-1:0]                 RXR_META_ATTR,
+     output [`SIG_TAG_W-1:0]                  RXR_META_TAG,
+     output [`SIG_TYPE_W-1:0]                 RXR_META_TYPE,
+     output [`SIG_ADDR_W-1:0]                 RXR_META_ADDR,
+     output [`SIG_BARDECODE_W-1:0]            RXR_META_BAR_DECODED,
+     output [`SIG_REQID_W-1:0]                RXR_META_REQUESTER_ID,
+     output [`SIG_LEN_W-1:0]                  RXR_META_LENGTH,
+     output                                   RXR_META_EP
+     );
+
+    localparam C_RX_PIPELINE_DEPTH = 3;
+
+    rxc_engine_ultrascale
+        #(///*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH		(C_PCI_DATA_WIDTH),
+          .C_RX_PIPELINE_DEPTH		(C_RX_PIPELINE_DEPTH))
+    rxc_engine_inst
+        (/*AUTOINST*/
+         // Outputs
+         .M_AXIS_RC_TREADY              (M_AXIS_RC_TREADY),
+         .RXC_DATA                      (RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_VALID                (RXC_DATA_VALID),
+         .RXC_DATA_WORD_ENABLE          (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_START_FLAG           (RXC_DATA_START_FLAG),
+         .RXC_DATA_START_OFFSET         (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_END_FLAG             (RXC_DATA_END_FLAG),
+         .RXC_DATA_END_OFFSET           (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_LDWBE                (RXC_META_LDWBE[`SIG_LBE_W-1:0]),
+         .RXC_META_FDWBE                (RXC_META_FDWBE[`SIG_FBE_W-1:0]),
+         .RXC_META_TAG                  (RXC_META_TAG[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (RXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (RXC_META_TYPE[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (RXC_META_LENGTH[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (RXC_META_COMPLETER_ID[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (RXC_META_EP),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .M_AXIS_RC_TVALID              (M_AXIS_RC_TVALID),
+         .M_AXIS_RC_TLAST               (M_AXIS_RC_TLAST),
+         .M_AXIS_RC_TDATA               (M_AXIS_RC_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (M_AXIS_RC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (M_AXIS_RC_TUSER[`SIG_RC_TUSER_W-1:0]));
+
+    rxr_engine_ultrascale
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_RX_PIPELINE_DEPTH          (C_RX_PIPELINE_DEPTH))
+    rxr_engine_inst
+        (/*AUTOINST*/
+         // Outputs
+         .M_AXIS_CQ_TREADY              (M_AXIS_CQ_TREADY),
+         .RXR_DATA                      (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_VALID                (RXR_DATA_VALID),
+         .RXR_DATA_WORD_ENABLE          (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_START_FLAG           (RXR_DATA_START_FLAG),
+         .RXR_DATA_START_OFFSET         (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (RXR_DATA_END_FLAG),
+         .RXR_DATA_END_OFFSET           (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (RXR_META_TC[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (RXR_META_TAG[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (RXR_META_LENGTH[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (RXR_META_EP),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .M_AXIS_CQ_TVALID              (M_AXIS_CQ_TVALID),
+         .M_AXIS_CQ_TLAST               (M_AXIS_CQ_TLAST),
+         .M_AXIS_CQ_TDATA               (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (M_AXIS_CQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (M_AXIS_CQ_TUSER[`SIG_CQ_TUSER_W-1:0]));
+
+endmodule // rx_engine_ultrascale
+// Local Variables:
+// verilog-library-directories:("." "./rx/")
+// End:
diff --git a/fpga/riffa_hdl/rx_port_128.v b/fpga/riffa_hdl/rx_port_128.v
new file mode 100644
index 0000000..0ec08c9
--- /dev/null
+++ b/fpga/riffa_hdl/rx_port_128.v
@@ -0,0 +1,515 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			rx_port_128.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Receives data from the rx_engine and buffers the output 
+//						for the RIFFA channel.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+module rx_port_128 #(
+	parameter C_DATA_WIDTH = 9'd128,
+	parameter C_MAIN_FIFO_DEPTH = 1024,
+	parameter C_SG_FIFO_DEPTH = 512,
+	parameter C_MAX_READ_REQ = 2,					// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+	// Local parameters
+	parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),
+	parameter C_MAIN_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_MAIN_FIFO_DEPTH))+1),
+	parameter C_SG_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_SG_FIFO_DEPTH))+1)
+)
+(
+	input CLK,
+	input RST,
+	input [2:0] CONFIG_MAX_READ_REQUEST_SIZE,				// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+
+	output SG_RX_BUF_RECVD,							// Scatter gather RX buffer completely read (ready for next if applicable)
+	input [31:0] SG_RX_BUF_DATA,					// Scatter gather RX buffer data
+	input SG_RX_BUF_LEN_VALID,						// Scatter gather RX buffer length valid
+	input SG_RX_BUF_ADDR_HI_VALID,					// Scatter gather RX buffer high address valid
+	input SG_RX_BUF_ADDR_LO_VALID,					// Scatter gather RX buffer low address valid
+
+	output SG_TX_BUF_RECVD,							// Scatter gather TX buffer completely read (ready for next if applicable)
+	input [31:0] SG_TX_BUF_DATA,					// Scatter gather TX buffer data
+	input SG_TX_BUF_LEN_VALID,						// Scatter gather TX buffer length valid
+	input SG_TX_BUF_ADDR_HI_VALID,					// Scatter gather TX buffer high address valid
+	input SG_TX_BUF_ADDR_LO_VALID,					// Scatter gather TX buffer low address valid
+
+	output [C_DATA_WIDTH-1:0] SG_DATA,				// Scatter gather TX buffer data
+	output SG_DATA_EMPTY,							// Scatter gather TX buffer data empty
+	input SG_DATA_REN,								// Scatter gather TX buffer data read enable
+	input SG_RST,									// Scatter gather TX buffer data reset
+	output SG_ERR,									// Scatter gather TX encountered an error
+	
+	input [31:0] TXN_DATA,							// Read transaction data
+	input TXN_LEN_VALID,							// Read transaction length valid
+	input TXN_OFF_LAST_VALID,						// Read transaction offset/last valid
+	output [31:0] TXN_DONE_LEN,						// Read transaction actual transfer length
+	output TXN_DONE,								// Read transaction done
+	input TXN_DONE_ACK,								// Read transaction actual transfer length read
+
+	output RX_REQ,									// Read request
+	input RX_REQ_ACK,								// Read request accepted
+	output [1:0] RX_REQ_TAG,						// Read request data tag 
+	output [63:0] RX_REQ_ADDR,						// Read request address
+	output [9:0] RX_REQ_LEN,						// Read request length
+
+	input [C_DATA_WIDTH-1:0] MAIN_DATA,				// Main incoming data 
+	input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN,		// Main incoming data enable
+	input MAIN_DONE,								// Main incoming data complete
+	input MAIN_ERR,									// Main incoming data completed with error
+	input [C_DATA_WIDTH-1:0] SG_RX_DATA,			// Scatter gather for RX incoming data 
+	input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN,	// Scatter gather for RX incoming data enable
+	input SG_RX_DONE,								// Scatter gather for RX incoming data complete
+	input SG_RX_ERR,								// Scatter gather for RX incoming data completed with error
+	input [C_DATA_WIDTH-1:0] SG_TX_DATA,			// Scatter gather for TX incoming data 
+	input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN,	// Scatter gather for TX incoming data enable
+	input SG_TX_DONE,								// Scatter gather for TX incoming data complete
+	input SG_TX_ERR,								// Scatter gather for TX incoming data completed with error
+
+	input CHNL_CLK,									// Channel read clock
+	output CHNL_RX,									// Channel read receive signal
+	input CHNL_RX_ACK,								// Channle read received signal
+	output CHNL_RX_LAST,							// Channel last read
+	output [31:0] CHNL_RX_LEN,						// Channel read length
+	output [30:0] CHNL_RX_OFF,						// Channel read offset
+	output [C_DATA_WIDTH-1:0] CHNL_RX_DATA,			// Channel read data
+	output CHNL_RX_DATA_VALID,						// Channel read data valid
+	input CHNL_RX_DATA_REN							// Channel read data has been recieved
+);
+
+`include "functions.vh"
+
+
+
+
+wire	[C_DATA_WIDTH-1:0]			wPackedMainData;
+wire								wPackedMainWen;
+wire								wPackedMainDone;
+wire								wPackedMainErr;
+wire								wMainFlush;
+wire								wMainFlushed;
+
+wire	[C_DATA_WIDTH-1:0]			wPackedSgRxData;
+wire								wPackedSgRxWen;
+wire								wPackedSgRxDone;
+wire								wPackedSgRxErr;
+wire								wSgRxFlush;
+wire								wSgRxFlushed;
+
+wire	[C_DATA_WIDTH-1:0]			wPackedSgTxData;
+wire								wPackedSgTxWen;
+wire								wPackedSgTxDone;
+wire								wPackedSgTxErr;
+wire								wSgTxFlush;
+wire								wSgTxFlushed;
+
+wire								wMainDataRen;
+wire								wMainDataEmpty;
+wire	[C_DATA_WIDTH-1:0]			wMainData;
+
+wire								wSgRxRst;
+wire								wSgRxDataRen;
+wire								wSgRxDataEmpty;
+wire	[C_DATA_WIDTH-1:0]			wSgRxData;
+wire	[C_SG_FIFO_DEPTH_WIDTH-1:0]	wSgRxFifoCount;
+
+wire								wSgTxRst;
+wire	[C_SG_FIFO_DEPTH_WIDTH-1:0]	wSgTxFifoCount;
+
+wire								wSgRxReq;
+wire	[63:0]						wSgRxReqAddr;
+wire	[9:0]						wSgRxReqLen;
+
+wire								wSgTxReq;
+wire	[63:0]						wSgTxReqAddr;
+wire	[9:0]						wSgTxReqLen;
+
+wire								wSgRxReqProc;
+wire								wSgTxReqProc;
+wire								wMainReqProc;
+wire								wReqAck;
+
+wire								wSgElemRdy;
+wire								wSgElemRen;
+wire	[63:0]						wSgElemAddr;
+wire	[31:0]						wSgElemLen;
+
+wire								wSgRst;
+wire								wMainReq;
+wire	[63:0]						wMainReqAddr;
+wire	[9:0]						wMainReqLen;
+wire								wTxnErr;
+wire								wChnlRx;
+wire								wChnlRxRecvd;
+wire								wChnlRxAckRecvd;
+wire								wChnlRxLast;
+wire	[31:0]						wChnlRxLen;
+wire	[30:0]						wChnlRxOff;
+wire	[31:0]						wChnlRxConsumed;
+
+reg		[4:0]						rWideRst=0;
+reg									rRst=0;
+
+assign SG_ERR = (wPackedSgTxDone & wPackedSgTxErr);
+
+// Generate a wide reset from the input reset.
+always @ (posedge CLK) begin
+	rRst <= #1 rWideRst[4]; 
+	if (RST) 
+		rWideRst <= #1 5'b11111;
+	else 
+		rWideRst <= (rWideRst<<1);
+end
+
+
+// Pack received data tightly into our FIFOs 
+fifo_packer_128 mainFifoPacker (
+	.CLK(CLK),
+	.RST(rRst),
+	.DATA_IN(MAIN_DATA),
+	.DATA_IN_EN(MAIN_DATA_EN),
+	.DATA_IN_DONE(MAIN_DONE),
+	.DATA_IN_ERR(MAIN_ERR),
+	.DATA_IN_FLUSH(wMainFlush),
+	.PACKED_DATA(wPackedMainData),
+	.PACKED_WEN(wPackedMainWen),
+	.PACKED_DATA_DONE(wPackedMainDone),
+	.PACKED_DATA_ERR(wPackedMainErr),
+	.PACKED_DATA_FLUSHED(wMainFlushed)
+);
+
+fifo_packer_128 sgRxFifoPacker (
+	.CLK(CLK),
+	.RST(rRst),
+	.DATA_IN(SG_RX_DATA),
+	.DATA_IN_EN(SG_RX_DATA_EN),
+	.DATA_IN_DONE(SG_RX_DONE),
+	.DATA_IN_ERR(SG_RX_ERR),
+	.DATA_IN_FLUSH(wSgRxFlush),
+	.PACKED_DATA(wPackedSgRxData),
+	.PACKED_WEN(wPackedSgRxWen),
+	.PACKED_DATA_DONE(wPackedSgRxDone),
+	.PACKED_DATA_ERR(wPackedSgRxErr),
+	.PACKED_DATA_FLUSHED(wSgRxFlushed)
+);
+
+fifo_packer_128 sgTxFifoPacker (
+	.CLK(CLK),
+	.RST(rRst),
+	.DATA_IN(SG_TX_DATA),
+	.DATA_IN_EN(SG_TX_DATA_EN),
+	.DATA_IN_DONE(SG_TX_DONE),
+	.DATA_IN_ERR(SG_TX_ERR),
+	.DATA_IN_FLUSH(wSgTxFlush),
+	.PACKED_DATA(wPackedSgTxData),
+	.PACKED_WEN(wPackedSgTxWen),
+	.PACKED_DATA_DONE(wPackedSgTxDone),
+	.PACKED_DATA_ERR(wPackedSgTxErr),
+	.PACKED_DATA_FLUSHED(wSgTxFlushed)
+);
+
+
+// FIFOs for storing received data for the channel.
+(* RAM_STYLE="BLOCK" *)
+async_fifo_fwft #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_MAIN_FIFO_DEPTH)) mainFifo (
+	.WR_CLK(CLK),
+	.WR_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
+	.WR_EN(wPackedMainWen),
+	.WR_DATA(wPackedMainData),
+	.WR_FULL(),
+	.RD_CLK(CHNL_CLK),
+	.RD_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
+	.RD_EN(wMainDataRen),
+	.RD_DATA(wMainData),
+	.RD_EMPTY(wMainDataEmpty)
+);
+
+(* RAM_STYLE="BLOCK" *)
+sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgRxFifo (
+	.RST(rRst | wSgRxRst),
+	.CLK(CLK),
+	.WR_EN(wPackedSgRxWen),
+	.WR_DATA(wPackedSgRxData),
+	.FULL(),
+	.RD_EN(wSgRxDataRen),
+	.RD_DATA(wSgRxData),
+	.EMPTY(wSgRxDataEmpty),
+	.COUNT(wSgRxFifoCount)
+);
+
+(* RAM_STYLE="BLOCK" *)
+sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgTxFifo (
+	.RST(rRst | wSgTxRst),
+	.CLK(CLK),
+	.WR_EN(wPackedSgTxWen),
+	.WR_DATA(wPackedSgTxData),
+	.FULL(),
+	.RD_EN(SG_DATA_REN),
+	.RD_DATA(SG_DATA),
+	.EMPTY(SG_DATA_EMPTY),
+	.COUNT(wSgTxFifoCount)
+);
+
+
+// Manage requesting and acknowledging scatter gather data. Note that
+// these modules will share the main requestor's RX channel. They will
+// take priority over the main logic's use of the RX channel.
+sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgRxReq (
+	.CLK(CLK),
+	.RST(rRst),
+	.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
+	.USER_RST(wSgRst),
+	.BUF_RECVD(SG_RX_BUF_RECVD),
+	.BUF_DATA(SG_RX_BUF_DATA),
+	.BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
+	.BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
+	.BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
+	.FIFO_COUNT(wSgRxFifoCount),
+	.FIFO_FLUSH(wSgRxFlush),
+	.FIFO_FLUSHED(wSgRxFlushed),
+	.FIFO_RST(wSgRxRst),
+	.RX_REQ(wSgRxReq),
+	.RX_ADDR(wSgRxReqAddr),
+	.RX_LEN(wSgRxReqLen),
+	.RX_REQ_ACK(wReqAck & wSgRxReqProc),
+	.RX_DONE(wPackedSgRxDone)
+);
+
+sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgTxReq (
+	.CLK(CLK),
+	.RST(rRst),
+	.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
+	.USER_RST(SG_RST),
+	.BUF_RECVD(SG_TX_BUF_RECVD),
+	.BUF_DATA(SG_TX_BUF_DATA),
+	.BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
+	.BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
+	.BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
+	.FIFO_COUNT(wSgTxFifoCount),
+	.FIFO_FLUSH(wSgTxFlush),
+	.FIFO_FLUSHED(wSgTxFlushed),
+	.FIFO_RST(wSgTxRst),
+	.RX_REQ(wSgTxReq),
+	.RX_ADDR(wSgTxReqAddr),
+	.RX_LEN(wSgTxReqLen),
+	.RX_REQ_ACK(wReqAck & wSgTxReqProc),
+	.RX_DONE(wPackedSgTxDone)
+);
+
+
+// A read requester for the channel and scatter gather requesters.
+rx_port_requester_mux requesterMux (
+	.RST(rRst), 
+	.CLK(CLK), 
+	.SG_RX_REQ(wSgRxReq), 
+	.SG_RX_LEN(wSgRxReqLen), 
+	.SG_RX_ADDR(wSgRxReqAddr), 
+	.SG_RX_REQ_PROC(wSgRxReqProc),
+	.SG_TX_REQ(wSgTxReq), 
+	.SG_TX_LEN(wSgTxReqLen), 
+	.SG_TX_ADDR(wSgTxReqAddr), 
+	.SG_TX_REQ_PROC(wSgTxReqProc),
+	.MAIN_REQ(wMainReq), 
+	.MAIN_LEN(wMainReqLen), 
+	.MAIN_ADDR(wMainReqAddr), 
+	.MAIN_REQ_PROC(wMainReqProc),
+	.RX_REQ(RX_REQ),
+	.RX_REQ_ACK(RX_REQ_ACK),
+	.RX_REQ_TAG(RX_REQ_TAG),
+	.RX_REQ_ADDR(RX_REQ_ADDR),
+	.RX_REQ_LEN(RX_REQ_LEN),
+	.REQ_ACK(wReqAck)
+);
+
+
+// Read the scatter gather buffer address and length, continuously so that
+// we have it ready whenever the next buffer is needed.
+sg_list_reader_128 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
+	.CLK(CLK),
+	.RST(rRst | wSgRst),
+	.BUF_DATA(wSgRxData),
+	.BUF_DATA_EMPTY(wSgRxDataEmpty),
+	.BUF_DATA_REN(wSgRxDataRen),
+	.VALID(wSgElemRdy),
+	.EMPTY(),
+	.REN(wSgElemRen),
+	.ADDR(wSgElemAddr),
+	.LEN(wSgElemLen)
+);
+
+
+// Main port reader logic
+rx_port_reader #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_MAIN_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) reader (
+	.CLK(CLK), 
+	.RST(rRst), 
+	.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
+	.TXN_DATA(TXN_DATA), 
+	.TXN_LEN_VALID(TXN_LEN_VALID), 
+	.TXN_OFF_LAST_VALID(TXN_OFF_LAST_VALID), 
+	.TXN_DONE_LEN(TXN_DONE_LEN),
+	.TXN_DONE(TXN_DONE),
+	.TXN_ERR(wTxnErr),
+	.TXN_DONE_ACK(TXN_DONE_ACK),
+	.TXN_DATA_FLUSH(wMainFlush),
+	.TXN_DATA_FLUSHED(wMainFlushed),
+	.RX_REQ(wMainReq),
+	.RX_ADDR(wMainReqAddr),
+	.RX_LEN(wMainReqLen),
+	.RX_REQ_ACK(wReqAck & wMainReqProc),
+	.RX_DATA_EN(MAIN_DATA_EN), 
+	.RX_DONE(wPackedMainDone),
+	.RX_ERR(wPackedMainErr),
+	.SG_DONE(wPackedSgRxDone), 
+	.SG_ERR(wPackedSgRxErr), 
+	.SG_ELEM_ADDR(wSgElemAddr), 
+	.SG_ELEM_LEN(wSgElemLen),
+	.SG_ELEM_RDY(wSgElemRdy),
+	.SG_ELEM_REN(wSgElemRen),
+	.SG_RST(wSgRst),
+	.CHNL_RX(wChnlRx), 
+	.CHNL_RX_LEN(wChnlRxLen), 
+	.CHNL_RX_LAST(wChnlRxLast),
+	.CHNL_RX_OFF(wChnlRxOff), 
+	.CHNL_RX_RECVD(wChnlRxRecvd), 
+	.CHNL_RX_ACK_RECVD(wChnlRxAckRecvd), 
+	.CHNL_RX_CONSUMED(wChnlRxConsumed)
+);
+
+
+// Manage the CHNL_RX* signals in the CHNL_CLK domain.
+rx_port_channel_gate #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
+	.RST(rRst), 
+	.CLK(CLK), 
+	.RX(wChnlRx), 
+	.RX_RECVD(wChnlRxRecvd), 
+	.RX_ACK_RECVD(wChnlRxAckRecvd), 
+	.RX_LAST(wChnlRxLast), 
+	.RX_LEN(wChnlRxLen), 
+	.RX_OFF(wChnlRxOff), 
+	.RX_CONSUMED(wChnlRxConsumed), 
+	.RD_DATA(wMainData), 
+	.RD_EMPTY(wMainDataEmpty), 
+	.RD_EN(wMainDataRen), 
+	.CHNL_CLK(CHNL_CLK), 
+	.CHNL_RX(CHNL_RX), 
+	.CHNL_RX_ACK(CHNL_RX_ACK), 
+	.CHNL_RX_LAST(CHNL_RX_LAST), 
+	.CHNL_RX_LEN(CHNL_RX_LEN), 
+	.CHNL_RX_OFF(CHNL_RX_OFF), 
+	.CHNL_RX_DATA(CHNL_RX_DATA), 
+	.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID), 
+	.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
+);
+
+
+
+/*
+reg [31:0] rCounter=0;
+always @ (posedge CLK) begin
+	if (RST)
+		rCounter <= #1 0;
+	else
+		rCounter <= #1 (RX_REQ_ACK ? rCounter + 1 : rCounter);
+end
+
+
+wire [35:0] wControl0;
+chipscope_icon_1 cs_icon(
+	.CONTROL0(wControl0)
+);
+
+chipscope_ila_t8_512_max a0(
+	.CLK(CLK), 
+	.CONTROL(wControl0), 
+	.TRIG0({(SG_RX_DATA_EN != 0) | (MAIN_DATA_EN != 0), 
+			RX_REQ_ACK, 
+			wSgElemRen, 
+			(SG_RX_BUF_ADDR_LO_VALID | SG_RX_BUF_ADDR_HI_VALID | SG_RX_BUF_LEN_VALID | SG_TX_BUF_ADDR_HI_VALID | SG_TX_BUF_LEN_VALID | TXN_OFF_LAST_VALID | TXN_LEN_VALID | wSgRst), 
+			rCounter[10:7]}),
+//	.TRIG0({wSgRxReq & wSgRxReqProc & wReqAck, 
+//			wSgElemRen, 
+//			wMainReq | wSgRxReq | wSgTxReq, 
+//			(SG_RX_DATA_EN != 0), 
+//			SG_RX_BUF_ADDR_LO_VALID | SG_RX_BUF_ADDR_HI_VALID | SG_RX_BUF_LEN_VALID | TXN_OFF_LAST_VALID | TXN_LEN_VALID, 
+//			rSgElemRenCount > 1100, 
+//			wSgRst | wTxnErr | wSgRxFlush | wSgRxFlushed, 
+//			wPackedSgRxDone | wPackedSgRxErr}),
+	.DATA({
+			MAIN_DATA_EN, // 3
+			//wPackedSgRxData, // 128
+			SG_RX_DONE, // 1
+			SG_RX_DATA_EN, // 3
+			SG_RX_DATA, // 128
+			wSgRxDataRen, // 1
+			wSgRxDataEmpty, // 1
+			MAIN_DATA, // 128
+			wSgRst, // 1
+			SG_RST, // 1
+			wPackedSgRxDone, // 1
+			wSgRxRst, // 1
+			wSgRxFlushed, // 1
+			wSgRxFlush, // 1
+			SG_RX_BUF_ADDR_LO_VALID, // 1
+			SG_RX_BUF_ADDR_HI_VALID, // 1 
+			SG_RX_BUF_LEN_VALID, // 1
+			//SG_RX_BUF_DATA, // 32
+				rCounter, // 32
+			RX_REQ_ADDR, // 64
+			RX_REQ_TAG, // 2
+			RX_REQ_ACK, // 1
+			RX_REQ, // 1
+			wSgTxReqProc, // 1
+			wSgTxReq, // 1
+			wSgRxReqProc, // 1
+			//wSgRxReqAddr, // 64
+				//wSgElemAddr, // 64
+				44'd0, // 44
+				wSgRxReqLen, // 10
+				RX_REQ_LEN, // 10
+			wSgRxReq, // 1
+			wMainReqProc, // 1
+			wMainReqAddr, // 64
+			wMainReq, // 1
+			wReqAck, // 1
+			wTxnErr, // 1
+			TXN_OFF_LAST_VALID, // 1
+			TXN_LEN_VALID}) // 1
+);
+*/
+
+endmodule
diff --git a/fpga/riffa_hdl/rx_port_32.v b/fpga/riffa_hdl/rx_port_32.v
new file mode 100644
index 0000000..1ad6ebd
--- /dev/null
+++ b/fpga/riffa_hdl/rx_port_32.v
@@ -0,0 +1,494 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			rx_port_32.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Receives data from the rx_engine and buffers the output 
+//						for the RIFFA channel.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+module rx_port_32 #(
+	parameter C_DATA_WIDTH = 9'd32,
+	parameter C_MAIN_FIFO_DEPTH = 1024,
+	parameter C_SG_FIFO_DEPTH = 512,
+	parameter C_MAX_READ_REQ = 2,					// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+	// Local parameters
+	parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),
+	parameter C_MAIN_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_MAIN_FIFO_DEPTH))+1),
+	parameter C_SG_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_SG_FIFO_DEPTH))+1)
+)
+(
+	input CLK,
+	input RST,
+	input [2:0] CONFIG_MAX_READ_REQUEST_SIZE,				// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+
+	output SG_RX_BUF_RECVD,							// Scatter gather RX buffer completely read (ready for next if applicable)
+	input [31:0] SG_RX_BUF_DATA,					// Scatter gather RX buffer data
+	input SG_RX_BUF_LEN_VALID,						// Scatter gather RX buffer length valid
+	input SG_RX_BUF_ADDR_HI_VALID,					// Scatter gather RX buffer high address valid
+	input SG_RX_BUF_ADDR_LO_VALID,					// Scatter gather RX buffer low address valid
+
+	output SG_TX_BUF_RECVD,							// Scatter gather TX buffer completely read (ready for next if applicable)
+	input [31:0] SG_TX_BUF_DATA,					// Scatter gather TX buffer data
+	input SG_TX_BUF_LEN_VALID,						// Scatter gather TX buffer length valid
+	input SG_TX_BUF_ADDR_HI_VALID,					// Scatter gather TX buffer high address valid
+	input SG_TX_BUF_ADDR_LO_VALID,					// Scatter gather TX buffer low address valid
+
+	output [C_DATA_WIDTH-1:0] SG_DATA,				// Scatter gather TX buffer data
+	output SG_DATA_EMPTY,							// Scatter gather TX buffer data empty
+	input SG_DATA_REN,								// Scatter gather TX buffer data read enable
+	input SG_RST,									// Scatter gather TX buffer data reset
+	output SG_ERR,									// Scatter gather TX encountered an error
+	
+	input [31:0] TXN_DATA,							// Read transaction data
+	input TXN_LEN_VALID,							// Read transaction length valid
+	input TXN_OFF_LAST_VALID,						// Read transaction offset/last valid
+	output [31:0] TXN_DONE_LEN,						// Read transaction actual transfer length
+	output TXN_DONE,								// Read transaction done
+	input TXN_DONE_ACK,								// Read transaction actual transfer length read
+
+	output RX_REQ,									// Read request
+	input RX_REQ_ACK,								// Read request accepted
+	output [1:0] RX_REQ_TAG,						// Read request data tag 
+	output [63:0] RX_REQ_ADDR,						// Read request address
+	output [9:0] RX_REQ_LEN,						// Read request length
+
+	input [C_DATA_WIDTH-1:0] MAIN_DATA,				// Main incoming data 
+	input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN,		// Main incoming data enable
+	input MAIN_DONE,								// Main incoming data complete
+	input MAIN_ERR,									// Main incoming data completed with error
+	input [C_DATA_WIDTH-1:0] SG_RX_DATA,			// Scatter gather for RX incoming data 
+	input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN,	// Scatter gather for RX incoming data enable
+	input SG_RX_DONE,								// Scatter gather for RX incoming data complete
+	input SG_RX_ERR,								// Scatter gather for RX incoming data completed with error
+	input [C_DATA_WIDTH-1:0] SG_TX_DATA,			// Scatter gather for TX incoming data 
+	input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN,	// Scatter gather for TX incoming data enable
+	input SG_TX_DONE,								// Scatter gather for TX incoming data complete
+	input SG_TX_ERR,								// Scatter gather for TX incoming data completed with error
+
+	input CHNL_CLK,									// Channel read clock
+	output CHNL_RX,									// Channel read receive signal
+	input CHNL_RX_ACK,								// Channle read received signal
+	output CHNL_RX_LAST,							// Channel last read
+	output [31:0] CHNL_RX_LEN,						// Channel read length
+	output [30:0] CHNL_RX_OFF,						// Channel read offset
+	output [C_DATA_WIDTH-1:0] CHNL_RX_DATA,			// Channel read data
+	output CHNL_RX_DATA_VALID,						// Channel read data valid
+	input CHNL_RX_DATA_REN							// Channel read data has been recieved
+);
+
+`include "functions.vh"
+
+
+
+
+wire	[C_DATA_WIDTH-1:0]			wPackedMainData;
+wire								wPackedMainWen;
+wire								wPackedMainDone;
+wire								wPackedMainErr;
+wire								wMainFlush;
+wire								wMainFlushed;
+
+wire	[C_DATA_WIDTH-1:0]			wPackedSgRxData;
+wire								wPackedSgRxWen;
+wire								wPackedSgRxDone;
+wire								wPackedSgRxErr;
+wire								wSgRxFlush;
+wire								wSgRxFlushed;
+
+wire	[C_DATA_WIDTH-1:0]			wPackedSgTxData;
+wire								wPackedSgTxWen;
+wire								wPackedSgTxDone;
+wire								wPackedSgTxErr;
+wire								wSgTxFlush;
+wire								wSgTxFlushed;
+
+wire								wMainDataRen;
+wire								wMainDataEmpty;
+wire	[C_DATA_WIDTH-1:0]			wMainData;
+
+wire								wSgRxRst;
+wire								wSgRxDataRen;
+wire								wSgRxDataEmpty;
+wire	[C_DATA_WIDTH-1:0]			wSgRxData;
+wire	[C_SG_FIFO_DEPTH_WIDTH-1:0]	wSgRxFifoCount;
+
+wire								wSgTxRst;
+wire	[C_SG_FIFO_DEPTH_WIDTH-1:0]	wSgTxFifoCount;
+
+wire								wSgRxReq;
+wire	[63:0]						wSgRxReqAddr;
+wire	[9:0]						wSgRxReqLen;
+
+wire								wSgTxReq;
+wire	[63:0]						wSgTxReqAddr;
+wire	[9:0]						wSgTxReqLen;
+
+wire								wSgRxReqProc;
+wire								wSgTxReqProc;
+wire								wMainReqProc;
+wire								wReqAck;
+
+wire								wSgElemRdy;
+wire								wSgElemRen;
+wire	[63:0]						wSgElemAddr;
+wire	[31:0]						wSgElemLen;
+
+wire								wSgRst;
+wire								wMainReq;
+wire	[63:0]						wMainReqAddr;
+wire	[9:0]						wMainReqLen;
+wire								wTxnErr;
+wire								wChnlRx;
+wire								wChnlRxRecvd;
+wire								wChnlRxAckRecvd;
+wire								wChnlRxLast;
+wire	[31:0]						wChnlRxLen;
+wire	[30:0]						wChnlRxOff;
+wire	[31:0]						wChnlRxConsumed;
+
+reg		[4:0]						rWideRst=0;
+reg									rRst=0;
+
+assign SG_ERR = (wPackedSgTxDone & wPackedSgTxErr);
+
+// Generate a wide reset from the input reset.
+always @ (posedge CLK) begin
+	rRst <= #1 rWideRst[4]; 
+	if (RST) 
+		rWideRst <= #1 5'b11111;
+	else 
+		rWideRst <= (rWideRst<<1);
+end
+
+
+// Pack received data tightly into our FIFOs 
+fifo_packer_32 mainFifoPacker (
+	.CLK(CLK),
+	.RST(rRst),
+	.DATA_IN(MAIN_DATA),
+	.DATA_IN_EN(MAIN_DATA_EN),
+	.DATA_IN_DONE(MAIN_DONE),
+	.DATA_IN_ERR(MAIN_ERR),
+	.DATA_IN_FLUSH(wMainFlush),
+	.PACKED_DATA(wPackedMainData),
+	.PACKED_WEN(wPackedMainWen),
+	.PACKED_DATA_DONE(wPackedMainDone),
+	.PACKED_DATA_ERR(wPackedMainErr),
+	.PACKED_DATA_FLUSHED(wMainFlushed)
+);
+
+fifo_packer_32 sgRxFifoPacker (
+	.CLK(CLK),
+	.RST(rRst),
+	.DATA_IN(SG_RX_DATA),
+	.DATA_IN_EN(SG_RX_DATA_EN),
+	.DATA_IN_DONE(SG_RX_DONE),
+	.DATA_IN_ERR(SG_RX_ERR),
+	.DATA_IN_FLUSH(wSgRxFlush),
+	.PACKED_DATA(wPackedSgRxData),
+	.PACKED_WEN(wPackedSgRxWen),
+	.PACKED_DATA_DONE(wPackedSgRxDone),
+	.PACKED_DATA_ERR(wPackedSgRxErr),
+	.PACKED_DATA_FLUSHED(wSgRxFlushed)
+);
+
+fifo_packer_32 sgTxFifoPacker (
+	.CLK(CLK),
+	.RST(rRst),
+	.DATA_IN(SG_TX_DATA),
+	.DATA_IN_EN(SG_TX_DATA_EN),
+	.DATA_IN_DONE(SG_TX_DONE),
+	.DATA_IN_ERR(SG_TX_ERR),
+	.DATA_IN_FLUSH(wSgTxFlush),
+	.PACKED_DATA(wPackedSgTxData),
+	.PACKED_WEN(wPackedSgTxWen),
+	.PACKED_DATA_DONE(wPackedSgTxDone),
+	.PACKED_DATA_ERR(wPackedSgTxErr),
+	.PACKED_DATA_FLUSHED(wSgTxFlushed)
+);
+
+
+// FIFOs for storing received data for the channel.
+(* RAM_STYLE="BLOCK" *)
+async_fifo_fwft #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_MAIN_FIFO_DEPTH)) mainFifo (
+	.WR_CLK(CLK),
+	.WR_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
+	.WR_EN(wPackedMainWen),
+	.WR_DATA(wPackedMainData),
+	.WR_FULL(),
+	.RD_CLK(CHNL_CLK),
+	.RD_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
+	.RD_EN(wMainDataRen),
+	.RD_DATA(wMainData),
+	.RD_EMPTY(wMainDataEmpty)
+);
+
+(* RAM_STYLE="BLOCK" *)
+sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgRxFifo (
+	.RST(rRst | wSgRxRst),
+	.CLK(CLK),
+	.WR_EN(wPackedSgRxWen),
+	.WR_DATA(wPackedSgRxData),
+	.FULL(),
+	.RD_EN(wSgRxDataRen),
+	.RD_DATA(wSgRxData),
+	.EMPTY(wSgRxDataEmpty),
+	.COUNT(wSgRxFifoCount)
+);
+
+(* RAM_STYLE="BLOCK" *)
+sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgTxFifo (
+	.RST(rRst | wSgTxRst),
+	.CLK(CLK),
+	.WR_EN(wPackedSgTxWen),
+	.WR_DATA(wPackedSgTxData),
+	.FULL(),
+	.RD_EN(SG_DATA_REN),
+	.RD_DATA(SG_DATA),
+	.EMPTY(SG_DATA_EMPTY),
+	.COUNT(wSgTxFifoCount)
+);
+
+
+// Manage requesting and acknowledging scatter gather data. Note that
+// these modules will share the main requestor's RX channel. They will
+// take priority over the main logic's use of the RX channel.
+sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgRxReq (
+	.CLK(CLK),
+	.RST(rRst),
+	.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
+	.USER_RST(wSgRst),
+	.BUF_RECVD(SG_RX_BUF_RECVD),
+	.BUF_DATA(SG_RX_BUF_DATA),
+	.BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
+	.BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
+	.BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
+	.FIFO_COUNT(wSgRxFifoCount),
+	.FIFO_FLUSH(wSgRxFlush),
+	.FIFO_FLUSHED(wSgRxFlushed),
+	.FIFO_RST(wSgRxRst),
+	.RX_REQ(wSgRxReq),
+	.RX_ADDR(wSgRxReqAddr),
+	.RX_LEN(wSgRxReqLen),
+	.RX_REQ_ACK(wReqAck & wSgRxReqProc),
+	.RX_DONE(wPackedSgRxDone)
+);
+
+sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgTxReq (
+	.CLK(CLK),
+	.RST(rRst),
+	.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
+	.USER_RST(SG_RST),
+	.BUF_RECVD(SG_TX_BUF_RECVD),
+	.BUF_DATA(SG_TX_BUF_DATA),
+	.BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
+	.BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
+	.BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
+	.FIFO_COUNT(wSgTxFifoCount),
+	.FIFO_FLUSH(wSgTxFlush),
+	.FIFO_FLUSHED(wSgTxFlushed),
+	.FIFO_RST(wSgTxRst),
+	.RX_REQ(wSgTxReq),
+	.RX_ADDR(wSgTxReqAddr),
+	.RX_LEN(wSgTxReqLen),
+	.RX_REQ_ACK(wReqAck & wSgTxReqProc),
+	.RX_DONE(wPackedSgTxDone)
+);
+
+
+// A read requester for the channel and scatter gather requesters.
+rx_port_requester_mux requesterMux (
+	.RST(rRst), 
+	.CLK(CLK), 
+	.SG_RX_REQ(wSgRxReq), 
+	.SG_RX_LEN(wSgRxReqLen), 
+	.SG_RX_ADDR(wSgRxReqAddr), 
+	.SG_RX_REQ_PROC(wSgRxReqProc),
+	.SG_TX_REQ(wSgTxReq), 
+	.SG_TX_LEN(wSgTxReqLen), 
+	.SG_TX_ADDR(wSgTxReqAddr), 
+	.SG_TX_REQ_PROC(wSgTxReqProc),
+	.MAIN_REQ(wMainReq), 
+	.MAIN_LEN(wMainReqLen), 
+	.MAIN_ADDR(wMainReqAddr), 
+	.MAIN_REQ_PROC(wMainReqProc),
+	.RX_REQ(RX_REQ),
+	.RX_REQ_ACK(RX_REQ_ACK),
+	.RX_REQ_TAG(RX_REQ_TAG),
+	.RX_REQ_ADDR(RX_REQ_ADDR),
+	.RX_REQ_LEN(RX_REQ_LEN),
+	.REQ_ACK(wReqAck)
+);
+
+
+// Read the scatter gather buffer address and length, continuously so that
+// we have it ready whenever the next buffer is needed.
+sg_list_reader_32 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
+	.CLK(CLK),
+	.RST(rRst | wSgRst),
+	.BUF_DATA(wSgRxData),
+	.BUF_DATA_EMPTY(wSgRxDataEmpty),
+	.BUF_DATA_REN(wSgRxDataRen),
+	.VALID(wSgElemRdy),
+	.EMPTY(),
+	.REN(wSgElemRen),
+	.ADDR(wSgElemAddr),
+	.LEN(wSgElemLen)
+);
+
+
+// Main port reader logic
+rx_port_reader #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_MAIN_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) reader (
+	.CLK(CLK), 
+	.RST(rRst), 
+	.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
+	.TXN_DATA(TXN_DATA), 
+	.TXN_LEN_VALID(TXN_LEN_VALID), 
+	.TXN_OFF_LAST_VALID(TXN_OFF_LAST_VALID), 
+	.TXN_DONE_LEN(TXN_DONE_LEN),
+	.TXN_DONE(TXN_DONE),
+	.TXN_ERR(wTxnErr),
+	.TXN_DONE_ACK(TXN_DONE_ACK),
+	.TXN_DATA_FLUSH(wMainFlush),
+	.TXN_DATA_FLUSHED(wMainFlushed),
+	.RX_REQ(wMainReq),
+	.RX_ADDR(wMainReqAddr),
+	.RX_LEN(wMainReqLen),
+	.RX_REQ_ACK(wReqAck & wMainReqProc),
+	.RX_DATA_EN(MAIN_DATA_EN), 
+	.RX_DONE(wPackedMainDone),
+	.RX_ERR(wPackedMainErr),
+	.SG_DONE(wPackedSgRxDone), 
+	.SG_ERR(wPackedSgRxErr), 
+	.SG_ELEM_ADDR(wSgElemAddr), 
+	.SG_ELEM_LEN(wSgElemLen),
+	.SG_ELEM_RDY(wSgElemRdy),
+	.SG_ELEM_REN(wSgElemRen),
+	.SG_RST(wSgRst),
+	.CHNL_RX(wChnlRx), 
+	.CHNL_RX_LEN(wChnlRxLen), 
+	.CHNL_RX_LAST(wChnlRxLast),
+	.CHNL_RX_OFF(wChnlRxOff), 
+	.CHNL_RX_RECVD(wChnlRxRecvd), 
+	.CHNL_RX_ACK_RECVD(wChnlRxAckRecvd), 
+	.CHNL_RX_CONSUMED(wChnlRxConsumed)
+);
+
+
+// Manage the CHNL_RX* signals in the CHNL_CLK domain.
+rx_port_channel_gate #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
+	.RST(rRst), 
+	.CLK(CLK), 
+	.RX(wChnlRx), 
+	.RX_RECVD(wChnlRxRecvd), 
+	.RX_ACK_RECVD(wChnlRxAckRecvd), 
+	.RX_LAST(wChnlRxLast), 
+	.RX_LEN(wChnlRxLen), 
+	.RX_OFF(wChnlRxOff), 
+	.RX_CONSUMED(wChnlRxConsumed), 
+	.RD_DATA(wMainData), 
+	.RD_EMPTY(wMainDataEmpty), 
+	.RD_EN(wMainDataRen), 
+	.CHNL_CLK(CHNL_CLK), 
+	.CHNL_RX(CHNL_RX), 
+	.CHNL_RX_ACK(CHNL_RX_ACK), 
+	.CHNL_RX_LAST(CHNL_RX_LAST), 
+	.CHNL_RX_LEN(CHNL_RX_LEN), 
+	.CHNL_RX_OFF(CHNL_RX_OFF), 
+	.CHNL_RX_DATA(CHNL_RX_DATA), 
+	.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID), 
+	.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
+);
+
+
+/*
+wire [35:0] wControl0;
+chipscope_icon_1 cs_icon(
+	.CONTROL0(wControl0)
+);
+
+chipscope_ila_t8_512 a0(
+	.CLK(CLK), 
+	.CONTROL(wControl0), 
+	.TRIG0({SG_RX_DATA_EN != 0, wSgElemRen, wMainReq | wSgRxReq | wSgTxReq, 
+			RX_REQ, SG_RX_BUF_ADDR_LO_VALID | SG_RX_BUF_ADDR_HI_VALID | SG_RX_BUF_LEN_VALID, 
+			wSgRst, wTxnErr | wPackedSgRxDone | wSgRxFlush | wSgRxFlushed, TXN_OFF_LAST_VALID | TXN_LEN_VALID}),
+	.DATA({
+			wPackedSgRxErr, // 1
+			wPackedSgRxDone, // 1
+			wPackedSgRxWen, // 1
+			wPackedSgRxData, // 64
+			SG_RX_ERR, // 1
+			SG_RX_DONE, // 1
+			SG_RX_DATA_EN, // 2
+			SG_RX_DATA, // 64
+			wSgRxDataRen, // 1
+			wSgRxDataEmpty, // 1
+			wSgRxData, // 64
+			wSgRst, // 1
+			SG_RST, // 1
+			wPackedSgRxDone, // 1
+			wSgRxRst, // 1
+			wSgRxFlushed, // 1
+			wSgRxFlush, // 1
+			SG_RX_BUF_ADDR_LO_VALID, // 1
+			SG_RX_BUF_ADDR_HI_VALID, // 1 
+			SG_RX_BUF_LEN_VALID, // 1
+			SG_RX_BUF_DATA, // 32
+			RX_REQ_ADDR, // 64
+			RX_REQ_TAG, // 2
+			RX_REQ_ACK, // 1
+			RX_REQ, // 1
+			wSgTxReqProc, // 1
+			wSgTxReqAddr, // 64
+			wSgTxReq, // 1
+			wSgRxReqProc, // 1
+			wSgRxReqAddr, // 64
+			wSgRxReq, // 1
+			wMainReqProc, // 1
+			wMainReqAddr, // 64
+			wMainReq, // 1
+			wReqAck, // 1
+			wTxnErr, // 1
+			TXN_OFF_LAST_VALID, // 1
+			TXN_LEN_VALID}) // 1
+);
+*/
+
+endmodule
diff --git a/fpga/riffa_hdl/rx_port_64.v b/fpga/riffa_hdl/rx_port_64.v
new file mode 100644
index 0000000..3bb9c7e
--- /dev/null
+++ b/fpga/riffa_hdl/rx_port_64.v
@@ -0,0 +1,494 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			rx_port_64.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Receives data from the rx_engine and buffers the output 
+//						for the RIFFA channel.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+module rx_port_64 #(
+	parameter C_DATA_WIDTH = 9'd64,
+	parameter C_MAIN_FIFO_DEPTH = 1024,
+	parameter C_SG_FIFO_DEPTH = 512,
+	parameter C_MAX_READ_REQ = 2,					// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+	// Local parameters
+	parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),
+	parameter C_MAIN_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_MAIN_FIFO_DEPTH))+1),
+	parameter C_SG_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_SG_FIFO_DEPTH))+1)
+)
+(
+	input CLK,
+	input RST,
+	input [2:0] CONFIG_MAX_READ_REQUEST_SIZE,				// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+
+	output SG_RX_BUF_RECVD,							// Scatter gather RX buffer completely read (ready for next if applicable)
+	input [31:0] SG_RX_BUF_DATA,					// Scatter gather RX buffer data
+	input SG_RX_BUF_LEN_VALID,						// Scatter gather RX buffer length valid
+	input SG_RX_BUF_ADDR_HI_VALID,					// Scatter gather RX buffer high address valid
+	input SG_RX_BUF_ADDR_LO_VALID,					// Scatter gather RX buffer low address valid
+
+	output SG_TX_BUF_RECVD,							// Scatter gather TX buffer completely read (ready for next if applicable)
+	input [31:0] SG_TX_BUF_DATA,					// Scatter gather TX buffer data
+	input SG_TX_BUF_LEN_VALID,						// Scatter gather TX buffer length valid
+	input SG_TX_BUF_ADDR_HI_VALID,					// Scatter gather TX buffer high address valid
+	input SG_TX_BUF_ADDR_LO_VALID,					// Scatter gather TX buffer low address valid
+
+	output [C_DATA_WIDTH-1:0] SG_DATA,				// Scatter gather TX buffer data
+	output SG_DATA_EMPTY,							// Scatter gather TX buffer data empty
+	input SG_DATA_REN,								// Scatter gather TX buffer data read enable
+	input SG_RST,									// Scatter gather TX buffer data reset
+	output SG_ERR,									// Scatter gather TX encountered an error
+	
+	input [31:0] TXN_DATA,							// Read transaction data
+	input TXN_LEN_VALID,							// Read transaction length valid
+	input TXN_OFF_LAST_VALID,						// Read transaction offset/last valid
+	output [31:0] TXN_DONE_LEN,						// Read transaction actual transfer length
+	output TXN_DONE,								// Read transaction done
+	input TXN_DONE_ACK,								// Read transaction actual transfer length read
+
+	output RX_REQ,									// Read request
+	input RX_REQ_ACK,								// Read request accepted
+	output [1:0] RX_REQ_TAG,						// Read request data tag 
+	output [63:0] RX_REQ_ADDR,						// Read request address
+	output [9:0] RX_REQ_LEN,						// Read request length
+
+	input [C_DATA_WIDTH-1:0] MAIN_DATA,				// Main incoming data 
+	input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN,		// Main incoming data enable
+	input MAIN_DONE,								// Main incoming data complete
+	input MAIN_ERR,									// Main incoming data completed with error
+	input [C_DATA_WIDTH-1:0] SG_RX_DATA,			// Scatter gather for RX incoming data 
+	input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN,	// Scatter gather for RX incoming data enable
+	input SG_RX_DONE,								// Scatter gather for RX incoming data complete
+	input SG_RX_ERR,								// Scatter gather for RX incoming data completed with error
+	input [C_DATA_WIDTH-1:0] SG_TX_DATA,			// Scatter gather for TX incoming data 
+	input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN,	// Scatter gather for TX incoming data enable
+	input SG_TX_DONE,								// Scatter gather for TX incoming data complete
+	input SG_TX_ERR,								// Scatter gather for TX incoming data completed with error
+
+	input CHNL_CLK,									// Channel read clock
+	output CHNL_RX,									// Channel read receive signal
+	input CHNL_RX_ACK,								// Channle read received signal
+	output CHNL_RX_LAST,							// Channel last read
+	output [31:0] CHNL_RX_LEN,						// Channel read length
+	output [30:0] CHNL_RX_OFF,						// Channel read offset
+	output [C_DATA_WIDTH-1:0] CHNL_RX_DATA,			// Channel read data
+	output CHNL_RX_DATA_VALID,						// Channel read data valid
+	input CHNL_RX_DATA_REN							// Channel read data has been recieved
+);
+
+`include "functions.vh"
+
+
+
+
+wire	[C_DATA_WIDTH-1:0]			wPackedMainData;
+wire								wPackedMainWen;
+wire								wPackedMainDone;
+wire								wPackedMainErr;
+wire								wMainFlush;
+wire								wMainFlushed;
+
+wire	[C_DATA_WIDTH-1:0]			wPackedSgRxData;
+wire								wPackedSgRxWen;
+wire								wPackedSgRxDone;
+wire								wPackedSgRxErr;
+wire								wSgRxFlush;
+wire								wSgRxFlushed;
+
+wire	[C_DATA_WIDTH-1:0]			wPackedSgTxData;
+wire								wPackedSgTxWen;
+wire								wPackedSgTxDone;
+wire								wPackedSgTxErr;
+wire								wSgTxFlush;
+wire								wSgTxFlushed;
+
+wire								wMainDataRen;
+wire								wMainDataEmpty;
+wire	[C_DATA_WIDTH-1:0]			wMainData;
+
+wire								wSgRxRst;
+wire								wSgRxDataRen;
+wire								wSgRxDataEmpty;
+wire	[C_DATA_WIDTH-1:0]			wSgRxData;
+wire	[C_SG_FIFO_DEPTH_WIDTH-1:0]	wSgRxFifoCount;
+
+wire								wSgTxRst;
+wire	[C_SG_FIFO_DEPTH_WIDTH-1:0]	wSgTxFifoCount;
+
+wire								wSgRxReq;
+wire	[63:0]						wSgRxReqAddr;
+wire	[9:0]						wSgRxReqLen;
+
+wire								wSgTxReq;
+wire	[63:0]						wSgTxReqAddr;
+wire	[9:0]						wSgTxReqLen;
+
+wire								wSgRxReqProc;
+wire								wSgTxReqProc;
+wire								wMainReqProc;
+wire								wReqAck;
+
+wire								wSgElemRdy;
+wire								wSgElemRen;
+wire	[63:0]						wSgElemAddr;
+wire	[31:0]						wSgElemLen;
+
+wire								wSgRst;
+wire								wMainReq;
+wire	[63:0]						wMainReqAddr;
+wire	[9:0]						wMainReqLen;
+wire								wTxnErr;
+wire								wChnlRx;
+wire								wChnlRxRecvd;
+wire								wChnlRxAckRecvd;
+wire								wChnlRxLast;
+wire	[31:0]						wChnlRxLen;
+wire	[30:0]						wChnlRxOff;
+wire	[31:0]						wChnlRxConsumed;
+
+reg		[4:0]						rWideRst=0;
+reg									rRst=0;
+
+assign SG_ERR = (wPackedSgTxDone & wPackedSgTxErr);
+
+// Generate a wide reset from the input reset.
+always @ (posedge CLK) begin
+	rRst <= #1 rWideRst[4]; 
+	if (RST) 
+		rWideRst <= #1 5'b11111;
+	else 
+		rWideRst <= (rWideRst<<1);
+end
+
+
+// Pack received data tightly into our FIFOs 
+fifo_packer_64 mainFifoPacker (
+	.CLK(CLK),
+	.RST(rRst),
+	.DATA_IN(MAIN_DATA),
+	.DATA_IN_EN(MAIN_DATA_EN),
+	.DATA_IN_DONE(MAIN_DONE),
+	.DATA_IN_ERR(MAIN_ERR),
+	.DATA_IN_FLUSH(wMainFlush),
+	.PACKED_DATA(wPackedMainData),
+	.PACKED_WEN(wPackedMainWen),
+	.PACKED_DATA_DONE(wPackedMainDone),
+	.PACKED_DATA_ERR(wPackedMainErr),
+	.PACKED_DATA_FLUSHED(wMainFlushed)
+);
+
+fifo_packer_64 sgRxFifoPacker (
+	.CLK(CLK),
+	.RST(rRst),
+	.DATA_IN(SG_RX_DATA),
+	.DATA_IN_EN(SG_RX_DATA_EN),
+	.DATA_IN_DONE(SG_RX_DONE),
+	.DATA_IN_ERR(SG_RX_ERR),
+	.DATA_IN_FLUSH(wSgRxFlush),
+	.PACKED_DATA(wPackedSgRxData),
+	.PACKED_WEN(wPackedSgRxWen),
+	.PACKED_DATA_DONE(wPackedSgRxDone),
+	.PACKED_DATA_ERR(wPackedSgRxErr),
+	.PACKED_DATA_FLUSHED(wSgRxFlushed)
+);
+
+fifo_packer_64 sgTxFifoPacker (
+	.CLK(CLK),
+	.RST(rRst),
+	.DATA_IN(SG_TX_DATA),
+	.DATA_IN_EN(SG_TX_DATA_EN),
+	.DATA_IN_DONE(SG_TX_DONE),
+	.DATA_IN_ERR(SG_TX_ERR),
+	.DATA_IN_FLUSH(wSgTxFlush),
+	.PACKED_DATA(wPackedSgTxData),
+	.PACKED_WEN(wPackedSgTxWen),
+	.PACKED_DATA_DONE(wPackedSgTxDone),
+	.PACKED_DATA_ERR(wPackedSgTxErr),
+	.PACKED_DATA_FLUSHED(wSgTxFlushed)
+);
+
+
+// FIFOs for storing received data for the channel.
+(* RAM_STYLE="BLOCK" *)
+async_fifo_fwft #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_MAIN_FIFO_DEPTH)) mainFifo (
+	.WR_CLK(CLK),
+	.WR_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
+	.WR_EN(wPackedMainWen),
+	.WR_DATA(wPackedMainData),
+	.WR_FULL(),
+	.RD_CLK(CHNL_CLK),
+	.RD_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
+	.RD_EN(wMainDataRen),
+	.RD_DATA(wMainData),
+	.RD_EMPTY(wMainDataEmpty)
+);
+
+(* RAM_STYLE="BLOCK" *)
+sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgRxFifo (
+	.RST(rRst | wSgRxRst),
+	.CLK(CLK),
+	.WR_EN(wPackedSgRxWen),
+	.WR_DATA(wPackedSgRxData),
+	.FULL(),
+	.RD_EN(wSgRxDataRen),
+	.RD_DATA(wSgRxData),
+	.EMPTY(wSgRxDataEmpty),
+	.COUNT(wSgRxFifoCount)
+);
+
+(* RAM_STYLE="BLOCK" *)
+sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgTxFifo (
+	.RST(rRst | wSgTxRst),
+	.CLK(CLK),
+	.WR_EN(wPackedSgTxWen),
+	.WR_DATA(wPackedSgTxData),
+	.FULL(),
+	.RD_EN(SG_DATA_REN),
+	.RD_DATA(SG_DATA),
+	.EMPTY(SG_DATA_EMPTY),
+	.COUNT(wSgTxFifoCount)
+);
+
+
+// Manage requesting and acknowledging scatter gather data. Note that
+// these modules will share the main requestor's RX channel. They will
+// take priority over the main logic's use of the RX channel.
+sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgRxReq (
+	.CLK(CLK),
+	.RST(rRst),
+	.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
+	.USER_RST(wSgRst),
+	.BUF_RECVD(SG_RX_BUF_RECVD),
+	.BUF_DATA(SG_RX_BUF_DATA),
+	.BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
+	.BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
+	.BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
+	.FIFO_COUNT(wSgRxFifoCount),
+	.FIFO_FLUSH(wSgRxFlush),
+	.FIFO_FLUSHED(wSgRxFlushed),
+	.FIFO_RST(wSgRxRst),
+	.RX_REQ(wSgRxReq),
+	.RX_ADDR(wSgRxReqAddr),
+	.RX_LEN(wSgRxReqLen),
+	.RX_REQ_ACK(wReqAck & wSgRxReqProc),
+	.RX_DONE(wPackedSgRxDone)
+);
+
+sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgTxReq (
+	.CLK(CLK),
+	.RST(rRst),
+	.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
+	.USER_RST(SG_RST),
+	.BUF_RECVD(SG_TX_BUF_RECVD),
+	.BUF_DATA(SG_TX_BUF_DATA),
+	.BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
+	.BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
+	.BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
+	.FIFO_COUNT(wSgTxFifoCount),
+	.FIFO_FLUSH(wSgTxFlush),
+	.FIFO_FLUSHED(wSgTxFlushed),
+	.FIFO_RST(wSgTxRst),
+	.RX_REQ(wSgTxReq),
+	.RX_ADDR(wSgTxReqAddr),
+	.RX_LEN(wSgTxReqLen),
+	.RX_REQ_ACK(wReqAck & wSgTxReqProc),
+	.RX_DONE(wPackedSgTxDone)
+);
+
+
+// A read requester for the channel and scatter gather requesters.
+rx_port_requester_mux requesterMux (
+	.RST(rRst), 
+	.CLK(CLK), 
+	.SG_RX_REQ(wSgRxReq), 
+	.SG_RX_LEN(wSgRxReqLen), 
+	.SG_RX_ADDR(wSgRxReqAddr), 
+	.SG_RX_REQ_PROC(wSgRxReqProc),
+	.SG_TX_REQ(wSgTxReq), 
+	.SG_TX_LEN(wSgTxReqLen), 
+	.SG_TX_ADDR(wSgTxReqAddr), 
+	.SG_TX_REQ_PROC(wSgTxReqProc),
+	.MAIN_REQ(wMainReq), 
+	.MAIN_LEN(wMainReqLen), 
+	.MAIN_ADDR(wMainReqAddr), 
+	.MAIN_REQ_PROC(wMainReqProc),
+	.RX_REQ(RX_REQ),
+	.RX_REQ_ACK(RX_REQ_ACK),
+	.RX_REQ_TAG(RX_REQ_TAG),
+	.RX_REQ_ADDR(RX_REQ_ADDR),
+	.RX_REQ_LEN(RX_REQ_LEN),
+	.REQ_ACK(wReqAck)
+);
+
+
+// Read the scatter gather buffer address and length, continuously so that
+// we have it ready whenever the next buffer is needed.
+sg_list_reader_64 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
+	.CLK(CLK),
+	.RST(rRst | wSgRst),
+	.BUF_DATA(wSgRxData),
+	.BUF_DATA_EMPTY(wSgRxDataEmpty),
+	.BUF_DATA_REN(wSgRxDataRen),
+	.VALID(wSgElemRdy),
+	.EMPTY(),
+	.REN(wSgElemRen),
+	.ADDR(wSgElemAddr),
+	.LEN(wSgElemLen)
+);
+
+
+// Main port reader logic
+rx_port_reader #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_MAIN_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) reader (
+	.CLK(CLK), 
+	.RST(rRst), 
+	.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
+	.TXN_DATA(TXN_DATA), 
+	.TXN_LEN_VALID(TXN_LEN_VALID), 
+	.TXN_OFF_LAST_VALID(TXN_OFF_LAST_VALID), 
+	.TXN_DONE_LEN(TXN_DONE_LEN),
+	.TXN_DONE(TXN_DONE),
+	.TXN_ERR(wTxnErr),
+	.TXN_DONE_ACK(TXN_DONE_ACK),
+	.TXN_DATA_FLUSH(wMainFlush),
+	.TXN_DATA_FLUSHED(wMainFlushed),
+	.RX_REQ(wMainReq),
+	.RX_ADDR(wMainReqAddr),
+	.RX_LEN(wMainReqLen),
+	.RX_REQ_ACK(wReqAck & wMainReqProc),
+	.RX_DATA_EN(MAIN_DATA_EN), 
+	.RX_DONE(wPackedMainDone),
+	.RX_ERR(wPackedMainErr),
+	.SG_DONE(wPackedSgRxDone), 
+	.SG_ERR(wPackedSgRxErr), 
+	.SG_ELEM_ADDR(wSgElemAddr), 
+	.SG_ELEM_LEN(wSgElemLen),
+	.SG_ELEM_RDY(wSgElemRdy),
+	.SG_ELEM_REN(wSgElemRen),
+	.SG_RST(wSgRst),
+	.CHNL_RX(wChnlRx), 
+	.CHNL_RX_LEN(wChnlRxLen), 
+	.CHNL_RX_LAST(wChnlRxLast),
+	.CHNL_RX_OFF(wChnlRxOff), 
+	.CHNL_RX_RECVD(wChnlRxRecvd), 
+	.CHNL_RX_ACK_RECVD(wChnlRxAckRecvd), 
+	.CHNL_RX_CONSUMED(wChnlRxConsumed)
+);
+
+
+// Manage the CHNL_RX* signals in the CHNL_CLK domain.
+rx_port_channel_gate #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
+	.RST(rRst), 
+	.CLK(CLK), 
+	.RX(wChnlRx), 
+	.RX_RECVD(wChnlRxRecvd), 
+	.RX_ACK_RECVD(wChnlRxAckRecvd), 
+	.RX_LAST(wChnlRxLast), 
+	.RX_LEN(wChnlRxLen), 
+	.RX_OFF(wChnlRxOff), 
+	.RX_CONSUMED(wChnlRxConsumed), 
+	.RD_DATA(wMainData), 
+	.RD_EMPTY(wMainDataEmpty), 
+	.RD_EN(wMainDataRen), 
+	.CHNL_CLK(CHNL_CLK), 
+	.CHNL_RX(CHNL_RX), 
+	.CHNL_RX_ACK(CHNL_RX_ACK), 
+	.CHNL_RX_LAST(CHNL_RX_LAST), 
+	.CHNL_RX_LEN(CHNL_RX_LEN), 
+	.CHNL_RX_OFF(CHNL_RX_OFF), 
+	.CHNL_RX_DATA(CHNL_RX_DATA), 
+	.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID), 
+	.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
+);
+
+
+/*
+wire [35:0] wControl0;
+chipscope_icon_1 cs_icon(
+	.CONTROL0(wControl0)
+);
+
+chipscope_ila_t8_512 a0(
+	.CLK(CLK), 
+	.CONTROL(wControl0), 
+	.TRIG0({SG_RX_DATA_EN != 0, wSgElemRen, wMainReq | wSgRxReq | wSgTxReq, 
+			RX_REQ, SG_RX_BUF_ADDR_LO_VALID | SG_RX_BUF_ADDR_HI_VALID | SG_RX_BUF_LEN_VALID, 
+			wSgRst, wTxnErr | wPackedSgRxDone | wSgRxFlush | wSgRxFlushed, TXN_OFF_LAST_VALID | TXN_LEN_VALID}),
+	.DATA({
+			wPackedSgRxErr, // 1
+			wPackedSgRxDone, // 1
+			wPackedSgRxWen, // 1
+			wPackedSgRxData, // 64
+			SG_RX_ERR, // 1
+			SG_RX_DONE, // 1
+			SG_RX_DATA_EN, // 2
+			SG_RX_DATA, // 64
+			wSgRxDataRen, // 1
+			wSgRxDataEmpty, // 1
+			wSgRxData, // 64
+			wSgRst, // 1
+			SG_RST, // 1
+			wPackedSgRxDone, // 1
+			wSgRxRst, // 1
+			wSgRxFlushed, // 1
+			wSgRxFlush, // 1
+			SG_RX_BUF_ADDR_LO_VALID, // 1
+			SG_RX_BUF_ADDR_HI_VALID, // 1 
+			SG_RX_BUF_LEN_VALID, // 1
+			SG_RX_BUF_DATA, // 32
+			RX_REQ_ADDR, // 64
+			RX_REQ_TAG, // 2
+			RX_REQ_ACK, // 1
+			RX_REQ, // 1
+			wSgTxReqProc, // 1
+			wSgTxReqAddr, // 64
+			wSgTxReq, // 1
+			wSgRxReqProc, // 1
+			wSgRxReqAddr, // 64
+			wSgRxReq, // 1
+			wMainReqProc, // 1
+			wMainReqAddr, // 64
+			wMainReq, // 1
+			wReqAck, // 1
+			wTxnErr, // 1
+			TXN_OFF_LAST_VALID, // 1
+			TXN_LEN_VALID}) // 1
+);
+*/
+
+endmodule
diff --git a/fpga/riffa_hdl/rx_port_channel_gate.v b/fpga/riffa_hdl/rx_port_channel_gate.v
new file mode 100644
index 0000000..01f5ad7
--- /dev/null
+++ b/fpga/riffa_hdl/rx_port_channel_gate.v
@@ -0,0 +1,165 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			rx_port_channel_gate.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Provides cross domain synchronization for the CHNL_RX* 
+// signals between the CHNL_CLK and CLK domains. 
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+
+`timescale 1ns/1ns
+module rx_port_channel_gate #(
+	parameter C_DATA_WIDTH = 9'd64
+)
+(
+	input RST,
+	input CLK,
+
+	input RX,								// Channel read signal (CLK)
+	output RX_RECVD,						// Channel read received signal (CLK)
+	output RX_ACK_RECVD,					// Channel read acknowledgment received signal (CLK)
+	input RX_LAST,							// Channel last read (CLK)
+	input [31:0] RX_LEN,					// Channel read length (CLK)
+	input [30:0] RX_OFF,					// Channel read offset (CLK)
+	output [31:0] RX_CONSUMED,				// Channel words consumed (CLK)
+	
+	input [C_DATA_WIDTH-1:0] RD_DATA,		// FIFO read data (CHNL_CLK)
+	input RD_EMPTY,							// FIFO is empty (CHNL_CLK)
+	output RD_EN,							// FIFO read enable (CHNL_CLK)
+
+	input CHNL_CLK,							// Channel read clock
+	output CHNL_RX,							// Channel read receive signal (CHNL_CLK)
+	input CHNL_RX_ACK,						// Channle read received signal (CHNL_CLK)
+	output CHNL_RX_LAST,					// Channel last read (CHNL_CLK)
+	output [31:0] CHNL_RX_LEN,				// Channel read length (CHNL_CLK)
+	output [30:0] CHNL_RX_OFF,				// Channel read offset (CHNL_CLK)
+	output [C_DATA_WIDTH-1:0] CHNL_RX_DATA,	// Channel read data (CHNL_CLK)
+	output CHNL_RX_DATA_VALID,				// Channel read data valid (CHNL_CLK)
+	input CHNL_RX_DATA_REN					// Channel read data has been recieved (CHNL_CLK)
+);
+
+reg								rAckd=0, _rAckd=0;
+reg								rChnlRxAck=0, _rChnlRxAck=0;
+
+reg		[31:0]					rConsumed=0, _rConsumed=0;
+reg		[31:0]					rConsumedStable=0, _rConsumedStable=0;
+reg		[31:0]					rConsumedSample=0, _rConsumedSample=0;
+reg								rCountRead=0, _rCountRead=0;
+wire							wCountRead;
+wire							wCountStable;
+wire							wDataRead = (CHNL_RX_DATA_REN & CHNL_RX_DATA_VALID);
+
+
+assign RX_CONSUMED = rConsumedSample;
+
+assign RD_EN = CHNL_RX_DATA_REN;
+
+assign CHNL_RX_LAST = RX_LAST;
+assign CHNL_RX_LEN = RX_LEN;
+assign CHNL_RX_OFF = RX_OFF;
+assign CHNL_RX_DATA = RD_DATA;
+assign CHNL_RX_DATA_VALID = !RD_EMPTY;
+
+
+// Buffer the input signals that come from outside the rx_port.
+always @ (posedge CHNL_CLK) begin
+	rChnlRxAck <= #1 (RST ? 1'd0 : _rChnlRxAck);
+end
+
+always @ (*) begin
+	_rChnlRxAck = CHNL_RX_ACK;
+end
+
+
+// Signal receive into the channel domain.
+cross_domain_signal rxSig (
+	.CLK_A(CLK), 
+	.CLK_A_SEND(RX), 
+	.CLK_A_RECV(RX_RECVD), 
+	.CLK_B(CHNL_CLK), 
+	.CLK_B_RECV(CHNL_RX), 
+	.CLK_B_SEND(CHNL_RX)
+);
+
+// Signal acknowledgment of receive into the CLK domain.
+syncff rxAckSig (.CLK(CLK), .IN_ASYNC(rAckd), .OUT_SYNC(RX_ACK_RECVD));
+
+
+// Capture CHNL_RX_ACK and reset only after the CHNL_RX drops.
+always @ (posedge CHNL_CLK) begin
+	rAckd <= #1 (RST ? 1'd0 : _rAckd);
+end
+
+always @ (*) begin
+	_rAckd = (CHNL_RX & (rAckd | rChnlRxAck));
+end
+
+
+// Count the words consumed by the channel and pass it into the CLK domain.
+always @ (posedge CHNL_CLK) begin
+	rConsumed <= #1 _rConsumed;
+	rConsumedStable <= #1 _rConsumedStable;
+	rCountRead <= #1 (RST ? 1'd0 : _rCountRead);
+end
+
+always @ (*) begin
+	_rConsumed = (!CHNL_RX ? 0 : rConsumed + (wDataRead*(C_DATA_WIDTH/32)));
+	_rConsumedStable = (wCountRead | rCountRead ? rConsumedStable : rConsumed);
+	_rCountRead = !wCountRead;
+end
+
+always @ (posedge CLK) begin
+	rConsumedSample <= #1 _rConsumedSample;
+end
+
+always @ (*) begin
+	_rConsumedSample = (wCountStable ? rConsumedStable : rConsumedSample);
+end
+
+// Determine when it's safe to update the count in the CLK domain.
+cross_domain_signal countSync (
+	.CLK_A(CHNL_CLK), 
+	.CLK_A_SEND(rCountRead), 
+	.CLK_A_RECV(wCountRead), 
+	.CLK_B(CLK), 
+	.CLK_B_RECV(wCountStable), 
+	.CLK_B_SEND(wCountStable)
+);
+
+
+endmodule
diff --git a/fpga/riffa_hdl/rx_port_reader.v b/fpga/riffa_hdl/rx_port_reader.v
new file mode 100644
index 0000000..11a24be
--- /dev/null
+++ b/fpga/riffa_hdl/rx_port_reader.v
@@ -0,0 +1,542 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			rx_port_reader.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Handles the RX lifecycle and issuing requests for receiving
+// data input. 
+//						for the RIFFA channel.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`define S_RXPORTRD_MAIN_IDLE		6'b00_0001
+`define S_RXPORTRD_MAIN_CHECK		6'b00_0010
+`define S_RXPORTRD_MAIN_READ		6'b00_0100
+`define S_RXPORTRD_MAIN_FLUSH		6'b00_1000
+`define S_RXPORTRD_MAIN_DONE		6'b01_0000
+`define S_RXPORTRD_MAIN_RESET		6'b10_0000
+
+`define S_RXPORTRD_RX_IDLE		8'b0000_0001
+`define S_RXPORTRD_RX_BUF		8'b0000_0010
+`define S_RXPORTRD_RX_ADJ_0		8'b0000_0100
+`define S_RXPORTRD_RX_ADJ_1		8'b0000_1000
+`define S_RXPORTRD_RX_ISSUE		8'b0001_0000
+`define S_RXPORTRD_RX_WAIT_0	8'b0010_0000
+`define S_RXPORTRD_RX_WAIT_1	8'b0100_0000
+`define S_RXPORTRD_RX_DONE		8'b1000_0000
+
+`timescale 1ns/1ns
+module rx_port_reader #(
+	parameter C_DATA_WIDTH = 9'd64,
+	parameter C_FIFO_DEPTH = 1024,
+	parameter C_MAX_READ_REQ = 2,				// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+	// Local parameters
+	parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),
+	parameter C_FIFO_WORDS = (C_DATA_WIDTH/32)*C_FIFO_DEPTH
+)
+(
+	input CLK,
+	input RST,
+	input [2:0] CONFIG_MAX_READ_REQUEST_SIZE,			// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+	
+	input [31:0] TXN_DATA,						// Read transaction data
+	input TXN_LEN_VALID,						// Read transaction length valid
+	input TXN_OFF_LAST_VALID,					// Read transaction offset/last valid
+	output [31:0] TXN_DONE_LEN,					// Read transaction actual transfer length
+	output TXN_DONE,							// Read transaction done
+	output TXN_ERR,								// Read transaction completed with error
+	input TXN_DONE_ACK,							// Read transaction actual transfer length read
+
+	output TXN_DATA_FLUSH,						// Request that all data in the packer be flushed
+	input TXN_DATA_FLUSHED,						// All data in the packer has been flushed
+
+	output RX_REQ,								// Issue a read request
+	output [63:0] RX_ADDR,						// Request address
+	output [9:0] RX_LEN,						// Request length
+	input RX_REQ_ACK,							// Request has been accepted
+
+	input [C_DATA_WORD_WIDTH-1:0] RX_DATA_EN,	// Incoming read data enable
+	input RX_DONE,								// Incoming read completed
+	input RX_ERR,								// Incoming read completed with error
+	input SG_DONE,								// Incoming scatter gather read completed
+	input SG_ERR,								// Incoming scatter gather read completed with error
+
+	input [63:0] SG_ELEM_ADDR,					// Scatter gather element address
+	input [31:0] SG_ELEM_LEN,					// Scatter gather element length (in words)
+	input SG_ELEM_RDY,							// Scatter gather element ready
+	output SG_ELEM_REN,							// Scatter gather element read enable
+	output SG_RST,								// Scatter gather reset
+
+	output CHNL_RX,								// Signal channel RX
+	output [31:0] CHNL_RX_LEN,					// Channel RX length
+	output CHNL_RX_LAST,						// Channel RX last
+	output [30:0] CHNL_RX_OFF,					// Channel RX offset
+	input CHNL_RX_RECVD,						// Channel RX received
+	input CHNL_RX_ACK_RECVD,					// Channel RX acknowledgment received
+	input [31:0] CHNL_RX_CONSUMED				// Channel words consumed in current RX
+);
+
+`include "functions.vh"
+
+
+reg		[31:0]						rTxnData=0, _rTxnData=0;
+reg									rTxnOffLastValid=0, _rTxnOffLastValid=0;
+reg									rTxnLenValid=0, _rTxnLenValid=0;
+reg		[C_DATA_WORD_WIDTH-1:0]		rRxDataEn=0, _rRxDataEn=0;
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg		[5:0]						rMainState=`S_RXPORTRD_MAIN_IDLE, _rMainState=`S_RXPORTRD_MAIN_IDLE;
+reg		[31:0]						rOffLast=0, _rOffLast=0;
+reg		[31:0]						rReadWords=0, _rReadWords=0;
+reg									rReadWordsZero=0, _rReadWordsZero=0;
+reg		[0:0]						rStart=0, _rStart=0;
+reg		[3:0]						rFlushed=0, _rFlushed=0;
+reg		[31:0]						rDoneLen=0, _rDoneLen=0;
+reg									rTxnDone=0, _rTxnDone=0;
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg		[7:0]						rRxState=`S_RXPORTRD_RX_IDLE, _rRxState=`S_RXPORTRD_RX_IDLE;
+reg									rSgRen=0, _rSgRen=0;
+reg		[31:0]						rWords=0, _rWords=0;
+reg		[31:0]						rBufWords=0, _rBufWords=0;
+reg		[31:0]						rBufWordsInit=0, _rBufWordsInit=0;
+reg									rLargeBuf=0, _rLargeBuf=0;
+reg		[63:0]						rAddr=64'd0, _rAddr=64'd0;
+reg		[3:0]						rValsProp=0, _rValsProp=0;
+reg		[2:0]						rCarry=0, _rCarry=0;
+reg									rCopyBufWords=0, _rCopyBufWords=0;
+reg									rUseInit=0, _rUseInit=0;
+reg		[10:0]						rPageRem=0, _rPageRem=0;
+reg									rPageSpill=0, _rPageSpill=0;
+reg									rPageSpillInit=0, _rPageSpillInit=0;
+reg		[10:0]						rPreLen=0, _rPreLen=0;
+reg		[2:0]						rMaxPayloadTrain=0, _rMaxPayloadTrain=0;
+reg		[2:0]						rMaxPayloadShift=0, _rMaxPayloadShift=0;
+reg		[9:0]						rMaxPayload=0, _rMaxPayload=0;
+reg									rPayloadSpill=0, _rPayloadSpill=0;
+reg									rMaxLen=0, _rMaxLen=0;
+reg		[9:0]						rLen=0, _rLen=0;
+reg									rLenEQWordsHi=0, _rLenEQWordsHi=0;
+reg									rLenEQWordsLo=0, _rLenEQWordsLo=0;
+reg									rLenEQBufWordsHi=0, _rLenEQBufWordsHi=0;
+reg									rLenEQBufWordsLo=0, _rLenEQBufWordsLo=0;
+
+reg		[31:0]						rRecvdWords=0, _rRecvdWords=0;
+reg		[31:0]						rReqdWords=0, _rReqdWords=0;
+reg		[31:0]						rRequestingWords=0, _rRequestingWords=0;
+reg		[31:0]						rAvailWords=0, _rAvailWords=0;
+reg		[31:0]						rPartWords=0, _rPartWords=0;
+reg		[10:0]						rAckCount=0, _rAckCount=0;
+reg									rAckCountEQ0=0, _rAckCountEQ0=0;
+reg									rLastDoneRead=1, _rLastDoneRead=1;
+reg									rTxnDoneAck=0, _rTxnDoneAck=0;
+reg									rPartWordsRecvd=0, _rPartWordsRecvd=0;
+reg									rCarryInv=0, _rCarryInv=0;
+reg									rSpaceAvail=0, _rSpaceAvail=0;
+
+reg									rPartialDone=0, _rPartialDone=0;
+reg									rReqPartialDone=0, _rReqPartialDone=0;
+
+reg									rErr=0, _rErr=0;
+
+
+assign TXN_DONE_LEN = rDoneLen;
+assign TXN_DONE = (rTxnDone | rPartialDone);
+assign TXN_ERR = rErr;
+
+assign TXN_DATA_FLUSH = rMainState[3]; // S_RXPORTRD_MAIN_FLUSH
+
+assign RX_REQ = (rRxState[4] & rSpaceAvail); // S_RXPORTRD_RX_ISSUE
+assign RX_ADDR = rAddr;
+assign RX_LEN = rLen;
+
+assign SG_ELEM_REN = rSgRen;
+assign SG_RST = rMainState[1]; // S_RXPORTRD_MAIN_CHECK
+
+assign CHNL_RX = (rMainState[2] | rMainState[3] | rMainState[4]); // S_RXPORTRD_MAIN_READ | S_RXPORTRD_MAIN_FLUSH | S_RXPORTRD_MAIN_DONE
+assign CHNL_RX_LEN = rReadWords;
+assign CHNL_RX_LAST = rOffLast[0];
+assign CHNL_RX_OFF = rOffLast[31:1];
+
+
+// Buffer signals that come from outside the rx_port.
+always @ (posedge CLK) begin
+	rTxnData <= #1 _rTxnData;
+	rTxnOffLastValid <= #1 _rTxnOffLastValid;
+	rTxnLenValid <= #1 _rTxnLenValid;
+	rTxnDoneAck <= #1 (RST ? 1'd0 : _rTxnDoneAck);	
+	rRxDataEn <= #1 _rRxDataEn;
+end
+
+always @ (*) begin
+	_rTxnData = TXN_DATA;
+	_rTxnOffLastValid = TXN_OFF_LAST_VALID;
+	_rTxnLenValid = TXN_LEN_VALID;
+	_rTxnDoneAck = TXN_DONE_ACK;	
+	_rRxDataEn = RX_DATA_EN;
+end
+
+
+// Handle RX lifecycle.
+always @ (posedge CLK) begin
+	rMainState <= #1 (RST ? `S_RXPORTRD_MAIN_IDLE : _rMainState);
+	rOffLast <= #1 _rOffLast;
+	rReadWords <= #1 _rReadWords;
+	rReadWordsZero <= #1 _rReadWordsZero;
+	rStart <= #1 _rStart;
+	rFlushed <= #1 _rFlushed;
+	rDoneLen <= #1 (RST ? 0 : _rDoneLen);
+	rTxnDone <= #1 _rTxnDone;
+end
+
+always @ (*) begin
+	_rMainState = rMainState;
+	_rDoneLen = rDoneLen;
+	_rTxnDone = rTxnDone;
+	
+	_rOffLast = (rTxnOffLastValid ? rTxnData : rOffLast);
+	_rReadWords = (rMainState[0] & rTxnLenValid ? rTxnData : rReadWords);
+	_rReadWordsZero = (rReadWords == 0);
+	_rStart = ((rStart<<1) | rTxnLenValid);
+	_rFlushed = ((rFlushed<<1) | TXN_DATA_FLUSHED);
+
+	case (rMainState)
+
+	`S_RXPORTRD_MAIN_IDLE: begin // Wait for new read transaction offset/last & length
+		_rTxnDone = 0;
+		if (rStart[0])
+			_rMainState = `S_RXPORTRD_MAIN_CHECK;
+	end
+
+	`S_RXPORTRD_MAIN_CHECK: begin // See if we should start a transaction
+		if (!rReadWordsZero)
+			_rMainState = `S_RXPORTRD_MAIN_READ;
+		else if (rOffLast[0])
+			_rMainState = `S_RXPORTRD_MAIN_FLUSH;
+		else
+			_rMainState = `S_RXPORTRD_MAIN_IDLE;
+	end
+	
+	`S_RXPORTRD_MAIN_READ: begin // Issue read transfers, wait for data to arrive
+		if (rRxState[7] & rLastDoneRead) begin // S_RXPORTRD_RX_DONE
+			_rDoneLen = rRecvdWords;
+			_rMainState = `S_RXPORTRD_MAIN_FLUSH;
+		end
+	end
+
+	`S_RXPORTRD_MAIN_FLUSH: begin // Wait for data to be flushed
+		if (rFlushed[3])
+			_rMainState = `S_RXPORTRD_MAIN_DONE;
+	end
+
+	`S_RXPORTRD_MAIN_DONE: begin // Wait for RX to be received and ackd in the channel
+		if (CHNL_RX_RECVD & CHNL_RX_ACK_RECVD)
+			_rMainState = `S_RXPORTRD_MAIN_RESET;
+	end
+
+	`S_RXPORTRD_MAIN_RESET: begin // Wait until RX has dropped in the channel
+		if (!CHNL_RX_RECVD) begin
+			_rTxnDone = 1;
+			_rMainState = `S_RXPORTRD_MAIN_IDLE;
+		end
+	end
+
+	default: begin
+		_rMainState = `S_RXPORTRD_MAIN_IDLE;
+	end
+
+	endcase
+end
+
+
+// Issue the read requests at the buffer level. Decrement the amount requested
+// after every request. Continue until all words have been requested.
+wire [9:0] wAddrLoInv = ~rAddr[11:2];
+always @ (posedge CLK) begin
+	rRxState <= #1 (RST ? `S_RXPORTRD_RX_IDLE : _rRxState);
+	rSgRen <= #1 (RST ? 1'd0: _rSgRen);
+	rWords <= #1 _rWords;
+	rBufWords <= #1 _rBufWords;
+	rBufWordsInit <= #1 _rBufWordsInit;
+	rLargeBuf <= #1 _rLargeBuf;
+	rAddr <= #1 _rAddr;
+	rCarry <= #1 _rCarry;
+	rValsProp <= #1 _rValsProp;
+	rPageRem <= #1 _rPageRem;
+	rPageSpill <= #1 _rPageSpill;
+	rPageSpillInit <= #1 _rPageSpillInit;
+	rCopyBufWords <= #1 _rCopyBufWords;
+	rUseInit <= #1 _rUseInit;
+	rPreLen <= #1 _rPreLen;
+	rMaxPayloadTrain <= #1 _rMaxPayloadTrain;
+	rMaxPayloadShift <= #1 _rMaxPayloadShift;
+	rMaxPayload <= #1 _rMaxPayload;
+	rPayloadSpill <= #1 _rPayloadSpill;
+	rMaxLen <= #1 _rMaxLen;
+	rLen <= #1 _rLen;
+	rLenEQWordsHi <= #1 _rLenEQWordsHi;
+	rLenEQWordsLo <= #1 _rLenEQWordsLo;
+	rLenEQBufWordsHi <= #1 _rLenEQBufWordsHi;
+	rLenEQBufWordsLo <= #1 _rLenEQBufWordsLo;
+end
+
+always @ (*) begin
+	_rRxState = rRxState;
+	_rCopyBufWords = rCopyBufWords;
+	_rUseInit = rUseInit;
+	_rSgRen = rSgRen;
+
+	_rValsProp = ((rValsProp<<1) | rRxState[2]); // S_RXPORTRD_RX_ADJ_0
+	_rLargeBuf = (SG_ELEM_LEN > rWords);
+   	{_rCarry[0], _rAddr[15:0]} = (rRxState[1] ? SG_ELEM_ADDR[15:0] : (rAddr[15:0] + ({12{RX_REQ_ACK}} & {rLen,2'd0}))); 
+	{_rCarry[1], _rAddr[31:16]} = (rRxState[1] ? SG_ELEM_ADDR[31:16] : (rAddr[31:16] + rCarry[0]));
+	{_rCarry[2], _rAddr[47:32]} = (rRxState[1] ? SG_ELEM_ADDR[47:32] : (rAddr[47:32] + rCarry[1]));
+				 _rAddr[63:48] = (rRxState[1] ? SG_ELEM_ADDR[63:48] : (rAddr[63:48] + rCarry[2]));
+	_rWords = (rRxState[0] ? rReadWords : (rWords - ({10{RX_REQ_ACK}} & rLen)));
+	_rBufWordsInit = (rLargeBuf ? rWords : SG_ELEM_LEN);
+    _rBufWords = (rCopyBufWords ? rBufWordsInit : rBufWords) - ({10{RX_REQ_ACK}} & rLen);
+	_rPageRem = (wAddrLoInv + 1'd1);	
+	_rPageSpillInit = (rBufWordsInit > rPageRem);	
+	_rPageSpill = (rBufWords > rPageRem);	
+	_rPreLen = ((rPageSpillInit & rUseInit) | (rPageSpill & !rUseInit) ? rPageRem : rBufWords[10:0]);
+	_rMaxPayloadTrain = (CONFIG_MAX_READ_REQUEST_SIZE > 3'd4 ? 3'd4 : CONFIG_MAX_READ_REQUEST_SIZE);
+	_rMaxPayloadShift = (C_MAX_READ_REQ[2:0] < rMaxPayloadTrain ? C_MAX_READ_REQ[2:0] : rMaxPayloadTrain);
+	_rMaxPayload = (6'd32<<rMaxPayloadShift);
+	_rPayloadSpill = (rPreLen > rMaxPayload);
+	_rMaxLen = ((rMaxLen & !rValsProp[2]) | RX_REQ_ACK);
+	_rLen = (rPayloadSpill | rMaxLen ? rMaxPayload : rPreLen[9:0]);
+	_rLenEQWordsHi = (16'd0 == rWords[31:16]);
+	_rLenEQWordsLo = ({6'd0, rLen} == rWords[15:0]);
+	_rLenEQBufWordsHi = (16'd0 == rBufWords[31:16]);
+	_rLenEQBufWordsLo = ({6'd0, rLen} == rBufWords[15:0]);
+
+	case (rRxState)
+
+	`S_RXPORTRD_RX_IDLE: begin // Wait for a new read transaction
+		if (rMainState[2]) // S_RXPORTRD_MAIN_READ
+			_rRxState = `S_RXPORTRD_RX_BUF;
+	end
+
+	`S_RXPORTRD_RX_BUF: begin // Wait for buffer length and address
+		if (SG_ELEM_RDY) begin
+			_rSgRen = 1;
+			_rRxState = `S_RXPORTRD_RX_ADJ_0;
+		end
+		else if (rErr) begin
+			_rRxState = `S_RXPORTRD_RX_WAIT_0;
+		end
+	end
+
+	`S_RXPORTRD_RX_ADJ_0: begin // Fix for large buffer
+		_rSgRen = 0;
+		_rCopyBufWords = rSgRen;
+		_rRxState = `S_RXPORTRD_RX_ADJ_1;
+	end
+
+	// (bufwords and pagerem valid here) 
+	`S_RXPORTRD_RX_ADJ_1: begin // Wait for the value to propagate 
+		// Check for page boundary crossing
+		// Fix for page boundary crossing
+		// Check for max read payload
+		// Fix for max read payload
+		_rCopyBufWords = 0;
+		_rUseInit = rCopyBufWords;
+		if (rValsProp[3])
+			_rRxState = `S_RXPORTRD_RX_ISSUE;
+	end
+
+	`S_RXPORTRD_RX_ISSUE: begin // Wait for the request to be accepted
+		if (RX_REQ_ACK) begin
+			if (rErr | (rLenEQWordsHi & rLenEQWordsLo))
+				_rRxState = `S_RXPORTRD_RX_WAIT_0;
+			else if (rLenEQBufWordsHi & rLenEQBufWordsLo)
+				_rRxState = `S_RXPORTRD_RX_BUF;
+			else
+				_rRxState = `S_RXPORTRD_RX_ADJ_0;
+		end
+	end
+
+	`S_RXPORTRD_RX_WAIT_0: begin // Wait for rAckCount to update
+		_rRxState = `S_RXPORTRD_RX_WAIT_1;
+	end
+
+	`S_RXPORTRD_RX_WAIT_1: begin // Wait for requested data to arrive
+		if (rAckCountEQ0)
+			_rRxState = `S_RXPORTRD_RX_DONE;
+	end
+
+	`S_RXPORTRD_RX_DONE: begin // Signal done
+		if (rMainState[3]) // S_RXPORTRD_MAIN_FLUSH
+			_rRxState = `S_RXPORTRD_RX_IDLE;
+	end
+	
+	default: begin
+		_rRxState = `S_RXPORTRD_RX_IDLE;
+	end
+	
+	endcase
+end
+
+
+// Count the data.
+always @ (posedge CLK) begin
+	rRecvdWords <= #1 _rRecvdWords;
+	rReqdWords <= #1 _rReqdWords;
+	rPartWords <= #1 _rPartWords;
+	rAckCount <= #1 _rAckCount;
+	rAckCountEQ0 <= #1 _rAckCountEQ0;
+	rPartWordsRecvd <= #1 _rPartWordsRecvd;
+	rRequestingWords <= #1 _rRequestingWords;
+	rAvailWords <= #1 _rAvailWords;
+	rCarryInv <= #1 _rCarryInv;
+	rSpaceAvail <= #1 _rSpaceAvail;
+	rLastDoneRead <= #1 (RST ? 1'd1 : _rLastDoneRead);	
+end
+
+always @ (*) begin
+	// Count words as they arrive (words from the rx_engine directly).
+	if (rMainState[0]) // S_RXPORTRD_MAIN_IDLE
+		_rRecvdWords = #1 0;
+	else
+		_rRecvdWords = #1 rRecvdWords + rRxDataEn;
+
+	// Count words as they are requested.
+	if (rMainState[0]) // S_RXPORTRD_MAIN_IDLE
+		_rReqdWords = #1 0;
+	else
+      _rReqdWords = #1 rReqdWords + ({10{RX_REQ_ACK}} & rLen);
+
+	// Track outstanding requests
+	if (rMainState[0]) // S_RXPORTRD_MAIN_IDLE
+		_rAckCount = 0;
+	else
+		_rAckCount = rAckCount + RX_REQ_ACK - RX_DONE;
+	_rAckCountEQ0 = (rAckCount == 11'd0);
+
+	// Track when the user reads the actual transfer amount.
+	_rLastDoneRead = (rTxnDone ? 1'd0 : (rLastDoneRead | rTxnDoneAck));
+
+	// Track the amount of words that are expected to arrive.
+	_rPartWords = #1 (rTxnLenValid ? rTxnData : rPartWords);
+
+	// Compare counts.
+	_rPartWordsRecvd = (rRecvdWords >= rPartWords);
+	_rRequestingWords = rReqdWords + rLen;
+	{_rCarryInv, _rAvailWords[15:0]} = {1'd1, rRequestingWords[15:0]} - CHNL_RX_CONSUMED[15:0];
+	_rAvailWords[31:16] = rRequestingWords[31:16] - CHNL_RX_CONSUMED[31:16] - !rCarryInv;
+	_rSpaceAvail = (rAvailWords <= C_FIFO_WORDS);
+end
+
+
+// Facilitate sending a TXN_DONE when we receive a TXN_ACK after the transaction
+// has begun sending. This will happen when the workstation detects that it has 
+// sent/used all its currently mapped scatter gather elements, but it's not enough 
+// to complete the transaction. The TXN_DONE will let the workstation know it can
+// release the current scatter gather mappings and allocate new ones.
+always @ (posedge CLK) begin
+	rPartialDone <= #1 _rPartialDone;
+	rReqPartialDone <= #1 (RST ? 1'd0 : _rReqPartialDone);
+end
+
+always @ (*) begin
+	// Signal TXN_DONE after we've recieved the (seemingly superfluous) TXN_ACK 
+	// and received the corresponding amount of words.
+	_rPartialDone = (rReqPartialDone & rPartWordsRecvd);
+	
+	// Keep track of (seemingly superfluous) TXN_ACK requests.
+	if ((rReqPartialDone & rPartWordsRecvd) | rMainState[0]) // S_RXPORTRD_MAIN_IDLE
+		_rReqPartialDone = 0;
+	else
+		_rReqPartialDone = (rReqPartialDone | rTxnLenValid);
+end
+
+
+// Handle errors in the main data or scatter gather data.
+always @ (posedge CLK) begin
+	rErr <= #1 (RST ? 1'd0 : _rErr);
+end
+
+always @ (*) begin
+	// Keep track of errors if we encounter them.
+	if (rMainState[0]) // S_RXPORTRD_MAIN_IDLE
+		_rErr = 0;
+	else
+		_rErr = (rErr | (RX_DONE & RX_ERR) | (SG_DONE & SG_ERR));
+end
+
+
+
+/*
+wire [35:0] wControl0;
+chipscope_icon_1 cs_icon(
+	.CONTROL0(wControl0)
+);
+
+chipscope_ila_t8_512 a0(
+	.CLK(CLK), 
+	.CONTROL(wControl0), 
+	.TRIG0({TXN_LEN_VALID | TXN_DONE_ACK | TXN_DONE | TXN_ERR, 1'd0, rMainState}),
+	.DATA({176'd0,
+			64'd0, // 64
+			rAddr, // 64
+			SG_ELEM_RDY, // 1
+			1'd0, // 1
+			1'd0, // 1
+			1'd0, // 1
+			rSgRen, // 1
+			1'd0, // 1
+			rLastDoneRead, // 1
+			rLen, // 10
+			rWords, // 32
+			rAckCount, // 11
+			rPartWords, // 32
+			rPartWordsRecvd, // 1
+			rReqPartialDone, // 1
+			rPartialDone, // 1
+			rTxnDone, // 1
+			rRxState, // 8
+			rRecvdWords, // 32
+			rReadWords, // 32
+			TXN_LEN_VALID, // 1
+			TXN_DONE_ACK, // 1
+			rDoneLen, // 32
+			rMainState}) // 6
+);
+*/
+
+endmodule
diff --git a/fpga/riffa_hdl/rx_port_requester_mux.v b/fpga/riffa_hdl/rx_port_requester_mux.v
new file mode 100644
index 0000000..594bb94
--- /dev/null
+++ b/fpga/riffa_hdl/rx_port_requester_mux.v
@@ -0,0 +1,211 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			rx_port_requester.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Issues read requests to the tx_engine for the rx_port
+// and sg_list_requester modules in the rx_port. Expects those modules to update
+// their address and length values after every request issued. Also expects them
+// to update their space available values within 6 cycles of a change to the
+// RX_LEN.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`define S_RXPORTREQ_RX_TX		2'b00
+`define S_RXPORTREQ_TX_RX		2'b01
+`define S_RXPORTREQ_ISSUE		2'b10
+
+`timescale 1ns/1ns
+module rx_port_requester_mux (
+	input RST,
+	input CLK,
+	
+	input SG_RX_REQ,				// Scatter gather RX read request
+	input [9:0] SG_RX_LEN,			// Scatter gather RX read request length
+	input [63:0] SG_RX_ADDR,		// Scatter gather RX read request address
+	output SG_RX_REQ_PROC,			// Scatter gather RX read request processing
+
+	input SG_TX_REQ,				// Scatter gather TX read request
+	input [9:0] SG_TX_LEN,			// Scatter gather TX read request length
+	input [63:0] SG_TX_ADDR,		// Scatter gather TX read request address
+	output SG_TX_REQ_PROC,			// Scatter gather TX read request processing
+	
+	input MAIN_REQ,					// Main read request
+	input [9:0] MAIN_LEN,			// Main read request length
+	input [63:0] MAIN_ADDR,			// Main read request address
+	output MAIN_REQ_PROC,			// Main read request processing
+
+	output RX_REQ,					// Read request
+	input RX_REQ_ACK,				// Read request accepted
+	output [1:0] RX_REQ_TAG,		// Read request data tag 
+	output [63:0] RX_REQ_ADDR,		// Read request address
+	output [9:0] RX_REQ_LEN,		// Read request length
+
+	output REQ_ACK					// Request accepted
+);
+
+reg									rRxReqAck=0, _rRxReqAck=0;
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg		[1:0]						rState=`S_RXPORTREQ_RX_TX, _rState=`S_RXPORTREQ_RX_TX;
+reg		[9:0]						rLen=0, _rLen=0;
+reg		[63:0]						rAddr=64'd0, _rAddr=64'd0;
+reg									rSgRxAck=0, _rSgRxAck=0;
+reg									rSgTxAck=0, _rSgTxAck=0;
+reg									rMainAck=0, _rMainAck=0;
+reg									rAck=0, _rAck=0;
+
+
+assign SG_RX_REQ_PROC = rSgRxAck;
+assign SG_TX_REQ_PROC = rSgTxAck;
+assign MAIN_REQ_PROC = rMainAck;
+
+assign RX_REQ = rState[1]; // S_RXPORTREQ_ISSUE
+assign RX_REQ_TAG = {rSgTxAck, rSgRxAck};
+assign RX_REQ_ADDR = rAddr;
+assign RX_REQ_LEN = rLen;
+
+assign REQ_ACK = rAck;
+
+
+// Buffer signals that come from outside the rx_port.
+always @ (posedge CLK) begin
+	rRxReqAck <= #1 (RST ? 1'd0 : _rRxReqAck);
+end
+
+always @ (*) begin
+	_rRxReqAck = RX_REQ_ACK;
+end
+
+
+// Handle issuing read requests. Scatter gather requests are processed
+// with higher priority than the main channel.
+always @ (posedge CLK) begin
+	rState <= #1 (RST ? `S_RXPORTREQ_RX_TX : _rState);
+	rLen <= #1 _rLen;
+	rAddr <= #1 _rAddr;
+	rSgRxAck <= #1 _rSgRxAck;
+	rSgTxAck <= #1 _rSgTxAck;
+	rMainAck <= #1 _rMainAck;
+	rAck <= #1 _rAck;
+end
+
+always @ (*) begin
+	_rState = rState;
+	_rLen = rLen;
+	_rAddr = rAddr;
+	_rSgRxAck = rSgRxAck;
+	_rSgTxAck = rSgTxAck;
+	_rMainAck = rMainAck;
+	_rAck = rAck;
+	case (rState)
+
+	`S_RXPORTREQ_RX_TX: begin // Wait for a new read request
+		if (SG_RX_REQ) begin
+			_rLen = SG_RX_LEN;
+			_rAddr = SG_RX_ADDR;
+			_rSgRxAck = 1;
+			_rAck = 1;
+			_rState = `S_RXPORTREQ_ISSUE;
+		end
+		else if (SG_TX_REQ) begin
+			_rLen = SG_TX_LEN;
+			_rAddr = SG_TX_ADDR;
+			_rSgTxAck = 1;
+			_rAck = 1;
+			_rState = `S_RXPORTREQ_ISSUE;
+		end
+		else if (MAIN_REQ) begin
+			_rLen = MAIN_LEN;
+			_rAddr = MAIN_ADDR;
+			_rMainAck = 1;
+			_rAck = 1;
+			_rState = `S_RXPORTREQ_ISSUE;
+		end
+		else begin
+			_rState = `S_RXPORTREQ_TX_RX;
+		end
+	end
+
+	`S_RXPORTREQ_TX_RX: begin // Wait for a new read request
+		if (SG_TX_REQ) begin
+			_rLen = SG_TX_LEN;
+			_rAddr = SG_TX_ADDR;
+			_rSgTxAck = 1;
+			_rAck = 1;
+			_rState = `S_RXPORTREQ_ISSUE;
+		end
+		else if (SG_RX_REQ) begin
+			_rLen = SG_RX_LEN;
+			_rAddr = SG_RX_ADDR;
+			_rSgRxAck = 1;
+			_rAck = 1;
+			_rState = `S_RXPORTREQ_ISSUE;
+		end
+		else if (MAIN_REQ) begin
+			_rLen = MAIN_LEN;
+			_rAddr = MAIN_ADDR;
+			_rMainAck = 1;
+			_rAck = 1;
+			_rState = `S_RXPORTREQ_ISSUE;
+		end
+		else begin
+			_rState = `S_RXPORTREQ_RX_TX;
+		end
+	end
+
+	`S_RXPORTREQ_ISSUE: begin // Issue the request
+		_rAck = 0;
+		if (rRxReqAck) begin
+			_rSgRxAck = 0;
+			_rSgTxAck = 0;
+			_rMainAck = 0;
+			if (rSgRxAck)
+				_rState = `S_RXPORTREQ_TX_RX;
+			else
+				_rState = `S_RXPORTREQ_RX_TX;
+		end
+	end
+
+	default: begin
+		_rState = `S_RXPORTREQ_RX_TX;
+	end
+
+	endcase
+end
+
+endmodule
diff --git a/fpga/riffa_hdl/rxc_engine_classic.v b/fpga/riffa_hdl/rxc_engine_classic.v
new file mode 100644
index 0000000..ca906df
--- /dev/null
+++ b/fpga/riffa_hdl/rxc_engine_classic.v
@@ -0,0 +1,785 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            rxc_engine_classic.v
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The RXC Engine (Classic) takes a single stream of TLP
+// packets and provides the completion packets on the RXC Interface.
+// This Engine is capable of operating at "line rate".
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "trellis.vh"
+`include "tlp.vh"
+module rxc_engine_classic
+    #(parameter C_VENDOR = "ALTERA",
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_RX_PIPELINE_DEPTH = 10
+      )
+    (
+     // Interface: Clocks
+     input                                                CLK,
+
+     // Interface: Resets
+     input                                                RST_IN,
+
+     // Interface: RX Classic
+     input [C_PCI_DATA_WIDTH-1:0]                         RX_TLP,
+     input                                                RX_TLP_VALID,
+     input                                                RX_TLP_START_FLAG,
+     input [`SIG_OFFSET_W-1:0]                            RX_TLP_START_OFFSET,
+     input                                                RX_TLP_END_FLAG,
+     input [`SIG_OFFSET_W-1:0]                            RX_TLP_END_OFFSET,
+     input [`SIG_BARDECODE_W-1:0]                         RX_TLP_BAR_DECODE,
+
+     // Interface: RXC Engine
+     output [C_PCI_DATA_WIDTH-1:0]                        RXC_DATA,
+     output                                               RXC_DATA_VALID,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]                   RXC_DATA_WORD_ENABLE,
+     output                                               RXC_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXC_DATA_START_OFFSET,
+     output                                               RXC_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXC_DATA_END_OFFSET,
+
+     output [`SIG_LBE_W-1:0]                              RXC_META_LDWBE,
+     output [`SIG_FBE_W-1:0]                              RXC_META_FDWBE,
+     output [`SIG_TAG_W-1:0]                              RXC_META_TAG,
+     output [`SIG_LOWADDR_W-1:0]                          RXC_META_ADDR,
+     output [`SIG_TYPE_W-1:0]                             RXC_META_TYPE,
+     output [`SIG_LEN_W-1:0]                              RXC_META_LENGTH,
+     output [`SIG_BYTECNT_W-1:0]                          RXC_META_BYTES_REMAINING,
+     output [`SIG_CPLID_W-1:0]                            RXC_META_COMPLETER_ID,
+     output                                               RXC_META_EP,
+    
+     // Interface: RX Shift Register
+     input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
+     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_EOP,
+     input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    RX_SR_END_OFFSET,
+     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_SOP,
+     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_VALID
+     );
+
+
+    /*AUTOWIRE*/
+    /*AUTOINPUT*/
+    ///*AUTOOUTPUT*/
+    // End of automatics
+    localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
+
+    localparam C_RX_INPUT_STAGES = 1;
+    localparam C_RX_OUTPUT_STAGES = 1; // Must always be at least one
+    localparam C_RX_COMPUTATION_STAGES = 1;
+    localparam C_RX_DATA_STAGES = C_RX_COMPUTATION_STAGES;
+    localparam C_RX_META_STAGES = C_RX_DATA_STAGES - 1;
+    localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
+    
+    // Cycle index in the SOP register when enable is raised
+    // Computation can begin when the last DW of the header is recieved. 
+    localparam C_RX_COMPUTATION_CYCLE = C_RX_COMPUTATION_STAGES + (`TLP_CPLMETADW2_I/C_PCI_DATA_WIDTH);
+    // The computation cycle must be at least one cycle before the address is enabled
+    localparam C_RX_DATA_CYCLE = C_RX_COMPUTATION_CYCLE;
+
+    localparam C_RX_METADW0_CYCLE = (`TLP_CPLMETADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+    localparam C_RX_METADW1_CYCLE = (`TLP_CPLMETADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+    localparam C_RX_METADW2_CYCLE = (`TLP_CPLMETADW2_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+
+    localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_CPLMETADW0_I%C_PCI_DATA_WIDTH);
+    localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_CPLMETADW1_I%C_PCI_DATA_WIDTH);
+    localparam C_RX_METADW2_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_CPLMETADW2_I%C_PCI_DATA_WIDTH);
+
+    localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
+    localparam C_MAX_ABLANK_WIDTH = 32;
+    localparam C_MAX_START_OFFSET = (`TLP_MAXHDR_W + C_MAX_ABLANK_WIDTH)/32;
+    localparam C_STD_START_DELAY = (64/C_PCI_DATA_WIDTH);
+
+    wire [`TLP_CPLADDR_W-1:0]                             wAddr;
+    wire [`TLP_CPLHDR_W-1:0]                              wMetadata;
+    wire [`TLP_TYPE_W-1:0]                                wType;
+    wire [`TLP_LEN_W-1:0]                                 wLength;
+    wire [2:0]                                            wHdrLength;
+    wire [2:0]                                            wHdrLengthM1;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wEndMask;
+    wire                                                  wEndFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]                wEndOffset;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wStartMask;
+    wire                                                  wStartFlag;
+    wire                                                  _wStartFlag;
+    wire [2:0]                                            wStartOffset;
+    wire [3:0]                                            wStartFlags;
+    
+    wire                                                  wInsertBlank;
+
+    wire [C_PCI_DATA_WIDTH-1:0]                           wRxcData;
+
+    wire [95:0]                                           wRxcMetadata;
+    wire                                                  wRxcDataValid;
+    wire                                                  wRxcDataEndFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]                wRxcDataEndOffset;
+    wire                                                  wRxcDataStartFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]                wRxcDataStartOffset;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wRxcDataWordEnable;
+    wire [C_RX_PIPELINE_DEPTH:0]                          wRxSrSop;
+
+    reg                                                   rValid,_rValid;
+    
+    
+    // Calculate the header length (start offset), and header length minus 1 (end offset)
+    assign wHdrLength = 3'b011;
+    assign wHdrLengthM1 = 3'b010;
+    // Determine if the TLP has an inserted blank before the payload
+    assign wInsertBlank = ~wAddr[2] & (C_VENDOR == "ALTERA");
+
+    assign wStartOffset = (wHdrLength + {2'd0,wInsertBlank}); // Start offset in dwords
+    assign wEndOffset = wHdrLengthM1 + wInsertBlank + wLength; //RX_SR_END_OFFSET[(C_TOTAL_STAGES-1)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
+    
+    // Outputs
+    assign RXC_DATA = RX_SR_DATA[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
+    assign RXC_DATA_VALID = wRxcDataValid;
+    assign RXC_DATA_END_FLAG = wRxcDataEndFlag;
+    assign RXC_DATA_END_OFFSET = wRxcDataEndOffset;
+    assign RXC_DATA_START_FLAG = wRxcDataStartFlag;
+    assign RXC_DATA_START_OFFSET = wRxcDataStartOffset;
+
+    assign RXC_META_LENGTH = wRxcMetadata[`TLP_LEN_R];
+    //assign RXC_META_TC = wRxcMetadata[`TLP_TC_R];
+    //assign RXC_META_ATTR = {wRxcMetadata[`TLP_ATTR1_R], wRxcMetadata[`TLP_ATTR0_R]};
+    assign RXC_META_TYPE = tlp_to_trellis_type({wRxcMetadata[`TLP_FMT_R],wRxcMetadata[`TLP_TYPE_R]});
+    assign RXC_META_ADDR = wRxcMetadata[`TLP_CPLADDR_R];
+    assign RXC_META_COMPLETER_ID = wRxcMetadata[`TLP_CPLCPLID_R];
+    assign RXC_META_BYTES_REMAINING = wRxcMetadata[`TLP_CPLBYTECNT_R];
+    assign RXC_META_TAG = wRxcMetadata[`TLP_CPLTAG_R];
+    assign RXC_META_EP = wRxcMetadata[`TLP_EP_R];
+    assign RXC_META_FDWBE = 0;// TODO: Remove (use addr)
+    assign RXC_META_LDWBE = 0;// TODO: Remove (use addr)
+    
+    assign wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES+1];
+    assign _wStartFlag = wStartFlags != 0;
+
+    generate
+        if(C_PCI_DATA_WIDTH == 32) begin
+            assign wStartFlags[3] = 0;
+            assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 3] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
+            assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
+            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~wMetadata[`TLP_PAYBIT_I]; // No Payload
+        end else if(C_PCI_DATA_WIDTH == 64) begin
+            assign wStartFlags[3] = 0;
+            assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
+            if(C_VENDOR == "ALTERA") begin
+                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_METADW2_INDEX + 2]; // 3DWH, No Blank
+            end else begin
+                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
+            end
+            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~wMetadata[`TLP_PAYBIT_I] & rValid; // No Payload
+        end else if (C_PCI_DATA_WIDTH == 128) begin    
+            assign wStartFlags[3] = 0;
+            assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Is this correct?
+            if(C_VENDOR == "ALTERA") begin
+                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_METADW2_INDEX + 2]; // 3DWH, No Blank
+            end else begin
+                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I];
+            end
+            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I]; // No Payload
+        end else begin // 256
+            assign wStartFlags[3] = 0;
+            assign wStartFlags[2] = 0;
+            assign wStartFlags[1] = 0;
+            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
+        end // else: !if(C_PCI_DATA_WIDTH == 128)
+    endgenerate
+
+    always @(*) begin
+        _rValid = rValid;
+        if(_wStartFlag) begin
+	        _rValid = 1'b1;
+        end else if (RX_SR_EOP[C_RX_INPUT_STAGES+1]) begin
+	        _rValid = 1'b0;
+        end
+    end
+    
+    always @(posedge CLK) begin
+        if(RST_IN) begin
+	        rValid <= 1'b0;
+        end else begin
+	        rValid <= _rValid;
+        end
+    end
+
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (32))
+    metadata_DW0_register
+        (
+         // Outputs
+         .RD_DATA                       (wMetadata[31:0]),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .WR_DATA                       (RX_SR_DATA[C_RX_METADW0_INDEX +: 32]),
+         .WR_EN                         (wRxSrSop[C_RX_METADW0_CYCLE]));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (32))
+    meta_DW1_register
+        (
+         // Outputs
+         .RD_DATA                       (wMetadata[63:32]),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .WR_DATA                       (RX_SR_DATA[C_RX_METADW1_INDEX +: 32]),
+         .WR_EN                         (wRxSrSop[C_RX_METADW1_CYCLE]));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (32))
+    meta_DW2_register
+        (
+         // Outputs
+         .RD_DATA                       (wMetadata[95:64]),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .WR_DATA                       (RX_SR_DATA[C_RX_METADW2_INDEX +: 32]),
+         .WR_EN                         (wRxSrSop[C_RX_METADW2_CYCLE]));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (`TLP_TYPE_W))
+    metadata_type_register
+        (
+         // Outputs
+         .RD_DATA                       (wType),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .WR_DATA                       (RX_SR_DATA[(`TLP_TYPE_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_TYPE_W]),
+         .WR_EN                         (wRxSrSop[`TLP_TYPE_I/C_PCI_DATA_WIDTH  + C_RX_INPUT_STAGES]));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (`TLP_LEN_W))
+    metadata_length_register
+        (
+         // Outputs
+         .RD_DATA                       (wLength),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .WR_DATA                       (RX_SR_DATA[((`TLP_LEN_I%C_PCI_DATA_WIDTH) + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_LEN_W]),
+         .WR_EN                         (wRxSrSop[`TLP_LEN_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (`TLP_CPLADDR_W))
+    metadata_address_register
+        (
+         // Outputs
+         .RD_DATA                       (wAddr),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .WR_DATA                       (RX_SR_DATA[((`TLP_CPLADDR_I%C_PCI_DATA_WIDTH) + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_CPLADDR_W]),
+         .WR_EN                         (wRxSrSop[`TLP_CPLADDR_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]));
+
+    
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (1),
+          .C_VALUE                      (1'b0)
+          /*AUTOINSTPARAM*/)
+    start_flag_register
+        (
+         // Outputs
+         .RD_DATA                       (wStartFlag),
+         // Inputs
+         .WR_DATA                       (_wStartFlag),
+         .WR_EN                         (1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
+
+    offset_to_mask
+        #(// Parameters
+          .C_MASK_SWAP                  (0),
+          .C_MASK_WIDTH                 (C_PCI_DATA_WIDTH/32)
+          /*AUTOINSTPARAM*/)
+    o2m_ef
+        (
+         // Outputs
+         .MASK                          (wEndMask),
+         // Inputs
+         .OFFSET_ENABLE                 (wEndFlag),
+         .OFFSET                        (wEndOffset)
+         /*AUTOINST*/);
+    generate
+        if(C_RX_OUTPUT_STAGES == 0) begin
+            assign RXC_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | ~wMetadata[`TLP_PAYBIT_I]}};
+        end else begin
+            register
+                #(
+                  // Parameters
+                  .C_WIDTH              (C_PCI_DATA_WIDTH/32),
+                  .C_VALUE              (0)
+                  /*AUTOINSTPARAM*/)
+            dw_enable
+                (// Outputs
+                 .RD_DATA               (wRxcDataWordEnable),
+                 // Inputs
+                 .RST_IN                (~rValid | ~wMetadata[`TLP_PAYBIT_I]),
+                 .WR_DATA               (wEndMask & wStartMask),
+                 .WR_EN                 (1),
+                 /*AUTOINST*/
+                 .CLK                   (CLK));
+
+            pipeline
+                #(
+                  // Parameters
+                  .C_DEPTH                      (C_RX_OUTPUT_STAGES-1),
+                  .C_WIDTH                      (C_PCI_DATA_WIDTH/32),
+                  .C_USE_MEMORY                 (0)
+                  /*AUTOINSTPARAM*/)
+            dw_pipeline
+                (
+                 // Outputs
+                 .WR_DATA_READY                 (), // Pinned to 1
+                 .RD_DATA                       (RXC_DATA_WORD_ENABLE),
+                 .RD_DATA_VALID                 (),
+                 // Inputs
+                 .WR_DATA                       (wRxcDataWordEnable),
+                 .WR_DATA_VALID                 (1),
+                 .RD_DATA_READY                 (1'b1),
+                 /*AUTOINST*/
+                 // Inputs
+                 .CLK                           (CLK),
+                 .RST_IN                        (RST_IN));
+
+        end
+    endgenerate
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_RX_OUTPUT_STAGES),
+          .C_WIDTH                      (`TLP_CPLHDR_W + 2*(clog2s(C_PCI_DATA_WIDTH/32) + 1)),
+          .C_USE_MEMORY                 (0)
+          /*AUTOINSTPARAM*/)
+    output_pipeline
+        (
+         // Outputs
+         .WR_DATA_READY                 (), // Pinned to 1
+         .RD_DATA                       ({wRxcMetadata,wRxcDataStartFlag,wRxcDataStartOffset,wRxcDataEndFlag,wRxcDataEndOffset}),
+         .RD_DATA_VALID                 (wRxcDataValid),
+         // Inputs
+         .WR_DATA                       ({wMetadata, wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0]}),
+         .WR_DATA_VALID                 (rValid),
+         .RD_DATA_READY                 (1'b1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+    // Start Flag Shift Register. Data enables are derived from the
+    // taps on this shift register.
+    shiftreg 
+        #(
+          // Parameters
+          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                      (1'b1)
+          /*AUTOINSTPARAM*/)
+    sop_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                       (wRxSrSop),
+         // Inputs
+         .WR_DATA                       (RX_TLP_START_FLAG & RX_TLP_VALID & (RX_SR_DATA[`TLP_TYPE_R] == `TLP_TYPE_CPL)),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+endmodule
+module rxc_engine_128
+    #(parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_RX_PIPELINE_DEPTH=10
+      )
+    (
+     // Interface: Clocks
+     input                                                CLK,
+
+     // Interface: Resets
+     input                                                RST_IN,
+
+     // Interface: RX Classic
+     input [C_PCI_DATA_WIDTH-1:0]                         RX_TLP,
+     input                                                RX_TLP_VALID,
+     input                                                RX_TLP_START_FLAG,
+     input [`SIG_OFFSET_W-1:0]                            RX_TLP_START_OFFSET,
+     input                                                RX_TLP_END_FLAG,
+     input [`SIG_OFFSET_W-1:0]                            RX_TLP_END_OFFSET,
+     input [`SIG_BARDECODE_W-1:0]                         RX_TLP_BAR_DECODE,
+
+     // Interface: RXC Engine
+     output [C_PCI_DATA_WIDTH-1:0]                        RXC_DATA,
+     output                                               RXC_DATA_VALID,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]                   RXC_DATA_WORD_ENABLE,
+     output                                               RXC_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXC_DATA_START_OFFSET,
+     output                                               RXC_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXC_DATA_END_OFFSET,
+
+     output [`SIG_LBE_W-1:0]                              RXC_META_LDWBE,
+     output [`SIG_FBE_W-1:0]                              RXC_META_FDWBE,
+     output [`SIG_TAG_W-1:0]                              RXC_META_TAG,
+     output [`SIG_LOWADDR_W-1:0]                          RXC_META_ADDR,
+     output [`SIG_TYPE_W-1:0]                             RXC_META_TYPE,
+     output [`SIG_LEN_W-1:0]                              RXC_META_LENGTH,
+     output [`SIG_BYTECNT_W-1:0]                          RXC_META_BYTES_REMAINING,
+     output [`SIG_CPLID_W-1:0]                            RXC_META_COMPLETER_ID,
+     output                                               RXC_META_EP,
+
+     // Interface: RX Shift Register
+     input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
+     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_EOP,
+     input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    RX_SR_END_OFFSET,
+     input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    RX_SR_START_OFFSET,
+     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_SOP,
+     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_VALID
+     );
+
+    /*AUTOWIRE*/
+    ///*AUTOOUTPUT*/
+    localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
+    localparam C_RX_INPUT_STAGES = 1;
+    localparam C_RX_OUTPUT_STAGES = 1;
+    localparam C_RX_COMPUTATION_STAGES = 1;
+    localparam C_RX_HDR_STAGES = 1; // Specific to the Xilinx 128-bit RXC Engine
+    localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES + C_RX_HDR_STAGES;
+
+    localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
+    localparam C_STRADDLE_W = 64;
+    localparam C_HDR_NOSTRADDLE_I = C_RX_INPUT_STAGES * C_PCI_DATA_WIDTH;
+    localparam C_OUTPUT_STAGE_WIDTH = (C_PCI_DATA_WIDTH/32) + 2 + clog2s(C_PCI_DATA_WIDTH/32) + 1 + `SIG_TAG_W + `SIG_TYPE_W + `SIG_LOWADDR_W + `SIG_REQID_W + `SIG_LEN_W + `SIG_BYTECNT_W;
+
+    // Header Reg Inputs
+    wire [`SIG_OFFSET_W-1:0]                              __wRxcStartOffset; 
+    wire [`SIG_OFFSET_W-1:0]                              __wRxcStraddledStartOffset; 
+    wire [`TLP_MAXHDR_W-1:0]                              __wRxcHdr;
+    wire [`TLP_MAXHDR_W-1:0]                              __wRxcHdrStraddled;
+    wire [`TLP_MAXHDR_W-1:0]                              __wRxcHdrNotStraddled;
+    wire                                                  __wRxcHdrStraddle;
+    wire                                                  __wRxcHdrValid;
+    wire                                                  __wRxcHdrSOP;
+    wire                                                  __wRxcHdrSOPStraddle;
+
+    // Header Reg Outputs
+    wire                                                  _wRxcHdrValid;
+    wire                                                  _wRxcHdrStraddle;
+    wire                                                  _wRxcHdrSOPStraddle;
+    wire                                                  _wRxcHdrSOP;
+    wire [`TLP_MAXHDR_W-1:0]                              _wRxcHdr;
+
+    wire                                                  _wRxcHdrSF;
+    wire [2:0]                                            _wRxcHdrDataSoff;
+    wire                                                  _wRxcHdrEF;
+    wire [1:0]                                            _wRxcHdrDataEoff;
+    wire                                                  _wRxcHdrSCP; // Single Cycle Packet
+    wire                                                  _wRxcHdrMCP; // Multi Cycle Packet
+    wire                                                  _wRxcHdrRegSF;
+    wire                                                  _wRxcHdrRegValid;
+    wire                                                  _wRxcHdrStartFlag;
+    wire                                                  _wRxcHdr3DWHSF;
+    wire [3:0]                                            _wRxcHdrStartMask;
+    wire [3:0]                                            _wRxcHdrEndMask;
+    
+    // Header Reg Outputs
+    wire [`TLP_MAXHDR_W-1:0]                              wRxcHdr;
+    wire                                                  wRxcHdrSF;
+    wire                                                  wRxcHdrEF;    
+    wire                                                  wRxcHdrValid;
+    wire [63:0]                                           wRxcMetadata;
+    wire [`TLP_TYPE_W-1:0]                                wRxcType;
+    wire [`TLP_LEN_W-1:0]                                 wRxcLength;
+    wire [2:0]                                            wRxcHdrLength;// TODO: 
+    wire [`SIG_OFFSET_W-1:0]                              wRxcHdrStartOffset;// TODO: 
+    wire                                                  wRxcHdrSCP; // Single Cycle Packet
+    wire                                                  wRxcHdrMCP; // Multi Cycle Packet
+    wire [1:0]                                            wRxcHdrDataSoff;
+    wire [3:0]                                            wRxcHdrStartMask;
+    wire [3:0]                                            wRxcHdrEndMask;
+
+    // Output Register Inputs
+    wire [C_PCI_DATA_WIDTH-1:0]                           wRxcData;
+    wire                                                  wRxcDataValid;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wRxcDataWordEnable;
+    wire                                                  wRxcDataStartFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]                wRxcDataStartOffset;
+    wire                                                  wRxcDataEndFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]                wRxcDataEndOffset;
+    wire [`SIG_TAG_W-1:0]                                 wRxcMetaTag;
+    wire [`SIG_TYPE_W-1:0]                                wRxcMetaType;
+    wire [`SIG_LOWADDR_W-1:0]                             wRxcMetaAddr;
+    wire [`SIG_REQID_W-1:0]                               wRxcMetaCompleterId;
+    wire [`SIG_LEN_W-1:0]                                 wRxcMetaLength;
+    wire                                                  wRxcMetaEP;
+    wire [`SIG_BYTECNT_W-1:0]                             wRxcMetaBytesRemaining;
+
+    reg                                                   rStraddledSOP;
+    reg                                                   rStraddledSOPSplit;    
+
+    // ----- Header Register -----
+    assign __wRxcHdrSOP = RX_SR_SOP[C_RX_INPUT_STAGES] & ~__wRxcStartOffset[1];
+    assign __wRxcHdrSOPStraddle = RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxcStraddledStartOffset[1];
+
+    assign __wRxcHdrNotStraddled = RX_SR_DATA[C_HDR_NOSTRADDLE_I +: C_PCI_DATA_WIDTH];
+    assign __wRxcHdrStraddled = {RX_SR_DATA[C_RX_INPUT_STAGES*C_PCI_DATA_WIDTH +: C_STRADDLE_W],
+                                 RX_SR_DATA[(C_RX_INPUT_STAGES+1)*C_PCI_DATA_WIDTH + C_STRADDLE_W +: C_STRADDLE_W ]};
+    assign __wRxcStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*C_RX_INPUT_STAGES +: `SIG_OFFSET_W];
+    assign __wRxcStraddledStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*(C_RX_INPUT_STAGES) +: `SIG_OFFSET_W];
+    assign __wRxcHdrValid = __wRxcHdrSOP | ((rStraddledSOP | rStraddledSOPSplit) & RX_SR_VALID[C_RX_INPUT_STAGES]);
+
+    assign _wRxcHdrRegSF = RX_SR_SOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES] & _wRxcHdrValid;
+    assign _wRxcHdrDataSoff = {1'b0,_wRxcHdrSOPStraddle,1'b0} + 3'd3;
+    assign _wRxcHdrRegValid = RX_SR_VALID[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
+    assign _wRxcHdr3DWHSF = ~_wRxcHdr[`TLP_4DWHBIT_I] & _wRxcHdrSOP;
+
+    assign _wRxcHdrSF = (_wRxcHdr3DWHSF | _wRxcHdrSOPStraddle);
+    assign _wRxcHdrEF = RX_SR_EOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
+    assign _wRxcHdrDataEoff = RX_SR_END_OFFSET[(C_RX_INPUT_STAGES+C_RX_HDR_STAGES)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
+
+    assign _wRxcHdrSCP = _wRxcHdrSF & _wRxcHdrEF & (_wRxcHdr[`TLP_TYPE_R] == `TLP_TYPE_CPL);
+    assign _wRxcHdrMCP = (_wRxcHdrSF & ~_wRxcHdrEF & (_wRxcHdr[`TLP_TYPE_R] == `TLP_TYPE_CPL)) | 
+                         (wRxcHdrMCP & ~wRxcHdrEF);
+
+    assign _wRxcHdrStartMask = 4'hf << (_wRxcHdrSF ? _wRxcHdrDataSoff[1:0] : 0);
+
+    assign wRxcDataWordEnable = wRxcHdrEndMask & wRxcHdrStartMask & {4{wRxcDataValid}};
+    assign wRxcDataValid = wRxcHdrSCP | wRxcHdrMCP;
+    assign wRxcDataStartFlag = wRxcHdrSF;
+    assign wRxcDataEndFlag = wRxcHdrEF;
+    assign wRxcDataStartOffset = wRxcHdrDataSoff;
+    assign wRxcMetaBytesRemaining = wRxcHdr[`TLP_CPLBYTECNT_R];
+    assign wRxcMetaTag = wRxcHdr[`TLP_CPLTAG_R];
+    assign wRxcMetaAddr = wRxcHdr[`TLP_CPLADDR_R];
+    assign wRxcMetaCompleterId = wRxcHdr[`TLP_REQREQID_R];
+    assign wRxcMetaLength = wRxcHdr[`TLP_LEN_R];
+    assign wRxcMetaEP = wRxcHdr[`TLP_EP_R];
+    assign wRxcMetaType = tlp_to_trellis_type({wRxcHdr[`TLP_FMT_R],wRxcHdr[`TLP_TYPE_R]});
+
+    assign RXC_DATA = RX_SR_DATA[C_PCI_DATA_WIDTH*C_TOTAL_STAGES +: C_PCI_DATA_WIDTH];
+    assign RXC_DATA_END_OFFSET = RX_SR_END_OFFSET[`SIG_OFFSET_W*(C_TOTAL_STAGES) +: C_OFFSET_WIDTH];
+    
+    always @(posedge CLK) begin
+        rStraddledSOP <= RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxcStraddledStartOffset[1];
+        // Set Straddled SOP Split when there is a straddled packet where the
+        // header is not contiguous. (Not sure if this is ever possible, but
+        // better safe than sorry assert Straddled SOP Split. See Virtex 6 PCIe
+        // errata.)
+        if(__wRxcHdrSOP | RST_IN) begin
+            rStraddledSOPSplit <=0;
+        end else begin
+            rStraddledSOPSplit <= (rStraddledSOP | rStraddledSOPSplit) & ~RX_SR_VALID[C_RX_INPUT_STAGES];
+        end
+        
+    end
+    
+    mux
+        #(
+          // Parameters
+          .C_NUM_INPUTS                 (2),
+          .C_CLOG_NUM_INPUTS            (1),
+          .C_WIDTH                      (`TLP_MAXHDR_W),
+          .C_MUX_TYPE                   ("SELECT")
+          /*AUTOINSTPARAM*/)
+    hdr_mux
+        (
+         // Outputs
+         .MUX_OUTPUT                    (__wRxcHdr[`TLP_MAXHDR_W-1:0]),
+         // Inputs
+         .MUX_INPUTS                    ({__wRxcHdrStraddled[`TLP_MAXHDR_W-1:0],
+                                          __wRxcHdrNotStraddled[`TLP_MAXHDR_W-1:0]}),
+         .MUX_SELECT                    (rStraddledSOP | rStraddledSOPSplit)
+         /*AUTOINST*/);
+    
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (64 + 1),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    hdr_register_63_0
+        (
+         // Outputs
+         .RD_DATA                       ({_wRxcHdr[C_STRADDLE_W-1:0], _wRxcHdrValid}),
+         // Inputs
+         .WR_DATA                       ({__wRxcHdr[C_STRADDLE_W-1:0], __wRxcHdrValid}),
+         .WR_EN                         (__wRxcHdrSOP | rStraddledSOP),
+         .RST_IN                        (RST_IN), // TODO: Remove
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (64),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    hdr_register_127_64
+        (
+         // Outputs
+         .RD_DATA                       (_wRxcHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
+         // Inputs
+         .WR_DATA                       (__wRxcHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
+         .WR_EN                         (__wRxcHdrSOP | rStraddledSOP | rStraddledSOPSplit), // Non straddled start, Straddled, or straddled split
+         .RST_IN                        (RST_IN), // TODO: Remove
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (2),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    sf4dwh// TODO: Rename
+        (
+         // Outputs
+         .RD_DATA                       ({_wRxcHdrSOPStraddle,_wRxcHdrSOP}),
+         // Inputs
+         .WR_DATA                       ({rStraddledSOP,__wRxcHdrSOP}),
+         .WR_EN                         (1),
+         .RST_IN                        (RST_IN), // TODO: Remove
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK));
+
+    // ----- Computation Register -----
+    register
+        #(
+          // Parameters
+          .C_WIDTH              (128 + 4),/* TODO: TLP_METADATA_W*/
+          .C_VALUE              (0)
+          /*AUTOINSTPARAM*/)
+    metadata 
+        (// Output
+         .RD_DATA               ({wRxcHdr,
+                                  wRxcHdrSF, wRxcHdrDataSoff,
+                                  wRxcHdrEF}),
+         // Inputs
+         .RST_IN                (0),
+         .WR_DATA               ({_wRxcHdr,
+                                  _wRxcHdrSF, _wRxcHdrDataSoff[1:0],
+                                  _wRxcHdrEF}),
+         .WR_EN                 (1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH              (3+8),
+          .C_VALUE              (0)
+          /*AUTOINSTPARAM*/)
+    metadata_valid
+        (// Output
+         .RD_DATA               ({wRxcHdrValid, 
+                                  wRxcHdrSCP, wRxcHdrMCP,
+                                  wRxcHdrEndMask, wRxcHdrStartMask}),
+         // Inputs
+         .RST_IN                (RST_IN),
+         .WR_DATA               ({_wRxcHdrValid, 
+                                  _wRxcHdrSCP, _wRxcHdrMCP,
+                                  _wRxcHdrEndMask, _wRxcHdrStartMask}), // Need to invert the start mask
+         .WR_EN                 (1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK));
+
+    offset_to_mask
+        #(// Parameters
+          .C_MASK_SWAP                  (0),
+          .C_MASK_WIDTH                 (4)
+          /*AUTOINSTPARAM*/)
+    o2m_ef
+        (
+         // Outputs
+         .MASK                          (_wRxcHdrEndMask),
+         // Inputs
+         .OFFSET_ENABLE                 (_wRxcHdrEF),
+         .OFFSET                        (_wRxcHdrDataEoff)
+         /*AUTOINST*/);
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_RX_OUTPUT_STAGES),
+          .C_WIDTH                      (C_OUTPUT_STAGE_WIDTH),
+          .C_USE_MEMORY                 (0)
+          /*AUTOINSTPARAM*/)
+    output_pipeline
+        (
+         // Outputs
+         .WR_DATA_READY                 (), // Pinned to 1
+         .RD_DATA                       ({RXC_DATA_WORD_ENABLE, RXC_DATA_START_FLAG, RXC_DATA_START_OFFSET,
+                                          RXC_DATA_END_FLAG, RXC_META_TAG, RXC_META_TYPE, 
+                                          RXC_META_ADDR, RXC_META_COMPLETER_ID, RXC_META_BYTES_REMAINING, 
+                                          RXC_META_LENGTH, RXC_META_EP}),
+         .RD_DATA_VALID                 (RXC_DATA_VALID),
+         // Inputs
+         .WR_DATA                       ({wRxcDataWordEnable, wRxcDataStartFlag, wRxcDataStartOffset,
+                                          wRxcDataEndFlag, wRxcMetaTag, wRxcMetaType, 
+                                          wRxcMetaAddr, wRxcMetaCompleterId, wRxcMetaBytesRemaining,
+                                          wRxcMetaLength, wRxcMetaEP}),
+         .WR_DATA_VALID                 (wRxcDataValid),
+         .RD_DATA_READY                 (1'b1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+endmodule
diff --git a/fpga/riffa_hdl/rxc_engine_ultrascale.v b/fpga/riffa_hdl/rxc_engine_ultrascale.v
new file mode 100644
index 0000000..6fb3735
--- /dev/null
+++ b/fpga/riffa_hdl/rxc_engine_ultrascale.v
@@ -0,0 +1,453 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            rxc_engine_classic.v
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The RXC Engine (Ultrascale) takes a single stream of 
+// AXI packets and provides the completion packets on the RXC Interface.
+// This Engine is capable of operating at "line rate".
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "trellis.vh"
+`include "ultrascale.vh"
+module rxc_engine_ultrascale
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_RX_PIPELINE_DEPTH=10,
+      // Number of data pipeline registers for metadata and data stages
+      parameter C_RX_META_STAGES = 0,
+      parameter C_RX_DATA_STAGES = 1
+      )
+    (
+     // Interface: Clocks
+     input                                    CLK,
+
+     // Interface: Resets
+     input                                    RST_IN,
+
+     // Interface: RC
+     input                                    M_AXIS_RC_TVALID,
+     input                                    M_AXIS_RC_TLAST,
+     input [C_PCI_DATA_WIDTH-1:0]             M_AXIS_RC_TDATA,
+     input [(C_PCI_DATA_WIDTH/32)-1:0]        M_AXIS_RC_TKEEP,
+     input [`SIG_RC_TUSER_W-1:0]              M_AXIS_RC_TUSER,
+     output                                   M_AXIS_RC_TREADY,
+    
+     // Interface: RXC Engine
+     output [C_PCI_DATA_WIDTH-1:0]            RXC_DATA,
+     output                                   RXC_DATA_VALID,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]       RXC_DATA_WORD_ENABLE,
+     output                                   RXC_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
+     output                                   RXC_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
+
+     output [`SIG_LBE_W-1:0]                  RXC_META_LDWBE,
+     output [`SIG_FBE_W-1:0]                  RXC_META_FDWBE,
+     output [`SIG_TAG_W-1:0]                  RXC_META_TAG,
+     output [`SIG_LOWADDR_W-1:0]              RXC_META_ADDR,
+     output [`SIG_TYPE_W-1:0]                 RXC_META_TYPE,
+     output [`SIG_LEN_W-1:0]                  RXC_META_LENGTH,
+     output [`SIG_BYTECNT_W-1:0]              RXC_META_BYTES_REMAINING,
+     output [`SIG_CPLID_W-1:0]                RXC_META_COMPLETER_ID,
+     output                                   RXC_META_EP
+     );
+
+    // Width of the Byte Enable Shift register
+    localparam C_RX_BE_W = (`SIG_FBE_W + `SIG_LBE_W);
+
+    localparam C_RX_INPUT_STAGES = 0;
+    localparam C_RX_OUTPUT_STAGES = 2; // Should always be at least one
+    localparam C_RX_COMPUTATION_STAGES = 1;
+    localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
+
+    // CYCLE = LOW ORDER BIT (INDEX) / C_PCI_DATA_WIDTH
+    localparam C_RX_METADW0_CYCLE = (`UPKT_RXC_METADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+    localparam C_RX_METADW1_CYCLE = (`UPKT_RXC_METADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+    localparam C_RX_METADW2_CYCLE = (`UPKT_RXC_METADW2_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+    localparam C_RX_PAYLOAD_CYCLE = (`UPKT_RXC_PAYLOAD_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+    localparam C_RX_BE_CYCLE = C_RX_INPUT_STAGES; // Available on the first cycle (as per the spec)
+    
+    localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXC_METADW0_I%C_PCI_DATA_WIDTH);
+    localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXC_METADW1_I%C_PCI_DATA_WIDTH);
+    localparam C_RX_METADW2_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXC_METADW2_I%C_PCI_DATA_WIDTH);
+    localparam C_RX_BE_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES;
+
+    // Mask width of the calculated SOF/EOF fields
+    localparam C_OFFSET_WIDTH = clog2(C_PCI_DATA_WIDTH/32);
+
+    wire                                      wMAxisRcSop;
+    wire                                      wMAxisRcTlast;
+    wire [C_RX_PIPELINE_DEPTH:0]              wRxSrSop;
+    wire [C_RX_PIPELINE_DEPTH:0]              wRxSrEop;
+    wire [C_RX_PIPELINE_DEPTH:0]              wRxSrDataValid;
+    wire [(C_RX_PIPELINE_DEPTH+1)*C_RX_BE_W-1:0] wRxSrBe;
+    wire [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] wRxSrData;
+
+    wire                                                wRxcDataValid;
+    wire                                                wRxcDataReady; // Pinned High
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]                    wRxcDataWordEnable;
+    wire                                                wRxcDataEndFlag;
+    wire [clog2(C_PCI_DATA_WIDTH/32)-1:0]               wRxcDataEndOffset;
+    wire                                                wRxcDataStartFlag;
+    wire [clog2(C_PCI_DATA_WIDTH/32)-1:0]               wRxcDataStartOffset;
+    wire [`SIG_BYTECNT_W-1:0]                           wRxcMetaBytesRemaining;
+    wire [`SIG_CPLID_W-1:0]                             wRxcMetaCompleterId;
+    wire [`UPKT_RXC_MAXHDR_W-1:0]                       wRxcHdr;
+    wire [`SIG_TYPE_W-1:0]                              wRxcType;
+    wire [`SIG_BARDECODE_W-1:0]                         wRxcBarDecoded;
+    
+    wire [`UPKT_RXC_MAXHDR_W-1:0]                       wHdr;
+    wire [`SIG_TYPE_W-1:0]                              wType;
+    
+    wire                                                wHasPayload;
+    wire                                                _wEndFlag;
+    wire                                                wEndFlag;
+    wire                                                wEndFlagLastCycle;
+    wire [clog2(C_PCI_DATA_WIDTH/32)-1:0]               wEndOffset;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]                    wEndMask;
+    wire                                                _wStartFlag;
+    wire                                                wStartFlag;
+    wire [1:0]                                          wStartFlags;
+    wire [clog2(C_PCI_DATA_WIDTH/32)-1:0]               wStartOffset;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]                    wStartMask;
+    wire [C_OFFSET_WIDTH-1:0]                           wOffsetMask;
+
+    reg                                                 rValid,_rValid;
+
+    assign wMAxisRcSop = M_AXIS_RC_TUSER[`UPKT_RC_TUSER_SOP_I];
+    assign wMAxisRcTlast = M_AXIS_RC_TLAST;
+
+    // We assert the end flag on the last cycle of a packet, however on single
+    // cycle packets we need to check that there wasn't an end flag last cycle
+    // (because wStartFlag will take priority when setting rValid) so we can
+    // deassert rValid if necessary.
+    assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES];
+    assign wEndFlagLastCycle = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES + 1];
+
+    /* verilator lint_off WIDTH */
+    assign wStartOffset = 3;
+    assign wEndOffset = wHdr[`UPKT_RXC_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXC_MAXHDR_W-32)/32);
+    /* verilator lint_on WIDTH */
+
+    // Output assignments. See the header file derived from the user
+    // guide for indices.
+    assign RXC_META_LENGTH = wRxcHdr[`UPKT_RXC_LENGTH_I+:`SIG_LEN_W];
+    //assign RXC_META_ATTR = wRxcHdr[`UPKT_RXC_ATTR_R];
+    //assign RXC_META_TC = wRxcHdr[`UPKT_RXC_TC_R];
+    assign RXC_META_TAG = wRxcHdr[`UPKT_RXC_TAG_R];
+    assign RXC_META_FDWBE = 0;// TODO: Remove (use addr)
+    assign RXC_META_LDWBE = 0;// TODO: Remove (use addr)
+    assign RXC_META_ADDR = wRxcHdr[(`UPKT_RXC_ADDRLOW_I) +: `SIG_LOWADDR_W];
+    assign RXC_DATA_START_FLAG = wRxcDataStartFlag;                      
+    assign RXC_DATA_START_OFFSET = {C_PCI_DATA_WIDTH > 64, 1'b1};
+    assign RXC_DATA_END_FLAG = wRxcDataEndFlag;                      
+    assign RXC_DATA_END_OFFSET = wRxcDataEndOffset;
+    assign RXC_DATA_VALID = wRxcDataValid;
+    assign RXC_DATA = wRxSrData[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
+    assign RXC_META_TYPE = wRxcType;
+    assign RXC_META_BYTES_REMAINING = wRxcHdr[`UPKT_RXC_BYTECNT_I +: `SIG_BYTECNT_W];
+    assign RXC_META_COMPLETER_ID = wRxcHdr[`UPKT_RXC_CPLID_R];
+    assign RXC_META_EP = wRxcHdr[`UPKT_RXC_EP_R];
+    
+    assign M_AXIS_RC_TREADY = 1'b1;
+
+    assign _wEndFlag = wRxSrEop[C_RX_INPUT_STAGES];
+    assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES+1];
+    assign _wStartFlag = wStartFlags != 0;
+    assign wType = (wHasPayload)? `TRLS_CPL_WD: `TRLS_CPL_ND;
+    
+    generate
+        if(C_PCI_DATA_WIDTH == 64) begin
+            assign wStartFlags[0] = 0;
+            assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1];
+            //assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wRxSrEop[C_RX_INPUT_STAGES]; // No Payload
+        end else if (C_PCI_DATA_WIDTH == 128) begin    
+            assign wStartFlags[1] = 0;
+            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
+        end else begin // 256
+            assign wStartFlags[1] = 0;
+            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
+        end // else: !if(C_PCI_DATA_WIDTH == 128)
+    endgenerate
+
+    always @(*) begin
+        _rValid = rValid;
+        if(_wStartFlag) begin
+	        _rValid = 1'b1;
+        end else if (wEndFlag) begin
+	        _rValid = 1'b0;
+        end
+    end
+    
+    always @(posedge CLK) begin
+        if(RST_IN) begin
+	        rValid <= 1'b0;
+        end else begin
+	        rValid <= _rValid;
+        end
+    end
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (1),
+          .C_VALUE                      (1'b0)
+          /*AUTOINSTPARAM*/)
+    start_flag_register
+        (
+         // Outputs
+         .RD_DATA                       (wStartFlag),
+         // Inputs
+         .WR_DATA                       (_wStartFlag),
+         .WR_EN                         (1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (32))
+    meta_DW2_register
+        (
+         // Outputs
+         .RD_DATA                       (wHdr[95:64]),
+         // Inputs
+         .WR_DATA                       (wRxSrData[C_RX_METADW2_INDEX +: 32]),
+         .WR_EN                         (wRxSrSop[C_RX_METADW2_CYCLE]),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (32+1))
+    meta_DW1_register
+        (
+         // Outputs
+         .RD_DATA                       ({wHdr[63:32],wHasPayload}),
+         // Inputs
+         .WR_DATA                       ({wRxSrData[C_RX_METADW1_INDEX +: 32],wRxSrData[C_RX_METADW1_INDEX +: `UPKT_LEN_W] != 0}),
+         .WR_EN                         (wRxSrSop[C_RX_METADW1_CYCLE]),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (32))
+    metadata_DW0_register
+        (
+         // Outputs
+         .RD_DATA                       (wHdr[31:0]),
+         // Inputs
+         .WR_DATA                       (wRxSrData[C_RX_METADW0_INDEX +: 32]),
+         .WR_EN                         (wRxSrSop[C_RX_METADW0_CYCLE]),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+
+    // Shift register for input data with output taps for each delayed
+    // cycle. 
+    shiftreg
+        #(
+          // Parameters
+          .C_DEPTH                     (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                     (C_PCI_DATA_WIDTH)
+          /*AUTOINSTPARAM*/)
+    data_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                       (wRxSrData),
+         // Inputs
+         .WR_DATA                       (M_AXIS_RC_TDATA),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    // Start Flag Shift Register. Data enables are derived from the
+    // taps on this shift register.
+    shiftreg 
+        #(
+          // Parameters
+          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                      (1'b1)
+          /*AUTOINSTPARAM*/)
+    sop_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                       (wRxSrSop),
+         // Inputs
+         .WR_DATA                       (wMAxisRcSop & M_AXIS_RC_TVALID),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    // End Flag Shift Register. 
+    shiftreg 
+        #(
+          // Parameters
+          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                      (1'b1)
+          /*AUTOINSTPARAM*/)
+    eop_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                       (wRxSrEop),
+         // Inputs
+         .WR_DATA                       (wMAxisRcTlast),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    // Data Valid Shift Register. Data enables are derived from the
+    // taps on this shift register.
+    shiftreg 
+        #(
+          // Parameters
+          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                      (1'b1)
+          /*AUTOINSTPARAM*/)
+    valid_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                       (wRxSrDataValid),
+         // Inputs
+         .WR_DATA                       (M_AXIS_RC_TVALID),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
+
+    offset_to_mask
+        #(// Parameters
+          .C_MASK_SWAP                  (0),
+          .C_MASK_WIDTH                 (C_PCI_DATA_WIDTH/32)
+          /*AUTOINSTPARAM*/)
+    o2m_ef
+        (
+         // Outputs
+         .MASK                          (wEndMask),
+         // Inputs
+         .OFFSET_ENABLE                 (wEndFlag),
+         .OFFSET                        (wEndOffset)
+         /*AUTOINST*/);
+
+    generate
+        if(C_RX_OUTPUT_STAGES == 0) begin
+            assign RXC_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | ~wHasPayload}};
+        end else begin
+            register
+                #(
+                  // Parameters
+                  .C_WIDTH              (C_PCI_DATA_WIDTH/32),
+                  .C_VALUE              (0)
+                  /*AUTOINSTPARAM*/)
+            dw_enable
+                (// Outputs
+                 .RD_DATA               (wRxcDataWordEnable),
+                 // Inputs
+                 .RST_IN                (~rValid | ~wHasPayload),
+                 .WR_DATA               (wEndMask & wStartMask),
+                 .WR_EN                 (1),
+                 /*AUTOINST*/
+                 .CLK                   (CLK));
+
+            pipeline
+                #(
+                  // Parameters
+                  .C_DEPTH                      (C_RX_OUTPUT_STAGES-1),
+                  .C_WIDTH                      (C_PCI_DATA_WIDTH/32),
+                  .C_USE_MEMORY                 (0)
+                  /*AUTOINSTPARAM*/)
+            dw_pipeline
+                (
+                 // Outputs
+                 .WR_DATA_READY                 (), // Pinned to 1
+                 .RD_DATA                       (RXC_DATA_WORD_ENABLE),
+                 .RD_DATA_VALID                 (),
+                 // Inputs
+                 .WR_DATA                       (wRxcDataWordEnable),
+                 .WR_DATA_VALID                 (1),
+                 .RD_DATA_READY                 (1'b1),
+                 /*AUTOINST*/
+                 // Inputs
+                 .CLK                           (CLK),
+                 .RST_IN                        (RST_IN));
+        end
+    endgenerate
+
+    // Shift register for input data with output taps for each delayed
+    // cycle. 
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_RX_OUTPUT_STAGES),
+          .C_WIDTH                      (`UPKT_RXC_MAXHDR_W + 2*(1 + clog2(C_PCI_DATA_WIDTH/32))+`SIG_TYPE_W),
+          .C_USE_MEMORY                 (0)
+          /*AUTOINSTPARAM*/)
+    output_pipeline
+        (
+         // Outputs
+         .WR_DATA_READY                 (), // Pinned to 1
+         .RD_DATA                       ({wRxcHdr,wRxcDataStartFlag,wRxcDataStartOffset,wRxcDataEndFlag,wRxcDataEndOffset,wRxcType}),
+         .RD_DATA_VALID                 (wRxcDataValid),
+         // Inputs
+         .WR_DATA                       ({wHdr,wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0],wType}),
+         .WR_DATA_VALID                 (rValid),
+         .RD_DATA_READY                 (1'b1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../common/")
+// End:
diff --git a/fpga/riffa_hdl/rxr_engine_classic.v b/fpga/riffa_hdl/rxr_engine_classic.v
new file mode 100644
index 0000000..1355811
--- /dev/null
+++ b/fpga/riffa_hdl/rxr_engine_classic.v
@@ -0,0 +1,980 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            rxr_engine_classic.v
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The RXR Engine (Classic) takes a single stream of TLP
+// packets and provides the request packets on the RXR Interface.
+// This Engine is capable of operating at "line rate".
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "trellis.vh"
+`include "tlp.vh"
+module rxr_engine_classic
+    #(parameter C_VENDOR = "ALTERA",
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_RX_PIPELINE_DEPTH=10
+      )
+    (
+     // Interface: Clocks
+     input                                                CLK,
+
+     // Interface: Resets
+     input                                                RST_IN,
+
+     // Interface: RX Classic
+     input [C_PCI_DATA_WIDTH-1:0]                         RX_TLP,
+     input                                                RX_TLP_VALID,
+     input                                                RX_TLP_START_FLAG,
+     input [`SIG_OFFSET_W-1:0]                            RX_TLP_START_OFFSET,
+     input                                                RX_TLP_END_FLAG,
+     input [`SIG_OFFSET_W-1:0]                            RX_TLP_END_OFFSET,
+     input [`SIG_BARDECODE_W-1:0]                         RX_TLP_BAR_DECODE,
+
+     // Interface: RXR
+     output [C_PCI_DATA_WIDTH-1:0]                        RXR_DATA,
+     output                                               RXR_DATA_VALID,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]                   RXR_DATA_WORD_ENABLE,
+     output                                               RXR_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXR_DATA_START_OFFSET,
+     output                                               RXR_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXR_DATA_END_OFFSET,
+    
+     output [`SIG_FBE_W-1:0]                              RXR_META_FDWBE,
+     output [`SIG_LBE_W-1:0]                              RXR_META_LDWBE,
+     output [`SIG_TC_W-1:0]                               RXR_META_TC,
+     output [`SIG_ATTR_W-1:0]                             RXR_META_ATTR,
+     output [`SIG_TAG_W-1:0]                              RXR_META_TAG,
+     output [`SIG_TYPE_W-1:0]                             RXR_META_TYPE,
+     output [`SIG_ADDR_W-1:0]                             RXR_META_ADDR,
+     output [`SIG_BARDECODE_W-1:0]                        RXR_META_BAR_DECODED,
+     output [`SIG_REQID_W-1:0]                            RXR_META_REQUESTER_ID,
+     output [`SIG_LEN_W-1:0]                              RXR_META_LENGTH,
+     output                                               RXR_META_EP,
+
+     // Interface: RX Shift Register
+     input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
+     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_EOP,
+     input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    RX_SR_END_OFFSET,
+     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_SOP,
+     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_VALID
+     );
+
+    /*AUTOWIRE*/
+    ///*AUTOOUTPUT*/
+    // End of automatics
+    localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
+
+    localparam C_RX_INPUT_STAGES = 1;
+    localparam C_RX_OUTPUT_STAGES = 1; // Must always be at least one
+    localparam C_RX_COMPUTATION_STAGES = 1;
+    localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
+    
+    // Cycle index in the SOP register when enable is raised
+    // Computation can begin when the last DW of the header is recieved. 
+    localparam C_RX_COMPUTATION_CYCLE = C_RX_COMPUTATION_STAGES + (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+    // The computation cycle must be at least one cycle before the address is enabled
+    localparam C_RX_DATA_CYCLE = C_RX_COMPUTATION_CYCLE;
+
+    localparam C_RX_ADDRDW0_CYCLE = (`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+    localparam C_RX_ADDRDW1_CYCLE = (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+    localparam C_RX_METADW0_CYCLE = (`TLP_REQMETADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+    localparam C_RX_METADW1_CYCLE = (`TLP_REQMETADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+
+    localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH);
+    localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH);
+    localparam C_RX_ADDRDW1_RESET_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + 
+                                          C_PCI_DATA_WIDTH*(C_RX_ADDRDW1_CYCLE - C_RX_METADW0_CYCLE) +
+                                          `TLP_4DWHBIT_I;
+    
+    localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW0_I%C_PCI_DATA_WIDTH);
+    localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW1_I%C_PCI_DATA_WIDTH);
+
+    localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
+    localparam C_MAX_ABLANK_WIDTH = 32;
+    localparam C_MAX_START_OFFSET = (`TLP_MAXHDR_W + C_MAX_ABLANK_WIDTH)/32;
+    localparam C_STD_START_DELAY = (64/C_PCI_DATA_WIDTH);
+
+    wire [63:0]                                           wAddrFmt;
+    wire [63:0]                                           wMetadata;
+    wire [`TLP_TYPE_W-1:0]                                wType;
+    wire [`TLP_LEN_W-1:0]                                 wLength;
+    wire                                                  wAddrDW0Bit2;
+    wire                                                  wAddrDW1Bit2;
+    wire                                                  wAddrHiReset;
+    wire [31:0]                                           wAddrMux[(`TLP_REQADDR_W / 32)-1:0];
+    wire [63:0]                                           wAddr;
+    wire                                                  w4DWH;
+    wire                                                  wHasPayload;
+    wire [2:0]                                            wHdrLength;
+    wire [2:0]                                            wHdrLengthM1;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wEndMask;
+    wire                                                  _wEndFlag;
+    wire                                                  wEndFlag;
+    wire [C_OFFSET_WIDTH-1:0]                             wEndOffset;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wStartMask;
+    wire [3:0]                                            wStartFlags;
+    wire                                                  wStartFlag;
+    wire                                                  _wStartFlag;
+    wire [clog2s(C_MAX_START_OFFSET)-1:0]                 wStartOffset;
+    wire                                                  wInsertBlank;
+    wire                                                  wRotateAddressField;
+
+
+    wire [C_PCI_DATA_WIDTH-1:0]                           wRxrData;
+
+    wire [`SIG_ADDR_W-1:0]                                wRxrMetaAddr;
+    wire [63:0]                                           wRxrMetadata;
+    wire                                                  wRxrDataValid;
+    wire                                                  wRxrDataReady; // Pinned High
+    wire                                                  wRxrDataEndFlag;
+    wire [C_OFFSET_WIDTH-1:0]                             wRxrDataEndOffset;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wRxrDataWordEnable;
+    wire                                                  wRxrDataStartFlag;
+    wire [C_OFFSET_WIDTH-1:0]                             wRxrDataStartOffset;
+
+    wire [C_RX_PIPELINE_DEPTH:0]                          wRxSrSop;
+
+    reg                                                   rValid,_rValid;
+
+    
+    assign wAddrHiReset = ~RX_SR_DATA[C_RX_ADDRDW1_RESET_INDEX];
+
+    // Select Addr[31:0] from one of the two possible locations in the TLP based
+    // on header length (1 bit)
+    assign wRotateAddressField = w4DWH;
+    assign wAddrFmt = {wAddrMux[~wRotateAddressField],wAddrMux[wRotateAddressField]};
+    assign wAddrMux[0] = wAddr[31:0];    
+    assign wAddrMux[1] = wAddr[63:32];    
+    // Calculate the header length (start offset), and header length minus 1 (end offset)
+    assign wHdrLength = {w4DWH,~w4DWH,~w4DWH};
+    assign wHdrLengthM1 = {1'b0,1'b1,w4DWH};
+    // Determine if the TLP has an inserted blank before the payload
+    assign wInsertBlank = ((w4DWH & wAddrDW1Bit2) | (~w4DWH & ~wAddrDW0Bit2)) & (C_VENDOR == "ALTERA");
+    
+
+    assign wStartOffset = (wHdrLength + {2'd0,wInsertBlank}); // Start offset in dwords
+    assign wEndOffset = wHdrLengthM1 + wInsertBlank + wLength;//RX_SR_END_OFFSET[(C_TOTAL_STAGES-1)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
+
+    // Inputs
+    // Technically an input, but the trellis protocol specifies it must be held high at all times
+    assign wRxrDataReady = 1;
+    // Outputs
+    assign RXR_DATA = RX_SR_DATA[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
+    assign RXR_DATA_VALID = wRxrDataValid;
+    assign RXR_DATA_END_FLAG = wRxrDataEndFlag;
+    assign RXR_DATA_END_OFFSET = wRxrDataEndOffset;
+    assign RXR_DATA_START_FLAG = wRxrDataStartFlag;
+    assign RXR_DATA_START_OFFSET = wRxrDataStartOffset;
+
+    assign RXR_META_BAR_DECODED = 0;
+    assign RXR_META_LENGTH = wRxrMetadata[`TLP_LEN_R];
+    assign RXR_META_TC = wRxrMetadata[`TLP_TC_R];
+    assign RXR_META_ATTR = {wRxrMetadata[`TLP_ATTR1_R], wRxrMetadata[`TLP_ATTR0_R]};
+    assign RXR_META_TYPE = tlp_to_trellis_type({wRxrMetadata[`TLP_FMT_R],wRxrMetadata[`TLP_TYPE_R]});
+    assign RXR_META_ADDR = wRxrMetaAddr;
+    assign RXR_META_REQUESTER_ID = wRxrMetadata[`TLP_REQREQID_R];
+    assign RXR_META_TAG = wRxrMetadata[`TLP_REQTAG_R];
+    assign RXR_META_FDWBE = wRxrMetadata[`TLP_REQFBE_R];
+    assign RXR_META_LDWBE = wRxrMetadata[`TLP_REQLBE_R];
+    assign RXR_META_EP = wRxrMetadata[`TLP_EP_R];
+    
+    assign _wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES];
+    assign wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES+1];
+    assign _wStartFlag = wStartFlags != 0;
+    generate
+        if(C_PCI_DATA_WIDTH == 32) begin
+            assign wStartFlags[3] = 0;
+            assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 3] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
+            assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
+            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~wMetadata[`TLP_PAYBIT_I]; // No Payload
+        end else if(C_PCI_DATA_WIDTH == 64) begin
+            assign wStartFlags[3] = 0;
+            assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
+            if(C_VENDOR == "ALTERA") begin
+                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_ADDRDW0_INDEX + 2]; // 3DWH, No Blank
+            end else begin
+                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
+            end
+            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~wMetadata[`TLP_PAYBIT_I]; // No Payload
+        end else if (C_PCI_DATA_WIDTH == 128) begin    
+            assign wStartFlags[3] = 0;
+            assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Is this correct?
+            if(C_VENDOR == "ALTERA") begin
+                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_ADDRDW0_INDEX + 2]; // 3DWH, No Blank
+            end else begin
+                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I];
+            end
+            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I]; // No Payload
+        end else begin // 256
+            assign wStartFlags[3] = 0;
+            assign wStartFlags[2] = 0;
+            assign wStartFlags[1] = 0;
+            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
+        end // else: !if(C_PCI_DATA_WIDTH == 128)
+    endgenerate
+
+    
+    always @(*) begin
+        _rValid = rValid;
+        if(_wStartFlag) begin
+	        _rValid = 1'b1;
+        end else if (wEndFlag) begin
+	        _rValid = 1'b0;
+        end
+    end
+    
+    always @(posedge CLK) begin
+        if(RST_IN) begin
+	        rValid <= 1'b0;
+        end else begin
+	        rValid <= _rValid;
+        end
+    end
+    assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
+
+    offset_to_mask
+        #(// Parameters
+          .C_MASK_SWAP                  (0),
+          .C_MASK_WIDTH                 (C_PCI_DATA_WIDTH/32)
+          /*AUTOINSTPARAM*/)
+    o2m_ef
+        (
+         // Outputs
+         .MASK                          (wEndMask),
+         // Inputs
+         .OFFSET_ENABLE                 (wEndFlag),
+         .OFFSET                        (wEndOffset[C_OFFSET_WIDTH-1:0])
+         /*AUTOINST*/);
+    generate
+        if(C_RX_OUTPUT_STAGES == 0) begin
+            assign RXR_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | ~wMetadata[`TLP_PAYBIT_I]}};
+        end else begin
+            register
+                #(
+                  // Parameters
+                  .C_WIDTH              (C_PCI_DATA_WIDTH/32),
+                  .C_VALUE              (0)
+                  /*AUTOINSTPARAM*/)
+            dw_enable
+                (// Outputs
+                 .RD_DATA               (wRxrDataWordEnable),
+                 // Inputs
+                 .RST_IN                (~rValid | ~wMetadata[`TLP_PAYBIT_I]),
+                 .WR_DATA               (wEndMask & wStartMask),
+                 .WR_EN                 (1),
+                 /*AUTOINST*/
+                 .CLK                   (CLK));
+
+            pipeline
+                #(
+                  // Parameters
+                  .C_DEPTH                      (C_RX_OUTPUT_STAGES-1),
+                  .C_WIDTH                      (C_PCI_DATA_WIDTH/32),
+                  .C_USE_MEMORY                 (0)
+                  /*AUTOINSTPARAM*/)
+            dw_pipeline
+                (
+                 // Outputs
+                 .WR_DATA_READY                 (), // Pinned to 1
+                 .RD_DATA                       (RXR_DATA_WORD_ENABLE),
+                 .RD_DATA_VALID                 (),
+                 // Inputs
+                 .WR_DATA                       (wRxrDataWordEnable),
+                 .WR_DATA_VALID                 (1),
+                 .RD_DATA_READY                 (1'b1),
+                 /*AUTOINST*/
+                 // Inputs
+                 .CLK                           (CLK),
+                 .RST_IN                        (RST_IN));
+        end
+    endgenerate
+    
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (32),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    metadata_DW0_register
+        (
+         // Outputs
+         .RD_DATA                       (wMetadata[31:0]),
+         // Inputs
+         .WR_DATA                       (RX_SR_DATA[C_RX_METADW0_INDEX +: 32]),
+         .WR_EN                         (wRxSrSop[C_RX_METADW0_CYCLE]),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (32),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    meta_DW1_register
+        (
+         // Outputs
+         .RD_DATA                       (wMetadata[63:32]),
+         // Inputs
+         .WR_DATA                       (RX_SR_DATA[C_RX_METADW1_INDEX +: 32]),
+         .WR_EN                         (wRxSrSop[C_RX_METADW1_CYCLE]),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (32),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    addr_DW0_register
+        (
+         // Outputs
+         .RD_DATA                       (wAddr[31:0]),
+         // Inputs
+         .WR_DATA                       (RX_SR_DATA[C_RX_ADDRDW0_INDEX +: 32]),
+         .WR_EN                         (wRxSrSop[C_RX_ADDRDW0_CYCLE]),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (32),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    addr_DW1_register
+        (
+         // Outputs
+         .RD_DATA                       (wAddr[63:32]),
+         // Inputs
+         .WR_DATA                       (RX_SR_DATA[C_RX_ADDRDW1_INDEX +: 32]),
+         .WR_EN                         (wRxSrSop[C_RX_ADDRDW1_CYCLE]),
+         .RST_IN                        (RST_IN | (wAddrHiReset & wRxSrSop[C_RX_ADDRDW1_CYCLE])),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (2),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    metadata_4DWH_register
+        (
+         // Outputs
+         .RD_DATA                       ({wHasPayload,w4DWH}),
+         // Inputs
+         .WR_DATA                       (RX_SR_DATA[`TLP_FMT_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES +: 2]),
+         .WR_EN                         (wRxSrSop[`TLP_4DWHBIT_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (`TLP_TYPE_W),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    metadata_type_register
+        (
+         // Outputs
+         .RD_DATA                       (wType),
+         // Inputs
+         .WR_DATA                       (RX_SR_DATA[(`TLP_TYPE_I/* + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES*/) +: `TLP_TYPE_W]),
+         .WR_EN                         (wRxSrSop[`TLP_TYPE_I/C_PCI_DATA_WIDTH/* + C_RX_INPUT_STAGES*/]),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (`TLP_LEN_W),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    metadata_length_register
+        (
+         // Outputs
+         .RD_DATA                       (wLength),
+         // Inputs
+         .WR_DATA                       (RX_SR_DATA[(`TLP_LEN_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_LEN_W]),
+         .WR_EN                         (wRxSrSop[`TLP_LEN_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (1),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    addr_DW0_bit_2_register
+        (
+         // Outputs
+         .RD_DATA                       (wAddrDW0Bit2),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .WR_DATA                       (RX_SR_DATA[(`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH) + 2 + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES]),
+         .WR_EN                         (wRxSrSop[(`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES]));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (1),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    addr_DW1_bit_2_register
+        (
+         // Outputs
+         .RD_DATA                       (wAddrDW1Bit2),
+         // Inputs
+         .WR_DATA                       (RX_SR_DATA[(`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH) + 2 + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES]),
+         .WR_EN                         (wRxSrSop[(`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES]),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (1),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    start_flag_register
+        (
+         // Outputs
+         .RD_DATA                       (wStartFlag),
+         // Inputs
+         .WR_DATA                       (_wStartFlag),
+         .WR_EN                         (1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+    
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_RX_OUTPUT_STAGES),
+          .C_WIDTH                      (`TLP_MAXHDR_W + 2*(1 + C_OFFSET_WIDTH)),
+          .C_USE_MEMORY                 (0)
+          /*AUTOINSTPARAM*/)
+    output_pipeline
+        (
+         // Outputs
+         .WR_DATA_READY                 (), // Pinned to 1
+         .RD_DATA                       ({wRxrMetadata,wRxrMetaAddr,wRxrDataStartFlag,wRxrDataStartOffset,wRxrDataEndFlag,wRxrDataEndOffset}),
+         .RD_DATA_VALID                 (wRxrDataValid),
+         // Inputs
+         .WR_DATA                       ({wMetadata, wAddrFmt, wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0]}),
+         .WR_DATA_VALID                 (rValid),
+         .RD_DATA_READY                 (1'b1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    // Start Flag Shift Register. Data enables are derived from the
+    // taps on this shift register.
+    shiftreg 
+        #(
+          // Parameters
+          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                      (1'b1)
+          /*AUTOINSTPARAM*/)
+    sop_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                       (wRxSrSop),
+         // Inputs
+         .WR_DATA                       (RX_TLP_START_FLAG & RX_TLP_VALID & (RX_SR_DATA[`TLP_TYPE_R] == `TLP_TYPE_REQ)),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+    
+endmodule
+module rxr_engine_128
+    #(parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_RX_PIPELINE_DEPTH=10
+      )
+    (
+     // Interface: Clocks
+     input                                                CLK,
+
+     // Interface: Resets
+     input                                                RST_IN,
+
+     // Interface: RX Classic
+     input [C_PCI_DATA_WIDTH-1:0]                         RX_TLP,
+     input                                                RX_TLP_VALID,
+     input                                                RX_TLP_START_FLAG,
+     input [`SIG_OFFSET_W-1:0]                            RX_TLP_START_OFFSET,
+     input                                                RX_TLP_END_FLAG,
+     input [`SIG_OFFSET_W-1:0]                            RX_TLP_END_OFFSET,
+     input [`SIG_BARDECODE_W-1:0]                         RX_TLP_BAR_DECODE,
+
+     // Interface: RXR
+     output [C_PCI_DATA_WIDTH-1:0]                        RXR_DATA,
+     output                                               RXR_DATA_VALID,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]                   RXR_DATA_WORD_ENABLE,
+     output                                               RXR_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXR_DATA_START_OFFSET,
+     output                                               RXR_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXR_DATA_END_OFFSET,
+    
+     output [`SIG_FBE_W-1:0]                              RXR_META_FDWBE,
+     output [`SIG_LBE_W-1:0]                              RXR_META_LDWBE,
+     output [`SIG_TC_W-1:0]                               RXR_META_TC,
+     output [`SIG_ATTR_W-1:0]                             RXR_META_ATTR,
+     output [`SIG_TAG_W-1:0]                              RXR_META_TAG,
+     output [`SIG_TYPE_W-1:0]                             RXR_META_TYPE,
+     output [`SIG_ADDR_W-1:0]                             RXR_META_ADDR,
+     output [`SIG_BARDECODE_W-1:0]                        RXR_META_BAR_DECODED,
+     output [`SIG_REQID_W-1:0]                            RXR_META_REQUESTER_ID,
+     output [`SIG_LEN_W-1:0]                              RXR_META_LENGTH,
+     output                                               RXR_META_EP,
+
+     // Interface: RX Shift Register
+     input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
+     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_EOP,
+     input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    RX_SR_END_OFFSET,
+     input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    RX_SR_START_OFFSET,
+     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_SOP,
+     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_VALID
+     );
+
+    /*AUTOWIRE*/
+    // Beginning of automatic wires (for undeclared instantiated-module outputs)
+    // End of automatics
+    ///*AUTOOUTPUT*/
+    // End of automatics
+    localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
+
+    localparam C_RX_INPUT_STAGES = 1;
+    localparam C_RX_OUTPUT_STAGES = 1;
+    localparam C_RX_COMPUTATION_STAGES = 1;
+    localparam C_RX_HDR_STAGES = 1; // Specific to the Xilinx 128-bit RXR Engine
+    localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES + C_RX_HDR_STAGES;
+    
+    localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
+    localparam C_STRADDLE_W = 64;
+    localparam C_HDR_NOSTRADDLE_I = C_RX_INPUT_STAGES * C_PCI_DATA_WIDTH;
+    localparam C_OUTPUT_STAGE_WIDTH = (C_PCI_DATA_WIDTH/32) + 2 + clog2s(C_PCI_DATA_WIDTH/32) + 1 + `SIG_FBE_W + `SIG_LBE_W + `SIG_TC_W + `SIG_ATTR_W + `SIG_TAG_W + `SIG_TYPE_W + `SIG_ADDR_W + `SIG_BARDECODE_W + `SIG_REQID_W + `SIG_LEN_W;
+
+    // Header Reg Inputs
+    wire [`SIG_OFFSET_W-1:0]                              __wRxrStartOffset; 
+    wire [`SIG_OFFSET_W-1:0]                              __wRxrStraddledStartOffset; 
+    wire [`TLP_MAXHDR_W-1:0]                              __wRxrHdr;
+    wire [`TLP_MAXHDR_W-1:0]                              __wRxrHdrStraddled;
+    wire [`TLP_MAXHDR_W-1:0]                              __wRxrHdrNotStraddled;
+    wire                                                  __wRxrHdrValid;
+    wire [`TLP_TYPE_W-1:0]                                __wRxrHdrType;
+    wire [`TLP_TYPE_W-1:0]                                __wRxrHdrTypeStraddled;
+
+    wire                                                  __wRxrHdrSOP; // Asserted on non-straddle SOP
+    wire                                                  __wRxrHdrSOPStraddle;
+    wire                                                  __wRxrHdr4DWHWDataSF;
+
+    // Header Reg Outputs
+    wire                                                  _wRxrHdrValid;
+    wire [`TLP_MAXHDR_W-1:0]                              _wRxrHdr;
+    wire [`SIG_ADDR_W-1:0]                                _wRxrAddrUnformatted;
+    wire [`SIG_ADDR_W-1:0]                                _wRxrAddr;
+    wire [63:0]                                           _wRxrTlpMetadata;
+    wire [`TLP_TYPE_W-1:0]                                _wRxrType;
+    wire [`TLP_LEN_W-1:0]                                 _wRxrLength;
+    wire [2:0]                                            _wRxrHdrHdrLen;// TODO: 
+    wire [`SIG_OFFSET_W-1:0]                              _wRxrHdrStartOffset;// TODO: 
+
+    wire                                                  _wRxrHdrDelayedSOP;
+    wire                                                  _wRxrHdrSOPStraddle;
+    wire                                                  _wRxrHdrSOP;
+
+    wire                                                  _wRxrHdrSF;
+    wire                                                  _wRxrHdrEF;
+    wire                                                  _wRxrHdrSCP; // Single Cycle Packet
+    wire                                                  _wRxrHdrMCP; // Multi Cycle Packet
+    wire                                                  _wRxrHdrRegSF;
+    wire                                                  _wRxrHdrRegValid;
+    wire                                                  _wRxrHdr4DWHSF;
+    wire                                                  _wRxrHdr4DWHNoDataSF;
+    wire                                                  _wRxrHdr4DWHWDataSF;
+    wire                                                  _wRxrHdr3DWHSF;
+    wire [2:0]                                            _wRxrHdrDataSoff;
+    wire [1:0]                                            _wRxrHdrDataEoff;
+    wire [3:0]                                            _wRxrHdrStartMask;
+    wire [3:0]                                            _wRxrHdrEndMask;
+    
+    // Header Reg Outputs
+    wire                                                  wRxrHdrSF;
+    wire                                                  wRxrHdrEF;
+    wire                                                  wRxrHdrValid;
+    wire [`TLP_MAXHDR_W-1:0]                              wRxrHdr;
+    wire [63:0]                                           wRxrMetadata;
+    wire [`TLP_TYPE_W-1:0]                                wRxrType;
+    wire [`TLP_LEN_W-1:0]                                 wRxrLength;
+    wire [2:0]                                            wRxrHdrLength; // TODO: 
+    wire [`SIG_OFFSET_W-1:0]                              wRxrHdrStartOffset; // TODO: 
+    wire                                                  wRxrHdrSCP; // Single Cycle Packet
+    wire                                                  wRxrHdrMCP; // Multi Cycle Packet
+    wire [1:0]                                            wRxrHdrDataSoff;
+    wire [3:0]                                            wRxrHdrStartMask;
+    wire [3:0]                                            wRxrHdrEndMask;
+
+    // Output Register Inputs
+    wire [C_PCI_DATA_WIDTH-1:0]                           wRxrData;
+    wire                                                  wRxrDataValid;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wRxrDataWordEnable;
+    wire                                                  wRxrDataStartFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]                wRxrDataStartOffset;
+    wire                                                  wRxrDataEndFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]                wRxrDataEndOffset;
+    wire [`SIG_FBE_W-1:0]                                 wRxrMetaFdwbe;
+    wire [`SIG_LBE_W-1:0]                                 wRxrMetaLdwbe;
+    wire [`SIG_TC_W-1:0]                                  wRxrMetaTC;
+    wire [`SIG_ATTR_W-1:0]                                wRxrMetaAttr;
+    wire [`SIG_TAG_W-1:0]                                 wRxrMetaTag;
+    wire [`SIG_TYPE_W-1:0]                                wRxrMetaType;
+    wire [`SIG_ADDR_W-1:0]                                wRxrMetaAddr;
+    wire [`SIG_BARDECODE_W-1:0]                           wRxrMetaBarDecoded;
+    wire [`SIG_REQID_W-1:0]                               wRxrMetaRequesterId;
+    wire [`SIG_LEN_W-1:0]                                 wRxrMetaLength;
+    wire                                                  wRxrMetaEP;
+
+    reg                                                   rStraddledSOP;
+    reg                                                   rStraddledSOPSplit;
+    
+    // ----- Header Register -----
+    assign __wRxrHdrSOP = RX_SR_SOP[C_RX_INPUT_STAGES] & ~__wRxrStartOffset[1];
+    assign __wRxrHdrSOPStraddle = RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxrStraddledStartOffset[1];
+    
+    assign __wRxrHdrNotStraddled = RX_SR_DATA[C_HDR_NOSTRADDLE_I +: C_PCI_DATA_WIDTH];
+    assign __wRxrHdrStraddled = {RX_SR_DATA[C_RX_INPUT_STAGES*C_PCI_DATA_WIDTH +: C_STRADDLE_W],
+                                 RX_SR_DATA[(C_RX_INPUT_STAGES+1)*C_PCI_DATA_WIDTH + C_STRADDLE_W +: C_STRADDLE_W ]};
+    assign __wRxrStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*C_RX_INPUT_STAGES +: `SIG_OFFSET_W];
+    assign __wRxrStraddledStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*(C_RX_INPUT_STAGES) +: `SIG_OFFSET_W];
+    assign __wRxrHdrValid = __wRxrHdrSOP | ((rStraddledSOP | rStraddledSOPSplit) & RX_SR_VALID[C_RX_INPUT_STAGES]);
+    assign __wRxrHdr4DWHWDataSF = (_wRxrHdr[`TLP_4DWHBIT_I] & _wRxrHdr[`TLP_PAYBIT_I] & RX_SR_VALID[C_RX_INPUT_STAGES] & _wRxrHdrDelayedSOP);
+                     
+
+    assign _wRxrHdrHdrLen = {_wRxrHdr[`TLP_4DWHBIT_I],~_wRxrHdr[`TLP_4DWHBIT_I],~_wRxrHdr[`TLP_4DWHBIT_I]};
+    assign _wRxrHdrDataSoff = {1'b0,_wRxrHdrSOPStraddle,1'b0} + _wRxrHdrHdrLen;
+    assign _wRxrHdrRegSF = RX_SR_SOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
+    assign _wRxrHdrRegValid = RX_SR_VALID[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
+
+    assign _wRxrHdr4DWHNoDataSF = _wRxrHdr[`TLP_4DWHBIT_I] & ~_wRxrHdr[`TLP_PAYBIT_I] & _wRxrHdrSOP;
+    assign _wRxrHdr4DWHSF = _wRxrHdr4DWHNoDataSF | (_wRxrHdr4DWHWDataSF & _wRxrHdrRegValid);
+    assign _wRxrHdr3DWHSF = ~_wRxrHdr[`TLP_4DWHBIT_I] & _wRxrHdrSOP;
+    
+    assign _wRxrHdrSF = (_wRxrHdr3DWHSF | _wRxrHdr4DWHSF | _wRxrHdrSOPStraddle);
+    assign _wRxrHdrEF = RX_SR_EOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
+
+    assign _wRxrHdrDataEoff = RX_SR_END_OFFSET[(C_RX_INPUT_STAGES+C_RX_HDR_STAGES)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
+    assign _wRxrHdrSCP = _wRxrHdrSF & _wRxrHdrEF & (_wRxrHdr[`TLP_TYPE_R] == `TLP_TYPE_REQ);
+    assign _wRxrHdrMCP = (_wRxrHdrSF & ~_wRxrHdrEF & (_wRxrHdr[`TLP_TYPE_R] == `TLP_TYPE_REQ)) | 
+                         (wRxrHdrMCP & ~wRxrHdrEF);
+    
+    assign _wRxrHdrStartMask = 4'hf << (_wRxrHdrSF ? _wRxrHdrDataSoff[1:0] : 0);
+
+    assign wRxrDataWordEnable = wRxrHdrEndMask & wRxrHdrStartMask & {4{wRxrDataValid}};
+    assign wRxrDataValid = wRxrHdrSCP | wRxrHdrMCP;
+    assign wRxrDataStartFlag = wRxrHdrSF;
+    assign wRxrDataEndFlag = wRxrHdrEF;
+    assign wRxrDataStartOffset = wRxrHdrDataSoff;
+    assign wRxrMetaFdwbe = wRxrHdr[`TLP_REQFBE_R];
+    assign wRxrMetaLdwbe = wRxrHdr[`TLP_REQLBE_R];
+    assign wRxrMetaTC = wRxrHdr[`TLP_TC_R];
+    assign wRxrMetaAttr = {wRxrHdr[`TLP_ATTR1_R], wRxrHdr[`TLP_ATTR0_R]};
+    assign wRxrMetaTag = wRxrHdr[`TLP_REQTAG_R];
+    assign wRxrMetaAddr = wRxrHdr[`TLP_REQADDRDW0_I +: `TLP_REQADDR_W];/* TODO: REQADDR_R*/
+    assign wRxrMetaRequesterId = wRxrHdr[`TLP_REQREQID_R];
+    assign wRxrMetaLength = wRxrHdr[`TLP_LEN_R];
+    assign wRxrMetaEP = wRxrHdr[`TLP_EP_R];
+    assign wRxrMetaType = tlp_to_trellis_type({wRxrHdr[`TLP_FMT_R],wRxrHdr[`TLP_TYPE_R]});
+
+    assign RXR_DATA = RX_SR_DATA[C_PCI_DATA_WIDTH*C_TOTAL_STAGES +: C_PCI_DATA_WIDTH];
+    assign RXR_DATA_END_OFFSET = RX_SR_END_OFFSET[`SIG_OFFSET_W*(C_TOTAL_STAGES) +: C_OFFSET_WIDTH];
+
+    always @(posedge CLK) begin
+        rStraddledSOP <= __wRxrHdrSOPStraddle;
+        // Set Straddled SOP Split when there is a straddled packet where the
+        // header is not contiguous. (Not sure if this is ever possible, but
+        // better safe than sorry assert Straddled SOP Split. See Virtex 6 PCIe
+        // errata.
+        if(__wRxrHdrSOP | RST_IN) begin
+            rStraddledSOPSplit <=0;
+        end else begin
+            rStraddledSOPSplit <= (__wRxrHdrSOPStraddle | rStraddledSOPSplit) & ~RX_SR_VALID[C_RX_INPUT_STAGES];
+        end
+    end
+    
+    mux
+        #(
+          // Parameters
+          .C_NUM_INPUTS                 (2),
+          .C_CLOG_NUM_INPUTS            (1),
+          .C_WIDTH                      (`TLP_MAXHDR_W),
+          .C_MUX_TYPE                   ("SELECT")
+          /*AUTOINSTPARAM*/)
+    hdr_mux
+        (
+         // Outputs
+         .MUX_OUTPUT                    (__wRxrHdr[`TLP_MAXHDR_W-1:0]),
+         // Inputs
+         .MUX_INPUTS                    ({__wRxrHdrStraddled[`TLP_MAXHDR_W-1:0],
+                                          __wRxrHdrNotStraddled[`TLP_MAXHDR_W-1:0]}),
+         .MUX_SELECT                    (rStraddledSOP | rStraddledSOPSplit)
+         /*AUTOINST*/);
+    
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (64 + 1),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    hdr_register_63_0
+        (
+         // Outputs
+         .RD_DATA                       ({_wRxrHdr[C_STRADDLE_W-1:0], _wRxrHdrValid}),
+                                          
+         // Inputs
+         .WR_DATA                       ({__wRxrHdr[C_STRADDLE_W-1:0], __wRxrHdrValid}),
+         .WR_EN                         (__wRxrHdrSOP | rStraddledSOP),
+         .RST_IN                        (RST_IN), // TODO: Remove
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK));
+
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (3),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    sf4dwh
+        (
+         // Outputs
+         .RD_DATA                       ({_wRxrHdr4DWHWDataSF, _wRxrHdrSOPStraddle,_wRxrHdrSOP}),
+         // Inputs
+         .WR_DATA                       ({__wRxrHdr4DWHWDataSF,rStraddledSOP,__wRxrHdrSOP}),
+         .WR_EN                         (1),
+         .RST_IN                        (RST_IN), // TODO: Remove
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (1),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    delayed_sop
+        (
+         // Outputs
+         .RD_DATA                       ({_wRxrHdrDelayedSOP}),
+         // Inputs
+         .WR_DATA                       ({__wRxrHdrSOP}),
+         .WR_EN                         (RX_SR_VALID[C_RX_INPUT_STAGES]),
+         .RST_IN                        (RST_IN), // TODO: Remove
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (64),
+          .C_VALUE                      (0)
+          /*AUTOINSTPARAM*/)
+    hdr_register_127_64
+        (
+         // Outputs
+         .RD_DATA                       (_wRxrHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
+         // Inputs
+         .WR_DATA                       (__wRxrHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
+         .WR_EN                         (__wRxrHdrSOP | rStraddledSOP | rStraddledSOPSplit), // Non straddled start, Straddled, or straddled split
+         .RST_IN                        (RST_IN), // TODO: Remove
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK));
+
+    // ----- Computation Register -----
+    register
+        #(
+          // Parameters
+          .C_WIDTH              (64 + 4),/* TODO: TLP_METADATA_W*/
+          .C_VALUE              (0)
+          /*AUTOINSTPARAM*/)
+    metadata 
+        (// Outputs
+         .RD_DATA               ({wRxrHdr[`TLP_REQMETADW0_I +: 64],
+                                  wRxrHdrSF,wRxrHdrDataSoff,
+                                  wRxrHdrEF}),/* TODO: TLP_METADATA_R and other signals*/
+         // Inputs
+         .RST_IN                (0),/* TODO: Never need to reset?*/
+         .WR_DATA               ({_wRxrHdr[`TLP_REQMETADW0_I +: 64],
+                                  _wRxrHdrSF,_wRxrHdrDataSoff[1:0],
+                                  _wRxrHdrEF}),/* TODO: TLP_METADATA_R*/
+         .WR_EN                 (1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                   (CLK));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH              (3+8),
+          .C_VALUE              (0)
+          /*AUTOINSTPARAM*/)
+    metadata_valid
+        (// Output
+         .RD_DATA               ({wRxrHdrValid, 
+                                  wRxrHdrSCP, wRxrHdrMCP,
+                                  wRxrHdrEndMask, wRxrHdrStartMask}),
+         // Inputs
+         .RST_IN                (RST_IN),
+         .WR_DATA               ({_wRxrHdrValid, 
+                                  _wRxrHdrSCP, _wRxrHdrMCP,
+                                  _wRxrHdrEndMask, _wRxrHdrStartMask}),
+         .WR_EN                 (1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH              (`SIG_ADDR_W/2),
+          .C_VALUE              (0)
+          /*AUTOINSTPARAM*/)
+    addr_63_32
+        (// Outputs
+         .RD_DATA               (wRxrHdr[`TLP_REQADDRHI_R]),
+         // Inputs
+         .RST_IN                (~_wRxrHdr[`TLP_4DWHBIT_I]),
+         .WR_DATA               (_wRxrHdr[`TLP_REQADDRLO_R]), // Instead of a mux, we'll use the reset
+         .WR_EN                 (1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                   (CLK));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH              (`SIG_ADDR_W/2),
+          .C_VALUE              (0)
+          /*AUTOINSTPARAM*/)
+    addr_31_0
+        (// Outputs
+         .RD_DATA               (wRxrHdr[`TLP_REQADDRLO_R]),
+         // Inputs
+         .RST_IN                (0),// Never need to reset
+         .WR_DATA               (_wRxrHdr[`TLP_4DWHBIT_I] ? _wRxrHdr[`TLP_REQADDRHI_R] : _wRxrHdr[`TLP_REQADDRLO_R]),
+         .WR_EN                 (1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                   (CLK));
+
+    offset_to_mask
+        #(// Parameters
+          .C_MASK_SWAP                  (0),
+          .C_MASK_WIDTH                 (4)
+          /*AUTOINSTPARAM*/)
+    o2m_ef
+        (
+         // Outputs
+         .MASK                          (_wRxrHdrEndMask),
+         // Inputs
+         .OFFSET_ENABLE                 (_wRxrHdrEF),
+         .OFFSET                        (_wRxrHdrDataEoff)
+         /*AUTOINST*/);
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_RX_OUTPUT_STAGES),
+          .C_WIDTH                      (C_OUTPUT_STAGE_WIDTH),// TODO: 
+          .C_USE_MEMORY                 (0)
+          /*AUTOINSTPARAM*/)
+    output_pipeline
+        (
+         // Outputs
+         .WR_DATA_READY                 (), // Pinned to 1
+         .RD_DATA                       ({RXR_DATA_WORD_ENABLE, RXR_DATA_START_FLAG, RXR_DATA_START_OFFSET,
+                                          RXR_DATA_END_FLAG,
+                                          RXR_META_FDWBE, RXR_META_LDWBE, RXR_META_TC, 
+                                          RXR_META_ATTR, RXR_META_TAG, RXR_META_TYPE, 
+                                          RXR_META_ADDR, RXR_META_BAR_DECODED, RXR_META_REQUESTER_ID, 
+                                          RXR_META_LENGTH, RXR_META_EP}),
+         .RD_DATA_VALID                 (RXR_DATA_VALID),
+         // Inputs
+         .WR_DATA                       ({wRxrDataWordEnable, wRxrDataStartFlag, wRxrDataStartOffset,
+                                          wRxrDataEndFlag, 
+                                          wRxrMetaFdwbe, wRxrMetaLdwbe, wRxrMetaTC, 
+                                          wRxrMetaAttr, wRxrMetaTag, wRxrMetaType, 
+                                          wRxrMetaAddr, wRxrMetaBarDecoded, wRxrMetaRequesterId, 
+                                          wRxrMetaLength, wRxrMetaEP}),
+         .WR_DATA_VALID                 (wRxrDataValid),
+         .RD_DATA_READY                 (1'b1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../common")
+// End:
diff --git a/fpga/riffa_hdl/rxr_engine_ultrascale.v b/fpga/riffa_hdl/rxr_engine_ultrascale.v
new file mode 100644
index 0000000..be84b1c
--- /dev/null
+++ b/fpga/riffa_hdl/rxr_engine_ultrascale.v
@@ -0,0 +1,497 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            rxr_engine_classic.v
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The RXR Engine (Ultrascale) takes a single stream of 
+// AXI packets and provides the completion packets on the RXR Interface.
+// This Engine is capable of operating at "line rate".
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "trellis.vh"
+`include "ultrascale.vh"
+module rxr_engine_ultrascale
+    #(parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_RX_PIPELINE_DEPTH=10
+      )
+    (
+     // Interface: Clocks
+     input                                    CLK,
+
+     // Interface: Resets
+     input                                    RST_IN,
+
+     // Interface: CQ
+     input                                    M_AXIS_CQ_TVALID,
+     input                                    M_AXIS_CQ_TLAST,
+     input [C_PCI_DATA_WIDTH-1:0]             M_AXIS_CQ_TDATA,
+     input [(C_PCI_DATA_WIDTH/32)-1:0]        M_AXIS_CQ_TKEEP,
+     input [`SIG_CQ_TUSER_W-1:0]              M_AXIS_CQ_TUSER,
+     output                                   M_AXIS_CQ_TREADY,
+
+     // Interface: RXR Engine
+     output [C_PCI_DATA_WIDTH-1:0]            RXR_DATA,
+     output                                   RXR_DATA_VALID,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]       RXR_DATA_WORD_ENABLE,
+     output                                   RXR_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
+     output                                   RXR_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
+     
+     output [`SIG_FBE_W-1:0]                  RXR_META_FDWBE,
+     output [`SIG_LBE_W-1:0]                  RXR_META_LDWBE,
+     output [`SIG_TC_W-1:0]                   RXR_META_TC,
+     output [`SIG_ATTR_W-1:0]                 RXR_META_ATTR,
+     output [`SIG_TAG_W-1:0]                  RXR_META_TAG,
+     output [`SIG_TYPE_W-1:0]                 RXR_META_TYPE,
+     output [`SIG_ADDR_W-1:0]                 RXR_META_ADDR,
+     output [`SIG_BARDECODE_W-1:0]            RXR_META_BAR_DECODED,
+     output [`SIG_REQID_W-1:0]                RXR_META_REQUESTER_ID,
+     output [`SIG_LEN_W-1:0]                  RXR_META_LENGTH,
+     output                                   RXR_META_EP
+     );
+
+    // Width of the Byte Enable Shift register
+    localparam C_RX_BE_W = (`SIG_FBE_W + `SIG_LBE_W);
+
+    localparam C_RX_INPUT_STAGES = 0;
+    localparam C_RX_OUTPUT_STAGES = 2; // Should always be at least one
+    localparam C_RX_COMPUTATION_STAGES = 1;
+    localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
+
+    // CYCLE = LOW ORDER BIT (INDEX) / C_PCI_DATA_WIDTH
+    localparam C_RX_ADDRDW0_CYCLE = (`UPKT_RXR_ADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+    localparam C_RX_ADDRDW1_CYCLE = (`UPKT_RXR_ADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+    localparam C_RX_METADW0_CYCLE = (`UPKT_RXR_METADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+    localparam C_RX_METADW1_CYCLE = (`UPKT_RXR_METADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+    localparam C_RX_PAYLOAD_CYCLE = (`UPKT_RXR_PAYLOAD_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
+    localparam C_RX_BE_CYCLE = C_RX_INPUT_STAGES; // Available on the first cycle (as per the spec)
+    
+    localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW0_I%C_PCI_DATA_WIDTH);
+    localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW1_I%C_PCI_DATA_WIDTH);
+    localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW0_I%C_PCI_DATA_WIDTH);
+    localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW1_I%C_PCI_DATA_WIDTH);
+    localparam C_RX_BE_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES;
+
+    // Mask width of the calculated SOF/EOF fields
+    localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
+
+    wire                                      wMAxisCqSop;
+    wire                                      wMAxisCqTlast;
+    wire [C_RX_PIPELINE_DEPTH:0]              wRxSrSop;
+    wire [C_RX_PIPELINE_DEPTH:0]              wRxSrEop;
+    wire [C_RX_PIPELINE_DEPTH:0]              wRxSrDataValid;
+    wire [(C_RX_PIPELINE_DEPTH+1)*C_RX_BE_W-1:0] wRxSrBe;
+    wire [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] wRxSrData;
+
+    wire                                                wRxrDataValid;
+    wire                                                wRxrDataReady; // Pinned High
+    wire                                                wRxrDataEndFlag;
+    wire [C_OFFSET_WIDTH-1:0]                           wRxrDataEndOffset;
+    wire                                                wRxrDataStartFlag;
+    wire [C_OFFSET_WIDTH-1:0]                           wRxrDataStartOffset;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]                    wRxrDataWordEnable;
+    wire [127:0]                                        wRxrHdr;
+    wire [`SIG_TYPE_W-1:0]                              wRxrType;
+    wire [`SIG_FBE_W-1:0]                               wRxrMetaFdwbe;
+    wire [`SIG_LBE_W-1:0]                               wRxrMetaLdwbe;
+    wire [C_RX_BE_W-1:0]                                wRxrBe;
+    wire [`SIG_BARDECODE_W-1:0]                         wRxrBarDecoded;
+    
+    wire [127:0]                                        wHdr;
+    wire                                                wEndFlag;
+    wire                                                wEndFlagLastCycle;
+    wire                                                _wEndFlag;    
+    wire [C_OFFSET_WIDTH-1:0]                           wEndOffset;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]                    wEndMask;
+    wire                                                _wStartFlag;
+    wire                                                wStartFlag;
+    wire [1:0]                                          wStartFlags;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]                    wStartMask;
+    wire [C_OFFSET_WIDTH-1:0]                           wStartOffset;
+    wire [C_RX_BE_W-1:0]                                wByteEnables;                    
+    wire [`SIG_BARDECODE_W-1:0]                         wBarDecoded;
+    wire                                                wHasPayload;
+    
+    wire [`SIG_TYPE_W-1:0]                              wType;
+    reg                                                 rValid,_rValid;
+
+    assign wMAxisCqSop = M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_SOP_R];
+    assign wMAxisCqTlast = M_AXIS_CQ_TLAST;
+
+    assign wBarDecoded = (8'b0000_0001 << wHdr[`UPKT_RXR_BARID_R]);
+    
+
+    // We assert the end flag on the last cycle of a packet, however on single
+    // cycle packets we need to check that there wasn't an end flag last cycle
+    // (because wStartFlag will take priority when setting rValid) so we can
+    // deassert rValid if necessary.
+    assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES];
+    assign wEndFlagLastCycle = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES + 1];
+
+    /* verilator lint_off WIDTH */
+    assign wStartOffset = 4;
+    assign wEndOffset = wHdr[`UPKT_RXR_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXR_MAXHDR_W-32)/32);
+    /* verilator lint_on WIDTH */
+
+    // Output assignments. See the header file derived from the user
+    // guide for indices.
+    assign RXR_META_EP = wRxrHdr[`UPKT_RXR_EP_R];
+    assign RXR_META_LENGTH = wRxrHdr[`UPKT_RXR_LENGTH_I+:`SIG_LEN_W];// The top three bits are ignored (fine)
+    assign RXR_META_ATTR = wRxrHdr[`UPKT_RXR_ATTR_R];
+    assign RXR_META_TC = wRxrHdr[`UPKT_RXR_TC_R];
+    assign RXR_META_TYPE = wRxrType;
+    assign RXR_META_REQUESTER_ID = wRxrHdr[`UPKT_RXR_REQID_R];
+    assign RXR_META_TAG = wRxrHdr[`UPKT_RXR_TAG_R];
+    assign RXR_META_FDWBE = wRxrMetaFdwbe;
+    assign RXR_META_LDWBE = wRxrMetaLdwbe;
+    assign RXR_META_ADDR = {wRxrHdr[`UPKT_RXR_ADDR_R],2'b0};
+    assign RXR_DATA_START_FLAG = wRxrDataStartFlag;
+    assign RXR_DATA_START_OFFSET = 0;
+    assign RXR_DATA_END_FLAG = wRxrDataEndFlag;
+    assign RXR_DATA_END_OFFSET = wEndOffset;
+    assign RXR_META_BAR_DECODED = wRxrBarDecoded;
+    assign RXR_DATA_VALID = wRxrDataValid;
+    assign RXR_DATA = wRxSrData[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
+
+    assign M_AXIS_CQ_TREADY = 1'b1;
+
+    assign wType = upkt_to_trellis_type({wHdr[`UPKT_RXR_TYPE_R], wHdr[`UPKT_RXR_LENGTH_R] != 0});
+    
+    assign _wEndFlag = wRxSrEop[C_RX_INPUT_STAGES];
+    assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES+1];
+    assign _wStartFlag = wStartFlags != 0;
+    assign wHasPayload = ~wType[`TRLS_TYPE_PAY_I];
+    assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
+
+    generate
+        if(C_PCI_DATA_WIDTH == 64) begin
+            assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~rValid;
+            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wRxSrEop[C_RX_INPUT_STAGES]; // No Payload
+        end else if (C_PCI_DATA_WIDTH == 128) begin    
+            assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~rValid;
+            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & wRxSrEop[C_RX_INPUT_STAGES]; // No Payload
+        end else begin // 256
+            assign wStartFlags[1] = 0;
+            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
+        end // else: !if(C_PCI_DATA_WIDTH == 128)
+    endgenerate
+
+    always @(*) begin
+        _rValid = rValid;
+        if(_wStartFlag) begin
+	        _rValid = 1'b1;
+        end else if (wEndFlag) begin
+	        _rValid = 1'b0;
+        end
+    end
+    
+    always @(posedge CLK) begin
+        if(RST_IN) begin
+	        rValid <= 1'b0;
+        end else begin
+	        rValid <= _rValid;
+        end
+    end
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (32))
+    meta_DW1_register
+        (
+         // Outputs
+         .RD_DATA                       (wHdr[127:96]),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .WR_DATA                       (wRxSrData[C_RX_METADW1_INDEX +: 32]),
+         .WR_EN                         (wRxSrSop[C_RX_METADW1_CYCLE]));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (32))
+    metadata_DW0_register
+        (
+         // Outputs
+         .RD_DATA                       (wHdr[95:64]),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .WR_DATA                       (wRxSrData[C_RX_METADW0_INDEX +: 32]),
+         .WR_EN                         (wRxSrSop[C_RX_METADW0_CYCLE]));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (32))
+    addr_DW1_register
+        (
+         // Outputs
+         .RD_DATA                       (wHdr[63:32]),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .WR_DATA                       (wRxSrData[C_RX_ADDRDW1_INDEX +: 32]),
+         .WR_EN                         (wRxSrSop[C_RX_ADDRDW1_CYCLE]));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (32))
+    addr_DW0_register
+        (
+         // Outputs
+         .RD_DATA                       (wHdr[31:0]),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .WR_DATA                       (wRxSrData[C_RX_ADDRDW0_INDEX +: 32]),
+         .WR_EN                         (wRxSrSop[C_RX_ADDRDW0_CYCLE]));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (C_RX_BE_W))
+    be_register
+        (
+         // Outputs
+         .RD_DATA                       (wByteEnables),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .WR_DATA                       (wRxSrBe[C_RX_BE_INDEX +: C_RX_BE_W]),
+         .WR_EN                         (wRxSrSop[C_RX_BE_CYCLE]));
+
+    // Shift register for input data with output taps for each delayed
+    // cycle. 
+    shiftreg
+        #(
+          // Parameters
+          .C_DEPTH                     (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                     (C_PCI_DATA_WIDTH)
+          /*AUTOINSTPARAM*/)
+    data_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                       (wRxSrData),
+         // Inputs
+         .WR_DATA                       (M_AXIS_CQ_TDATA),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    // Start Flag Shift Register. Data enables are derived from the
+    // taps on this shift register.
+    shiftreg 
+        #(
+          // Parameters
+          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                      (1'b1)
+          /*AUTOINSTPARAM*/)
+    sop_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                       (wRxSrSop),
+         // Inputs
+         .WR_DATA                       (wMAxisCqSop & M_AXIS_CQ_TVALID),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    // End Flag Shift Register. 
+    shiftreg 
+        #(
+          // Parameters
+          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                      (1'b1)
+          /*AUTOINSTPARAM*/)
+    eop_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                       (wRxSrEop),
+         // Inputs
+         .WR_DATA                       (wMAxisCqTlast),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    // Data Valid Shift Register. Data enables are derived from the
+    // taps on this shift register.
+    shiftreg 
+        #(
+          // Parameters
+          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                      (1'b1)
+          /*AUTOINSTPARAM*/)
+    valid_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                       (wRxSrDataValid),
+         // Inputs
+         .WR_DATA                       (M_AXIS_CQ_TVALID),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+
+    // Shift register for input data with output taps for each delayed
+    // cycle. 
+    shiftreg
+        #(
+          // Parameters
+          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
+          .C_WIDTH                      (C_RX_BE_W)
+          /*AUTOINSTPARAM*/)
+    be_shiftreg_inst
+        (
+         // Outputs
+         .RD_DATA                       (wRxSrBe),
+         // Inputs
+         .WR_DATA                       (M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_BE_R]),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    register
+        #(
+          // Parameters
+          .C_WIDTH                      (1),
+          .C_VALUE                      (1'b0)
+          /*AUTOINSTPARAM*/)
+    start_flag_register
+        (
+         // Outputs
+         .RD_DATA                       (wStartFlag),
+         // Inputs
+         .WR_DATA                       (_wStartFlag),
+         .WR_EN                         (1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    offset_to_mask
+        #(// Parameters
+          .C_MASK_SWAP                  (0),
+          .C_MASK_WIDTH                 (C_PCI_DATA_WIDTH/32)
+          /*AUTOINSTPARAM*/)
+    o2m_ef
+        (
+         // Outputs
+         .MASK                          (wEndMask),
+         // Inputs
+         .OFFSET_ENABLE                 (wEndFlag),
+         .OFFSET                        (wEndOffset)
+         /*AUTOINST*/);
+
+    generate
+        if(C_RX_OUTPUT_STAGES == 0) begin
+            assign RXR_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | wHasPayload}};
+        end else begin
+            register
+                #(
+                  // Parameters
+                  .C_WIDTH              (C_PCI_DATA_WIDTH/32),
+                  .C_VALUE              (0)
+                  /*AUTOINSTPARAM*/)
+            dw_enable
+                (// Outputs
+                 .RD_DATA               (wRxrDataWordEnable),
+                 // Inputs
+                 .RST_IN                (~rValid | wHasPayload),
+                 .WR_DATA               (wEndMask & wStartMask),
+                 .WR_EN                 (1),
+                 /*AUTOINST*/
+                 .CLK                   (CLK));
+
+            pipeline
+                #(
+                  // Parameters
+                  .C_DEPTH                      (C_RX_OUTPUT_STAGES-1),
+                  .C_WIDTH                      (C_PCI_DATA_WIDTH/32),
+                  .C_USE_MEMORY                 (0)
+                  /*AUTOINSTPARAM*/)
+            dw_pipeline
+                (
+                 // Outputs
+                 .WR_DATA_READY                 (), // Pinned to 1
+                 .RD_DATA                       (RXR_DATA_WORD_ENABLE),
+                 .RD_DATA_VALID                 (),
+                 // Inputs
+                 .WR_DATA                       (wRxrDataWordEnable),
+                 .WR_DATA_VALID                 (1),
+                 .RD_DATA_READY                 (1'b1),
+                 /*AUTOINST*/
+                 // Inputs
+                 .CLK                           (CLK),
+                 .RST_IN                        (RST_IN));
+        end
+    endgenerate
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_RX_OUTPUT_STAGES),
+          .C_WIDTH                      (`UPKT_RXR_MAXHDR_W + 2*(1 + C_OFFSET_WIDTH) + `SIG_LBE_W + `SIG_FBE_W + `SIG_BARDECODE_W + `SIG_TYPE_W),
+          .C_USE_MEMORY                 (0)
+          /*AUTOINSTPARAM*/)
+    output_pipeline
+        (
+         // Outputs
+         .WR_DATA_READY                 (), // Pinned to 1
+         .RD_DATA                       ({wRxrHdr,wRxrBarDecoded,wRxrType,wRxrDataStartFlag,wRxrDataStartOffset,wRxrDataEndFlag,wRxrDataEndOffset,wRxrMetaLdwbe,wRxrMetaFdwbe}),
+         .RD_DATA_VALID                 (wRxrDataValid),
+         // Inputs
+         .WR_DATA                       ({wHdr,wBarDecoded,wType,wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0],wByteEnables}),
+         .WR_DATA_VALID                 (rValid),
+         .RD_DATA_READY                 (1'b1),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../common/")
+// End:
diff --git a/fpga/riffa_hdl/schedules.vh b/fpga/riffa_hdl/schedules.vh
new file mode 100644
index 0000000..30eea45
--- /dev/null
+++ b/fpga/riffa_hdl/schedules.vh
@@ -0,0 +1,326 @@
+/*
+ Filename: schedules.vh
+ Version: 1.0
+ Verilog Standard: Verilog-2001
+
+ Description: This file defines the schedules for each output mux used
+ in the tx_alignment alignment pipeline and the connections for each
+ mux. The schedule depends on the width of the PCI bus.
+ 
+ The wSchedule array is intended to be a multiported ROM implemented
+ as small memory slices adjacent to the corresponding output
+ multiplexer. The wSchedule array is first indexed by the MUX id,
+ then the concatenation of the header select bit (3 or 4 DW Header),
+ whether or not the packet is Quad word aligned, and a saturating
+ counter that counts up from the start of the packet to the maximum
+ schedule index for that particular data bus width. 
+ 
+ For a 256-bit PCIe interface, the schedule is 2 cycles long. 
+ For a 128-bit PCIe interface, the schedule is 3 cycles long. 
+ For a 64-bit PCIe interface, the schedule is 4 cycles long. 
+ For a 32-bit PCIe interface, the schedule is 5 cycles long. 
+ 
+ This file also contains the array wTxMuxInputs, which defines the
+ connections for each output multiplexer. The wTxMuxInputs array is
+ indexed by the output multiplexer ID, which provides a concatenated
+ bus of all of the DW inputs for that particular mux.
+ 
+ These schedules are derived from the .csv files:
+ SchedulesTable_256.csv SchedulesTable_128.csv SchedulesTable_64.csv
+ and SchedulesTable_32.csv
+ 
+ Notes: Any modifications to this file should meet the conditions set
+ forth in the "Trellis Style Guide"
+ 
+ Author: Dustin Richmond (@darichmond) 
+ Co-Authors:
+ */
+`ifndef SCHEDULES_VH
+
+    `define SCHEDULES_VH
+
+    `define TXA_HDR0_INDEX 0
+    `define TXA_HDR1_INDEX 1
+    `define TXA_HDR2_INDEX 2
+    `define TXA_HDR3_INDEX 3
+    `define TXA_DW0_INDEX 4
+    `define TXA_DW1_INDEX 5
+    `define TXA_DW2_INDEX 6
+    `define TXA_DW3_INDEX 7
+    `define TXA_DW4_INDEX 8
+    `define TXA_DW5_INDEX 9
+    `define TXA_DW6_INDEX 10
+    `define TXA_DW7_INDEX 11
+
+    `define TXA_5DW 3'b101
+    `define TXA_4DW 3'b100
+    `define TXA_3DW 3'b011
+
+    `define TXA_3DWH 1'b0
+    `define TXA_4DWH 1'b1
+    `define TXA_NOB  1'b0
+    `define TXA_INSB 1'b1
+
+    `define TXA_READ 1'b1
+// 256 Schedule
+
+// Ugly as sin, but works
+generate 
+    if(C_DATA_WIDTH == 256) begin
+        assign wTxMuxInputs[0] = {wAggregate[`TXA_DW5_INDEX],
+                                  wAggregate[`TXA_DW4_INDEX],
+                                  wAggregate[`TXA_DW3_INDEX],
+                                  wAggregate[`TXA_HDR0_INDEX]};
+        assign wSchedule[0][{`TXA_3DW,1'b0}] = 2'd0;
+        assign wSchedule[0][{`TXA_3DW,1'b1}] = 2'd3;
+
+        assign wSchedule[0][{`TXA_4DW,1'b0}] = 2'd0;
+        assign wSchedule[0][{`TXA_4DW,1'b1}] = 2'd2;
+
+        assign wSchedule[0][{`TXA_5DW,1'b0}] = 2'd0;
+        assign wSchedule[0][{`TXA_5DW,1'b1}] = 2'd1;
+
+        
+        assign wTxMuxInputs[1] = {wAggregate[`TXA_DW6_INDEX],
+                                  wAggregate[`TXA_DW5_INDEX],
+                                  wAggregate[`TXA_DW4_INDEX],
+                                  wAggregate[`TXA_HDR1_INDEX]};
+
+        assign wSchedule[1][{`TXA_3DW,1'b0}] = 2'd0;
+        assign wSchedule[1][{`TXA_3DW,1'b1}] = 2'd3;
+
+        assign wSchedule[1][{`TXA_4DW,1'b0}] = 2'd0;
+        assign wSchedule[1][{`TXA_4DW,1'b1}] = 2'd2;
+
+        assign wSchedule[1][{`TXA_5DW,1'b0}] = 2'd0;
+        assign wSchedule[1][{`TXA_5DW,1'b1}] = 2'd1;
+
+        assign wTxMuxInputs[2] = {wAggregate[`TXA_DW7_INDEX],
+                                  wAggregate[`TXA_DW6_INDEX],
+                                  wAggregate[`TXA_DW5_INDEX],
+                                  wAggregate[`TXA_HDR2_INDEX]};
+
+        assign wSchedule[2][{`TXA_3DW,1'b0}] = 2'd0;
+        assign wSchedule[2][{`TXA_3DW,1'b1}] = 2'd3;
+
+        assign wSchedule[2][{`TXA_4DW,1'b0}] = 2'd0;
+        assign wSchedule[2][{`TXA_4DW,1'b1}] = 2'd2;
+
+        assign wSchedule[2][{`TXA_5DW,1'b0}] = 2'd0;
+        assign wSchedule[2][{`TXA_5DW,1'b1}] = 2'd1;
+
+        assign wTxMuxInputs[3] = {wAggregate[`TXA_DW7_INDEX],
+                                  wAggregate[`TXA_DW6_INDEX],
+                                  wAggregate[`TXA_DW0_INDEX],
+                                  wAggregate[`TXA_HDR3_INDEX]};
+
+        assign wSchedule[3][{`TXA_3DW,1'b0}] = 2'd1;
+        assign wSchedule[3][{`TXA_3DW,1'b1}] = 2'd1;
+
+        assign wSchedule[3][{`TXA_4DW,1'b0}] = 2'd0;
+        assign wSchedule[3][{`TXA_4DW,1'b1}] = 2'd3;
+
+        assign wSchedule[3][{`TXA_5DW,1'b0}] = 2'd0;
+        assign wSchedule[3][{`TXA_5DW,1'b1}] = 2'd2;
+
+        assign wTxMuxInputs[4] = {wAggregate[`TXA_DW7_INDEX],
+                                  wAggregate[`TXA_DW1_INDEX],
+                                  wAggregate[`TXA_DW0_INDEX],
+                                  wAggregate[`TXA_DW0_INDEX]};
+
+        assign wSchedule[4][{`TXA_3DW,1'b0}] = 2'd2;
+        assign wSchedule[4][{`TXA_3DW,1'b1}] = 2'd2;
+
+        assign wSchedule[4][{`TXA_4DW,1'b0}] = 2'd0;
+        assign wSchedule[4][{`TXA_4DW,1'b1}] = 2'd0;
+
+        assign wSchedule[4][{`TXA_5DW,1'b0}] = 2'd3;
+        assign wSchedule[4][{`TXA_5DW,1'b1}] = 2'd3;
+
+        assign wTxMuxInputs[5] = {wAggregate[`TXA_DW2_INDEX],
+                                  wAggregate[`TXA_DW1_INDEX],
+                                  wAggregate[`TXA_DW1_INDEX],
+                                  wAggregate[`TXA_DW0_INDEX]};
+
+        assign wSchedule[5][{`TXA_3DW,1'b0}] = 2'd3;
+        assign wSchedule[5][{`TXA_3DW,1'b1}] = 2'd3;
+
+        assign wSchedule[5][{`TXA_4DW,1'b0}] = 2'd1;
+        assign wSchedule[5][{`TXA_4DW,1'b1}] = 2'd1;
+
+        assign wSchedule[5][{`TXA_5DW,1'b0}] = 2'd0;
+        assign wSchedule[5][{`TXA_5DW,1'b1}] = 2'd0;
+
+        assign wTxMuxInputs[6] = {wAggregate[`TXA_DW3_INDEX],
+                                  wAggregate[`TXA_DW2_INDEX],
+                                  wAggregate[`TXA_DW2_INDEX],
+                                  wAggregate[`TXA_DW1_INDEX]};
+
+        assign wSchedule[6][{`TXA_3DW,1'b0}] = 2'd3;
+        assign wSchedule[6][{`TXA_3DW,1'b1}] = 2'd3;
+
+        assign wSchedule[6][{`TXA_4DW,1'b0}] = 2'd1;
+        assign wSchedule[6][{`TXA_4DW,1'b1}] = 2'd1;
+
+        assign wSchedule[6][{`TXA_5DW,1'b0}] = 2'd0;
+        assign wSchedule[6][{`TXA_5DW,1'b1}] = 2'd0;
+
+        assign wTxMuxInputs[7] = {wAggregate[`TXA_DW4_INDEX],
+                                  wAggregate[`TXA_DW3_INDEX],
+                                  wAggregate[`TXA_DW3_INDEX],
+                                  wAggregate[`TXA_DW2_INDEX]};
+
+        assign wSchedule[7][{`TXA_3DW,1'b0}] = 2'd3;
+        assign wSchedule[7][{`TXA_3DW,1'b1}] = 2'd3;
+
+        assign wSchedule[7][{`TXA_4DW,1'b0}] = 2'd1;
+        assign wSchedule[7][{`TXA_4DW,1'b1}] = 2'd1;
+
+        assign wSchedule[7][{`TXA_5DW,1'b0}] = 2'd0;
+        assign wSchedule[7][{`TXA_5DW,1'b1}] = 2'd0;
+
+    end else if (C_DATA_WIDTH == 128) begin
+
+        assign wTxMuxInputs[0] = {wAggregate[`TXA_DW3_INDEX],
+                                  wAggregate[`TXA_DW1_INDEX],
+                                  wAggregate[`TXA_DW0_INDEX],
+                                  wAggregate[`TXA_HDR0_INDEX]};
+
+        assign wSchedule[0][{`TXA_3DW,1'b0,1'b0}] = 2'd0;
+        assign wSchedule[0][{`TXA_3DW,1'b0,1'b1}] = 2'd2;
+        assign wSchedule[0][{`TXA_3DW,1'b1,1'b0}] = 2'd2;
+        
+        assign wSchedule[0][{`TXA_4DW,1'b0,1'b0}] = 2'd0;
+        assign wSchedule[0][{`TXA_4DW,1'b0,1'b1}] = 2'd1;
+        assign wSchedule[0][{`TXA_4DW,1'b1,1'b0}] = 2'd1;
+
+        assign wSchedule[0][{`TXA_5DW,1'b0,1'b0}] = 2'd0;
+        assign wSchedule[0][{`TXA_5DW,1'b0,1'b1}] = 2'd3;
+        assign wSchedule[0][{`TXA_5DW,1'b1,1'b0}] = 2'd3;
+
+        assign wTxMuxInputs[1] = {wAggregate[`TXA_DW2_INDEX],
+                                  wAggregate[`TXA_DW1_INDEX],
+                                  wAggregate[`TXA_DW0_INDEX],
+                                  wAggregate[`TXA_HDR1_INDEX]};
+
+        assign wSchedule[1][{`TXA_3DW,1'b0,1'b0}] = 2'd0;
+        assign wSchedule[1][{`TXA_3DW,1'b0,1'b1}] = 2'd3;
+        assign wSchedule[1][{`TXA_3DW,1'b1,1'b0}] = 2'd3;
+
+        assign wSchedule[1][{`TXA_4DW,1'b0,1'b0}] = 2'd0;
+        assign wSchedule[1][{`TXA_4DW,1'b0,1'b1}] = 2'd2;
+        assign wSchedule[1][{`TXA_4DW,1'b1,1'b0}] = 2'd2;
+
+        assign wSchedule[1][{`TXA_5DW,1'b0,1'b0}] = 2'd0;
+        assign wSchedule[1][{`TXA_5DW,1'b0,1'b1}] = 2'd1;
+        assign wSchedule[1][{`TXA_5DW,1'b1,1'b0}] = 2'd1;
+
+        assign wTxMuxInputs[2] = {wAggregate[`TXA_DW3_INDEX],
+                                  wAggregate[`TXA_DW2_INDEX],
+                                  wAggregate[`TXA_DW1_INDEX],
+                                  wAggregate[`TXA_HDR2_INDEX]};
+
+        assign wSchedule[2][{`TXA_3DW,1'b0,1'b0}] = 2'd0;
+        assign wSchedule[2][{`TXA_3DW,1'b0,1'b1}] = 2'd3;
+        assign wSchedule[2][{`TXA_3DW,1'b1,1'b0}] = 2'd3;
+
+        assign wSchedule[2][{`TXA_4DW,1'b0,1'b0}] = 2'd0;
+        assign wSchedule[2][{`TXA_4DW,1'b0,1'b1}] = 2'd2;
+        assign wSchedule[2][{`TXA_4DW,1'b1,1'b0}] = 2'd2;
+
+        assign wSchedule[2][{`TXA_5DW,1'b0,1'b0}] = 2'd0;
+        assign wSchedule[2][{`TXA_5DW,1'b0,1'b1}] = 2'd1;
+        assign wSchedule[2][{`TXA_5DW,1'b1,1'b0}] = 2'd1;
+
+        assign wTxMuxInputs[3] = {wAggregate[`TXA_DW3_INDEX],
+                                  wAggregate[`TXA_DW2_INDEX],
+                                  wAggregate[`TXA_DW0_INDEX],
+                                  wAggregate[`TXA_HDR3_INDEX]};
+
+        assign wSchedule[3][{`TXA_3DW,1'b0,1'b0}] = 2'd1;
+        assign wSchedule[3][{`TXA_3DW,1'b0,1'b1}] = 2'd1;
+        assign wSchedule[3][{`TXA_3DW,1'b1,1'b0}] = 2'd1;
+
+        assign wSchedule[3][{`TXA_4DW,1'b0,1'b0}] = 2'd0;
+        assign wSchedule[3][{`TXA_4DW,1'b0,1'b1}] = 2'd3;
+        assign wSchedule[3][{`TXA_4DW,1'b1,1'b0}] = 2'd3;
+
+        assign wSchedule[3][{`TXA_5DW,1'b0,1'b0}] = 2'd0;
+        assign wSchedule[3][{`TXA_5DW,1'b0,1'b1}] = 2'd2;
+        assign wSchedule[3][{`TXA_5DW,1'b1,1'b0}] = 2'd2;
+
+    end else if (C_DATA_WIDTH == 64) begin
+
+        assign wTxMuxInputs[0] = {wAggregate[`TXA_DW1_INDEX],
+                                  wAggregate[`TXA_DW0_INDEX],
+                                  wAggregate[`TXA_HDR2_INDEX],
+                                  wAggregate[`TXA_HDR0_INDEX]};
+
+        assign wSchedule[0][{`TXA_3DW,2'b00}] = 2'd0;
+        assign wSchedule[0][{`TXA_3DW,2'b01}] = 2'd1;
+        assign wSchedule[0][{`TXA_3DW,2'b10}] = 2'd3;
+        assign wSchedule[0][{`TXA_3DW,2'b11}] = 2'd3;
+        
+        assign wSchedule[0][{`TXA_4DW,2'b00}] = 2'd0;
+        assign wSchedule[0][{`TXA_4DW,2'b01}] = 2'd1;
+        assign wSchedule[0][{`TXA_4DW,2'b10}] = 2'd2;
+        assign wSchedule[0][{`TXA_4DW,2'b11}] = 2'd2;
+
+        assign wSchedule[0][{`TXA_5DW,2'b00}] = 2'd0;
+        assign wSchedule[0][{`TXA_5DW,2'b01}] = 2'd1;
+        assign wSchedule[0][{`TXA_5DW,2'b10}] = 2'd3;
+        assign wSchedule[0][{`TXA_5DW,2'b11}] = 2'd3;
+
+        assign wTxMuxInputs[1] = {wAggregate[`TXA_DW1_INDEX],
+                                  wAggregate[`TXA_DW0_INDEX],
+                                  wAggregate[`TXA_HDR3_INDEX],
+                                  wAggregate[`TXA_HDR1_INDEX]};
+
+        assign wSchedule[1][{`TXA_3DW,2'b00}] = 2'd0;
+        assign wSchedule[1][{`TXA_3DW,2'b01}] = 2'd2;
+        assign wSchedule[1][{`TXA_3DW,2'b10}] = 2'd2;
+        assign wSchedule[1][{`TXA_3DW,2'b11}] = 2'd2;
+
+        assign wSchedule[1][{`TXA_4DW,2'b00}] = 2'd0;
+        assign wSchedule[1][{`TXA_4DW,2'b01}] = 2'd1;
+        assign wSchedule[1][{`TXA_4DW,2'b10}] = 2'd3;
+        assign wSchedule[1][{`TXA_4DW,2'b11}] = 2'd3;
+        
+        assign wSchedule[1][{`TXA_5DW,2'b00}] = 2'd0;
+        assign wSchedule[1][{`TXA_5DW,2'b01}] = 2'd1;
+        assign wSchedule[1][{`TXA_5DW,2'b10}] = 2'd2;
+        assign wSchedule[1][{`TXA_5DW,2'b11}] = 2'd2;
+
+    end else if (C_DATA_WIDTH == 32) begin
+
+        assign wTxMuxInputs[0] = {wAggregate[`TXA_DW0_INDEX],
+                                  wAggregate[`TXA_HDR3_INDEX],
+                                  wAggregate[`TXA_HDR2_INDEX],
+                                  wAggregate[`TXA_HDR1_INDEX],
+                                  wAggregate[`TXA_HDR0_INDEX]};
+
+        assign wSchedule[0][{`TXA_3DW,3'b000}] = 3'd0;
+        assign wSchedule[0][{`TXA_3DW,3'b001}] = 3'd1;
+        assign wSchedule[0][{`TXA_3DW,3'b010}] = 3'd2;
+        assign wSchedule[0][{`TXA_3DW,3'b011}] = 3'd4;
+        assign wSchedule[0][{`TXA_3DW,3'b100}] = 3'd4;
+        assign wSchedule[0][{`TXA_3DW,3'b101}] = 3'd4;
+        
+        assign wSchedule[0][{`TXA_4DW,3'b000}] = 3'd0;
+        assign wSchedule[0][{`TXA_4DW,3'b001}] = 3'd1;
+        assign wSchedule[0][{`TXA_4DW,3'b010}] = 3'd2;
+        assign wSchedule[0][{`TXA_4DW,3'b011}] = 3'd3;
+        assign wSchedule[0][{`TXA_4DW,3'b100}] = 3'd4;
+        assign wSchedule[0][{`TXA_4DW,3'b101}] = 3'd4;
+
+        assign wSchedule[0][{`TXA_5DW,3'b000}] = 3'd0;
+        assign wSchedule[0][{`TXA_5DW,3'b001}] = 3'd1;
+        assign wSchedule[0][{`TXA_5DW,3'b010}] = 3'd2;
+        assign wSchedule[0][{`TXA_5DW,3'b011}] = 3'd3;
+        assign wSchedule[0][{`TXA_5DW,3'b100}] = 3'd4;
+        assign wSchedule[0][{`TXA_5DW,3'b101}] = 3'd4;
+    end else begin
+        // Error!!!
+    end
+endgenerate
+`endif
diff --git a/fpga/riffa_hdl/scsdpram.v b/fpga/riffa_hdl/scsdpram.v
new file mode 100644
index 0000000..0629a2e
--- /dev/null
+++ b/fpga/riffa_hdl/scsdpram.v
@@ -0,0 +1,80 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+/*
+ Filename: shiftreg.v
+ Version: 1.0
+ Verilog Standard: Verilog-2001
+
+ Description: A simple, single clock, simple dual port (SCSDP) ram
+ 
+ Notes: Any modifications to this file should meet the conditions set
+ forth in the "Trellis Style Guide"
+ 
+ Author: Dustin Richmond (@darichmond) 
+ Co-Authors:
+ */
+`timescale 1ns/1ns
+`include "functions.vh"
+module scsdpram
+    #(
+      parameter C_WIDTH = 32,
+      parameter C_DEPTH = 1024
+      )
+    (
+     input                       CLK,
+
+     input                       RD1_EN,
+     input [clog2s(C_DEPTH)-1:0] RD1_ADDR,
+     output [C_WIDTH-1:0]        RD1_DATA,
+
+     input                       WR1_EN,
+     input [clog2s(C_DEPTH)-1:0] WR1_ADDR,
+     input [C_WIDTH-1:0]         WR1_DATA
+     );
+
+    reg [C_WIDTH-1:0]            rMemory [C_DEPTH-1:0];
+    reg [C_WIDTH-1:0]            rDataOut;   
+
+    assign RD1_DATA = rDataOut;
+
+    always @(posedge CLK) begin
+        if (WR1_EN) begin
+            rMemory[WR1_ADDR] <= #1 WR1_DATA;
+        end
+        if(RD1_EN) begin
+            rDataOut <= #1 rMemory[RD1_ADDR];
+        end
+    end   
+endmodule
diff --git a/fpga/riffa_hdl/sg_list_reader_128.v b/fpga/riffa_hdl/sg_list_reader_128.v
new file mode 100644
index 0000000..f7d520f
--- /dev/null
+++ b/fpga/riffa_hdl/sg_list_reader_128.v
@@ -0,0 +1,141 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			sg_list_reader_128.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Reads data from the scatter gather list buffer.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`define S_SGR128_RD_0		1'b1
+`define S_SGR128_RD_WAIT	1'b0
+
+`define S_SGR128_CAP_0		1'b0
+`define S_SGR128_CAP_RDY	1'b1
+
+`timescale 1ns/1ns
+module sg_list_reader_128 #(
+	parameter C_DATA_WIDTH = 9'd128
+)
+(
+	input CLK,
+	input RST,
+
+	input [C_DATA_WIDTH-1:0] BUF_DATA,	// Scatter gather buffer data 
+	input BUF_DATA_EMPTY,				// Scatter gather buffer data empty
+	output BUF_DATA_REN,				// Scatter gather buffer data read enable
+
+	output VALID,						// Scatter gather element data is valid
+	output EMPTY,						// Scatter gather elements empty
+	input REN,							// Scatter gather element data read enable
+	output [63:0] ADDR,					// Scatter gather element address
+	output [31:0] LEN					// Scatter gather element length (in words)
+);
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg							rRdState=`S_SGR128_RD_0, _rRdState=`S_SGR128_RD_0;
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg							rCapState=`S_SGR128_CAP_0, _rCapState=`S_SGR128_CAP_0;
+reg		[C_DATA_WIDTH-1:0]	rData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};
+reg		[63:0]				rAddr=64'd0, _rAddr=64'd0;
+reg		[31:0]				rLen=0, _rLen=0;
+reg							rFifoValid=0, _rFifoValid=0;
+reg							rDataValid=0, _rDataValid=0;
+
+
+assign BUF_DATA_REN = rRdState; // Not S_SGR128_RD_WAIT
+assign VALID = rCapState; // S_SGR128_CAP_RDY
+assign EMPTY = (BUF_DATA_EMPTY & rRdState); // Not S_SGR128_RD_WAIT
+assign ADDR = rAddr;
+assign LEN = rLen;
+
+
+// Capture address and length as it comes out of the FIFO
+always @ (posedge CLK) begin
+	rRdState <= #1 (RST ? `S_SGR128_RD_0 : _rRdState);
+	rCapState <= #1 (RST ? `S_SGR128_CAP_0 : _rCapState);
+	rData <= #1 _rData;
+	rFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);
+	rDataValid <= #1 (RST ? 1'd0 : _rDataValid);
+	rAddr <= #1 _rAddr;
+	rLen <= #1 _rLen;
+end
+
+always @ (*) begin
+	_rRdState = rRdState;
+	_rCapState = rCapState;
+	_rAddr = rAddr;
+	_rLen = rLen;
+	_rData = BUF_DATA;
+	_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);
+	_rDataValid = rFifoValid;
+
+	case (rCapState)
+	
+	`S_SGR128_CAP_0: begin
+		if (rDataValid) begin
+			_rAddr = rData[63:0];
+			_rLen = rData[95:64];
+			_rCapState = `S_SGR128_CAP_RDY;
+		end
+	end
+
+	`S_SGR128_CAP_RDY: begin
+		if (REN)
+			_rCapState = `S_SGR128_CAP_0;
+	end
+	
+	endcase
+
+	case (rRdState)
+
+	`S_SGR128_RD_0: begin // Read from the sg data FIFO
+		if (!BUF_DATA_EMPTY)
+			_rRdState = `S_SGR128_RD_WAIT;
+	end
+
+	`S_SGR128_RD_WAIT: begin // Wait for the data to be consumed
+		if (REN)
+			_rRdState = `S_SGR128_RD_0;
+	end
+	
+	endcase
+end
+
+endmodule
diff --git a/fpga/riffa_hdl/sg_list_reader_32.v b/fpga/riffa_hdl/sg_list_reader_32.v
new file mode 100644
index 0000000..425968d
--- /dev/null
+++ b/fpga/riffa_hdl/sg_list_reader_32.v
@@ -0,0 +1,188 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			sg_list_reader_32.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Reads data from the scatter gather list buffer.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`define S_SGR32_RD_0		3'b000
+`define S_SGR32_RD_1		3'b001
+`define S_SGR32_RD_2		3'b010
+`define S_SGR32_RD_3		3'b011
+`define S_SGR32_RD_WAIT		3'b100
+
+`define S_SGR32_CAP_0		3'b000
+`define S_SGR32_CAP_1		3'b001
+`define S_SGR32_CAP_2		3'b010
+`define S_SGR32_CAP_3		3'b011
+`define S_SGR32_CAP_RDY		3'b100
+
+`timescale 1ns/1ns
+module sg_list_reader_32 #(
+	parameter C_DATA_WIDTH = 9'd32
+)
+(
+	input CLK,
+	input RST,
+
+	input [C_DATA_WIDTH-1:0] BUF_DATA,	// Scatter gather buffer data 
+	input BUF_DATA_EMPTY,				// Scatter gather buffer data empty
+	output BUF_DATA_REN,				// Scatter gather buffer data read enable
+
+	output VALID,						// Scatter gather element data is valid
+	output EMPTY,						// Scatter gather elements empty
+	input REN,							// Scatter gather element data read enable
+	output [63:0] ADDR,					// Scatter gather element address
+	output [31:0] LEN					// Scatter gather element length (in words)
+);
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg		[2:0]				rRdState=`S_SGR32_RD_0, _rRdState=`S_SGR32_RD_0;
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg		[2:0]				rCapState=`S_SGR32_CAP_0, _rCapState=`S_SGR32_CAP_0;
+reg		[C_DATA_WIDTH-1:0]	rData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};
+reg		[63:0]				rAddr=64'd0, _rAddr=64'd0;
+reg		[31:0]				rLen=0, _rLen=0;
+reg							rFifoValid=0, _rFifoValid=0;
+reg							rDataValid=0, _rDataValid=0;
+
+
+assign BUF_DATA_REN = !rRdState[2]; // Not S_SGR32_RD_0
+assign VALID = rCapState[2]; // S_SGR32_CAP_RDY
+assign EMPTY = (BUF_DATA_EMPTY & !rRdState[2]); // Not S_SGR32_RD_0
+assign ADDR = rAddr;
+assign LEN = rLen;
+
+
+// Capture address and length as it comes out of the FIFO
+always @ (posedge CLK) begin
+	rRdState <= #1 (RST ? `S_SGR32_RD_0 : _rRdState);
+	rCapState <= #1 (RST ? `S_SGR32_CAP_0 : _rCapState);
+	rData <= #1 _rData;
+	rFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);
+	rDataValid <= #1 (RST ? 1'd0 : _rDataValid);
+	rAddr <= #1 _rAddr;
+	rLen <= #1 _rLen;
+end
+
+always @ (*) begin
+	_rRdState = rRdState;
+	_rCapState = rCapState;
+	_rAddr = rAddr;
+	_rLen = rLen;
+	_rData = BUF_DATA;
+	_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);
+	_rDataValid = rFifoValid;
+
+	case (rCapState)
+	
+	`S_SGR32_CAP_0: begin
+		if (rDataValid) begin
+			_rAddr[31:0] = rData;
+			_rCapState = `S_SGR32_CAP_1;
+		end
+	end
+
+	`S_SGR32_CAP_1: begin
+		if (rDataValid) begin
+			_rAddr[63:32] = rData;
+			_rCapState = `S_SGR32_CAP_2;
+		end
+	end
+	
+	`S_SGR32_CAP_2: begin
+		if (rDataValid) begin
+			_rLen = rData;
+			_rCapState = `S_SGR32_CAP_3;
+		end
+	end
+
+	`S_SGR32_CAP_3: begin
+		if (rDataValid)
+			_rCapState = `S_SGR32_CAP_RDY;
+	end
+
+	`S_SGR32_CAP_RDY: begin
+		if (REN)
+			_rCapState = `S_SGR32_CAP_0;
+	end
+
+	default: begin
+		_rCapState = `S_SGR32_CAP_0;
+	end
+	
+	endcase
+
+	case (rRdState)
+
+	`S_SGR32_RD_0: begin // Read from the sg data FIFO
+		if (!BUF_DATA_EMPTY)
+			_rRdState = `S_SGR32_RD_1;
+	end
+
+	`S_SGR32_RD_1: begin // Read from the sg data FIFO
+		if (!BUF_DATA_EMPTY)
+			_rRdState = `S_SGR32_RD_2;
+	end
+
+	`S_SGR32_RD_2: begin // Read from the sg data FIFO
+		if (!BUF_DATA_EMPTY)
+			_rRdState = `S_SGR32_RD_3;
+	end
+
+	`S_SGR32_RD_3: begin // Read from the sg data FIFO
+		if (!BUF_DATA_EMPTY)
+			_rRdState = `S_SGR32_RD_WAIT;
+	end
+
+	`S_SGR32_RD_WAIT: begin // Wait for the data to be consumed
+		if (REN)
+			_rRdState = `S_SGR32_RD_0;
+	end
+
+	default: begin
+		_rRdState = `S_SGR32_RD_0;
+	end
+	
+	endcase
+end
+
+endmodule
diff --git a/fpga/riffa_hdl/sg_list_reader_64.v b/fpga/riffa_hdl/sg_list_reader_64.v
new file mode 100644
index 0000000..af62b32
--- /dev/null
+++ b/fpga/riffa_hdl/sg_list_reader_64.v
@@ -0,0 +1,162 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			sg_list_reader_64.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Reads data from the scatter gather list buffer.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`define S_SGR64_RD_0		2'b01
+`define S_SGR64_RD_1		2'b11
+`define S_SGR64_RD_WAIT		2'b10
+
+`define S_SGR64_CAP_0		2'b00
+`define S_SGR64_CAP_1		2'b01
+`define S_SGR64_CAP_RDY		2'b10
+
+`timescale 1ns/1ns
+module sg_list_reader_64 #(
+	parameter C_DATA_WIDTH = 9'd64
+)
+(
+	input CLK,
+	input RST,
+
+	input [C_DATA_WIDTH-1:0] BUF_DATA,	// Scatter gather buffer data 
+	input BUF_DATA_EMPTY,				// Scatter gather buffer data empty
+	output BUF_DATA_REN,				// Scatter gather buffer data read enable
+
+	output VALID,						// Scatter gather element data is valid
+	output EMPTY,						// Scatter gather elements empty
+	input REN,							// Scatter gather element data read enable
+	output [63:0] ADDR,					// Scatter gather element address
+	output [31:0] LEN					// Scatter gather element length (in words)
+);
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg		[1:0]				rRdState=`S_SGR64_RD_0, _rRdState=`S_SGR64_RD_0;
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg		[1:0]				rCapState=`S_SGR64_CAP_0, _rCapState=`S_SGR64_CAP_0;
+reg		[C_DATA_WIDTH-1:0]	rData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};
+reg		[63:0]				rAddr=64'd0, _rAddr=64'd0;
+reg		[31:0]				rLen=0, _rLen=0;
+reg							rFifoValid=0, _rFifoValid=0;
+reg							rDataValid=0, _rDataValid=0;
+
+
+assign BUF_DATA_REN = rRdState[0]; // Not S_SGR64_RD_WAIT
+assign VALID = rCapState[1]; // S_SGR64_CAP_RDY
+assign EMPTY = (BUF_DATA_EMPTY & rRdState[0]); // Not S_SGR64_RD_WAIT
+assign ADDR = rAddr;
+assign LEN = rLen;
+
+
+// Capture address and length as it comes out of the FIFO
+always @ (posedge CLK) begin
+	rRdState <= #1 (RST ? `S_SGR64_RD_0 : _rRdState);
+	rCapState <= #1 (RST ? `S_SGR64_CAP_0 : _rCapState);
+	rData <= #1 _rData;
+	rFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);
+	rDataValid <= #1 (RST ? 1'd0 : _rDataValid);
+	rAddr <= #1 _rAddr;
+	rLen <= #1 _rLen;
+end
+
+always @ (*) begin
+	_rRdState = rRdState;
+	_rCapState = rCapState;
+	_rAddr = rAddr;
+	_rLen = rLen;
+	_rData = BUF_DATA;
+	_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);
+	_rDataValid = rFifoValid;
+
+	case (rCapState)
+	
+	`S_SGR64_CAP_0: begin
+		if (rDataValid) begin
+			_rAddr = rData;
+			_rCapState = `S_SGR64_CAP_1;
+		end
+	end
+	
+	`S_SGR64_CAP_1: begin
+		if (rDataValid) begin
+			_rLen = rData[31:0];
+			_rCapState = `S_SGR64_CAP_RDY;
+		end
+	end
+
+	`S_SGR64_CAP_RDY: begin
+		if (REN)
+			_rCapState = `S_SGR64_CAP_0;
+	end
+
+	default: begin
+		_rCapState = `S_SGR64_CAP_0;
+	end
+	
+	endcase
+
+	case (rRdState)
+
+	`S_SGR64_RD_0: begin // Read from the sg data FIFO
+		if (!BUF_DATA_EMPTY)
+			_rRdState = `S_SGR64_RD_1;
+	end
+
+	`S_SGR64_RD_1: begin // Read from the sg data FIFO
+		if (!BUF_DATA_EMPTY)
+			_rRdState = `S_SGR64_RD_WAIT;
+	end
+
+	`S_SGR64_RD_WAIT: begin // Wait for the data to be consumed
+		if (REN)
+			_rRdState = `S_SGR64_RD_0;
+	end
+
+	default: begin
+		_rRdState = `S_SGR64_RD_0;
+	end
+	
+	endcase
+end
+
+endmodule
diff --git a/fpga/riffa_hdl/sg_list_requester.v b/fpga/riffa_hdl/sg_list_requester.v
new file mode 100644
index 0000000..54e24b3
--- /dev/null
+++ b/fpga/riffa_hdl/sg_list_requester.v
@@ -0,0 +1,272 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			sg_list_requester.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Receives scatter gather address/length info and requests
+// the scatter gather data from the RX engine. Monitors the state of the scatter
+// gather FIFO to make sure it can accommodate the requested data. Also signals
+// when the entire scatter gather data has been received so the buffer can be
+// overwritten with new data.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`define S_SGREQ_IDLE	8'b0000_0001
+`define S_SGREQ_WAIT_0	8'b0000_0010
+`define S_SGREQ_WAIT_1	8'b0000_0100
+`define S_SGREQ_CHECK	8'b0000_1000
+`define S_SGREQ_ISSUE	8'b0001_0000
+`define S_SGREQ_UPDATE	8'b0010_0000
+`define S_SGREQ_COUNT	8'b0100_0000
+`define S_SGREQ_FLUSH	8'b1000_0000
+
+`timescale 1ns/1ns
+module sg_list_requester #(
+	parameter C_FIFO_DATA_WIDTH = 9'd64,
+	parameter C_FIFO_DEPTH = 1024,
+	parameter C_MAX_READ_REQ = 2,				// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+	// Local parameters
+	parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
+	parameter C_WORDS_PER_ELEM = 4,
+	parameter C_MAX_ELEMS = 200,
+	parameter C_MAX_ENTRIES = (C_MAX_ELEMS*C_WORDS_PER_ELEM),
+	parameter C_FIFO_COUNT_THRESH = C_FIFO_DEPTH - C_MAX_ENTRIES
+)
+(
+	input CLK,
+	input RST,
+	input [2:0] CONFIG_MAX_READ_REQUEST_SIZE,			// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+
+	input USER_RST,								// User reset, should clear FIFO data too
+	
+	output BUF_RECVD,							// Signals when scatter gather buffer received
+	input [31:0] BUF_DATA,						// Buffer data
+	input BUF_LEN_VALID,						// Buffer length valid
+	input BUF_ADDR_HI_VALID,					// Buffer high address valid
+	input BUF_ADDR_LO_VALID,					// Buffer low address valid
+
+	input [C_FIFO_DEPTH_WIDTH-1:0] FIFO_COUNT,	// Scatter gather FIFO count
+	output FIFO_FLUSH,							// Scatter gather FIFO flush request
+	input FIFO_FLUSHED,							// Scatter gather FIFO flushed
+	output FIFO_RST,							// Scatter gather FIFO data reset request
+
+	output RX_REQ,								// Issue a read request
+	output [63:0] RX_ADDR,						// Request address
+	output [9:0] RX_LEN,						// Request length
+	input RX_REQ_ACK,							// Request has been issued
+	input RX_DONE								// Request has completed (data received)
+);
+
+`include "functions.vh"
+
+reg		[31:0]			rData=0, _rData=0;
+reg						rAddrHiValid=0, _rAddrHiValid=0;
+reg						rAddrLoValid=0, _rAddrLoValid=0;
+reg						rLenValid=0, _rLenValid=0;
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg		[7:0]			rState=`S_SGREQ_IDLE, _rState=`S_SGREQ_IDLE;
+reg						rDone=0, _rDone=0;
+reg						rDelay=0, _rDelay=0;
+reg		[2:0]			rCarry=0, _rCarry=0;
+reg		[3:0]			rValsProp=0, _rValsProp=0;
+reg		[63:0]			rAddr=64'd0, _rAddr=64'd0;
+reg		[31:0]			rBufWords=0, _rBufWords=0;
+reg		[10:0]			rPageRem=0, _rPageRem=0;
+reg						rPageSpill=0, _rPageSpill=0;
+reg		[10:0]			rPreLen=0, _rPreLen=0;
+reg		[2:0]			rMaxPayloadTrain=0, _rMaxPayloadTrain=0;
+reg		[2:0]			rMaxPayloadShift=0, _rMaxPayloadShift=0;
+reg		[9:0]			rMaxPayload=0, _rMaxPayload=0;
+reg						rPayloadSpill=0, _rPayloadSpill=0;
+reg		[9:0]			rLen=0, _rLen=0;
+reg						rBufWordsEQ0Hi=0, _rBufWordsEQ0Hi=0;
+reg						rBufWordsEQ0Lo=0, _rBufWordsEQ0Lo=0;
+reg						rUserRst=0, _rUserRst=0;
+
+reg						rRecvdAll=0, _rRecvdAll=0;
+reg		[10:0]			rAckCount=0, _rAckCount=0;
+
+
+assign BUF_RECVD = rDone;
+
+assign FIFO_FLUSH = rState[7]; // S_SGREQ_FLUSH
+assign FIFO_RST = (rUserRst & rState[0]); // S_SGREQ_IDLE
+
+assign RX_ADDR = rAddr;
+assign RX_LEN = rLen;
+assign RX_REQ = rState[4]; // S_SGREQ_ISSUE
+
+
+// Buffer signals coming from outside the rx_port.
+always @ (posedge CLK) begin
+	rData <= #1 _rData;
+	rAddrHiValid <= #1 _rAddrHiValid;
+	rAddrLoValid <= #1 _rAddrLoValid;
+	rLenValid <= #1 _rLenValid;
+end
+
+always @ (*) begin
+	_rData = BUF_DATA;
+	_rAddrHiValid = BUF_ADDR_HI_VALID;
+	_rAddrLoValid = BUF_ADDR_LO_VALID;
+	_rLenValid = BUF_LEN_VALID;
+end
+
+
+// Handle requesting the next scatter gather buffer data.
+wire [9:0] wAddrLoInv = ~rAddr[11:2];
+always @ (posedge CLK) begin
+	rState <= #1 (RST ? `S_SGREQ_IDLE : _rState);
+	rDone <= #1 (RST ? 1'd0 : _rDone);
+	rDelay <= #1 _rDelay;
+	rAddr <= #1 _rAddr;
+	rCarry <= #1 _rCarry;
+	rBufWords <= #1 _rBufWords;
+	rValsProp <= #1 _rValsProp;
+	rPageRem <= #1 _rPageRem;
+	rPageSpill <= #1 _rPageSpill;
+	rPreLen <= #1 _rPreLen;
+	rMaxPayloadTrain <= #1 _rMaxPayloadTrain;
+	rMaxPayloadShift <= #1 _rMaxPayloadShift;
+	rMaxPayload <= #1 _rMaxPayload;
+	rPayloadSpill <= #1 _rPayloadSpill;
+	rLen <= #1 _rLen;
+	rBufWordsEQ0Hi <= #1 _rBufWordsEQ0Hi;
+	rBufWordsEQ0Lo <= #1 _rBufWordsEQ0Lo;
+	rUserRst <= #1 (RST ? 1'd0 : _rUserRst);
+end
+
+always @ (*) begin
+	_rState = rState;
+	_rDone = rDone;
+	_rDelay = rDelay;
+
+	_rUserRst = ((rUserRst & !rState[0]) | USER_RST);
+	_rValsProp = ((rValsProp<<1) | RX_REQ_ACK);
+	{_rCarry[0], _rAddr[15:0]} = (rAddrLoValid ? rData[15:0] : (rAddr[15:0] + ({12{RX_REQ_ACK}} & {2'b0,rLen}<<2)));
+	{_rCarry[1], _rAddr[31:16]} = (rAddrLoValid ? rData[31:16] : (rAddr[31:16] + rCarry[0]));
+	{_rCarry[2], _rAddr[47:32]} = (rAddrHiValid ? rData[15:0] : (rAddr[47:32] + rCarry[1]));
+				 _rAddr[63:48] = (rAddrHiValid ? rData[31:16] : (rAddr[63:48] + rCarry[2]));
+	_rBufWords = (rLenValid ? rData : rBufWords) - ({10{RX_REQ_ACK}} & rLen);
+	_rPageRem = (wAddrLoInv + 1'd1);	
+	_rPageSpill = (rBufWords > rPageRem);	
+	_rPreLen = (rPageSpill ? rPageRem : rBufWords[10:0]);			
+	_rMaxPayloadTrain = (CONFIG_MAX_READ_REQUEST_SIZE > 3'd4 ? 3'd4 : CONFIG_MAX_READ_REQUEST_SIZE);
+	_rMaxPayloadShift = (C_MAX_READ_REQ[2:0] < rMaxPayloadTrain ? C_MAX_READ_REQ[2:0] : rMaxPayloadTrain);
+	_rMaxPayload = (6'd32<<rMaxPayloadShift);
+	_rPayloadSpill = (rPreLen > rMaxPayload);
+	_rLen = (rPayloadSpill ? rMaxPayload : rPreLen[9:0]);
+	_rBufWordsEQ0Hi = (16'd0 == rBufWords[31:16]);
+	_rBufWordsEQ0Lo = (16'd0 == rBufWords[15:0]);
+
+	case (rState)
+
+	`S_SGREQ_IDLE: begin // Wait for addr & length
+		_rDone = 0;
+		if (rLenValid)
+			_rState = `S_SGREQ_WAIT_0;
+	end
+
+	`S_SGREQ_WAIT_0: begin // Wait 1 cycle for values to propagate
+		_rDelay = 0;
+		_rState = `S_SGREQ_WAIT_1;
+	end
+
+	`S_SGREQ_WAIT_1: begin // Wait 2 cycles for values to propagate
+		_rDelay = 1;
+		if (rDelay)
+			_rState = `S_SGREQ_CHECK;
+	end
+
+	`S_SGREQ_CHECK: begin // Wait for space to be made available
+		if (FIFO_COUNT < C_FIFO_COUNT_THRESH)
+			_rState = `S_SGREQ_ISSUE;
+		else if (rUserRst)
+			_rState = `S_SGREQ_COUNT;
+	end
+	
+	`S_SGREQ_ISSUE: begin // Wait for read request to be serviced
+		if (RX_REQ_ACK)
+			_rState = `S_SGREQ_UPDATE;
+	end
+
+	`S_SGREQ_UPDATE: begin // Update the address and length
+		if (rUserRst | (rBufWordsEQ0Hi & rBufWordsEQ0Lo))
+			_rState = `S_SGREQ_COUNT;
+		else if (rValsProp[3])
+			_rState = `S_SGREQ_ISSUE;
+	end
+
+	`S_SGREQ_COUNT: begin // Wait for read data to arrive
+		if (rRecvdAll)
+			_rState = `S_SGREQ_FLUSH;
+	end
+
+	`S_SGREQ_FLUSH: begin // Wait for read data to arrive
+		if (FIFO_FLUSHED) begin
+			_rDone = !rUserRst;
+			_rState = `S_SGREQ_IDLE;
+		end
+	end
+
+	default: begin
+		_rState = `S_SGREQ_IDLE;
+	end
+
+	endcase
+end
+
+
+// Keep track of requests made and requests completed so we know when all
+// the outstanding data has been received.
+always @ (posedge CLK) begin
+	rAckCount <= #1 (RST ? 10'd0 : _rAckCount);
+	rRecvdAll <= #1 _rRecvdAll;
+end
+
+always @ (*) begin
+	// Track REQ_DONE and SG_DONE to maintain an outstanding request count.
+	_rRecvdAll = (rAckCount == 10'd0);
+	if (rState[0]) // S_SGREQ_IDLE
+		_rAckCount = 0;
+	else
+		_rAckCount = rAckCount + RX_REQ_ACK - RX_DONE; 
+end
+
+
+endmodule
diff --git a/fpga/riffa_hdl/shiftreg.v b/fpga/riffa_hdl/shiftreg.v
new file mode 100644
index 0000000..c3615e8
--- /dev/null
+++ b/fpga/riffa_hdl/shiftreg.v
@@ -0,0 +1,83 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+/*
+ Filename: shiftreg.v
+ Version: 1.0
+ Verilog Standard: Verilog-2001
+
+ Description: A simple parameterized shift register. 
+ 
+ Notes: Any modifications to this file should meet the conditions set
+ forth in the "Trellis Style Guide"
+ 
+ Author: Dustin Richmond (@darichmond) 
+ Co-Authors:
+ */
+`timescale 1ns/1ns
+module shiftreg
+    #(
+      parameter C_DEPTH=10,
+      parameter C_WIDTH=32
+      )
+    (
+     input                            CLK,
+     input                            RST_IN,
+     input [C_WIDTH-1:0]              WR_DATA,
+     output [(C_DEPTH+1)*C_WIDTH-1:0] RD_DATA
+     );
+
+    // Start Flag Shift Register. Data enables are derived from the 
+    // taps on this shift register.
+
+    wire [(C_DEPTH+1)*C_WIDTH-1:0]    wDataShift;
+    reg [C_WIDTH-1:0]                 rDataShift[C_DEPTH:0];
+
+    assign wDataShift[(C_WIDTH*0)+:C_WIDTH] = WR_DATA;
+    always @(posedge CLK) begin
+        rDataShift[0] <= WR_DATA;
+    end
+    
+    genvar                                     i;
+    generate
+        for (i = 1 ; i <= C_DEPTH; i = i + 1) begin : gen_sr_registers
+            assign wDataShift[(C_WIDTH*i)+:C_WIDTH] = rDataShift[i-1];
+            always @(posedge CLK) begin
+                rDataShift[i] <= rDataShift[i-1];
+            end
+        end
+    endgenerate
+    assign RD_DATA = wDataShift;
+    
+endmodule
diff --git a/fpga/riffa_hdl/sync_fifo.v b/fpga/riffa_hdl/sync_fifo.v
new file mode 100644
index 0000000..9081ec4
--- /dev/null
+++ b/fpga/riffa_hdl/sync_fifo.v
@@ -0,0 +1,186 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			sync_fifo.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			A synchronous capable parameterized FIFO. As with all
+// traditional FIFOs, the RD_DATA will be valid one cycle following a RD_EN 
+// assertion. EMPTY will remain low until the cycle following the last RD_EN 
+// assertion. Note, that EMPTY may actually be high on the same cycle that 
+// RD_DATA contains valid data.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+module sync_fifo #(
+	parameter C_WIDTH = 32,	// Data bus width
+	parameter C_DEPTH = 1024,	// Depth of the FIFO
+	parameter C_PROVIDE_COUNT = 0, // Include code for counts
+	// Local parameters
+	parameter C_REAL_DEPTH = 2**clog2(C_DEPTH),
+	parameter C_DEPTH_BITS = clog2s(C_REAL_DEPTH),
+	parameter C_DEPTH_P1_BITS = clog2s(C_REAL_DEPTH+1)
+)
+(
+	input CLK,								// Clock
+	input RST, 								// Sync reset, active high
+	input [C_WIDTH-1:0] WR_DATA, 			// Write data input
+	input WR_EN, 							// Write enable, high active
+	output [C_WIDTH-1:0] RD_DATA, 			// Read data output
+	input RD_EN,							// Read enable, high active
+	output FULL, 							// Full condition
+	output EMPTY, 							// Empty condition
+	output [C_DEPTH_P1_BITS-1:0] COUNT		// Data count
+);
+
+`include "functions.vh"
+
+reg		[C_DEPTH_BITS:0]	rWrPtr=0, _rWrPtr=0;
+reg		[C_DEPTH_BITS:0]	rWrPtrPlus1=1, _rWrPtrPlus1=1;
+reg		[C_DEPTH_BITS:0]	rRdPtr=0, _rRdPtr=0;
+reg		[C_DEPTH_BITS:0]	rRdPtrPlus1=1, _rRdPtrPlus1=1;
+reg							rFull=0, _rFull=0;
+reg							rEmpty=1, _rEmpty=1;
+
+// Memory block (synthesis attributes applied to this module will
+// determine the memory option).
+ram_1clk_1w_1r #(.C_RAM_WIDTH(C_WIDTH), .C_RAM_DEPTH(C_REAL_DEPTH)) mem (
+	.CLK(CLK),
+	.ADDRA(rWrPtr[C_DEPTH_BITS-1:0]),
+	.WEA(WR_EN & !rFull),
+	.DINA(WR_DATA),
+	.ADDRB(rRdPtr[C_DEPTH_BITS-1:0]),
+	.DOUTB(RD_DATA)
+);
+
+
+// Write pointer logic.
+always @ (posedge CLK) begin
+	if (RST) begin
+		rWrPtr <= #1 0;
+		rWrPtrPlus1 <= #1 1;
+	end
+	else begin
+		rWrPtr <= #1 _rWrPtr;
+		rWrPtrPlus1 <= #1 _rWrPtrPlus1;
+	end
+end
+
+always @ (*) begin
+	if (WR_EN & !rFull) begin
+		_rWrPtr = rWrPtrPlus1;
+		_rWrPtrPlus1 = rWrPtrPlus1 + 1'd1;
+	end
+	else begin
+		_rWrPtr = rWrPtr;
+		_rWrPtrPlus1 = rWrPtrPlus1;
+	end
+end
+
+
+// Read pointer logic.
+always @ (posedge CLK) begin
+	if (RST) begin
+		rRdPtr <= #1 0;
+		rRdPtrPlus1 <= #1 1;
+	end
+	else begin
+		rRdPtr <= #1 _rRdPtr;
+		rRdPtrPlus1 <= #1 _rRdPtrPlus1;
+	end
+end
+
+always @ (*) begin
+	if (RD_EN & !rEmpty) begin
+		_rRdPtr = rRdPtrPlus1;
+		_rRdPtrPlus1 = rRdPtrPlus1 + 1'd1;
+	end
+	else begin
+		_rRdPtr = rRdPtr;
+		_rRdPtrPlus1 = rRdPtrPlus1;
+	end
+end
+
+
+// Calculate empty
+assign EMPTY = rEmpty;
+
+always @ (posedge CLK) begin
+	rEmpty <= #1 (RST ? 1'd1 : _rEmpty);
+end
+
+always @ (*) begin
+	_rEmpty = (rWrPtr == rRdPtr) || (RD_EN && !rEmpty && (rWrPtr == rRdPtrPlus1));
+end
+
+
+// Calculate full
+assign FULL = rFull;
+
+always @ (posedge CLK) begin
+	rFull <= #1 (RST ? 1'd0 : _rFull);
+end
+
+always @ (*) begin
+	_rFull = ((rWrPtr[C_DEPTH_BITS-1:0] == rRdPtr[C_DEPTH_BITS-1:0]) && (rWrPtr[C_DEPTH_BITS] != rRdPtr[C_DEPTH_BITS])) ||
+	(WR_EN && (rWrPtrPlus1[C_DEPTH_BITS-1:0] == rRdPtr[C_DEPTH_BITS-1:0]) && (rWrPtrPlus1[C_DEPTH_BITS] != rRdPtr[C_DEPTH_BITS]));
+end
+
+generate
+if (C_PROVIDE_COUNT) begin: provide_count
+	reg [C_DEPTH_BITS:0] rCount=0, _rCount=0;
+
+	assign COUNT = (rFull ? C_REAL_DEPTH[C_DEPTH_P1_BITS-1:0] : rCount);
+
+	// Calculate read count
+	always @ (posedge CLK) begin
+		if (RST)
+			rCount <= #1 0;
+		else
+			rCount <= #1 _rCount;
+	end
+
+	always @ (*) begin
+		_rCount = (rWrPtr - rRdPtr);
+	end
+end
+else begin: provide_no_count
+	assign COUNT = 0;
+end 
+endgenerate
+ 
+endmodule
+ 
diff --git a/fpga/riffa_hdl/syncff.v b/fpga/riffa_hdl/syncff.v
new file mode 100644
index 0000000..1f41b85
--- /dev/null
+++ b/fpga/riffa_hdl/syncff.v
@@ -0,0 +1,66 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			syncff.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			A back to back FF design to mitigate metastable issues 
+// 						when crossing clock domains.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+module syncff
+    (
+     input  CLK,
+     input  IN_ASYNC,
+     output OUT_SYNC
+     );
+    wire    wSyncFFQ;
+
+    ff 
+        syncFF 
+            (
+             .CLK(CLK),
+	         .D(IN_ASYNC),
+	         .Q(wSyncFFQ)
+             );
+
+    ff metaFF (
+	           .CLK(CLK),
+	           .D(wSyncFFQ),
+	           .Q(OUT_SYNC)
+               );
+endmodule
diff --git a/fpga/riffa_hdl/tlp.vh b/fpga/riffa_hdl/tlp.vh
new file mode 100644
index 0000000..a9c8a62
--- /dev/null
+++ b/fpga/riffa_hdl/tlp.vh
@@ -0,0 +1,250 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            tlp.vh
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The tlp.vh file is a header file that defines various
+// TLP specific primitives for the Xilinx and Altera "Classic" endpoints
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`ifndef __TLP_VH
+`define __TLP_VH 1
+`include "widths.vh"
+`include "types.vh"
+
+`define TLP_MAXHDR_W 128
+
+// Generic 1'st word TLP header widths & indices
+`define TLP_LEN_I 0
+`define TLP_LEN_W `LEN_W
+`define TLP_LEN_R `TLP_LEN_I +: `TLP_LEN_W 
+
+`define TLP_ADDRTYPE_I 10
+`define TLP_ADDRTYPE_W 2
+`define TLP_ADDRTYPE_R `TLP_ADDRTYPE_I +: `TLP_ADDRTYPE_W
+
+`define TLP_ATTR0_I 12
+`define TLP_ATTR0_W 2
+`define TLP_ATTR0_R `TLP_ATTR0_I +: `TLP_ATTR0_W 
+
+`define TLP_EP_I 14
+`define TLP_EP_W `EP_W
+`define TLP_EP_R `TLP_EP_I +: `TLP_EP_W 
+
+`define TLP_TD_I 15
+`define TLP_TD_W `TD_W
+`define TLP_TD_R `TLP_TD_I +: `TLP_TD_W 
+
+`define TLP_TH_I 16
+`define TLP_TH_W 1
+`define TLP_TH_R `TLP_TH_I +: `TLP_TH_W 
+
+// Bit 17 is reserved
+`define TLP_RSVD0_I 17
+`define TLP_RSVD0_W 1
+`define TLP_RSVD0_R `TLP_RSVD0_I +: `TLP_RSVD0_W
+`define TLP_RSVD0_V `TLP_RSVD0_W'b0
+
+// There are two attr fields
+`define TLP_ATTR1_I 18
+`define TLP_ATTR1_W 1
+`define TLP_ATTR1_R `TLP_ATTR1_I +: `TLP_ATTR1_W 
+
+`define TLP_ATTR_W (`TLP_ATTR0_W + `TLP_ATTR1_W)
+
+// Bit 19 is reserved
+`define TLP_RSVD1_I 19
+`define TLP_RSVD1_W 1
+`define TLP_RSVD1_R `TLP_RSVD1_I +: `TLP_RSVD1_W
+`define TLP_RSVD1_V `TLP_RSVD1_W'b0
+
+`define TLP_TC_I 20
+`define TLP_TC_W `TC_W
+`define TLP_TC_R `TLP_TC_I +: `TLP_TC_W 
+
+// Bit 23 is reserved
+`define TLP_RSVD2_I 23
+`define TLP_RSVD2_W 1
+`define TLP_RSVD2_R `TLP_RSVD2_I +: `TLP_RSVD2_W
+`define TLP_RSVD2_V `TLP_RSVD2_W'b0
+
+`define TLP_TYPE_I 24
+`define TLP_TYPE_W `TYPE_W
+`define TLP_TYPE_R `TLP_TYPE_I +: `TLP_TYPE_W 
+
+`define TLP_FMT_I 29
+`define TLP_FMT_W `FMT_W
+`define TLP_FMT_R `TLP_FMT_I +: `TLP_FMT_W 
+
+`define TLP_4DWHBIT_I 29
+`define TLP_PAYBIT_I 30
+
+
+// Request specific fields
+`define TLP_REQMETADW0_I 0
+`define TLP_REQMETADW1_I 32
+`define TLP_REQADDRDW0_I 64
+`define TLP_REQADDRDW1_I 96
+
+`define TLP_REQFBE_I 32
+`define TLP_REQFBE_W `FBE_W
+`define TLP_REQFBE_R `TLP_REQFBE_I +: `TLP_REQFBE_W
+
+`define TLP_REQLBE_I 36
+`define TLP_REQLBE_W `LBE_W
+`define TLP_REQLBE_R `TLP_REQLBE_I +: `TLP_REQLBE_W
+
+`define TLP_REQTAG_I 40
+`define TLP_REQTAG_W `TAG_W
+`define TLP_REQTAG_R `TLP_REQTAG_I +: `TLP_REQTAG_W
+
+`define TLP_REQREQID_I 48
+`define TLP_REQREQID_W `REQID_W
+`define TLP_REQREQID_R `TLP_REQREQID_I +: `TLP_REQREQID_W
+
+`define TLP_REQADDRLO_I 64
+`define TLP_REQADDRLO_W 32
+`define TLP_REQADDRLO_R `TLP_REQADDRLO_I +: `TLP_REQADDRLO_W
+
+`define TLP_REQADDRHI_I 96
+`define TLP_REQADDRHI_W 32
+`define TLP_REQADDRHI_R `TLP_REQADDRHI_I +: `TLP_REQADDRHI_W
+
+`define TLP_REQADDR_W `ADDR_W
+
+// Completion specific fields
+`define TLP_CPLMETADW0_I 0
+`define TLP_CPLMETADW1_I 32
+`define TLP_CPLMETADW2_I 64
+`define TLP_CPLPAYLOAD_I 96
+`define TLP_CPLMDATA_I 95:0
+`define TLP_CPLHDR_W 96
+
+`define TLP_CPLBYTECNT_I 32
+`define TLP_CPLBYTECNT_W `BYTECNT_W
+`define TLP_CPLBYTECNT_R `TLP_CPLBYTECNT_I +: `TLP_CPLBYTECNT_W 
+
+`define TLP_CPLBCM_I 44
+`define TLP_CPLBCM_W 1
+`define TLP_CPLBCM_R `TLP_CPLBCM_I +: `TLP_CPLBCM_W 
+
+`define TLP_CPLSTAT_I 45
+`define TLP_CPLSTAT_W `STAT_W
+`define TLP_CPLSTAT_R `TLP_CPLSTAT_I +: `TLP_CPLSTAT_W
+
+`define TLP_CPLLEN_I 0
+`define TLP_CPLLEN_W `LEN_W
+`define TLP_CPLLEN_R `TLP_CPLLEN_I +: `TLP_CPLLEN_W
+
+`define TLP_CPLCPLID_I 48
+`define TLP_CPLCPLID_W `CPLID_W
+`define TLP_CPLCPLID_R `TLP_CPLCPLID_I +: `TLP_CPLCPLID_W
+
+`define TLP_CPLADDR_I 64
+`define TLP_CPLADDR_W `LOWADDR_W
+`define TLP_CPLADDR_R `TLP_CPLADDR_I +: `TLP_CPLADDR_W
+
+`define TLP_CPLRSVD0_I 71
+`define TLP_CPLRSVD0_W 1
+`define TLP_CPLRSVD0_R `TLP_CPLRSVD0_I +: `TLP_CPLRSVD0_W
+
+`define TLP_CPLTAG_I 72
+`define TLP_CPLTAG_W `TAG_W
+`define TLP_CPLTAG_R `TLP_CPLTAG_I +: `TLP_CPLTAG_W
+
+`define TLP_CPLREQID_I 80
+`define TLP_CPLREQID_W `REQID_W
+`define TLP_CPLREQID_R `TLP_CPLREQID_I +: `TLP_CPLREQID_W
+
+`define TLP_CPLFBE_W `FBE_W
+`define TLP_CPLLBE_W `LBE_W
+
+// Values
+`define TLP_4DWH_V 1'b1
+`define TLP_3DWH_V (~`TLP_4DWH_V)
+`define TLP_NODIGEST_V (`TLP_TD_W'b0)
+`define TLP_CPL_SUCCESSFUL_V `TLP_CPLSTAT_W'd0;
+
+// Decoding the format & Type field
+`define TLP_TYPE_REQ 5'b00000
+`define TLP_TYPE_CPL 5'b01010
+`define TLP_TYPE_MSG 5'b10001
+
+`define TLP_REQ_RD {{3'bx0x},`TLP_TYPE_REQ}
+`define TLP_REQ_WR {{3'bx1x},`TLP_TYPE_REQ}
+`define TLP_CPL_ND {{3'bx00},`TLP_TYPE_CPL}
+`define TLP_CPL_WD {{3'bx10},`TLP_TYPE_CPL}
+`define TLP_MSG_ND {{3'bx01},`TLP_TYPE_MSG}
+`define TLP_MSG_WD {{3'bx11},`TLP_TYPE_MSG}
+
+function [ `EXT_TYPE_W - 1 : 0 ] tlp_to_trellis_type;
+    input [`FMT_W + `TYPE_W - 1 : 0 ] tlp_type;
+    begin
+        /* verilator lint_off CASEX */
+        casex(tlp_type)
+            `TLP_REQ_RD: tlp_to_trellis_type = `TRLS_REQ_RD;
+            `TLP_REQ_WR: tlp_to_trellis_type = `TRLS_REQ_WR;
+            `TLP_CPL_ND: tlp_to_trellis_type = `TRLS_CPL_ND;
+            `TLP_CPL_WD: tlp_to_trellis_type = `TRLS_CPL_WD;
+            `TLP_MSG_ND: tlp_to_trellis_type = `TRLS_MSG_ND; // We only use messages routed by address
+            `TLP_MSG_WD: tlp_to_trellis_type = `TRLS_MSG_WD; // We only use messages routed by address
+            default:     tlp_to_trellis_type = `TRLS_REQ_RD;
+        endcase
+        /* verilator lint_on CASEX */
+   end
+endfunction // if
+
+function [`FMT_W + `TYPE_W - 1 : 0 ] trellis_to_tlp_type;
+    input  [`EXT_TYPE_W - 1 : 0 ]    trellis_type;
+    input                            hdrlen_wr;
+    reg [`FMT_W + `TYPE_W - 1 : 0 ]  temp;
+    begin
+        /* verilator lint_off CASEX */
+        casex(trellis_type)
+            `TRLS_REQ_RD: temp = `TLP_REQ_RD;
+            `TRLS_REQ_WR: temp = `TLP_REQ_WR;
+            `TRLS_CPL_ND: temp = `TLP_CPL_ND;
+            `TRLS_CPL_WD: temp = `TLP_CPL_WD;
+            `TRLS_MSG_ND: temp = `TLP_MSG_ND; // We only use messages routed by address
+            `TRLS_MSG_WD: temp = `TLP_MSG_WD; // We only use messages routed by address
+            default:      temp = `TLP_REQ_RD;
+        endcase
+        /* verilator lint_on CASEX */
+        trellis_to_tlp_type = {temp[`FMT_W +`TYPE_W - 1 : `TYPE_W + 1], hdrlen_wr, temp[`TYPE_W-1:0]};
+    end
+endfunction // if
+`endif
+
diff --git a/fpga/riffa_hdl/translation_altera.v b/fpga/riffa_hdl/translation_altera.v
new file mode 100644
index 0000000..0135eb0
--- /dev/null
+++ b/fpga/riffa_hdl/translation_altera.v
@@ -0,0 +1,230 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+/*
+ Filename: translation_layer.v
+ Version: 1.0
+ Verilog Standard: Verilog-2001
+
+ Description: The translation layer provides a uniform interface for all Altera 
+ PCIe interfaces
+ 
+ Notes: Any modifications to this file should meet the conditions set
+ forth in the "Trellis Style Guide"
+
+ Author: Dustin Richmond (@darichmond) 
+ Co-Authors:
+ */
+`include "trellis.vh" // Defines the user-facing signal widths.
+`include "altera.vh"
+module translation_altera
+    #(
+      parameter C_PCI_DATA_WIDTH = 128
+      )
+    (
+     input                          CLK,
+     input                          RST_IN,
+
+     // Interface: Altera RX 
+     input [C_PCI_DATA_WIDTH-1:0]   RX_ST_DATA,
+     input [0:0]                    RX_ST_EOP,
+     input [0:0]                    RX_ST_SOP,
+     input [0:0]                    RX_ST_VALID,
+     output                         RX_ST_READY,
+     input [0:0]                    RX_ST_EMPTY,
+
+     // Interface: Altera TX
+     output [C_PCI_DATA_WIDTH-1:0]  TX_ST_DATA,
+     output [0:0]                   TX_ST_VALID,
+     input                          TX_ST_READY,
+     output [0:0]                   TX_ST_EOP,
+     output [0:0]                   TX_ST_SOP,
+     output [0:0]                   TX_ST_EMPTY,
+
+     // Interface: Altera Config
+     input [`SIG_CFG_CTL_W-1:0]     TL_CFG_CTL,
+     input [`SIG_CFG_ADD_W-1:0]     TL_CFG_ADD,
+     input [`SIG_CFG_STS_W-1:0]     TL_CFG_STS,
+
+     // Interface: Altera Flow Control
+     input [`SIG_FC_CPLH_W-1:0]     KO_CPL_SPC_HEADER,
+     input [`SIG_FC_CPLD_W-1:0]     KO_CPL_SPC_DATA,
+    
+     // Interface: Altera Interrupt
+     input                          APP_MSI_ACK,
+     output                         APP_MSI_REQ,
+
+     // Interface: RX Classic
+     output [C_PCI_DATA_WIDTH-1:0]  RX_TLP,
+     output                         RX_TLP_VALID,
+     output                         RX_TLP_START_FLAG,
+     output [`SIG_OFFSET_W-1:0]     RX_TLP_START_OFFSET,
+     output                         RX_TLP_END_FLAG,
+     output [`SIG_OFFSET_W-1:0]     RX_TLP_END_OFFSET,
+     output [`SIG_BARDECODE_W-1:0]  RX_TLP_BAR_DECODE,
+     input                          RX_TLP_READY,
+
+     // Interface: TX Classic
+     output                         TX_TLP_READY,
+     input [C_PCI_DATA_WIDTH-1:0]   TX_TLP,
+     input                          TX_TLP_VALID,
+     input                          TX_TLP_START_FLAG,
+     input [`SIG_OFFSET_W-1:0]      TX_TLP_START_OFFSET,
+     input                          TX_TLP_END_FLAG,
+     input [`SIG_OFFSET_W-1:0]      TX_TLP_END_OFFSET,
+
+     // Interface: Configuration
+     output [`SIG_CPLID_W-1:0]      CONFIG_COMPLETER_ID,
+     output                         CONFIG_BUS_MASTER_ENABLE, 
+     output [`SIG_LINKWIDTH_W-1:0]  CONFIG_LINK_WIDTH,
+     output [`SIG_LINKRATE_W-1:0]   CONFIG_LINK_RATE,
+     output [`SIG_MAXREAD_W-1:0]    CONFIG_MAX_READ_REQUEST_SIZE, 
+     output [`SIG_MAXPAYLOAD_W-1:0] CONFIG_MAX_PAYLOAD_SIZE,
+     output                         CONFIG_INTERRUPT_MSIENABLE,
+     output                         CONFIG_CPL_BOUNDARY_SEL,
+     output [`SIG_FC_CPLD_W-1:0]    CONFIG_MAX_CPL_DATA, // Receive credit limit for data
+     output [`SIG_FC_CPLH_W-1:0]    CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
+
+     // Interface: Interrupt     
+     output                         INTR_MSI_RDY, // High when interrupt is able to be sent
+     input                          INTR_MSI_REQUEST // High to request interrupt
+     );
+    
+    localparam C_ALTERA_TX_READY_LATENCY = 1;// TODO: HMmmmmm 2?
+    localparam C_OFFSET_WIDTH  = clog2s(C_PCI_DATA_WIDTH/32);
+
+    reg [C_PCI_DATA_WIDTH-1:0]      rRxStData;
+    reg                             rRxStValid;
+    reg                             rRxStEop;
+    reg                             rRxStSop;
+
+    reg [`SIG_CFG_ADD_W-1:0]        rTlCfgAdd,_rTlCfgAdd;
+    reg [`SIG_CFG_CTL_W-1:0]        rTlCfgCtl,_rTlCfgCtl;
+    reg [`SIG_CFG_STS_W-1:0]        rTlCfgSts,_rTlCfgSts;
+
+    reg [`SIG_CPLID_W-1:0]          rCfgCompleterId;
+    reg                             rCfgBusMstrEnable;
+    reg [`SIG_MAXREAD_W-1:0]        rCfgMaxReadRequestSize;
+    reg [`SIG_MAXPAYLOAD_W-1:0]     rCfgMaxPayloadSize;
+    reg                             rCfgInterruptMsienable;
+    reg                             rReadCompletionBoundarySel;
+
+    reg [C_ALTERA_TX_READY_LATENCY-1:0] rTxStReady, _rTxStReady;
+
+    // Rx Interface (To PCIe Core)
+    assign RX_ST_READY = RX_TLP_READY;
+
+    // Rx Interface (From PCIe Core)
+    assign RX_TLP = RX_ST_DATA;
+    assign RX_TLP_VALID = RX_ST_VALID;
+    assign RX_TLP_END_FLAG = RX_ST_EOP;
+    assign RX_TLP_END_OFFSET = {3'b000,RX_ST_EMPTY};
+    assign RX_TLP_START_FLAG = RX_ST_SOP;
+    assign RX_TLP_START_OFFSET = 0;
+
+    // TX Interface (From PCIe Core)
+    assign TX_TLP_READY = rTxStReady[C_ALTERA_TX_READY_LATENCY-1];
+
+    // TX Interface (To PCIe Core)
+    assign TX_ST_DATA = TX_TLP;
+    assign TX_ST_VALID = TX_TLP_VALID & TX_TLP_READY;
+    assign TX_ST_EOP = TX_TLP_END_FLAG;
+    assign TX_ST_SOP = TX_TLP_START_FLAG;
+    
+    // Configuration Interface
+    assign CONFIG_COMPLETER_ID = rCfgCompleterId; 
+    assign CONFIG_BUS_MASTER_ENABLE = rCfgBusMstrEnable;
+    assign CONFIG_LINK_WIDTH = rTlCfgSts[`TLSTS_LWIDTH_R]; 
+    assign CONFIG_LINK_RATE = rTlCfgSts[`TLSTS_LRATE_R];
+    assign CONFIG_MAX_READ_REQUEST_SIZE = rCfgMaxReadRequestSize;
+    assign CONFIG_MAX_PAYLOAD_SIZE = rCfgMaxPayloadSize;
+    assign CONFIG_INTERRUPT_MSIENABLE = rCfgInterruptMsienable;
+    assign CONFIG_CPL_BOUNDARY_SEL = rReadCompletionBoundarySel;
+    assign CONFIG_MAX_CPL_HDR = KO_CPL_SPC_HEADER;
+    assign CONFIG_MAX_CPL_DATA = KO_CPL_SPC_DATA;
+
+    // Interrupt interface 
+    assign APP_MSI_REQ = INTR_MSI_REQUEST;
+    assign INTR_MSI_RDY = APP_MSI_ACK;
+
+    always @(*) begin
+        _rTxStReady = (rTxStReady << 1) | TX_ST_READY;
+    end
+
+    always @(posedge CLK) begin
+        rTxStReady <= _rTxStReady;
+    end
+
+    always @(*) begin
+        _rTlCfgCtl = TL_CFG_CTL;
+        _rTlCfgAdd = TL_CFG_ADD;
+        _rTlCfgSts = TL_CFG_STS;
+    end
+
+    always @(posedge CLK) begin // Should be the same clock as pld_clk
+        rTlCfgAdd <= _rTlCfgAdd;
+        rTlCfgCtl <= _rTlCfgCtl;
+        rTlCfgSts <= _rTlCfgSts;
+        
+        if(rTlCfgAdd == `TLCFG_DEVCTL_I) begin
+            rCfgMaxReadRequestSize <= rTlCfgCtl[`TLCTL_MAXREQ_R];
+            rCfgMaxPayloadSize <= rTlCfgCtl[`TLCTL_MAXPAY_R];
+        end
+        
+        if(rTlCfgAdd == `TLCFG_LNKCTL_I) begin
+            rReadCompletionBoundarySel <= rTlCfgCtl[`TLCTL_RCB_R];
+        end
+        if(rTlCfgAdd == `TLCFG_PRMCMD_I) begin
+            rCfgBusMstrEnable <= rTlCfgCtl[`TLCTL_BUSMSTR_R];
+        end
+        if(rTlCfgAdd == `TLCFG_MSICSR_I) begin
+            rCfgInterruptMsienable <= rTlCfgCtl[`TLCTL_MSIENABLE_R];
+        end
+        if(rTlCfgAdd == `TLCFG_BUSDEV_I) begin
+            rCfgCompleterId <= {rTlCfgCtl[`TLCTL_BUSDEV_R],3'b0};
+        end
+    end // always @ (posedge CLK)
+    generate
+        if (C_PCI_DATA_WIDTH == 9'd32) begin : a32
+            // Not possible...
+        end else if (C_PCI_DATA_WIDTH == 9'd64) begin : a64
+            assign TX_ST_EMPTY = 0;
+        end else if (C_PCI_DATA_WIDTH == 9'd128) begin : a128
+            assign TX_ST_EMPTY = ~TX_TLP_END_OFFSET[1] & TX_ST_EOP;
+        end else if (C_PCI_DATA_WIDTH == 9'd256) begin : a256
+            assign TX_ST_EMPTY = TX_TLP_END_OFFSET[2];
+        end
+    endgenerate
+endmodule // translation_layer
+
diff --git a/fpga/riffa_hdl/translation_xilinx.v b/fpga/riffa_hdl/translation_xilinx.v
new file mode 100644
index 0000000..4304781
--- /dev/null
+++ b/fpga/riffa_hdl/translation_xilinx.v
@@ -0,0 +1,228 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+/*
+ Filename: translation_layer.v
+ Version: 1.0
+ Verilog Standard: Verilog-2001
+
+ Description: The translation layer provides a uniform interface for all classic
+ PCIe interfaces, such as all Altera devices, and all Xilinx devices (pre VC709).
+ 
+ Notes: Any modifications to this file should meet the conditions set
+ forth in the "Trellis Style Guide"
+
+ Author: Dustin Richmond (@darichmond) 
+ Co-Authors:
+ */
+`include "trellis.vh" // Defines the user-facing signal widths.
+`include "xilinx.vh"
+module translation_xilinx
+    #(
+      parameter C_PCI_DATA_WIDTH = 256
+      )
+    (
+     input                                    CLK,
+     input                                    RST_IN,
+
+     // Interface: Xilinx RX 
+     input [C_PCI_DATA_WIDTH-1:0]             M_AXIS_RX_TDATA,
+     input [(C_PCI_DATA_WIDTH/8)-1:0]         M_AXIS_RX_TKEEP,
+     input                                    M_AXIS_RX_TLAST,
+     input                                    M_AXIS_RX_TVALID,
+     output                                   M_AXIS_RX_TREADY,
+     input [`SIG_XIL_RX_TUSER_W-1:0]          M_AXIS_RX_TUSER,
+     output                                   RX_NP_OK,
+     output                                   RX_NP_REQ,
+
+     // Interface: Xilinx TX
+     output [C_PCI_DATA_WIDTH-1:0]            S_AXIS_TX_TDATA,
+     output [(C_PCI_DATA_WIDTH/8)-1:0]        S_AXIS_TX_TKEEP,
+     output                                   S_AXIS_TX_TLAST,
+     output                                   S_AXIS_TX_TVALID,
+     input                                    S_AXIS_TX_TREADY,
+     output [`SIG_XIL_TX_TUSER_W-1:0]         S_AXIS_TX_TUSER,
+     output                                   TX_CFG_GNT,
+
+     // Interface: Xilinx Configuration 
+     input [`SIG_BUSID_W-1:0]                 CFG_BUS_NUMBER,
+     input [`SIG_DEVID_W-1:0]                 CFG_DEVICE_NUMBER,
+     input [`SIG_FNID_W-1:0]                  CFG_FUNCTION_NUMBER,
+     input [`SIG_CFGREG_W-1:0]                CFG_COMMAND,
+     input [`SIG_CFGREG_W-1:0]                CFG_DCOMMAND,
+     input [`SIG_CFGREG_W-1:0]                CFG_LSTATUS,
+     input [`SIG_CFGREG_W-1:0]                CFG_LCOMMAND,
+
+     // Interface: Xilinx Flow Control
+     input [`SIG_FC_CPLD_W-1:0]               FC_CPLD,
+     input [`SIG_FC_CPLH_W-1:0]               FC_CPLH,
+     output [`SIG_FC_SEL_W-1:0]               FC_SEL,
+    
+     // Interface: Xilinx Interrupt
+     input                                    CFG_INTERRUPT_MSIEN,
+     input                                    CFG_INTERRUPT_RDY,
+     output                                   CFG_INTERRUPT,
+    
+     // Interface: RX Classic
+     output [C_PCI_DATA_WIDTH-1:0]            RX_TLP,
+     output                                   RX_TLP_VALID,
+     output                                   RX_TLP_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RX_TLP_START_OFFSET,
+     output                                   RX_TLP_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RX_TLP_END_OFFSET,
+     output [`SIG_BARDECODE_W-1:0]            RX_TLP_BAR_DECODE,
+     input                                    RX_TLP_READY,
+
+     // Interface: TX Classic
+     output                                   TX_TLP_READY,
+     input [C_PCI_DATA_WIDTH-1:0]             TX_TLP,
+     input                                    TX_TLP_VALID,
+     input                                    TX_TLP_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TX_TLP_START_OFFSET,
+     input                                    TX_TLP_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TX_TLP_END_OFFSET,
+
+     // Interface: Configuration
+     output [`SIG_CPLID_W-1:0]                CONFIG_COMPLETER_ID,
+     output                                   CONFIG_BUS_MASTER_ENABLE, 
+     output [`SIG_LINKWIDTH_W-1:0]            CONFIG_LINK_WIDTH,
+     output [`SIG_LINKRATE_W-1:0]             CONFIG_LINK_RATE,
+     output [`SIG_MAXREAD_W-1:0]              CONFIG_MAX_READ_REQUEST_SIZE, 
+     output [`SIG_MAXPAYLOAD_W-1:0]           CONFIG_MAX_PAYLOAD_SIZE,
+     output                                   CONFIG_INTERRUPT_MSIENABLE,
+     output                                   CONFIG_CPL_BOUNDARY_SEL,
+
+     // Interface: Flow Control
+     output [`SIG_FC_CPLD_W-1:0]              CONFIG_MAX_CPL_DATA,
+     output [`SIG_FC_CPLH_W-1:0]              CONFIG_MAX_CPL_HDR,
+
+     // Interface: Interrupt     
+     output                                   INTR_MSI_RDY, // High when interrupt is able to be sent
+     input                                    INTR_MSI_REQUEST // High to request interrupt
+     );
+    /* 
+     Notes on the Configuration Interface:
+     Link Width (cfg_lstatus[9:4]): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16
+     Link Rate (cfg_lstatus[3:0]): 0001=2.5GT/s, 0010=5.0GT/s, 0011=8.0GT/s
+     Max Read Request Size (cfg_dcommand[14:12]): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
+     Max Payload Size (cfg_dcommand[7:5]): 000=128B, 001=256B, 010=512B, 011=1024B
+     Bus Master Enable (cfg_command[2]): 1=Enabled, 0=Disabled
+     Read Completion Boundary (cfg_lcommand[3]): 0=64 bytes, 1=128 bytes
+     MSI Enable (cfg_msicsr[0]): 1=Enabled, 0=Disabled
+     
+     Notes on the Flow Control Interface:
+     FC_CPLD (Xilinx) Receive credit limit for data 
+     FC_CPLH (Xilinx) Receive credit limit for headers 
+     FC_SEL (Xilinx Only) Selects the correct output on the FC_* signals
+
+     Notes on the TX Interface:
+     TX_CFG_GNT (Xilinx): 1=Always allow core to transmit internally generated TLPs
+     
+     Notes on the RX Interface:
+     RX_NP_OK (Xilinx): 1=Always allow non posted transactions
+     */
+    
+    /*AUTOWIRE*/
+
+    reg rRxTlpValid;
+    reg rRxTlpEndFlag;
+
+    // Rx Interface (From PCIe Core)
+    assign RX_TLP = M_AXIS_RX_TDATA;
+    assign RX_TLP_VALID = M_AXIS_RX_TVALID;
+
+    // Rx Interface (To PCIe Core)
+    assign M_AXIS_RX_TREADY =  RX_TLP_READY;
+
+    // TX Interface (From PCIe Core)
+    assign TX_TLP_READY = S_AXIS_TX_TREADY;
+
+    // TX Interface (TO PCIe Core)
+    assign S_AXIS_TX_TDATA = TX_TLP;
+    assign S_AXIS_TX_TVALID = TX_TLP_VALID;
+    assign S_AXIS_TX_TLAST = TX_TLP_END_FLAG;
+
+    // Configuration Interface
+    assign CONFIG_COMPLETER_ID = {CFG_BUS_NUMBER,CFG_DEVICE_NUMBER,CFG_FUNCTION_NUMBER};
+    assign CONFIG_BUS_MASTER_ENABLE = CFG_COMMAND[`CFG_COMMAND_BUSMSTR_R];
+    assign CONFIG_LINK_WIDTH = CFG_LSTATUS[`CFG_LSTATUS_LWIDTH_R];
+    assign CONFIG_LINK_RATE = CFG_LSTATUS[`CFG_LSTATUS_LRATE_R];
+    assign CONFIG_MAX_READ_REQUEST_SIZE = CFG_DCOMMAND[`CFG_DCOMMAND_MAXREQ_R];
+    assign CONFIG_MAX_PAYLOAD_SIZE = CFG_DCOMMAND[`CFG_DCOMMAND_MAXPAY_R];
+    assign CONFIG_INTERRUPT_MSIENABLE = CFG_INTERRUPT_MSIEN;
+    assign CONFIG_CPL_BOUNDARY_SEL = CFG_LCOMMAND[`CFG_LCOMMAND_RCB_R];
+    assign CONFIG_MAX_CPL_DATA = FC_CPLD;
+    assign CONFIG_MAX_CPL_HDR = FC_CPLH;
+
+    assign FC_SEL = `SIG_FC_SEL_RX_MAXALLOC_V;
+    assign RX_NP_OK = 1'b1;
+    assign RX_NP_REQ = 1'b1;
+    assign TX_CFG_GNT = 1'b1;
+    
+    // Interrupt interface
+    assign CFG_INTERRUPT = INTR_MSI_REQUEST;
+    assign INTR_MSI_RDY = CFG_INTERRUPT_RDY;
+    generate
+        if (C_PCI_DATA_WIDTH == 9'd32) begin : gen_xilinx_32
+            assign RX_TLP_START_FLAG = ~rRxTlpValid | rRxTlpEndFlag;
+            assign RX_TLP_START_OFFSET = {clog2s(C_PCI_DATA_WIDTH/32){1'b0}};
+            assign RX_TLP_END_OFFSET = 0;
+            assign RX_TLP_END_FLAG = M_AXIS_RX_TLAST;
+            assign S_AXIS_TX_TKEEP = 4'hF;
+        end else if (C_PCI_DATA_WIDTH == 9'd64) begin : gen_xilinx_64
+            assign RX_TLP_START_FLAG = ~rRxTlpValid | rRxTlpEndFlag;
+            assign RX_TLP_START_OFFSET = {clog2s(C_PCI_DATA_WIDTH/32){1'b0}};
+            assign RX_TLP_END_OFFSET = M_AXIS_RX_TKEEP[4];
+            assign RX_TLP_END_FLAG = M_AXIS_RX_TLAST;
+            assign S_AXIS_TX_TKEEP = {{4{TX_TLP_END_OFFSET | ~TX_TLP_END_FLAG}},4'hF};
+        end else if (C_PCI_DATA_WIDTH == 9'd128) begin : gen_xilinx_128
+            assign RX_TLP_END_OFFSET = M_AXIS_RX_TUSER[20:19];
+            assign RX_TLP_END_FLAG = M_AXIS_RX_TUSER[21];
+            assign RX_TLP_START_FLAG = M_AXIS_RX_TUSER[14];
+            assign RX_TLP_START_OFFSET = M_AXIS_RX_TUSER[13:12];
+            assign S_AXIS_TX_TKEEP = {{4{~TX_TLP_END_FLAG | (TX_TLP_END_OFFSET == 2'b11)}},
+                                      {4{~TX_TLP_END_FLAG | (TX_TLP_END_OFFSET >= 2'b10)}},
+                                      {4{~TX_TLP_END_FLAG | (TX_TLP_END_OFFSET >= 2'b01)}},
+                                      {4{1'b1}}};// TODO: More efficient if we use masks...
+        end else if (C_PCI_DATA_WIDTH == 9'd256) begin : x256
+            // Not possible...
+        end
+    endgenerate
+
+    always @(posedge CLK) begin
+        rRxTlpValid <= RX_TLP_VALID;
+        rRxTlpEndFlag <= RX_TLP_END_FLAG;
+    end
+endmodule // translation_layer
+
diff --git a/fpga/riffa_hdl/trellis.vh b/fpga/riffa_hdl/trellis.vh
new file mode 100644
index 0000000..032cd13
--- /dev/null
+++ b/fpga/riffa_hdl/trellis.vh
@@ -0,0 +1,88 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            trellis.vh
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The trellis.vh file is a header file with many interface
+// width definitions for the Trellis stack
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`ifndef __TRELLIS_VH
+`define __TRELLIS_VH 1
+`include "widths.vh"
+`include "types.vh"
+`include "functions.vh"
+
+// PCIe Signals
+`define SIG_BARDECODE_W `BARDECODE_W
+`define SIG_OFFSET_W `OFFSET_W
+`define SIG_TC_W `TC_W
+`define SIG_ATTR_W `ATTR_W
+`define SIG_LEN_W `LEN_W
+`define SIG_TD_W `TD_W
+`define SIG_TYPE_W `EXT_TYPE_W
+`define SIG_FMT_W `FMT_W
+`define SIG_FBE_W `FBE_W
+`define SIG_LBE_W `LBE_W
+`define SIG_TAG_W `TAG_W
+`define SIG_REQID_W `REQID_W
+`define SIG_ADDR_W `ADDR_W
+`define SIG_BYTECNT_W `BYTECNT_W
+`define SIG_STAT_W `STAT_W
+`define SIG_CPLID_W `CPLID_W
+`define SIG_LOWADDR_W `LOWADDR_W
+
+`define SIG_CFGREG_W `PCIE_CONFIGURATION_REGISTER_WIDTH
+`define SIG_BUSID_W `PCIE_BUS_ID_WIDTH
+`define SIG_DEVID_W `PCIE_DEVICE_ID_WIDTH // Device ID Width
+`define SIG_FNID_W `PCIE_FUNCTION_ID_WIDTH // Function Number
+
+`define SIG_LINKWIDTH_W `LINKWIDTH_W
+`define SIG_LINKRATE_W `LINKRATE_W
+`define SIG_MAXREAD_W `MAXREAD_W
+`define SIG_MAXPAYLOAD_W `MAXPAYLOAD_W
+
+`define SIG_FC_CPLD_W 12
+`define SIG_FC_CPLH_W 8
+
+// The maximum number of alignment blanks that can be inserted in a packet is 7
+`define SIG_NONPAY_W 4
+`define SIG_PACKETLEN_W (clog2s(4096/4) + `SIG_NONPAY_W + 1)
+`define SIG_ALIGN_W 3
+`define SIG_HDRLEN_W 3
+`define SIG_MAXHDR_W 128
+
+`endif
diff --git a/fpga/riffa_hdl/tx_alignment_pipeline.v b/fpga/riffa_hdl/tx_alignment_pipeline.v
new file mode 100644
index 0000000..8bfcefb
--- /dev/null
+++ b/fpga/riffa_hdl/tx_alignment_pipeline.v
@@ -0,0 +1,494 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename: tx_alignment_pipeline
+// Version: 1.0
+// Verilog Standard: Verilog-2001
+//
+// Description: The TX alignment pipeline takes a formatted header and data and
+// "aligns" them to create a formatted PKT. The aligner is used in both the TXC
+// and TXR engines.
+// 
+// The data interface (TX_DATA) is an interface for N 32-bit FIFOs, where N =
+// (C_DATA_WIDTH/32). The START_FLAG signal indicates that the first dword of
+// a packet is in FIFO 0 (TX_DATA[31:0]). Each FIFO interface also contains an
+// END_FLAG signal in the END_FLAGS bus. When a bit in END_FLAGS bus is asserted,
+// its corresponding fifo contains the last dword of data for the current
+// packet. START_FLAG, END_FLAG and DATA are all qualified by the VALID signal,
+// and read by the READY signal.
+// 
+// The header interface (TX_HDR) presents the entire header in a single cycle on a
+// fifo-like read-interface. The interface also contains the metadata signals
+// NOPAYLOAD, ABLANKS, and LEN. NOPAYLOAD indicates that the header is not
+// associated with a payload. ABLANKS indicates how many blanks are inserted
+// between header and payload for address alignment. LEN indicates the length of
+// the header (in DWORDS). The previous two signals determine the multiplexer
+// schedule.
+// 
+// The aligner is built around N alignment muxes that chose between header and
+// data. The aligner uses a multiplexer ROM-based schedule to determine the
+// outputs of the alignment muxes. This schedule is listed in the schedules.vh
+// include file. It initializes the wSchedule ROM. The ROM is indexed by the
+// concatenation of ABLANKS, (Header) LEN, and a saturating counter. The
+// saturating counter stops when the selection bits for all multiplexers reach a
+// steady state. 
+// 
+// See schedules.vh for more information regarding the wSchedule and wTxMuxInputs
+// arrays.
+// 
+// Plans:
+// - At some point in the future, wSchedule and wTxMuxInputs should be set by
+// initialization functions to improve extensibility and reusability, but it may
+// decrease readability.
+// 
+// - (with above) Right now the alignment pipeline works for devices that have 3
+// or 4 header dwords and insert a maximum of one alignment blank. To extend
+// this, wScheduleSelect, and C_MAX_SCHEDULE_LENGTH need to be
+// changed. wSchedule select needs to incorporate additional information bits
+// (including the minimum header length). and C_MAX_SCHEDULE_LENGTH must be
+// calculated using a function (see previous note)
+//
+// Author: Dustin Richmond (@darichmond)
+//----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "trellis.vh" // Defines the user-facing signal widths.
+module tx_alignment_pipeline
+    #(
+      parameter C_PIPELINE_OUTPUT = 1,
+      parameter C_PIPELINE_DATA_INPUT = 1,
+      parameter C_PIPELINE_HDR_INPUT = 1,
+      parameter C_USE_COMPUTE_REG = 1,
+      parameter C_USE_READY_REG = 1,
+      parameter C_DATA_WIDTH = 128,
+      parameter C_MAX_HDR_WIDTH = 128,
+      parameter C_VENDOR = "ALTERA"
+      )
+    (
+     // Interface: Clocks
+     input                                CLK,
+
+     // Interface: Reset
+     input                                RST_IN,
+
+     // Interface: TX DATA FIFOS
+     input [(C_DATA_WIDTH/32)-1:0]        TX_DATA_WORD_VALID,
+     input [C_DATA_WIDTH-1:0]             TX_DATA,
+     input                                TX_DATA_START_FLAG,
+     input [(C_DATA_WIDTH/32)-1:0]        TX_DATA_END_FLAGS,
+     output [(C_DATA_WIDTH/32)-1:0]       TX_DATA_WORD_READY,
+    
+     // Interface: TX HDR
+     input                                TX_HDR_VALID,
+     input [C_MAX_HDR_WIDTH-1:0]          TX_HDR,
+     input [`SIG_LEN_W-1:0]               TX_HDR_PAYLOAD_LEN,
+     input [`SIG_NONPAY_W-1:0]            TX_HDR_NONPAY_LEN,
+     input [`SIG_PACKETLEN_W-1:0]         TX_HDR_PACKET_LEN,
+     input                                TX_HDR_NOPAYLOAD,
+     output                               TX_HDR_READY,
+
+     // TX Interface (Unified)
+     input                                TX_PKT_READY,
+     output [C_DATA_WIDTH-1:0]            TX_PKT,
+     output                               TX_PKT_START_FLAG,
+     output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_START_OFFSET,
+     output                               TX_PKT_END_FLAG,
+     output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_END_OFFSET,
+     output                               TX_PKT_VALID
+     );
+
+    localparam C_OFFSET_WIDTH = clog2s(C_DATA_WIDTH/32);
+    localparam C_AGGREGATE_WIDTH = (C_DATA_WIDTH+C_MAX_HDR_WIDTH);
+    localparam C_MASK_WIDTH = (C_DATA_WIDTH/32);
+    localparam C_NUM_MUXES = (C_DATA_WIDTH/32);
+    localparam C_MUX_INPUTS = (C_DATA_WIDTH == 32)?5:4;
+    localparam C_CLOG_MUX_INPUTS = clog2s(C_MUX_INPUTS);
+    localparam C_MAX_SCHEDULE = (C_DATA_WIDTH == 256)? 2 : (C_DATA_WIDTH == 128)? 3: (C_DATA_WIDTH == 64)? 4: (C_DATA_WIDTH == 32)? 6 : 0;
+    localparam C_CLOG_MAX_SCHEDULE = clog2s(C_MAX_SCHEDULE);
+
+    genvar                                i;
+
+    // Wires from the data interface input registers
+    wire [(C_DATA_WIDTH/32)-1:0]          wTxDataWordValid;
+    wire [(C_DATA_WIDTH/32)-1:0]          wTxDataWordReady;
+    wire [C_DATA_WIDTH-1:0]               wTxData;
+    wire                                  wTxDataStartFlag;
+    wire [(C_DATA_WIDTH/32)-1:0]          wTxDataEndFlags;
+    wire [clog2s(C_DATA_WIDTH/32)-1:0]    wTxDataEndOffset;
+
+    // Wires from the header interface input register
+    wire                                  wTxHdrReady,_wTxHdrReady,__wTxHdrReady;
+    wire [C_MAX_HDR_WIDTH -1:0]           wTxHdr,_wTxHdr,__wTxHdr;
+    wire                                  wTxHdrValid,_wTxHdrValid,__wTxHdrValid;
+    wire                                  wTxHdrNoPayload,_wTxHdrNoPayload,__wTxHdrNoPayload;
+    wire [`SIG_LEN_W-1:0]                 wTxHdrPayloadLen,_wTxHdrPayloadLen,__wTxHdrPayloadLen; 
+    wire [`SIG_NONPAY_W-1:0]              wTxHdrNonpayLen,_wTxHdrNonpayLen,__wTxHdrNonpayLen; 
+    wire [`SIG_PACKETLEN_W-1:0]           wTxHdrPacketLen,_wTxHdrPacketLen,__wTxHdrPacketLen; 
+
+    wire [`SIG_PACKETLEN_W:0]             __wTxHdrPacketLenMinus1; 
+    wire [C_MUX_INPUTS-1:0]               __wTxHdrPacketMask;
+    wire [C_MUX_INPUTS-1:0]               __wTxHdrLenMask;    
+    // wSchedule is the array containing all of the schedules for each mux and ready signal
+    // wSchedule is indexed by the concatenation {Insert Blanks, Header Length, Saturating Counter}
+    wire [C_CLOG_MUX_INPUTS-1:0]          wSchedule[C_NUM_MUXES-1:0][(1<<(3+C_CLOG_MAX_SCHEDULE))-1:0];
+    // Create an array of mux selects, and a bus of ready signals. The ready
+    // signals are indicate when a dword is being read from the input fifo and
+    // are statically determined in the schedules.vh file
+    wire [(3+C_CLOG_MAX_SCHEDULE)-1:0]    wScheduleSelect;
+
+    wire [C_NUM_MUXES-1:0]                __wTxHdrStartEndReady,_wTxHdrStartEndReady;
+    wire [C_NUM_MUXES-1:0]                __wTxHdrStartReady,_wTxHdrStartReady;
+    wire [C_NUM_MUXES-1:0]                __wTxHdrEndReady,_wTxHdrEndReady;
+    wire [C_NUM_MUXES-1:0]                __wTxHdrSteadyStateReady,_wTxHdrSteadyStateReady;
+
+    wire [1:0]                            wReadyMuxSelect;
+    wire [C_NUM_MUXES-1:0]                wReadyMux[3:0];
+
+    // Aggreate the header and the current data inputs into an array.
+    wire [31:0]                           wAggregate[C_AGGREGATE_WIDTH/32-1:0];
+    wire [32*C_MUX_INPUTS-1:0]            wTxMuxInputs[C_NUM_MUXES-1:0];
+    wire [(C_CLOG_MUX_INPUTS*C_NUM_MUXES)-1:0] wTxMuxSelect,_wTxMuxSelect;
+    wire [C_NUM_MUXES-1:0]                     wTxMuxSelectDataReady,_wTxMuxSelectDataReady;
+    wire                                       wTxMuxSelectDataEndFlag,_wTxMuxSelectDataEndFlag;
+    wire                                       wTxMuxSelectDataStartFlag,_wTxMuxSelectDataStartFlag;
+    wire                                       wTxMuxSelectPktStartFlag,_wTxMuxSelectPktStartFlag;
+    wire                                       wTxMuxSelectReady,_wTxMuxSelectReady; 
+    wire                                       wTxMuxSelectValid,_wTxMuxSelectValid; 
+
+    // Wires from the output of the muxes to the input of the output register stage
+    // wTxPktReady is asserted when a packet is complete
+    wire                                       wTxPktReady;
+    wire                                       wTxPktValid;
+    wire [C_DATA_WIDTH-1:0]                    wTxPkt;
+    wire                                       wTxPktStartFlag;
+    wire                                       wTxPktEndFlag;
+    wire [C_OFFSET_WIDTH:0]                    wTxPktEndOffset; // An additional bit for addition overflow
+    
+    // Saturating Counter Wires
+    wire                                       wSatCtrEnable;
+    wire                                       wSatCtrReset;
+    wire [C_CLOG_MAX_SCHEDULE-1:0]             wSatCtr;
+
+    // Packet Cycle Counter Wires
+    wire                                       wPktCtrEnable;
+    wire                                       wPktCtrReset;
+    wire [`SIG_PACKETLEN_W-1:0]                wPktCtr;
+
+    wire                                       wCounterReset;
+`include "schedules.vh"
+
+    // Assignments for the Input Register Stage
+    assign __wTxHdrPacketLenMinus1 = __wTxHdrPacketLen - 1;
+    assign __wTxHdrSteadyStateReady = {C_NUM_MUXES{1'b1}};
+    assign __wTxHdrStartReady = {C_NUM_MUXES{1'b1}} >> __wTxHdrNonpayLen[C_OFFSET_WIDTH-1:0];
+    //assign __wTxHdrEndReady = __wTxHdrPacketMask ROTATE-RIGHT __wTxHdrNonpayLen[C_OFFSET_WIDTH-1:0];
+    assign __wTxHdrStartEndReady = __wTxHdrLenMask;
+    
+    // Assignments for the computation stage
+    // Counter logic
+    assign wCounterReset = _wTxMuxSelectDataEndFlag & _wTxMuxSelectReady;
+    assign wSatCtrReset = RST_IN | wCounterReset;
+    assign wSatCtrEnable = _wTxMuxSelectReady & _wTxMuxSelectValid;
+    assign wPktCtrReset = RST_IN | wCounterReset;
+    assign wPktCtrEnable = _wTxMuxSelectReady & _wTxMuxSelectValid;
+    assign wScheduleSelect = {_wTxHdrNonpayLen[2:0],wSatCtr[C_CLOG_MAX_SCHEDULE-1:0]};
+    // Ready Mux Logic
+    assign wReadyMuxSelect[0] = _wTxMuxSelectDataStartFlag;
+    assign wReadyMuxSelect[1] = _wTxMuxSelectDataEndFlag;
+    assign wReadyMux[0] = _wTxHdrSteadyStateReady;
+    assign wReadyMux[1] = _wTxHdrStartReady;
+    assign wReadyMux[2] = _wTxHdrEndReady;
+    assign wReadyMux[3] = _wTxHdrStartEndReady;
+    assign _wTxMuxSelectValid = _wTxHdrValid;
+    assign _wTxMuxSelectDataReady = wReadyMux[wReadyMuxSelect] & {C_NUM_MUXES{(wPktCtr >= _wTxHdrNonpayLen[`SIG_NONPAY_W-1:clog2s(C_NUM_MUXES)])}};
+    assign _wTxMuxSelectPktStartFlag = wPktCtr == 0;
+    assign _wTxMuxSelectDataStartFlag = wPktCtr == _wTxHdrNonpayLen[`SIG_NONPAY_W-1:clog2s(C_NUM_MUXES)];
+    assign _wTxMuxSelectDataEndFlag   = ({wPktCtr,{clog2s(C_NUM_MUXES){1'b0}}} + C_NUM_MUXES) >= _wTxHdrPacketLen;// TODO: Simplify
+
+    // Assignments for the ready stage
+    assign wTxHdrReady = (wTxMuxSelectDataEndFlag & wTxMuxSelectValid & wTxMuxSelectReady) | ~wTxMuxSelectValid;
+    assign wTxMuxSelectReady = (wTxPktReady & wTxHdrNoPayload) | 
+                               (wTxPktReady & wTxDataWordValid != 0) | 
+                               (~wTxMuxSelectValid);
+    assign wTxPktStartFlag = wTxMuxSelectPktStartFlag;
+    assign wTxPktEndFlag = wTxMuxSelectDataEndFlag;
+    assign wTxPktEndOffset = wTxHdrPacketLen[C_OFFSET_WIDTH-1:0]-1; // TODO: Retime -1?
+    assign wTxPktValid = wTxMuxSelectValid & (wTxHdrNoPayload | (~wTxHdrNoPayload & (wTxDataWordValid != 0)));
+    assign wTxDataWordReady = wTxMuxSelectDataReady & {C_NUM_MUXES{wTxPktReady & wTxMuxSelectValid & ~wTxHdrNoPayload}};
+
+    // Assignments for the output stage
+    assign TX_PKT_START_OFFSET = {C_OFFSET_WIDTH{1'b0}};
+
+    /*See comment block at start of module*/
+    generate
+        for(i = 0 ; i < C_NUM_MUXES ; i = i + 1) begin : muxes
+            assign _wTxMuxSelect[i*C_CLOG_MUX_INPUTS +: C_CLOG_MUX_INPUTS] = wSchedule[i][wScheduleSelect];
+        end
+    endgenerate
+
+    offset_to_mask
+        #(// Parameters
+          .C_MASK_SWAP                  (0),
+          .C_MASK_WIDTH                 (C_NUM_MUXES)
+          /*AUTOINSTPARAM*/)
+    packet_mask
+        (
+         // Outputs
+         .MASK                          (__wTxHdrPacketMask),
+         // Inputs
+         .OFFSET_ENABLE                 (1),
+         .OFFSET                        (__wTxHdrPacketLenMinus1[clog2s(C_NUM_MUXES)-1:0])
+         /*AUTOINST*/);
+
+    offset_to_mask
+        #(// Parameters
+          .C_MASK_SWAP                  (0),
+          .C_MASK_WIDTH                 (C_NUM_MUXES)
+          /*AUTOINSTPARAM*/)
+    len_mask
+        (// Outputs
+         .MASK                          (__wTxHdrLenMask),
+         // Inputs
+         .OFFSET_ENABLE                 (1),
+         .OFFSET                        (__wTxHdrPayloadLen[clog2s(C_NUM_MUXES)-1:0]-1)
+         /*AUTOINST*/);
+
+    rotate
+        #(// Parameters
+          .C_DIRECTION                  ("RIGHT"),
+          .C_WIDTH                      (C_NUM_MUXES)
+          /*AUTOINSTPARAM*/)
+    rot_inst
+        (
+         // Outputs
+         .RD_DATA                   (__wTxHdrEndReady),
+         // Inputs
+         .WR_DATA                   (__wTxHdrPacketMask),
+         .WR_SHIFTAMT               (__wTxHdrNonpayLen[C_OFFSET_WIDTH-1:0])
+         /*AUTOINST*/);
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_PIPELINE_HDR_INPUT?1:0),
+          .C_WIDTH                      (C_MAX_HDR_WIDTH + `SIG_NONPAY_W + `SIG_PACKETLEN_W + `SIG_LEN_W + 1),
+          .C_USE_MEMORY                 (0)
+          /*AUTOINSTPARAM*/)
+    hdr_input_reg
+        (
+         // Outputs
+         .WR_DATA_READY             (TX_HDR_READY),
+         .RD_DATA                   ({__wTxHdr,__wTxHdrNonpayLen,__wTxHdrPacketLen,__wTxHdrPayloadLen,__wTxHdrNoPayload}),
+         .RD_DATA_VALID             (__wTxHdrValid),
+         // Inputs
+         .WR_DATA                   ({TX_HDR,TX_HDR_NONPAY_LEN,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NOPAYLOAD}),
+         .WR_DATA_VALID             (TX_HDR_VALID),
+         .RD_DATA_READY             (__wTxHdrReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_USE_COMPUTE_REG?1:0),
+          .C_WIDTH                      (C_MAX_HDR_WIDTH + `SIG_NONPAY_W + `SIG_PACKETLEN_W + `SIG_LEN_W + 1 + 4*C_MASK_WIDTH),
+          .C_USE_MEMORY                 (0)
+          /*AUTOINSTPARAM*/)
+    compute_reg
+        (
+         // Outputs
+         .WR_DATA_READY             (__wTxHdrReady),
+         .RD_DATA                   ({_wTxHdr,_wTxHdrNonpayLen,_wTxHdrPacketLen,_wTxHdrPayloadLen,_wTxHdrNoPayload,
+                                      _wTxHdrSteadyStateReady,_wTxHdrStartReady,_wTxHdrEndReady,_wTxHdrStartEndReady}),
+         .RD_DATA_VALID             (_wTxHdrValid),
+         // Inputs
+         .WR_DATA                   ({__wTxHdr,__wTxHdrNonpayLen,__wTxHdrPacketLen,__wTxHdrPayloadLen,__wTxHdrNoPayload,
+                                      __wTxHdrSteadyStateReady,__wTxHdrStartReady,__wTxHdrEndReady,__wTxHdrStartEndReady}),
+         .WR_DATA_VALID             (__wTxHdrValid),
+         .RD_DATA_READY             (_wTxMuxSelectDataEndFlag & _wTxMuxSelectReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_USE_READY_REG?1:0),
+          .C_WIDTH                      (C_MAX_HDR_WIDTH + `SIG_NONPAY_W + `SIG_PACKETLEN_W + `SIG_LEN_W + 1),
+          .C_USE_MEMORY                 (0)
+          /*AUTOINSTPARAM*/)
+    ready_reg
+        (
+         // Outputs
+         .WR_DATA_READY             (_wTxHdrReady),
+         .RD_DATA                   ({wTxHdr,wTxHdrNonpayLen,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNoPayload}),
+         .RD_DATA_VALID             (wTxHdrValid),
+         // Inputs
+         .WR_DATA                   ({_wTxHdr,_wTxHdrNonpayLen,_wTxHdrPacketLen,_wTxHdrPayloadLen,_wTxHdrNoPayload}),
+         .WR_DATA_VALID             (_wTxHdrValid),
+         .RD_DATA_READY             (wTxHdrReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+    
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_USE_READY_REG?1:0),
+          .C_WIDTH                      (C_NUM_MUXES + C_CLOG_MUX_INPUTS * C_NUM_MUXES + 3),
+          .C_USE_MEMORY                 (0)
+          /*AUTOINSTPARAM*/)
+    select_reg
+        (
+         // Outputs
+         .WR_DATA_READY             (_wTxMuxSelectReady),
+         .RD_DATA                   ({wTxMuxSelectDataReady,wTxMuxSelect,wTxMuxSelectDataEndFlag,wTxMuxSelectDataStartFlag,wTxMuxSelectPktStartFlag}),
+         .RD_DATA_VALID             (wTxMuxSelectValid),
+         // Inputs
+         .WR_DATA                   ({_wTxMuxSelectDataReady,_wTxMuxSelect,_wTxMuxSelectDataEndFlag,_wTxMuxSelectDataStartFlag,_wTxMuxSelectPktStartFlag}),
+         .WR_DATA_VALID             (_wTxMuxSelectValid),
+         .RD_DATA_READY             (wTxMuxSelectReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    counter
+        #(// Parameters
+          .C_MAX_VALUE                  (C_MAX_SCHEDULE-1),
+          .C_SAT_VALUE                  (C_MAX_SCHEDULE-1),
+          .C_RST_VALUE                  (0)
+          /*AUTOINSTPARAM*/)
+    satctr_inst
+        (// Outputs
+         .VALUE                         (wSatCtr),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (wSatCtrReset),
+         .ENABLE                        (wSatCtrEnable)
+         /*AUTOINST*/);
+
+    counter
+        #(// Parameters
+          .C_MAX_VALUE                  (1<<`SIG_PACKETLEN_W),
+          .C_SAT_VALUE                  (1<<`SIG_PACKETLEN_W + 1), // Never saturate
+          .C_RST_VALUE                  (0)
+          /*AUTOINSTPARAM*/)
+    pktctr_inst
+        (// Outputs
+         .VALUE                         (wPktCtr),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (wPktCtrReset),
+         .ENABLE                        (wPktCtrEnable)
+         /*AUTOINST*/);
+
+    generate
+        for( i = 0  ; i < C_MAX_HDR_WIDTH/32 ; i = i + 1) begin : gen_aggregate
+            assign wAggregate[i] = wTxHdr[i*32 +: 32];
+        end
+
+        for( i = 0; i < C_NUM_MUXES ; i = i + 1) begin : gen_data_input_regs
+            assign wAggregate[i + C_MAX_HDR_WIDTH/32] = wTxData[32*i +: 32];
+            pipeline
+                #(// Parameters
+                  .C_DEPTH                      (C_PIPELINE_DATA_INPUT?1:0),
+                  .C_WIDTH                      (32 + 1),
+                  .C_USE_MEMORY                 (0)
+                  /*AUTOINSTPARAM*/)
+            data_register_
+                (// Outputs
+                 .WR_DATA_READY             (TX_DATA_WORD_READY[i]),
+                 .RD_DATA                   ({wTxData[32*i +: 32],wTxDataEndFlags[i]}),
+                 .RD_DATA_VALID             (wTxDataWordValid[i]),
+                 // Inputs
+                 .WR_DATA                   ({TX_DATA[32*i +: 32],TX_DATA_END_FLAGS[i] & TX_DATA_WORD_VALID[i]}),
+                 .WR_DATA_VALID             (TX_DATA_WORD_VALID[i]),
+                 .RD_DATA_READY             (wTxDataWordReady[i]),
+                 /*AUTOINST*/
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST_IN                (RST_IN));
+        end
+
+        for( i = 0 ; i < C_NUM_MUXES ; i = i + 1) begin : gen_packet_format_multiplexers
+            mux
+                 #(
+                   // Parameters
+                   .C_NUM_INPUTS                 (C_MUX_INPUTS),
+                   .C_CLOG_NUM_INPUTS            (C_CLOG_MUX_INPUTS),
+                   .C_WIDTH                      (32),
+                   .C_MUX_TYPE                   ("SELECT")
+                   /*AUTOINSTPARAM*/)
+            dw_mux_
+                 (
+                  // Outputs
+                  .MUX_OUTPUT                (wTxPkt[32*i +: 32]),
+                  // Inputs
+                  .MUX_INPUTS                (wTxMuxInputs[i]),
+                  .MUX_SELECT                (wTxMuxSelect[i*C_CLOG_MUX_INPUTS +: C_CLOG_MUX_INPUTS])
+                  /*AUTOINST*/);
+        end
+    endgenerate
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_PIPELINE_OUTPUT?1:0),
+          .C_WIDTH                      (C_DATA_WIDTH + 2 + C_OFFSET_WIDTH),
+          .C_USE_MEMORY                 (0)
+          /*AUTOINSTPARAM*/)
+    output_register_inst
+        (
+         // Outputs
+         .WR_DATA_READY             (wTxPktReady),
+         .RD_DATA                   ({TX_PKT,TX_PKT_START_FLAG,TX_PKT_END_FLAG,TX_PKT_END_OFFSET}),
+         .RD_DATA_VALID             (TX_PKT_VALID),
+         // Inputs
+         .WR_DATA                   ({wTxPkt,wTxPktStartFlag,wTxPktEndFlag,wTxPktEndOffset[C_OFFSET_WIDTH-1:0]}),
+         .WR_DATA_VALID             (wTxPktValid),
+         .RD_DATA_READY             (TX_PKT_READY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../common/")
+// End:
diff --git a/fpga/riffa_hdl/tx_data_fifo.v b/fpga/riffa_hdl/tx_data_fifo.v
new file mode 100644
index 0000000..65c0e70
--- /dev/null
+++ b/fpga/riffa_hdl/tx_data_fifo.v
@@ -0,0 +1,245 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Filename: tx_data_pipeline.v
+// Version: 1.0
+// Verilog Standard: Verilog-2001
+//
+// Description: The tx_data_fifo takes 0-bit aligned packet data and
+// puts each DW into one of N FIFOs where N = (C_DATA_WIDTH/32).
+// 
+// The data interface (TX_DATA) is an interface for N 32-bit FIFOs, where N =
+// (C_DATA_WIDTH/32). The START_FLAG signal indicates that the first dword of
+// a packet is in FIFO 0 (TX_DATA[31:0]). Each FIFO interface also contains an
+// END_FLAG signal in the END_FLAGS bus. When a bit in END_FLAGS bus is asserted,
+// its corresponding fifo contains the last dword of data for the current
+// packet. START_FLAG, END_FLAG and DATA are all qualified by the VALID signal,
+// and read by the READY signal.
+// 
+// The write interface (WR_TX) differs slightly from the read interface because it
+// produces a READY signal and consumes a VALID signal. VALID is asserted when an
+// entire packet has been packed into a FIFO. 
+//  
+// TODO: 
+// - Make sure that the synthesis tool is removing the other three start
+// flag wires (and modifying the width of the FIFOs)
+// 
+// Author: Dustin Richmond (@darichmond) 
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "trellis.vh" // Defines the user-facing signal widths.
+module tx_data_fifo 
+    #(parameter C_DEPTH_PACKETS = 10,
+      parameter C_DATA_WIDTH = 128,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 1,
+      parameter C_MAX_PAYLOAD = 256 // BYTES
+      )
+    (
+     // Interface: Clocks
+     input                          CLK,
+
+     // Interface: Reset
+     input                          RST_IN,
+
+     // Interface: WR TX DATA
+     input [C_DATA_WIDTH-1:0]       WR_TX_DATA,
+     input                          WR_TX_DATA_VALID,
+     input                          WR_TX_DATA_START_FLAG,
+     input [(C_DATA_WIDTH/32)-1:0]  WR_TX_DATA_WORD_VALID,
+     input [(C_DATA_WIDTH/32)-1:0]  WR_TX_DATA_END_FLAGS,
+     output                         WR_TX_DATA_READY,
+
+     // Interface: RD TX DATA
+     input [(C_DATA_WIDTH/32)-1:0]  RD_TX_DATA_WORD_READY,
+     output [C_DATA_WIDTH-1:0]      RD_TX_DATA,
+     output                         RD_TX_DATA_START_FLAG,
+     output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_END_FLAGS,
+     output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_VALID,
+     output                         RD_TX_DATA_PACKET_VALID
+     );
+    localparam C_FIFO_OUTPUT_DEPTH = 1;
+    localparam C_INPUT_DEPTH = C_PIPELINE_INPUT != 0 ? 1 : 0;
+    localparam C_OUTPUT_DEPTH = C_PIPELINE_OUTPUT != 0 ? 1 : 0;
+    localparam C_MAXPACKET_LINES = (C_MAX_PAYLOAD*8)/C_DATA_WIDTH;
+    localparam C_FIFO_DEPTH = C_MAXPACKET_LINES*C_DEPTH_PACKETS;
+    localparam C_FIFO_DATA_WIDTH = 32; 
+    localparam C_REGISTER_WIDTH = C_FIFO_DATA_WIDTH + 2;
+    localparam C_FIFO_WIDTH = C_FIFO_DATA_WIDTH + 2; // Data, end flag and start flag
+    localparam C_NUM_FIFOS = (C_DATA_WIDTH/32);
+    genvar                          i;
+
+    wire                            RST;
+    
+    wire [C_FIFO_DATA_WIDTH-1:0]    wWrTxData[C_NUM_FIFOS-1:0];
+    wire [C_NUM_FIFOS-1:0]          wWrTxDataValid;
+    wire [C_NUM_FIFOS-1:0]          wWrTxDataReady;
+    wire [C_NUM_FIFOS-1:0]          wWrTxDataStartFlags;
+    wire [C_NUM_FIFOS-1:0]          wWrTxDataEndFlags;
+
+    wire [C_NUM_FIFOS-1:0]          _wRdTxDataStartFlags;
+
+    wire [C_FIFO_DATA_WIDTH-1:0]    wRdTxData[C_NUM_FIFOS-1:0];
+    wire [C_NUM_FIFOS-1:0]          wRdTxDataValid;
+    wire [C_NUM_FIFOS-1:0]          wRdTxDataReady;
+    wire [C_NUM_FIFOS-1:0]          wRdTxDataStartFlags;
+    wire [C_NUM_FIFOS-1:0]          wRdTxDataEndFlags;
+    wire                            wRdTxDataPacketValid;
+    
+    wire                            wWrTxEndFlagValid;
+    wire                            wWrTxEndFlagReady;
+
+    wire                            wRdTxEndFlagValid;
+    wire                            wRdTxEndFlagReady;
+
+    wire                            wPacketDecrement; 
+    wire                            wPacketIncrement;
+
+    reg [clog2(C_DEPTH_PACKETS+1)-1:0] rPacketCounter,_rPacketCounter;
+
+    /*AUTOINPUT*/
+    /*AUTOWIRE*/
+    ///*AUTOOUTPUT*/
+
+    assign RST = RST_IN;
+
+    assign wWrTxEndFlagValid = (wWrTxDataEndFlags & wWrTxDataValid) != {C_NUM_FIFOS{1'b0}};
+    assign wWrTxEndFlagReady = rPacketCounter != C_DEPTH_PACKETS;// Designed a small bit of latency here to help timing...
+    assign wPacketIncrement = wWrTxEndFlagValid & wWrTxEndFlagReady;
+    assign wPacketDecrement = wRdTxEndFlagValid & wRdTxEndFlagReady;
+    
+    assign WR_TX_DATA_READY = wWrTxEndFlagReady;
+
+    assign wRdTxEndFlagValid = rPacketCounter != 0;
+    assign wRdTxEndFlagReady = (wRdTxDataReady & wRdTxDataEndFlags & wRdTxDataValid) != {C_NUM_FIFOS{1'b0}};
+    assign wRdTxDataPacketValid = rPacketCounter != 0;
+
+    assign RD_TX_DATA_START_FLAG = _wRdTxDataStartFlags[0];
+    
+    always @(*) begin
+        _rPacketCounter = rPacketCounter;
+        if(wPacketIncrement & wPacketDecrement) begin
+            _rPacketCounter = rPacketCounter + 0;
+        end else if(wPacketIncrement) begin
+            _rPacketCounter = rPacketCounter + 1;
+        end else if(wPacketDecrement) begin
+            _rPacketCounter = rPacketCounter - 1;
+        end
+    end // always @ (*)
+
+    always @(posedge CLK) begin
+        if(RST_IN) begin
+            rPacketCounter <= #1 0;
+        end else begin
+            rPacketCounter <= #1 _rPacketCounter;
+        end
+    end
+
+    generate
+        for( i = 0 ; i < C_NUM_FIFOS ; i = i + 1 ) begin : gen_regs_fifos
+            pipeline
+                 #(
+                   .C_DEPTH              (C_INPUT_DEPTH),
+                   .C_USE_MEMORY         (0),
+                   .C_WIDTH              (C_REGISTER_WIDTH)
+                   /*AUTOINSTPARAM*/)
+            input_pipeline_inst_
+                 (
+                  // Outputs
+                  .WR_DATA_READY         (),
+                  .RD_DATA               ({wWrTxData[i], wWrTxDataEndFlags[i],wWrTxDataStartFlags[i]}),
+                  .RD_DATA_VALID         (wWrTxDataValid[i]),
+                  // Inputs
+                  .CLK                   (CLK),
+                  .RST_IN                (RST_IN),
+                  .WR_DATA               ({WR_TX_DATA[C_FIFO_DATA_WIDTH*i +: C_FIFO_DATA_WIDTH], 
+                                           WR_TX_DATA_END_FLAGS[i], (i == 0) ? WR_TX_DATA_START_FLAG: 1'b0}),
+                  .WR_DATA_VALID         (WR_TX_DATA_VALID & WR_TX_DATA_WORD_VALID[i]),
+                  .RD_DATA_READY         (wWrTxDataReady[i]));
+
+            fifo
+                #(
+                  // Parameters
+                  .C_WIDTH             (C_FIFO_WIDTH),
+                  .C_DEPTH             (C_FIFO_DEPTH),
+                  .C_DELAY             (0)
+                  /*AUTOINSTPARAM*/)
+            fifo_inst_
+                (
+                 // Outputs
+                 .RD_DATA              ({wRdTxData[i], wRdTxDataStartFlags[i], wRdTxDataEndFlags[i]}),
+                 .WR_READY             (wWrTxDataReady[i]),
+                 .RD_VALID             (wRdTxDataValid[i]),
+                 // Inputs
+                 .WR_DATA              ({wWrTxData[i], wWrTxDataStartFlags[i], wWrTxDataEndFlags[i]}),
+                 .WR_VALID             (wWrTxDataValid[i]),
+                 .RD_READY             (wRdTxDataReady[i]),
+                 /*AUTOINST*/
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST                   (RST));
+
+            pipeline
+                #(
+                  .C_DEPTH              (C_FIFO_OUTPUT_DEPTH),
+                  .C_USE_MEMORY         (0),
+                  .C_WIDTH              (C_FIFO_WIDTH)
+                  /*AUTOINSTPARAM*/)
+            fifo_pipeline_inst_
+                (
+                 // Outputs
+                 .WR_DATA_READY         (wRdTxDataReady[i]),
+                 .RD_DATA               ({RD_TX_DATA[i*32 +: 32],
+                                          _wRdTxDataStartFlags[i],
+                                          RD_TX_DATA_END_FLAGS[i]}),
+                 .RD_DATA_VALID         (RD_TX_DATA_WORD_VALID[i]),
+                 // Inputs
+                 .WR_DATA               ({wRdTxData[i], 
+                                          wRdTxDataStartFlags[i],
+                                          wRdTxDataEndFlags[i]}),
+                 .WR_DATA_VALID         (wRdTxDataValid[i]),
+                 .RD_DATA_READY         (RD_TX_DATA_WORD_READY[i]),
+                 /*AUTOINST*/
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST_IN                (RST_IN));
+        end // for ( i = 0 ; i < C_NUM_FIFOS ; i = i + 1 )
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../common/")
+// End:
+
+
diff --git a/fpga/riffa_hdl/tx_data_pipeline.v b/fpga/riffa_hdl/tx_data_pipeline.v
new file mode 100644
index 0000000..d7e5678
--- /dev/null
+++ b/fpga/riffa_hdl/tx_data_pipeline.v
@@ -0,0 +1,161 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename: tx_data_pipeline
+// Version: 1.0
+// Verilog Standard: Verilog-2001
+//
+// Description: The TX Data pipeline module takes arbitrarily 32-bit aligned data
+// from the WR_TX_DATA interface and shifts the data so that it is 0-bit
+// aligned. This data is presented on a set of N fifos, where N =
+// (C_DATA_WIDTH/32). Each fifo provides it's own VALID signal and is
+// controlled by a READY signal. Each fifo also provides an independent DATA bus
+// and additional END_FLAG signal which inidicates that the dword provided in this
+// fifo is the last dword in the current payload. The START_FLAG signal indicates
+// that the dword at index N = 0 is the start of a new packet.
+// 
+// The TX Data Pipeline is built from two modules: tx_data_shift.v and
+// tx_data_fifo.v. See these modules for more information.
+// 
+// Author: Dustin Richmond (@darichmond) 
+//----------------------------------------------------------------------------
+`include "trellis.vh" // Defines the user-facing signal widths.
+module tx_data_pipeline
+    #(
+      parameter C_DATA_WIDTH = 128,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 1,
+      parameter C_MAX_PAYLOAD = 256,
+      parameter C_DEPTH_PACKETS = 10,
+      parameter C_VENDOR = "ALTERA"
+      )
+    (
+     // Interface: Clocks
+     input                               CLK,
+     // Interface: Resets
+     input                               RST_IN,
+
+     // Interface: WR TX DATA
+     input                               WR_TX_DATA_VALID,
+     input [C_DATA_WIDTH-1:0]            WR_TX_DATA,
+     input                               WR_TX_DATA_START_FLAG,
+     input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_START_OFFSET,
+     input                               WR_TX_DATA_END_FLAG,
+     input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_OFFSET,
+     output                              WR_TX_DATA_READY,
+
+     // Interface: TX DATA FIFOS
+     input [(C_DATA_WIDTH/32)-1:0]       RD_TX_DATA_WORD_READY,
+     output [C_DATA_WIDTH-1:0]           RD_TX_DATA,
+     output [(C_DATA_WIDTH/32)-1:0]      RD_TX_DATA_END_FLAGS,
+     output                              RD_TX_DATA_START_FLAG,
+     output [(C_DATA_WIDTH/32)-1:0]      RD_TX_DATA_WORD_VALID
+     );
+    
+    wire                                 wRdTxDataValid;
+    wire                                 wRdTxDataReady;
+    wire                                 wRdTxDataStartFlag;
+    wire [C_DATA_WIDTH-1:0]              wRdTxData;
+    wire [(C_DATA_WIDTH/32)-1:0]         wRdTxDataEndFlags;
+    wire [(C_DATA_WIDTH/32)-1:0]         wRdTxDataWordValid;
+
+    /*AUTOWIRE*/
+    /*AUTOINPUT*/
+    /*AUTOOUTPUT*/
+
+    tx_data_shift
+        #(
+          .C_PIPELINE_OUTPUT            (0),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_DATA_WIDTH                 (C_DATA_WIDTH),
+          .C_VENDOR                     (C_VENDOR))
+    tx_shift_inst
+        (
+         // Outputs
+         .WR_TX_DATA_READY              (WR_TX_DATA_READY),
+         .RD_TX_DATA                    (wRdTxData),
+         .RD_TX_DATA_VALID              (wRdTxDataValid),
+         .RD_TX_DATA_START_FLAG         (wRdTxDataStartFlag),
+         .RD_TX_DATA_WORD_VALID         (wRdTxDataWordValid),
+         .RD_TX_DATA_END_FLAGS          (wRdTxDataEndFlags),
+         // Inputs
+         .WR_TX_DATA                    (WR_TX_DATA[C_DATA_WIDTH-1:0]),
+         .WR_TX_DATA_VALID              (WR_TX_DATA_VALID),
+         .WR_TX_DATA_START_FLAG         (WR_TX_DATA_START_FLAG),
+         .WR_TX_DATA_START_OFFSET       (WR_TX_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .WR_TX_DATA_END_FLAG           (WR_TX_DATA_END_FLAG),
+         .WR_TX_DATA_END_OFFSET         (WR_TX_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .RD_TX_DATA_READY              (wRdTxDataReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    // TX Data Fifo
+    tx_data_fifo
+        #(
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_PIPELINE_INPUT             (1),
+          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS),
+          .C_MAX_PAYLOAD                (C_MAX_PAYLOAD),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_DATA_WIDTH             (C_DATA_WIDTH))
+    txdf_inst
+        (
+         // Outputs
+         .WR_TX_DATA_READY            (wRdTxDataReady),
+         .RD_TX_DATA                  (RD_TX_DATA[C_DATA_WIDTH-1:0]),
+         .RD_TX_DATA_START_FLAG       (RD_TX_DATA_START_FLAG),
+         .RD_TX_DATA_WORD_VALID       (RD_TX_DATA_WORD_VALID[(C_DATA_WIDTH/32)-1:0]),
+         .RD_TX_DATA_END_FLAGS        (RD_TX_DATA_END_FLAGS[(C_DATA_WIDTH/32)-1:0]),
+         // Inputs
+         .WR_TX_DATA                  (wRdTxData),
+         .WR_TX_DATA_VALID            (wRdTxDataValid),
+         .WR_TX_DATA_START_FLAG       (wRdTxDataStartFlag),
+         .WR_TX_DATA_WORD_VALID       (wRdTxDataWordValid),
+         .WR_TX_DATA_END_FLAGS        (wRdTxDataEndFlags),
+         .RD_TX_DATA_WORD_READY       (RD_TX_DATA_WORD_READY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../common/")
+// End:
diff --git a/fpga/riffa_hdl/tx_data_shift.v b/fpga/riffa_hdl/tx_data_shift.v
new file mode 100644
index 0000000..f9f6e6d
--- /dev/null
+++ b/fpga/riffa_hdl/tx_data_shift.v
@@ -0,0 +1,326 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename: tx_data_shift.v
+// Version: 1.0
+// Verilog Standard: Verilog-2001
+//
+// Description: The TX Data Shift module takes arbitrarily 32-bit aligned data
+// from the WR_TX_DATA interface and shifts the data so that it is 0-bit aligned
+// on the output RD_TX_DATA interface. The VALID, END_OFFSET, and END_FLAG signal
+// in the WR_TX_DATA interface are replaced by WORD_VALID and END_FLAGS signals in
+// the RD_TX_DATA interface. Each bit in the WORD_VALID bus indicates that the
+// corresponding dword in the RD_TX_DATA bus is valid. Each bit in the END_FLAGS
+// bus indicates that the end of the payload occurs at the corresponding dword in
+// the RD_TX_DATA bus.
+//
+// The core of the TX_DATA_SHIFT module is a set of N multiplexers, where N =
+// (C_DATA_WIDTH/32). The multiplexers are surrounded by a set of optional
+// input and output registers with output wires wWrTxData* and input wires
+// wRdTxData*. Each register in the array rMuxSelect choses which mux input
+// desplay on the mux output. The values of the registers are set based on the
+// value of wWrTxDataStartOffset. These registers are enabled when
+// wWrTxDataStartFlag is 1 and their value set based on the value of
+// wWrTxDataStartOffset.
+// 
+// Each bit in the VALID bus is determined by the result of two masks,
+// wRdTxEndFlagMask and wRdTxStartFlagMask, to make wRdTxDataValid. The start flag
+// mask is active when wWrTxDataStartFlag is 1, based on wWrTxDataStartOffset. The
+// end flag mask is active when wWrTxDataEndFlag is 1, based on
+// wWrTxDataEndOffset.
+// 
+// TODO: 
+// - Using WORD_VALID is a little bit confusing. I should bring back VALID as well
+// - WORD_VALID should be DWORD_VALID
+// - Use a uniform naming scheme for C_DATA_WIDTH/32
+// - Is there a more efficient way to implement the wRdTxStartMaskFlag? Perhaps using the reset of a register?
+// Author: Dustin Richmond (@darichmond) 
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "trellis.vh"
+module tx_data_shift
+    #(
+      parameter C_PIPELINE_OUTPUT = 1,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_DATA_WIDTH = 128,
+      parameter C_VENDOR = "ALTERA"
+      )
+    (
+     // Interface: Clocks
+     input                               CLK,
+
+     // Interface: Reset
+     input                               RST_IN,
+
+     // Interface: WR TX DATA
+     input                               WR_TX_DATA_VALID,
+     input [C_DATA_WIDTH-1:0]            WR_TX_DATA,
+     input                               WR_TX_DATA_START_FLAG,
+     input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_START_OFFSET,
+     input                               WR_TX_DATA_END_FLAG,
+     input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_OFFSET,
+     output                              WR_TX_DATA_READY,
+
+     // Interface: RD TX DATA
+     input                               RD_TX_DATA_READY,
+     output [C_DATA_WIDTH-1:0]           RD_TX_DATA,
+     output                              RD_TX_DATA_START_FLAG,
+     output [(C_DATA_WIDTH/32)-1:0]      RD_TX_DATA_WORD_VALID,
+     output [(C_DATA_WIDTH/32)-1:0]      RD_TX_DATA_END_FLAGS,
+     output                              RD_TX_DATA_VALID
+     );
+    localparam C_ROTATE_BITS = clog2s(C_DATA_WIDTH/32);
+    localparam C_NUM_MUXES = (C_DATA_WIDTH/32);
+    localparam C_SELECT_WIDTH = C_DATA_WIDTH/32;
+    localparam C_MASK_WIDTH = C_DATA_WIDTH/32;
+    localparam C_AGGREGATE_WIDTH = C_DATA_WIDTH;
+    
+    genvar                               i;
+
+    wire                                 wWrTxDataValid;
+    wire [C_DATA_WIDTH-1:0]              wWrTxData;
+    wire                                 wWrTxDataStartFlag;
+    wire [clog2s(C_DATA_WIDTH/32)-1:0]   wWrTxDataStartOffset;
+    wire                                 wWrTxDataEndFlag;
+    wire [clog2s(C_DATA_WIDTH/32)-1:0]   wWrTxDataEndOffset;
+    wire [(C_DATA_WIDTH/32)-1:0]         wWrTxEndFlagMask;
+    wire [(C_DATA_WIDTH/32)-1:0]         wWrTxDataEndFlags;
+    wire                                 wWrTxDataReady;
+
+    wire                                 wRdTxDataReady;
+    wire [C_DATA_WIDTH-1:0]              wRdTxData;
+    wire                                 wRdTxDataStartFlag;
+    wire [(C_DATA_WIDTH/32)-1:0]         wRdTxDataEndFlags;
+    wire [(C_DATA_WIDTH/32)-1:0]         wRdTxDataWordValid;
+    wire [(C_DATA_WIDTH/32)-1:0]         wRdTxStartFlagMask;
+    wire [(C_DATA_WIDTH/32)-1:0]         wRdTxEndFlagMask;
+    wire                                 wRdTxDataValid;
+
+    // wSelectDefault is the default select value for each mux, 1 << i where i
+    // is the mux/dword index.
+    wire [C_SELECT_WIDTH-1:0]            wSelectDefault[C_NUM_MUXES-1:0]; 
+    // wSelectRotated is the value the select for each mux after the data's
+    // start offset has been applied and until the end flag is seen.
+    wire [C_SELECT_WIDTH-1:0]            wSelectRotated[C_NUM_MUXES-1:0];
+
+    reg [C_SELECT_WIDTH-1:0]             rMuxSelect[C_NUM_MUXES-1:0],_rMuxSelect[C_NUM_MUXES-1:0];
+    reg [clog2s(C_DATA_WIDTH/32)-1:0]    rStartOffset,_rStartOffset;
+
+    assign wWrTxDataReady = wRdTxDataReady;
+
+    assign wRdTxStartFlagMask = wWrTxDataStartFlag ? 
+                                {(C_DATA_WIDTH/32){1'b1}} >> wWrTxDataStartOffset:
+                                {(C_DATA_WIDTH/32){1'b1}};
+    assign wRdTxDataWordValid = wRdTxEndFlagMask & wRdTxStartFlagMask;
+    assign wRdTxDataStartFlag = wWrTxDataStartFlag;
+    assign wRdTxDataValid = wWrTxDataValid;
+
+    generate
+        for (i = 0; i < C_NUM_MUXES; i = i + 1) begin : gen_mux_default
+            assign wSelectDefault[i] = (1 << i);
+        end
+    endgenerate
+
+    always @(*) begin
+        _rStartOffset = WR_TX_DATA_START_OFFSET;
+    end
+
+    always @(posedge CLK) begin
+        if(WR_TX_DATA_READY & WR_TX_DATA_START_FLAG & WR_TX_DATA_VALID) begin
+            rStartOffset <= _rStartOffset;
+        end
+    end
+
+    generate
+        for (i = 0; i < C_NUM_MUXES; i = i + 1) begin : gen_mux_select
+            always @(*) begin
+                _rMuxSelect[i] = wSelectRotated[i];
+            end
+
+            always @(posedge CLK) begin
+                if(WR_TX_DATA_READY & WR_TX_DATA_START_FLAG) begin
+                    rMuxSelect[i] <= _rMuxSelect[i];
+                end
+            end
+        end
+    endgenerate
+    
+    pipeline
+        #(// Parameters
+          .C_WIDTH                      (C_DATA_WIDTH+2*(1+clog2s(C_DATA_WIDTH/32))),
+          .C_USE_MEMORY                 (0),
+          .C_DEPTH                      (C_PIPELINE_INPUT?1:0)
+          /*AUTOINSTPARAM*/)
+    input_register
+        (
+         // Outputs
+         .WR_DATA_READY                 (WR_TX_DATA_READY),
+         .RD_DATA                       ({wWrTxData,wWrTxDataStartFlag,wWrTxDataStartOffset,wWrTxDataEndFlag,wWrTxDataEndOffset}),
+         .RD_DATA_VALID                 (wWrTxDataValid),
+         // Inputs
+         .WR_DATA                       ({WR_TX_DATA,WR_TX_DATA_START_FLAG,WR_TX_DATA_START_OFFSET,
+                                          WR_TX_DATA_END_FLAG,WR_TX_DATA_END_OFFSET}),
+         .WR_DATA_VALID                 (WR_TX_DATA_VALID),
+         .RD_DATA_READY                 (wWrTxDataReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+    
+    // The pipeline carries the data bus and SOF/EOF.
+    pipeline
+        #(// Parameters
+          .C_WIDTH                      (C_DATA_WIDTH + 2*C_MASK_WIDTH + 1),
+          .C_USE_MEMORY                 (0),
+          .C_DEPTH                      ((C_PIPELINE_OUTPUT > 1) ? 1 : 0)
+          /*AUTOINSTPARAM*/)
+    output_register
+        (
+         // Outputs
+         .WR_DATA_READY                 (wRdTxDataReady),
+         .RD_DATA                       ({RD_TX_DATA,RD_TX_DATA_START_FLAG,
+                                          RD_TX_DATA_END_FLAGS,RD_TX_DATA_WORD_VALID}),
+         .RD_DATA_VALID                 (RD_TX_DATA_VALID),
+         // Inputs
+         .WR_DATA                       ({wRdTxData,wRdTxDataStartFlag,
+                                          wRdTxDataEndFlags,wRdTxDataWordValid}),
+         .WR_DATA_VALID                 (wRdTxDataValid),
+         .RD_DATA_READY                 (RD_TX_DATA_READY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    offset_to_mask
+        #(
+          .C_MASK_SWAP                  (0),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_MASK_WIDTH                 (C_MASK_WIDTH))
+    eof_convert
+        (
+         // Outputs
+         .MASK                      (wWrTxEndFlagMask),
+         // Inputs
+         .OFFSET_ENABLE             (wWrTxDataEndFlag),
+         .OFFSET                    (wWrTxDataEndOffset)
+         /*AUTOINST*/);
+    rotate
+        #(
+          // Parameters
+          .C_DIRECTION                  ("RIGHT"),
+          .C_WIDTH                      (C_DATA_WIDTH/32)
+          /*AUTOINSTPARAM*/)
+    em_rotate_inst
+        (
+         // Outputs
+         .RD_DATA                       (wRdTxEndFlagMask),
+         // Inputs
+         .WR_DATA                       (wWrTxEndFlagMask),
+         .WR_SHIFTAMT                   (rStartOffset[clog2s(C_DATA_WIDTH/32)-1:0])
+         /*AUTOINST*/);
+
+    // Determine the 1-hot dword end flag
+    offset_flag_to_one_hot
+        #(
+          .C_WIDTH                      (C_DATA_WIDTH/32)
+          /*AUTOINSTPARAM*/)
+    ef_onehot_inst
+        (
+         // Outputs
+         .RD_ONE_HOT                    (wWrTxDataEndFlags),
+         // Inputs
+         .WR_OFFSET                     (wWrTxDataEndOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .WR_FLAG                       (wWrTxDataEndFlag)
+         /*AUTOINST*/);
+
+    rotate
+        #(
+          // Parameters
+          .C_DIRECTION                  ("RIGHT"),
+          .C_WIDTH                      (C_DATA_WIDTH/32)
+          /*AUTOINSTPARAM*/)
+    ef_rotate_inst
+        (
+         // Outputs
+         .RD_DATA                       (wRdTxDataEndFlags),
+         // Inputs
+         .WR_DATA                       (wWrTxDataEndFlags),
+         .WR_SHIFTAMT                   (rStartOffset[clog2s(C_DATA_WIDTH/32)-1:0])
+         /*AUTOINST*/);
+
+    generate
+        for (i = 0; i < C_NUM_MUXES; i = i + 1) begin : gen_rotates
+            rotate
+                 #(
+                   // Parameters
+                   .C_DIRECTION         ("LEFT"),
+                   .C_WIDTH             ((C_DATA_WIDTH/32))
+                   /*AUTOINSTPARAM*/)
+            select_rotate_inst_
+                 (
+                  // Outputs
+                  .RD_DATA               (wSelectRotated[i]),
+                  // Inputs
+                  .WR_DATA               (wSelectDefault[i]),
+                  .WR_SHIFTAMT           (WR_TX_DATA_START_OFFSET[C_ROTATE_BITS-1:0])
+                  /*AUTOINST*/);
+        end
+    endgenerate
+
+    generate
+        for (i = 0; i < C_DATA_WIDTH/32; i = i + 1) begin : gen_multiplexers
+            one_hot_mux
+                 #(
+                   .C_DATA_WIDTH        (32),
+                   /*AUTOINSTPARAM*/
+                   // Parameters
+                   .C_SELECT_WIDTH      (C_SELECT_WIDTH),
+                   .C_AGGREGATE_WIDTH   (C_AGGREGATE_WIDTH))
+            mux_inst_
+                 (
+                  // Inputs
+                  .ONE_HOT_SELECT       (rMuxSelect[i]),
+                  // Outputs
+                  .ONE_HOT_OUTPUT       (wRdTxData[32*i +: 32]),
+                  .ONE_HOT_INPUTS       (wWrTxData)
+                  /*AUTOINST*/);
+        end
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../common/" "../../common/")
+// End:    
+
diff --git a/fpga/riffa_hdl/tx_engine.v b/fpga/riffa_hdl/tx_engine.v
new file mode 100644
index 0000000..12e6a77
--- /dev/null
+++ b/fpga/riffa_hdl/tx_engine.v
@@ -0,0 +1,227 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename: tx_engine.v
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description: The tx_engine module takes a formatted header, number of alignment
+// blanks and a payloa and concatenates all three (in that order) to form a
+// packet. These packets must meet max-request, max-payload, and payload
+// termination requirements (see Read Completion Boundary). The tx_engine does
+// not check these requirements during operation, but may do so during simulation.
+// This Engine is capable of operating at "line rate".
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "trellis.vh" // Defines the user-facing signal widths.
+module tx_engine
+    #(parameter C_DATA_WIDTH = 128,
+      parameter C_DEPTH_PACKETS = 10,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 0,
+      parameter C_FORMATTER_DELAY = 1,
+      parameter C_MAX_HDR_WIDTH  = 128,
+      parameter C_MAX_PAYLOAD_DWORDS = 64,
+      parameter C_VENDOR = "ALTERA"
+      )
+    (
+     // Interface: Clocks
+     input                                CLK,
+
+     // Interface: Reset
+     input                                RST_IN,
+
+     // Interface: TX HDR
+     input                                TX_HDR_VALID,
+     input [C_MAX_HDR_WIDTH-1:0]          TX_HDR,
+     input [`SIG_LEN_W-1:0]               TX_HDR_PAYLOAD_LEN,
+     input [`SIG_NONPAY_W-1:0]            TX_HDR_NONPAY_LEN,
+     input [`SIG_PACKETLEN_W-1:0]         TX_HDR_PACKET_LEN,
+     input                                TX_HDR_NOPAYLOAD,
+     output                               TX_HDR_READY,
+
+     // Interface: TX_DATA
+     input                                TX_DATA_VALID,
+     input [C_DATA_WIDTH-1:0]             TX_DATA,
+     input                                TX_DATA_START_FLAG,
+     input [clog2s(C_DATA_WIDTH/32)-1:0]  TX_DATA_START_OFFSET,
+     input                                TX_DATA_END_FLAG,
+     input [clog2s(C_DATA_WIDTH/32)-1:0]  TX_DATA_END_OFFSET,
+     output                               TX_DATA_READY,
+
+     // Interface: TX_PKT
+     input                                TX_PKT_READY,
+     output [C_DATA_WIDTH-1:0]            TX_PKT,
+     output                               TX_PKT_START_FLAG,
+     output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_START_OFFSET,
+     output                               TX_PKT_END_FLAG,
+     output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_END_OFFSET,
+     output                               TX_PKT_VALID
+     );
+    localparam C_PIPELINE_HDR_FIFO_INPUT = C_PIPELINE_INPUT;
+    localparam C_PIPELINE_HDR_FIFO_OUTPUT = C_PIPELINE_OUTPUT;
+    localparam C_PIPELINE_HDR_INPUT = C_PIPELINE_INPUT;
+    localparam C_ACTUAL_HDR_FIFO_DEPTH = clog2s(C_DEPTH_PACKETS);
+    localparam C_USE_COMPUTE_REG = 1;
+    localparam C_USE_READY_REG = 1;
+    localparam C_USE_FWFT_HDR_FIFO = 1;
+    localparam C_DATA_FIFO_DEPTH = C_ACTUAL_HDR_FIFO_DEPTH + C_FORMATTER_DELAY + 
+                                   C_PIPELINE_HDR_FIFO_INPUT + C_PIPELINE_HDR_FIFO_OUTPUT + C_USE_FWFT_HDR_FIFO + // Header Fifo
+                                   C_PIPELINE_HDR_INPUT + C_USE_COMPUTE_REG + C_USE_READY_REG + C_PIPELINE_OUTPUT; // Aligner
+
+    wire                                  wTxHdrReady;
+    wire                                  wTxHdrValid;
+    wire [C_MAX_HDR_WIDTH-1:0]            wTxHdr;
+    wire [`SIG_NONPAY_W-1:0]              wTxHdrNonpayLen;
+    wire [`SIG_PACKETLEN_W-1:0]           wTxHdrPacketLen;
+    wire [`SIG_LEN_W-1:0]                 wTxHdrPayloadLen; 
+    wire                                  wTxHdrNoPayload;
+
+    wire                                  wTxDataReady;
+    wire [C_DATA_WIDTH-1:0]               wTxData;
+    wire [clog2s(C_DATA_WIDTH/32)-1:0]    wTxDataEndOffset;
+    wire                                  wTxDataStartFlag;
+    wire [(C_DATA_WIDTH/32)-1:0]          wTxDataEndFlags;
+    wire [(C_DATA_WIDTH/32)-1:0]          wTxDataWordValid;
+    wire [(C_DATA_WIDTH/32)-1:0]          wTxDataWordReady;
+
+    tx_data_pipeline
+        #(
+          .C_MAX_PAYLOAD                (C_MAX_PAYLOAD_DWORDS*32),
+          .C_DEPTH_PACKETS              (C_DATA_FIFO_DEPTH),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_DATA_WIDTH                 (C_DATA_WIDTH),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_VENDOR                     (C_VENDOR))
+    tx_data_pipeline_inst
+        (
+         // Outputs
+         .RD_TX_DATA                  (wTxData[C_DATA_WIDTH-1:0]),
+         .RD_TX_DATA_WORD_VALID       (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
+         .RD_TX_DATA_START_FLAG       (wTxDataStartFlag),
+         .RD_TX_DATA_END_FLAGS        (wTxDataEndFlags[(C_DATA_WIDTH/32)-1:0]),
+         .WR_TX_DATA_READY            (TX_DATA_READY),
+         // Inputs
+         .RD_TX_DATA_WORD_READY       (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
+         .WR_TX_DATA                  (TX_DATA),
+         .WR_TX_DATA_VALID            (TX_DATA_VALID),
+         .WR_TX_DATA_START_FLAG       (TX_DATA_START_FLAG),
+         .WR_TX_DATA_START_OFFSET     (TX_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .WR_TX_DATA_END_FLAG         (TX_DATA_END_FLAG),
+         .WR_TX_DATA_END_OFFSET       (TX_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    // TX Header Fifo
+    tx_hdr_fifo
+        #(
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_HDR_FIFO_OUTPUT),
+          .C_PIPELINE_INPUT             (C_PIPELINE_HDR_FIFO_INPUT),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_DEPTH_PACKETS              (C_ACTUAL_HDR_FIFO_DEPTH),
+          .C_MAX_HDR_WIDTH              (C_MAX_HDR_WIDTH),
+          .C_VENDOR                     (C_VENDOR))
+    txhf_inst
+        (
+         // Outputs
+         .WR_TX_HDR_READY               (TX_HDR_READY),
+         .RD_TX_HDR                     (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
+         .RD_TX_HDR_VALID               (wTxHdrValid),
+         .RD_TX_HDR_NOPAYLOAD           (wTxHdrNoPayload),
+         .RD_TX_HDR_PAYLOAD_LEN         (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
+         .RD_TX_HDR_NONPAY_LEN          (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
+         .RD_TX_HDR_PACKET_LEN          (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
+         // Inputs
+         .WR_TX_HDR                     (TX_HDR[C_MAX_HDR_WIDTH-1:0]),
+         .WR_TX_HDR_VALID               (TX_HDR_VALID),
+         .WR_TX_HDR_NOPAYLOAD           (TX_HDR_NOPAYLOAD),
+         .WR_TX_HDR_PAYLOAD_LEN         (TX_HDR_PAYLOAD_LEN[`SIG_LEN_W-1:0]),
+         .WR_TX_HDR_NONPAY_LEN          (TX_HDR_NONPAY_LEN[`SIG_NONPAY_W-1:0]),
+         .WR_TX_HDR_PACKET_LEN          (TX_HDR_PACKET_LEN[`SIG_PACKETLEN_W-1:0]),
+         .RD_TX_HDR_READY               (wTxHdrReady),
+         /*AUTOINST*/
+         // Outputs
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    // TX Header Fifo
+    tx_alignment_pipeline
+        #(
+          // Parameters
+          .C_PIPELINE_OUTPUT            (1),
+          .C_PIPELINE_DATA_INPUT        (1),
+          .C_PIPELINE_HDR_INPUT         (C_PIPELINE_HDR_INPUT),
+          .C_DATA_WIDTH                 (C_DATA_WIDTH),
+          // Parameters
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_USE_COMPUTE_REG            (C_USE_COMPUTE_REG),
+          .C_USE_READY_REG              (C_USE_READY_REG),
+          .C_VENDOR                     (C_VENDOR))
+    tx_alignment_inst
+        (
+         // Outputs
+         .TX_DATA_WORD_READY            (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
+         .TX_HDR_READY                  (wTxHdrReady),
+         .TX_PKT                        (TX_PKT[C_DATA_WIDTH-1:0]),
+         .TX_PKT_VALID                  (TX_PKT_VALID),
+         .TX_PKT_START_FLAG             (TX_PKT_START_FLAG),
+         .TX_PKT_START_OFFSET           (TX_PKT_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_PKT_END_FLAG               (TX_PKT_END_FLAG),
+         .TX_PKT_END_OFFSET             (TX_PKT_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         // Inputs
+         .TX_DATA_START_FLAG            (wTxDataStartFlag),
+         .TX_DATA_END_FLAGS             (wTxDataEndFlags),
+         .TX_DATA_WORD_VALID            (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
+         .TX_DATA                       (wTxData[C_DATA_WIDTH-1:0]),
+         .TX_HDR                        (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
+         .TX_HDR_VALID                  (wTxHdrValid),
+         .TX_HDR_NOPAYLOAD              (wTxHdrNoPayload),
+         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
+         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
+         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
+         .TX_PKT_READY                  (TX_PKT_READY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_engine_classic.v b/fpga/riffa_hdl/tx_engine_classic.v
new file mode 100644
index 0000000..5eea7c4
--- /dev/null
+++ b/fpga/riffa_hdl/tx_engine_classic.v
@@ -0,0 +1,844 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//
+// Filename:            tx_engine_classic.v
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The TX Engine takes unformatted request and completions,
+// formats these packets into "TLP's" or Transaction Layer Packets and abitrates
+// their sending over the PCIe bus. These packets must meet max-request,
+// max-payload, and payload termination requirements (see Read Completion
+// Boundary). The TX Engine does not check these requirements during operation,
+// but may do so during simulation.
+// 
+// Valid packets are transmitted over the shared PCIe bus as determined
+// by the arbiter. 
+// 
+// This Engine is capable of operating at "line rate".
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "tlp.vh"
+module tx_engine_classic
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 1,
+      parameter C_MAX_PAYLOAD_DWORDS = 256,
+      parameter C_VENDOR = "ALTERA"
+      )
+    (
+     // Interface: Clocks
+     input                                    CLK,
+
+     // Interface: Resets
+     input                                    RST_IN,
+
+     // Interface: Configuration 
+     input [`SIG_CPLID_W-1:0]                 CONFIG_COMPLETER_ID,
+
+     // Interface: TX Classic
+     input                                    TX_TLP_READY,
+     output [C_PCI_DATA_WIDTH-1:0]            TX_TLP,
+     output                                   TX_TLP_VALID,
+     output                                   TX_TLP_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET,
+     output                                   TX_TLP_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET,
+
+     // Interface: TXC Engine
+     input                                    TXC_DATA_VALID,
+     input [C_PCI_DATA_WIDTH-1:0]             TXC_DATA,
+     input                                    TXC_DATA_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXC_DATA_START_OFFSET,
+     input                                    TXC_DATA_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXC_DATA_END_OFFSET,
+     output                                   TXC_DATA_READY,
+
+     input                                    TXC_META_VALID,
+     input [`SIG_FBE_W-1:0]                   TXC_META_FDWBE,
+     input [`SIG_LBE_W-1:0]                   TXC_META_LDWBE,
+     input [`SIG_LOWADDR_W-1:0]               TXC_META_ADDR,
+     input [`SIG_TYPE_W-1:0]                  TXC_META_TYPE,
+     input [`SIG_LEN_W-1:0]                   TXC_META_LENGTH,
+     input [`SIG_BYTECNT_W-1:0]                  TXC_META_BYTE_COUNT,
+     input [`SIG_TAG_W-1:0]                   TXC_META_TAG,
+     input [`SIG_REQID_W-1:0]                 TXC_META_REQUESTER_ID,
+     input [`SIG_TC_W-1:0]                    TXC_META_TC,
+     input [`SIG_ATTR_W-1:0]                  TXC_META_ATTR,
+     input                                    TXC_META_EP,
+     output                                   TXC_META_READY,
+     output                                   TXC_SENT,
+     
+     // Interface: TXR Engine
+     input                                    TXR_DATA_VALID,
+     input [C_PCI_DATA_WIDTH-1:0]             TXR_DATA,
+     input                                    TXR_DATA_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_START_OFFSET,
+     input                                    TXR_DATA_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_END_OFFSET,
+     output                                   TXR_DATA_READY,
+
+     input                                    TXR_META_VALID,
+     input [`SIG_FBE_W-1:0]                   TXR_META_FDWBE, 
+     input [`SIG_LBE_W-1:0]                   TXR_META_LDWBE,
+     input [`SIG_ADDR_W-1:0]                  TXR_META_ADDR,
+     input [`SIG_LEN_W-1:0]                   TXR_META_LENGTH,
+     input [`SIG_TAG_W-1:0]                   TXR_META_TAG,
+     input [`SIG_TC_W-1:0]                    TXR_META_TC,
+     input [`SIG_ATTR_W-1:0]                  TXR_META_ATTR,
+     input [`SIG_TYPE_W-1:0]                  TXR_META_TYPE,
+     input                                    TXR_META_EP,
+     output                                   TXR_META_READY,
+     output                                   TXR_SENT
+     );
+    localparam C_MUX_TYPE = "SHIFT";
+    localparam C_DEPTH_PACKETS = 10;
+    /*AUTOWIRE*/
+    /*AUTOINPUT*/
+
+    wire [C_PCI_DATA_WIDTH-1:0]               _TXC_DATA;
+    wire [C_PCI_DATA_WIDTH-1:0]               _TXR_DATA;
+    wire [C_PCI_DATA_WIDTH-1:0]               wTxcTlp;
+    wire                                      wTxcTlpEndFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]    wTxcTlpEndOffset;
+    wire                                      wTxcTlpReady;
+    wire                                      wTxcTlpStartFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]    wTxcTlpStartOffset;
+    wire                                      wTxcTlpValid;
+
+    wire [C_PCI_DATA_WIDTH-1:0]               wTxrTlp;
+    wire                                      wTxrTlpEndFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]    wTxrTlpEndOffset;
+    wire                                      wTxrTlpReady;
+    wire                                      wTxrTlpStartFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]    wTxrTlpStartOffset;
+    wire                                      wTxrTlpValid;
+
+    reg                                       rTxValid;
+    reg [`TLP_TYPE_W-1:0]                     rTxType;
+    reg                                       rTxEndFlag;
+    reg                                       rTxrSent;
+    reg                                       rTxcSent;
+
+    assign TXC_SENT = rTxcSent;
+    assign TXR_SENT = rTxrSent;
+        
+    always @(posedge CLK) begin
+        if(TX_TLP_START_FLAG) begin
+            rTxType <= TX_TLP[`TLP_TYPE_R];
+        end
+        rTxEndFlag <= TX_TLP_END_FLAG;
+        rTxValid <= TX_TLP_VALID & TX_TLP_READY;
+        rTxcSent <= rTxEndFlag & rTxValid & (rTxType == `TLP_TYPE_CPL);
+        rTxrSent <= rTxEndFlag & rTxValid & (rTxType == `TLP_TYPE_REQ);
+    end
+    
+    generate
+        if(C_VENDOR == "XILINX") begin : xilinx_data
+            if(C_PCI_DATA_WIDTH == 128) begin : x_be_swap128
+                assign _TXC_DATA = {TXC_DATA[103:96], TXC_DATA[111:104], TXC_DATA[119:112], TXC_DATA[127:120],
+                                    TXC_DATA[71:64], TXC_DATA[79:72], TXC_DATA[87:80], TXC_DATA[95:88],
+                                    TXC_DATA[39:32], TXC_DATA[47:40], TXC_DATA[55:48], TXC_DATA[63:56],
+                                    TXC_DATA[07:00], TXC_DATA[15:08], TXC_DATA[23:16], TXC_DATA[31:24]};
+                assign _TXR_DATA = {TXR_DATA[103:96], TXR_DATA[111:104], TXR_DATA[119:112], TXR_DATA[127:120],
+                                    TXR_DATA[71:64], TXR_DATA[79:72], TXR_DATA[87:80], TXR_DATA[95:88],
+                                    TXR_DATA[39:32], TXR_DATA[47:40], TXR_DATA[55:48], TXR_DATA[63:56],
+                                    TXR_DATA[07:00], TXR_DATA[15:08], TXR_DATA[23:16], TXR_DATA[31:24]};
+            end else if(C_PCI_DATA_WIDTH == 64) begin: x_be_swap64
+                assign _TXC_DATA = {TXC_DATA[39:32], TXC_DATA[47:40], TXC_DATA[55:48], TXC_DATA[63:56],
+                                    TXC_DATA[07:00], TXC_DATA[15:08], TXC_DATA[23:16], TXC_DATA[31:24]};
+                assign _TXR_DATA = {TXR_DATA[39:32], TXR_DATA[47:40], TXR_DATA[55:48], TXR_DATA[63:56],
+                                    TXR_DATA[07:00], TXR_DATA[15:08], TXR_DATA[23:16], TXR_DATA[31:24]};
+            end else if(C_PCI_DATA_WIDTH == 32) begin: x_be_swap32
+                assign _TXC_DATA = {TXC_DATA[07:00], TXC_DATA[15:08], TXC_DATA[23:16], TXC_DATA[31:24]};
+                assign _TXR_DATA = {TXR_DATA[07:00], TXR_DATA[15:08], TXR_DATA[23:16], TXR_DATA[31:24]};
+            end
+        end else begin : altera_data
+            assign _TXC_DATA = TXC_DATA;
+            assign _TXR_DATA = TXR_DATA;
+        end
+    endgenerate
+
+    txc_engine_classic
+        #(
+          .C_PIPELINE_OUTPUT            (0),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_DWORDS),
+          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS),
+          .C_VENDOR                     (C_VENDOR))
+    txc_engine_inst
+        (
+         // Outputs
+         .TXC_TLP                       (wTxcTlp[C_PCI_DATA_WIDTH-1:0] ),
+         .TXC_TLP_VALID                 (wTxcTlpValid),
+         .TXC_TLP_START_FLAG            (wTxcTlpStartFlag),
+         .TXC_TLP_START_OFFSET          (wTxcTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_TLP_END_FLAG              (wTxcTlpEndFlag),
+         .TXC_TLP_END_OFFSET            (wTxcTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         // Inputs
+         .TXC_TLP_READY                 (wTxcTlpReady),
+         .TXC_DATA                      (_TXC_DATA[C_PCI_DATA_WIDTH-1:0]),
+         /*AUTOINST*/
+         // Outputs
+         .TXC_DATA_READY                (TXC_DATA_READY),
+         .TXC_META_READY                (TXC_META_READY),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .CONFIG_COMPLETER_ID           (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
+         .TXC_DATA_VALID                (TXC_DATA_VALID),
+         .TXC_DATA_START_FLAG           (TXC_DATA_START_FLAG),
+         .TXC_DATA_START_OFFSET         (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (TXC_DATA_END_FLAG),
+         .TXC_DATA_END_OFFSET           (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (TXC_META_VALID),
+         .TXC_META_FDWBE                (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (TXC_META_TAG[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (TXC_META_TC[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (TXC_META_EP));
+
+    txr_engine_classic
+        #(
+          .C_PIPELINE_OUTPUT            (0),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_DWORDS),
+          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS),
+          .C_VENDOR                     (C_VENDOR))
+    txr_engine_inst
+        (
+         // Outputs
+         .TXR_TLP                       (wTxrTlp[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_TLP_VALID                 (wTxrTlpValid),
+         .TXR_TLP_START_FLAG            (wTxrTlpStartFlag),
+         .TXR_TLP_START_OFFSET          (wTxrTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_TLP_END_FLAG              (wTxrTlpEndFlag),
+         .TXR_TLP_END_OFFSET            (wTxrTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA                      (_TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
+         // Inputs
+         .TXR_TLP_READY                 (wTxrTlpReady),
+         /*AUTOINST*/
+         // Outputs
+         .TXR_DATA_READY                (TXR_DATA_READY),
+         .TXR_META_READY                (TXR_META_READY),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .CONFIG_COMPLETER_ID           (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
+         .TXR_DATA_VALID                (TXR_DATA_VALID),
+         .TXR_DATA_START_FLAG           (TXR_DATA_START_FLAG),
+         .TXR_DATA_START_OFFSET         (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (TXR_DATA_END_FLAG),
+         .TXR_DATA_END_OFFSET           (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (TXR_META_VALID),
+         .TXR_META_FDWBE                (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (TXR_META_TAG[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (TXR_META_TC[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (TXR_META_EP));
+
+    tx_mux
+        #(
+          .C_PIPELINE_INPUT             (0),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_MUX_TYPE                   (C_MUX_TYPE),
+          .C_VENDOR                     (C_VENDOR))
+    tx_mux_inst
+        (
+         // Inputs
+         .TXC_TLP                       (wTxcTlp[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_TLP_VALID                 (wTxcTlpValid),
+         .TXC_TLP_START_FLAG            (wTxcTlpStartFlag),
+         .TXC_TLP_START_OFFSET          (wTxcTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_TLP_END_FLAG              (wTxcTlpEndFlag),
+         .TXC_TLP_END_OFFSET            (wTxcTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_TLP                       (wTxrTlp[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_TLP_VALID                 (wTxrTlpValid),
+         .TXR_TLP_START_FLAG            (wTxrTlpStartFlag),
+         .TXR_TLP_START_OFFSET          (wTxrTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_TLP_END_FLAG              (wTxrTlpEndFlag),
+         .TXR_TLP_END_OFFSET            (wTxrTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         // Outputs
+         .TXC_TLP_READY                 (wTxcTlpReady),
+         .TXR_TLP_READY                 (wTxrTlpReady),
+         /*AUTOINST*/
+         // Outputs
+         .TX_TLP                        (TX_TLP[C_PCI_DATA_WIDTH-1:0]),
+         .TX_TLP_VALID                  (TX_TLP_VALID),
+         .TX_TLP_START_FLAG             (TX_TLP_START_FLAG),
+         .TX_TLP_START_OFFSET           (TX_TLP_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TX_TLP_END_FLAG               (TX_TLP_END_FLAG),
+         .TX_TLP_END_OFFSET             (TX_TLP_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .TX_TLP_READY                  (TX_TLP_READY));
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../common/")
+// End:
+/*
+ Filename: tx_mux.v
+ Version: 1.0
+ Verilog Standard: Verilog-2001
+
+ Description: The tx_mux arbitrates access to the PCI TX interface
+ between the the Request and Completion engines. The top level tx_mux
+ module instantiates two sub-modules (also declared in this file):
+ tx_arbiter and tx_phi. The arbiter choses the next packet that will
+ be granted the TX interface, based on the priorities given to
+ it. Each priority is the count of how many successive, back-to-back
+ packets can be sent by either the TXC or TXR interface before
+ granting time to the other engine. The mux is a simple multiplexer
+ that uses the select signals from the arbiter.
+ 
+ Notes: Any modifications to this file should meet the conditions set
+ forth in the "Trellis Style Guide"
+
+ - The pipeline stage at the start of the mux means that ready stays high for
+ both TXC and TXR. This the behavior we want?
+ 
+ Author: Dustin Richmond (@darichmond) 
+ Co-Authors:
+ */
+`timescale 1ns/1ns
+`include "trellis.vh"
+module tx_mux
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 1,
+      parameter C_MUX_TYPE = "SHIFT",
+      parameter C_VENDOR = "ALTERA"
+      )
+    (
+     // Interface: Clocks
+     input                                    CLK,
+
+     // Interface: Resets
+     input                                    RST_IN,
+
+     // Interface: TXC
+     input [C_PCI_DATA_WIDTH-1:0]             TXC_TLP,
+     output                                   TXC_TLP_READY,
+     input                                    TXC_TLP_VALID,
+     input                                    TXC_TLP_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXC_TLP_START_OFFSET,
+     input                                    TXC_TLP_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXC_TLP_END_OFFSET,
+
+     // Interface: TXR
+     input [C_PCI_DATA_WIDTH-1:0]             TXR_TLP,
+     input                                    TXR_TLP_VALID,
+     input                                    TXR_TLP_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_TLP_START_OFFSET,
+     input                                    TXR_TLP_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_TLP_END_OFFSET,
+     output                                   TXR_TLP_READY,
+
+     // Interface: TX Classic
+     input                                    TX_TLP_READY,
+     output [C_PCI_DATA_WIDTH-1:0]            TX_TLP,
+     output                                   TX_TLP_VALID,
+     output                                   TX_TLP_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET,
+     output                                   TX_TLP_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET
+     );
+    localparam C_WIDTH = (C_PCI_DATA_WIDTH + 2 * (clog2s(C_PCI_DATA_WIDTH/32) + 1));
+    localparam C_TXC_PRIORITY = 1;
+    localparam C_TXR_PRIORITY = 2;
+    /*AUTOWIRE*/
+    /*AUTOINPUT*/
+    /*AUTOOUTPUT*/
+
+    // Input Pipeline Stage to Mux
+    wire [C_PCI_DATA_WIDTH-1:0]               wTxcTlp;
+    wire                                      wTxcTlpReady;
+    wire                                      wTxcTlpValid;
+    wire                                      wTxcTlpStartFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]    wTxcTlpStartOffset;
+    wire                                      wTxcTlpEndFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]    wTxcTlpEndOffset;
+
+    wire [C_PCI_DATA_WIDTH-1:0]               wTxrTlp;
+    wire                                      wTxrTlpReady;
+    wire                                      wTxrTlpValid;
+    wire                                      wTxrTlpStartFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]    wTxrTlpStartOffset;
+    wire                                      wTxrTlpEndFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]    wTxrTlpEndOffset;
+
+    // Output of Mux to 
+    wire [C_PCI_DATA_WIDTH-1:0]               wTxTlp;
+    wire                                      wTxTlpReady;
+    wire                                      wTxTlpValid;
+    wire                                      wTxTlpStartFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]    wTxTlpStartOffset;
+    wire                                      wTxTlpEndFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]    wTxTlpEndOffset;
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_PIPELINE_INPUT?1:0),
+          .C_USE_MEMORY                 (0),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_WIDTH                      (C_WIDTH))
+    txr_capture_inst
+        (
+         // Outputs
+         .WR_DATA_READY                 (TXR_TLP_READY),
+         .RD_DATA                       ({wTxrTlp, wTxrTlpStartFlag, wTxrTlpStartOffset,
+                                          wTxrTlpEndFlag, wTxrTlpEndOffset}),
+         .RD_DATA_VALID                 (wTxrTlpValid),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .WR_DATA                       ({TXR_TLP, 
+                                          TXR_TLP_START_FLAG, TXR_TLP_START_OFFSET, 
+                                          TXR_TLP_END_FLAG, TXR_TLP_END_OFFSET}),
+         .WR_DATA_VALID                 (TXR_TLP_VALID),
+         .RD_DATA_READY                 (wTxrTlpReady));
+    
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                         (C_PIPELINE_INPUT?1:0),
+          .C_USE_MEMORY                    (0),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_WIDTH                      (C_WIDTH))
+    txc_capture_inst
+        (
+         // Outputs
+         .WR_DATA_READY                    (TXC_TLP_READY),
+         .RD_DATA                          ({wTxcTlp, wTxcTlpStartFlag, wTxcTlpStartOffset,
+                                             wTxcTlpEndFlag, wTxcTlpEndOffset}),
+         .RD_DATA_VALID                    (wTxcTlpValid),
+         // Inputs
+         .WR_DATA                          ({TXC_TLP, 
+                                             TXC_TLP_START_FLAG, TXC_TLP_START_OFFSET, 
+                                             TXC_TLP_END_FLAG, TXC_TLP_END_OFFSET}),
+         .WR_DATA_VALID                    (TXC_TLP_VALID),
+         .RD_DATA_READY                    (wTxcTlpReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    tx_arbiter
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_TXC_PRIORITY               (C_TXC_PRIORITY),
+          .C_TXR_PRIORITY               (C_TXR_PRIORITY))
+    tx_arbiter_inst
+        (
+         // Outputs
+         .TXR_TLP_READY                    (wTxrTlpReady),
+         .TXC_TLP_READY                    (wTxcTlpReady),
+         // Inputs
+         .TX_TLP_READY                     (wTxTlpReady),
+         .TXC_TLP_VALID                    (wTxcTlpValid),
+         .TXC_TLP_START_FLAG               (wTxcTlpStartFlag),
+         .TXC_TLP_END_FLAG                 (wTxcTlpEndFlag),
+         .TXR_TLP_VALID                    (wTxrTlpValid),
+         .TXR_TLP_START_FLAG               (wTxrTlpStartFlag),
+         .TXR_TLP_END_FLAG                 (wTxrTlpEndFlag),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+    
+    // MUX Selector
+
+    tx_phi
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MUX_TYPE                   (C_MUX_TYPE),
+          .C_WIDTH                      (C_WIDTH))
+    tx_phi_inst
+        (
+         // Outputs
+         .TXC_TLP_READY                    (wTxcTlpReady),
+         .TXR_TLP_READY                    (wTxrTlpReady),
+        
+         .TX_TLP                           (wTxTlp),
+         .TX_TLP_VALID                     (wTxTlpValid),
+         .TX_TLP_START_FLAG                (wTxTlpStartFlag),
+         .TX_TLP_START_OFFSET              (wTxTlpStartOffset),
+         .TX_TLP_END_FLAG                  (wTxTlpEndFlag),
+         .TX_TLP_END_OFFSET                (wTxTlpEndOffset),
+         // Inputs
+         .TXC_TLP                          (wTxcTlp),
+         .TXC_TLP_VALID                    (wTxcTlpValid),
+         .TXC_TLP_START_FLAG               (wTxcTlpStartFlag),
+         .TXC_TLP_START_OFFSET             (wTxcTlpStartOffset),
+         .TXC_TLP_END_FLAG                 (wTxcTlpEndFlag),
+         .TXC_TLP_END_OFFSET               (wTxcTlpEndOffset),
+        
+         .TXR_TLP                          (wTxrTlp),
+         .TXR_TLP_VALID                    (wTxrTlpValid),
+         .TXR_TLP_START_FLAG               (wTxrTlpStartFlag),
+         .TXR_TLP_START_OFFSET             (wTxrTlpStartOffset),
+         .TXR_TLP_END_FLAG                 (wTxrTlpEndFlag),
+         .TXR_TLP_END_OFFSET               (wTxrTlpEndOffset),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                      (C_PIPELINE_OUTPUT?1:0),
+          .C_USE_MEMORY                 (0),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_WIDTH                      (C_WIDTH))
+    tx_output_inst
+        (
+         // Outputs
+         .WR_DATA_READY                    (wTxTlpReady),
+         .RD_DATA                          ({TX_TLP, 
+                                             TX_TLP_START_FLAG, TX_TLP_START_OFFSET, 
+                                             TX_TLP_END_FLAG, TX_TLP_END_OFFSET}),
+         .RD_DATA_VALID                    (TX_TLP_VALID),
+         // Inputs
+         .WR_DATA                          ({wTxTlp, wTxTlpStartFlag, wTxTlpStartOffset,
+                                             wTxTlpEndFlag, wTxTlpEndOffset}),
+         .WR_DATA_VALID                    (wTxTlpValid),
+         .RD_DATA_READY                    (TX_TLP_READY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../common/")
+// End:
+
+/* 
+ Description: The tx_arbiter arbitrates between TXC and TXR channels. The C_TX*_PRIORITY
+ values are counters are the maximum number of uninterrupted TXR or TXC packets that can be
+ transmitted without transmitting a packet of the other type. 
+ 
+ Notes: Any modifications to this file should meet the conditions set
+ forth in the "Trellis Style Guide"
+
+ Author: Dustin Richmond (@darichmond) 
+ Co-Authors:
+ */
+module tx_arbiter
+    #(
+      parameter C_TXC_PRIORITY = 1,
+      parameter C_TXR_PRIORITY = 1)
+    (
+     // Interface: Clocks
+     input  CLK,
+
+     // Interface: Resets     
+     input  RST_IN,
+
+     // Interface: TX Classic Flow Control
+     input  TX_TLP_READY,
+
+     // Interface: TXR Flow Control
+     output TXR_TLP_READY,
+     input  TXR_TLP_VALID,
+     input  TXR_TLP_START_FLAG,
+     input  TXR_TLP_END_FLAG,
+
+     // Interface: TXC Flow Control
+     output TXC_TLP_READY,
+     input  TXC_TLP_VALID,
+     input  TXC_TLP_START_FLAG,
+     input  TXC_TLP_END_FLAG
+
+     );
+    
+    localparam S_TXARB_IDLE = 0; // STATE: Idle state for the arbiter (not currently used)
+    localparam S_TXARB_TRANSMIT_TXR = 1; // STATE: Transmit TXR packets until the priority counter is reached
+    localparam S_TXARB_TRANSMIT_TXC = 2; // STATE: Transmit TXC packets until the priority counter is reached
+
+    // S_TXARB_PRIORITY is a special state that encodes the type (TXR/TXC) with
+    // higher priority so that the state machine (below) is general.
+    localparam S_TXARB_PRIORITY = (S_TXARB_TRANSMIT_TXR >= S_TXARB_TRANSMIT_TXC)? S_TXARB_TRANSMIT_TXR: S_TXARB_TRANSMIT_TXC;
+    localparam C_NUM_STATES = S_TXARB_TRANSMIT_TXC;
+    
+    wire    wTxrGrant;
+    wire    wTxrReq;
+    wire    wTxrDone;
+
+    wire    wTxcGrant;
+    wire    wTxcReq;
+    wire    wTxcDone;
+
+    reg [clog2s(C_NUM_STATES):0] rArbState,_rArbState;
+
+    reg                          rTxrLast,_rTxrLast; // Reset on RST_IN or TXC_TLP_READY
+    reg                          rTxcLast,_rTxcLast; // Reset on RST_IN or TXR_TLP_READY
+
+    reg                          rTxrActive,_rTxrActive; // Reset on RST_IN or TXC_TLP_READY
+    reg                          rTxcActive,_rTxcActive; // Reset on RST_IN or TXR_TLP_READY
+
+    reg [clog2s(C_TXC_PRIORITY)-1:0] rTxcCounter,_rTxcCounter; // Reset on RST_IN or TXC_TLP_READY
+    reg [clog2s(C_TXR_PRIORITY)-1:0] rTxrCounter,_rTxrCounter; // Reset on RST_IN or TXR_TLP_READY
+
+    assign TXR_TLP_READY = wTxrGrant & TX_TLP_READY; // TODO: Not great
+    assign wTxrReq = TXR_TLP_START_FLAG & TXR_TLP_VALID;
+    assign wTxrDone = TXR_TLP_END_FLAG & TXR_TLP_READY;
+    assign wTxrGrant = (rArbState == S_TXARB_TRANSMIT_TXR);
+
+    assign TXC_TLP_READY = wTxcGrant & TX_TLP_READY; // TODO: Not great
+    assign wTxcReq = TXC_TLP_START_FLAG & TXC_TLP_VALID;
+    assign wTxcDone = TXC_TLP_END_FLAG & TXC_TLP_READY;
+    assign wTxcGrant = (rArbState == S_TXARB_TRANSMIT_TXC);
+    
+    always @(*) begin
+        // Defaults
+        _rTxcCounter  = rTxcCounter;
+        _rTxcActive   = rTxcActive;
+        _rTxcLast     = rTxcLast;
+        
+        if(wTxrGrant) begin
+            _rTxcCounter = 0;
+        end else if(wTxcReq & wTxcGrant & ~rTxcLast) begin
+            _rTxcCounter = _rTxcCounter + 1;
+        end 
+
+        if(wTxcReq & wTxcGrant) begin
+            _rTxcActive = 1;
+        end else if(wTxcDone) begin
+            _rTxcActive = 0;
+        end
+
+        if(wTxrGrant | RST_IN) begin
+            _rTxcLast = 0;
+        end else if(wTxcReq & wTxcGrant) begin
+            _rTxcLast = (rTxcCounter == (C_TXC_PRIORITY - 1));
+        end
+    end // always @ (*)
+
+    always @(posedge CLK) begin
+        if(RST_IN) begin
+            rTxcCounter <= #1 0;
+            rTxcActive  <= #1 0;
+            rTxcLast    <= #1 0;
+        end else begin
+            rTxcCounter <= #1  _rTxcCounter;
+            rTxcActive  <= #1  _rTxcActive;
+            rTxcLast    <= #1  _rTxcLast;
+        end
+    end
+
+    always @(*) begin
+        // Defaults
+        _rTxrCounter  = rTxrCounter;
+        _rTxrActive   = rTxrActive;
+        _rTxrLast     = rTxrLast;
+        
+        if(wTxcGrant) begin
+            _rTxrCounter = 0;
+        end else if(wTxrReq & wTxrGrant & ~rTxrLast) begin
+            _rTxrCounter = _rTxrCounter + 1;
+        end 
+
+        if(wTxrReq & wTxrGrant) begin
+            _rTxrActive = 1;
+        end else if(wTxrDone) begin
+            _rTxrActive = 0;
+        end
+
+        if(wTxcGrant | RST_IN) begin
+            _rTxrLast = 0;
+        end else if(wTxrReq & wTxrGrant) begin
+            /* verilator lint_off WIDTH */
+            _rTxrLast  = (rTxrCounter == (C_TXR_PRIORITY - 1));
+            /* verilator lint_on WIDTH */
+        end
+    end
+    
+    always @(posedge CLK) begin
+        if(RST_IN) begin
+            rTxrCounter <= #1 0;
+            rTxrActive  <= #1 0;
+            rTxrLast    <= #1 0;
+        end else begin
+            rTxrCounter <= #1 _rTxrCounter;
+            rTxrActive  <= #1 _rTxrActive;
+            rTxrLast    <= #1 _rTxrLast;
+        end
+    end
+
+    // User encoded state machine
+    always @(*) begin
+        _rArbState = rArbState;
+
+        case(rArbState)
+            S_TXARB_TRANSMIT_TXR: begin
+                if((rTxrLast & wTxrDone & wTxcReq) | (~rTxrActive & ~wTxrReq & wTxcReq)) begin
+                    _rArbState = S_TXARB_TRANSMIT_TXC;
+                end
+            end
+            S_TXARB_TRANSMIT_TXC: begin
+                if((rTxcLast & wTxcDone & wTxrReq) | (~rTxcActive & ~wTxcReq & wTxrReq)) begin
+                    _rArbState = S_TXARB_TRANSMIT_TXR;
+                end
+            end
+            default: begin
+                // Error! This should never happen...
+            end
+        endcase
+    end // always @ begin
+    
+    always @(posedge CLK) begin
+        if(RST_IN) begin
+            rArbState <= #1 S_TXARB_PRIORITY;
+        end else begin
+            rArbState <= #1 _rArbState;
+        end
+    end
+    
+endmodule
+
+/* 
+ Description: The tx_phi wraps a mux instantiation for the tx_mux. It is
+ controlled by the tx_arbiter
+ 
+ Notes: Any modifications to this file should meet the conditions set
+ forth in the "Trellis Style Guide"
+
+ Author: Dustin Richmond (@darichmond) 
+ Co-Authors:
+ */
+module tx_phi
+    #(
+      parameter C_PCI_DATA_WIDTH = 10'd128,
+      parameter C_MUX_TYPE = "SHIFT",
+      parameter C_WIDTH = (C_PCI_DATA_WIDTH + 2 * (clog2s(C_PCI_DATA_WIDTH/32) + 1))
+      )
+    (
+     // Interface: Clocks
+     input                                    CLK,
+
+     // Interface: Resets
+     input                                    RST_IN,
+
+     // Interface: TXC Flow Control
+     input                                    TXC_TLP_READY,
+
+     // Interface: TXR Flow Control
+     input                                    TXR_TLP_READY,
+
+     // Interface: TXC
+     input [C_PCI_DATA_WIDTH-1:0]             TXC_TLP,
+     input                                    TXC_TLP_VALID,
+     input                                    TXC_TLP_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXC_TLP_START_OFFSET,
+     input                                    TXC_TLP_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXC_TLP_END_OFFSET,
+
+     // Interface: TXR
+     input [C_PCI_DATA_WIDTH-1:0]             TXR_TLP,
+     input                                    TXR_TLP_VALID,
+     input                                    TXR_TLP_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_TLP_START_OFFSET,
+     input                                    TXR_TLP_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_TLP_END_OFFSET,
+
+
+     // Interface: TX Classic
+     output [C_PCI_DATA_WIDTH-1:0]            TX_TLP,
+     output                                   TX_TLP_VALID,
+     output                                   TX_TLP_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET,
+     output                                   TX_TLP_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET
+     );
+
+    // Width = 2 * (DATA WIDTH + VALID + START FLAG + START OFFSET + END FLAG + END OFFSET)
+    localparam C_MUX_WIDTH = C_PCI_DATA_WIDTH + 3 + 2*clog2s(C_PCI_DATA_WIDTH/32);
+    
+    wire [2*C_MUX_WIDTH-1:0]                  wAggregate;
+
+    assign wAggregate = {{TXR_TLP,TXR_TLP_VALID,TXR_TLP_START_FLAG,
+                          TXR_TLP_START_OFFSET,TXR_TLP_END_FLAG,TXR_TLP_END_OFFSET},
+                         {TXC_TLP,TXC_TLP_VALID,TXC_TLP_START_FLAG,
+                          TXC_TLP_START_OFFSET,TXC_TLP_END_FLAG,TXC_TLP_END_OFFSET}};
+
+    mux
+        #(
+          // Parameters
+          .C_NUM_INPUTS                 (2),
+          .C_CLOG_NUM_INPUTS            (1),
+          .C_WIDTH                      (C_MUX_WIDTH),
+          .C_MUX_TYPE                   ("SELECT")
+          /*AUTOINSTPARAM*/)
+    mux_inst
+        (
+         // Outputs
+         .MUX_OUTPUT                    ({TX_TLP,TX_TLP_VALID,TX_TLP_START_FLAG,
+                                          TX_TLP_START_OFFSET,TX_TLP_END_FLAG,
+                                          TX_TLP_END_OFFSET}),
+         // Inputs
+         .MUX_INPUTS                    (wAggregate),
+         .MUX_SELECT                    (TXR_TLP_READY)
+         /*AUTOINST*/);
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_engine_selector.v b/fpga/riffa_hdl/tx_engine_selector.v
new file mode 100644
index 0000000..3f4519c
--- /dev/null
+++ b/fpga/riffa_hdl/tx_engine_selector.v
@@ -0,0 +1,117 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            tx_engine_selector.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         Searches for read and write requests.
+//                      PCIe Endpoint core.
+// Author:              Matt Jacobsen
+// History:             @mattj: Version 2.0
+// Additional Comments: 
+//-----------------------------------------------------------------------------
+
+`timescale 1ns/1ns
+module tx_engine_selector 
+    #(
+      parameter C_NUM_CHNL = 4'd12
+      )
+    (
+     input                  CLK,
+     input                  RST,
+
+     input [C_NUM_CHNL-1:0] REQ_ALL, // Write requests
+
+     output                 REQ, // Write request
+     output [3:0]           CHNL// Write channel
+     );
+
+    reg [3:0]               rReqChnl=0, _rReqChnl=0;
+    reg [3:0]               rReqChnlNext=0, _rReqChnlNext=0;
+    reg                     rReqChnlsSame=0, _rReqChnlsSame=0;
+    reg [3:0]               rChnlNext=0, _rChnlNext=0;
+    reg [3:0]               rChnlNextNext=0, _rChnlNextNext=0;
+    reg                     rChnlNextDfrnt=0, _rChnlNextDfrnt=0;
+    reg                     rChnlNextNextOn=0, _rChnlNextNextOn=0;
+    wire                    wChnlNextNextOn;
+    reg                     rReq=0, _rReq=0;
+    wire                    wReq;// = (REQ_ALL>>(rReqChnl));
+    reg                     rReqChnlNextUpdated=0, _rReqChnlNextUpdated=0;
+
+    assign wReq = REQ_ALL[rReqChnl];
+    assign wChnlNextNextOn = REQ_ALL[rChnlNextNext];
+    assign REQ = rReq;
+    assign CHNL = rReqChnl;
+
+
+    // Search for the next request so that we can move onto it immediately after
+    // the current channel has released its request.
+    always @ (posedge CLK) begin
+        rReq <= #1 (RST ? 1'd0 : _rReq);
+        rReqChnl <= #1 (RST ? 4'd0 : _rReqChnl);
+        rReqChnlNext <= #1 (RST ? 4'd0 : _rReqChnlNext);
+        rChnlNext <= #1 (RST ? 4'd0 : _rChnlNext);
+        rChnlNextNext <= #1 (RST ? 4'd0 : _rChnlNextNext);
+        rChnlNextDfrnt <= #1 (RST ? 1'd0 : _rChnlNextDfrnt);
+        rChnlNextNextOn <= #1 (RST ? 1'd0 : _rChnlNextNextOn);
+        rReqChnlsSame <= #1 (RST ? 1'd0 : _rReqChnlsSame);
+        rReqChnlNextUpdated <= #1 (RST ? 1'd1 : _rReqChnlNextUpdated);
+    end
+
+    always @ (*) begin
+        // Go through each channel (RR), looking for requests
+        _rChnlNextNextOn = wChnlNextNextOn;
+        _rChnlNext = rChnlNextNext;
+        _rChnlNextNext = (rChnlNextNext == C_NUM_CHNL - 1 ? 4'd0 : rChnlNextNext + 1'd1);
+        _rChnlNextDfrnt = (rChnlNextNext != rReqChnl);
+        _rReqChnlsSame = (rReqChnlNext == rReqChnl);
+
+        // Save ready channel if it is not the same channel we're currently on
+        if (rChnlNextNextOn & rChnlNextDfrnt & rReqChnlsSame & !rReqChnlNextUpdated) begin
+            _rReqChnlNextUpdated = 1;
+            _rReqChnlNext = rChnlNext;
+        end
+        else begin
+            _rReqChnlNextUpdated = 0;
+            _rReqChnlNext = rReqChnlNext;
+        end
+        
+        // Assign the new channel
+        _rReq = wReq;
+        _rReqChnl = (!rReq ? rReqChnlNext : rReqChnl);
+    end
+
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_engine_ultrascale.v b/fpga/riffa_hdl/tx_engine_ultrascale.v
new file mode 100644
index 0000000..f7d72e8
--- /dev/null
+++ b/fpga/riffa_hdl/tx_engine_ultrascale.v
@@ -0,0 +1,229 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            tx_engine_ultrascale.v
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The TX Engine takes unformatted request and completions,
+// formats these packets into AXI packets for the Xilinx Core. These packets
+// must meet max-request, max-payload, and payload termination requirements (see
+// Read Completion Boundary). The TX Engine does not check these requirements
+// during operation, but may do so during simulation.
+// 
+// This Engine is capable of operating at "line rate".
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "ultrascale.vh"
+module tx_engine_ultrascale
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 0,
+      parameter C_MAX_PAYLOAD_DWORDS = 64
+      )
+    (
+     // Interface: Clocks
+     input                                   CLK,
+     // Interface: Resets
+     input                                   RST_IN,
+     // Interface: Configuration
+     input [`SIG_CPLID_W-1:0]                CONFIG_COMPLETER_ID,
+
+     // Interface: CC
+     input                                   S_AXIS_CC_TREADY,
+     output                                  S_AXIS_CC_TVALID,
+     output                                  S_AXIS_CC_TLAST,
+     output [C_PCI_DATA_WIDTH-1:0]           S_AXIS_CC_TDATA,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]      S_AXIS_CC_TKEEP,
+     output [`SIG_CC_TUSER_W-1:0]            S_AXIS_CC_TUSER,
+
+     // Interface: TXC Engine
+     input                                   TXC_DATA_VALID,
+     input [C_PCI_DATA_WIDTH-1:0]            TXC_DATA,
+     input                                   TXC_DATA_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
+     input                                   TXC_DATA_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
+     output                                  TXC_DATA_READY,
+
+     input                                   TXC_META_VALID,
+     input [`SIG_FBE_W-1:0]                  TXC_META_FDWBE,
+     input [`SIG_LBE_W-1:0]                  TXC_META_LDWBE,
+     input [`SIG_LOWADDR_W-1:0]              TXC_META_ADDR,
+     input [`SIG_TYPE_W-1:0]                 TXC_META_TYPE,
+     input [`SIG_LEN_W-1:0]                  TXC_META_LENGTH,
+     input [`SIG_BYTECNT_W-1:0]                 TXC_META_BYTE_COUNT,
+     input [`SIG_TAG_W-1:0]                  TXC_META_TAG,
+     input [`SIG_REQID_W-1:0]                TXC_META_REQUESTER_ID,
+     input [`SIG_TC_W-1:0]                   TXC_META_TC,
+     input [`SIG_ATTR_W-1:0]                 TXC_META_ATTR,
+     input                                   TXC_META_EP,
+     output                                  TXC_META_READY,
+     output                                  TXC_SENT,
+
+     // Interface: RQ
+     input                                   S_AXIS_RQ_TREADY,
+     output                                  S_AXIS_RQ_TVALID,
+     output                                  S_AXIS_RQ_TLAST,
+     output [C_PCI_DATA_WIDTH-1:0]           S_AXIS_RQ_TDATA,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]      S_AXIS_RQ_TKEEP,
+     output [`SIG_RQ_TUSER_W-1:0]            S_AXIS_RQ_TUSER,
+    
+     // Interface: TXR Engine
+     input                                   TXR_DATA_VALID,
+     input [C_PCI_DATA_WIDTH-1:0]            TXR_DATA,
+     input                                   TXR_DATA_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
+     input                                   TXR_DATA_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
+     output                                  TXR_DATA_READY,
+
+     input                                   TXR_META_VALID,
+     input [`SIG_FBE_W-1:0]                  TXR_META_FDWBE, 
+     input [`SIG_LBE_W-1:0]                  TXR_META_LDWBE,
+     input [`SIG_ADDR_W-1:0]                 TXR_META_ADDR,
+     input [`SIG_LEN_W-1:0]                  TXR_META_LENGTH,
+     input [`SIG_TAG_W-1:0]                  TXR_META_TAG,
+     input [`SIG_TC_W-1:0]                   TXR_META_TC,
+     input [`SIG_ATTR_W-1:0]                 TXR_META_ATTR,
+     input [`SIG_TYPE_W-1:0]                 TXR_META_TYPE,
+     input                                   TXR_META_EP,
+     output                                  TXR_META_READY,
+     output                                  TXR_SENT
+     );
+
+    localparam C_DEPTH_PACKETS = 10;
+    /*AUTOWIRE*/
+    /*AUTOINPUT*/
+    /*AUTOOUTPUT*/
+
+    reg                                      rTxcSent;
+    reg                                      rTxrSent;
+
+    assign TXC_SENT = rTxcSent;
+    assign TXR_SENT = rTxrSent;
+    
+    always @(posedge CLK) begin
+        rTxcSent <= S_AXIS_CC_TLAST & S_AXIS_CC_TVALID & S_AXIS_CC_TREADY;
+        rTxrSent <= S_AXIS_RQ_TLAST & S_AXIS_RQ_TVALID & S_AXIS_RQ_TREADY;
+    end                                  
+    
+    txr_engine_ultrascale
+        #(
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_DWORDS))
+    txr_engine_inst
+        (/*AUTOINST*/
+         // Outputs
+         .S_AXIS_RQ_TVALID              (S_AXIS_RQ_TVALID),
+         .S_AXIS_RQ_TLAST               (S_AXIS_RQ_TLAST),
+         .S_AXIS_RQ_TDATA               (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),
+         .TXR_DATA_READY                (TXR_DATA_READY),
+         .TXR_META_READY                (TXR_META_READY),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .CONFIG_COMPLETER_ID           (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
+         .S_AXIS_RQ_TREADY              (S_AXIS_RQ_TREADY),
+         .TXR_DATA_VALID                (TXR_DATA_VALID),
+         .TXR_DATA                      (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (TXR_DATA_START_FLAG),
+         .TXR_DATA_START_OFFSET         (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (TXR_DATA_END_FLAG),
+         .TXR_DATA_END_OFFSET           (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (TXR_META_VALID),
+         .TXR_META_FDWBE                (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (TXR_META_TAG[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (TXR_META_TC[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (TXR_META_EP));
+    
+
+    txc_engine_ultrascale
+        #(
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_DWORDS))
+    txc_engine_inst
+        (/*AUTOINST*/
+         // Outputs
+         .S_AXIS_CC_TVALID              (S_AXIS_CC_TVALID),
+         .S_AXIS_CC_TLAST               (S_AXIS_CC_TLAST),
+         .S_AXIS_CC_TDATA               (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
+         .TXC_DATA_READY                (TXC_DATA_READY),
+         .TXC_META_READY                (TXC_META_READY),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .CONFIG_COMPLETER_ID           (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
+         .S_AXIS_CC_TREADY              (S_AXIS_CC_TREADY),
+         .TXC_DATA_VALID                (TXC_DATA_VALID),
+         .TXC_DATA                      (TXC_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_START_FLAG           (TXC_DATA_START_FLAG),
+         .TXC_DATA_START_OFFSET         (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (TXC_DATA_END_FLAG),
+         .TXC_DATA_END_OFFSET           (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (TXC_META_VALID),
+         .TXC_META_FDWBE                (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (TXC_META_TAG[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (TXC_META_TC[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (TXC_META_EP));
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_hdr_fifo.v b/fpga/riffa_hdl/tx_hdr_fifo.v
new file mode 100644
index 0000000..e65b7a3
--- /dev/null
+++ b/fpga/riffa_hdl/tx_hdr_fifo.v
@@ -0,0 +1,181 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename: tx_hdr_fifo.v
+// Version: 1.0
+// Verilog Standard: Verilog-2001
+//
+// Description: The tx_hdr_fifo module implements a simple fifo for a packet
+// (WR_TX_HDR) header and three metadata signals: WR_TX_HDR_ABLANKS,
+// WR_TX_HDR_LEN, WR_TX_HDR_NOPAYLOAD. NOPAYLOAD indicates that the header is not
+// followed by a payload. HDR_LEN indicates the length of the header in
+// dwords. The ABLANKS signal indicates how many dwords should be inserted between
+// the header and payload.
+// 
+// The intended use for this module is between the interface specific tx formatter
+// (TXC or TXR) and the alignment pipeline, in parallel with the tx_data_pipeline
+// which contains a fifo for payloads.
+// 
+// Author: Dustin Richmond (@darichmond) 
+// Co-Authors:
+//----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "trellis.vh" // Defines the user-facing signal widths.
+module tx_hdr_fifo
+    #(parameter C_DEPTH_PACKETS = 10,
+      parameter C_MAX_HDR_WIDTH = 128,
+      parameter C_PIPELINE_OUTPUT = 1,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_VENDOR = "ALTERA"
+      )
+    (
+     // Interface: Clocks
+     input                          CLK,
+
+     // Interface: Reset
+     input                          RST_IN,
+
+     // Interface: WR_TX_HDR
+     input                          WR_TX_HDR_VALID,
+     input [(C_MAX_HDR_WIDTH)-1:0]  WR_TX_HDR,
+     input [`SIG_LEN_W-1:0]         WR_TX_HDR_PAYLOAD_LEN,
+     input [`SIG_NONPAY_W-1:0]      WR_TX_HDR_NONPAY_LEN,
+     input [`SIG_PACKETLEN_W-1:0]   WR_TX_HDR_PACKET_LEN,
+     input                          WR_TX_HDR_NOPAYLOAD,
+     output                         WR_TX_HDR_READY,
+
+     // Interface: RD_TX_HDR
+     output                         RD_TX_HDR_VALID,
+     output [(C_MAX_HDR_WIDTH)-1:0] RD_TX_HDR,
+     output [`SIG_LEN_W-1:0]        RD_TX_HDR_PAYLOAD_LEN,
+     output [`SIG_NONPAY_W-1:0]     RD_TX_HDR_NONPAY_LEN,
+     output [`SIG_PACKETLEN_W-1:0]  RD_TX_HDR_PACKET_LEN,
+     output                         RD_TX_HDR_NOPAYLOAD,
+     input                          RD_TX_HDR_READY
+     );
+
+    // Size of the header, plus the three metadata signals
+    localparam C_WIDTH = (C_MAX_HDR_WIDTH) + `SIG_NONPAY_W + `SIG_PACKETLEN_W + 1 + `SIG_LEN_W;
+
+    wire                            RST;
+
+    wire                            wWrTxHdrReady;
+    wire                            wWrTxHdrValid;
+    wire [(C_MAX_HDR_WIDTH)-1:0]    wWrTxHdr;
+    wire [`SIG_NONPAY_W-1:0]        wWrTxHdrNonpayLen;
+    wire [`SIG_PACKETLEN_W-1:0]     wWrTxHdrPacketLen;
+    wire [`SIG_LEN_W-1:0]           wWrTxHdrPayloadLen; 
+    wire                            wWrTxHdrNoPayload;
+
+    wire                            wRdTxHdrReady;
+    wire                            wRdTxHdrValid;
+    wire [C_MAX_HDR_WIDTH-1:0]      wRdTxHdr;
+    wire [`SIG_NONPAY_W-1:0]        wRdTxHdrNonpayLen;
+    wire [`SIG_PACKETLEN_W-1:0]     wRdTxHdrPacketLen;
+    wire [`SIG_LEN_W-1:0]           wRdTxHdrPayloadLen; 
+    wire                            wRdTxHdrNoPayload;
+
+    assign RST = RST_IN;
+
+    pipeline
+        #(
+          .C_DEPTH              (C_PIPELINE_INPUT?1:0),
+          .C_USE_MEMORY         (0),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_WIDTH                      (C_WIDTH))
+    input_pipeline_inst
+        (
+         // Outputs
+         .WR_DATA_READY         (WR_TX_HDR_READY),
+         .RD_DATA               ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
+         .RD_DATA_VALID         (wWrTxHdrValid),
+         // Inputs
+         .WR_DATA               ({WR_TX_HDR,WR_TX_HDR_NONPAY_LEN,WR_TX_HDR_PACKET_LEN,WR_TX_HDR_PAYLOAD_LEN,WR_TX_HDR_NOPAYLOAD}),
+         .WR_DATA_VALID         (WR_TX_HDR_VALID),
+         .RD_DATA_READY         (wWrTxHdrReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    fifo
+        #(
+          // Parameters
+          .C_DELAY             (0),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_WIDTH                      (C_WIDTH),
+          .C_DEPTH                      (C_DEPTH_PACKETS))
+    fifo_inst
+        (
+         // Outputs
+         .RD_DATA              ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
+         .WR_READY             (wWrTxHdrReady),
+         .RD_VALID             (wRdTxHdrValid),
+         // Inputs
+         .WR_DATA              ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
+         .WR_VALID             (wWrTxHdrValid),
+         .RD_READY             (wRdTxHdrReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST                           (RST));
+
+    pipeline
+        #(
+          .C_DEPTH              (C_PIPELINE_OUTPUT?1:0),
+          .C_USE_MEMORY         (0),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_WIDTH                      (C_WIDTH))
+    output_pipeline_inst
+        (
+         // Outputs
+         .WR_DATA_READY         (wRdTxHdrReady),
+         .RD_DATA               ({RD_TX_HDR,RD_TX_HDR_NONPAY_LEN,RD_TX_HDR_PACKET_LEN,RD_TX_HDR_PAYLOAD_LEN,RD_TX_HDR_NOPAYLOAD}),
+         .RD_DATA_VALID         (RD_TX_HDR_VALID),
+         // Inputs
+         .WR_DATA              ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
+         .WR_DATA_VALID         (wRdTxHdrValid),
+         .RD_DATA_READY         (RD_TX_HDR_READY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../common/")
+// End:
diff --git a/fpga/riffa_hdl/tx_multiplexer.v b/fpga/riffa_hdl/tx_multiplexer.v
new file mode 100644
index 0000000..bda4735
--- /dev/null
+++ b/fpga/riffa_hdl/tx_multiplexer.v
@@ -0,0 +1,263 @@
+`include "trellis.vh"
+module tx_multiplexer
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_NUM_CHNL = 12,
+      parameter C_TAG_WIDTH = 5,
+      parameter C_VENDOR = "ALTERA",
+      parameter C_DEPTH_PACKETS = 10
+      )
+    (
+     input                                     CLK,
+     input                                     RST_IN,
+
+     input [C_NUM_CHNL-1:0]                    WR_REQ, // Write request
+     input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]      WR_ADDR, // Write address
+     input [(C_NUM_CHNL*`SIG_LEN_W)-1:0]       WR_LEN, // Write data length
+     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
+     output [C_NUM_CHNL-1:0]                   WR_DATA_REN, // Write data read enable
+     output [C_NUM_CHNL-1:0]                   WR_ACK, // Write request has been accepted
+     output [C_NUM_CHNL-1:0]                   WR_SENT, // Write Reuqest has been sent to the core
+     
+     input [C_NUM_CHNL-1:0]                    RD_REQ, // Read request
+     input [(C_NUM_CHNL*2)-1:0]                RD_SG_CHNL, // Read request channel for scatter gather lists
+     input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]      RD_ADDR, // Read request address
+     input [(C_NUM_CHNL*`SIG_LEN_W)-1:0]       RD_LEN, // Read request length
+     output [C_NUM_CHNL-1:0]                   RD_ACK, // Read request has been accepted
+
+     output [5:0]                              INT_TAG, // Internal tag to exchange with external
+     output                                    INT_TAG_VALID, // High to signal tag exchange 
+     input [C_TAG_WIDTH-1:0]                   EXT_TAG, // External tag to provide in exchange for internal tag
+     input                                     EXT_TAG_VALID, // High to signal external tag is valid
+
+     output                                    TX_ENG_RD_REQ_SENT, // Read completion request issued
+     input                                     RXBUF_SPACE_AVAIL,
+     
+     // Interface: TXR Engine
+     output                                    TXR_DATA_VALID,
+     output [C_PCI_DATA_WIDTH-1:0]             TXR_DATA,
+     output                                    TXR_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_START_OFFSET,
+     output                                    TXR_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_END_OFFSET,
+     input                                     TXR_DATA_READY,
+
+     output                                    TXR_META_VALID,
+     output [`SIG_FBE_W-1:0]                   TXR_META_FDWBE, 
+     output [`SIG_LBE_W-1:0]                   TXR_META_LDWBE,
+     output [`SIG_ADDR_W-1:0]                  TXR_META_ADDR,
+     output [`SIG_LEN_W-1:0]                   TXR_META_LENGTH,
+     output [`SIG_TAG_W-1:0]                   TXR_META_TAG,
+     output [`SIG_TC_W-1:0]                    TXR_META_TC,
+     output [`SIG_ATTR_W-1:0]                  TXR_META_ATTR,
+     output [`SIG_TYPE_W-1:0]                  TXR_META_TYPE,
+     output                                    TXR_META_EP,
+     input                                     TXR_META_READY,
+     input                                     TXR_SENT);
+
+    wire [C_NUM_CHNL-1:0]                      wAckRdData;
+
+    reg [C_NUM_CHNL-1:0]                       rAckWrData; // Registered fifo input (only write acks)
+    reg [C_NUM_CHNL-1:0]                       rAckRdData; // Registered fifo output (only write acks)
+    reg                                        rAckWrEn,_rAckWrEn; // Fifo write enable (RD or WR_ACK)
+    reg                                        rAckRdEn; // Fifo read enable (TXR_SENT)
+
+    always @(*) begin
+        _rAckWrEn = (WR_ACK != 0) | (RD_ACK != 0);
+    end
+
+    always @(posedge CLK) begin
+        rAckWrData <= WR_ACK;
+        rAckWrEn <= _rAckWrEn;
+    end    
+
+    always @(posedge CLK) begin
+        rAckRdEn <= TXR_SENT;
+        if(rAckRdEn) begin
+            rAckRdData <= wAckRdData;
+        end else begin
+            rAckRdData <= 0;
+        end
+    end
+
+    assign WR_SENT = rAckRdData;
+    
+    fifo
+        #(// Parameters
+          .C_WIDTH                      (C_NUM_CHNL),
+          .C_DEPTH                      (C_DEPTH_PACKETS*3), // This is an extremely conservative estimate...
+          .C_DELAY                      (0)
+          /*AUTOINSTPARAM*/)
+    req_ack_fifo
+        (// Outputs
+         .WR_READY                      (),
+         .RD_DATA                       (wAckRdData),
+         .RD_VALID                      (),
+         // Inputs
+         .WR_DATA                       (rAckWrData),
+         .WR_VALID                      (rAckWrEn),
+         .RD_READY                      (rAckRdEn),
+         .RST                           (RST_IN),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK));
+
+    generate
+        if(C_PCI_DATA_WIDTH == 32) begin
+            tx_multiplexer_32 
+                #(/*AUTOINSTPARAM*/
+                  // Parameters
+                  .C_PCI_DATA_WIDTH     (C_PCI_DATA_WIDTH),
+                  .C_NUM_CHNL           (C_NUM_CHNL),
+                  .C_TAG_WIDTH          (C_TAG_WIDTH),
+                  .C_VENDOR             (C_VENDOR))
+            tx_mux 
+                (/*AUTOINST*/
+                 // Outputs
+                 .WR_DATA_REN           (WR_DATA_REN[C_NUM_CHNL-1:0]),
+                 .WR_ACK                (WR_ACK[C_NUM_CHNL-1:0]),
+                 .RD_ACK                (RD_ACK[C_NUM_CHNL-1:0]),
+                 .INT_TAG               (INT_TAG[5:0]),
+                 .INT_TAG_VALID         (INT_TAG_VALID),
+                 .TX_ENG_RD_REQ_SENT    (TX_ENG_RD_REQ_SENT),
+                 .TXR_DATA_VALID        (TXR_DATA_VALID),
+                 .TXR_DATA              (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
+                 .TXR_DATA_START_FLAG   (TXR_DATA_START_FLAG),
+                 .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TXR_DATA_END_FLAG     (TXR_DATA_END_FLAG),
+                 .TXR_DATA_END_OFFSET   (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TXR_META_VALID        (TXR_META_VALID),
+                 .TXR_META_FDWBE        (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
+                 .TXR_META_LDWBE        (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
+                 .TXR_META_ADDR         (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
+                 .TXR_META_LENGTH       (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
+                 .TXR_META_TAG          (TXR_META_TAG[`SIG_TAG_W-1:0]),
+                 .TXR_META_TC           (TXR_META_TC[`SIG_TC_W-1:0]),
+                 .TXR_META_ATTR         (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
+                 .TXR_META_TYPE         (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
+                 .TXR_META_EP           (TXR_META_EP),
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST_IN                (RST_IN),
+                 .WR_REQ                (WR_REQ[C_NUM_CHNL-1:0]),
+                 .WR_ADDR               (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
+                 .WR_LEN                (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
+                 .WR_DATA               (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+                 .RD_REQ                (RD_REQ[C_NUM_CHNL-1:0]),
+                 .RD_SG_CHNL            (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
+                 .RD_ADDR               (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
+                 .RD_LEN                (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
+                 .EXT_TAG               (EXT_TAG[C_TAG_WIDTH-1:0]),
+                 .EXT_TAG_VALID         (EXT_TAG_VALID),
+                 .RXBUF_SPACE_AVAIL     (RXBUF_SPACE_AVAIL),
+                 .TXR_DATA_READY        (TXR_DATA_READY),
+                 .TXR_META_READY        (TXR_META_READY));
+            
+        end else if(C_PCI_DATA_WIDTH == 64) begin
+
+            tx_multiplexer_64 
+                #(/*AUTOINSTPARAM*/
+                  // Parameters
+                  .C_PCI_DATA_WIDTH     (C_PCI_DATA_WIDTH),
+                  .C_NUM_CHNL           (C_NUM_CHNL),
+                  .C_TAG_WIDTH          (C_TAG_WIDTH),
+                  .C_VENDOR             (C_VENDOR))
+            tx_mux 
+                (/*AUTOINST*/
+                 // Outputs
+                 .WR_DATA_REN           (WR_DATA_REN[C_NUM_CHNL-1:0]),
+                 .WR_ACK                (WR_ACK[C_NUM_CHNL-1:0]),
+                 .RD_ACK                (RD_ACK[C_NUM_CHNL-1:0]),
+                 .INT_TAG               (INT_TAG[5:0]),
+                 .INT_TAG_VALID         (INT_TAG_VALID),
+                 .TX_ENG_RD_REQ_SENT    (TX_ENG_RD_REQ_SENT),
+                 .TXR_DATA_VALID        (TXR_DATA_VALID),
+                 .TXR_DATA              (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
+                 .TXR_DATA_START_FLAG   (TXR_DATA_START_FLAG),
+                 .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TXR_DATA_END_FLAG     (TXR_DATA_END_FLAG),
+                 .TXR_DATA_END_OFFSET   (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TXR_META_VALID        (TXR_META_VALID),
+                 .TXR_META_FDWBE        (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
+                 .TXR_META_LDWBE        (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
+                 .TXR_META_ADDR         (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
+                 .TXR_META_LENGTH       (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
+                 .TXR_META_TAG          (TXR_META_TAG[`SIG_TAG_W-1:0]),
+                 .TXR_META_TC           (TXR_META_TC[`SIG_TC_W-1:0]),
+                 .TXR_META_ATTR         (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
+                 .TXR_META_TYPE         (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
+                 .TXR_META_EP           (TXR_META_EP),
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST_IN                (RST_IN),
+                 .WR_REQ                (WR_REQ[C_NUM_CHNL-1:0]),
+                 .WR_ADDR               (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
+                 .WR_LEN                (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
+                 .WR_DATA               (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+                 .RD_REQ                (RD_REQ[C_NUM_CHNL-1:0]),
+                 .RD_SG_CHNL            (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
+                 .RD_ADDR               (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
+                 .RD_LEN                (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
+                 .EXT_TAG               (EXT_TAG[C_TAG_WIDTH-1:0]),
+                 .EXT_TAG_VALID         (EXT_TAG_VALID),
+                 .RXBUF_SPACE_AVAIL     (RXBUF_SPACE_AVAIL),
+                 .TXR_DATA_READY        (TXR_DATA_READY),
+                 .TXR_META_READY        (TXR_META_READY));
+
+        end else if(C_PCI_DATA_WIDTH == 128) begin
+
+            tx_multiplexer_128
+                #(/*AUTOINSTPARAM*/
+                  // Parameters
+                  .C_PCI_DATA_WIDTH     (C_PCI_DATA_WIDTH),
+                  .C_NUM_CHNL           (C_NUM_CHNL),
+                  .C_TAG_WIDTH          (C_TAG_WIDTH),
+                  .C_VENDOR             (C_VENDOR))
+            tx_mux_128_inst
+                (/*AUTOINST*/
+                 // Outputs
+                 .WR_DATA_REN           (WR_DATA_REN[C_NUM_CHNL-1:0]),
+                 .WR_ACK                (WR_ACK[C_NUM_CHNL-1:0]),
+                 .RD_ACK                (RD_ACK[C_NUM_CHNL-1:0]),
+                 .INT_TAG               (INT_TAG[5:0]),
+                 .INT_TAG_VALID         (INT_TAG_VALID),
+                 .TX_ENG_RD_REQ_SENT    (TX_ENG_RD_REQ_SENT),
+                 .TXR_DATA_VALID        (TXR_DATA_VALID),
+                 .TXR_DATA              (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
+                 .TXR_DATA_START_FLAG   (TXR_DATA_START_FLAG),
+                 .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TXR_DATA_END_FLAG     (TXR_DATA_END_FLAG),
+                 .TXR_DATA_END_OFFSET   (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+                 .TXR_META_VALID        (TXR_META_VALID),
+                 .TXR_META_FDWBE        (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
+                 .TXR_META_LDWBE        (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
+                 .TXR_META_ADDR         (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
+                 .TXR_META_LENGTH       (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
+                 .TXR_META_TAG          (TXR_META_TAG[`SIG_TAG_W-1:0]),
+                 .TXR_META_TC           (TXR_META_TC[`SIG_TC_W-1:0]),
+                 .TXR_META_ATTR         (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
+                 .TXR_META_TYPE         (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
+                 .TXR_META_EP           (TXR_META_EP),
+                 // Inputs
+                 .CLK                   (CLK),
+                 .RST_IN                (RST_IN),
+                 .WR_REQ                (WR_REQ[C_NUM_CHNL-1:0]),
+                 .WR_ADDR               (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
+                 .WR_LEN                (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
+                 .WR_DATA               (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+                 .RD_REQ                (RD_REQ[C_NUM_CHNL-1:0]),
+                 .RD_SG_CHNL            (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
+                 .RD_ADDR               (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
+                 .RD_LEN                (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
+                 .EXT_TAG               (EXT_TAG[C_TAG_WIDTH-1:0]),
+                 .EXT_TAG_VALID         (EXT_TAG_VALID),
+                 .RXBUF_SPACE_AVAIL     (RXBUF_SPACE_AVAIL),
+                 .TXR_DATA_READY        (TXR_DATA_READY),
+                 .TXR_META_READY        (TXR_META_READY));
+
+        end 
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "registers/" "../common/")
+// End:
diff --git a/fpga/riffa_hdl/tx_multiplexer_128.v b/fpga/riffa_hdl/tx_multiplexer_128.v
new file mode 100644
index 0000000..cb85d24
--- /dev/null
+++ b/fpga/riffa_hdl/tx_multiplexer_128.v
@@ -0,0 +1,370 @@
+`include "trellis.vh"
+`define S_TXENGUPR128_MAIN_IDLE     1'b0
+`define S_TXENGUPR128_MAIN_WR       1'b1
+
+`define S_TXENGUPR128_CAP_RD_WR     4'b0001
+`define S_TXENGUPR128_CAP_WR_RD     4'b0010
+`define S_TXENGUPR128_CAP_CAP       4'b0100
+`define S_TXENGUPR128_CAP_REL       4'b1000
+`timescale 1ns/1ns
+module tx_multiplexer_128 
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_NUM_CHNL = 12,
+      parameter C_TAG_WIDTH = 5,                             // Number of outstanding requests 
+      parameter C_VENDOR = "ALTERA"
+      )
+    (
+     input                                     CLK,
+     input                                     RST_IN,
+
+     input [C_NUM_CHNL-1:0]                    WR_REQ, // Write request
+     input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]      WR_ADDR, // Write address
+     input [(C_NUM_CHNL*`SIG_LEN_W)-1:0]       WR_LEN, // Write data length
+     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
+     output [C_NUM_CHNL-1:0]                   WR_DATA_REN, // Write data read enable
+     output [C_NUM_CHNL-1:0]                   WR_ACK, // Write request has been accepted
+
+     input [C_NUM_CHNL-1:0]                    RD_REQ, // Read request
+     input [(C_NUM_CHNL*2)-1:0]                RD_SG_CHNL, // Read request channel for scatter gather lists
+     input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]      RD_ADDR, // Read request address
+     input [(C_NUM_CHNL*`SIG_LEN_W)-1:0]       RD_LEN, // Read request length
+     output [C_NUM_CHNL-1:0]                   RD_ACK, // Read request has been accepted
+
+     output [5:0]                              INT_TAG, // Internal tag to exchange with external
+     output                                    INT_TAG_VALID, // High to signal tag exchange 
+     input [C_TAG_WIDTH-1:0]                   EXT_TAG, // External tag to provide in exchange for internal tag
+     input                                     EXT_TAG_VALID, // High to signal external tag is valid
+
+     output                                    TX_ENG_RD_REQ_SENT, // Read completion request issued
+     input                                     RXBUF_SPACE_AVAIL,
+     
+     // Interface: TXR Engine
+     output                                    TXR_DATA_VALID,
+     output [C_PCI_DATA_WIDTH-1:0]             TXR_DATA,
+     output                                    TXR_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_START_OFFSET,
+     output                                    TXR_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_END_OFFSET,
+     input                                     TXR_DATA_READY,
+
+     output                                    TXR_META_VALID,
+     output [`SIG_FBE_W-1:0]                   TXR_META_FDWBE, 
+     output [`SIG_LBE_W-1:0]                   TXR_META_LDWBE,
+     output [`SIG_ADDR_W-1:0]                  TXR_META_ADDR,
+     output [`SIG_LEN_W-1:0]                   TXR_META_LENGTH,
+     output [`SIG_TAG_W-1:0]                   TXR_META_TAG,
+     output [`SIG_TC_W-1:0]                    TXR_META_TC,
+     output [`SIG_ATTR_W-1:0]                  TXR_META_ATTR,
+     output [`SIG_TYPE_W-1:0]                  TXR_META_TYPE,
+     output                                    TXR_META_EP,
+     input                                     TXR_META_READY);
+
+    localparam C_DATA_DELAY = 6;
+
+    reg                                        rMainState=`S_TXENGUPR128_MAIN_IDLE, _rMainState=`S_TXENGUPR128_MAIN_IDLE;
+    reg                                        rCountIsWr=0, _rCountIsWr=0;
+    reg [9:0]                                  rCountLen=0, _rCountLen=0;
+    reg [3:0]                                  rCountChnl=0, _rCountChnl=0;
+    reg [C_TAG_WIDTH-1:0]                      rCountTag=0, _rCountTag=0;
+    reg [61:0]                                 rCountAddr=62'd0, _rCountAddr=62'd0;
+    reg                                        rCountAddr64=0, _rCountAddr64=0;
+    reg [9:0]                                  rCount=0, _rCount=0;
+    reg                                        rCountDone=0, _rCountDone=0;
+    reg                                        rCountStart=0, _rCountStart=0;
+    reg                                        rCountValid=0, _rCountValid=0;
+    reg [C_NUM_CHNL-1:0]                       rWrDataRen=0, _rWrDataRen=0;
+
+    reg                                        rTxEngRdReqAck, _rTxEngRdReqAck;
+    
+    wire                                       wRdReq;
+    wire [3:0]                                 wRdReqChnl;
+    wire                                       wWrReq;
+    wire [3:0]                                 wWrReqChnl;
+    wire                                       wRdAck;
+
+    wire [3:0]                                 wCountChnl;
+    wire [11:0]                                wCountChnlShiftDW = (wCountChnl*C_PCI_DATA_WIDTH); // Mult can exceed 9 bits, so make this a wire
+    wire [63:0]                                wRdAddr;
+    wire [9:0]                                 wRdLen;
+    wire [1:0]                                 wRdSgChnl;
+    wire [63:0]                                wWrAddr;
+    wire [9:0]                                 wWrLen;
+    wire [C_PCI_DATA_WIDTH-1:0]                wWrData;
+    wire [C_PCI_DATA_WIDTH-1:0]                wWrDataSwap;
+
+    reg [3:0]                                  rRdChnl=0, _rRdChnl=0;
+    reg [61:0]                                 rRdAddr=62'd0, _rRdAddr=62'd0;
+    reg [9:0]                                  rRdLen=0, _rRdLen=0;
+    reg [1:0]                                  rRdSgChnl=0, _rRdSgChnl=0;
+    reg [3:0]                                  rWrChnl=0, _rWrChnl=0;
+    reg [61:0]                                 rWrAddr=62'd0, _rWrAddr=62'd0;
+    reg [9:0]                                  rWrLen=0, _rWrLen=0;
+    reg [C_PCI_DATA_WIDTH-1:0]                 rWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};
+
+    assign wRdAddr = RD_ADDR[wRdReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
+    assign wRdLen = RD_LEN[wRdReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
+    assign wRdSgChnl = RD_SG_CHNL[wRdReqChnl * 2 +: 2];
+    assign wWrAddr = WR_ADDR[wWrReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
+    assign wWrLen = WR_LEN[wWrReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
+    assign wWrData = WR_DATA[wCountChnl * C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
+
+    (* syn_encoding = "user" *)
+    (* fsm_encoding = "user" *)
+    reg     [3:0]                       rCapState=`S_TXENGUPR128_CAP_RD_WR, _rCapState=`S_TXENGUPR128_CAP_RD_WR;
+    reg [C_NUM_CHNL-1:0]                rRdAck=0, _rRdAck=0;
+    reg [C_NUM_CHNL-1:0]                rWrAck=0, _rWrAck=0;
+    reg                                 rIsWr=0, _rIsWr=0;
+    reg [5:0]                           rCapChnl=0, _rCapChnl=0;
+    reg [61:0]                          rCapAddr=62'd0, _rCapAddr=62'd0;
+    reg                                 rCapAddr64=0, _rCapAddr64=0;
+    reg [9:0]                           rCapLen=0, _rCapLen=0;
+    reg                                 rCapIsWr=0, _rCapIsWr=0;
+    reg                                 rExtTagReq=0, _rExtTagReq=0;
+    reg [C_TAG_WIDTH-1:0]               rExtTag=0, _rExtTag=0;
+
+    reg [C_DATA_DELAY-1:0]              rWnR=0, _rWnR=0;
+    reg [(C_DATA_DELAY*4)-1:0]          rChnl=0, _rChnl=0;
+    reg [(C_DATA_DELAY*8)-1:0]          rTag=0, _rTag=0;
+    reg [(C_DATA_DELAY*62)-1:0]         rAddr=0, _rAddr=0;
+    reg [C_DATA_DELAY-1:0]              rAddr64=0, _rAddr64=0;
+    reg [(C_DATA_DELAY*10)-1:0]         rLen=0, _rLen=0;
+    reg [C_DATA_DELAY-1:0]              rLenEQ1=0, _rLenEQ1=0;
+    reg [C_DATA_DELAY-1:0]              rValid=0, _rValid=0;
+    reg [C_DATA_DELAY-1:0]              rDone=0, _rDone=0;
+    reg [C_DATA_DELAY-1:0]              rStart=0, _rStart=0;
+
+    assign WR_DATA_REN = rWrDataRen;
+    assign WR_ACK = rWrAck;
+    assign RD_ACK = rRdAck;
+
+    assign INT_TAG = {rRdSgChnl, rRdChnl};
+    assign INT_TAG_VALID = rExtTagReq;
+
+    assign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;
+    assign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);
+
+    // Search for the next request so that we can move onto it immediately after
+    // the current channel has released its request.
+    tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST_IN), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));
+    tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST_IN), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));
+
+
+    // Buffer shift-selected channel request signals and FIFO data.
+    always @ (posedge CLK) begin
+        rRdChnl <= #1 _rRdChnl;
+        rRdAddr <= #1 _rRdAddr;
+        rRdLen <= #1 _rRdLen;
+        rRdSgChnl <= #1 _rRdSgChnl;
+        rWrChnl <= #1 _rWrChnl;
+        rWrAddr <= #1 _rWrAddr;
+        rWrLen <= #1 _rWrLen;
+        rWrData <= #1 _rWrData;
+    end
+
+    always @ (*) begin
+        _rRdChnl = wRdReqChnl;
+        _rRdAddr = wRdAddr[63:2];
+        _rRdLen = wRdLen;
+        _rRdSgChnl = wRdSgChnl;
+        _rWrChnl = wWrReqChnl;
+        _rWrAddr = wWrAddr[63:2];
+        _rWrLen = wWrLen;
+        _rWrData = wWrData;
+    end
+
+    // Accept requests when the selector indicates. Capture the buffered 
+    // request parameters for hand-off to the formatting pipeline. Then
+    // acknowledge the receipt to the channel so it can deassert the 
+    // request, and let the selector choose another channel.
+    always @ (posedge CLK) begin
+        rCapState <= #1 (RST_IN ? `S_TXENGUPR128_CAP_RD_WR : _rCapState);
+        rRdAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rRdAck);
+        rWrAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rWrAck);
+        rIsWr <= #1 _rIsWr;
+        rCapChnl <= #1 _rCapChnl;
+        rCapAddr <= #1 _rCapAddr;
+        rCapAddr64 <= #1 _rCapAddr64;
+        rCapLen <= #1 _rCapLen;
+        rCapIsWr <= #1 _rCapIsWr;
+        rExtTagReq <= #1 _rExtTagReq;
+        rExtTag <= #1 _rExtTag;
+        rTxEngRdReqAck <= #1 _rTxEngRdReqAck;
+    end
+
+    always @ (*) begin
+        _rCapState = rCapState;
+        _rRdAck = rRdAck;
+        _rWrAck = rWrAck;
+        _rIsWr = rIsWr;
+        _rCapChnl = rCapChnl;
+        _rCapAddr = rCapAddr;
+        _rCapAddr64 = rCapAddr64;
+        _rCapLen = rCapLen;
+        _rCapIsWr = rCapIsWr;
+        _rExtTagReq = rExtTagReq;
+        _rExtTag = rExtTag;
+        _rTxEngRdReqAck = rTxEngRdReqAck;
+
+        case (rCapState) 
+
+            `S_TXENGUPR128_CAP_RD_WR : begin
+                _rIsWr = !wRdReq;
+                _rRdAck = ((wRdAck)<<wRdReqChnl);
+                _rTxEngRdReqAck = wRdAck;
+                _rExtTagReq = wRdAck;
+                _rCapState = (wRdAck ? `S_TXENGUPR128_CAP_CAP : `S_TXENGUPR128_CAP_WR_RD);
+            end
+
+            `S_TXENGUPR128_CAP_WR_RD : begin
+                _rIsWr = wWrReq;
+                _rWrAck = (wWrReq<<wWrReqChnl);
+                _rCapState = (wWrReq ? `S_TXENGUPR128_CAP_CAP : `S_TXENGUPR128_CAP_RD_WR);
+            end
+
+            `S_TXENGUPR128_CAP_CAP : begin
+                _rTxEngRdReqAck = 0;
+                _rRdAck = 0;
+                _rWrAck = 0;
+                _rCapIsWr = rIsWr;
+                _rExtTagReq = 0;
+                _rExtTag = EXT_TAG ^ {rIsWr,{(C_TAG_WIDTH-1){1'b0}}};
+                if (rIsWr) begin
+                    _rCapChnl = {2'd0, rWrChnl};
+                    _rCapAddr = rWrAddr;
+                    _rCapAddr64 = (rWrAddr[61:30] != 0);
+                    _rCapLen = rWrLen;
+                end
+                else begin
+                    _rCapChnl = {rRdSgChnl, rRdChnl};
+                    _rCapAddr = rRdAddr;
+                    _rCapAddr64 = (rRdAddr[61:30] != 0);
+                    _rCapLen = rRdLen;
+                end
+                _rCapState = `S_TXENGUPR128_CAP_REL;
+            end
+            
+            `S_TXENGUPR128_CAP_REL : begin
+                // Push into the formatting pipeline when ready
+                if (TXR_META_READY & !rMainState) begin // S_TXENGUPR128_MAIN_IDLE
+                    _rCapState = (`S_TXENGUPR128_CAP_WR_RD>>(rCapIsWr)); // Changes to S_TXENGUPR128_CAP_RD_WR
+                end
+            end
+            
+            default : begin
+                _rCapState = `S_TXENGUPR128_CAP_RD_WR;
+            end
+            
+        endcase
+    end
+
+    // Start the read/write when space is available in the output FIFO and when
+    // request parameters have been captured (i.e. a pending request).
+    always @ (posedge CLK) begin
+        rMainState <= #1 (RST_IN ? `S_TXENGUPR128_MAIN_IDLE : _rMainState);
+        rCountIsWr <= #1 _rCountIsWr;
+        rCountLen <= #1 _rCountLen;
+        rCountChnl <= #1 _rCountChnl;
+        rCountTag <= #1 _rCountTag;
+        rCountAddr <= #1 _rCountAddr;
+        rCountAddr64 <= #1 _rCountAddr64;
+        rCount <= #1 _rCount;
+        rCountDone <= #1 _rCountDone;
+        rCountStart <= #1 _rCountStart;
+        rCountValid <= #1 _rCountValid;
+        rWrDataRen <= #1 _rWrDataRen;
+    end
+
+    always @ (*) begin
+        _rMainState = rMainState;
+        _rCountIsWr = rCountIsWr;
+        _rCountLen = rCountLen;
+        _rCountChnl = rCountChnl;
+        _rCountTag = rCountTag;
+        _rCountAddr = rCountAddr;
+        _rCountAddr64 = rCountAddr64;
+        _rCount = rCount;
+        _rCountDone = rCountDone;
+        _rCountValid = rCountValid;
+        _rWrDataRen = rWrDataRen;
+        _rCountStart = 0;
+        case (rMainState) 
+
+            `S_TXENGUPR128_MAIN_IDLE : begin
+                _rCountIsWr = rCapIsWr;
+                _rCountLen = rCapLen;
+                _rCountChnl = rCapChnl[3:0];
+                _rCountTag = rExtTag;
+                _rCountAddr = rCapAddr;
+                _rCountAddr64 = rCapAddr64;
+                _rCount = rCapLen;
+                _rCountDone = (rCapLen <= 3'd4);
+                _rWrDataRen = ((TXR_META_READY & rCapState[3] & rCapIsWr)<<(rCapChnl[3:0])); // S_TXENGUPR128_CAP_REL
+                _rCountValid = (TXR_META_READY & rCapState[3]);
+                _rCountStart = (TXR_META_READY & rCapState[3]);
+                if (TXR_META_READY && rCapState[3] && rCapIsWr && (rCapAddr64 || (rCapLen != 10'd1))) // S_TXENGUPR128_CAP_REL
+                    _rMainState = `S_TXENGUPR128_MAIN_WR;
+            end
+
+            `S_TXENGUPR128_MAIN_WR : begin
+                _rCount = rCount - 3'd4;
+                _rCountDone = (rCount <= 4'd8);
+                if (rCountDone) begin
+                    _rWrDataRen = 0;
+                    _rCountValid = 0;
+                    _rMainState = `S_TXENGUPR128_MAIN_IDLE;
+                end
+            end
+            
+        endcase
+    end
+
+
+    // Shift in the captured parameters and valid signal every cycle.
+    // This pipeline will keep the formatter busy.
+    assign wCountChnl = rChnl[(C_DATA_DELAY-2)*4 +:4];
+    always @ (posedge CLK) begin
+        rWnR <= #1 _rWnR;
+        rChnl <= #1 _rChnl;
+        rTag <= #1 _rTag;
+        rAddr <= #1 _rAddr;
+        rAddr64 <= #1 _rAddr64;
+        rLen <= #1 _rLen;
+        rLenEQ1 <= #1 _rLenEQ1;
+        rValid <= #1 _rValid;
+        rDone <= #1 _rDone;
+        rStart <= #1 _rStart;
+    end
+
+    always @ (*) begin
+        _rWnR = {rWnR[((C_DATA_DELAY-1)*1)-1:0], rCountIsWr};
+        _rChnl = {rChnl[((C_DATA_DELAY-1)*4)-1:0], rCountChnl};
+        _rTag = {rTag[((C_DATA_DELAY-1)*8)-1:0], (8'd0 | rCountTag)};
+        _rAddr = {rAddr[((C_DATA_DELAY-1)*62)-1:0], rCountAddr};
+        _rAddr64 = {rAddr64[((C_DATA_DELAY-1)*1)-1:0], rCountAddr64};
+        _rLen = {rLen[((C_DATA_DELAY-1)*10)-1:0], rCountLen};
+        _rLenEQ1 = {rLenEQ1[((C_DATA_DELAY-1)*1)-1:0], (rCountLen == 10'd1)};
+        _rValid = {rValid[((C_DATA_DELAY-1)*1)-1:0], rCountValid & rCountIsWr};
+        _rDone = {rDone[((C_DATA_DELAY-1)*1)-1:0], rCountDone};
+        _rStart = {rStart[((C_DATA_DELAY-1)*1)-1:0], rCountStart};
+    end // always @ begin
+
+    assign TXR_DATA = rWrData;
+    assign TXR_DATA_VALID = rValid[(C_DATA_DELAY-1)*1 +:1];
+    assign TXR_DATA_START_FLAG = rStart[(C_DATA_DELAY-1)*1 +:1];
+    assign TXR_DATA_START_OFFSET = 0;
+    assign TXR_DATA_END_FLAG = rDone[(C_DATA_DELAY-1)*1 +:1];
+    assign TXR_DATA_END_OFFSET = rLen[(C_DATA_DELAY-1)*10 +:`SIG_OFFSET_W] - 1;
+
+    assign TXR_META_VALID = rCountStart;
+    assign TXR_META_TYPE = rCountIsWr ? `TRLS_REQ_WR : `TRLS_REQ_RD;
+    assign TXR_META_ADDR = {rCountAddr,2'b00};
+    assign TXR_META_LENGTH = rCountLen;
+    assign TXR_META_LDWBE = rCountLen == 10'd1 ? 0 : 4'b1111;
+    assign TXR_META_FDWBE = 4'b1111;
+    assign TXR_META_TAG = rCountTag;
+    assign TXR_META_EP = 1'b0;
+    assign TXR_META_ATTR = 3'b110;
+    assign TXR_META_TC = 0;
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_multiplexer_32.v b/fpga/riffa_hdl/tx_multiplexer_32.v
new file mode 100644
index 0000000..536134b
--- /dev/null
+++ b/fpga/riffa_hdl/tx_multiplexer_32.v
@@ -0,0 +1,410 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+`define FMT_TXENGUPR32_WR32 7'b10_00000
+`define FMT_TXENGUPR32_RD32 7'b00_00000
+`define FMT_TXENGUPR32_WR64 7'b11_00000
+`define FMT_TXENGUPR32_RD64 7'b01_00000
+
+`define S_TXENGUPR32_MAIN_IDLE      6'b00_0001
+`define S_TXENGUPR32_MAIN_RD        6'b00_0010
+`define S_TXENGUPR32_MAIN_WR        6'b00_0100
+`define S_TXENGUPR32_MAIN_WAIT_0    6'b00_1000
+`define S_TXENGUPR32_MAIN_WAIT_1    6'b01_0000
+`define S_TXENGUPR32_MAIN_WAIT_2    6'b10_0000
+
+`define S_TXENGUPR32_CAP_RD_WR      4'b0001
+`define S_TXENGUPR32_CAP_WR_RD      4'b0010
+`define S_TXENGUPR32_CAP_CAP        4'b0100
+`define S_TXENGUPR32_CAP_REL        4'b1000
+`include "trellis.vh"
+`timescale 1ns/1ns
+module tx_multiplexer_32 
+    #(
+      parameter C_PCI_DATA_WIDTH = 9'd32,
+      parameter C_NUM_CHNL = 4'd12,
+      parameter C_TAG_WIDTH = 5, // Number of outstanding requests
+      parameter C_VENDOR = "XILINX"
+      )
+    (
+     input                                     CLK,
+     input                                     RST_IN,
+
+     input [C_NUM_CHNL-1:0]                    WR_REQ, // Write request
+     input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]      WR_ADDR, // Write address
+     input [(C_NUM_CHNL*`SIG_LEN_W)-1:0]       WR_LEN, // Write data length
+     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
+     output [C_NUM_CHNL-1:0]                   WR_DATA_REN, // Write data read enable
+     output [C_NUM_CHNL-1:0]                   WR_ACK, // Write request has been accepted
+
+     input [C_NUM_CHNL-1:0]                    RD_REQ, // Read request
+     input [(C_NUM_CHNL*2)-1:0]                RD_SG_CHNL, // Read request channel for scatter gather lists
+     input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]      RD_ADDR, // Read request address
+     input [(C_NUM_CHNL*`SIG_LEN_W)-1:0]       RD_LEN, // Read request length
+     output [C_NUM_CHNL-1:0]                   RD_ACK, // Read request has been accepted
+
+     output [5:0]                              INT_TAG, // Internal tag to exchange with external
+     output                                    INT_TAG_VALID, // High to signal tag exchange 
+     input [C_TAG_WIDTH-1:0]                   EXT_TAG, // External tag to provide in exchange for internal tag
+     input                                     EXT_TAG_VALID, // High to signal external tag is valid
+
+     output                                    TX_ENG_RD_REQ_SENT, // Read completion request issued
+     input                                     RXBUF_SPACE_AVAIL,
+
+     // Interface: TXR Engine
+     output                                    TXR_DATA_VALID,
+     output [C_PCI_DATA_WIDTH-1:0]             TXR_DATA,
+     output                                    TXR_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_START_OFFSET,
+     output                                    TXR_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_END_OFFSET,
+     input                                     TXR_DATA_READY,
+
+     output                                    TXR_META_VALID,
+     output [`SIG_FBE_W-1:0]                   TXR_META_FDWBE, 
+     output [`SIG_LBE_W-1:0]                   TXR_META_LDWBE,
+     output [`SIG_ADDR_W-1:0]                  TXR_META_ADDR,
+     output [`SIG_LEN_W-1:0]                   TXR_META_LENGTH,
+     output [`SIG_TAG_W-1:0]                   TXR_META_TAG,
+     output [`SIG_TC_W-1:0]                    TXR_META_TC,
+     output [`SIG_ATTR_W-1:0]                  TXR_META_ATTR,
+     output [`SIG_TYPE_W-1:0]                  TXR_META_TYPE,
+     output                                    TXR_META_EP,
+     input                                     TXR_META_READY
+     );
+
+    // Local parameters
+    localparam C_DATA_DELAY = 6'd1; // Delays read/write params to accommodate tx_port_buffer delay and tx_engine_formatter delay.
+
+    (* syn_encoding = "user" *)
+    (* fsm_encoding = "user" *)
+    reg [5:0]                                  rMainState=`S_TXENGUPR32_MAIN_IDLE, _rMainState=`S_TXENGUPR32_MAIN_IDLE;
+    reg [3:0]                                  rCountChnl=0, _rCountChnl=0;
+    reg [C_TAG_WIDTH-1:0]                      rCountTag=0, _rCountTag=0;
+    reg [9:0]                                  rCount=0, _rCount=0;
+    reg                                        rCountDone=0, _rCountDone=0;
+    reg                                        rCountStart=0, _rCountStart=0;
+    reg                                        rCount32=0, _rCount32=0;
+    reg [C_NUM_CHNL-1:0]                       rWrDataRen=0, _rWrDataRen=0;
+
+    reg                                        rTxEngRdReqAck, _rTxEngRdReqAck;
+    
+    wire                                       wRdReq;
+    wire [3:0]                                 wRdReqChnl;
+    wire                                       wWrReq;
+    wire [3:0]                                 wWrReqChnl;
+    wire                                       wRdAck;
+
+    wire [3:0]                                 wCountChnl;
+    wire [11:0]                                wCountChnlShiftDW = (wCountChnl*C_PCI_DATA_WIDTH); // Mult can exceed 9 bits, so make this a wire
+    wire [63:0]                                wRdAddr;
+    wire [9:0]                                 wRdLen;
+    wire [1:0]                                 wRdSgChnl;
+    wire [63:0]                                wWrAddr;
+    wire [9:0]                                 wWrLen;
+    wire [C_PCI_DATA_WIDTH-1:0]                wWrData;
+
+    reg [3:0]                                  rRdChnl=0, _rRdChnl=0;
+    reg [61:0]                                 rRdAddr=62'd0, _rRdAddr=62'd0;
+    reg [9:0]                                  rRdLen=0, _rRdLen=0;
+    reg [1:0]                                  rRdSgChnl=0, _rRdSgChnl=0;
+    reg [3:0]                                  rWrChnl=0, _rWrChnl=0;
+    reg [61:0]                                 rWrAddr=62'd0, _rWrAddr=62'd0;
+    reg [9:0]                                  rWrLen=0, _rWrLen=0;
+    reg [C_PCI_DATA_WIDTH-1:0]                 rWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};
+
+    (* syn_encoding = "user" *)
+    (* fsm_encoding = "user" *)
+    reg [3:0]                                  rCapState=`S_TXENGUPR32_CAP_RD_WR, _rCapState=`S_TXENGUPR32_CAP_RD_WR;
+    reg [C_NUM_CHNL-1:0]                       rRdAck=0, _rRdAck=0;
+    reg [C_NUM_CHNL-1:0]                       rWrAck=0, _rWrAck=0;
+    reg                                        rIsWr=0, _rIsWr=0;
+    reg [5:0]                                  rCapChnl=0, _rCapChnl=0;
+    reg [61:0]                                 rCapAddr=62'd0, _rCapAddr=62'd0;
+    reg                                        rCapAddr64=0, _rCapAddr64=0;
+    reg [9:0]                                  rCapLen=0, _rCapLen=0;
+    reg                                        rCapIsWr=0, _rCapIsWr=0;
+    reg                                        rExtTagReq=0, _rExtTagReq=0;
+    reg [C_TAG_WIDTH-1:0]                      rExtTag=0, _rExtTag=0;
+
+    reg [C_DATA_DELAY-1:0]                     rWnR=0, _rWnR=0;
+    reg [(C_DATA_DELAY*4)-1:0]                 rChnl=0, _rChnl=0;
+    reg [(C_DATA_DELAY*8)-1:0]                 rTag=0, _rTag=0;
+    reg [(C_DATA_DELAY*62)-1:0]                rAddr=0, _rAddr=0;
+    reg [C_DATA_DELAY-1:0]                     rAddr64=0, _rAddr64=0;
+    reg [(C_DATA_DELAY*10)-1:0]                rLen=0, _rLen=0;
+    reg [C_DATA_DELAY-1:0]                     rLenEQ1=0, _rLenEQ1=0;
+    reg [C_DATA_DELAY-1:0]                     rValid=0, _rValid=0;
+    reg [C_DATA_DELAY-1:0]                     rDone=0, _rDone=0;
+    reg [C_DATA_DELAY-1:0]                     rStart=0, _rStart=0;
+
+    assign wRdAddr = RD_ADDR[wRdReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
+    assign wRdLen = RD_LEN[wRdReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
+    assign wRdSgChnl = RD_SG_CHNL[wRdReqChnl * 2 +: 2];
+    assign wWrAddr = WR_ADDR[wWrReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
+    assign wWrLen = WR_LEN[wWrReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
+    assign wWrData = WR_DATA[wCountChnl * C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
+
+    assign WR_DATA_REN = rWrDataRen;
+    assign WR_ACK = rWrAck;
+    assign RD_ACK = rRdAck;
+
+    assign INT_TAG = {rRdSgChnl, rRdChnl};
+    assign INT_TAG_VALID = rExtTagReq;
+
+    assign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;
+    assign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);
+
+    // Search for the next request so that we can move onto it immediately after
+    // the current channel has released its request.
+    tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST_IN), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));
+    tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST_IN), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));
+
+    // Buffer shift-selected channel request signals and FIFO data.
+    always @ (posedge CLK) begin
+        rRdChnl <= #1 _rRdChnl;
+        rRdAddr <= #1 _rRdAddr;
+        rRdLen <= #1 _rRdLen;
+        rRdSgChnl <= #1 _rRdSgChnl;
+        rWrChnl <= #1 _rWrChnl;
+        rWrAddr <= #1 _rWrAddr;
+        rWrLen <= #1 _rWrLen;
+        rWrData <= #1 _rWrData;
+    end
+
+    always @ (*) begin
+        _rRdChnl = wRdReqChnl;
+        _rRdAddr = wRdAddr[63:2];
+        _rRdLen = wRdLen;
+        _rRdSgChnl = wRdSgChnl;
+        _rWrChnl = wWrReqChnl;
+        _rWrAddr = wWrAddr[63:2];
+        _rWrLen = wWrLen;
+        _rWrData = wWrData;
+    end
+
+    // Accept requests when the selector indicates. Capture the buffered 
+    // request parameters for hand-off to the formatting pipeline. Then
+    // acknowledge the receipt to the channel so it can deassert the 
+    // request, and let the selector choose another channel.
+    always @ (posedge CLK) begin
+        rCapState <= #1 (RST_IN ? `S_TXENGUPR32_CAP_RD_WR : _rCapState);
+        rRdAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rRdAck);
+        rWrAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rWrAck);
+        rIsWr <= #1 _rIsWr;
+        rCapChnl <= #1 _rCapChnl;
+        rCapAddr <= #1 _rCapAddr;
+        rCapAddr64 <= #1 _rCapAddr64;
+        rCapLen <= #1 _rCapLen;
+        rCapIsWr <= #1 _rCapIsWr;
+        rExtTagReq <= #1 _rExtTagReq;
+        rExtTag <= #1 _rExtTag;
+        rTxEngRdReqAck <= #1 _rTxEngRdReqAck;
+    end
+
+    always @ (*) begin
+        _rCapState = rCapState;
+        _rRdAck = rRdAck;
+        _rWrAck = rWrAck;
+        _rIsWr = rIsWr;
+        _rCapChnl = rCapChnl;
+        _rCapAddr = rCapAddr;
+        _rCapAddr64 = (rCapAddr[61:30] != 0);
+        _rCapLen = rCapLen;
+        _rCapIsWr = rCapIsWr;
+        _rExtTagReq = rExtTagReq;
+        _rExtTag = rExtTag;
+        _rTxEngRdReqAck = rTxEngRdReqAck;
+        
+        case (rCapState) 
+
+            `S_TXENGUPR32_CAP_RD_WR : begin
+                _rIsWr = !wRdReq;
+                _rRdAck = ((wRdAck)<<wRdReqChnl);
+                _rTxEngRdReqAck = wRdAck;
+                _rExtTagReq = wRdAck;
+                _rCapState = (wRdAck ? `S_TXENGUPR32_CAP_CAP : `S_TXENGUPR32_CAP_WR_RD);
+            end
+
+            `S_TXENGUPR32_CAP_WR_RD : begin
+                _rIsWr = wWrReq;
+                _rWrAck = (wWrReq<<wWrReqChnl);
+                _rCapState = (wWrReq ? `S_TXENGUPR32_CAP_CAP : `S_TXENGUPR32_CAP_RD_WR);
+            end
+
+            `S_TXENGUPR32_CAP_CAP : begin
+                _rTxEngRdReqAck = 0;
+                _rRdAck = 0;
+                _rWrAck = 0;
+                _rCapIsWr = rIsWr;
+                _rExtTagReq = 0;
+                _rExtTag = EXT_TAG;
+                if (rIsWr) begin
+                    _rCapChnl = {2'd0, rWrChnl};
+                    _rCapAddr = rWrAddr;
+                    _rCapLen = rWrLen;
+                end
+                else begin
+                    _rCapChnl = {rRdSgChnl, rRdChnl};
+                    _rCapAddr = rRdAddr;
+                    _rCapLen = rRdLen;
+                end
+                _rCapState = `S_TXENGUPR32_CAP_REL;
+            end
+            
+            `S_TXENGUPR32_CAP_REL : begin
+                // Push into the formatting pipeline when ready
+                if (TXR_META_READY & rMainState[0]) // S_TXENGUPR32_MAIN_IDLE
+                    _rCapState = (`S_TXENGUPR32_CAP_WR_RD>>(rCapIsWr)); // Changes to S_TXENGUPR32_CAP_RD_WR
+            end
+            
+            default : begin
+                _rCapState = `S_TXENGUPR32_CAP_RD_WR;
+            end
+            
+        endcase
+    end
+
+
+    // Start the read/write when space is available in the output FIFO and when
+    // request parameters have been captured (i.e. a pending request).
+    always @ (posedge CLK) begin
+        rMainState <= #1 (RST_IN ? `S_TXENGUPR32_MAIN_IDLE : _rMainState);
+        rCount <= #1 _rCount;
+        rCountDone <= #1 _rCountDone;
+        rCountStart <= #1 _rCountStart;
+        rCountChnl <= #1 _rCountChnl;
+        rCountTag <= #1 _rCountTag;
+        rCount32 <= #1 _rCount32;
+        rWrDataRen <= #1 _rWrDataRen;
+    end
+
+    always @ (*) begin
+        _rMainState = rMainState;
+        _rCount = rCount;
+        _rCountDone = rCountDone;
+        _rCountChnl = rCountChnl;
+        _rCountTag = rCountTag;
+        _rCount32 = rCount32;
+        _rWrDataRen = rWrDataRen;
+        _rCountStart = 0;
+        case (rMainState) 
+
+            `S_TXENGUPR32_MAIN_IDLE : begin
+                _rCount = rCapLen;
+                _rCountDone = (rCapLen == 10'd1);
+                _rCountChnl = rCapChnl[3:0];
+                _rCountTag = rExtTag;
+                _rCount32 = (rCapAddr[61:30] == 0);
+                _rWrDataRen = ((TXR_META_READY & rCapState[3] & rCapIsWr)<<(rCapChnl[3:0])); // S_TXENGUPR32_CAP_REL
+                _rCountStart = (TXR_META_READY & rCapState[3]);
+                if (TXR_META_READY & rCapState[3]) // S_TXENGUPR32_CAP_REL
+                    _rMainState = (`S_TXENGUPR32_MAIN_RD<<(rCapIsWr)); // Change to S_TXENGUPR32_MAIN_WR;
+            end
+
+            `S_TXENGUPR32_MAIN_RD : begin
+                _rMainState = (`S_TXENGUPR32_MAIN_WAIT_1<<(rCount32)); // Change to S_TXENGUPR32_MAIN_WAIT_2
+            end
+
+            `S_TXENGUPR32_MAIN_WR : begin
+                _rCount = rCount - 1'd1;
+                _rCountDone = (rCount == 2'd2);
+                if (rCountDone) begin
+                    _rWrDataRen = 0;
+                    _rMainState = (`S_TXENGUPR32_MAIN_WAIT_0<<(rCount32)); // Change to S_TXENGUPR32_MAIN_WAIT_1
+                end
+            end
+
+            `S_TXENGUPR32_MAIN_WAIT_0 : begin
+                _rMainState = `S_TXENGUPR32_MAIN_WAIT_1;
+            end
+            
+            `S_TXENGUPR32_MAIN_WAIT_1 : begin
+                _rMainState = `S_TXENGUPR32_MAIN_WAIT_2;
+            end
+            
+            `S_TXENGUPR32_MAIN_WAIT_2 : begin
+                _rMainState = `S_TXENGUPR32_MAIN_IDLE;
+            end
+            
+            default : begin
+                _rMainState = `S_TXENGUPR32_MAIN_IDLE;
+            end
+            
+        endcase
+    end
+
+    // Shift in the captured parameters and valid signal every cycle.
+    // This pipeline will keep the formatter busy.
+    assign wCountChnl = rCountChnl[3:0];
+    always @ (posedge CLK) begin
+        rWnR <= #1 _rWnR;
+        rChnl <= #1 _rChnl;
+        rTag <= #1 _rTag;
+        rAddr <= #1 _rAddr;
+        rAddr64 <= #1 _rAddr64;
+        rLen <= #1 _rLen;
+        rLenEQ1 <= #1 _rLenEQ1;
+        rValid <= #1 _rValid;
+    end
+
+    always @ (*) begin
+        _rWnR = ((rWnR<<1) | rCapIsWr);
+        _rChnl = ((rChnl<<4) | rCountChnl);
+        _rTag = ((rTag<<8) | (8'd0 | rCountTag));
+        _rAddr = ((rAddr<<62) | rCapAddr);
+        _rAddr64 = ((rAddr64<<1) | rCapAddr64);
+        _rLen = ((rLen<<10) | rCapLen);
+        _rLenEQ1 = ((rLenEQ1<<1) | (rCapLen == 10'd1));
+        _rValid = ((rValid<<1) | (rMainState[2] | rMainState[1])); // S_TXENGUPR64_MAIN_RD | S_TXENGUPR64_MAIN_WR
+        _rDone = rDone<<1   | rCountDone;
+        _rStart = rStart<<1 | rCountStart;
+    end
+    assign TXR_DATA = rWrData;
+    assign TXR_DATA_VALID = rValid[(C_DATA_DELAY-1)*1 +:1];
+    assign TXR_DATA_START_FLAG = rStart[(C_DATA_DELAY-1)*1 +:1];
+    assign TXR_DATA_START_OFFSET = 0;
+    assign TXR_DATA_END_FLAG = rDone[(C_DATA_DELAY-1)*1 +:1];
+    assign TXR_DATA_END_OFFSET = rLen[(C_DATA_DELAY-1)*10 +:`SIG_OFFSET_W] - 1;
+    assign TXR_META_VALID = rCountStart;
+    assign TXR_META_TYPE = rCapIsWr ? `TRLS_REQ_WR : `TRLS_REQ_RD;
+    assign TXR_META_ADDR = {rCapAddr,2'b00};
+    assign TXR_META_LENGTH = rCapLen;
+    assign TXR_META_LDWBE = rCapLen == 10'd1 ? 0 : 4'b1111;
+    assign TXR_META_FDWBE = 4'b1111;
+    assign TXR_META_TAG = rCountTag;
+    assign TXR_META_EP = 1'b0;
+    assign TXR_META_ATTR = 3'b110;
+    assign TXR_META_TC = 0;
+endmodule
diff --git a/fpga/riffa_hdl/tx_multiplexer_64.v b/fpga/riffa_hdl/tx_multiplexer_64.v
new file mode 100644
index 0000000..7267a5c
--- /dev/null
+++ b/fpga/riffa_hdl/tx_multiplexer_64.v
@@ -0,0 +1,379 @@
+`define FMT_TXENGUPR64_WR32	7'b10_00000
+`define FMT_TXENGUPR64_RD32	7'b00_00000
+`define FMT_TXENGUPR64_WR64	7'b11_00000
+`define FMT_TXENGUPR64_RD64	7'b01_00000
+
+`define S_TXENGUPR64_MAIN_IDLE		4'b0001
+`define S_TXENGUPR64_MAIN_RD		4'b0010
+`define S_TXENGUPR64_MAIN_WR		4'b0100
+`define S_TXENGUPR64_MAIN_WAIT		4'b1000
+
+`define S_TXENGUPR64_CAP_RD_WR		4'b0001
+`define S_TXENGUPR64_CAP_WR_RD		4'b0010
+`define S_TXENGUPR64_CAP_CAP		4'b0100
+`define S_TXENGUPR64_CAP_REL		4'b1000
+`include "trellis.vh"
+`timescale 1ns/1ns
+module tx_multiplexer_64
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_NUM_CHNL = 12,
+      parameter C_TAG_WIDTH = 5,                             // Number of outstanding requests 
+      parameter C_VENDOR = "ALTERA"
+      )
+    (
+     input                                     CLK,
+     input                                     RST_IN,
+
+     input [C_NUM_CHNL-1:0]                    WR_REQ, // Write request
+     input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]      WR_ADDR, // Write address
+     input [(C_NUM_CHNL*`SIG_LEN_W)-1:0]       WR_LEN, // Write data length
+     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
+     output [C_NUM_CHNL-1:0]                   WR_DATA_REN, // Write data read enable
+     output [C_NUM_CHNL-1:0]                   WR_ACK, // Write request has been accepted
+
+     input [C_NUM_CHNL-1:0]                    RD_REQ, // Read request
+     input [(C_NUM_CHNL*2)-1:0]                RD_SG_CHNL, // Read request channel for scatter gather lists
+     input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]      RD_ADDR, // Read request address
+     input [(C_NUM_CHNL*`SIG_LEN_W)-1:0]       RD_LEN, // Read request length
+     output [C_NUM_CHNL-1:0]                   RD_ACK, // Read request has been accepted
+
+     output [5:0]                              INT_TAG, // Internal tag to exchange with external
+     output                                    INT_TAG_VALID, // High to signal tag exchange 
+     input [C_TAG_WIDTH-1:0]                   EXT_TAG, // External tag to provide in exchange for internal tag
+     input                                     EXT_TAG_VALID, // High to signal external tag is valid
+
+     output                                    TX_ENG_RD_REQ_SENT, // Read completion request issued
+     input                                     RXBUF_SPACE_AVAIL,
+    
+     // Interface: TXR Engine
+     output                                    TXR_DATA_VALID,
+     output [C_PCI_DATA_WIDTH-1:0]             TXR_DATA,
+     output                                    TXR_DATA_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_START_OFFSET,
+     output                                    TXR_DATA_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_END_OFFSET,
+     input                                     TXR_DATA_READY,
+
+     output                                    TXR_META_VALID,
+     output [`SIG_FBE_W-1:0]                   TXR_META_FDWBE, 
+     output [`SIG_LBE_W-1:0]                   TXR_META_LDWBE,
+     output [`SIG_ADDR_W-1:0]                  TXR_META_ADDR,
+     output [`SIG_LEN_W-1:0]                   TXR_META_LENGTH,
+     output [`SIG_TAG_W-1:0]                   TXR_META_TAG,
+     output [`SIG_TC_W-1:0]                    TXR_META_TC,
+     output [`SIG_ATTR_W-1:0]                  TXR_META_ATTR,
+     output [`SIG_TYPE_W-1:0]                  TXR_META_TYPE,
+     output                                    TXR_META_EP,
+     input                                     TXR_META_READY);
+
+    localparam C_DATA_DELAY = 6'd6; // Delays read/write params to accommodate tx_port_buffer delay and tx_engine_formatter delay.
+    (* syn_encoding = "user" *)
+    (* fsm_encoding = "user" *)
+    reg [3:0]                                  rMainState=`S_TXENGUPR64_MAIN_IDLE, _rMainState=`S_TXENGUPR64_MAIN_IDLE;
+    reg                                        rCountIsWr=0, _rCountIsWr=0;
+    reg [3:0]                                  rCountChnl=0, _rCountChnl=0;
+    reg [C_TAG_WIDTH-1:0]                      rCountTag=0, _rCountTag=0;
+    reg [9:0]                                  rCount=0, _rCount=0;
+    reg                                        rCountDone=0, _rCountDone=0;
+    reg                                        rCountValid=0,_rCountValid=0;
+    reg                                        rCountStart=0, _rCountStart=0;
+    reg                                        rCountOdd32=0, _rCountOdd32=0;
+    reg [9:0]                                  rCountLen=0, _rCountLen=0;
+    reg [C_NUM_CHNL-1:0]                       rWrDataRen=0, _rWrDataRen=0;
+    reg                                        rTxEngRdReqAck, _rTxEngRdReqAck;
+
+    wire                                       wRdReq;
+    wire [3:0]                                 wRdReqChnl;
+    wire                                       wWrReq;
+    wire [3:0]                                 wWrReqChnl;
+    wire                                       wRdAck;
+
+    
+    wire [3:0]                                 wCountChnl;
+    wire [11:0]                                wCountChnlShiftDW = (wCountChnl*C_PCI_DATA_WIDTH); // Mult can exceed 9 bits, so make this a wire
+    wire [63:0]                                wRdAddr;
+    wire [9:0]                                 wRdLen;
+    wire [1:0]                                 wRdSgChnl;
+    wire [63:0]                                wWrAddr;
+    wire [9:0]                                 wWrLen;
+    wire [C_PCI_DATA_WIDTH-1:0]                wWrData;
+
+    reg [3:0]                                  rRdChnl=0, _rRdChnl=0;
+    reg [61:0]                                 rRdAddr=62'd0, _rRdAddr=62'd0;
+    reg [9:0]                                  rRdLen=0, _rRdLen=0;
+    reg [1:0]                                  rRdSgChnl=0, _rRdSgChnl=0;
+    reg [3:0]                                  rWrChnl=0, _rWrChnl=0;
+    reg [61:0]                                 rWrAddr=62'd0, _rWrAddr=62'd0;
+    reg [9:0]                                  rWrLen=0, _rWrLen=0;
+    reg [C_PCI_DATA_WIDTH-1:0]                 rWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};
+
+    assign wRdAddr = RD_ADDR[wRdReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
+    assign wRdLen = RD_LEN[wRdReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
+    assign wRdSgChnl = RD_SG_CHNL[wRdReqChnl * 2 +: 2];
+    assign wWrAddr = WR_ADDR[wWrReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
+    assign wWrLen = WR_LEN[wWrReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
+    assign wWrData = WR_DATA[wCountChnl * C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
+
+    (* syn_encoding = "user" *)
+    (* fsm_encoding = "user" *)
+    reg		[3:0]						rCapState=`S_TXENGUPR64_CAP_RD_WR, _rCapState=`S_TXENGUPR64_CAP_RD_WR;
+    reg [C_NUM_CHNL-1:0]                rRdAck=0, _rRdAck=0;
+    reg [C_NUM_CHNL-1:0]                rWrAck=0, _rWrAck=0;
+    reg 								rIsWr=0, _rIsWr=0;
+    reg [5:0]                           rCapChnl=0, _rCapChnl=0;
+    reg [61:0]                          rCapAddr=62'd0, _rCapAddr=62'd0;
+    reg 								rCapAddr64=0, _rCapAddr64=0;
+    reg [9:0]                           rCapLen=0, _rCapLen=0;
+    reg 								rCapIsWr=0, _rCapIsWr=0;
+    reg 								rExtTagReq=0, _rExtTagReq=0;
+    reg [C_TAG_WIDTH-1:0]               rExtTag=0, _rExtTag=0;
+
+    reg [C_DATA_DELAY-1:0]              rWnR=0, _rWnR=0;
+    reg [(C_DATA_DELAY*4)-1:0]          rChnl=0, _rChnl=0;
+    reg [(C_DATA_DELAY*8)-1:0]          rTag=0, _rTag=0;
+    reg [(C_DATA_DELAY*62)-1:0]         rAddr=0, _rAddr=0;
+    reg [((C_DATA_DELAY+1)*10)-1:0]     rLen=0, _rLen=0;
+    reg [C_DATA_DELAY-1:0]              rValid=0, _rValid=0;
+    reg [C_DATA_DELAY-1:0]              rDone=0, _rDone=0;
+    reg [C_DATA_DELAY-1:0]              rStart=0, _rStart=0;
+
+
+    assign WR_DATA_REN = rWrDataRen;
+    assign WR_ACK = rWrAck;
+    assign RD_ACK = rRdAck;
+
+    assign INT_TAG = {rRdSgChnl, rRdChnl};
+    assign INT_TAG_VALID = rExtTagReq;
+
+    assign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;
+    assign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);
+
+    // Search for the next request so that we can move onto it immediately after
+    // the current channel has released its request.
+    tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST_IN), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));
+    tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST_IN), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));
+
+
+    // Buffer shift-selected channel request signals and FIFO data.
+    always @ (posedge CLK) begin
+        rRdChnl <= #1 _rRdChnl;
+        rRdAddr <= #1 _rRdAddr;
+        rRdLen <= #1 _rRdLen;
+        rRdSgChnl <= #1 _rRdSgChnl;
+        rWrChnl <= #1 _rWrChnl;
+        rWrAddr <= #1 _rWrAddr;
+        rWrLen <= #1 _rWrLen;
+        rWrData <= #1 _rWrData;
+    end
+
+    always @ (*) begin
+        _rRdChnl = wRdReqChnl;
+        _rRdAddr = wRdAddr[63:2];
+        _rRdLen = wRdLen;
+        _rRdSgChnl = wRdSgChnl;
+        _rWrChnl = wWrReqChnl;
+        _rWrAddr = wWrAddr[63:2];
+        _rWrLen = wWrLen;
+        _rWrData = wWrData;
+    end
+
+
+    // Accept requests when the selector indicates. Capture the buffered 
+    // request parameters for hand-off to the formatting pipeline. Then
+    // acknowledge the receipt to the channel so it can deassert the 
+    // request, and let the selector choose another channel.
+    always @ (posedge CLK) begin
+        rCapState <= #1 (RST_IN ? `S_TXENGUPR64_CAP_RD_WR : _rCapState);
+        rRdAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rRdAck);
+        rWrAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rWrAck);
+        rIsWr <= #1 _rIsWr;
+        rCapChnl <= #1 _rCapChnl;
+        rCapAddr <= #1 _rCapAddr;
+        rCapAddr64 <= #1 _rCapAddr64;
+        rCapLen <= #1 _rCapLen;
+        rCapIsWr <= #1 _rCapIsWr;
+        rExtTagReq <= #1 _rExtTagReq;
+        rExtTag <= #1 _rExtTag;
+        rTxEngRdReqAck <= #1 _rTxEngRdReqAck;
+    end
+
+    always @ (*) begin
+        _rCapState = rCapState;
+        _rRdAck = rRdAck;
+        _rWrAck = rWrAck;
+        _rIsWr = rIsWr;
+        _rCapChnl = rCapChnl;
+        _rCapAddr = rCapAddr;
+        _rCapAddr64 = (rCapAddr[61:30] != 0);
+        _rCapLen = rCapLen;
+        _rCapIsWr = rCapIsWr;
+        _rExtTagReq = rExtTagReq;
+        _rExtTag = rExtTag;
+        _rTxEngRdReqAck = rTxEngRdReqAck;
+
+        case (rCapState) 
+
+	        `S_TXENGUPR64_CAP_RD_WR : begin
+	            _rIsWr = !wRdReq;
+	            _rRdAck = (wRdAck<<wRdReqChnl);
+	            _rTxEngRdReqAck = wRdAck;
+	            _rExtTagReq = wRdAck;
+	            _rCapState = (wRdAck ? `S_TXENGUPR64_CAP_CAP : `S_TXENGUPR64_CAP_WR_RD);
+	        end
+
+	        `S_TXENGUPR64_CAP_WR_RD : begin
+	            _rIsWr = wWrReq;
+	            _rWrAck = (wWrReq<<wWrReqChnl);
+	            _rCapState = (wWrReq ? `S_TXENGUPR64_CAP_CAP : `S_TXENGUPR64_CAP_RD_WR);
+	        end
+
+	        `S_TXENGUPR64_CAP_CAP : begin
+	            _rTxEngRdReqAck = 0;
+	            _rRdAck = 0;
+	            _rWrAck = 0;
+	            _rCapIsWr = rIsWr;
+	            _rExtTagReq = 0;
+	            _rExtTag = EXT_TAG;
+	            if (rIsWr) begin
+	                _rCapChnl = {2'd0, rWrChnl};
+	                _rCapAddr = rWrAddr;
+	                _rCapLen = rWrLen;
+	            end
+	            else begin
+	                _rCapChnl = {rRdSgChnl, rRdChnl};
+	                _rCapAddr = rRdAddr;
+	                _rCapLen = rRdLen;
+	            end
+	            _rCapState = `S_TXENGUPR64_CAP_REL;
+	        end
+	        
+	        `S_TXENGUPR64_CAP_REL : begin
+	            // Push into the formatting pipeline when ready
+	            if (TXR_META_READY & rMainState[0]) // S_TXENGUPR64_MAIN_IDLE
+	                _rCapState = (`S_TXENGUPR64_CAP_WR_RD>>(rCapIsWr)); // Changes to S_TXENGUPR64_CAP_RD_WR
+	        end
+	        
+	        default : begin
+	            _rCapState = `S_TXENGUPR64_CAP_RD_WR;
+	        end
+	        
+        endcase
+    end
+
+
+    // Start the read/write when space is available in the output FIFO and when
+    // request parameters have been captured (i.e. a pending request).
+    always @ (posedge CLK) begin
+        rMainState <= #1 (RST_IN ? `S_TXENGUPR64_MAIN_IDLE : _rMainState);
+        rCountIsWr <= #1 _rCountIsWr;
+        rCountLen <= #1 _rCountLen;
+        rCount <= #1 _rCount;
+        rCountDone <= #1 _rCountDone;
+        rCountStart <= #1 _rCountStart;
+        rCountChnl <= #1 _rCountChnl;
+        rCountTag <= #1 _rCountTag;
+        rCountOdd32 <= #1 _rCountOdd32;
+        rWrDataRen <= #1 _rWrDataRen;
+        rCountValid <= #1 RST_IN ? 0 : _rCountValid;
+    end
+
+    always @ (*) begin
+        _rMainState = rMainState;
+        _rCountIsWr = rCountIsWr;
+        _rCount = rCount;
+        _rCountLen = rCountLen;
+        _rCountDone = rCountDone;
+        _rCountStart = rCountStart;
+        _rCountChnl = rCountChnl;
+        _rCountTag = rCountTag;
+        _rCountOdd32 = rCountOdd32;
+        _rWrDataRen = rWrDataRen;
+        _rCountStart = 0;
+        _rCountValid = rCountValid;
+        case (rMainState) 
+
+	        `S_TXENGUPR64_MAIN_IDLE : begin
+                _rCountIsWr = rCapIsWr;
+                _rCountLen = rCapLen;
+	            _rCount = rCapLen;
+	            _rCountDone = (rCapLen <= 2'd2);
+	            _rCountChnl = rCapChnl[3:0];
+	            _rCountTag = rExtTag;
+	            _rCountOdd32 = (rCapLen[0] & ((rCapAddr[61:30] == 0)));
+	            _rWrDataRen = ((TXR_META_READY & rCapState[3] & rCapIsWr)<<(rCapChnl[3:0])); // S_TXENGUPR64_CAP_REL
+                _rCountStart = (TXR_META_READY & rCapState[3]);
+                _rCountValid = TXR_META_READY & rCapState[3];
+	            if (TXR_META_READY & rCapState[3]) // S_TXENGUPR64_CAP_REL
+	                _rMainState = (`S_TXENGUPR64_MAIN_RD<<(rCapIsWr)); // Change to S_TXENGUPR64_MAIN_WR;
+	        end
+
+	        `S_TXENGUPR64_MAIN_RD : begin
+	            _rMainState = `S_TXENGUPR64_MAIN_IDLE;
+	        end
+
+	        `S_TXENGUPR64_MAIN_WR : begin
+	            _rCount = rCount - 2'd2;
+	            _rCountDone = (rCount <= 3'd4);
+	            if (rCountDone) begin
+	                _rWrDataRen = 0;
+                    _rCountValid = 0;
+	                _rMainState = (rCountOdd32 ? `S_TXENGUPR64_MAIN_IDLE : `S_TXENGUPR64_MAIN_WAIT);
+	            end
+	        end
+	        `S_TXENGUPR64_MAIN_WAIT : begin // Signals request FIFO ren
+	            _rMainState = `S_TXENGUPR64_MAIN_IDLE;
+	        end
+
+	        default : begin
+	            _rMainState = `S_TXENGUPR64_MAIN_IDLE;
+	        end
+	        
+        endcase
+    end
+
+
+    // Shift in the captured parameters and valid signal every cycle.
+    // This pipeline will keep the formatter busy.
+    assign wCountChnl = rChnl[(C_DATA_DELAY-2)*4 +:4];
+    always @ (posedge CLK) begin
+        rWnR <= #1 _rWnR;
+        rChnl <= #1 _rChnl;
+        rTag <= #1 _rTag;
+        rAddr <= #1 _rAddr;
+        rLen <= #1 _rLen;
+        rValid <= #1 _rValid;
+        rDone <= #1 _rDone;
+        rStart <= #1 _rStart;
+    end
+
+    always @ (*) begin
+        _rWnR = {rWnR[((C_DATA_DELAY-1)*1)-1:0], rCapIsWr};
+        _rAddr = {rAddr[((C_DATA_DELAY-1)*62)-1:0], rCapAddr};
+
+        _rLen = {rLen[((C_DATA_DELAY-1)*10)-1:0], rCountLen};
+        _rChnl = {rChnl[((C_DATA_DELAY-1)*4)-1:0], rCountChnl};
+        _rTag = {rTag[((C_DATA_DELAY-1)*8)-1:0], (8'd0 | rCountTag)};
+        _rValid = {rValid[((C_DATA_DELAY-1)*1)-1:0], rCountValid & rCountIsWr}; // S_TXENGUPR64_MAIN_RD | S_TXENGUPR64_MAIN_WR
+        _rDone = {rDone[((C_DATA_DELAY-1)*1)-1:0], rCountDone};
+        _rStart = {rStart[((C_DATA_DELAY-1)*1)-1:0], rCountStart};
+    end
+
+    assign TXR_DATA = rWrData;
+    assign TXR_DATA_VALID = rValid[(C_DATA_DELAY-1)*1 +:1];
+    assign TXR_DATA_START_FLAG = rStart[(C_DATA_DELAY-1)*1 +:1];
+    assign TXR_DATA_START_OFFSET = 0;
+    assign TXR_DATA_END_FLAG = rDone[(C_DATA_DELAY-1)*1 +:1];
+    assign TXR_DATA_END_OFFSET = rLen[(C_DATA_DELAY-1)*10 +:`SIG_OFFSET_W] - 1;
+    assign TXR_META_VALID = rCountStart;
+    assign TXR_META_TYPE = rCapIsWr ? `TRLS_REQ_WR : `TRLS_REQ_RD;
+    assign TXR_META_ADDR = {rCapAddr,2'b00};
+    assign TXR_META_LENGTH = rCapLen;
+    assign TXR_META_LDWBE = 4'b1111;
+    assign TXR_META_FDWBE = 4'b1111;
+    assign TXR_META_TAG = rCountTag;
+    assign TXR_META_EP = 1'b0;
+    assign TXR_META_ATTR = 3'b110;
+    assign TXR_META_TC = 0;
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_port_128.v b/fpga/riffa_hdl/tx_port_128.v
new file mode 100644
index 0000000..f001d90
--- /dev/null
+++ b/fpga/riffa_hdl/tx_port_128.v
@@ -0,0 +1,240 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			tx_port_128.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Receives data from the tx_engine and buffers the input 
+//						for the RIFFA channel.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+
+`timescale 1ns/1ns
+module tx_port_128 #(
+	parameter C_DATA_WIDTH = 9'd128,
+	parameter C_FIFO_DEPTH = 512,
+	// Local parameters
+	parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
+)
+(
+	input CLK,
+	input RST,
+	input [2:0] CONFIG_MAX_PAYLOAD_SIZE,	// Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
+	
+	output TXN,								// Write transaction notification
+	input TXN_ACK,							// Write transaction acknowledged
+	output [31:0] TXN_LEN,					// Write transaction length
+	output [31:0] TXN_OFF_LAST,				// Write transaction offset/last
+	output [31:0] TXN_DONE_LEN,				// Write transaction actual transfer length
+	output TXN_DONE,						// Write transaction done
+	input TXN_DONE_ACK,						// Write transaction actual transfer length read
+
+	input [C_DATA_WIDTH-1:0] SG_DATA,		// Scatter gather data 
+	input SG_DATA_EMPTY,					// Scatter gather buffer empty
+	output SG_DATA_REN,						// Scatter gather data read enable
+	output SG_RST,							// Scatter gather reset
+	input SG_ERR,							// Scatter gather read encountered an error
+	
+	output TX_REQ,							// Outgoing write request
+	input TX_REQ_ACK,						// Outgoing write request acknowledged
+	output [63:0] TX_ADDR,					// Outgoing write high address
+	output [9:0] TX_LEN,					// Outgoing write length (in 32 bit words)
+	output [C_DATA_WIDTH-1:0] TX_DATA,		// Outgoing write data
+	input TX_DATA_REN,						// Outgoing write data read enable
+	input TX_SENT,							// Outgoing write complete
+
+	input CHNL_CLK,							// Channel write clock
+	input CHNL_TX,							// Channel write receive signal
+	output CHNL_TX_ACK,						// Channel write acknowledgement signal
+	input CHNL_TX_LAST,						// Channel last write
+	input [31:0] CHNL_TX_LEN,				// Channel write length (in 32 bit words)
+	input [30:0] CHNL_TX_OFF,				// Channel write offset
+	input [C_DATA_WIDTH-1:0] CHNL_TX_DATA,	// Channel write data
+	input CHNL_TX_DATA_VALID,				// Channel write data valid
+	output CHNL_TX_DATA_REN					// Channel write data has been recieved
+);
+
+`include "functions.vh"
+
+wire								wGateRen;
+wire								wGateEmpty;
+wire	[C_DATA_WIDTH:0]			wGateData;
+
+wire								wBufWen;
+wire	[C_FIFO_DEPTH_WIDTH-1:0]	wBufCount;
+wire	[C_DATA_WIDTH-1:0]			wBufData;
+
+wire								wTxn;
+wire								wTxnAck;
+wire								wTxnLast;
+wire	[31:0]						wTxnLen;
+wire	[30:0]						wTxnOff;
+wire	[31:0]						wTxnWordsRecvd;
+wire								wTxnDone;
+wire								wTxnErr;
+
+wire								wSgElemRen;
+wire								wSgElemRdy;
+wire								wSgElemEmpty;
+wire	[31:0]						wSgElemLen;
+wire	[63:0]						wSgElemAddr;
+
+wire								wTxLast;
+
+reg		[4:0]						rWideRst=0;
+reg									rRst=0;
+
+
+// Generate a wide reset from the input reset.
+always @ (posedge CLK) begin
+	rRst <= #1 rWideRst[4]; 
+	if (RST) 
+		rWideRst <= #1 5'b11111;
+	else 
+		rWideRst <= (rWideRst<<1);
+end
+
+
+// Capture channel transaction open/close events as well as channel data. 
+tx_port_channel_gate_128 #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
+	.RST(rRst),
+	.RD_CLK(CLK),
+	.RD_DATA(wGateData),
+	.RD_EMPTY(wGateEmpty),
+	.RD_EN(wGateRen),
+	.CHNL_CLK(CHNL_CLK),
+	.CHNL_TX(CHNL_TX),
+	.CHNL_TX_ACK(CHNL_TX_ACK),
+	.CHNL_TX_LAST(CHNL_TX_LAST),
+	.CHNL_TX_LEN(CHNL_TX_LEN),
+	.CHNL_TX_OFF(CHNL_TX_OFF),
+	.CHNL_TX_DATA(CHNL_TX_DATA),
+	.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
+	.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
+);
+
+
+// Filter transaction events from channel data. Use the events to put only
+// the requested amount of data into the port buffer.
+tx_port_monitor_128 #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) monitor (
+	.RST(rRst),
+	.CLK(CLK),
+	.EVT_DATA(wGateData),
+	.EVT_DATA_EMPTY(wGateEmpty),
+	.EVT_DATA_RD_EN(wGateRen),
+	.WR_DATA(wBufData),
+	.WR_EN(wBufWen),
+	.WR_COUNT(wBufCount),
+	.TXN(wTxn),
+	.ACK(wTxnAck),
+	.LAST(wTxnLast),
+	.LEN(wTxnLen),
+	.OFF(wTxnOff),
+	.WORDS_RECVD(wTxnWordsRecvd),
+	.DONE(wTxnDone),
+	.TX_ERR(SG_ERR)
+);
+
+
+// Buffer the incoming channel data. Also make sure to discard only as
+// much data as is needed for a transfer (which may involve non-integral 
+// packets (i.e. reading only 1, 2, or 3 words out of the packet).
+tx_port_buffer_128 #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) buffer (
+	.CLK(CLK),
+	.RST(rRst | (TXN_DONE & wTxnErr)),
+	.RD_DATA(TX_DATA),
+	.RD_EN(TX_DATA_REN),
+	.LEN_VALID(TX_REQ_ACK),
+	.LEN_LSB(TX_LEN[1:0]),
+	.LEN_LAST(wTxLast),
+	.WR_DATA(wBufData),
+	.WR_EN(wBufWen),
+	.WR_COUNT(wBufCount)
+);
+
+
+// Read the scatter gather buffer address and length, continuously so that
+// we have it ready whenever the next buffer is needed.
+sg_list_reader_128 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
+	.CLK(CLK),
+	.RST(rRst | SG_RST),
+	.BUF_DATA(SG_DATA),
+	.BUF_DATA_EMPTY(SG_DATA_EMPTY),
+	.BUF_DATA_REN(SG_DATA_REN),
+	.VALID(wSgElemRdy),
+	.EMPTY(wSgElemEmpty),
+	.REN(wSgElemRen),
+	.ADDR(wSgElemAddr),
+	.LEN(wSgElemLen)
+);
+
+
+// Controls the flow of request to the tx engine for transfers in a transaction.
+tx_port_writer writer (
+	.CLK(CLK),
+	.RST(rRst),
+	.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
+	.TXN(TXN),
+	.TXN_ACK(TXN_ACK),
+	.TXN_LEN(TXN_LEN),
+	.TXN_OFF_LAST(TXN_OFF_LAST),
+	.TXN_DONE_LEN(TXN_DONE_LEN),
+	.TXN_DONE(TXN_DONE),
+	.TXN_ERR(wTxnErr),
+	.TXN_DONE_ACK(TXN_DONE_ACK),
+	.NEW_TXN(wTxn),
+	.NEW_TXN_ACK(wTxnAck),
+	.NEW_TXN_LAST(wTxnLast),
+	.NEW_TXN_LEN(wTxnLen),
+	.NEW_TXN_OFF(wTxnOff),
+	.NEW_TXN_WORDS_RECVD(wTxnWordsRecvd),
+	.NEW_TXN_DONE(wTxnDone),
+	.SG_ELEM_ADDR(wSgElemAddr),
+	.SG_ELEM_LEN(wSgElemLen),
+	.SG_ELEM_RDY(wSgElemRdy),
+	.SG_ELEM_EMPTY(wSgElemEmpty),
+	.SG_ELEM_REN(wSgElemRen),
+	.SG_RST(SG_RST),
+	.SG_ERR(SG_ERR),
+	.TX_REQ(TX_REQ),
+	.TX_REQ_ACK(TX_REQ_ACK),
+	.TX_ADDR(TX_ADDR),
+	.TX_LEN(TX_LEN),
+	.TX_LAST(wTxLast),
+	.TX_SENT(TX_SENT)
+);
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_port_32.v b/fpga/riffa_hdl/tx_port_32.v
new file mode 100644
index 0000000..0eee77f
--- /dev/null
+++ b/fpga/riffa_hdl/tx_port_32.v
@@ -0,0 +1,233 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			tx_port_32.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Receives data from the tx_engine and buffers the input 
+//						for the RIFFA channel.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+
+`timescale 1ns/1ns
+module tx_port_32 #(
+	parameter C_DATA_WIDTH = 9'd32,
+	parameter C_FIFO_DEPTH = 512,
+	// Local parameters
+	parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
+)
+(
+	input CLK,
+	input RST,
+	input [2:0] CONFIG_MAX_PAYLOAD_SIZE,	// Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
+	
+	output TXN,								// Write transaction notification
+	input TXN_ACK,							// Write transaction acknowledged
+	output [31:0] TXN_LEN,					// Write transaction length
+	output [31:0] TXN_OFF_LAST,				// Write transaction offset/last
+	output [31:0] TXN_DONE_LEN,				// Write transaction actual transfer length
+	output TXN_DONE,						// Write transaction done
+	input TXN_DONE_ACK,						// Write transaction actual transfer length read
+
+	input [C_DATA_WIDTH-1:0] SG_DATA,		// Scatter gather data 
+	input SG_DATA_EMPTY,					// Scatter gather buffer empty
+	output SG_DATA_REN,						// Scatter gather data read enable
+	output SG_RST,							// Scatter gather reset
+	input SG_ERR,							// Scatter gather read encountered an error
+	
+	output TX_REQ,							// Outgoing write request
+	input TX_REQ_ACK,						// Outgoing write request acknowledged
+	output [63:0] TX_ADDR,					// Outgoing write high address
+	output [9:0] TX_LEN,					// Outgoing write length (in 32 bit words)
+	output [C_DATA_WIDTH-1:0] TX_DATA,		// Outgoing write data
+	input TX_DATA_REN,						// Outgoing write data read enable
+	input TX_SENT,							// Outgoing write complete
+
+	input CHNL_CLK,							// Channel write clock
+	input CHNL_TX,							// Channel write receive signal
+	output CHNL_TX_ACK,						// Channel write acknowledgement signal
+	input CHNL_TX_LAST,						// Channel last write
+	input [31:0] CHNL_TX_LEN,				// Channel write length (in 32 bit words)
+	input [30:0] CHNL_TX_OFF,				// Channel write offset
+	input [C_DATA_WIDTH-1:0] CHNL_TX_DATA,	// Channel write data
+	input CHNL_TX_DATA_VALID,				// Channel write data valid
+	output CHNL_TX_DATA_REN					// Channel write data has been recieved
+);
+
+`include "functions.vh"
+
+wire								wGateRen;
+wire								wGateEmpty;
+wire	[C_DATA_WIDTH:0]			wGateData;
+
+wire								wBufWen;
+wire	[C_FIFO_DEPTH_WIDTH-1:0]	wBufCount;
+wire	[C_DATA_WIDTH-1:0]			wBufData;
+
+wire								wTxn;
+wire								wTxnAck;
+wire								wTxnLast;
+wire	[31:0]						wTxnLen;
+wire	[30:0]						wTxnOff;
+wire	[31:0]						wTxnWordsRecvd;
+wire								wTxnDone;
+wire								wTxnErr;
+
+wire								wSgElemRen;
+wire								wSgElemRdy;
+wire								wSgElemEmpty;
+wire	[31:0]						wSgElemLen;
+wire	[63:0]						wSgElemAddr;
+
+reg		[4:0]						rWideRst=0;
+reg									rRst=0;
+
+
+// Generate a wide reset from the input reset.
+always @ (posedge CLK) begin
+	rRst <= #1 rWideRst[4]; 
+	if (RST) 
+		rWideRst <= #1 5'b11111;
+	else 
+		rWideRst <= (rWideRst<<1);
+end
+
+
+// Capture channel transaction open/close events as well as channel data. 
+tx_port_channel_gate_32 #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
+	.RST(rRst),
+	.RD_CLK(CLK),
+	.RD_DATA(wGateData),
+	.RD_EMPTY(wGateEmpty),
+	.RD_EN(wGateRen),
+	.CHNL_CLK(CHNL_CLK),
+	.CHNL_TX(CHNL_TX),
+	.CHNL_TX_ACK(CHNL_TX_ACK),
+	.CHNL_TX_LAST(CHNL_TX_LAST),
+	.CHNL_TX_LEN(CHNL_TX_LEN),
+	.CHNL_TX_OFF(CHNL_TX_OFF),
+	.CHNL_TX_DATA(CHNL_TX_DATA),
+	.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
+	.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
+);
+
+
+// Filter transaction events from channel data. Use the events to put only
+// the requested amount of data into the port buffer.
+tx_port_monitor_32 #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) monitor (
+	.RST(rRst),
+	.CLK(CLK),
+	.EVT_DATA(wGateData),
+	.EVT_DATA_EMPTY(wGateEmpty),
+	.EVT_DATA_RD_EN(wGateRen),
+	.WR_DATA(wBufData),
+	.WR_EN(wBufWen),
+	.WR_COUNT(wBufCount),
+	.TXN(wTxn),
+	.ACK(wTxnAck),
+	.LAST(wTxnLast),
+	.LEN(wTxnLen),
+	.OFF(wTxnOff),
+	.WORDS_RECVD(wTxnWordsRecvd),
+	.DONE(wTxnDone),
+	.TX_ERR(SG_ERR)
+);
+
+
+// Buffer the incoming channel data. 
+tx_port_buffer_32 #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) buffer (
+	.CLK(CLK),
+	.RST(rRst | (TXN_DONE & wTxnErr)),
+	.RD_DATA(TX_DATA),
+	.RD_EN(TX_DATA_REN),
+	.WR_DATA(wBufData),
+	.WR_EN(wBufWen),
+	.WR_COUNT(wBufCount)
+);
+
+
+// Read the scatter gather buffer address and length, continuously so that
+// we have it ready whenever the next buffer is needed.
+sg_list_reader_32 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
+	.CLK(CLK),
+	.RST(rRst | SG_RST),
+	.BUF_DATA(SG_DATA),
+	.BUF_DATA_EMPTY(SG_DATA_EMPTY),
+	.BUF_DATA_REN(SG_DATA_REN),
+	.VALID(wSgElemRdy),
+	.EMPTY(wSgElemEmpty),
+	.REN(wSgElemRen),
+	.ADDR(wSgElemAddr),
+	.LEN(wSgElemLen)
+);
+
+
+// Controls the flow of request to the tx engine for transfers in a transaction.
+tx_port_writer writer (
+	.CLK(CLK),
+	.RST(rRst),
+	.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
+	.TXN(TXN),
+	.TXN_ACK(TXN_ACK),
+	.TXN_LEN(TXN_LEN),
+	.TXN_OFF_LAST(TXN_OFF_LAST),
+	.TXN_DONE_LEN(TXN_DONE_LEN),
+	.TXN_DONE(TXN_DONE),
+	.TXN_ERR(wTxnErr),
+	.TXN_DONE_ACK(TXN_DONE_ACK),
+	.NEW_TXN(wTxn),
+	.NEW_TXN_ACK(wTxnAck),
+	.NEW_TXN_LAST(wTxnLast),
+	.NEW_TXN_LEN(wTxnLen),
+	.NEW_TXN_OFF(wTxnOff),
+	.NEW_TXN_WORDS_RECVD(wTxnWordsRecvd),
+	.NEW_TXN_DONE(wTxnDone),
+	.SG_ELEM_ADDR(wSgElemAddr),
+	.SG_ELEM_LEN(wSgElemLen),
+	.SG_ELEM_RDY(wSgElemRdy),
+	.SG_ELEM_EMPTY(wSgElemEmpty),
+	.SG_ELEM_REN(wSgElemRen),
+	.SG_RST(SG_RST),
+	.SG_ERR(SG_ERR),
+	.TX_REQ(TX_REQ),
+	.TX_REQ_ACK(TX_REQ_ACK),
+	.TX_ADDR(TX_ADDR),
+	.TX_LEN(TX_LEN),
+	.TX_LAST(),
+	.TX_SENT(TX_SENT)
+);
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_port_64.v b/fpga/riffa_hdl/tx_port_64.v
new file mode 100644
index 0000000..88841da
--- /dev/null
+++ b/fpga/riffa_hdl/tx_port_64.v
@@ -0,0 +1,240 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			tx_port_64.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Receives data from the tx_engine and buffers the input 
+//						for the RIFFA channel.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+
+`timescale 1ns/1ns
+module tx_port_64 #(
+	parameter C_DATA_WIDTH = 9'd64,
+	parameter C_FIFO_DEPTH = 512,
+	// Local parameters
+	parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
+)
+(
+	input CLK,
+	input RST,
+	input [2:0] CONFIG_MAX_PAYLOAD_SIZE,	// Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
+	
+	output TXN,								// Write transaction notification
+	input TXN_ACK,							// Write transaction acknowledged
+	output [31:0] TXN_LEN,					// Write transaction length
+	output [31:0] TXN_OFF_LAST,				// Write transaction offset/last
+	output [31:0] TXN_DONE_LEN,				// Write transaction actual transfer length
+	output TXN_DONE,						// Write transaction done
+	input TXN_DONE_ACK,						// Write transaction actual transfer length read
+
+	input [C_DATA_WIDTH-1:0] SG_DATA,		// Scatter gather data 
+	input SG_DATA_EMPTY,					// Scatter gather buffer empty
+	output SG_DATA_REN,						// Scatter gather data read enable
+	output SG_RST,							// Scatter gather reset
+	input SG_ERR,							// Scatter gather read encountered an error
+	
+	output TX_REQ,							// Outgoing write request
+	input TX_REQ_ACK,						// Outgoing write request acknowledged
+	output [63:0] TX_ADDR,					// Outgoing write high address
+	output [9:0] TX_LEN,					// Outgoing write length (in 32 bit words)
+	output [C_DATA_WIDTH-1:0] TX_DATA,		// Outgoing write data
+	input TX_DATA_REN,						// Outgoing write data read enable
+	input TX_SENT,							// Outgoing write complete
+
+	input CHNL_CLK,							// Channel write clock
+	input CHNL_TX,							// Channel write receive signal
+	output CHNL_TX_ACK,						// Channel write acknowledgement signal
+	input CHNL_TX_LAST,						// Channel last write
+	input [31:0] CHNL_TX_LEN,				// Channel write length (in 32 bit words)
+	input [30:0] CHNL_TX_OFF,				// Channel write offset
+	input [C_DATA_WIDTH-1:0] CHNL_TX_DATA,	// Channel write data
+	input CHNL_TX_DATA_VALID,				// Channel write data valid
+	output CHNL_TX_DATA_REN					// Channel write data has been recieved
+);
+
+`include "functions.vh"
+
+wire								wGateRen;
+wire								wGateEmpty;
+wire	[C_DATA_WIDTH:0]			wGateData;
+
+wire								wBufWen;
+wire	[C_FIFO_DEPTH_WIDTH-1:0]	wBufCount;
+wire	[C_DATA_WIDTH-1:0]			wBufData;
+
+wire								wTxn;
+wire								wTxnAck;
+wire								wTxnLast;
+wire	[31:0]						wTxnLen;
+wire	[30:0]						wTxnOff;
+wire	[31:0]						wTxnWordsRecvd;
+wire								wTxnDone;
+wire								wTxnErr;
+
+wire								wSgElemRen;
+wire								wSgElemRdy;
+wire								wSgElemEmpty;
+wire	[31:0]						wSgElemLen;
+wire	[63:0]						wSgElemAddr;
+
+wire								wTxLast;
+
+reg		[4:0]						rWideRst=0;
+reg									rRst=0;
+
+
+// Generate a wide reset from the input reset.
+always @ (posedge CLK) begin
+	rRst <= #1 rWideRst[4]; 
+	if (RST) 
+		rWideRst <= #1 5'b11111;
+	else 
+		rWideRst <= (rWideRst<<1);
+end
+
+
+// Capture channel transaction open/close events as well as channel data. 
+tx_port_channel_gate_64 #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
+	.RST(rRst),
+	.RD_CLK(CLK),
+	.RD_DATA(wGateData),
+	.RD_EMPTY(wGateEmpty),
+	.RD_EN(wGateRen),
+	.CHNL_CLK(CHNL_CLK),
+	.CHNL_TX(CHNL_TX),
+	.CHNL_TX_ACK(CHNL_TX_ACK),
+	.CHNL_TX_LAST(CHNL_TX_LAST),
+	.CHNL_TX_LEN(CHNL_TX_LEN),
+	.CHNL_TX_OFF(CHNL_TX_OFF),
+	.CHNL_TX_DATA(CHNL_TX_DATA),
+	.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
+	.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
+);
+
+
+// Filter transaction events from channel data. Use the events to put only
+// the requested amount of data into the port buffer.
+tx_port_monitor_64 #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) monitor (
+	.RST(rRst),
+	.CLK(CLK),
+	.EVT_DATA(wGateData),
+	.EVT_DATA_EMPTY(wGateEmpty),
+	.EVT_DATA_RD_EN(wGateRen),
+	.WR_DATA(wBufData),
+	.WR_EN(wBufWen),
+	.WR_COUNT(wBufCount),
+	.TXN(wTxn),
+	.ACK(wTxnAck),
+	.LAST(wTxnLast),
+	.LEN(wTxnLen),
+	.OFF(wTxnOff),
+	.WORDS_RECVD(wTxnWordsRecvd),
+	.DONE(wTxnDone),
+	.TX_ERR(SG_ERR)
+);
+
+
+// Buffer the incoming channel data. Also make sure to discard only as
+// much data as is needed for a transfer (which may involve non-integral 
+// packets (i.e. reading only 1 word out of the packet).
+tx_port_buffer_64 #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) buffer (
+	.CLK(CLK),
+	.RST(rRst | (TXN_DONE & wTxnErr)),
+	.RD_DATA(TX_DATA),
+	.RD_EN(TX_DATA_REN),
+	.LEN_VALID(TX_REQ_ACK),
+	.LEN_LSB(TX_LEN[0]),
+	.LEN_LAST(wTxLast),
+	.WR_DATA(wBufData),
+	.WR_EN(wBufWen),
+	.WR_COUNT(wBufCount)
+);
+
+
+// Read the scatter gather buffer address and length, continuously so that
+// we have it ready whenever the next buffer is needed.
+sg_list_reader_64 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
+	.CLK(CLK),
+	.RST(rRst | SG_RST),
+	.BUF_DATA(SG_DATA),
+	.BUF_DATA_EMPTY(SG_DATA_EMPTY),
+	.BUF_DATA_REN(SG_DATA_REN),
+	.VALID(wSgElemRdy),
+	.EMPTY(wSgElemEmpty),
+	.REN(wSgElemRen),
+	.ADDR(wSgElemAddr),
+	.LEN(wSgElemLen)
+);
+
+
+// Controls the flow of request to the tx engine for transfers in a transaction.
+tx_port_writer writer (
+	.CLK(CLK),
+	.RST(rRst),
+	.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
+	.TXN(TXN),
+	.TXN_ACK(TXN_ACK),
+	.TXN_LEN(TXN_LEN),
+	.TXN_OFF_LAST(TXN_OFF_LAST),
+	.TXN_DONE_LEN(TXN_DONE_LEN),
+	.TXN_DONE(TXN_DONE),
+	.TXN_ERR(wTxnErr),
+	.TXN_DONE_ACK(TXN_DONE_ACK),
+	.NEW_TXN(wTxn),
+	.NEW_TXN_ACK(wTxnAck),
+	.NEW_TXN_LAST(wTxnLast),
+	.NEW_TXN_LEN(wTxnLen),
+	.NEW_TXN_OFF(wTxnOff),
+	.NEW_TXN_WORDS_RECVD(wTxnWordsRecvd),
+	.NEW_TXN_DONE(wTxnDone),
+	.SG_ELEM_ADDR(wSgElemAddr),
+	.SG_ELEM_LEN(wSgElemLen),
+	.SG_ELEM_RDY(wSgElemRdy),
+	.SG_ELEM_EMPTY(wSgElemEmpty),
+	.SG_ELEM_REN(wSgElemRen),
+	.SG_RST(SG_RST),
+	.SG_ERR(SG_ERR),
+	.TX_REQ(TX_REQ),
+	.TX_REQ_ACK(TX_REQ_ACK),
+	.TX_ADDR(TX_ADDR),
+	.TX_LEN(TX_LEN),
+	.TX_LAST(wTxLast),
+	.TX_SENT(TX_SENT)
+);
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_port_buffer_128.v b/fpga/riffa_hdl/tx_port_buffer_128.v
new file mode 100644
index 0000000..1802402
--- /dev/null
+++ b/fpga/riffa_hdl/tx_port_buffer_128.v
@@ -0,0 +1,234 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			tx_port_buffer_128.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Wraps a FIFO for saving channel data and provides a 
+// registered read output. Retains unread words from reads that are a length 
+// which is not a multiple of the data bus width (C_FIFO_DATA_WIDTH). Data is
+// available 5 cycles after RD_EN is asserted (not 1, like a traditional FIFO).
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+
+`timescale 1ns/1ns
+module tx_port_buffer_128 #(
+	parameter C_FIFO_DATA_WIDTH = 9'd128,
+	parameter C_FIFO_DEPTH = 512,
+	// Local parameters
+	parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
+	parameter C_RD_EN_HIST = 2,
+	parameter C_FIFO_RD_EN_HIST = 2,
+	parameter C_CONSUME_HIST = 3,
+	parameter C_COUNT_HIST = 3,
+	parameter C_LEN_LAST_HIST = 1
+)
+(
+	input RST,
+	input CLK,
+
+	input LEN_VALID,							// Transfer length is valid
+	input [1:0] LEN_LSB,						// LSBs of transfer length
+	input LEN_LAST,								// Last transfer in transaction
+
+	input [C_FIFO_DATA_WIDTH-1:0] WR_DATA,		// Input data
+	input WR_EN,								// Input data write enable
+	output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT,	// Input data write count
+
+	output [C_FIFO_DATA_WIDTH-1:0] RD_DATA,		// Output data
+	input RD_EN									// Output data read enable
+);
+
+`include "functions.vh"
+
+reg 	[1:0]						rRdPtr=0, _rRdPtr=0;
+reg 	[1:0]						rWrPtr=0, _rWrPtr=0;
+reg 	[3:0]						rLenLSB0=0, _rLenLSB0=0;
+reg 	[3:0]						rLenLSB1=0, _rLenLSB1=0;
+reg 	[3:0]						rLenLast=0, _rLenLast=0;
+reg									rLenValid=0, _rLenValid=0;
+
+reg									rRen=0, _rRen=0;	
+reg 	[2:0]						rCount=0, _rCount=0;
+reg 	[(C_COUNT_HIST*3)-1:0]		rCountHist={C_COUNT_HIST{3'd0}}, _rCountHist={C_COUNT_HIST{3'd0}};
+reg 	[C_LEN_LAST_HIST-1:0]		rLenLastHist={C_LEN_LAST_HIST{1'd0}}, _rLenLastHist={C_LEN_LAST_HIST{1'd0}};
+reg 	[C_RD_EN_HIST-1:0]			rRdEnHist={C_RD_EN_HIST{1'd0}}, _rRdEnHist={C_RD_EN_HIST{1'd0}};
+reg 								rFifoRdEn=0, _rFifoRdEn=0;
+reg 	[C_FIFO_RD_EN_HIST-1:0]		rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}}, _rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}};
+reg 	[(C_CONSUME_HIST*3)-1:0]	rConsumedHist={C_CONSUME_HIST{3'd0}}, _rConsumedHist={C_CONSUME_HIST{3'd0}};
+reg		[C_FIFO_DATA_WIDTH-1:0]		rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
+reg		[223:0]						rData=224'd0, _rData=224'd0;
+
+wire	[C_FIFO_DATA_WIDTH-1:0]		wFifoData;
+
+assign RD_DATA = rData[0 +:C_FIFO_DATA_WIDTH];
+
+
+// Buffer the input signals that come from outside the tx_port.
+always @ (posedge CLK) begin
+	rLenValid <= #1 (RST ? 1'd0 : _rLenValid);
+	rRen <= #1 (RST ? 1'd0 : _rRen);
+end
+
+always @ (*) begin
+	_rLenValid = LEN_VALID;
+	_rRen = RD_EN;
+end
+
+
+// FIFO for storing data from the channel.
+(* RAM_STYLE="BLOCK" *)
+sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
+	.CLK(CLK),
+	.RST(RST),
+	.WR_EN(WR_EN),
+	.WR_DATA(WR_DATA),
+	.FULL(),
+	.COUNT(WR_COUNT),
+	.RD_EN(rFifoRdEn),
+	.RD_DATA(wFifoData),
+	.EMPTY()
+);
+
+
+// Manage shifting of data in from the FIFO and shifting of data out once
+// it is consumed. We'll keep 7 words of output registers to hold an input
+// packet with up to 3 extra words of unread data.
+wire [1:0] wLenLSB = {rLenLSB1[rRdPtr], rLenLSB0[rRdPtr]};
+wire wLenLast = rLenLast[rRdPtr];
+wire wAfterEnd = (!rRen & rRdEnHist[0]);
+    // consumed = 4 if RD+2
+    // consumed = remainder if EOP on RD+1 (~rRen & rRdEnHist[0])
+    // consumed = 4 if EOP on RD+3 and LAST on RD+3
+wire [2:0] wConsumed = ({(rRdEnHist[0] | (!rRdEnHist[0] & rRdEnHist[1] & rLenLastHist[0])),2'd0}) - ({2{wAfterEnd}} & wLenLSB);
+
+always @ (posedge CLK) begin
+	rCount <= #1 (RST ? 2'd0 : _rCount);
+	rCountHist <= #1 _rCountHist;
+	rRdEnHist <= #1 (RST ? {C_RD_EN_HIST{1'd0}} : _rRdEnHist);
+	rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
+	rFifoRdEnHist <= #1 (RST ? {C_FIFO_RD_EN_HIST{1'd0}} : _rFifoRdEnHist);
+	rConsumedHist <= #1 _rConsumedHist;
+	rLenLastHist <= #1 (RST ? {C_LEN_LAST_HIST{1'd0}} : _rLenLastHist);
+	rFifoData <= #1 _rFifoData;
+	rData <= #1 _rData;
+end
+
+always @ (*) begin
+	// Keep track of words in our buffer. Subtract 4 when we reach 4 on RD_EN.
+	// Add wLenLSB when we finish a sequence of RD_EN that read 1, 2, or 3 words.
+    // rCount + remainder
+	_rCount = rCount + ({2{(wAfterEnd & !wLenLast)}} & wLenLSB) - ({(rRen & rCount[2]), 2'd0}) - ({3{(wAfterEnd & wLenLast)}} & rCount);
+	_rCountHist = ((rCountHist<<3) | rCount);
+
+	// Track read enables in the pipeline.
+	_rRdEnHist = ((rRdEnHist<<1) | rRen);
+	_rFifoRdEnHist = ((rFifoRdEnHist<<1) | rFifoRdEn);
+	
+	// Track delayed length last value
+	_rLenLastHist = ((rLenLastHist<<1) | wLenLast);
+
+	// Calculate the amount to shift out each RD_EN. This is always 4 unless it's
+	// the last RD_EN in the sequence and the read words length is 1, 2, or 3.
+	_rConsumedHist = ((rConsumedHist<<3) | wConsumed);
+
+	// Read from the FIFO unless we have 4 words cached.
+	_rFifoRdEn = (!rCount[2] & rRen);
+
+	// Buffer the FIFO data.
+	_rFifoData = wFifoData;
+
+	// Shift the buffered FIFO data into and the consumed data out of the output register.
+	if (rFifoRdEnHist[1])
+		_rData = ((rData>>({rConsumedHist[8:6], 5'd0})) | (rFifoData<<({rCountHist[7:6], 5'd0})));
+	else
+		_rData = (rData>>({rConsumedHist[8:6], 5'd0}));
+end
+
+
+// Buffer up to 4 length LSB values for use to detect unread data that was
+// part of a consumed packet. Should only need 2. This is basically a FIFO.
+always @ (posedge CLK) begin
+	rRdPtr <= #1 (RST ? 2'd0 : _rRdPtr);
+	rWrPtr <= #1 (RST ? 2'd0 : _rWrPtr);
+	rLenLSB0 <= #1 _rLenLSB0;
+	rLenLSB1 <= #1 _rLenLSB1;
+	rLenLast <= #1 _rLenLast;
+end
+
+always @ (*) begin
+	_rRdPtr = (wAfterEnd ? rRdPtr + 1'd1 : rRdPtr);
+	_rWrPtr = (rLenValid ? rWrPtr + 1'd1 : rWrPtr);
+	_rLenLSB0 = rLenLSB0;
+	_rLenLSB1 = rLenLSB1;
+	{_rLenLSB1[rWrPtr], _rLenLSB0[rWrPtr]} = (rLenValid ? (~LEN_LSB + 1'd1) : {rLenLSB1[rWrPtr], rLenLSB0[rWrPtr]}); // Negative ,
+	_rLenLast = rLenLast;
+	_rLenLast[rWrPtr] = (rLenValid ? LEN_LAST : rLenLast[rWrPtr]);
+end
+
+
+
+/*
+wire [35:0] wControl0;
+chipscope_icon_1 cs_icon(
+	.CONTROL0(wControl0)
+);
+
+chipscope_ila_t8_512_max a0(
+	.CLK(CLK), 
+	.CONTROL(wControl0), 
+	.TRIG0({2'd0, rCount, RD_EN, WR_EN, rFifoRdEn}),
+	.DATA({4'd0,
+			wLenLSB, // 2
+			wLenLast, // 1
+			wAfterEnd, // 1
+			wConsumed, // 3
+			rData, // 224
+			rFifoRdEn, // 1
+			rCount, // 3
+			rRen, // 1
+			RD_EN, // 1
+			RD_DATA, // 128
+			WR_COUNT, // 10
+			WR_EN, // 1
+			WR_DATA, // 128
+			LEN_LSB, // 2
+			LEN_LAST, // 1
+			LEN_VALID}) // 1
+);
+*/
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_port_buffer_32.v b/fpga/riffa_hdl/tx_port_buffer_32.v
new file mode 100644
index 0000000..9401843
--- /dev/null
+++ b/fpga/riffa_hdl/tx_port_buffer_32.v
@@ -0,0 +1,109 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			tx_port_buffer_32.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Wraps a FIFO for saving channel data and provides a 
+// registered read output. Data is available 3 cycles after RD_EN is asserted 
+// (not 1, like a traditional FIFO).
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+
+`timescale 1ns/1ns
+module tx_port_buffer_32 #(
+	parameter C_FIFO_DATA_WIDTH = 9'd32,
+	parameter C_FIFO_DEPTH = 512,
+	// Local parameters
+	parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
+)
+(
+	input RST,
+	input CLK,
+
+	input [C_FIFO_DATA_WIDTH-1:0] WR_DATA,		// Input data
+	input WR_EN,								// Input data write enable
+	output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT,	// Input data FIFO is full
+
+	output [C_FIFO_DATA_WIDTH-1:0] RD_DATA,		// Output data
+	input RD_EN									// Output data read enable
+);
+
+`include "functions.vh"
+
+reg 								rFifoRdEn=0, _rFifoRdEn=0;
+reg		[C_FIFO_DATA_WIDTH-1:0]		rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
+wire	[C_FIFO_DATA_WIDTH-1:0]		wFifoData;
+
+assign RD_DATA = rFifoData;
+
+
+// Buffer the input signals that come from outside the tx_port.
+always @ (posedge CLK) begin
+	rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
+end
+
+always @ (*) begin
+	_rFifoRdEn = RD_EN;
+end
+
+
+// FIFO for storing data from the channel.
+(* RAM_STYLE="BLOCK" *)
+sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
+	.CLK(CLK),
+	.RST(RST),
+	.WR_EN(WR_EN),
+	.WR_DATA(WR_DATA),
+	.FULL(),
+	.COUNT(WR_COUNT),
+	.RD_EN(rFifoRdEn),
+	.RD_DATA(wFifoData),
+	.EMPTY()
+);
+
+
+// Buffer data from the FIFO.
+always @ (posedge CLK) begin
+	rFifoData <= #1 _rFifoData;
+end
+
+always @ (*) begin
+	_rFifoData = wFifoData;
+end
+
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_port_buffer_64.v b/fpga/riffa_hdl/tx_port_buffer_64.v
new file mode 100644
index 0000000..69c0177
--- /dev/null
+++ b/fpga/riffa_hdl/tx_port_buffer_64.v
@@ -0,0 +1,196 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			tx_port_buffer_64.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Wraps a FIFO for saving channel data and provides a 
+// registered read output. Retains unread words from reads that are a length 
+// which is not a multiple of the data bus width (C_FIFO_DATA_WIDTH). Data is
+// available 5 cycles after RD_EN is asserted (not 1, like a traditional FIFO).
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+
+`timescale 1ns/1ns
+module tx_port_buffer_64 #(
+	parameter C_FIFO_DATA_WIDTH = 9'd64,
+	parameter C_FIFO_DEPTH = 512,
+	// Local parameters
+	parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
+	parameter C_RD_EN_HIST = 2,
+	parameter C_FIFO_RD_EN_HIST = 2,
+	parameter C_CONSUME_HIST = 3,
+	parameter C_COUNT_HIST = 3,
+	parameter C_LEN_LAST_HIST = 1
+)
+(
+	input RST,
+	input CLK,
+
+	input LEN_VALID,							// Transfer length is valid
+	input [0:0] LEN_LSB,						// LSBs of transfer length
+	input LEN_LAST,								// Last transfer in transaction
+
+	input [C_FIFO_DATA_WIDTH-1:0] WR_DATA,		// Input data
+	input WR_EN,								// Input data write enable
+	output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT,	// Input data FIFO is full
+
+	output [C_FIFO_DATA_WIDTH-1:0] RD_DATA,		// Output data
+	input RD_EN									// Output data read enable
+);
+
+`include "functions.vh"
+
+reg 	[1:0]						rRdPtr=0, _rRdPtr=0;
+reg 	[1:0]						rWrPtr=0, _rWrPtr=0;
+reg 	[3:0]						rLenLSB=0, _rLenLSB=0;
+reg 	[3:0]						rLenLast=0, _rLenLast=0;
+reg									rLenValid=0, _rLenValid=0;
+
+reg									rRen=0, _rRen=0;	
+reg 	[1:0]						rCount=0, _rCount=0;
+reg 	[(C_COUNT_HIST*2)-1:0]		rCountHist={C_COUNT_HIST{2'd0}}, _rCountHist={C_COUNT_HIST{2'd0}};
+reg 	[C_LEN_LAST_HIST-1:0]		rLenLastHist={C_LEN_LAST_HIST{1'd0}}, _rLenLastHist={C_LEN_LAST_HIST{1'd0}};
+reg 	[C_RD_EN_HIST-1:0]			rRdEnHist={C_RD_EN_HIST{1'd0}}, _rRdEnHist={C_RD_EN_HIST{1'd0}};
+reg 								rFifoRdEn=0, _rFifoRdEn=0;
+reg 	[C_FIFO_RD_EN_HIST-1:0]		rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}}, _rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}};
+reg 	[(C_CONSUME_HIST*2)-1:0]	rConsumedHist={C_CONSUME_HIST{2'd0}}, _rConsumedHist={C_CONSUME_HIST{2'd0}};
+reg		[C_FIFO_DATA_WIDTH-1:0]		rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
+reg		[95:0]						rData=96'd0, _rData=96'd0;
+
+wire	[C_FIFO_DATA_WIDTH-1:0]		wFifoData;
+
+assign RD_DATA = rData[0 +:C_FIFO_DATA_WIDTH];
+
+
+// Buffer the input signals that come from outside the tx_port.
+always @ (posedge CLK) begin
+	rLenValid <= #1 (RST ? 1'd0 : _rLenValid);
+	rRen <= #1 (RST ? 1'd0 : _rRen);
+end
+
+always @ (*) begin
+	_rLenValid = LEN_VALID;
+	_rRen = RD_EN;
+end
+
+
+// FIFO for storing data from the channel.
+(* RAM_STYLE="BLOCK" *)
+sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
+	.CLK(CLK),
+	.RST(RST),
+	.WR_EN(WR_EN),
+	.WR_DATA(WR_DATA),
+	.FULL(),
+	.COUNT(WR_COUNT),
+	.RD_EN(rFifoRdEn),
+	.RD_DATA(wFifoData),
+	.EMPTY()
+);
+
+
+// Manage shifting of data in from the FIFO and shifting of data out once
+// it is consumed. We'll keep 3 words of output registers to hold an input
+// packet with up to 1 extra word of unread data.
+wire wLenOdd = rLenLSB[rRdPtr];
+wire wLenLast = rLenLast[rRdPtr];
+wire wAfterEnd = (!rRen & rRdEnHist[0]);
+wire [1:0] wConsumed = ({(rRdEnHist[0] | (!rRdEnHist[0] & rRdEnHist[1] & rLenLastHist[0])), 1'd0}) - (wAfterEnd & wLenOdd);
+   
+always @ (posedge CLK) begin
+	rCount <= #1 (RST ? 2'd0 : _rCount);
+	rCountHist <= #1 _rCountHist;
+	rRdEnHist <= #1 (RST ? {C_RD_EN_HIST{1'd0}} : _rRdEnHist);
+	rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
+	rFifoRdEnHist <= #1 (RST ? {C_FIFO_RD_EN_HIST{1'd0}} : _rFifoRdEnHist);
+	rConsumedHist <= #1 _rConsumedHist;
+	rLenLastHist <= #1 (RST ? {C_LEN_LAST_HIST{1'd0}} : _rLenLastHist);
+	rFifoData <= #1 _rFifoData;
+	rData <= #1 _rData;
+end
+
+always @ (*) begin
+	// Keep track of words in our buffer. Subtract 2 when we reach 2 on RD_EN.
+	// Add 1 when we finish a sequence of RD_EN that read an odd number of words.
+	_rCount = rCount + (wAfterEnd & wLenOdd & !wLenLast) - ({rRen & rCount[1], 1'd0}) - ({(wAfterEnd & wLenLast)&rCount[1], (wAfterEnd & wLenLast)&rCount[0]});
+	_rCountHist = ((rCountHist<<2) | rCount);
+
+	// Track read enables in the pipeline.
+	_rRdEnHist = ((rRdEnHist<<1) | rRen);
+	_rFifoRdEnHist = ((rFifoRdEnHist<<1) | rFifoRdEn);
+	
+	// Track delayed length last value
+	_rLenLastHist = ((rLenLastHist<<1) | wLenLast);
+
+	// Calculate the amount to shift out each RD_EN. This is always 2 unless
+	// it's the last RD_EN in the sequence and the read words length is odd.
+	_rConsumedHist = ((rConsumedHist<<2) | wConsumed);
+
+	// Read from the FIFO unless we have 2 words cached.
+	_rFifoRdEn = (!rCount[1] & rRen);
+
+	// Buffer the FIFO data.
+	_rFifoData = wFifoData;
+
+	// Shift the buffered FIFO data into and the consumed data out of the output register.
+	if (rFifoRdEnHist[1])
+		_rData = ((rData>>({rConsumedHist[5:4], 5'd0})) | (rFifoData<<({rCountHist[4], 5'd0})));
+	else
+		_rData = (rData>>({rConsumedHist[5:4], 5'd0}));
+end
+
+
+// Buffer up to 4 length LSB values for use to detect unread data that was
+// part of a consumed packet. Should only need 2. This is basically a FIFO.
+always @ (posedge CLK) begin
+	rRdPtr <= #1 (RST ? 2'd0 : _rRdPtr);
+	rWrPtr <= #1 (RST ? 2'd0 : _rWrPtr);
+	rLenLSB <= #1 _rLenLSB;
+	rLenLast <= #1 _rLenLast;
+end
+
+always @ (*) begin
+	_rRdPtr = (wAfterEnd ? rRdPtr + 1'd1 : rRdPtr);
+	_rWrPtr = (rLenValid ? rWrPtr + 1'd1 : rWrPtr);
+	_rLenLSB = rLenLSB;
+	_rLenLSB[rWrPtr] = (rLenValid ? (~LEN_LSB + 1'd1) : rLenLSB[rWrPtr]);
+	_rLenLast = rLenLast;
+	_rLenLast[rWrPtr] = (rLenValid ? LEN_LAST : rLenLast[rWrPtr]);
+end
+
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_port_channel_gate_128.v b/fpga/riffa_hdl/tx_port_channel_gate_128.v
new file mode 100644
index 0000000..336673b
--- /dev/null
+++ b/fpga/riffa_hdl/tx_port_channel_gate_128.v
@@ -0,0 +1,221 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			tx_port_channel_gate_128.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Captures transaction open/close events as well as data
+// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can
+// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When
+// CHNL_TX drops, the channel closes (until the next transaction -- signaled by
+// CHNL_TX going up again).
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`define S_TXPORTGATE128_IDLE		2'b00
+`define S_TXPORTGATE128_OPENING		2'b01
+`define S_TXPORTGATE128_OPEN		2'b10
+`define S_TXPORTGATE128_CLOSED		2'b11
+
+`timescale 1ns/1ns
+module tx_port_channel_gate_128 #(
+	parameter C_DATA_WIDTH = 9'd128,
+	// Local parameters
+	parameter C_FIFO_DEPTH = 8,
+	parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1
+)
+(
+	input RST,
+
+	input RD_CLK,							// FIFO read clock
+	output [C_FIFO_DATA_WIDTH-1:0] RD_DATA,	// FIFO read data
+	output RD_EMPTY,						// FIFO is empty
+	input RD_EN,							// FIFO read enable
+
+	input CHNL_CLK,							// Channel write clock
+	input CHNL_TX,							// Channel write receive signal
+	output CHNL_TX_ACK,						// Channel write acknowledgement signal
+	input CHNL_TX_LAST,						// Channel last write
+	input [31:0] CHNL_TX_LEN,				// Channel write length (in 32 bit words)
+	input [30:0] CHNL_TX_OFF,				// Channel write offset
+	input [C_DATA_WIDTH-1:0] CHNL_TX_DATA,	// Channel write data
+	input CHNL_TX_DATA_VALID,				// Channel write data valid
+	output CHNL_TX_DATA_REN					// Channel write data has been recieved
+);
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg		[1:0]					rState=`S_TXPORTGATE128_IDLE, _rState=`S_TXPORTGATE128_IDLE;
+reg								rFifoWen=0, _rFifoWen=0;
+reg		[C_FIFO_DATA_WIDTH-1:0]	rFifoData=0, _rFifoData=0;
+wire						    wFifoFull;
+
+reg								rChnlTx=0, _rChnlTx=0;
+reg								rChnlLast=0, _rChnlLast=0;
+reg		[31:0]					rChnlLen=0, _rChnlLen=0;
+reg		[30:0]					rChnlOff=0, _rChnlOff=0;
+reg								rAck=0, _rAck=0;
+reg								rPause=0, _rPause=0;
+reg								rClosed=0, _rClosed=0;
+
+
+assign CHNL_TX_ACK = rAck;
+assign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE128_OPEN
+
+
+// Buffer the input signals that come from outside the tx_port.
+always @ (posedge CHNL_CLK) begin
+	rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
+	rChnlLast <= #1 _rChnlLast;
+	rChnlLen <= #1 _rChnlLen;
+	rChnlOff <= #1 _rChnlOff;
+end
+
+always @ (*) begin
+	_rChnlTx = CHNL_TX;
+	_rChnlLast = CHNL_TX_LAST;
+	_rChnlLen = CHNL_TX_LEN;
+	_rChnlOff = CHNL_TX_OFF;
+end
+
+
+// FIFO for temporarily storing data from the channel.
+(* RAM_STYLE="DISTRIBUTED" *)
+async_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo (
+	.WR_CLK(CHNL_CLK),
+	.WR_RST(RST),
+	.WR_EN(rFifoWen),
+	.WR_DATA(rFifoData),
+	.WR_FULL(wFifoFull),
+	.RD_CLK(RD_CLK),
+	.RD_RST(RST),
+	.RD_EN(RD_EN),
+	.RD_DATA(RD_DATA),
+	.RD_EMPTY(RD_EMPTY)
+);
+
+
+// Pass the transaction open event, transaction data, and the transaction
+// close event through to the RD_CLK domain via the async_fifo.
+always @ (posedge CHNL_CLK) begin
+	rState <= #1 (RST ? `S_TXPORTGATE128_IDLE : _rState);
+	rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
+	rFifoData <= #1 _rFifoData;
+	rAck <= #1 (RST ? 1'd0 : _rAck);
+	rPause <= #1 (RST ? 1'd0 : _rPause);
+	rClosed <= #1 (RST ? 1'd0 : _rClosed);
+end
+
+always @ (*) begin
+	_rState = rState;
+	_rFifoWen = rFifoWen;
+	_rFifoData = rFifoData;
+	_rPause = rPause;
+	_rAck = rAck;
+	_rClosed = rClosed;
+	case (rState)
+
+	`S_TXPORTGATE128_IDLE: begin // Write the len, off, last
+		_rPause = 0;
+		_rClosed = 0;
+		if (!wFifoFull) begin
+			_rAck = rChnlTx;
+			_rFifoWen = rChnlTx;
+			_rFifoData = {1'd1, 64'd0, rChnlLen, rChnlOff, rChnlLast};
+			if (rChnlTx)
+				_rState = `S_TXPORTGATE128_OPENING;
+		end
+	end
+
+	`S_TXPORTGATE128_OPENING: begin // Write the len, off, last (again)
+		_rAck = 0;
+		_rClosed = (rClosed | !rChnlTx);
+		if (!wFifoFull) begin
+			if (rClosed | !rChnlTx)
+				_rState = `S_TXPORTGATE128_CLOSED;
+			else
+				_rState = `S_TXPORTGATE128_OPEN;
+		end
+	end
+
+	`S_TXPORTGATE128_OPEN: begin // Copy channel data into the FIFO
+		if (!wFifoFull) begin
+			_rFifoWen = CHNL_TX_DATA_VALID; 	// CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
+			_rFifoData = {1'd0, CHNL_TX_DATA};	// but the VALID+REN model seem to make this difficult.
+		end
+		if (!rChnlTx)
+			_rState = `S_TXPORTGATE128_CLOSED;
+	end
+	
+	`S_TXPORTGATE128_CLOSED: begin // Write the end marker (twice)
+		if (!wFifoFull) begin
+			_rPause = 1;
+			_rFifoWen = 1;
+			_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
+			if (rPause)
+			_rState = `S_TXPORTGATE128_IDLE;
+		end
+	end
+	
+	endcase	
+end
+
+/*
+wire [35:0] wControl0;
+chipscope_icon_1 cs_icon(
+	.CONTROL0(wControl0)
+);
+
+chipscope_ila_t8_512 a0(
+	.CLK(CHNL_CLK), 
+	.CONTROL(wControl0), 
+	.TRIG0({4'd0, wFifoFull, CHNL_TX, rState}),
+	.DATA({313'd0,
+			rChnlOff, // 31
+			rChnlLen, // 32
+			rChnlLast, // 1
+			rChnlTx, // 1
+			CHNL_TX_OFF, // 31
+			CHNL_TX_LEN, // 32
+			CHNL_TX_LAST, // 1
+			CHNL_TX, // 1
+			wFifoFull, // 1
+			rFifoData, // 65
+			rFifoWen, // 1
+			rState}) // 2
+);
+*/
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_port_channel_gate_32.v b/fpga/riffa_hdl/tx_port_channel_gate_32.v
new file mode 100644
index 0000000..0cb4e08
--- /dev/null
+++ b/fpga/riffa_hdl/tx_port_channel_gate_32.v
@@ -0,0 +1,223 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			tx_port_channel_gate_32.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Captures transaction open/close events as well as data
+// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can
+// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When
+// CHNL_TX drops, the channel closes (until the next transaction -- signaled by
+// CHNL_TX going up again).
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`define S_TXPORTGATE32_IDLE		2'b00
+`define S_TXPORTGATE32_OPENING	2'b01
+`define S_TXPORTGATE32_OPEN		2'b10
+`define S_TXPORTGATE32_CLOSED	2'b11
+
+`timescale 1ns/1ns
+module tx_port_channel_gate_32 #(
+	parameter C_DATA_WIDTH = 9'd32,
+	// Local parameters
+	parameter C_FIFO_DEPTH = 8,
+	parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1
+)
+(
+	input RST,
+
+	input RD_CLK,							// FIFO read clock
+	output [C_FIFO_DATA_WIDTH-1:0] RD_DATA,	// FIFO read data
+	output RD_EMPTY,						// FIFO is empty
+	input RD_EN,							// FIFO read enable
+
+	input CHNL_CLK,							// Channel write clock
+	input CHNL_TX,							// Channel write receive signal
+	output CHNL_TX_ACK,						// Channel write acknowledgement signal
+	input CHNL_TX_LAST,						// Channel last write
+	input [31:0] CHNL_TX_LEN,				// Channel write length (in 32 bit words)
+	input [30:0] CHNL_TX_OFF,				// Channel write offset
+	input [C_DATA_WIDTH-1:0] CHNL_TX_DATA,	// Channel write data
+	input CHNL_TX_DATA_VALID,				// Channel write data valid
+	output CHNL_TX_DATA_REN					// Channel write data has been recieved
+);
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg		[1:0]					rState=`S_TXPORTGATE32_IDLE, _rState=`S_TXPORTGATE32_IDLE;
+reg								rFifoWen=0, _rFifoWen=0;
+reg		[C_FIFO_DATA_WIDTH-1:0]	rFifoData=0, _rFifoData=0;
+wire							wFifoFull;
+
+reg								rChnlTx=0, _rChnlTx=0;
+reg								rChnlLast=0, _rChnlLast=0;
+reg		[31:0]					rChnlLen=0, _rChnlLen=0;
+reg		[30:0]					rChnlOff=0, _rChnlOff=0;
+reg								rAck=0, _rAck=0;
+reg								rPause=0, _rPause=0;
+reg								rClosed=0, _rClosed=0;
+
+
+assign CHNL_TX_ACK = rAck;
+assign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE32_OPEN
+
+
+// Buffer the input signals that come from outside the tx_port.
+always @ (posedge CHNL_CLK) begin
+	rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
+	rChnlLast <= #1 _rChnlLast;
+	rChnlLen <= #1 _rChnlLen;
+	rChnlOff <= #1 _rChnlOff;
+end
+
+always @ (*) begin
+	_rChnlTx = CHNL_TX;
+	_rChnlLast = CHNL_TX_LAST;
+	_rChnlLen = CHNL_TX_LEN;
+	_rChnlOff = CHNL_TX_OFF;
+end
+
+
+// FIFO for temporarily storing data from the channel.
+(* RAM_STYLE="DISTRIBUTED" *)
+async_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo (
+	.WR_CLK(CHNL_CLK),
+	.WR_RST(RST),
+	.WR_EN(rFifoWen),
+	.WR_DATA(rFifoData),
+	.WR_FULL(wFifoFull),
+	.RD_CLK(RD_CLK),
+	.RD_RST(RST),
+	.RD_EN(RD_EN),
+	.RD_DATA(RD_DATA),
+	.RD_EMPTY(RD_EMPTY)
+);
+
+
+// Pass the transaction open event, transaction data, and the transaction
+// close event through to the RD_CLK domain via the async_fifo.
+always @ (posedge CHNL_CLK) begin
+	rState <= #1 (RST ? `S_TXPORTGATE32_IDLE : _rState);
+	rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
+	rFifoData <= #1 _rFifoData;
+	rAck <= #1 (RST ? 1'd0 : _rAck);
+	rPause <= #1 (RST ? 1'd0 : _rPause);
+	rClosed <= #1 (RST ? 1'd0 : _rClosed);
+end
+
+always @ (*) begin
+	_rState = rState;
+	_rFifoWen = rFifoWen;
+	_rFifoData = rFifoData;
+	_rPause = rPause;
+	_rAck = rAck;
+	_rClosed = rClosed;
+	case (rState)
+
+	`S_TXPORTGATE32_IDLE: begin // Write the len
+		_rPause = 0;
+		_rClosed = 0;
+		if (!wFifoFull) begin
+			_rFifoWen = rChnlTx;
+			_rFifoData = {1'd1, rChnlLen};
+			if (rChnlTx)
+				_rState = `S_TXPORTGATE32_OPENING;
+		end
+	end
+
+	`S_TXPORTGATE32_OPENING: begin // Write the off, last
+		_rClosed = (rClosed | !rChnlTx);
+		if (!wFifoFull) begin
+			_rAck = rChnlTx;
+			_rFifoData = {1'd1, rChnlOff, rChnlLast};
+			if (rClosed | !rChnlTx)
+				_rState = `S_TXPORTGATE32_CLOSED;
+			else
+				_rState = `S_TXPORTGATE32_OPEN;
+		end
+	end
+
+	`S_TXPORTGATE32_OPEN: begin // Copy channel data into the FIFO
+		_rAck = 0;
+		if (!wFifoFull) begin
+			_rFifoWen = CHNL_TX_DATA_VALID; 	// CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
+			_rFifoData = {1'd0, CHNL_TX_DATA};	// but the VALID+REN model seem to make this difficult.
+		end
+		if (!rChnlTx)
+			_rState = `S_TXPORTGATE32_CLOSED;
+	end
+	
+	`S_TXPORTGATE32_CLOSED: begin // Write the end marker (twice)
+		_rAck = 0;
+		if (!wFifoFull) begin
+			_rPause = 1;
+			_rFifoWen = 1;
+			_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
+			if (rPause)
+			_rState = `S_TXPORTGATE32_IDLE;
+		end
+	end
+	
+	endcase	
+end
+
+/*
+wire [35:0] wControl0;
+chipscope_icon_1 cs_icon(
+	.CONTROL0(wControl0)
+);
+
+chipscope_ila_t8_512 a0(
+	.CLK(CHNL_CLK), 
+	.CONTROL(wControl0), 
+	.TRIG0({4'd0, wFifoFull, CHNL_TX, rState}),
+	.DATA({313'd0,
+			rChnlOff, // 31
+			rChnlLen, // 32
+			rChnlLast, // 1
+			rChnlTx, // 1
+			CHNL_TX_OFF, // 31
+			CHNL_TX_LEN, // 32
+			CHNL_TX_LAST, // 1
+			CHNL_TX, // 1
+			wFifoFull, // 1
+			rFifoData, // 65
+			rFifoWen, // 1
+			rState}) // 2
+);
+*/
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_port_channel_gate_64.v b/fpga/riffa_hdl/tx_port_channel_gate_64.v
new file mode 100644
index 0000000..97d5a44
--- /dev/null
+++ b/fpga/riffa_hdl/tx_port_channel_gate_64.v
@@ -0,0 +1,221 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			tx_port_channel_gate_64.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Captures transaction open/close events as well as data
+// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can
+// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When
+// CHNL_TX drops, the channel closes (until the next transaction -- signaled by
+// CHNL_TX going up again).
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`define S_TXPORTGATE64_IDLE		2'b00
+`define S_TXPORTGATE64_OPENING	2'b01
+`define S_TXPORTGATE64_OPEN		2'b10
+`define S_TXPORTGATE64_CLOSED	2'b11
+
+`timescale 1ns/1ns
+module tx_port_channel_gate_64 #(
+	parameter C_DATA_WIDTH = 9'd64,
+	// Local parameters
+	parameter C_FIFO_DEPTH = 8,
+	parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1
+)
+(
+	input RST,
+
+	input RD_CLK,							// FIFO read clock
+	output [C_FIFO_DATA_WIDTH-1:0] RD_DATA,	// FIFO read data
+	output RD_EMPTY,						// FIFO is empty
+	input RD_EN,							// FIFO read enable
+
+	input CHNL_CLK,							// Channel write clock
+	input CHNL_TX,							// Channel write receive signal
+	output CHNL_TX_ACK,						// Channel write acknowledgement signal
+	input CHNL_TX_LAST,						// Channel last write
+	input [31:0] CHNL_TX_LEN,				// Channel write length (in 32 bit words)
+	input [30:0] CHNL_TX_OFF,				// Channel write offset
+	input [C_DATA_WIDTH-1:0] CHNL_TX_DATA,	// Channel write data
+	input CHNL_TX_DATA_VALID,				// Channel write data valid
+	output CHNL_TX_DATA_REN					// Channel write data has been recieved
+);
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg		[1:0]					rState=`S_TXPORTGATE64_IDLE, _rState=`S_TXPORTGATE64_IDLE;
+reg								rFifoWen=0, _rFifoWen=0;
+reg		[C_FIFO_DATA_WIDTH-1:0]	rFifoData=0, _rFifoData=0;
+wire							wFifoFull;
+
+reg								rChnlTx=0, _rChnlTx=0;
+reg								rChnlLast=0, _rChnlLast=0;
+reg		[31:0]					rChnlLen=0, _rChnlLen=0;
+reg		[30:0]					rChnlOff=0, _rChnlOff=0;
+reg								rAck=0, _rAck=0;
+reg								rPause=0, _rPause=0;
+reg								rClosed=0, _rClosed=0;
+
+
+assign CHNL_TX_ACK = rAck;
+assign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE64_OPEN
+
+
+// Buffer the input signals that come from outside the tx_port.
+always @ (posedge CHNL_CLK) begin
+	rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
+	rChnlLast <= #1 _rChnlLast;
+	rChnlLen <= #1 _rChnlLen;
+	rChnlOff <= #1 _rChnlOff;
+end
+
+always @ (*) begin
+	_rChnlTx = CHNL_TX;
+	_rChnlLast = CHNL_TX_LAST;
+	_rChnlLen = CHNL_TX_LEN;
+	_rChnlOff = CHNL_TX_OFF;
+end
+
+
+// FIFO for temporarily storing data from the channel.
+(* RAM_STYLE="DISTRIBUTED" *)
+async_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo (
+	.WR_CLK(CHNL_CLK),
+	.WR_RST(RST),
+	.WR_EN(rFifoWen),
+	.WR_DATA(rFifoData),
+	.WR_FULL(wFifoFull),
+	.RD_CLK(RD_CLK),
+	.RD_RST(RST),
+	.RD_EN(RD_EN),
+	.RD_DATA(RD_DATA),
+	.RD_EMPTY(RD_EMPTY)
+);
+
+
+// Pass the transaction open event, transaction data, and the transaction
+// close event through to the RD_CLK domain via the async_fifo.
+always @ (posedge CHNL_CLK) begin
+	rState <= #1 (RST ? `S_TXPORTGATE64_IDLE : _rState);
+	rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
+	rFifoData <= #1 _rFifoData;
+	rAck <= #1 (RST ? 1'd0 : _rAck);
+	rPause <= #1 (RST ? 1'd0 : _rPause);
+	rClosed <= #1 (RST ? 1'd0 : _rClosed);
+end
+
+always @ (*) begin
+	_rState = rState;
+	_rFifoWen = rFifoWen;
+	_rFifoData = rFifoData;
+	_rPause = rPause;
+	_rAck = rAck;
+	_rClosed = rClosed;
+	case (rState)
+
+	`S_TXPORTGATE64_IDLE: begin // Write the len, off, last
+		_rPause = 0;
+		_rClosed = 0;
+		if (!wFifoFull) begin
+			_rAck = rChnlTx;
+			_rFifoWen = rChnlTx;
+			_rFifoData = {1'd1, rChnlLen, rChnlOff, rChnlLast};
+			if (rChnlTx)
+				_rState = `S_TXPORTGATE64_OPENING;
+		end
+	end
+
+	`S_TXPORTGATE64_OPENING: begin // Write the len, off, last (again)
+		_rAck = 0;
+		_rClosed = (rClosed | !rChnlTx);
+		if (!wFifoFull) begin
+			if (rClosed | !rChnlTx)
+				_rState = `S_TXPORTGATE64_CLOSED;
+			else
+				_rState = `S_TXPORTGATE64_OPEN;
+		end
+	end
+
+	`S_TXPORTGATE64_OPEN: begin // Copy channel data into the FIFO
+		if (!wFifoFull) begin
+			_rFifoWen = CHNL_TX_DATA_VALID; 	// CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
+			_rFifoData = {1'd0, CHNL_TX_DATA};	// but the VALID+REN model seem to make this difficult.
+		end
+		if (!rChnlTx)
+			_rState = `S_TXPORTGATE64_CLOSED;
+	end
+	
+	`S_TXPORTGATE64_CLOSED: begin // Write the end marker (twice)
+		if (!wFifoFull) begin
+			_rPause = 1;
+			_rFifoWen = 1;
+			_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
+			if (rPause)
+			_rState = `S_TXPORTGATE64_IDLE;
+		end
+	end
+	
+	endcase	
+end
+
+/*
+wire [35:0] wControl0;
+chipscope_icon_1 cs_icon(
+	.CONTROL0(wControl0)
+);
+
+chipscope_ila_t8_512 a0(
+	.CLK(CHNL_CLK), 
+	.CONTROL(wControl0), 
+	.TRIG0({4'd0, wFifoFull, CHNL_TX, rState}),
+	.DATA({313'd0,
+			rChnlOff, // 31
+			rChnlLen, // 32
+			rChnlLast, // 1
+			rChnlTx, // 1
+			CHNL_TX_OFF, // 31
+			CHNL_TX_LEN, // 32
+			CHNL_TX_LAST, // 1
+			CHNL_TX, // 1
+			wFifoFull, // 1
+			rFifoData, // 65
+			rFifoWen, // 1
+			rState}) // 2
+);
+*/
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_port_monitor_128.v b/fpga/riffa_hdl/tx_port_monitor_128.v
new file mode 100644
index 0000000..7be9980
--- /dev/null
+++ b/fpga/riffa_hdl/tx_port_monitor_128.v
@@ -0,0 +1,250 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			tx_port_monitor_128.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Detects transaction open/close events from the stream
+// of data from the tx_port_channel_gate. Filters out events and passes data
+// onto the tx_port_buffer. 
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`define S_TXPORTMON128_NEXT		5'b0_0001
+`define S_TXPORTMON128_TXN		5'b0_0010
+`define S_TXPORTMON128_READ		5'b0_0100
+`define S_TXPORTMON128_END_0	5'b0_1000
+`define S_TXPORTMON128_END_1	5'b1_0000
+
+`timescale 1ns/1ns
+module tx_port_monitor_128 #(
+	parameter C_DATA_WIDTH = 9'd128,
+	parameter C_FIFO_DEPTH = 512,
+	// Local parameters
+	parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),
+	parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
+	parameter C_VALID_HIST = 1
+)
+(
+	input RST,
+	input CLK,
+
+	input [C_DATA_WIDTH:0] EVT_DATA,			// Event data from tx_port_channel_gate
+	input EVT_DATA_EMPTY,						// Event data FIFO is empty
+	output EVT_DATA_RD_EN,						// Event data FIFO read enable
+
+	output [C_DATA_WIDTH-1:0] WR_DATA,			// Output data
+	output WR_EN,								// Write enable for output data
+	input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT,	// Output FIFO count
+
+	output TXN,									// Transaction parameters are valid
+	input ACK,									// Transaction parameter read, continue
+	output LAST,								// Channel last write
+	output [31:0] LEN,							// Channel write length (in 32 bit words)
+	output [30:0] OFF,							// Channel write offset
+	output [31:0] WORDS_RECVD,					// Count of data words received in transaction
+	output DONE,								// Transaction is closed
+
+	input TX_ERR								// Transaction encountered an error
+);
+
+`include "functions.vh"
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg 	[4:0]				rState=`S_TXPORTMON128_NEXT, _rState=`S_TXPORTMON128_NEXT;
+reg 						rRead=0, _rRead=0;
+reg 	[C_VALID_HIST-1:0]	rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
+reg 						rEvent=0, _rEvent=0;
+reg 	[63:0]				rReadData=64'd0, _rReadData=64'd0;
+reg 	[31:0]				rWordsRecvd=0, _rWordsRecvd=0;
+reg 	[31:0]				rWordsRecvdAdv=0, _rWordsRecvdAdv=0;
+reg 						rAlmostAllRecvd=0, _rAlmostAllRecvd=0;
+reg 						rAlmostFull=0, _rAlmostFull=0;
+reg 						rLenEQ0Hi=0, _rLenEQ0Hi=0;
+reg 						rLenEQ0Lo=0, _rLenEQ0Lo=0;
+reg 						rLenLE4Lo=0, _rLenLE4Lo=0;
+reg							rTxErr=0, _rTxErr=0;
+
+wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
+wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[2]); // S_TXPORTMON128_READ
+wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE4Lo)) & wPayloadData);
+
+assign EVT_DATA_RD_EN = rRead;
+
+assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
+assign WR_EN = wPayloadData; // S_TXPORTMON128_READ
+
+assign TXN = rState[1]; // S_TXPORTMON128_TXN
+assign LAST = rReadData[0];
+assign OFF = rReadData[31:1];
+assign LEN = rReadData[63:32];
+assign WORDS_RECVD = rWordsRecvd;
+assign DONE = !rState[2]; // !S_TXPORTMON128_READ
+
+
+
+
+// Buffer the input signals that come from outside the tx_port.
+always @ (posedge CLK) begin
+	rTxErr <= #1 (RST ? 1'd0 : _rTxErr);
+end
+
+always @ (*) begin
+	_rTxErr = TX_ERR;
+end
+
+
+// Transaction monitoring FSM.
+always @ (posedge CLK) begin
+	rState <= #1 (RST ? `S_TXPORTMON128_NEXT : _rState);
+end
+
+always @ (*) begin
+	_rState = rState;
+	case (rState)
+
+	`S_TXPORTMON128_NEXT: begin // Read, wait for start of transaction event
+		if (rEvent)
+			_rState = `S_TXPORTMON128_TXN;
+	end
+
+	`S_TXPORTMON128_TXN: begin // Don't read, wait until transaction has been acknowledged
+		if (ACK)
+			_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON128_END_0 : `S_TXPORTMON128_READ);
+	end
+
+	`S_TXPORTMON128_READ: begin // Continue reading, wait for end of transaction event or all expected data
+		if (rEvent)
+			_rState = `S_TXPORTMON128_END_1;
+		else if (wAllWordsRecvd | rTxErr)
+			_rState = `S_TXPORTMON128_END_0;
+	end
+	
+	`S_TXPORTMON128_END_0: begin // Continue reading, wait for first end of transaction event
+		if (rEvent)
+			_rState = `S_TXPORTMON128_END_1;
+	end
+
+	`S_TXPORTMON128_END_1: begin // Continue reading, wait for second end of transaction event
+		if (rEvent)
+			_rState = `S_TXPORTMON128_NEXT;
+	end
+
+	default: begin
+		_rState = `S_TXPORTMON128_NEXT;
+	end
+
+	endcase	
+end
+
+
+// Manage reading from the FIFO and tracking amounts read.
+always @ (posedge CLK) begin
+	rRead <= #1 (RST ? 1'd0 : _rRead);
+	rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);
+	rEvent <= #1 (RST ? 1'd0 : _rEvent);
+	rReadData <= #1 _rReadData;
+	rWordsRecvd <= #1 _rWordsRecvd;
+	rWordsRecvdAdv <= #1 _rWordsRecvdAdv;
+	rAlmostAllRecvd <= #1 _rAlmostAllRecvd;
+	rAlmostFull <= #1 _rAlmostFull;
+	rLenEQ0Hi <= #1 _rLenEQ0Hi;
+	rLenEQ0Lo <= #1 _rLenEQ0Lo;
+	rLenLE4Lo <= #1 _rLenLE4Lo;
+end
+
+always @ (*) begin
+	// Don't get to the full point in the output FIFO
+	_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);
+
+	// Track read history so we know when data is valid
+	_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
+
+	// Read until we get a (valid) event
+	_rRead = (!rState[1] & !wEventData & !rAlmostFull); // !S_TXPORTMON128_TXN
+
+	// Track detected events
+	_rEvent = wEventData;
+
+	// Save event data when valid
+	if (wEventData)
+		_rReadData = EVT_DATA[63:0];
+	else
+		_rReadData = rReadData;
+	
+	// If LEN == 0, we don't want to send any data to the output
+	_rLenEQ0Hi = (LEN[31:16] == 16'd0);
+	_rLenEQ0Lo = (LEN[15:0] == 16'd0);
+
+	// If LEN <= 4, we want to trigger the almost all received flag
+	_rLenLE4Lo = (LEN[15:0] <= 16'd4);
+	
+	// Count received non-event data
+	_rWordsRecvd = (ACK ? 0 : rWordsRecvd + (wPayloadData<<2));
+	_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + (wPayloadData<<2));
+	_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);
+end
+
+/*
+wire [35:0] wControl0;
+chipscope_icon_1 cs_icon(
+	.CONTROL0(wControl0)
+);
+
+chipscope_ila_t8_512 a0(
+	.CLK(CLK), 
+	.CONTROL(wControl0), 
+	.TRIG0({TXN, wPayloadData, wEventData, rState}),
+	.DATA({201'd0,
+			rWordsRecvd, // 32
+			WR_COUNT, // 10
+			wPayloadData, // 1
+			EVT_DATA_RD_EN, // 1
+			RST, // 1
+			rTxErr, // 1
+			wEventData, // 1
+			rReadData, // 64
+			OFF, // 31
+			LEN, // 32
+			LAST, // 1
+			TXN, // 1
+			EVT_DATA_EMPTY, // 1
+			EVT_DATA, // 129
+			rState}) // 5
+);
+*/
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_port_monitor_32.v b/fpga/riffa_hdl/tx_port_monitor_32.v
new file mode 100644
index 0000000..b692b1b
--- /dev/null
+++ b/fpga/riffa_hdl/tx_port_monitor_32.v
@@ -0,0 +1,259 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			tx_port_monitor_32.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Detects transaction open/close events from the stream
+// of data from the tx_port_channel_gate. Filters out events and passes data
+// onto the tx_port_buffer. 
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`define S_TXPORTMON32_NEXT	5'b0_0001
+`define S_TXPORTMON32_TXN	5'b0_0010
+`define S_TXPORTMON32_READ	5'b0_0100
+`define S_TXPORTMON32_END_0	5'b0_1000
+`define S_TXPORTMON32_END_1	5'b1_0000
+
+`timescale 1ns/1ns
+module tx_port_monitor_32 #(
+	parameter C_DATA_WIDTH = 9'd32,
+	parameter C_FIFO_DEPTH = 512,
+	// Local parameters
+	parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),
+	parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
+	parameter C_VALID_HIST = 1
+)
+(
+	input RST,
+	input CLK,
+
+	input [C_DATA_WIDTH:0] EVT_DATA,			// Event data from tx_port_channel_gate
+	input EVT_DATA_EMPTY,						// Event data FIFO is empty
+	output EVT_DATA_RD_EN,						// Event data FIFO read enable
+
+	output [C_DATA_WIDTH-1:0] WR_DATA,			// Output data
+	output WR_EN,								// Write enable for output data
+	input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT,	// Output FIFO count
+
+	output TXN,									// Transaction parameters are valid
+	input ACK,									// Transaction parameter read, continue
+	output LAST,								// Channel last write
+	output [31:0] LEN,							// Channel write length (in 32 bit words)
+	output [30:0] OFF,							// Channel write offset
+	output [31:0] WORDS_RECVD,					// Count of data words received in transaction
+	output DONE,								// Transaction is closed
+
+	input TX_ERR								// Transaction encountered an error
+);
+
+`include "functions.vh"
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg 	[4:0]				rState=`S_TXPORTMON32_NEXT, _rState=`S_TXPORTMON32_NEXT;
+reg 						rRead=0, _rRead=0;
+reg 	[C_VALID_HIST-1:0]	rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
+reg 						rEvent=0, _rEvent=0;
+reg 	[31:0]				rReadOffLast=0, _rReadOffLast=0;
+reg 	[31:0]				rReadLen=0, _rReadLen=0;
+reg 						rReadCount=0, _rReadCount=0;
+reg 	[31:0]				rWordsRecvd=0, _rWordsRecvd=0;
+reg 	[31:0]				rWordsRecvdAdv=0, _rWordsRecvdAdv=0;
+reg 						rAlmostAllRecvd=0, _rAlmostAllRecvd=0;
+reg 						rAlmostFull=0, _rAlmostFull=0;
+reg 						rLenEQ0Hi=0, _rLenEQ0Hi=0;
+reg 						rLenEQ0Lo=0, _rLenEQ0Lo=0;
+reg 						rLenLE1Lo=0, _rLenLE1Lo=0;
+reg							rTxErr=0, _rTxErr=0;
+
+wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
+wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[2]); // S_TXPORTMON32_READ
+wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE1Lo)) & wPayloadData);
+
+assign EVT_DATA_RD_EN = rRead;
+
+assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
+assign WR_EN = wPayloadData;
+
+assign TXN = rState[1]; // S_TXPORTMON32_TXN
+assign LAST = rReadOffLast[0];
+assign OFF = rReadOffLast[31:1];
+assign LEN = rReadLen;
+assign WORDS_RECVD = rWordsRecvd;
+assign DONE = !rState[2]; // !S_TXPORTMON32_READ
+
+
+
+
+// Buffer the input signals that come from outside the tx_port.
+always @ (posedge CLK) begin
+	rTxErr <= #1 (RST ? 1'd0 : _rTxErr);
+end
+
+always @ (*) begin
+	_rTxErr = TX_ERR;
+end
+
+
+// Transaction monitoring FSM.
+always @ (posedge CLK) begin
+	rState <= #1 (RST ? `S_TXPORTMON32_NEXT : _rState);
+end
+
+always @ (*) begin
+	_rState = rState;
+	case (rState)
+
+	`S_TXPORTMON32_NEXT: begin // Read, wait for start of transaction event
+		if (rEvent)
+			_rState = `S_TXPORTMON32_TXN;
+	end
+
+	`S_TXPORTMON32_TXN: begin // Don't read, wait until transaction has been acknowledged
+		if (ACK)
+			_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON32_END_0 : `S_TXPORTMON32_READ);
+	end
+
+	`S_TXPORTMON32_READ: begin // Continue reading, wait for end of transaction event or all expected data
+		if (rEvent)
+			_rState = `S_TXPORTMON32_END_1;
+		else if (wAllWordsRecvd | rTxErr)
+			_rState = `S_TXPORTMON32_END_0;
+	end
+	
+	`S_TXPORTMON32_END_0: begin // Continue reading, wait for first end of transaction event
+		if (rEvent)
+			_rState = `S_TXPORTMON32_END_1;
+	end
+
+	`S_TXPORTMON32_END_1: begin // Continue reading, wait for second end of transaction event
+		if (rEvent)
+			_rState = `S_TXPORTMON32_NEXT;
+	end
+
+	default: begin
+		_rState = `S_TXPORTMON32_NEXT;
+	end
+
+	endcase	
+end
+
+
+// Manage reading from the FIFO and tracking amounts read.
+always @ (posedge CLK) begin
+	rRead <= #1 (RST ? 1'd0 : _rRead);
+	rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);
+	rEvent <= #1 (RST ? 1'd0 : _rEvent);
+	rReadOffLast <= #1 _rReadOffLast;
+	rReadLen <= #1 _rReadLen;
+	rReadCount <= #1 (RST ? 1'd0 : _rReadCount);
+	rWordsRecvd <= #1 _rWordsRecvd;
+	rWordsRecvdAdv <= #1 _rWordsRecvdAdv;
+	rAlmostAllRecvd <= #1 _rAlmostAllRecvd;
+	rAlmostFull <= #1 _rAlmostFull;
+	rLenEQ0Hi <= #1 _rLenEQ0Hi;
+	rLenEQ0Lo <= #1 _rLenEQ0Lo;
+	rLenLE1Lo <= #1 _rLenLE1Lo;
+end
+
+always @ (*) begin
+	// Don't get to the full point in the output FIFO
+	_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);
+
+	// Track read history so we know when data is valid
+	_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
+
+	// Read until we get a (valid) event
+	_rRead = (!rState[1] & !wEventData & !rAlmostFull); // !S_TXPORTMON32_TXN
+
+	// Track detected events
+	_rEvent = wEventData;
+
+	// Save event data when valid
+	if (wEventData) begin
+		_rReadOffLast = (rReadCount ? EVT_DATA[C_DATA_WIDTH-1:0] : rReadOffLast);
+		_rReadLen = (!rReadCount ? EVT_DATA[C_DATA_WIDTH-1:0] : rReadLen);
+		_rReadCount = rReadCount + 1'd1;
+	end
+	else begin
+		_rReadOffLast = rReadOffLast;
+		_rReadLen = rReadLen;
+		_rReadCount = rReadCount;
+	end
+	
+	// If LEN == 0, we don't want to send any data to the output
+	_rLenEQ0Hi = (LEN[31:16] == 16'd0);
+	_rLenEQ0Lo = (LEN[15:0] == 16'd0);
+
+	// If LEN <= 1, we want to trigger the almost all received flag
+	_rLenLE1Lo = (LEN[15:0] <= 16'd1);
+	
+	// Count received non-event data
+	_rWordsRecvd = (ACK ? 0 : rWordsRecvd + wPayloadData);
+	_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + wPayloadData);
+	_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);
+end
+
+/*
+wire [35:0] wControl0;
+chipscope_icon_1 cs_icon(
+	.CONTROL0(wControl0)
+);
+
+chipscope_ila_t8_512 a0(
+	.CLK(CLK), 
+	.CONTROL(wControl0), 
+	.TRIG0({TXN, wPayloadData, wEventData, rState}),
+	.DATA({297'd0,
+			WR_COUNT, // 10
+			wPayloadData, // 1
+			EVT_DATA_RD_EN, // 1
+			RST, // 1
+			rTxErr, // 1
+			wEventData, // 1
+			rReadData, // 64
+			OFF, // 31
+			LEN, // 32
+			LAST, // 1
+			TXN, // 1
+			EVT_DATA_EMPTY, // 1
+			EVT_DATA, // 65
+			rState}) // 5
+);
+*/
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_port_monitor_64.v b/fpga/riffa_hdl/tx_port_monitor_64.v
new file mode 100644
index 0000000..46360c2
--- /dev/null
+++ b/fpga/riffa_hdl/tx_port_monitor_64.v
@@ -0,0 +1,250 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			tx_port_monitor_64.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Detects transaction open/close events from the stream
+// of data from the tx_port_channel_gate. Filters out events and passes data
+// onto the tx_port_buffer. 
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`define S_TXPORTMON64_NEXT	5'b0_0001
+`define S_TXPORTMON64_TXN	5'b0_0010
+`define S_TXPORTMON64_READ	5'b0_0100
+`define S_TXPORTMON64_END_0	5'b0_1000
+`define S_TXPORTMON64_END_1	5'b1_0000
+
+`timescale 1ns/1ns
+module tx_port_monitor_64 #(
+	parameter C_DATA_WIDTH = 9'd64,
+	parameter C_FIFO_DEPTH = 512,
+	// Local parameters
+	parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),
+	parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
+	parameter C_VALID_HIST = 1
+)
+(
+	input RST,
+	input CLK,
+
+	input [C_DATA_WIDTH:0] EVT_DATA,			// Event data from tx_port_channel_gate
+	input EVT_DATA_EMPTY,						// Event data FIFO is empty
+	output EVT_DATA_RD_EN,						// Event data FIFO read enable
+
+	output [C_DATA_WIDTH-1:0] WR_DATA,			// Output data
+	output WR_EN,								// Write enable for output data
+	input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT,	// Output FIFO count
+
+	output TXN,									// Transaction parameters are valid
+	input ACK,									// Transaction parameter read, continue
+	output LAST,								// Channel last write
+	output [31:0] LEN,							// Channel write length (in 32 bit words)
+	output [30:0] OFF,							// Channel write offset
+	output [31:0] WORDS_RECVD,					// Count of data words received in transaction
+	output DONE,								// Transaction is closed
+
+	input TX_ERR								// Transaction encountered an error
+);
+
+`include "functions.vh"
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg 	[4:0]				rState=`S_TXPORTMON64_NEXT, _rState=`S_TXPORTMON64_NEXT;
+reg 						rRead=0, _rRead=0;
+reg 	[C_VALID_HIST-1:0]	rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
+reg 						rEvent=0, _rEvent=0;
+reg 	[63:0]				rReadData=64'd0, _rReadData=64'd0;
+reg 	[31:0]				rWordsRecvd=0, _rWordsRecvd=0;
+reg 	[31:0]				rWordsRecvdAdv=0, _rWordsRecvdAdv=0;
+reg 						rAlmostAllRecvd=0, _rAlmostAllRecvd=0;
+reg 						rAlmostFull=0, _rAlmostFull=0;
+reg 						rLenEQ0Hi=0, _rLenEQ0Hi=0;
+reg 						rLenEQ0Lo=0, _rLenEQ0Lo=0;
+reg 						rLenLE2Lo=0, _rLenLE2Lo=0;
+reg							rTxErr=0, _rTxErr=0;
+
+
+wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
+wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[2]); // S_TXPORTMON64_READ
+wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE2Lo)) & wPayloadData);
+
+assign EVT_DATA_RD_EN = rRead;
+
+assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
+assign WR_EN = wPayloadData; // S_TXPORTMON64_READ
+
+assign TXN = rState[1]; // S_TXPORTMON64_TXN
+assign LAST = rReadData[0];
+assign OFF = rReadData[31:1];
+assign LEN = rReadData[63:32];
+assign WORDS_RECVD = rWordsRecvd;
+assign DONE = !rState[2]; // !S_TXPORTMON64_READ
+
+
+
+
+// Buffer the input signals that come from outside the tx_port.
+always @ (posedge CLK) begin
+	rTxErr <= #1 (RST ? 1'd0 : _rTxErr);
+end
+
+always @ (*) begin
+	_rTxErr = TX_ERR;
+end
+
+
+// Transaction monitoring FSM.
+always @ (posedge CLK) begin
+	rState <= #1 (RST ? `S_TXPORTMON64_NEXT : _rState);
+end
+
+always @ (*) begin
+	_rState = rState;
+	case (rState)
+
+	`S_TXPORTMON64_NEXT: begin // Read, wait for start of transaction event
+		if (rEvent)
+			_rState = `S_TXPORTMON64_TXN;
+	end
+
+	`S_TXPORTMON64_TXN: begin // Don't read, wait until transaction has been acknowledged
+		if (ACK)
+			_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON64_END_0 : `S_TXPORTMON64_READ);
+	end
+
+	`S_TXPORTMON64_READ: begin // Continue reading, wait for end of transaction event or all expected data
+		if (rEvent)
+			_rState = `S_TXPORTMON64_END_1;
+		else if (wAllWordsRecvd | rTxErr)
+			_rState = `S_TXPORTMON64_END_0;
+	end
+	
+	`S_TXPORTMON64_END_0: begin // Continue reading, wait for first end of transaction event
+		if (rEvent)
+			_rState = `S_TXPORTMON64_END_1;
+	end
+
+	`S_TXPORTMON64_END_1: begin // Continue reading, wait for second end of transaction event
+		if (rEvent)
+			_rState = `S_TXPORTMON64_NEXT;
+	end
+
+	default: begin
+		_rState = `S_TXPORTMON64_NEXT;
+	end
+
+	endcase	
+end
+
+
+// Manage reading from the FIFO and tracking amounts read.
+always @ (posedge CLK) begin
+	rRead <= #1 (RST ? 1'd0 : _rRead);
+	rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);
+	rEvent <= #1 (RST ? 1'd0 : _rEvent);
+	rReadData <= #1 _rReadData;
+	rWordsRecvd <= #1 _rWordsRecvd;
+	rWordsRecvdAdv <= #1 _rWordsRecvdAdv;
+	rAlmostAllRecvd <= #1 _rAlmostAllRecvd;
+	rAlmostFull <= #1 _rAlmostFull;
+	rLenEQ0Hi <= #1 _rLenEQ0Hi;
+	rLenEQ0Lo <= #1 _rLenEQ0Lo;
+	rLenLE2Lo <= #1 _rLenLE2Lo;
+end
+
+always @ (*) begin
+	// Don't get to the full point in the output FIFO
+	_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);
+
+	// Track read history so we know when data is valid
+	_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
+
+	// Read until we get a (valid) event
+	_rRead = (!rState[1] & !wEventData & !rAlmostFull); // !S_TXPORTMON64_TXN
+
+	// Track detected events
+	_rEvent = wEventData;
+
+	// Save event data when valid
+	if (wEventData)
+		_rReadData = EVT_DATA[C_DATA_WIDTH-1:0];
+	else
+		_rReadData = rReadData;
+	
+	// If LEN == 0, we don't want to send any data to the output
+	_rLenEQ0Hi = (LEN[31:16] == 16'd0);
+	_rLenEQ0Lo = (LEN[15:0] == 16'd0);
+
+	// If LEN <= 2, we want to trigger the almost all received flag
+	_rLenLE2Lo = (LEN[15:0] <= 16'd2);
+	
+	// Count received non-event data
+	_rWordsRecvd = (ACK ? 0 : rWordsRecvd + (wPayloadData<<1));
+	_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + (wPayloadData<<1));
+	_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);
+end
+
+/*
+wire [35:0] wControl0;
+chipscope_icon_1 cs_icon(
+	.CONTROL0(wControl0)
+);
+
+chipscope_ila_t8_512 a0(
+	.CLK(CLK), 
+	.CONTROL(wControl0), 
+	.TRIG0({TXN, wPayloadData, wEventData, rState}),
+	.DATA({297'd0,
+			WR_COUNT, // 10
+			wPayloadData, // 1
+			EVT_DATA_RD_EN, // 1
+			RST, // 1
+			rTxErr, // 1
+			wEventData, // 1
+			rReadData, // 64
+			OFF, // 31
+			LEN, // 32
+			LAST, // 1
+			TXN, // 1
+			EVT_DATA_EMPTY, // 1
+			EVT_DATA, // 65
+			rState}) // 5
+);
+*/
+
+endmodule
diff --git a/fpga/riffa_hdl/tx_port_writer.v b/fpga/riffa_hdl/tx_port_writer.v
new file mode 100644
index 0000000..a200ee2
--- /dev/null
+++ b/fpga/riffa_hdl/tx_port_writer.v
@@ -0,0 +1,510 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:			tx_port_writer.v
+// Version:				1.00.a
+// Verilog Standard:	Verilog-2001
+// Description:			Handles receiving new transaction events and data, and
+// making requests to tx engine. 
+//						for the RIFFA channel.
+// Author:				Matt Jacobsen
+// History:				@mattj: Version 2.0
+//-----------------------------------------------------------------------------
+`define S_TXPORTWR_MAIN_IDLE		8'b0000_0001
+`define S_TXPORTWR_MAIN_CHECK		8'b0000_0010
+`define S_TXPORTWR_MAIN_SIG_NEW		8'b0000_0100
+`define S_TXPORTWR_MAIN_NEW_ACK		8'b0000_1000
+`define S_TXPORTWR_MAIN_WRITE		8'b0001_0000
+`define S_TXPORTWR_MAIN_DONE		8'b0010_0000
+`define S_TXPORTWR_MAIN_SIG_DONE	8'b0100_0000
+`define S_TXPORTWR_MAIN_RESET		8'b1000_0000
+
+`define S_TXPORTWR_TX_IDLE			8'b0000_0001
+`define S_TXPORTWR_TX_BUF			8'b0000_0010
+`define S_TXPORTWR_TX_ADJ_0			8'b0000_0100
+`define S_TXPORTWR_TX_ADJ_1			8'b0000_1000
+`define S_TXPORTWR_TX_ADJ_2			8'b0001_0000
+`define S_TXPORTWR_TX_CHECK_DATA	8'b0010_0000
+`define S_TXPORTWR_TX_WRITE			8'b0100_0000
+`define S_TXPORTWR_TX_WRITE_REM		8'b1000_0000
+
+`timescale 1ns/1ns
+module tx_port_writer (
+	input CLK,
+	input RST,
+	input [2:0] CONFIG_MAX_PAYLOAD_SIZE,	// Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
+
+	output TXN,							// Write transaction notification
+	input TXN_ACK,						// Write transaction acknowledged
+	output [31:0] TXN_LEN,				// Write transaction length
+	output [31:0] TXN_OFF_LAST,			// Write transaction offset/last
+	output [31:0] TXN_DONE_LEN,			// Write transaction actual transfer length
+	output TXN_DONE,					// Write transaction done
+	output TXN_ERR,						// Write transaction encountered an error
+	input TXN_DONE_ACK,					// Write transaction actual transfer length read
+
+	input NEW_TXN,						// Transaction parameters are valid
+	output NEW_TXN_ACK,					// Transaction parameter read, continue
+	input NEW_TXN_LAST,					// Channel last write
+	input [31:0] NEW_TXN_LEN,			// Channel write length (in 32 bit words)
+	input [30:0] NEW_TXN_OFF,			// Channel write offset
+	input [31:0] NEW_TXN_WORDS_RECVD,	// Count of data words received in transaction
+	input NEW_TXN_DONE,					// Transaction is closed
+
+	input [63:0] SG_ELEM_ADDR,			// Scatter gather element address
+	input [31:0] SG_ELEM_LEN,			// Scatter gather element length (in words)
+	input SG_ELEM_RDY,					// Scatter gather element ready
+	input SG_ELEM_EMPTY,				// Scatter gather elements empty
+	output SG_ELEM_REN,					// Scatter gather element read enable
+	output SG_RST,						// Scatter gather data reset
+	input SG_ERR,						// Scatter gather read encountered an error
+	
+	output TX_REQ,						// Outgoing write request
+	input TX_REQ_ACK,					// Outgoing write request acknowledged
+	output [63:0] TX_ADDR,				// Outgoing write high address
+	output [9:0] TX_LEN,				// Outgoing write length (in 32 bit words)
+	output TX_LAST,						// Outgoing write is last request for transaction
+	input TX_SENT						// Outgoing write complete
+);
+
+`include "functions.vh"
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg		[7:0]						rMainState=`S_TXPORTWR_MAIN_IDLE, _rMainState=`S_TXPORTWR_MAIN_IDLE;
+reg		[31:0]						rOffLast=0, _rOffLast=0;
+reg									rWordsEQ0=0, _rWordsEQ0=0;
+reg									rStarted=0, _rStarted=0;
+reg		[31:0]						rDoneLen=0, _rDoneLen=0;
+reg									rSgErr=0, _rSgErr=0;
+reg									rTxErrd=0, _rTxErrd=0;
+reg									rTxnAck=0, _rTxnAck=0;
+
+(* syn_encoding = "user" *)
+(* fsm_encoding = "user" *)
+reg		[7:0]						rTxState=`S_TXPORTWR_TX_IDLE, _rTxState=`S_TXPORTWR_TX_IDLE;
+reg		[31:0]						rSentWords=0, _rSentWords=0;
+reg		[31:0]						rWords=0, _rWords=0;
+reg		[31:0]						rBufWords=0, _rBufWords=0;
+reg		[31:0]						rBufWordsInit=0, _rBufWordsInit=0;
+reg									rLargeBuf=0, _rLargeBuf=0;
+reg		[63:0]						rAddr=64'd0, _rAddr=64'd0;
+reg		[2:0]						rCarry=0, _rCarry=0;
+reg									rValsPropagated=0, _rValsPropagated=0;
+reg		[5:0]						rValsProp=0, _rValsProp=0;
+reg									rCopyBufWords=0, _rCopyBufWords=0;
+reg									rUseInit=0, _rUseInit=0;
+reg		[10:0]						rPageRem=0, _rPageRem=0;
+reg									rPageSpill=0, _rPageSpill=0;
+reg									rPageSpillInit=0, _rPageSpillInit=0;
+reg		[10:0]						rPreLen=0, _rPreLen=0;
+reg		[2:0]						rMaxPayloadSize=0, _rMaxPayloadSize=0;
+reg		[2:0]						rMaxPayloadShift=0, _rMaxPayloadShift=0;
+reg		[9:0]						rMaxPayload=0, _rMaxPayload=0;
+reg									rPayloadSpill=0, _rPayloadSpill=0;
+reg									rMaxLen=1, _rMaxLen=1;
+reg		[9:0]						rLen=0, _rLen=0;
+reg		[31:0]						rSendingWords=0, _rSendingWords=0;
+reg									rAvail=0, _rAvail=0;
+reg		[1:0]						rTxnDone=0, _rTxnDone=0;
+reg		[9:0]						rLastLen=0, _rLastLen=0;
+reg									rLastLenEQ0=0, _rLastLenEQ0=0;
+reg									rLenEQWords=0, _rLenEQWords=0;
+reg									rLenEQBufWords=0, _rLenEQBufWords=0;
+
+reg									rNotRequesting=1, _rNotRequesting=1;
+reg		[63:0]						rReqAddr=64'd0, _rReqAddr=64'd0;
+reg		[9:0]						rReqLen=0, _rReqLen=0;
+reg									rReqLast=0, _rReqLast=0;
+reg									rTxReqAck=0, _rTxReqAck=0;
+
+reg									rDone=0, _rDone=0;
+reg		[9:0]						rAckCount=0, _rAckCount=0;
+reg									rTxSent=0, _rTxSent=0;
+reg									rLastDoneRead=1, _rLastDoneRead=1;
+reg									rTxnDoneAck=0, _rTxnDoneAck=0;
+
+reg									rReqPartialDone=0, _rReqPartialDone=0;
+reg									rPartialDone=0, _rPartialDone=0;
+
+
+assign NEW_TXN_ACK = rMainState[1]; // S_TXPORTWR_MAIN_CHECK
+
+assign TXN = rMainState[2]; // S_TXPORTWR_MAIN_SIG_NEW
+assign TXN_DONE = (rMainState[6] | rPartialDone); // S_TXPORTWR_MAIN_SIG_DONE
+assign TXN_LEN = rWords;
+assign TXN_OFF_LAST = rOffLast;
+assign TXN_DONE_LEN = rDoneLen;
+assign TXN_ERR = rTxErrd;
+
+assign SG_ELEM_REN = rTxState[2]; // S_TXPORTWR_TX_ADJ_0
+assign SG_RST = rMainState[3]; // S_TXPORTWR_MAIN_NEW_ACK
+
+assign TX_REQ = !rNotRequesting;
+assign TX_ADDR = rReqAddr; 
+assign TX_LEN = rReqLen;
+assign TX_LAST = rReqLast;
+
+
+// Buffer the input signals that come from outside the tx_port.
+always @ (posedge CLK) begin
+	rTxnAck <= #1 (RST ? 1'd0 : _rTxnAck);
+	rTxnDoneAck <= #1 (RST ? 1'd0 : _rTxnDoneAck);
+	rSgErr <= #1 (RST ? 1'd0 : _rSgErr);
+	rTxReqAck <= #1 (RST ? 1'd0 : _rTxReqAck);
+	rTxSent <= #1 (RST ? 1'd0 : _rTxSent);
+end
+
+always @ (*) begin
+	_rTxnAck = TXN_ACK;
+	_rTxnDoneAck = TXN_DONE_ACK;
+	_rSgErr = SG_ERR;
+	_rTxReqAck = TX_REQ_ACK;
+	_rTxSent = TX_SENT;
+end
+	
+
+// Wait for a NEW_TXN request. Then request transfers until all the data is sent
+// or until the specified length is reached. Then signal TXN_DONE.
+always @ (posedge CLK) begin
+	rMainState <= #1 (RST ? `S_TXPORTWR_MAIN_IDLE : _rMainState);
+	rOffLast <= #1 _rOffLast;
+	rWordsEQ0 <= #1 _rWordsEQ0;
+	rStarted <= #1 _rStarted;
+	rDoneLen <= #1 (RST ? 0 : _rDoneLen);
+	rTxErrd <= #1 (RST ? 1'd0 : _rTxErrd);
+end
+
+always @ (*) begin
+	_rMainState = rMainState;
+	_rOffLast = rOffLast;
+	_rWordsEQ0 = rWordsEQ0;
+	_rStarted = rStarted;
+	_rDoneLen = rDoneLen;
+	_rTxErrd = rTxErrd;
+	case (rMainState)
+
+	`S_TXPORTWR_MAIN_IDLE: begin // Wait for channel write request
+		_rStarted = 0;
+		_rWordsEQ0 = (NEW_TXN_LEN == 0);
+		_rOffLast = {NEW_TXN_OFF, NEW_TXN_LAST};
+		if (NEW_TXN)
+			_rMainState = `S_TXPORTWR_MAIN_CHECK;
+	end
+
+	`S_TXPORTWR_MAIN_CHECK: begin // Continue with transaction?
+		if (rOffLast[0] | !rWordsEQ0)
+			_rMainState = `S_TXPORTWR_MAIN_SIG_NEW;
+		else
+			_rMainState = `S_TXPORTWR_MAIN_RESET;
+	end
+
+	`S_TXPORTWR_MAIN_SIG_NEW: begin // Signal new write
+		_rMainState = `S_TXPORTWR_MAIN_NEW_ACK;
+	end
+
+	`S_TXPORTWR_MAIN_NEW_ACK: begin // Wait for acknowledgement
+		if (rTxnAck) // ACK'd on PC read of TXN length
+			_rMainState = (rWordsEQ0 ? `S_TXPORTWR_MAIN_SIG_DONE : `S_TXPORTWR_MAIN_WRITE);
+	end
+
+	`S_TXPORTWR_MAIN_WRITE: begin // Start writing and wait for all writes to complete
+		_rStarted = (rStarted | rTxState[1]); // S_TXPORTWR_TX_BUF
+		_rTxErrd = (rTxErrd | rSgErr);
+		if (rTxState[0] & rStarted) // S_TXPORTWR_TX_IDLE
+			_rMainState = `S_TXPORTWR_MAIN_DONE;
+	end
+
+	`S_TXPORTWR_MAIN_DONE: begin // Wait for the last transaction to complete
+		if (rDone & rLastDoneRead) begin
+			_rDoneLen = rSentWords;
+			_rMainState = `S_TXPORTWR_MAIN_SIG_DONE;
+		end
+	end
+
+	`S_TXPORTWR_MAIN_SIG_DONE: begin // Signal the done port
+		_rTxErrd = 0;
+		_rMainState = `S_TXPORTWR_MAIN_RESET;
+	end
+
+	`S_TXPORTWR_MAIN_RESET: begin // Wait for the channel tx to drop
+		if (NEW_TXN_DONE)
+			_rMainState = `S_TXPORTWR_MAIN_IDLE;
+	end
+	
+	default: begin
+		_rMainState = `S_TXPORTWR_MAIN_IDLE;
+	end
+	
+	endcase
+end
+
+
+// Manage sending TX requests to the TX engine. Transfers will be limited
+// by each scatter gather buffer's size, max payload size, and must not
+// cross a (4KB) page boundary. The request is only made if there is sufficient
+// data already written to the buffer.
+wire [9:0] wLastLen = (NEW_TXN_WORDS_RECVD - rSentWords);
+wire [9:0] wAddrLoInv = ~rAddr[11:2];
+wire [10:0] wPageRem = (wAddrLoInv + 1'd1);	
+always @ (posedge CLK) begin
+	rTxState <= #1 (RST | rSgErr ? `S_TXPORTWR_TX_IDLE : _rTxState);
+	rSentWords <= #1 (rMainState[0] ? 0 : _rSentWords);
+	rWords <= #1 _rWords;
+	rBufWords <= #1 _rBufWords;
+	rBufWordsInit <= #1 _rBufWordsInit;
+	rAddr <= #1 _rAddr;
+	rCarry <= #1 _rCarry;
+	rValsPropagated <= #1 _rValsPropagated;
+	rValsProp <= #1 _rValsProp;
+	rLargeBuf <= #1 _rLargeBuf;
+	rPageRem <= #1 _rPageRem;
+	rPageSpill <= #1 _rPageSpill;
+	rPageSpillInit <= #1 _rPageSpillInit;
+	rCopyBufWords <= #1 _rCopyBufWords;
+	rUseInit <= #1 _rUseInit;
+	rPreLen <= #1 _rPreLen;
+	rMaxPayloadSize <= #1 _rMaxPayloadSize;
+	rMaxPayloadShift <= #1 _rMaxPayloadShift;
+	rMaxPayload <= #1 _rMaxPayload;
+	rPayloadSpill <= #1 _rPayloadSpill;
+	rMaxLen <= #1 (RST ? 1'd1 : _rMaxLen);
+	rLen <= #1 _rLen;
+	rSendingWords <= #1 _rSendingWords;
+	rAvail <= #1 _rAvail;
+	rTxnDone <= #1 _rTxnDone;
+	rLastLen <= #1 _rLastLen;
+	rLastLenEQ0 <= #1 _rLastLenEQ0;
+	rLenEQWords <= #1 _rLenEQWords;
+	rLenEQBufWords <= #1 _rLenEQBufWords;
+end
+
+always @ (*) begin
+	_rTxState = rTxState;
+	_rCopyBufWords = rCopyBufWords;
+	_rUseInit = rUseInit;
+	
+	_rValsProp = ((rValsProp<<1) | rTxState[3]); // S_TXPORTWR_TX_ADJ_1
+	_rValsPropagated = (rValsProp == 6'd0);
+	_rLargeBuf = (SG_ELEM_LEN > rWords);
+	{_rCarry[0], _rAddr[15:0]} = (rTxState[1] ? SG_ELEM_ADDR[15:0] : (rAddr[15:0] + ({12{rTxState[6]}} & {rLen, 2'd0}))); // S_TXPORTWR_TX_WRITE
+	{_rCarry[1], _rAddr[31:16]} = (rTxState[1] ? SG_ELEM_ADDR[31:16] : (rAddr[31:16] + rCarry[0]));
+	{_rCarry[2], _rAddr[47:32]} = (rTxState[1] ? SG_ELEM_ADDR[47:32] : (rAddr[47:32] + rCarry[1]));
+				 _rAddr[63:48] = (rTxState[1] ? SG_ELEM_ADDR[63:48] : (rAddr[63:48] + rCarry[2]));
+	_rSentWords = (rTxState[7] ? NEW_TXN_WORDS_RECVD : rSentWords) + ({10{rTxState[6]}} & rLen); // S_TXPORTWR_TX_WRITE
+	_rWords = (NEW_TXN_ACK ? NEW_TXN_LEN : (rWords - ({10{rTxState[6]}} & rLen))); // S_TXPORTWR_TX_WRITE
+	_rBufWordsInit = (rLargeBuf ? rWords : SG_ELEM_LEN); 
+	_rBufWords = (rCopyBufWords ? rBufWordsInit : rBufWords) - ({10{rTxState[6]}} & rLen); // S_TXPORTWR_TX_WRITE
+	_rPageRem = wPageRem;	
+	_rPageSpillInit = (rBufWordsInit > wPageRem);	
+	_rPageSpill = (rBufWords > wPageRem);	
+	_rPreLen = ((rPageSpillInit & rUseInit) | (rPageSpill & !rUseInit) ? rPageRem : rBufWords[10:0]);
+	_rMaxPayloadSize = CONFIG_MAX_PAYLOAD_SIZE;
+	_rMaxPayloadShift = (rMaxPayloadSize > 3'd4 ? 3'd4 : rMaxPayloadSize);
+	_rMaxPayload = (6'd32<<rMaxPayloadShift);
+	_rPayloadSpill = (rPreLen > rMaxPayload);
+	_rMaxLen = ((rMaxLen & !rValsProp[1]) | rTxState[6]); // S_TXPORTWR_TX_WRITE
+	_rLen = (rPayloadSpill | rMaxLen ? rMaxPayload : rPreLen[9:0]);
+	_rSendingWords = rSentWords + rLen;
+	_rAvail = (NEW_TXN_WORDS_RECVD >= rSendingWords);
+	_rTxnDone = ((rTxnDone<<1) | NEW_TXN_DONE);
+	_rLastLen = wLastLen;
+	_rLastLenEQ0 = (rLastLen == 10'd0);
+	_rLenEQWords = (rLen == rWords);
+	_rLenEQBufWords = (rLen == rBufWords);
+	
+	case (rTxState)
+
+	`S_TXPORTWR_TX_IDLE: begin // Wait for channel write request
+		if (rMainState[4] & !rStarted) // S_TXPORTWR_MAIN_WRITE
+			_rTxState = `S_TXPORTWR_TX_BUF;
+	end
+
+	`S_TXPORTWR_TX_BUF: begin // Wait for buffer length and address
+		if (SG_ELEM_RDY)
+			_rTxState = `S_TXPORTWR_TX_ADJ_0;
+	end
+
+	`S_TXPORTWR_TX_ADJ_0: begin // Fix for large buffer
+		_rCopyBufWords = 1;
+		_rTxState = `S_TXPORTWR_TX_ADJ_1;
+	end
+
+	`S_TXPORTWR_TX_ADJ_1: begin // Check for page boundary crossing
+		_rCopyBufWords = 0;
+		_rUseInit = rCopyBufWords;
+		_rTxState = `S_TXPORTWR_TX_ADJ_2;
+	end
+
+	`S_TXPORTWR_TX_ADJ_2: begin // Wait for values to propagate
+		// Fix for page boundary crossing
+		// Check for max payload
+		// Fix for max payload
+		_rUseInit = 0;
+		if (rValsProp[2])
+			_rTxState = `S_TXPORTWR_TX_CHECK_DATA;
+	end
+
+	`S_TXPORTWR_TX_CHECK_DATA: begin // Wait for available data
+		if (rNotRequesting) begin
+			if (rAvail)
+				_rTxState = `S_TXPORTWR_TX_WRITE;
+			else if (rValsPropagated & rTxnDone[1])
+				_rTxState = (rLastLenEQ0 ? `S_TXPORTWR_TX_IDLE : `S_TXPORTWR_TX_WRITE_REM);
+		end
+	end
+
+	`S_TXPORTWR_TX_WRITE: begin // Send len and repeat or finish?
+		if (rLenEQWords)
+			_rTxState = `S_TXPORTWR_TX_IDLE;
+		else if (rLenEQBufWords)
+			_rTxState = `S_TXPORTWR_TX_BUF;
+		else
+			_rTxState = `S_TXPORTWR_TX_ADJ_1;
+	end
+
+	`S_TXPORTWR_TX_WRITE_REM: begin // Send remaining data and finish
+		_rTxState = `S_TXPORTWR_TX_IDLE;
+	end
+	
+	default: begin
+		_rTxState = `S_TXPORTWR_TX_IDLE;
+	end
+	
+	endcase
+end
+
+// Request TX transfers separately so that the TX FSM can continue calculating
+// the next set of request parameters without having to wait for the TX_REQ_ACK.
+always @ (posedge CLK) begin
+	rAckCount <= #1 (RST ? 10'd0 : _rAckCount);
+	rNotRequesting <= #1 (RST ? 1'd1 : _rNotRequesting);
+	rReqAddr <= #1 _rReqAddr;
+	rReqLen <= #1 _rReqLen;
+	rReqLast <= #1 _rReqLast;
+	rDone <= #1 _rDone;
+	rLastDoneRead <= #1 (RST ? 1'd1 : _rLastDoneRead);
+end
+
+always @ (*) begin
+	// Start signaling when the TX FSM is ready.
+	if (rTxState[6] | rTxState[7]) // S_TXPORTWR_TX_WRITE
+		_rNotRequesting = 0;
+	else
+		_rNotRequesting = (rNotRequesting | rTxReqAck);
+
+	// Pass off the rAddr & rLen when ready and wait for TX_REQ_ACK.
+	if (rTxState[6]) begin // S_TXPORTWR_TX_WRITE
+		_rReqAddr = rAddr;
+		_rReqLen = rLen;
+		_rReqLast = rLenEQWords;
+	end
+	else if (rTxState[7]) begin // S_TXPORTWR_TX_WRITE_REM
+		_rReqAddr = rAddr;
+		_rReqLen = rLastLen;
+		_rReqLast = 1;
+	end
+	else begin
+		_rReqAddr = rReqAddr;
+		_rReqLen = rReqLen;
+		_rReqLast = rReqLast;
+	end
+
+	// Track TX_REQ_ACK and TX_SENT to determine when the transaction is over.
+	_rDone = (rAckCount == 10'd0);
+	if (rMainState[0]) // S_TXPORTWR_MAIN_IDLE
+		_rAckCount = 0;
+	else
+		_rAckCount = rAckCount + rTxState[6] + rTxState[7] - rTxSent; // S_TXPORTWR_TX_WRITE, S_TXPORTWR_TX_WRITE_REM
+		
+	// Track when the user reads the actual transfer amount.
+	_rLastDoneRead = (rMainState[6] ? 1'd0 : (rLastDoneRead | rTxnDoneAck)); // S_TXPORTWR_MAIN_SIG_DONE
+end
+
+
+// Facilitate sending a TXN_DONE when we receive a TXN_ACK after the transaction
+// has begun sending. This will happen when the workstation detects that it has 
+// sent/used all its currently mapped scatter gather elements, but it's not enough 
+// to complete the transaction. The TXN_DONE will let the workstation know it can
+// release the current scatter gather mappings and allocate new ones.
+always @ (posedge CLK) begin
+	rPartialDone <= #1 _rPartialDone;
+	rReqPartialDone <= #1 (RST ? 1'd0 : _rReqPartialDone);
+end
+
+always @ (*) begin
+	// Signal TXN_DONE after we've recieved the (seemingly superfluous) TXN_ACK, 
+	// we have no outstanding transfer requests, we're not currently requesting a
+	// transfer, and there are no more scatter gather elements.
+	_rPartialDone = (rReqPartialDone & rDone & rNotRequesting & SG_ELEM_EMPTY & rTxState[1]); // S_TXPORTWR_TX_BUF
+	
+	// Keep track of (seemingly superfluous) TXN_ACK requests.
+	if ((rReqPartialDone & rDone & rNotRequesting & SG_ELEM_EMPTY & rTxState[1]) | rMainState[0]) // S_TXPORTWR_MAIN_IDLE
+		_rReqPartialDone = 0;
+	else
+		_rReqPartialDone = (rReqPartialDone | (rTxnAck & !rMainState[3])); // !S_TXPORTWR_MAIN_NEW_ACK
+end
+
+
+
+/*
+wire [35:0] wControl0;
+chipscope_icon_1 cs_icon(
+	.CONTROL0(wControl0)
+);
+
+chipscope_ila_t8_512 a0(
+	.CLK(CLK), 
+	.CONTROL(wControl0), 
+	.TRIG0({rTxState[6] | rTxState[7] | rTxSent, rAckCount[6:0]}),
+	.DATA({280'd0,
+			NEW_TXN_WORDS_RECVD, // 32
+			rSendingWords, // 32
+			rAvail, // 1
+			rNotRequesting, // 1
+			NEW_TXN_LAST, // 1
+			NEW_TXN_LEN, // 32
+			NEW_TXN_OFF, // 31
+			NEW_TXN, // 1
+			rAckCount, // 10
+			rLastDoneRead, // 1
+			rWords, // 32
+			rBufWords, // 32
+			rLen, // 10
+			rTxState, // 8
+			rMainState}) // 8
+);
+*/
+endmodule
diff --git a/fpga/riffa_hdl/txc_engine_classic.v b/fpga/riffa_hdl/txc_engine_classic.v
new file mode 100644
index 0000000..72fa8a5
--- /dev/null
+++ b/fpga/riffa_hdl/txc_engine_classic.v
@@ -0,0 +1,347 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            txc_engine_classic.v
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description: The TXC Engine takes unformatted completions, formats
+// these packets into "TLP's" or Transaction Layer Packets. These
+// packets must meet max-request, max-payload, and payload termination
+// requirements (see Read Completion Boundary). The TXC Engine does not
+// check these requirements during operation, but may do so during
+// simulation.
+// This file also contains the txc_formatter module, which formats
+// completion headers. 
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "trellis.vh" // Defines the user-facing signal widths.
+`include "tlp.vh" // Defines the endpoint-facing field widths in a TLP
+module txc_engine_classic
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 0,
+      parameter C_MAX_PAYLOAD_DWORDS = 64,
+      parameter C_DEPTH_PACKETS = 10,
+      parameter C_VENDOR = "ALTERA"
+      )
+    (
+     // Interface: Clocks
+     input                                    CLK,
+
+     // Interface: Resets
+     input                                    RST_IN,
+
+     // Interface: Configuration
+     input [`SIG_CPLID_W-1:0]                 CONFIG_COMPLETER_ID,
+
+     // Interface: TXC Classic
+     input                                    TXC_TLP_READY,
+     output [C_PCI_DATA_WIDTH-1:0]            TXC_TLP,
+     output                                   TXC_TLP_VALID,
+     output                                   TXC_TLP_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_START_OFFSET,
+     output                                   TXC_TLP_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_END_OFFSET,
+
+     // Interface: TXC Engine
+     input                                    TXC_DATA_VALID,
+     input [C_PCI_DATA_WIDTH-1:0]             TXC_DATA,
+     input                                    TXC_DATA_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXC_DATA_START_OFFSET,
+     input                                    TXC_DATA_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXC_DATA_END_OFFSET,
+     output                                   TXC_DATA_READY,
+
+     input                                    TXC_META_VALID,
+     input [`SIG_FBE_W-1:0]                   TXC_META_FDWBE,
+     input [`SIG_LBE_W-1:0]                   TXC_META_LDWBE,
+     input [`SIG_LOWADDR_W-1:0]               TXC_META_ADDR,
+     input [`SIG_TYPE_W-1:0]                  TXC_META_TYPE,
+     input [`SIG_LEN_W-1:0]                   TXC_META_LENGTH,
+     input [`SIG_BYTECNT_W-1:0]                  TXC_META_BYTE_COUNT,
+     input [`SIG_TAG_W-1:0]                   TXC_META_TAG,
+     input [`SIG_REQID_W-1:0]                 TXC_META_REQUESTER_ID,
+     input [`SIG_TC_W-1:0]                    TXC_META_TC,
+     input [`SIG_ATTR_W-1:0]                  TXC_META_ATTR,
+     input                                    TXC_META_EP,
+     output                                   TXC_META_READY);
+
+    localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
+    localparam C_MAX_HDR_WIDTH = `TLP_MAXHDR_W;
+    localparam C_MAX_ALIGN_WIDTH = (C_VENDOR == "ALTERA") ? 32: 
+                                   (C_VENDOR == "XILINX") ? 0  : 
+                                   0;
+    localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
+    localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
+    localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
+    
+    /*AUTOWIRE*/
+    /*AUTOINPUT*/
+    ///*AUTOOUTPUT*/
+
+    wire                                      wTxHdrReady;
+    wire                                      wTxHdrValid;
+    wire [C_MAX_HDR_WIDTH-1:0]                wTxHdr;
+    wire [`SIG_TYPE_W-1:0]                    wTxType;
+    wire [`SIG_NONPAY_W-1:0]                  wTxHdrNonpayLen;
+    wire [`SIG_PACKETLEN_W-1:0]               wTxHdrPacketLen;
+    wire [`SIG_LEN_W-1:0]                     wTxHdrPayloadLen; 
+    wire                                      wTxHdrNopayload;
+
+    txc_formatter_classic
+        #(
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_FORMATTER_OUTPUT),
+          .C_PIPELINE_INPUT             (C_PIPELINE_FORMATTER_INPUT),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_HDR_WIDTH              (C_MAX_HDR_WIDTH),
+          .C_MAX_ALIGN_WIDTH            (C_MAX_ALIGN_WIDTH),
+          .C_VENDOR                     (C_VENDOR))
+    txc_formatter_inst
+        (
+         // Outputs
+         .TX_HDR_VALID                  (wTxHdrValid),
+         .TX_HDR                        (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
+         .TX_HDR_NOPAYLOAD              (wTxHdrNopayload),
+         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
+         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
+         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
+         // Inputs
+         .TX_HDR_READY                  (wTxHdrReady),
+         /*AUTOINST*/
+         // Outputs
+         .TXC_META_READY                (TXC_META_READY),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .CONFIG_COMPLETER_ID           (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
+         .TXC_META_VALID                (TXC_META_VALID),
+         .TXC_META_FDWBE                (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_LENGTH               (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (TXC_META_TAG[`SIG_TAG_W-1:0]),
+         .TXC_META_TYPE                 (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
+         .TXC_META_REQUESTER_ID         (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (TXC_META_TC[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (TXC_META_EP));
+
+    tx_engine
+        #(
+          .C_DATA_WIDTH                 (C_PCI_DATA_WIDTH),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_FORMATTER_DELAY            (C_FORMATTER_DELAY),
+          .C_MAX_HDR_WIDTH              (C_MAX_HDR_WIDTH),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_DWORDS),
+          .C_VENDOR                     (C_VENDOR))
+    txc_engine_inst
+        (
+         // Outputs
+         .TX_HDR_READY                  (wTxHdrReady),
+         .TX_DATA_READY                 (TXC_DATA_READY),
+         .TX_PKT                        (TXC_TLP[C_DATA_WIDTH-1:0]),
+         .TX_PKT_START_FLAG             (TXC_TLP_START_FLAG),
+         .TX_PKT_START_OFFSET           (TXC_TLP_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_PKT_END_FLAG               (TXC_TLP_END_FLAG),
+         .TX_PKT_END_OFFSET             (TXC_TLP_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_PKT_VALID                  (TXC_TLP_VALID),
+         // Inputs
+         .TX_HDR_VALID                  (wTxHdrValid),
+         .TX_HDR                        (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
+         .TX_HDR_NOPAYLOAD              (wTxHdrNopayload),
+         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
+         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
+         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
+         .TX_DATA_VALID                 (TXC_DATA_VALID),
+         .TX_DATA                       (TXC_DATA[C_DATA_WIDTH-1:0]),
+         .TX_DATA_START_FLAG            (TXC_DATA_START_FLAG),
+         .TX_DATA_START_OFFSET          (TXC_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_DATA_END_FLAG              (TXC_DATA_END_FLAG),
+         .TX_DATA_END_OFFSET            (TXC_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_PKT_READY                  (TXC_TLP_READY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+endmodule
+
+module txc_formatter_classic
+    #(
+      parameter C_PCI_DATA_WIDTH = 10'd128,
+      parameter C_MAX_HDR_WIDTH = `TLP_MAXHDR_W,
+      parameter C_MAX_ALIGN_WIDTH = 32,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 1,
+      parameter C_VENDOR = "ALTERA"
+      )
+    (
+     // Interface: Clocks
+     input                         CLK,
+
+     // Interface: Resets
+     input                         RST_IN,
+
+     // Interface: Configuration
+     input [`SIG_CPLID_W-1:0]      CONFIG_COMPLETER_ID,
+
+     // Interface: TXC
+     input                         TXC_META_VALID,
+     input [`SIG_FBE_W-1:0]        TXC_META_FDWBE,
+     input [`SIG_LBE_W-1:0]        TXC_META_LDWBE,
+     input [`SIG_LOWADDR_W-1:0]    TXC_META_ADDR,
+     input [`SIG_LEN_W-1:0]        TXC_META_LENGTH,
+     input [`SIG_BYTECNT_W-1:0]       TXC_META_BYTE_COUNT,
+     input [`SIG_TAG_W-1:0]        TXC_META_TAG,
+     input [`SIG_TYPE_W-1:0]       TXC_META_TYPE,
+     input [`SIG_REQID_W-1:0]      TXC_META_REQUESTER_ID,
+     input [`SIG_TC_W-1:0]         TXC_META_TC,
+     input [`SIG_ATTR_W-1:0]       TXC_META_ATTR,
+     input                         TXC_META_EP,
+     output                        TXC_META_READY,
+
+     // Interface: TX HDR
+     output                        TX_HDR_VALID,
+     output [C_MAX_HDR_WIDTH-1:0]  TX_HDR,
+     output [`SIG_LEN_W-1:0]       TX_HDR_PAYLOAD_LEN,
+     output [`SIG_NONPAY_W-1:0]    TX_HDR_NONPAY_LEN,
+     output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
+     output                        TX_HDR_NOPAYLOAD,
+     input                         TX_HDR_READY
+     );
+
+    wire [C_MAX_HDR_WIDTH-1:0]     wCplHdr;
+
+
+    wire                           wTxHdrReady;
+    wire                           wTxHdrValid;
+    wire [C_MAX_HDR_WIDTH-1:0]     wTxHdr;
+    wire [`SIG_TYPE_W-1:0]         wTxType;
+    wire [`SIG_NONPAY_W-1:0]       wTxHdrNonpayLen;
+    wire [`SIG_PACKETLEN_W-1:0]    wTxHdrPacketLen;
+    wire [`SIG_LEN_W-1:0]          wTxHdrPayloadLen; 
+    wire                           wTxHdrNopayload;
+
+    wire [`TLP_CPLADDR_W-1:0]      wTxLoAddr;
+
+
+    // Reserved Fields
+    assign wCplHdr[`TLP_RSVD0_R] = `TLP_RSVD0_V;
+    assign wCplHdr[`TLP_ADDRTYPE_R] = `TLP_ADDRTYPE_W'b0;
+    assign wCplHdr[`TLP_TH_R] = `TLP_TH_W'b0;
+    assign wCplHdr[`TLP_RSVD1_R] = `TLP_RSVD1_V;
+    assign wCplHdr[`TLP_RSVD2_R] = `TLP_RSVD2_V;
+    assign wCplHdr[`TLP_CPLBCM_R] = `TLP_CPLBCM_W'b0;
+    assign wCplHdr[`TLP_CPLRSVD0_R] = `TLP_CPLRSVD0_W'b0;
+    assign wCplHdr[127:96] = 32'b0;
+
+    // Generic Header Fields
+    assign wCplHdr[`TLP_LEN_R] = TXC_META_LENGTH;
+    assign wCplHdr[`TLP_EP_R] = TXC_META_EP;
+    assign wCplHdr[`TLP_TD_R] = `TLP_NODIGEST_V;
+    assign wCplHdr[`TLP_ATTR0_R] = TXC_META_ATTR[1:0];
+    assign wCplHdr[`TLP_ATTR1_R] = TXC_META_ATTR[2];
+    assign {wCplHdr[`TLP_FMT_R], wCplHdr[`TLP_TYPE_R]} = trellis_to_tlp_type(TXC_META_TYPE,0);
+    assign wCplHdr[`TLP_TC_R] = TXC_META_TC;
+
+    // Completion Specific Fields
+    assign wCplHdr[`TLP_CPLBYTECNT_R] = TXC_META_BYTE_COUNT;
+    assign wCplHdr[`TLP_CPLSTAT_R] = 0;
+    assign wCplHdr[`TLP_CPLCPLID_R] = CONFIG_COMPLETER_ID;
+    assign wCplHdr[`TLP_CPLADDR_R] = TXC_META_ADDR;
+    assign wCplHdr[`TLP_CPLTAG_R] = TXC_META_TAG;
+    assign wCplHdr[`TLP_CPLREQID_R] = TXC_META_REQUESTER_ID;
+
+    // Metadata, to the aligner
+    assign wTxLoAddr = wTxHdr[`TLP_CPLADDR_R];
+    assign wTxHdrNopayload = ~wTxHdr[`TLP_PAYBIT_I];
+    assign wTxHdrNonpayLen = 3 + ((C_VENDOR == "ALTERA")? {3'b0,(~wTxLoAddr[2] & ~wTxHdrNopayload)} : 4'b0);
+    assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`TLP_LEN_R];
+    assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;    
+
+    pipeline
+        #(// Parameters
+          .C_DEPTH                         (C_PIPELINE_INPUT?1:0),
+          .C_WIDTH                         (C_MAX_HDR_WIDTH),
+          .C_USE_MEMORY                    (0)
+          /*AUTOINSTPARAM*/)
+    input_inst
+        (// Outputs
+         .WR_DATA_READY                  (TXC_META_READY),
+         .RD_DATA                        (wTxHdr),
+         .RD_DATA_VALID                  (wTxHdrValid),
+         // Inputs
+         .WR_DATA                        (wCplHdr),
+         .WR_DATA_VALID                  (TXC_META_VALID),
+         .RD_DATA_READY                  (wTxHdrReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                         (C_PIPELINE_OUTPUT?1:0),
+          .C_WIDTH                         (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
+          .C_USE_MEMORY                    (0)
+          /*AUTOINSTPARAM*/)
+    output_inst
+        (
+         // Outputs
+         .WR_DATA_READY                  (wTxHdrReady),
+         .RD_DATA                        ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
+         .RD_DATA_VALID                  (TX_HDR_VALID),
+         // Inputs
+         .WR_DATA                        ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
+         .WR_DATA_VALID                  (wTxHdrValid),
+         .RD_DATA_READY                  (TX_HDR_READY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../common/" "../../common/")
+// End:
+
diff --git a/fpga/riffa_hdl/txc_engine_ultrascale.v b/fpga/riffa_hdl/txc_engine_ultrascale.v
new file mode 100644
index 0000000..6954863
--- /dev/null
+++ b/fpga/riffa_hdl/txc_engine_ultrascale.v
@@ -0,0 +1,496 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            txc_engine_ultrascale.v
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The TXC Engine takes unformatted completions, formats
+// these packets into AXI-style packets. These packets must meet max-request,
+// max-payload, and payload termination requirements (see Read Completion
+// Boundary). The TXC Engine does not check these requirements during operation,
+// but may do so during simulation.
+// 
+// This Engine is capable of operating at "line rate".
+// 
+// Author: Dustin Richmond (@darichmond) 
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "ultrascale.vh"
+module txc_engine_ultrascale
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 1,
+      parameter C_DEPTH_PACKETS = 10,
+      parameter C_MAX_PAYLOAD_DWORDS = 256
+      )
+    (
+     // Interface: Clocks
+     input                                   CLK,
+
+     // Interface: Resets
+     input                                   RST_IN,
+
+     // Interface: Configuration
+     input [`SIG_CPLID_W-1:0]                CONFIG_COMPLETER_ID,
+
+     // Interface: CC
+     input                                   S_AXIS_CC_TREADY,
+     output                                  S_AXIS_CC_TVALID,
+     output                                  S_AXIS_CC_TLAST,
+     output [C_PCI_DATA_WIDTH-1:0]           S_AXIS_CC_TDATA,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]      S_AXIS_CC_TKEEP,
+     output [`SIG_CC_TUSER_W-1:0]            S_AXIS_CC_TUSER,
+
+     // Interface: TXC Engine
+     input                                   TXC_DATA_VALID,
+     input [C_PCI_DATA_WIDTH-1:0]            TXC_DATA,
+     input                                   TXC_DATA_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
+     input                                   TXC_DATA_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
+     output                                  TXC_DATA_READY,
+
+     input                                   TXC_META_VALID,
+     input [`SIG_FBE_W-1:0]                  TXC_META_FDWBE,
+     input [`SIG_LBE_W-1:0]                  TXC_META_LDWBE,
+     input [`SIG_LOWADDR_W-1:0]              TXC_META_ADDR,
+     input [`SIG_TYPE_W-1:0]                 TXC_META_TYPE,
+     input [`SIG_LEN_W-1:0]                  TXC_META_LENGTH,
+     input [`SIG_BYTECNT_W-1:0]              TXC_META_BYTE_COUNT,
+     input [`SIG_TAG_W-1:0]                  TXC_META_TAG,
+     input [`SIG_REQID_W-1:0]                TXC_META_REQUESTER_ID,
+     input [`SIG_TC_W-1:0]                   TXC_META_TC,
+     input [`SIG_ATTR_W-1:0]                 TXC_META_ATTR,
+     input                                   TXC_META_EP,
+     output                                  TXC_META_READY
+     );
+
+    localparam C_VENDOR = "XILINX";
+    localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
+    localparam C_MAX_HDR_WIDTH = 128; // It's really 96... But it gets trimmed
+    localparam C_MAX_HDR_DWORDS = C_MAX_HDR_WIDTH/32;
+    localparam C_MAX_ALIGN_DWORDS = 0;
+    localparam C_MAX_NONPAY_DWORDS = C_MAX_HDR_DWORDS + C_MAX_ALIGN_DWORDS;
+    //
+    localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
+    localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
+    localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
+
+    /*AUTOWIRE*/
+    /*AUTOINPUT*/
+    ///*AUTOOUTPUT*/
+
+    wire                                     wTxHdrReady;
+    wire                                     wTxHdrValid;
+    wire [C_MAX_HDR_WIDTH-1:0]               wTxHdr;
+    wire [`SIG_NONPAY_W-1:0]                 wTxHdrNonpayLen;
+    wire [`SIG_PACKETLEN_W-1:0]              wTxHdrPacketLen;
+    wire [`SIG_LEN_W-1:0]                    wTxHdrPayloadLen; 
+    wire                                     wTxHdrNopayload;
+
+    wire                                     wTxDataReady;
+    wire [C_PCI_DATA_WIDTH-1:0]              wTxData;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxDataEndOffset;
+    wire                                     wTxDataStartFlag;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wTxDataEndFlags;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wTxDataWordValid;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wTxDataWordReady;
+
+    wire [C_PCI_DATA_WIDTH-1:0]              wTxcPkt;
+    wire                                     wTxcPktEndFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxcPktEndOffset;
+    wire                                     wTxcPktStartFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxcPktStartOffset;
+    wire                                     wTxcPktValid;
+    wire                                     wTxcPktReady;
+
+    txc_formatter_ultrascale
+        #(
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_FORMATTER_OUTPUT),
+          .C_PIPELINE_INPUT             (C_PIPELINE_FORMATTER_INPUT),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_HDR_WIDTH              (C_MAX_HDR_WIDTH))
+    txc_formatter_inst
+        (
+         // Outputs
+         .TX_HDR_VALID                  (wTxHdrValid),
+         .TX_HDR                        (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
+         .TX_HDR_NOPAYLOAD              (wTxHdrNopayload),
+         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
+         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
+         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
+         // Inputs
+         .TX_HDR_READY                  (wTxHdrReady),
+         /*AUTOINST*/
+         // Outputs
+         .TXC_META_READY                (TXC_META_READY),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .CONFIG_COMPLETER_ID           (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
+         .TXC_META_VALID                (TXC_META_VALID),
+         .TXC_META_FDWBE                (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_LENGTH               (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
+         .TXC_META_TYPE                 (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
+         .TXC_META_BYTE_COUNT           (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (TXC_META_TAG[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (TXC_META_TC[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (TXC_META_EP));
+
+    tx_engine
+        #(
+          .C_DATA_WIDTH                 (C_PCI_DATA_WIDTH),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_FORMATTER_DELAY            (C_FORMATTER_DELAY),
+          .C_MAX_HDR_WIDTH              (C_MAX_HDR_WIDTH),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_DWORDS),
+          .C_VENDOR                     (C_VENDOR))
+    txc_engine_inst
+        (
+         // Outputs
+         .TX_HDR_READY                  (wTxHdrReady),
+         .TX_DATA_READY                 (TXC_DATA_READY),
+         .TX_PKT                        (wTxcPkt[C_DATA_WIDTH-1:0]),
+         .TX_PKT_START_FLAG             (wTxcPktStartFlag),
+         .TX_PKT_START_OFFSET           (wTxcPktStartOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_PKT_END_FLAG               (wTxcPktEndFlag),
+         .TX_PKT_END_OFFSET             (wTxcPktEndOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_PKT_VALID                  (wTxcPktValid),
+         // Inputs
+         .TX_HDR_VALID                  (wTxHdrValid),
+         .TX_HDR                        (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
+         .TX_HDR_NOPAYLOAD              (wTxHdrNopayload),
+         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
+         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
+         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
+         .TX_DATA_VALID                 (TXC_DATA_VALID),
+         .TX_DATA                       (TXC_DATA[C_DATA_WIDTH-1:0]),
+         .TX_DATA_START_FLAG            (TXC_DATA_START_FLAG),
+         .TX_DATA_START_OFFSET          (TXC_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_DATA_END_FLAG              (TXC_DATA_END_FLAG),
+         .TX_DATA_END_OFFSET            (TXC_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_PKT_READY                  (wTxcPktReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    txc_translation_layer
+        #(
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT)
+          /*AUTOINSTPARAM*/)
+    txc_trans_inst
+        (
+         // Outputs
+         .TXC_PKT_READY                 (wTxcPktReady),
+         .S_AXIS_CC_TVALID              (S_AXIS_CC_TVALID),
+         .S_AXIS_CC_TLAST               (S_AXIS_CC_TLAST),
+         .S_AXIS_CC_TDATA               (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .TXC_PKT                       (wTxcPkt),
+         .TXC_PKT_VALID                 (wTxcPktValid),
+         .TXC_PKT_START_FLAG            (wTxcPktStartFlag),
+         .TXC_PKT_START_OFFSET          (wTxcPktStartOffset),
+         .TXC_PKT_END_FLAG              (wTxcPktEndFlag),
+         .TXC_PKT_END_OFFSET            (wTxcPktEndOffset),
+         .S_AXIS_CC_TREADY              (S_AXIS_CC_TREADY)
+         /*AUTOINST*/);
+
+endmodule // txc_engine_ultrascale
+
+module txc_formatter_ultrascale
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 1,
+      parameter C_MAX_HDR_WIDTH = `UPKT_TXC_MAXHDR_W
+      )
+    (
+     // Interface: Clocks
+     input                         CLK,
+
+     // Interface: Resets
+     input                         RST_IN,
+
+     // Interface: Configuration
+     input [`SIG_CPLID_W-1:0]      CONFIG_COMPLETER_ID,
+
+     // Interface: TXC
+     input                         TXC_META_VALID,
+     input [`SIG_FBE_W-1:0]        TXC_META_FDWBE,
+     input [`SIG_LBE_W-1:0]        TXC_META_LDWBE,
+     input [`SIG_LOWADDR_W-1:0]    TXC_META_ADDR,
+     input [`SIG_LEN_W-1:0]        TXC_META_LENGTH,
+     input [`SIG_TYPE_W-1:0]       TXC_META_TYPE,
+     input [`SIG_BYTECNT_W-1:0]    TXC_META_BYTE_COUNT,
+     input [`SIG_TAG_W-1:0]        TXC_META_TAG,
+     input [`SIG_REQID_W-1:0]      TXC_META_REQUESTER_ID,
+     input [`SIG_TC_W-1:0]         TXC_META_TC,
+     input [`SIG_ATTR_W-1:0]       TXC_META_ATTR,
+     input                         TXC_META_EP,
+     output                        TXC_META_READY,
+
+     // Interface: TX HDR
+     output                        TX_HDR_VALID,
+     output [C_MAX_HDR_WIDTH-1:0]  TX_HDR,
+     output [`SIG_LEN_W-1:0]       TX_HDR_PAYLOAD_LEN,
+     output [`SIG_NONPAY_W-1:0]    TX_HDR_NONPAY_LEN,
+     output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
+     output                        TX_HDR_NOPAYLOAD,
+     input                         TX_HDR_READY
+     );
+
+    wire [`UPKT_TXC_MAXHDR_W-1:0]  wHdr;
+
+    wire                           wTxHdrReady;
+    wire                           wTxHdrValid;
+    wire [C_MAX_HDR_WIDTH-1:0]     wTxHdr;
+    wire [`SIG_TYPE_W-1:0]         wTxType;
+    wire [`SIG_NONPAY_W-1:0]       wTxHdrNonpayLen;
+    wire [`SIG_PACKETLEN_W-1:0]    wTxHdrPacketLen;
+    wire [`SIG_LEN_W-1:0]          wTxHdrPayloadLen; 
+    wire                           wTxHdrNopayload;
+    
+    // Generic Header Fields
+    // ATYPE Should be copied from the request parameters, but we only use 0
+    assign wHdr[`UPKT_TXC_ADDRLOW_R] = TXC_META_ADDR;
+    assign wHdr[`UPKT_TXC_RSVD0_R] = `UPKT_TXC_RSVD0_W'd0;
+    assign wHdr[`UPKT_TXC_ATYPE_R] = `UPKT_TXC_ATYPE_W'd0;
+    assign wHdr[`UPKT_TXC_RSVD1_R] = `UPKT_TXC_RSVD1_W'd0;
+    assign wHdr[`UPKT_TXC_BYTECNT_R] = {1'b0,TXC_META_BYTE_COUNT};
+    assign wHdr[`UPKT_TXC_LOCKED_R] = `UPKT_TXC_LOCKED_W'd0;
+    assign wHdr[`UPKT_TXC_RSVD2_R] = `UPKT_TXC_RSVD2_W'd0;
+    assign wHdr[`UPKT_TXC_LENGTH_R] = {1'b0, TXC_META_LENGTH};
+    assign wHdr[`UPKT_TXC_STATUS_R] = `UPKT_TXC_STATUS_W'd0;
+    assign wHdr[`UPKT_TXC_EP_R] = TXC_META_EP;
+    assign wHdr[`UPKT_TXC_RSVD3_R] = `UPKT_TXC_RSVD3_W'd0;
+    assign wHdr[`UPKT_TXC_REQID_R] = TXC_META_REQUESTER_ID;
+    assign wHdr[`UPKT_TXC_TAG_R] = TXC_META_TAG;
+    assign wHdr[`UPKT_TXC_CPLID_R] = CONFIG_COMPLETER_ID;
+    assign wHdr[`UPKT_TXC_CPLIDEN_R] = 1'b0;
+    assign wHdr[`UPKT_TXC_TC_R] = TXC_META_TC;
+    assign wHdr[`UPKT_TXC_ATTR_R] = TXC_META_ATTR;
+    assign wHdr[`UPKT_TXC_TD_R] = `UPKT_TXC_TD_W'd0;
+    
+    assign wTxHdrNopayload = ~wTxType[`TRLS_TYPE_PAY_I];
+    assign wTxHdrNonpayLen = 3;
+    assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`UPKT_TXC_LENGTH_I +: `SIG_LEN_W];
+    assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                         (C_PIPELINE_INPUT?1:0),
+          .C_WIDTH                         (C_MAX_HDR_WIDTH + `SIG_TYPE_W),
+          .C_USE_MEMORY                    (0)
+          /*AUTOINSTPARAM*/)
+    input_inst
+        (
+         // Outputs
+         .WR_DATA_READY                  (TXC_META_READY),
+         .RD_DATA                        ({wTxHdr,wTxType}),
+         .RD_DATA_VALID                  (wTxHdrValid),
+         // Inputs
+         .WR_DATA                        ({32'b0,wHdr,TXC_META_TYPE}),
+         .WR_DATA_VALID                  (TXC_META_VALID),
+         .RD_DATA_READY                  (wTxHdrReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                         (C_PIPELINE_OUTPUT?1:0),
+          .C_WIDTH                         (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
+          .C_USE_MEMORY                    (0)
+          /*AUTOINSTPARAM*/)
+    output_inst
+        (
+         // Outputs
+         .WR_DATA_READY                  (wTxHdrReady),
+         .RD_DATA                        ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
+         .RD_DATA_VALID                  (TX_HDR_VALID),
+         // Inputs
+         .WR_DATA                        ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
+         .WR_DATA_VALID                  (wTxHdrValid),
+         .RD_DATA_READY                  (TX_HDR_READY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+endmodule
+
+module txc_translation_layer
+    #(
+      parameter C_PCI_DATA_WIDTH = 10'd128,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 0
+    
+      )
+    (
+     // Interface: Clocks
+     input                                   CLK,
+
+     // Interface: Resets
+     input                                   RST_IN,
+
+     // Interface: TXC Classic
+     output                                  TXC_PKT_READY,
+     input [C_PCI_DATA_WIDTH-1:0]            TXC_PKT,
+     input                                   TXC_PKT_VALID,
+     input                                   TXC_PKT_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_START_OFFSET,
+     input                                   TXC_PKT_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_END_OFFSET,
+
+     // Interface: CC
+     input                                   S_AXIS_CC_TREADY,
+     output                                  S_AXIS_CC_TVALID,
+     output                                  S_AXIS_CC_TLAST,
+     output [C_PCI_DATA_WIDTH-1:0]           S_AXIS_CC_TDATA,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]      S_AXIS_CC_TKEEP,
+     output [`SIG_CC_TUSER_W-1:0]            S_AXIS_CC_TUSER
+     );
+
+    localparam C_INPUT_STAGES = C_PIPELINE_INPUT != 0? 1:0;
+    localparam C_OUTPUT_STAGES = C_PIPELINE_OUTPUT != 0? 1:0;
+
+    wire                                     wTxcPktReady;
+    wire [C_PCI_DATA_WIDTH-1:0]              wTxcPkt;
+    wire                                     wTxcPktValid;
+    wire                                     wTxcPktStartFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxcPktStartOffset;
+    wire                                     wTxcPktEndFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxcPktEndOffset;
+
+    wire                                     wSAxisCcTReady;
+    wire                                     wSAxisCcTValid;
+    wire                                     wSAxisCcTLast;
+    wire [C_PCI_DATA_WIDTH-1:0]              wSAxisCcTData;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wSAxisCcTKeep;
+    wire [`SIG_CC_TUSER_W-1:0]               wSAxisCcTUser;
+
+    /*ASSIGN TXC -> CC*/
+    assign wTxcPktReady = wSAxisCcTReady;
+    assign wSAxisCcTValid = wTxcPktValid;
+    assign wSAxisCcTLast = wTxcPktEndFlag;
+    assign wSAxisCcTData = wTxcPkt;
+    assign S_AXIS_CC_TUSER = `SIG_CC_TUSER_W'd0; // Do not enable parity bits, and no discontinues
+    
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                         (C_INPUT_STAGES),
+          .C_WIDTH                         (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))),
+          .C_USE_MEMORY                    (0)
+          /*AUTOINSTPARAM*/)
+    input_inst
+        (
+         // Outputs
+         .WR_DATA_READY                  (TXC_PKT_READY),
+         .RD_DATA                        ({wTxcPkt,wTxcPktStartFlag,wTxcPktStartOffset,wTxcPktEndFlag,wTxcPktEndOffset}),
+         .RD_DATA_VALID                  (wTxcPktValid),
+         // Inputs
+         .WR_DATA                        ({TXC_PKT,TXC_PKT_START_FLAG,TXC_PKT_START_OFFSET,
+                                           TXC_PKT_END_FLAG,TXC_PKT_END_OFFSET}),
+         .WR_DATA_VALID                  (TXC_PKT_VALID),
+         .RD_DATA_READY                  (wTxcPktReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+
+    offset_to_mask
+        #(
+          // Parameters
+          .C_MASK_SWAP                  (0),
+          .C_MASK_WIDTH                 (C_PCI_DATA_WIDTH/32)
+          /*AUTOINSTPARAM*/)
+    otom_inst
+        (
+         // Outputs
+         .MASK                          (wSAxisCcTKeep),
+         // Inputs
+         .OFFSET_ENABLE                 (wTxcPktEndFlag),
+         .OFFSET                        (wTxcPktEndOffset)
+         /*AUTOINST*/);
+    
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                         (C_OUTPUT_STAGES),
+          .C_WIDTH                         (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)),
+          .C_USE_MEMORY                    (0)
+          /*AUTOINSTPARAM*/)
+    output_inst
+        (
+         // Outputs
+         .WR_DATA_READY                  (wSAxisCcTReady),
+         .RD_DATA                        ({S_AXIS_CC_TDATA,S_AXIS_CC_TLAST,S_AXIS_CC_TKEEP}),
+         .RD_DATA_VALID                  (S_AXIS_CC_TVALID),
+         // Inputs
+         .WR_DATA                        ({wSAxisCcTData,wSAxisCcTLast,wSAxisCcTKeep}),
+         .WR_DATA_VALID                  (wSAxisCcTValid),
+         .RD_DATA_READY                  (S_AXIS_CC_TREADY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../common/" "../../common/")
+// End:
diff --git a/fpga/riffa_hdl/txr_engine_classic.v b/fpga/riffa_hdl/txr_engine_classic.v
new file mode 100644
index 0000000..651ff50
--- /dev/null
+++ b/fpga/riffa_hdl/txr_engine_classic.v
@@ -0,0 +1,352 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            txc_engine_classic.v
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The TXR Engine takes unformatted completions, formats
+// these packets into "TLP's" or Transaction Layer Packets. These packets must
+// meet max-request, max-payload, and payload termination requirements (see Read
+// Completion Boundary). The TXR Engine does not check these requirements during
+// operation, but may do so during simulation. This Engine is capable of
+// operating at "line rate".  This file also contains the txr_formatter module,
+// which formats request headers.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "trellis.vh" // Defines the user-facing signal widths.
+`include "tlp.vh" // Defines the endpoint-facing field widths in a TLP
+module txr_engine_classic
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 0,
+      parameter C_MAX_PAYLOAD_DWORDS = 64,
+      parameter C_DEPTH_PACKETS = 10,
+      parameter C_VENDOR = "ALTERA"
+      )
+    (
+     // Interface: Clocks
+     input                                    CLK,
+
+     // Interface: Resets
+     input                                    RST_IN,
+
+     // Interface: Configuration 
+     input [`SIG_CPLID_W-1:0]                 CONFIG_COMPLETER_ID,
+
+     // Interface: TXR Classic
+     input                                    TXR_TLP_READY,
+     output [C_PCI_DATA_WIDTH-1:0]            TXR_TLP,
+     output                                   TXR_TLP_VALID,
+     output                                   TXR_TLP_START_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_START_OFFSET,
+     output                                   TXR_TLP_END_FLAG,
+     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_END_OFFSET,
+
+     // Interface: TXR Engine
+     input                                    TXR_DATA_VALID,
+     input [C_PCI_DATA_WIDTH-1:0]             TXR_DATA,
+     input                                    TXR_DATA_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_START_OFFSET,
+     input                                    TXR_DATA_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_END_OFFSET,
+     output                                   TXR_DATA_READY,
+
+     input                                    TXR_META_VALID,
+     input [`SIG_FBE_W-1:0]                   TXR_META_FDWBE, 
+     input [`SIG_LBE_W-1:0]                   TXR_META_LDWBE,
+     input [`SIG_ADDR_W-1:0]                  TXR_META_ADDR,
+     input [`SIG_LEN_W-1:0]                   TXR_META_LENGTH,
+     input [`SIG_TAG_W-1:0]                   TXR_META_TAG,
+     input [`SIG_TC_W-1:0]                    TXR_META_TC,
+     input [`SIG_ATTR_W-1:0]                  TXR_META_ATTR,
+     input [`SIG_TYPE_W-1:0]                  TXR_META_TYPE,
+     input                                    TXR_META_EP,
+     output                                   TXR_META_READY     
+     );
+
+    localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
+    localparam C_MAX_HDR_WIDTH = `TLP_MAXHDR_W;
+    localparam C_MAX_ALIGN_WIDTH = (C_VENDOR == "ALTERA") ? 32: 
+                                   (C_VENDOR == "XILINX") ? 0  : 
+                                   0;
+
+    localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
+    localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
+    localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
+    
+    /*AUTOWIRE*/
+    /*AUTOINPUT*/
+    ///*AUTOOUTPUT*/
+
+    wire                                      wTxHdrReady;
+    wire                                      wTxHdrValid;
+    wire [C_MAX_HDR_WIDTH-1:0]                wTxHdr;
+    wire [`SIG_TYPE_W-1:0]                    wTxType;
+    wire [`SIG_NONPAY_W-1:0]                  wTxHdrNonpayLen;
+    wire [`SIG_PACKETLEN_W-1:0]               wTxHdrPacketLen;
+    wire [`SIG_LEN_W-1:0]                     wTxHdrPayloadLen; 
+    wire                                      wTxHdrNopayload;
+
+    txr_formatter_classic
+        #(
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_FORMATTER_OUTPUT),
+          .C_PIPELINE_INPUT             (C_PIPELINE_FORMATTER_INPUT),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_HDR_WIDTH              (C_MAX_HDR_WIDTH),
+          .C_MAX_ALIGN_WIDTH            (C_MAX_ALIGN_WIDTH),
+          .C_VENDOR                     (C_VENDOR))
+    txr_formatter_inst
+        (
+         // Outputs
+         .TX_HDR_VALID                  (wTxHdrValid),
+         .TX_HDR                        (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
+         .TX_HDR_NOPAYLOAD              (wTxHdrNopayload),
+         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
+         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
+         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
+         // Inputs
+         .TX_HDR_READY                  (wTxHdrReady),
+         /*AUTOINST*/
+         // Outputs
+         .TXR_META_READY                (TXR_META_READY),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .CONFIG_COMPLETER_ID           (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
+         .TXR_META_VALID                (TXR_META_VALID),
+         .TXR_META_FDWBE                (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (TXR_META_TAG[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (TXR_META_TC[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (TXR_META_EP));
+
+    tx_engine
+        #(
+          .C_DATA_WIDTH                 (C_PCI_DATA_WIDTH),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_FORMATTER_DELAY            (C_FORMATTER_DELAY),
+          .C_MAX_HDR_WIDTH              (C_MAX_HDR_WIDTH),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_DWORDS),
+          .C_VENDOR                     (C_VENDOR))
+    txr_engine_inst
+        (
+         // Outputs
+         .TX_HDR_READY                  (wTxHdrReady),
+         .TX_DATA_READY                 (TXR_DATA_READY),
+         .TX_PKT                        (TXR_TLP[C_DATA_WIDTH-1:0]),
+         .TX_PKT_START_FLAG             (TXR_TLP_START_FLAG),
+         .TX_PKT_START_OFFSET           (TXR_TLP_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_PKT_END_FLAG               (TXR_TLP_END_FLAG),
+         .TX_PKT_END_OFFSET             (TXR_TLP_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_PKT_VALID                  (TXR_TLP_VALID),
+         // Inputs
+         .TX_HDR_VALID                  (wTxHdrValid),
+         .TX_HDR                        (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
+         .TX_HDR_NOPAYLOAD              (wTxHdrNopayload),
+         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
+         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
+         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
+         .TX_DATA_VALID                 (TXR_DATA_VALID),
+         .TX_DATA                       (TXR_DATA[C_DATA_WIDTH-1:0]),
+         .TX_DATA_START_FLAG            (TXR_DATA_START_FLAG),
+         .TX_DATA_START_OFFSET          (TXR_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_DATA_END_FLAG              (TXR_DATA_END_FLAG),
+         .TX_DATA_END_OFFSET            (TXR_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_PKT_READY                  (TXR_TLP_READY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+endmodule
+
+module txr_formatter_classic
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_HDR_WIDTH = `TLP_MAXHDR_W,
+      parameter C_MAX_ALIGN_WIDTH = 32,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 1,
+      parameter C_VENDOR = "ALTERA"
+      )
+    (
+     // Interface: Clocks
+     input                         CLK,
+
+     // Interface: Resets
+     input                         RST_IN,
+
+     // Interface: Configuration
+     input [`SIG_CPLID_W-1:0]      CONFIG_COMPLETER_ID,
+
+     // Interface: TXR
+     input                         TXR_META_VALID,
+     input [`SIG_FBE_W-1:0]        TXR_META_FDWBE,
+     input [`SIG_LBE_W-1:0]        TXR_META_LDWBE,
+     input [`SIG_ADDR_W-1:0]       TXR_META_ADDR,
+     input [`SIG_LEN_W-1:0]        TXR_META_LENGTH,
+     input [`SIG_TAG_W-1:0]        TXR_META_TAG,
+     input [`SIG_TC_W-1:0]         TXR_META_TC,
+     input [`SIG_ATTR_W-1:0]       TXR_META_ATTR,
+     input [`SIG_TYPE_W-1:0]       TXR_META_TYPE,
+     input                         TXR_META_EP,
+     output                        TXR_META_READY,
+
+     // Interface: TX HDR
+     output                        TX_HDR_VALID,
+     output [C_MAX_HDR_WIDTH-1:0]  TX_HDR,
+     output [`SIG_LEN_W-1:0]       TX_HDR_PAYLOAD_LEN,
+     output [`SIG_NONPAY_W-1:0]    TX_HDR_NONPAY_LEN,
+     output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
+     output                        TX_HDR_NOPAYLOAD,
+     input                         TX_HDR_READY
+     );
+    
+    wire                           wWrReq;
+    wire [`TLP_FMT_W-1:0]          wHdrLoFmt;
+    wire [63:0]                    wHdrLo;
+
+    wire [63:0]                    _wTxHdr;
+    wire                           wTxHdrReady;
+    wire                           wTxHdrValid;
+    wire [(`TLP_REQADDR_W/2)-1:0]  wTxHdrAddr[1:0];
+    wire [(`TLP_REQADDR_W/2)-1:0]  wTxHdrAddrDW0;
+    wire                           wTxHdr4DW;
+    wire                           wTxHdrAlignmentNeeded;
+    wire [C_MAX_HDR_WIDTH-1:0]     wTxHdr;
+    wire [`SIG_TYPE_W-1:0]         wTxType;
+    wire [`SIG_NONPAY_W-1:0]       wTxHdrNonpayLen;
+    wire [`SIG_PACKETLEN_W-1:0]    wTxHdrPacketLen;
+    wire [`SIG_LEN_W-1:0]          wTxHdrPayloadLen; 
+    wire                           wTxHdrNopayload;
+
+    assign wHdrLoFmt = {1'b0, TXR_META_TYPE[`TRLS_TYPE_PAY_I],1'bx};
+
+    // Reserved Fields
+    assign wHdrLo[`TLP_RSVD0_R] = `TLP_RSVD0_V;
+    assign wHdrLo[`TLP_ADDRTYPE_R] = `TLP_ADDRTYPE_W'b0;
+    assign wHdrLo[`TLP_TH_R] = `TLP_TH_W'b0;
+    assign wHdrLo[`TLP_RSVD1_R] = `TLP_RSVD1_V;
+    assign wHdrLo[`TLP_RSVD2_R] = `TLP_RSVD2_V;
+
+    // Generic Header Fields
+    assign wHdrLo[`TLP_LEN_R] = TXR_META_LENGTH;
+    assign wHdrLo[`TLP_EP_R] = TXR_META_EP;
+    assign wHdrLo[`TLP_TD_R] = `TLP_NODIGEST_V;
+    assign wHdrLo[`TLP_ATTR0_R] = TXR_META_ATTR[1:0];
+    assign wHdrLo[`TLP_ATTR1_R] = TXR_META_ATTR[2];
+    assign wHdrLo[`TLP_TYPE_R] = TXR_META_TYPE; // WORKAROUND
+    assign wHdrLo[`TLP_TC_R] = TXR_META_TC;
+    assign wHdrLo[`TLP_FMT_R] = wHdrLoFmt; 
+
+    // Request Specific Fields
+    assign wHdrLo[`TLP_REQFBE_R] = TXR_META_FDWBE;
+    assign wHdrLo[`TLP_REQLBE_R] = TXR_META_LDWBE;
+    assign wHdrLo[`TLP_REQTAG_R] = TXR_META_TAG;
+    assign wHdrLo[`TLP_REQREQID_R] = CONFIG_COMPLETER_ID;
+
+    // Second header formatting stage
+    assign wTxHdr4DW = wTxHdrAddr[1] != 32'b0;
+    assign {wTxHdr[`TLP_FMT_R],wTxHdr[`TLP_TYPE_R]} = trellis_to_tlp_type(_wTxHdr[`TLP_TYPE_I +: `SIG_TYPE_W],wTxHdr4DW);
+    assign wTxHdr[`TLP_TYPE_I-1:0] = _wTxHdr[`TLP_TYPE_I-1:0];
+    assign wTxHdr[63:32] = _wTxHdr[63:32];
+    assign wTxHdr[127:64] = {wTxHdrAddr[~wTxHdr4DW],wTxHdrAddr[wTxHdr4DW]};
+
+    // Metadata, to the aligner
+    assign wTxHdrNopayload = ~wTxHdr[`TLP_PAYBIT_I];
+    assign wTxHdrAddrDW0 = wTxHdrAddr[0];
+    assign wTxHdrAlignmentNeeded = (wTxHdrAddrDW0[2] == wTxHdr4DW);
+    assign wTxHdrNonpayLen = {1'b0,{wTxHdr4DW,~wTxHdr4DW,~wTxHdr4DW}} + ((C_VENDOR == "ALTERA") ? {3'b0,(wTxHdrAlignmentNeeded & ~wTxHdrNopayload)}:0);    
+    assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`TLP_LEN_R];
+    assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;    
+
+    pipeline
+        #(// Parameters
+          .C_DEPTH                         (C_PIPELINE_INPUT?1:0),
+          .C_WIDTH                         (C_MAX_HDR_WIDTH),
+          .C_USE_MEMORY                    (0)
+          /*AUTOINSTPARAM*/)
+    input_inst
+        (// Outputs
+         .WR_DATA_READY                  (TXR_META_READY),
+         .RD_DATA                        ({wTxHdrAddr[1],wTxHdrAddr[0],_wTxHdr[63:0]}),
+         .RD_DATA_VALID                  (wTxHdrValid),
+         // Inputs
+         .WR_DATA                        ({TXR_META_ADDR, wHdrLo}),
+         .WR_DATA_VALID                  (TXR_META_VALID),
+         .RD_DATA_READY                  (wTxHdrReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                         (C_PIPELINE_OUTPUT?1:0),
+          .C_WIDTH                         (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
+          .C_USE_MEMORY                    (0)
+          /*AUTOINSTPARAM*/)
+    output_inst
+        (
+         // Outputs
+         .WR_DATA_READY                  (wTxHdrReady),
+         .RD_DATA                        ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
+         .RD_DATA_VALID                  (TX_HDR_VALID),
+         // Inputs
+         .WR_DATA                        ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
+         .WR_DATA_VALID                  (wTxHdrValid),
+         .RD_DATA_READY                  (TX_HDR_READY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../common/" "../../common/")
+// End:
diff --git a/fpga/riffa_hdl/txr_engine_ultrascale.v b/fpga/riffa_hdl/txr_engine_ultrascale.v
new file mode 100644
index 0000000..53631f3
--- /dev/null
+++ b/fpga/riffa_hdl/txr_engine_ultrascale.v
@@ -0,0 +1,539 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            txr_engine_ultrascale.v
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The TXR Engine takes unformatted completions, formats
+// these packets into AXI-style packets. These packets must meet max-request,
+// max-payload, and payload termination requirements (see Read Completion
+// Boundary). The TXR Engine does not check these requirements during operation,
+// but may do so during simulation.
+// 
+// This Engine is capable of operating at "line rate".
+// 
+// Author: Dustin Richmond (@darichmond) 
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "ultrascale.vh"
+module txr_engine_ultrascale
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 1,
+      parameter C_DEPTH_PACKETS = 10,
+      parameter C_MAX_PAYLOAD_DWORDS = 256
+      )
+    (
+     // Interface: Clocks
+     input                                   CLK,
+
+     // Interface: Resets
+     input                                   RST_IN,
+
+     // Interface: Configuration
+     input [`SIG_CPLID_W-1:0]                CONFIG_COMPLETER_ID,
+
+     // Interface: RQ
+     input                                   S_AXIS_RQ_TREADY,
+     output                                  S_AXIS_RQ_TVALID,
+     output                                  S_AXIS_RQ_TLAST,
+     output [C_PCI_DATA_WIDTH-1:0]           S_AXIS_RQ_TDATA,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]      S_AXIS_RQ_TKEEP,
+     output [`SIG_RQ_TUSER_W-1:0]            S_AXIS_RQ_TUSER,
+
+     // Interface: TXR Engine
+     input                                   TXR_DATA_VALID,
+     input [C_PCI_DATA_WIDTH-1:0]            TXR_DATA,
+     input                                   TXR_DATA_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
+     input                                   TXR_DATA_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
+     output                                  TXR_DATA_READY,
+
+     input                                   TXR_META_VALID,
+     input [`SIG_FBE_W-1:0]                  TXR_META_FDWBE, 
+     input [`SIG_LBE_W-1:0]                  TXR_META_LDWBE,
+     input [`SIG_ADDR_W-1:0]                 TXR_META_ADDR,
+     input [`SIG_LEN_W-1:0]                  TXR_META_LENGTH,
+     input [`SIG_TAG_W-1:0]                  TXR_META_TAG,
+     input [`SIG_TC_W-1:0]                   TXR_META_TC,
+     input [`SIG_ATTR_W-1:0]                 TXR_META_ATTR,
+     input [`SIG_TYPE_W-1:0]                 TXR_META_TYPE,
+     input                                   TXR_META_EP,
+     output                                  TXR_META_READY     
+     );
+
+    localparam C_VENDOR = "XILINX";
+    localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
+    localparam C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W;
+    localparam C_MAX_HDR_DWORDS = C_MAX_HDR_WIDTH/32;
+    localparam C_MAX_ALIGN_DWORDS = 0;
+    localparam C_MAX_NONPAY_DWORDS = C_MAX_HDR_DWORDS + C_MAX_ALIGN_DWORDS + 1;
+    localparam C_MAX_PACKET_DWORDS = C_MAX_NONPAY_DWORDS + C_MAX_PAYLOAD_DWORDS;
+    localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
+    localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
+    localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
+    
+    /*AUTOWIRE*/
+    /*AUTOINPUT*/
+    ///*AUTOOUTPUT*/
+    
+    wire                                     wTxHdrReady;
+    wire                                     wTxHdrValid;
+    wire [C_MAX_HDR_WIDTH-1:0]               wTxHdr;
+    wire [`SIG_NONPAY_W-1:0]                 wTxHdrNonpayLen;
+    wire [`SIG_PACKETLEN_W-1:0]              wTxHdrPacketLen;
+    wire [`SIG_LEN_W-1:0]                    wTxHdrPayloadLen; 
+    wire                                     wTxHdrNopayload;
+
+    wire                                     wTxDataReady;
+    wire [C_PCI_DATA_WIDTH-1:0]              wTxData;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxDataEndOffset;
+    wire                                     wTxDataStartFlag;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wTxDataEndFlags;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wTxDataWordValid;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wTxDataWordReady;
+
+    wire [C_PCI_DATA_WIDTH-1:0]              wTxrPkt;
+    wire                                     wTxrPktEndFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxrPktEndOffset;
+    wire                                     wTxrPktStartFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxrPktStartOffset;
+    wire                                     wTxrPktValid;
+    wire                                     wTxrPktReady;
+
+    wire                                     wTxrDataReady;
+
+    assign TXR_DATA_READY = wTxrDataReady;
+    
+    txr_formatter_ultrascale
+        #(
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_FORMATTER_OUTPUT),
+          .C_PIPELINE_INPUT             (C_PIPELINE_FORMATTER_INPUT),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_HDR_WIDTH              (C_MAX_HDR_WIDTH),
+          .C_MAX_NONPAY_DWORDS          (C_MAX_NONPAY_DWORDS),
+          .C_MAX_PACKET_DWORDS          (C_MAX_PACKET_DWORDS))
+    txr_formatter_inst
+        (
+         // Outputs
+         .TX_HDR_VALID                  (wTxHdrValid),
+         .TX_HDR                        (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
+         .TX_HDR_NOPAYLOAD              (wTxHdrNopayload),
+         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
+         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
+         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
+         // Inputs
+         .TX_HDR_READY                  (wTxHdrReady),
+         /*AUTOINST*/
+         // Outputs
+         .TXR_META_READY                (TXR_META_READY),
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN),
+         .CONFIG_COMPLETER_ID           (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
+         .TXR_META_VALID                (TXR_META_VALID),
+         .TXR_META_FDWBE                (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (TXR_META_TAG[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (TXR_META_TC[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (TXR_META_EP));
+
+    tx_engine
+        #(
+          .C_DATA_WIDTH                 (C_PCI_DATA_WIDTH),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_FORMATTER_DELAY            (C_FORMATTER_DELAY),
+          .C_MAX_HDR_WIDTH              (C_MAX_HDR_WIDTH),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_DWORDS),
+          .C_VENDOR                     (C_VENDOR))
+    txr_engine_inst
+        (
+         // Outputs
+         .TX_HDR_READY                  (wTxHdrReady),
+         .TX_DATA_READY                 (wTxrDataReady),
+         .TX_PKT                        (wTxrPkt[C_DATA_WIDTH-1:0]),
+         .TX_PKT_START_FLAG             (wTxrPktStartFlag),
+         .TX_PKT_START_OFFSET           (wTxrPktStartOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_PKT_END_FLAG               (wTxrPktEndFlag),
+         .TX_PKT_END_OFFSET             (wTxrPktEndOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_PKT_VALID                  (wTxrPktValid),
+         // Inputs
+         .TX_HDR_VALID                  (wTxHdrValid),
+         .TX_HDR                        (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
+         .TX_HDR_NOPAYLOAD              (wTxHdrNopayload),
+         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
+         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
+         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
+         .TX_DATA_VALID                 (TXR_DATA_VALID),
+         .TX_DATA                       (TXR_DATA[C_DATA_WIDTH-1:0]),
+         .TX_DATA_START_FLAG            (TXR_DATA_START_FLAG),
+         .TX_DATA_START_OFFSET          (TXR_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_DATA_END_FLAG              (TXR_DATA_END_FLAG),
+         .TX_DATA_END_OFFSET            (TXR_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
+         .TX_PKT_READY                  (wTxrPktReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    txr_translation_layer
+        #(
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT)
+          /*AUTOINSTPARAM*/)
+    txr_trans_inst
+        (
+         // Outputs
+         .TXR_PKT_READY                 (wTxrPktReady),
+         .S_AXIS_RQ_TVALID              (S_AXIS_RQ_TVALID),
+         .S_AXIS_RQ_TLAST               (S_AXIS_RQ_TLAST),
+         .S_AXIS_RQ_TDATA               (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),
+         // Inputs
+         .TXR_PKT                       (wTxrPkt),
+         .TXR_PKT_VALID                 (wTxrPktValid),
+         .TXR_PKT_START_FLAG            (wTxrPktStartFlag),
+         .TXR_PKT_START_OFFSET          (wTxrPktStartOffset),
+         .TXR_PKT_END_FLAG              (wTxrPktEndFlag),
+         .TXR_PKT_END_OFFSET            (wTxrPktEndOffset),
+         .S_AXIS_RQ_TREADY              (S_AXIS_RQ_TREADY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+endmodule // txr_engine_ultrascale
+
+
+module txr_formatter_ultrascale
+    #(
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 1,
+      parameter C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W,
+      parameter C_MAX_NONPAY_DWORDS = 5,
+      parameter C_MAX_PACKET_DWORDS = 10
+      )
+    (
+     // Interface: Clocks
+     input                         CLK,
+
+     // Interface: Resets
+     input                         RST_IN,
+
+     // Interface: Configuration
+     input [`SIG_CPLID_W-1:0]      CONFIG_COMPLETER_ID,
+
+     // Interface: TXR
+     input                         TXR_META_VALID,
+     input [`SIG_FBE_W-1:0]        TXR_META_FDWBE,
+     input [`SIG_LBE_W-1:0]        TXR_META_LDWBE,
+     input [`SIG_ADDR_W-1:0]       TXR_META_ADDR,
+     input [`SIG_LEN_W-1:0]        TXR_META_LENGTH,
+     input [`SIG_TAG_W-1:0]        TXR_META_TAG,
+     input [`SIG_TC_W-1:0]         TXR_META_TC,
+     input [`SIG_ATTR_W-1:0]       TXR_META_ATTR,
+     input [`SIG_TYPE_W-1:0]       TXR_META_TYPE,
+     input                         TXR_META_EP,
+     output                        TXR_META_READY,
+
+     // Interface: TX HDR
+     output                        TX_HDR_VALID,
+     output [C_MAX_HDR_WIDTH-1:0]  TX_HDR,
+     output [`SIG_LEN_W-1:0]       TX_HDR_PAYLOAD_LEN,
+     output [`SIG_NONPAY_W-1:0]    TX_HDR_NONPAY_LEN,
+     output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
+     output                        TX_HDR_NOPAYLOAD,
+     input                         TX_HDR_READY
+     );
+
+    wire                           wHdrNoPayload;
+    wire [`UPKT_TXR_MAXHDR_W-1:0]  wHdr;
+    
+    wire                           wTxHdrReady;
+    wire                           wTxHdrValid;
+    wire [`UPKT_TXR_MAXHDR_W-1:0]  wTxHdr;
+    wire [`SIG_NONPAY_W-1:0]       wTxHdrNonpayLen;
+    wire [`SIG_PACKETLEN_W-1:0]    wTxHdrPacketLen;
+    wire [`SIG_LEN_W-1:0]          wTxHdrPayloadLen; 
+    wire                           wTxHdrNopayload;
+    wire [`SIG_TYPE_W-1:0]         wTxHdrType;
+    
+    // Generic Header Fields
+    assign wHdr[`UPKT_TXR_ATYPE_R] = `UPKT_TXR_ATYPE_W'd0;
+    assign wHdr[`UPKT_TXR_ADDR_R] = TXR_META_ADDR[63:2];
+    assign wHdr[`UPKT_TXR_LENGTH_R] = {1'b0,TXR_META_LENGTH};
+    assign wHdr[`UPKT_TXR_EP_R] = TXR_META_EP;
+`ifdef BE_HACK
+    assign wHdr[`UPKT_TXR_FBE_R] = TXR_META_FDWBE;
+    assign wHdr[`UPKT_TXR_LBE_R] = TXR_META_LDWBE;
+    assign wHdr[`UPKT_TXR_RSVD0_R] = 0;
+
+`else
+    assign wHdr[`UPKT_TXR_REQID_R] = CONFIG_COMPLETER_ID;
+`endif
+    //assign wHdr[`UPKT_TXR_REQID_R] = `UPKT_TXR_REQID_W'd0;
+    assign wHdr[`UPKT_TXR_TAG_R] = TXR_META_TAG;
+    assign wHdr[`UPKT_TXR_CPLID_R] = `UPKT_TXR_CPLID_W'd0;
+    assign wHdr[`UPKT_TXR_REQIDEN_R] = 0;
+    assign wHdr[`UPKT_TXR_TC_R] = TXR_META_TC;
+    assign wHdr[`UPKT_TXR_ATTR_R] = TXR_META_ATTR;
+    assign wHdr[`UPKT_TXR_TD_R] = `UPKT_TXR_TD_W'd0;
+
+    assign wTxHdr[`UPKT_TXR_TYPE_R] = trellis_to_upkt_type(wTxHdrType);
+    assign wTxHdrNopayload = ~wTxHdrType[`TRLS_TYPE_PAY_I];
+    assign wTxHdrNonpayLen = 4;
+    assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`UPKT_TXR_LENGTH_R];
+    assign wTxHdrPacketLen = wTxHdrNonpayLen + wTxHdrPayloadLen;
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                         (C_PIPELINE_INPUT?1:0),
+          .C_WIDTH                         (`UPKT_TXR_MAXHDR_W-1),
+          .C_USE_MEMORY                    (0)
+          /*AUTOINSTPARAM*/)
+    input_inst
+        (
+         // Outputs
+         .WR_DATA_READY                  (TXR_META_READY),
+         .RD_DATA                        ({wTxHdr[`UPKT_TXR_MAXHDR_W-1:(`UPKT_TXR_TYPE_I + `UPKT_TXR_TYPE_W)],
+                                           wTxHdr[`UPKT_TXR_TYPE_I-1:0],
+                                           wTxHdrType}),
+         .RD_DATA_VALID                  (wTxHdrValid),
+         // Inputs
+         .WR_DATA                        ({wHdr[`UPKT_TXR_MAXHDR_W-1:(`UPKT_TXR_TYPE_I + `UPKT_TXR_TYPE_W)],
+                                           wHdr[`UPKT_TXR_TYPE_I-1:0],
+                                           TXR_META_TYPE}),
+         .WR_DATA_VALID                  (TXR_META_VALID),
+         .RD_DATA_READY                  (wTxHdrReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                         (C_PIPELINE_OUTPUT?1:0),
+          .C_WIDTH                         (`UPKT_TXR_MAXHDR_W + 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
+          .C_USE_MEMORY                    (0)
+          /*AUTOINSTPARAM*/)
+    output_inst
+        (
+         // Outputs
+         .WR_DATA_READY                  (wTxHdrReady),
+         .RD_DATA                        ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
+         .RD_DATA_VALID                  (TX_HDR_VALID),
+         // Inputs
+         .WR_DATA                        ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
+         .WR_DATA_VALID                  (wTxHdrValid),
+         .RD_DATA_READY                  (TX_HDR_READY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+endmodule
+
+
+module txr_translation_layer
+    #(
+      parameter C_PCI_DATA_WIDTH = 10'd128,
+      parameter C_PIPELINE_INPUT = 1,
+      parameter C_PIPELINE_OUTPUT = 0
+      )
+    (
+     // Interface: Clocks
+     input                                   CLK,
+
+     // Interface: Resets
+     input                                   RST_IN,
+
+     // Interface: TXR Classic
+     output                                  TXR_PKT_READY,
+     input [C_PCI_DATA_WIDTH-1:0]            TXR_PKT,
+     input                                   TXR_PKT_VALID,
+     input                                   TXR_PKT_START_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_PKT_START_OFFSET,
+     input                                   TXR_PKT_END_FLAG,
+     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_PKT_END_OFFSET,
+
+     // Interface: RQ
+     input                                   S_AXIS_RQ_TREADY,
+     output                                  S_AXIS_RQ_TVALID,
+     output                                  S_AXIS_RQ_TLAST,
+     output [C_PCI_DATA_WIDTH-1:0]           S_AXIS_RQ_TDATA,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]      S_AXIS_RQ_TKEEP,
+     output [`SIG_RQ_TUSER_W-1:0]            S_AXIS_RQ_TUSER
+     );
+
+    localparam C_INPUT_STAGES = C_PIPELINE_INPUT != 0? 1:0;
+    localparam C_OUTPUT_STAGES = C_PIPELINE_OUTPUT != 0? 1:0;
+
+    wire                                     wTxrPktReady;
+    wire [C_PCI_DATA_WIDTH-1:0]              wTxrPkt;
+    wire                                     wTxrPktValid;
+    wire                                     wTxrPktStartFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxrPktStartOffset;
+    wire                                     wTxrPktEndFlag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxrPktEndOffset;
+
+    wire                                     wSAxisRqTReady;
+    wire                                     wSAxisRqTValid;
+    wire                                     wSAxisRqTLast;
+    wire [C_PCI_DATA_WIDTH-1:0]              wSAxisRqTData;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wSAxisRqTKeep;
+    wire [`SIG_RQ_TUSER_W-1:0]               wSAxisRqTUser;
+
+    wire                                     _wSAxisRqTReady;
+    wire                                     _wSAxisRqTValid;
+    wire                                     _wSAxisRqTLast;
+    wire [C_PCI_DATA_WIDTH-1:0]              _wSAxisRqTData;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]         _wSAxisRqTKeep;
+
+    /*ASSIGN TXR -> RQ*/
+    assign wTxrPktReady = _wSAxisRqTReady;
+    assign _wSAxisRqTValid = wTxrPktValid;
+    assign _wSAxisRqTLast = wTxrPktEndFlag;
+    assign _wSAxisRqTData = wTxrPkt;
+
+    // BE Hack
+    assign wSAxisRqTUser[3:0] = wTxrPkt[(`UPKT_TXR_FBE_I % C_PCI_DATA_WIDTH) +: `UPKT_TXR_FBE_W];
+    assign wSAxisRqTUser[7:4] = wTxrPkt[(`UPKT_TXR_LBE_I % C_PCI_DATA_WIDTH) +: `UPKT_TXR_LBE_W];
+
+    assign wSAxisRqTUser[`SIG_RQ_TUSER_W-1:8] = 0;
+    
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                         (C_INPUT_STAGES),
+          .C_WIDTH                         (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))),
+          .C_USE_MEMORY                    (0)
+          /*AUTOINSTPARAM*/)
+    input_inst
+        (
+         // Outputs
+         .WR_DATA_READY                  (TXR_PKT_READY),
+         .RD_DATA                        ({wTxrPkt,wTxrPktStartFlag,wTxrPktStartOffset,wTxrPktEndFlag,wTxrPktEndOffset}),
+         .RD_DATA_VALID                  (wTxrPktValid),
+         // Inputs
+         .WR_DATA                        ({TXR_PKT,TXR_PKT_START_FLAG,TXR_PKT_START_OFFSET,
+                                           TXR_PKT_END_FLAG,TXR_PKT_END_OFFSET}),
+         .WR_DATA_VALID                  (TXR_PKT_VALID),
+         .RD_DATA_READY                  (wTxrPktReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+
+    offset_to_mask
+        #(
+          // Parameters
+          .C_MASK_SWAP                  (0),
+          .C_MASK_WIDTH                 (C_PCI_DATA_WIDTH/32)
+          /*AUTOINSTPARAM*/)
+    otom_inst
+        (
+         // Outputs
+         .MASK                          (_wSAxisRqTKeep),
+         // Inputs
+         .OFFSET_ENABLE                 (wTxrPktEndFlag),
+         .OFFSET                        (wTxrPktEndOffset)
+         /*AUTOINST*/);
+    
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                         (64/C_PCI_DATA_WIDTH),
+          .C_WIDTH                         (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)),
+          .C_USE_MEMORY                    (0)
+          /*AUTOINSTPARAM*/)
+    fbe_hack_inst
+        (
+         // Outputs
+         .WR_DATA_READY                  (_wSAxisRqTReady),
+         .RD_DATA                        ({wSAxisRqTData,wSAxisRqTLast,wSAxisRqTKeep}),
+         .RD_DATA_VALID                  (wSAxisRqTValid),
+         // Inputs
+         .WR_DATA                        ({_wSAxisRqTData,_wSAxisRqTLast,_wSAxisRqTKeep}),
+         .WR_DATA_VALID                  (_wSAxisRqTValid),
+         .RD_DATA_READY                  (wSAxisRqTReady),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+    pipeline
+        #(
+          // Parameters
+          .C_DEPTH                         (C_OUTPUT_STAGES),
+          .C_WIDTH                         (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32) + `SIG_RQ_TUSER_W),
+          .C_USE_MEMORY                    (0)
+          /*AUTOINSTPARAM*/)
+    output_inst
+        (
+         // Outputs
+         .WR_DATA_READY                  (wSAxisRqTReady),
+         .RD_DATA                        ({S_AXIS_RQ_TDATA,S_AXIS_RQ_TLAST,S_AXIS_RQ_TKEEP,S_AXIS_RQ_TUSER}),
+         .RD_DATA_VALID                  (S_AXIS_RQ_TVALID),
+         // Inputs
+         .WR_DATA                        ({wSAxisRqTData,wSAxisRqTLast,wSAxisRqTKeep,wSAxisRqTUser}),
+         .WR_DATA_VALID                  (wSAxisRqTValid),
+         .RD_DATA_READY                  (S_AXIS_RQ_TREADY),
+         /*AUTOINST*/
+         // Inputs
+         .CLK                           (CLK),
+         .RST_IN                        (RST_IN));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../common/" "../../common/")
+// End:
diff --git a/fpga/riffa_hdl/types.vh b/fpga/riffa_hdl/types.vh
new file mode 100644
index 0000000..3d09c37
--- /dev/null
+++ b/fpga/riffa_hdl/types.vh
@@ -0,0 +1,15 @@
+`ifndef __TYPES_VH
+`define __TYPES_VH 1
+
+`define TRLS_REQ_RD `EXT_TYPE_W'b000 
+`define TRLS_REQ_WR `EXT_TYPE_W'b001 
+`define TRLS_CPL_ND `EXT_TYPE_W'b010
+`define TRLS_CPL_WD `EXT_TYPE_W'b011
+`define TRLS_MSG_ND `EXT_TYPE_W'b100
+`define TRLS_MSG_WD `EXT_TYPE_W'b101
+
+`define TRLS_TYPE_PAY_I 0 // Payload Bit Index. If 1, packet has a payload, else 0
+`define TRLS_TYPE_CPL_I 1 // Completion Bit Index. If 1, packet is a Completion
+`define TRLS_TYPE_MSG_I 2 // Message Bit Index. If 1, packet is a message
+
+`endif
diff --git a/fpga/riffa_hdl/ultrascale.vh b/fpga/riffa_hdl/ultrascale.vh
new file mode 100644
index 0000000..7d2f8b6
--- /dev/null
+++ b/fpga/riffa_hdl/ultrascale.vh
@@ -0,0 +1,380 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            ultrascale.vh
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The ultrascale.vh file is a header file that defines
+// various AXI packet primitives for the Xilinx Gen3 PCIE interface
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+// TODO: STANDARDIZE NAMES
+// Ultrascale Request specific fields
+`ifndef __ULTRASCALE_VH
+`define __ULTRASCALE_VH 1
+`include "widths.vh"
+`include "types.vh"
+
+`define SIG_CQ_TUSER_W 85
+`define SIG_RC_TUSER_W 75
+`define SIG_CC_TUSER_W 33
+`define SIG_RQ_TUSER_W 60
+
+`define UPKT_ATYPE_W 2
+`define UPKT_ADDR_W 62
+`define UPKT_LEN_W (`LEN_W + 1)
+`define UPKT_TYPE_W 4
+`define UPKT_IDEN_W 1
+`define UPKT_TC_W `TC_W
+`define UPKT_ATTR_W 3
+`define UPKT_TARGET_FUNCTION_W 8
+`define UPKT_BARID_W 3
+`define UPKT_BARSIZE_W 6
+
+`define UPKT_RXC_MAXHDR_W 96
+`define UPKT_RXR_MAXHDR_W 128
+`define UPKT_TXC_MAXHDR_W 96
+`define UPKT_TXR_MAXHDR_W 128
+
+// TXR Defines
+`define UPKT_TXR_ATYPE_W `UPKT_ATYPE_W
+`define UPKT_TXR_ATYPE_I 0
+`define UPKT_TXR_ATYPE_R `UPKT_TXR_ATYPE_I +: `UPKT_TXR_ATYPE_W
+
+`define UPKT_TXR_ADDR_W `UPKT_ADDR_W
+`define UPKT_TXR_ADDR_I 2
+`define UPKT_TXR_ADDR_R `UPKT_TXR_ADDR_I +: `UPKT_TXR_ADDR_W
+
+`define UPKT_TXR_LENGTH_W `UPKT_LEN_W
+`define UPKT_TXR_LENGTH_I 64
+`define UPKT_TXR_LENGTH_R `UPKT_TXR_LENGTH_I +: `UPKT_TXR_LENGTH_W
+
+`define UPKT_TXR_TYPE_W `UPKT_TYPE_W
+`define UPKT_TXR_TYPE_I 75
+`define UPKT_TXR_TYPE_R `UPKT_TXR_TYPE_I +: `UPKT_TXR_TYPE_W
+
+`define UPKT_TXR_EP_W `EP_W 
+`define UPKT_TXR_EP_I 79
+`define UPKT_TXR_EP_R `UPKT_TXR_EP_I +: `UPKT_TXR_EP_W
+
+`define BE_HACK 1
+`ifndef BE_HACK
+
+`define UPKT_TXR_REQID_W `REQID_W
+`define UPKT_TXR_REQID_I 80
+`define UPKT_TXR_REQID_R `UPKT_TXR_REQID_I +: `UPKT_TXR_REQID_W
+
+`else 
+
+`define UPKT_TXR_FBE_W `FBE_W
+`define UPKT_TXR_FBE_I 80
+`define UPKT_TXR_FBE_R `UPKT_TXR_FBE_I +: `UPKT_TXR_FBE_W
+
+`define UPKT_TXR_LBE_W `LBE_W
+`define UPKT_TXR_LBE_I 84
+`define UPKT_TXR_LBE_R `UPKT_TXR_LBE_I +: `UPKT_TXR_LBE_W
+
+`define UPKT_TXR_RSVD0_W 8
+`define UPKT_TXR_RSVD0_I 88
+`define UPKT_TXR_RSVD0_R `UPKT_TXR_RSVD0_I +: `UPKT_TXR_RSVD0_W
+
+`endif
+
+`define UPKT_TXR_TAG_W `TAG_W
+`define UPKT_TXR_TAG_I 96
+`define UPKT_TXR_TAG_R `UPKT_TXR_TAG_I +: `UPKT_TXR_TAG_W
+
+`define UPKT_TXR_CPLID_W `CPLID_W
+`define UPKT_TXR_CPLID_I 104
+`define UPKT_TXR_CPLID_R `UPKT_TXR_CPLID_I +: `UPKT_TXR_CPLID_W
+
+`define UPKT_TXR_REQIDEN_W 1
+`define UPKT_TXR_REQIDEN_I 120
+`define UPKT_TXR_REQIDEN_R `UPKT_TXR_REQIDEN_I +: `UPKT_TXR_REQIDEN_W
+
+`define UPKT_TXR_TC_W `UPKT_TC_W
+`define UPKT_TXR_TC_I 121
+`define UPKT_TXR_TC_R `UPKT_TXR_TC_I +: `UPKT_TXR_TC_W
+
+`define UPKT_TXR_ATTR_W `UPKT_ATTR_W
+`define UPKT_TXR_ATTR_I 124
+`define UPKT_TXR_ATTR_R `UPKT_TXR_ATTR_I +: `UPKT_TXR_ATTR_W
+
+`define UPKT_TXR_TD_W `TD_W
+`define UPKT_TXR_TD_I 127
+`define UPKT_TXR_TD_R `UPKT_TXR_TD_I +: `UPKT_TXR_TD_W
+
+// RXR Defines
+`define UPKT_RXR_ATYPE_W `UPKT_ATYPE_W
+`define UPKT_RXR_ATYPE_I 0
+`define UPKT_RXR_ATYPE_R `UPKT_RXR_ATYPE_I +: `UPKT_RXR_ATYPE_W
+
+`define UPKT_RXR_ADDR_W `UPKT_ADDR_W
+`define UPKT_RXR_ADDR_I 2 
+`define UPKT_RXR_ADDR_R `UPKT_RXR_ADDR_I +: `UPKT_RXR_ADDR_W
+
+`define UPKT_RXR_LENGTH_W `UPKT_LEN_W
+`define UPKT_RXR_LENGTH_I 64
+`define UPKT_RXR_LENGTH_R `UPKT_RXR_LENGTH_I +: `UPKT_RXR_LENGTH_W
+
+`define UPKT_RXR_TYPE_W `UPKT_TYPE_W
+`define UPKT_RXR_TYPE_I 75
+`define UPKT_RXR_TYPE_R `UPKT_RXR_TYPE_I +: `UPKT_RXR_TYPE_W
+
+`define UPKT_RXR_EP_W `EP_W 
+`define UPKT_RXR_EP_I 79
+`define UPKT_RXR_EP_R `UPKT_RXR_EP_I +: `UPKT_RXR_EP_W
+
+`define UPKT_RXR_REQID_W `REQID_W
+`define UPKT_RXR_REQID_I 80
+`define UPKT_RXR_REQID_R `UPKT_RXR_REQID_I +: `UPKT_RXR_REQID_W
+
+`define UPKT_RXR_TAG_W `TAG_W
+`define UPKT_RXR_TAG_I 96
+`define UPKT_RXR_TAG_R `UPKT_RXR_TAG_I +: `UPKT_RXR_TAG_W
+
+`define UPKT_RXR_TGTFN_W `UPKT_TARGET_FUNCTION_W
+`define UPKT_RXR_TGTFN_I 104
+`define UPKT_RXR_TGTFN_R `UPKT_RXR_TGTFN_I +: `UPKT_RXR_TGTFN_W
+
+`define UPKT_RXR_BARID_W `UPKT_BARID_W
+`define UPKT_RXR_BARID_I 112
+`define UPKT_RXR_BARID_R `UPKT_RXR_BARID_I +: `UPKT_RXR_BARID_W
+
+`define UPKT_RXR_BARSIZE_W `UPKT_BARSIZE_W
+`define UPKT_RXR_BARSIZE_I 115
+`define UPKT_RXR_BARSIZE_R `UPKT_RXR_BARSIZE_I +: `UPKT_RXR_BARSIZE_W
+
+`define UPKT_RXR_TC_W `UPKT_TC_W
+`define UPKT_RXR_TC_I 121
+`define UPKT_RXR_TC_R `UPKT_RXR_TC_I +: `UPKT_RXR_TC_W
+
+`define UPKT_RXR_ATTR_W `UPKT_ATTR_W
+`define UPKT_RXR_ATTR_I 124
+`define UPKT_RXR_ATTR_R `UPKT_RXR_ATTR_I +: `UPKT_RXR_ATTR_W
+
+`define UPKT_RXR_TD_W `UPKT_TD_W
+`define UPKT_RXR_TD_I 127
+`define UPKT_RXR_TD_R `UPKT_RXR_TD_I +: `UPKT_RXR_TD_W
+
+`define UPKT_RXR_ADDRDW0_I 0
+`define UPKT_RXR_ADDRDW1_I 32
+`define UPKT_RXR_METADW0_I 64
+`define UPKT_RXR_METADW1_I 96
+`define UPKT_RXR_PAYLOAD_I 128
+
+// Indicies in M_AXIS_CQ_TUSER
+`define UPKT_CQ_TUSER_SOP_I 40
+`define UPKT_CQ_TUSER_SOP_W 1
+`define UPKT_CQ_TUSER_SOP_R `UPKT_CQ_TUSER_SOP_I +: `UPKT_CQ_TUSER_SOP_W
+
+`define UPKT_CQ_TUSER_BE_I 0
+`define UPKT_CQ_TUSER_BE_W 8
+`define UPKT_CQ_TUSER_BE_R `UPKT_CQ_TUSER_BE_I +: `UPKT_CQ_TUSER_BE_W
+
+// RXC Fields
+`define UPKT_RXC_ADDRLOW_W 12 // BYTE ADDRESS!!!
+`define UPKT_RXC_ADDRLOW_I 0
+`define UPKT_RXC_ADDRLOW_R `UPKT_RXC_ADDRLOW_I +: `UPKT_RXC_ADDRLOW_W
+
+`define UPKT_RXC_ERRCODE_W 4
+`define UPKT_RXC_ERRCODE_I 12
+`define UPKT_RXC_ERRCODE_R `UPKT_RXC_ERRCODE_I +: `UPKT_RXC_ERRCODE_W
+
+`define UPKT_RXC_BYTECNT_W 13
+`define UPKT_RXC_BYTECNT_I 16
+`define UPKT_RXC_BYTECNT_R `UPKT_RXC_BYTECNT_I +: `UPKT_RXC_BYTECNT_W
+
+`define UPKT_RXC_LOCKED_W 1 // Same as Type[0]
+`define UPKT_RXC_LOCKED_I 29
+`define UPKT_RXC_LOCKED_R `UPKT_RXC_LOCKED_I +: `UPKT_RXC_LOCKED_W
+
+`define UPKT_RXC_COMPLETE_W 1
+`define UPKT_RXC_COMPLETE_I 30
+`define UPKT_RXC_COMPLETE_R `UPKT_RXC_COMPLETE_I +: `UPKT_RXC_COMPLETE_W
+
+`define UPKT_RXC_LENGTH_W 11
+`define UPKT_RXC_LENGTH_I 32
+`define UPKT_RXC_LENGTH_R `UPKT_RXC_LENGTH_I +: `UPKT_RXC_LENGTH_W
+
+`define UPKT_RXC_STATUS_W 3
+`define UPKT_RXC_STATUS_I 43
+`define UPKT_RXC_STATUS_R `UPKT_RXC_STATUS_I +: `UPKT_RXC_STATUS_W
+
+`define UPKT_RXC_EP_W 1
+`define UPKT_RXC_EP_I 46
+`define UPKT_RXC_EP_R `UPKT_RXC_EP_I +: `UPKT_RXC_EP_W
+
+`define UPKT_RXC_REQID_W 16
+`define UPKT_RXC_REQID_I 48
+`define UPKT_RXC_REQID_R `UPKT_RXC_REQID_I +: `UPKT_RXC_REQID_W
+
+`define UPKT_RXC_TAG_W 8
+`define UPKT_RXC_TAG_I 64
+`define UPKT_RXC_TAG_R `UPKT_RXC_TAG_I +: `UPKT_RXC_TAG_W
+
+`define UPKT_RXC_CPLID_W 16
+`define UPKT_RXC_CPLID_I 72
+`define UPKT_RXC_CPLID_R `UPKT_RXC_CPLID_I +: `UPKT_RXC_CPLID_W
+
+`define UPKT_RXC_TC_W `UPKT_TC_W
+`define UPKT_RXC_TC_I 89
+`define UPKT_RXC_TC_R `UPKT_RXC_TC_I +: `UPKT_RXC_TC_W
+
+`define UPKT_RXC_ATTR_W 3
+`define UPKT_RXC_ATTR_I 92
+`define UPKT_RXC_ATTR_R `UPKT_RXC_ATTR_I +: `UPKT_RXC_ATTR_W
+
+`define UPKT_RXC_METADW0_I 0
+`define UPKT_RXC_METADW1_I 32
+`define UPKT_RXC_METADW2_I 64
+`define UPKT_RXC_PAYLOAD_I 96 // Payload DW0
+
+// Indicies in M_AXIS_RC_TUSER
+`define UPKT_RC_TUSER_SOP_I 32
+`define UPKT_RC_TUSER_SOP_W 1
+`define UPKT_RC_TUSER_SOP_R `UPKT_RC_TUSER_SOP_I +: `UPKT_RC_TUSER_SOP_W
+
+// TXC Defines
+`define UPKT_TXC_ADDRLOW_W 7
+`define UPKT_TXC_ADDRLOW_I 0
+`define UPKT_TXC_ADDRLOW_R `UPKT_TXC_ADDRLOW_I +: `UPKT_TXC_ADDRLOW_W
+
+`define UPKT_TXC_RSVD0_W 1
+`define UPKT_TXC_RSVD0_I 7
+`define UPKT_TXC_RSVD0_R `UPKT_TXC_RSVD0_I +: `UPKT_TXC_RSVD0_W
+
+`define UPKT_TXC_ATYPE_W 2
+`define UPKT_TXC_ATYPE_I 8
+`define UPKT_TXC_ATYPE_R `UPKT_TXC_ATYPE_I +: `UPKT_TXC_ATYPE_W
+
+`define UPKT_TXC_RSVD1_W 6
+`define UPKT_TXC_RSVD1_I 10
+`define UPKT_TXC_RSVD1_R `UPKT_TXC_RSVD1_I +: `UPKT_TXC_RSVD1_W
+
+`define UPKT_TXC_BYTECNT_W 13
+`define UPKT_TXC_BYTECNT_I 16
+`define UPKT_TXC_BYTECNT_R `UPKT_TXC_BYTECNT_I +: `UPKT_TXC_BYTECNT_W
+
+`define UPKT_TXC_LOCKED_W 1
+`define UPKT_TXC_LOCKED_I 29
+`define UPKT_TXC_LOCKED_R `UPKT_TXC_LOCKED_I +: `UPKT_TXC_LOCKED_W
+
+`define UPKT_TXC_RSVD2_W 2
+`define UPKT_TXC_RSVD2_I 30
+`define UPKT_TXC_RSVD2_R `UPKT_TXC_RSVD2_I +: `UPKT_TXC_RSVD2_W
+
+`define UPKT_TXC_LENGTH_W 11
+`define UPKT_TXC_LENGTH_I 32
+`define UPKT_TXC_LENGTH_R `UPKT_TXC_LENGTH_I +: `UPKT_TXC_LENGTH_W
+
+`define UPKT_TXC_STATUS_W 3
+`define UPKT_TXC_STATUS_I 43
+`define UPKT_TXC_STATUS_R `UPKT_TXC_STATUS_I +: `UPKT_TXC_STATUS_W
+
+`define UPKT_TXC_EP_W 1
+`define UPKT_TXC_EP_I 46
+`define UPKT_TXC_EP_R `UPKT_TXC_EP_I +: `UPKT_TXC_EP_W
+
+`define UPKT_TXC_RSVD3_W 1
+`define UPKT_TXC_RSVD3_I 47
+`define UPKT_TXC_RSVD3_R `UPKT_TXC_RSVD3_I +: `UPKT_TXC_RSVD3_W
+
+`define UPKT_TXC_REQID_W 16
+`define UPKT_TXC_REQID_I 48
+`define UPKT_TXC_REQID_R `UPKT_TXC_REQID_I +: `UPKT_TXC_REQID_W
+
+`define UPKT_TXC_TAG_W 8
+`define UPKT_TXC_TAG_I 64
+`define UPKT_TXC_TAG_R `UPKT_TXC_TAG_I +: `UPKT_TXC_TAG_W
+
+`define UPKT_TXC_CPLID_W 16
+`define UPKT_TXC_CPLID_I 72
+`define UPKT_TXC_CPLID_R `UPKT_TXC_CPLID_I +: `UPKT_TXC_CPLID_W
+
+`define UPKT_TXC_CPLIDEN_W 1
+`define UPKT_TXC_CPLIDEN_I 88
+`define UPKT_TXC_CPLIDEN_R `UPKT_TXC_CPLIDEN_I +: `UPKT_TXC_CPLIDEN_W
+
+`define UPKT_TXC_TC_W `UPKT_TC_W
+`define UPKT_TXC_TC_I 89
+`define UPKT_TXC_TC_R `UPKT_TXC_TC_I +: `UPKT_TXC_TC_W
+
+`define UPKT_TXC_ATTR_W 3
+`define UPKT_TXC_ATTR_I 92
+`define UPKT_TXC_ATTR_R `UPKT_TXC_ATTR_I +: `UPKT_RXC_ATTR_W
+
+`define UPKT_TXC_TD_W 1
+`define UPKT_TXC_TD_I 95
+`define UPKT_TXC_TD_R `UPKT_TXC_TD_I +: `UPKT_TXC_TD_W
+                         
+// Decoding the type field
+`define UPKT_REQ_RD 4'b0000
+`define UPKT_REQ_WR 4'b0001
+`define UPKT_MSG 4'b1100
+
+function [ `EXT_TYPE_W - 1: 0 ] upkt_to_trellis_type;
+    input [`UPKT_TYPE_W : 0 ] WR_UPKT_TYPE;
+    begin
+        /* verilator lint_off CASEX */
+        casex(WR_UPKT_TYPE)
+            {`UPKT_REQ_RD,1'bx}: upkt_to_trellis_type = `TRLS_REQ_RD;
+            {`UPKT_REQ_WR,1'bx}: upkt_to_trellis_type = `TRLS_REQ_WR;
+            {`UPKT_MSG   ,1'b0}: upkt_to_trellis_type = `TRLS_MSG_ND;
+            {`UPKT_MSG   ,1'b1}: upkt_to_trellis_type = `TRLS_MSG_WD;
+            default:             upkt_to_trellis_type = `TRLS_REQ_RD;
+        endcase
+        /* verilator lint_on CASEX */
+    end
+endfunction // if
+
+function [`UPKT_TYPE_W - 1 : 0 ] trellis_to_upkt_type;
+    input  [ `EXT_TYPE_W - 1 : 0 ] trellis_type;
+    begin
+        /* verilator lint_off CASEX */
+        casex(trellis_type)
+            `TRLS_REQ_RD : trellis_to_upkt_type = `UPKT_REQ_RD;
+            `TRLS_REQ_WR : trellis_to_upkt_type = `UPKT_REQ_WR;
+            `TRLS_MSG_ND : trellis_to_upkt_type = `UPKT_MSG; // We only use messages routed by address
+            `TRLS_MSG_WD : trellis_to_upkt_type = `UPKT_MSG; // We only use messages routed by address
+            default      : trellis_to_upkt_type = `UPKT_REQ_RD;
+        endcase
+        /* verilator lint_on CASEX */
+    end
+endfunction // if
+
+`endif
+
+
diff --git a/fpga/riffa_hdl/widths.vh b/fpga/riffa_hdl/widths.vh
new file mode 100644
index 0000000..3548e75
--- /dev/null
+++ b/fpga/riffa_hdl/widths.vh
@@ -0,0 +1,37 @@
+`ifndef __WIDTHS_VH
+`define __WIDTHS_VH 1
+
+`define LEN_W 10
+`define TD_W 1
+
+`define BARDECODE_W 8
+`define OFFSET_W 4
+`define EP_W 1
+`define TC_W 3
+`define TYPE_W 5
+`define ATTR_W 3
+`define FMT_W 3
+`define FBE_W 4
+`define LBE_W 4
+`define TAG_W 8
+`define ADDR_W 64
+`define REQID_W 16
+`define CPLID_W 16
+`define BYTECNT_W 12
+`define STAT_W 3
+`define LOWADDR_W 7
+
+`define EXT_TYPE_W 3
+
+`define LINKWIDTH_W 6
+`define LINKRATE_W 4
+`define MAXREAD_W 3
+`define MAXPAYLOAD_W 3
+
+`define PCIE_CONFIGURATION_REGISTER_WIDTH 16
+`define PCIE_BUS_ID_WIDTH 8
+`define PCIE_DEVICE_ID_WIDTH 5
+`define PCIE_FUNCTION_ID_WIDTH 3
+
+`endif
+
diff --git a/fpga/riffa_hdl/xilinx.vh b/fpga/riffa_hdl/xilinx.vh
new file mode 100644
index 0000000..11c538e
--- /dev/null
+++ b/fpga/riffa_hdl/xilinx.vh
@@ -0,0 +1,65 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            xilinx.vh
+// Version:             1.0
+// Verilog Standard:    Verilog-2001
+// Description:         The xilinx.vh file is a header file that defines
+// various Xilinx-specific primitives.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`ifndef __XILINX_VH
+`define __XILINX_VH 1
+
+`define SIG_XIL_TX_TUSER_W 4
+`define SIG_XIL_RX_TUSER_W 22
+
+`define SIG_FC_SEL_W 3 // Xilinx specific
+
+`define SIG_FC_SEL_RX_BUF_AVAIL_V 3'b000
+`define SIG_FC_SEL_RX_MAXALLOC_V 3'b001
+`define SIG_FC_SEL_RX_CONSUMED_V 3'b010
+`define SIG_FC_SEL_TX_CRED_AVAIL_V 3'b100
+`define SIG_FC_SEL_TX_MAXALLOC_V 3'b101
+`define SIG_FC_SEL_TX_CONSUMED_V 3'b110
+
+`define CFG_COMMAND_BUSMSTR_R 2
+`define CFG_LSTATUS_LWIDTH_R 9:4
+`define CFG_LSTATUS_LRATE_R 3:0
+`define CFG_DCOMMAND_MAXREQ_R 14:12
+`define CFG_DCOMMAND_MAXPAY_R 7:5
+`define CFG_LCOMMAND_RCB_R 3
+
+`endif
diff --git a/fpga/xilinx/vc707/VC707_Gen1x8If64/bit/VC707Gen1x8If64.bit b/fpga/xilinx/vc707/VC707_Gen1x8If64/bit/VC707Gen1x8If64.bit
new file mode 100644
index 0000000..3565ee2
Binary files /dev/null and b/fpga/xilinx/vc707/VC707_Gen1x8If64/bit/VC707Gen1x8If64.bit differ
diff --git a/fpga/xilinx/vc707/VC707_Gen1x8If64/constr/VC707_Top.xdc b/fpga/xilinx/vc707/VC707_Gen1x8If64/constr/VC707_Top.xdc
new file mode 100644
index 0000000..bd431f8
--- /dev/null
+++ b/fpga/xilinx/vc707/VC707_Gen1x8If64/constr/VC707_Top.xdc
@@ -0,0 +1,130 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            VC707_Top.xdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Xilinx Design Constraints for the VC707 board.
+# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin
+# 
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+#
+#########################################################################################################################
+# User Constraints
+#########################################################################################################################
+
+###############################################################################
+# User Time Names / User Time Groups / Time Specs
+###############################################################################
+
+###############################################################################
+# User Physical Constraints
+###############################################################################
+
+#
+# LED Status Indicators for Example Design.
+# LED 0-2 should be all ON if link is up and functioning correctly
+# LED 3 should be blinking if user application is receiving valid clock
+#
+
+#System Reset, User Reset, User Link Up, User Clk Heartbeat
+
+
+#########################################################################################################################
+# End User Constraints
+#########################################################################################################################
+#
+#
+#
+#########################################################################################################################
+# PCIE Core Constraints
+#########################################################################################################################
+
+#
+# SYS reset (input) signal.  The sys_reset_n signal should be
+# obtained from the PCI Express interface if possible.  For
+# slot based form factors, a system reset signal is usually
+# present on the connector.  For cable based form factors, a
+# system reset signal may not be available.  In this case, the
+# system reset signal must be generated locally by some form of
+# supervisory circuit.  You may change the IOSTANDARD and LOC
+# to suit your requirements and VCCO voltage banking rules.
+# Some 7 series devices do not have 3.3 V I/Os available.
+# Therefore the appropriate level shift is required to operate
+# with these devices that contain only 1.8 V banks.
+#
+
+set_property PACKAGE_PIN AV35 [get_ports PCIE_RESET_N]
+set_property IOSTANDARD LVCMOS18 [get_ports PCIE_RESET_N]
+set_property PULLUP true [get_ports PCIE_RESET_N]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}]
+
+set_property PACKAGE_PIN AM39 [get_ports {LED[0]}]
+set_property PACKAGE_PIN AN39 [get_ports {LED[1]}]
+set_property PACKAGE_PIN AR37 [get_ports {LED[2]}]
+set_property PACKAGE_PIN AT37 [get_ports {LED[3]}]
+
+set_false_path -to [get_ports -filter NAME=~LED*]
+#
+#
+# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
+# signals are the PCI Express reference clock. Virtex-7 GT
+# Transceiver architecture requires the use of a dedicated clock
+# resources (FPGA input pins) associated with each GT Transceiver.
+# To use these pins an IBUFDS primitive (refclk_ibuf) is
+# instantiated in user's design.
+# Please refer to the Virtex-7 GT Transceiver User Guide
+# (UG) for guidelines regarding clock resource selection.
+#
+set_property LOC IBUFDS_GTE2_X1Y5 [get_cells refclk_ibuf]
+
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O]
+
+###############################################################################
+# Physical Constraints
+###############################################################################
+
+set_false_path -from [get_ports PCIE_RESET_N]
+###############################################################################
+# End
+###############################################################################
diff --git a/fpga/xilinx/vc707/VC707_Gen1x8If64/hdl/VC707Gen1x8If64.v b/fpga/xilinx/vc707/VC707_Gen1x8If64/hdl/VC707Gen1x8If64.v
new file mode 100644
index 0000000..656765f
--- /dev/null
+++ b/fpga/xilinx/vc707/VC707_Gen1x8If64/hdl/VC707Gen1x8If64.v
@@ -0,0 +1,402 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            VC707Gen1x8If64.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Xilinx VC707 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "tlp.vh"
+`include "xilinx.vh"
+`timescale 1ps / 1ps
+module VC707Gen1x8If64
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 12,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 64,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
+     output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXP,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXN,
+
+     output [3:0]                   LED,
+     input                          PCIE_REFCLK_P,
+     input                          PCIE_REFCLK_N,
+     input                          PCIE_RESET_N
+     );
+
+    wire                            pcie_refclk;
+    wire                            pcie_reset_n;
+
+    wire                            user_clk;
+    wire                            user_reset;
+    wire                            user_lnk_up;
+    wire                            user_app_rdy;
+    
+    wire                            s_axis_tx_tready;
+    wire [C_PCI_DATA_WIDTH-1 : 0]   s_axis_tx_tdata;
+    wire [(C_PCI_DATA_WIDTH/8)-1 : 0] s_axis_tx_tkeep;
+    wire                              s_axis_tx_tlast;
+    wire                              s_axis_tx_tvalid;
+    wire [`SIG_XIL_TX_TUSER_W : 0]    s_axis_tx_tuser;
+    
+    wire [C_PCI_DATA_WIDTH-1 : 0]     m_axis_rx_tdata;
+    wire [(C_PCI_DATA_WIDTH/8)-1 : 0] m_axis_rx_tkeep;
+    wire                              m_axis_rx_tlast;
+    wire                              m_axis_rx_tvalid;
+    wire                              m_axis_rx_tready;
+    wire [`SIG_XIL_RX_TUSER_W - 1 : 0] m_axis_rx_tuser;
+
+    wire                               tx_cfg_gnt;
+    wire                               rx_np_ok;
+    wire                               rx_np_req;
+    wire                               cfg_turnoff_ok;
+    wire                               cfg_trn_pending;
+    wire                               cfg_pm_halt_aspm_l0s;
+    wire                               cfg_pm_halt_aspm_l1;
+    wire                               cfg_pm_force_state_en;
+    wire [1:0]                         cfg_pm_force_state;
+    wire                               cfg_pm_wake;
+    wire [63:0]                        cfg_dsn;
+
+    wire [11 : 0]                      fc_cpld;
+    wire [7 : 0]                       fc_cplh;
+    wire [11 : 0]                      fc_npd;
+    wire [7 : 0]                       fc_nph;
+    wire [11 : 0]                      fc_pd;
+    wire [7 : 0]                       fc_ph;
+    wire [2 : 0]                       fc_sel;
+    
+    wire [15 : 0]                      cfg_status;
+    wire [15 : 0]                      cfg_command;
+    wire [15 : 0]                      cfg_dstatus;
+    wire [15 : 0]                      cfg_dcommand;
+    wire [15 : 0]                      cfg_lstatus;
+    wire [15 : 0]                      cfg_lcommand;
+    wire [15 : 0]                      cfg_dcommand2;
+    
+    wire [2 : 0]                       cfg_pcie_link_state;
+    wire                               cfg_pmcsr_pme_en;
+    wire [1 : 0]                       cfg_pmcsr_powerstate;
+    wire                               cfg_pmcsr_pme_status;
+    wire                               cfg_received_func_lvl_rst;
+    wire [4 : 0]                       cfg_pciecap_interrupt_msgnum;
+    wire                               cfg_to_turnoff;
+    wire [7 : 0]                       cfg_bus_number;
+    wire [4 : 0]                       cfg_device_number;
+    wire [2 : 0]                       cfg_function_number;
+
+    wire                               cfg_interrupt;
+    wire                               cfg_interrupt_rdy;
+    wire                               cfg_interrupt_assert;
+    wire [7 : 0]                       cfg_interrupt_di;
+    wire [7 : 0]                       cfg_interrupt_do;
+    wire [2 : 0]                       cfg_interrupt_mmenable;
+    wire                               cfg_interrupt_msienable;
+    wire                               cfg_interrupt_msixenable;
+    wire                               cfg_interrupt_msixfm;
+    wire                               cfg_interrupt_stat;
+    
+
+
+    wire                               rst_out;
+    wire [C_NUM_CHNL-1:0]              chnl_rx_clk; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx_ack; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_rx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_ren;
+
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_clk; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_tx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_ren;
+
+    genvar                                     chnl;
+
+    assign cfg_turnoff_ok = 0;
+    assign cfg_trn_pending = 0;
+    assign cfg_pm_halt_aspm_l0s = 0;
+    assign cfg_pm_halt_aspm_l1 = 0;
+    assign cfg_pm_force_state_en = 0;
+    assign cfg_pm_force_state = 0;
+    assign cfg_dsn = 0;
+    assign cfg_interrupt_assert = 0;
+    assign cfg_interrupt_di = 0;
+    assign cfg_interrupt_stat = 0;
+    assign cfg_pciecap_interrupt_msgnum = 0;
+    assign cfg_turnoff_ok = 0;
+    assign cfg_pm_wake = 0;
+
+    IBUF 
+        #()  
+    pci_reset_n_ibuf 
+        (.O(pcie_reset_n), 
+         .I(PCIE_RESET_N));
+
+    IBUFDS_GTE2 
+        #()
+    refclk_ibuf 
+        (.O(pcie_refclk), 
+         .ODIV2(), 
+         .I(PCIE_REFCLK_P), 
+         .CEB(1'b0), 
+         .IB(PCIE_REFCLK_N));
+
+    // Core Top Level Wrapper
+
+    PCIeGen1x8If64 PCIeGen1x8If64_i
+        (//---------------------------------------------------------------------
+         // PCI Express (pci_exp) Interface                                     
+         //---------------------------------------------------------------------
+         // Tx
+         .pci_exp_txn                               ( PCI_EXP_TXN ),
+         .pci_exp_txp                               ( PCI_EXP_TXP ),
+        
+         // Rx
+         .pci_exp_rxn                               ( PCI_EXP_RXN ),
+         .pci_exp_rxp                               ( PCI_EXP_RXP ),
+        
+         //---------------------------------------------------------------------
+         // AXI-S Interface                                                     
+         //---------------------------------------------------------------------
+         // Common
+         .user_clk_out                              ( user_clk ),
+         .user_reset_out                            ( user_reset ),
+         .user_lnk_up                               ( user_lnk_up ),
+         .user_app_rdy                              ( user_app_rdy ),
+        
+         // TX
+         .s_axis_tx_tready                          ( s_axis_tx_tready ),
+         .s_axis_tx_tdata                           ( s_axis_tx_tdata ),
+         .s_axis_tx_tkeep                           ( s_axis_tx_tkeep ),
+         .s_axis_tx_tuser                           ( s_axis_tx_tuser ),
+         .s_axis_tx_tlast                           ( s_axis_tx_tlast ),
+         .s_axis_tx_tvalid                          ( s_axis_tx_tvalid ),
+        
+         // Rx
+         .m_axis_rx_tdata                           ( m_axis_rx_tdata ),
+         .m_axis_rx_tkeep                           ( m_axis_rx_tkeep ),
+         .m_axis_rx_tlast                           ( m_axis_rx_tlast ),
+         .m_axis_rx_tvalid                          ( m_axis_rx_tvalid ),
+         .m_axis_rx_tready                          ( m_axis_rx_tready ),
+         .m_axis_rx_tuser                           ( m_axis_rx_tuser ),
+
+         .tx_cfg_gnt                                ( tx_cfg_gnt ),
+         .rx_np_ok                                  ( rx_np_ok ),
+         .rx_np_req                                 ( rx_np_req ),
+         .cfg_trn_pending                           ( cfg_trn_pending ),
+         .cfg_pm_halt_aspm_l0s                      ( cfg_pm_halt_aspm_l0s ),
+         .cfg_pm_halt_aspm_l1                       ( cfg_pm_halt_aspm_l1 ),
+         .cfg_pm_force_state_en                     ( cfg_pm_force_state_en ),
+         .cfg_pm_force_state                        ( cfg_pm_force_state ),
+         .cfg_dsn                                   ( cfg_dsn ),
+         .cfg_turnoff_ok                            ( cfg_turnoff_ok ),
+         .cfg_pm_wake                               ( cfg_pm_wake ),
+         .cfg_pm_send_pme_to                        ( 1'b0 ),
+         .cfg_ds_bus_number                         ( 8'b0 ),
+         .cfg_ds_device_number                      ( 5'b0 ),
+         .cfg_ds_function_number                    ( 3'b0 ),
+
+         //---------------------------------------------------------------------
+         // Flow Control Interface                                              
+         //---------------------------------------------------------------------
+         .fc_cpld                                   ( fc_cpld ),
+         .fc_cplh                                   ( fc_cplh ),
+         .fc_npd                                    ( fc_npd ),
+         .fc_nph                                    ( fc_nph ),
+         .fc_pd                                     ( fc_pd ),
+         .fc_ph                                     ( fc_ph ),
+         .fc_sel                                    ( fc_sel ),
+         
+         //---------------------------------------------------------------------
+         // Configuration (CFG) Interface                                       
+         //---------------------------------------------------------------------
+         .cfg_device_number                         ( cfg_device_number ),
+         .cfg_dcommand2                             ( cfg_dcommand2 ),
+         .cfg_pmcsr_pme_status                      ( cfg_pmcsr_pme_status ),
+         .cfg_status                                ( cfg_status ),
+         .cfg_to_turnoff                            ( cfg_to_turnoff ),
+         .cfg_received_func_lvl_rst                 ( cfg_received_func_lvl_rst ),
+         .cfg_dcommand                              ( cfg_dcommand ),
+         .cfg_bus_number                            ( cfg_bus_number ),
+         .cfg_function_number                       ( cfg_function_number ),
+         .cfg_command                               ( cfg_command ),
+         .cfg_dstatus                               ( cfg_dstatus ),
+         .cfg_lstatus                               ( cfg_lstatus ),
+         .cfg_pcie_link_state                       ( cfg_pcie_link_state ),
+         .cfg_lcommand                              ( cfg_lcommand ),
+         .cfg_pmcsr_pme_en                          ( cfg_pmcsr_pme_en ),
+         .cfg_pmcsr_powerstate                      ( cfg_pmcsr_powerstate ),
+         
+         //------------------------------------------------//
+         // EP Only                                        //
+         //------------------------------------------------//
+         .cfg_interrupt                             ( cfg_interrupt ),
+         .cfg_interrupt_rdy                         ( cfg_interrupt_rdy ),
+         .cfg_interrupt_assert                      ( cfg_interrupt_assert ),
+         .cfg_interrupt_di                          ( cfg_interrupt_di ),
+         .cfg_interrupt_do                          ( cfg_interrupt_do ),
+         .cfg_interrupt_mmenable                    ( cfg_interrupt_mmenable ),
+         .cfg_interrupt_msienable                   ( cfg_interrupt_msienable ),
+         .cfg_interrupt_msixenable                  ( cfg_interrupt_msixenable ),
+         .cfg_interrupt_msixfm                      ( cfg_interrupt_msixfm ),
+         .cfg_interrupt_stat                        ( cfg_interrupt_stat ),
+         .cfg_pciecap_interrupt_msgnum              ( cfg_pciecap_interrupt_msgnum ),
+         //---------------------------------------------------------------------
+         // System  (SYS) Interface                                             
+         //---------------------------------------------------------------------
+         .sys_clk                                    ( pcie_refclk ),
+         .sys_rst_n                                  ( pcie_reset_n )
+         
+         );
+
+
+    riffa_wrapper_vc707
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .CFG_INTERRUPT                 (cfg_interrupt),
+         .M_AXIS_RX_TREADY              (m_axis_rx_tready),
+         .S_AXIS_TX_TDATA               (s_axis_tx_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_TX_TKEEP               (s_axis_tx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .S_AXIS_TX_TLAST               (s_axis_tx_tlast),
+         .S_AXIS_TX_TVALID              (s_axis_tx_tvalid),
+         .S_AXIS_TX_TUSER               (s_axis_tx_tuser[`SIG_XIL_TX_TUSER_W-1:0]),
+         .FC_SEL                        (fc_sel[`SIG_FC_SEL_W-1:0]),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .M_AXIS_RX_TDATA               (m_axis_rx_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RX_TKEEP               (m_axis_rx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .M_AXIS_RX_TLAST               (m_axis_rx_tlast),
+         .M_AXIS_RX_TVALID              (m_axis_rx_tvalid),
+         .M_AXIS_RX_TUSER               (m_axis_rx_tuser[`SIG_XIL_RX_TUSER_W-1:0]),
+         .S_AXIS_TX_TREADY              (s_axis_tx_tready),
+         .CFG_BUS_NUMBER                (cfg_bus_number[`SIG_BUSID_W-1:0]),
+         .CFG_DEVICE_NUMBER             (cfg_device_number[`SIG_DEVID_W-1:0]),
+         .CFG_FUNCTION_NUMBER           (cfg_function_number[`SIG_FNID_W-1:0]),
+         .CFG_COMMAND                   (cfg_command[`SIG_CFGREG_W-1:0]),
+         .CFG_DCOMMAND                  (cfg_dcommand[`SIG_CFGREG_W-1:0]),
+         .CFG_LSTATUS                   (cfg_lstatus[`SIG_CFGREG_W-1:0]),
+         .CFG_LCOMMAND                  (cfg_lcommand[`SIG_CFGREG_W-1:0]),
+         .FC_CPLD                       (fc_cpld[`SIG_FC_CPLD_W-1:0]),
+         .FC_CPLH                       (fc_cplh[`SIG_FC_CPLH_W-1:0]),
+         .CFG_INTERRUPT_MSIEN           (cfg_interrupt_msienable),// TODO: Rename
+         .CFG_INTERRUPT_RDY             (cfg_interrupt_rdy),
+         .USER_CLK                      (user_clk),
+         .USER_RESET                    (user_reset),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]),
+         .RX_NP_OK                      (rx_np_ok),
+         .TX_CFG_GNT                    (tx_cfg_gnt),
+         .RX_NP_REQ                     (rx_np_req)
+         /*AUTOINST*/);
+
+    generate
+        for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
+            chnl_tester 
+                    #(
+                      .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                      ) 
+            module1 
+                    (.CLK(user_clk),
+                     .RST(rst_out),    // riffa_reset includes riffa_endpoint resets
+                     // Rx interface
+                     .CHNL_RX_CLK(chnl_rx_clk[chnl]), 
+                     .CHNL_RX(chnl_rx[chnl]), 
+                     .CHNL_RX_ACK(chnl_rx_ack[chnl]), 
+                     .CHNL_RX_LAST(chnl_rx_last[chnl]), 
+                     .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), 
+                     .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), 
+                     .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), 
+                     .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
+                     // Tx interface
+                     .CHNL_TX_CLK(chnl_tx_clk[chnl]), 
+                     .CHNL_TX(chnl_tx[chnl]), 
+                     .CHNL_TX_ACK(chnl_tx_ack[chnl]), 
+                     .CHNL_TX_LAST(chnl_tx_last[chnl]), 
+                     .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), 
+                     .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), 
+                     .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), 
+                     .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
+                     );    
+        end
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/" "../..")
+// End:
+
diff --git a/fpga/xilinx/vc707/VC707_Gen1x8If64/ip/PCIeGen1x8If64.xci b/fpga/xilinx/vc707/VC707_Gen1x8If64/ip/PCIeGen1x8If64.xci
new file mode 100644
index 0000000..f9e0926
--- /dev/null
+++ b/fpga/xilinx/vc707/VC707_Gen1x8If64/ip/PCIeGen1x8If64.xci
@@ -0,0 +1,479 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>PCIeGen1x8If64</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie_7x" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Advanced</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">PCIeGen1x8If64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_Port_Type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Maximum_Link_Width">X8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Link_Speed">2.5_GT/s</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Width">64_bit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.User_Clk_Freq">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IO_Base_Limit_Registers">Disabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Prefetchable_Memory_Base_Limit_Registers">Disabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Vendor_ID">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_ID">7018</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Revision_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Subsystem_Vendor_ID">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Subsystem_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Class_Code_Base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Class_Code_Sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Class_Code_Interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Base_Class_Menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Sub_Class_Interface_Menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cardbus_CIS_Pointer">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Cap_Slot_Implemented">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Max_Payload_Size">512_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Extended_Tag_Field">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Extended_Tag_Default">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phantom_Functions">No_function_number_bits_used</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Acceptable_L0s_Latency">Maximum_of_64_ns</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Acceptable_L1_Latency">No_limit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cpl_Finite">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cpl_Timeout_Disable_Sup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cpl_Timeout_Range">Range_B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Buf_Opt_BMA">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Perf_Level">High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dll_Link_Active_Cap">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RCB">64_byte</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Trgt_Link_Speed">4&apos;h1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Hw_Auton_Spd_Disable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.De_emph">-3.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Slot_Clock_Cfg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Root_Cap_CRS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Attn_Butn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Ctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_MRL">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Attn_Ind">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Ind">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_HotPlug_Surprise">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_HotPlug_Cap">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Elec_Interlock">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_No_Cmd_Comp_Sup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Limit_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Limit_Scale">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Physical_Slot_Num">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IntX_Generation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Legacy_Interrupt">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_64b">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Multiple_Message_Capable">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_Vec_Mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_Size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_Offset">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_PBA_Offset">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_Specific_Initialization">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3hot_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3cold_PME_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Soft_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DSN_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VC_Cap_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VC_Cap_Reject_Snoop">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VSEC_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCI_CFG_Space">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCI_CFG_Space_Addr">3F</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXT_PCI_CFG_Space">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXT_PCI_CFG_Space_Addr">3FF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Xlnx_Ref_Board">VC707</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Blk_Locn">X1Y0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Trans_Buf_Pipeline">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_unlock">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pme_to">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_cor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_nfl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_ftl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_inta">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pm_pme">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pme_to_ack">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Receive_NP_Request">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ACK_NAK_Timer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACK_NAK_Timeout_Func">Absolute</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACK_NAK_Timeout_Value">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Replay_Timer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Replay_Timeout_Func">Add</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Replay_Timeout_Value">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Lane_Reversal">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Upconfigure_Capable">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Force_No_Scrambling">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Tx_ASPM_L0s">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Downstream_Link_Num">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_INV_REQ">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_PRS_RESPONSE">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Silicon_Rev">GES_and_Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pcie_fast_config">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Debug_Ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Ref_Clk_Freq">100_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cost_Table">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_Atomic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ATOMICOP32_Completer_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ATOMICOP64_Completer_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CAS128_Completer_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TPH_Completer_Supported">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARI_Forwarding_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AtomicOp_Routing_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASPM_Optionality">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Check_Capable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Gen_Capable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Multiheader">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Permit_Root_Error_Update">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Correctable_Internal_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Header_Log_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Receiver_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Surprise_Down">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Flow_Control_Protocol_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Completion_Timeout">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Completer_Abort">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Receiver_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ACS_Violation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Uncorrectable_Internal_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_MC_Blocked_TLP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_AtomicOp_Egress_Blocked">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_TLP_Prefix_Blocked">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optional_Error_Support">000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Num">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR0_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR1_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR2_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR3_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR4_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR5_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECRC_Check">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECRC_Check_Trim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Rx_Poisoned_Resp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_gt_common">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
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new file mode 100644
index 0000000..7578571
--- /dev/null
+++ b/fpga/xilinx/vc707/VC707_Gen1x8If64/prj/VC707_Gen1x8If64.xpr
@@ -0,0 +1,785 @@
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+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxc_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel_32.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/txc_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/txc_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel_128.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue_output.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxr_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_multiplexer_64.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel_64.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxr_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/txr_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/txr_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/interrupt_controller.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue_input.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/riffa.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/registers.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/recv_credit_flow_ctrl.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rx_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/interrupt.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_multiplexer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rx_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/engine_layer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/xilinx.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/translation_xilinx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/riffa.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../riffa_wrapper_vc707.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/chnl_tester.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../hdl/VC707Gen1x8If64.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/altera.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="VC707Gen1x8If64"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../constr/VC707_Top.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/VC707_Top.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="VC707Gen1x8If64"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="PCIeGen1x8If64" Type="BlockSrcs" RelSrcDir="$PSRCDIR/PCIeGen1x8If64">
+      <File Path="$PPRDIR/../ip/PCIeGen1x8If64.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="PCIeGen1x8If64"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="9">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1761-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen1x8If64_synth_1" Type="Ft3:Synth" SrcSet="PCIeGen1x8If64" Part="xc7vx485tffg1761-2" ConstrsSet="PCIeGen1x8If64" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/PCIeGen1x8If64_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1761-2" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen1x8If64_impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1761-2" ConstrsSet="PCIeGen1x8If64" Description="Vivado Implementation Defaults" SynthRun="PCIeGen1x8If64_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+  </Runs>
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</Project>
diff --git a/fpga/xilinx/vc707/VC707_Gen2x8If128/bit/VC707Gen2x8If128.bit b/fpga/xilinx/vc707/VC707_Gen2x8If128/bit/VC707Gen2x8If128.bit
new file mode 100644
index 0000000..367de45
Binary files /dev/null and b/fpga/xilinx/vc707/VC707_Gen2x8If128/bit/VC707Gen2x8If128.bit differ
diff --git a/fpga/xilinx/vc707/VC707_Gen2x8If128/constr/VC707_Top.xdc b/fpga/xilinx/vc707/VC707_Gen2x8If128/constr/VC707_Top.xdc
new file mode 100644
index 0000000..877af1d
--- /dev/null
+++ b/fpga/xilinx/vc707/VC707_Gen2x8If128/constr/VC707_Top.xdc
@@ -0,0 +1,131 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            VC707_Top.xdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Xilinx Design Constraints for the VC707 board.
+# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin
+#
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+#
+#########################################################################################################################
+# User Constraints
+#########################################################################################################################
+
+###############################################################################
+# User Time Names / User Time Groups / Time Specs
+###############################################################################
+
+###############################################################################
+# User Physical Constraints
+###############################################################################
+
+#
+# LED Status Indicators for Example Design.
+# LED 0-2 should be all ON if link is up and functioning correctly
+# LED 3 should be blinking if user application is receiving valid clock
+#
+
+#System Reset, User Reset, User Link Up, User Clk Heartbeat
+
+
+#########################################################################################################################
+# End User Constraints
+#########################################################################################################################
+#
+#
+#
+#########################################################################################################################
+# PCIE Core Constraints
+#########################################################################################################################
+
+#
+# SYS reset (input) signal.  The sys_reset_n signal should be
+# obtained from the PCI Express interface if possible.  For
+# slot based form factors, a system reset signal is usually
+# present on the connector.  For cable based form factors, a
+# system reset signal may not be available.  In this case, the
+# system reset signal must be generated locally by some form of
+# supervisory circuit.  You may change the IOSTANDARD and LOC
+# to suit your requirements and VCCO voltage banking rules.
+# Some 7 series devices do not have 3.3 V I/Os available.
+# Therefore the appropriate level shift is required to operate
+# with these devices that contain only 1.8 V banks.
+#
+
+set_property PACKAGE_PIN AV35 [get_ports PCIE_RESET_N]
+set_property IOSTANDARD LVCMOS18 [get_ports PCIE_RESET_N]
+set_property PULLUP true [get_ports PCIE_RESET_N]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}]
+
+set_property PACKAGE_PIN AM39 [get_ports {LED[0]}]
+set_property PACKAGE_PIN AN39 [get_ports {LED[1]}]
+set_property PACKAGE_PIN AR37 [get_ports {LED[2]}]
+set_property PACKAGE_PIN AT37 [get_ports {LED[3]}]
+
+set_false_path -to [get_ports -filter NAME=~LED*]
+#
+#
+# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
+# signals are the PCI Express reference clock. Virtex-7 GT
+# Transceiver architecture requires the use of a dedicated clock
+# resources (FPGA input pins) associated with each GT Transceiver.
+# To use these pins an IBUFDS primitive (refclk_ibuf) is
+# instantiated in user's design.
+# Please refer to the Virtex-7 GT Transceiver User Guide
+# (UG) for guidelines regarding clock resource selection.
+#
+set_property LOC IBUFDS_GTE2_X1Y5 [get_cells refclk_ibuf]
+
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O]
+
+###############################################################################
+# Physical Constraints
+###############################################################################
+
+set_false_path -from [get_ports PCIE_RESET_N]
+###############################################################################
+# End
+###############################################################################
+
diff --git a/fpga/xilinx/vc707/VC707_Gen2x8If128/hdl/VC707Gen2x8If128.v b/fpga/xilinx/vc707/VC707_Gen2x8If128/hdl/VC707Gen2x8If128.v
new file mode 100644
index 0000000..bf6393f
--- /dev/null
+++ b/fpga/xilinx/vc707/VC707_Gen2x8If128/hdl/VC707Gen2x8If128.v
@@ -0,0 +1,401 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            VC707Gen2x8If128.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Xilinx VC707 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "tlp.vh"
+`include "xilinx.vh"
+`timescale 1ps / 1ps
+module VC707Gen2x8If128
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 12,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 6
+      )
+    (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
+     output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXP,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXN,
+
+     output [3:0]                   LED,
+     input                          PCIE_REFCLK_P,
+     input                          PCIE_REFCLK_N,
+     input                          PCIE_RESET_N
+     );
+
+    wire                            pcie_refclk;
+    wire                            pcie_reset_n;
+
+    wire                            user_clk;
+    wire                            user_reset;
+    wire                            user_lnk_up;
+    wire                            user_app_rdy;
+    
+    wire                            s_axis_tx_tready;
+    wire [C_PCI_DATA_WIDTH-1 : 0]   s_axis_tx_tdata;
+    wire [(C_PCI_DATA_WIDTH/8)-1 : 0] s_axis_tx_tkeep;
+    wire                              s_axis_tx_tlast;
+    wire                              s_axis_tx_tvalid;
+    wire [`SIG_XIL_TX_TUSER_W : 0]    s_axis_tx_tuser;
+    
+    wire [C_PCI_DATA_WIDTH-1 : 0]     m_axis_rx_tdata;
+    wire [(C_PCI_DATA_WIDTH/8)-1 : 0] m_axis_rx_tkeep;
+    wire                              m_axis_rx_tlast;
+    wire                              m_axis_rx_tvalid;
+    wire                              m_axis_rx_tready;
+    wire [`SIG_XIL_RX_TUSER_W - 1 : 0] m_axis_rx_tuser;
+
+    wire                               tx_cfg_gnt;
+    wire                               rx_np_ok;
+    wire                               rx_np_req;
+    wire                               cfg_turnoff_ok;
+    wire                               cfg_trn_pending;
+    wire                               cfg_pm_halt_aspm_l0s;
+    wire                               cfg_pm_halt_aspm_l1;
+    wire                               cfg_pm_force_state_en;
+    wire [1:0]                         cfg_pm_force_state;
+    wire                               cfg_pm_wake;
+    wire [63:0]                        cfg_dsn;
+
+    wire [11 : 0]                      fc_cpld;
+    wire [7 : 0]                       fc_cplh;
+    wire [11 : 0]                      fc_npd;
+    wire [7 : 0]                       fc_nph;
+    wire [11 : 0]                      fc_pd;
+    wire [7 : 0]                       fc_ph;
+    wire [2 : 0]                       fc_sel;
+    
+    wire [15 : 0]                      cfg_status;
+    wire [15 : 0]                      cfg_command;
+    wire [15 : 0]                      cfg_dstatus;
+    wire [15 : 0]                      cfg_dcommand;
+    wire [15 : 0]                      cfg_lstatus;
+    wire [15 : 0]                      cfg_lcommand;
+    wire [15 : 0]                      cfg_dcommand2;
+    
+    wire [2 : 0]                       cfg_pcie_link_state;
+    wire                               cfg_pmcsr_pme_en;
+    wire [1 : 0]                       cfg_pmcsr_powerstate;
+    wire                               cfg_pmcsr_pme_status;
+    wire                               cfg_received_func_lvl_rst;
+    wire [4 : 0]                       cfg_pciecap_interrupt_msgnum;
+    wire                               cfg_to_turnoff;
+    wire [7 : 0]                       cfg_bus_number;
+    wire [4 : 0]                       cfg_device_number;
+    wire [2 : 0]                       cfg_function_number;
+
+    wire                               cfg_interrupt;
+    wire                               cfg_interrupt_rdy;
+    wire                               cfg_interrupt_assert;
+    wire [7 : 0]                       cfg_interrupt_di;
+    wire [7 : 0]                       cfg_interrupt_do;
+    wire [2 : 0]                       cfg_interrupt_mmenable;
+    wire                               cfg_interrupt_msien;
+    wire                               cfg_interrupt_msixenable;
+    wire                               cfg_interrupt_msixfm;
+    wire                               cfg_interrupt_stat;
+    
+
+
+    wire                               rst_out;
+    wire [C_NUM_CHNL-1:0]              chnl_rx_clk; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx_ack; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_rx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_ren;
+
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_clk; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_tx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_ren;
+
+    genvar                                     chnl;
+
+    assign cfg_turnoff_ok = 0;
+    assign cfg_trn_pending = 0;
+    assign cfg_pm_halt_aspm_l0s = 0;
+    assign cfg_pm_halt_aspm_l1 = 0;
+    assign cfg_pm_force_state_en = 0;
+    assign cfg_pm_force_state = 0;
+    assign cfg_dsn = 0;
+    assign cfg_interrupt_assert = 0;
+    assign cfg_interrupt_di = 0;
+    assign cfg_interrupt_stat = 0;
+    assign cfg_pciecap_interrupt_msgnum = 0;
+    assign cfg_turnoff_ok = 0;
+    assign cfg_pm_wake = 0;
+
+    IBUF 
+        #()  
+    pci_reset_n_ibuf 
+        (.O(pcie_reset_n), 
+         .I(PCIE_RESET_N));
+
+    IBUFDS_GTE2 
+        #()
+    refclk_ibuf 
+        (.O(pcie_refclk), 
+         .ODIV2(), 
+         .I(PCIE_REFCLK_P), 
+         .CEB(1'b0), 
+         .IB(PCIE_REFCLK_N));
+
+    // Core Top Level Wrapper
+    PCIeGen2x8If128 PCIeGen2x8If128_i
+        (//---------------------------------------------------------------------
+         // PCI Express (pci_exp) Interface                                     
+         //---------------------------------------------------------------------
+         // Tx
+         .pci_exp_txn                               ( PCI_EXP_TXN ),
+         .pci_exp_txp                               ( PCI_EXP_TXP ),
+        
+         // Rx
+         .pci_exp_rxn                               ( PCI_EXP_RXN ),
+         .pci_exp_rxp                               ( PCI_EXP_RXP ),
+        
+         //---------------------------------------------------------------------
+         // AXI-S Interface                                                     
+         //---------------------------------------------------------------------
+         // Common
+         .user_clk_out                              ( user_clk ),
+         .user_reset_out                            ( user_reset ),
+         .user_lnk_up                               ( user_lnk_up ),
+         .user_app_rdy                              ( user_app_rdy ),
+        
+         // TX
+         .s_axis_tx_tready                          ( s_axis_tx_tready ),
+         .s_axis_tx_tdata                           ( s_axis_tx_tdata ),
+         .s_axis_tx_tkeep                           ( s_axis_tx_tkeep ),
+         .s_axis_tx_tuser                           ( s_axis_tx_tuser ),
+         .s_axis_tx_tlast                           ( s_axis_tx_tlast ),
+         .s_axis_tx_tvalid                          ( s_axis_tx_tvalid ),
+        
+         // Rx
+         .m_axis_rx_tdata                           ( m_axis_rx_tdata ),
+         .m_axis_rx_tkeep                           ( m_axis_rx_tkeep ),
+         .m_axis_rx_tlast                           ( m_axis_rx_tlast ),
+         .m_axis_rx_tvalid                          ( m_axis_rx_tvalid ),
+         .m_axis_rx_tready                          ( m_axis_rx_tready ),
+         .m_axis_rx_tuser                           ( m_axis_rx_tuser ),
+
+         .tx_cfg_gnt                                ( tx_cfg_gnt ),
+         .rx_np_ok                                  ( rx_np_ok ),
+         .rx_np_req                                 ( rx_np_req ),
+         .cfg_trn_pending                           ( cfg_trn_pending ),
+         .cfg_pm_halt_aspm_l0s                      ( cfg_pm_halt_aspm_l0s ),
+         .cfg_pm_halt_aspm_l1                       ( cfg_pm_halt_aspm_l1 ),
+         .cfg_pm_force_state_en                     ( cfg_pm_force_state_en ),
+         .cfg_pm_force_state                        ( cfg_pm_force_state ),
+         .cfg_dsn                                   ( cfg_dsn ),
+         .cfg_turnoff_ok                            ( cfg_turnoff_ok ),
+         .cfg_pm_wake                               ( cfg_pm_wake ),
+         .cfg_pm_send_pme_to                        ( 1'b0 ),
+         .cfg_ds_bus_number                         ( 8'b0 ),
+         .cfg_ds_device_number                      ( 5'b0 ),
+         .cfg_ds_function_number                    ( 3'b0 ),
+
+         //---------------------------------------------------------------------
+         // Flow Control Interface                                              
+         //---------------------------------------------------------------------
+         .fc_cpld                                   ( fc_cpld ),
+         .fc_cplh                                   ( fc_cplh ),
+         .fc_npd                                    ( fc_npd ),
+         .fc_nph                                    ( fc_nph ),
+         .fc_pd                                     ( fc_pd ),
+         .fc_ph                                     ( fc_ph ),
+         .fc_sel                                    ( fc_sel ),
+         
+         //---------------------------------------------------------------------
+         // Configuration (CFG) Interface                                       
+         //---------------------------------------------------------------------
+         .cfg_device_number                         ( cfg_device_number ),
+         .cfg_dcommand2                             ( cfg_dcommand2 ),
+         .cfg_pmcsr_pme_status                      ( cfg_pmcsr_pme_status ),
+         .cfg_status                                ( cfg_status ),
+         .cfg_to_turnoff                            ( cfg_to_turnoff ),
+         .cfg_received_func_lvl_rst                 ( cfg_received_func_lvl_rst ),
+         .cfg_dcommand                              ( cfg_dcommand ),
+         .cfg_bus_number                            ( cfg_bus_number ),
+         .cfg_function_number                       ( cfg_function_number ),
+         .cfg_command                               ( cfg_command ),
+         .cfg_dstatus                               ( cfg_dstatus ),
+         .cfg_lstatus                               ( cfg_lstatus ),
+         .cfg_pcie_link_state                       ( cfg_pcie_link_state ),
+         .cfg_lcommand                              ( cfg_lcommand ),
+         .cfg_pmcsr_pme_en                          ( cfg_pmcsr_pme_en ),
+         .cfg_pmcsr_powerstate                      ( cfg_pmcsr_powerstate ),
+         
+         //------------------------------------------------//
+         // EP Only                                        //
+         //------------------------------------------------//
+         .cfg_interrupt                             ( cfg_interrupt ),
+         .cfg_interrupt_rdy                         ( cfg_interrupt_rdy ),
+         .cfg_interrupt_assert                      ( cfg_interrupt_assert ),
+         .cfg_interrupt_di                          ( cfg_interrupt_di ),
+         .cfg_interrupt_do                          ( cfg_interrupt_do ),
+         .cfg_interrupt_mmenable                    ( cfg_interrupt_mmenable ),
+         .cfg_interrupt_msienable                   ( cfg_interrupt_msien ),
+         .cfg_interrupt_msixenable                  ( cfg_interrupt_msixenable ),
+         .cfg_interrupt_msixfm                      ( cfg_interrupt_msixfm ),
+         .cfg_interrupt_stat                        ( cfg_interrupt_stat ),
+         .cfg_pciecap_interrupt_msgnum              ( cfg_pciecap_interrupt_msgnum ),
+         //---------------------------------------------------------------------
+         // System  (SYS) Interface                                             
+         //---------------------------------------------------------------------
+         .sys_clk                                    ( pcie_refclk ),
+         .sys_rst_n                                  ( pcie_reset_n )
+         
+         );
+
+
+    riffa_wrapper_vc707
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .CFG_INTERRUPT                 (cfg_interrupt),
+         .M_AXIS_RX_TREADY              (m_axis_rx_tready),
+         .S_AXIS_TX_TDATA               (s_axis_tx_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_TX_TKEEP               (s_axis_tx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .S_AXIS_TX_TLAST               (s_axis_tx_tlast),
+         .S_AXIS_TX_TVALID              (s_axis_tx_tvalid),
+         .S_AXIS_TX_TUSER               (s_axis_tx_tuser[`SIG_XIL_TX_TUSER_W-1:0]),
+         .FC_SEL                        (fc_sel[`SIG_FC_SEL_W-1:0]),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .M_AXIS_RX_TDATA               (m_axis_rx_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RX_TKEEP               (m_axis_rx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .M_AXIS_RX_TLAST               (m_axis_rx_tlast),
+         .M_AXIS_RX_TVALID              (m_axis_rx_tvalid),
+         .M_AXIS_RX_TUSER               (m_axis_rx_tuser[`SIG_XIL_RX_TUSER_W-1:0]),
+         .S_AXIS_TX_TREADY              (s_axis_tx_tready),
+         .CFG_BUS_NUMBER                (cfg_bus_number[`SIG_BUSID_W-1:0]),
+         .CFG_DEVICE_NUMBER             (cfg_device_number[`SIG_DEVID_W-1:0]),
+         .CFG_FUNCTION_NUMBER           (cfg_function_number[`SIG_FNID_W-1:0]),
+         .CFG_COMMAND                   (cfg_command[`SIG_CFGREG_W-1:0]),
+         .CFG_DCOMMAND                  (cfg_dcommand[`SIG_CFGREG_W-1:0]),
+         .CFG_LSTATUS                   (cfg_lstatus[`SIG_CFGREG_W-1:0]),
+         .CFG_LCOMMAND                  (cfg_lcommand[`SIG_CFGREG_W-1:0]),
+         .FC_CPLD                       (fc_cpld[`SIG_FC_CPLD_W-1:0]),
+         .FC_CPLH                       (fc_cplh[`SIG_FC_CPLH_W-1:0]),
+         .CFG_INTERRUPT_MSIEN           (cfg_interrupt_msien),
+         .CFG_INTERRUPT_RDY             (cfg_interrupt_rdy),
+         .USER_CLK                      (user_clk),
+         .USER_RESET                    (user_reset),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]),
+         .RX_NP_OK                      (rx_np_ok),
+         .TX_CFG_GNT                    (tx_cfg_gnt),
+         .RX_NP_REQ                     (rx_np_req)
+         /*AUTOINST*/);
+
+    generate
+        for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
+            chnl_tester 
+                    #(
+                      .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                      ) 
+            module1 
+                    (.CLK(user_clk),
+                     .RST(rst_out),    // riffa_reset includes riffa_endpoint resets
+                     // Rx interface
+                     .CHNL_RX_CLK(chnl_rx_clk[chnl]), 
+                     .CHNL_RX(chnl_rx[chnl]), 
+                     .CHNL_RX_ACK(chnl_rx_ack[chnl]), 
+                     .CHNL_RX_LAST(chnl_rx_last[chnl]), 
+                     .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), 
+                     .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), 
+                     .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), 
+                     .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
+                     // Tx interface
+                     .CHNL_TX_CLK(chnl_tx_clk[chnl]), 
+                     .CHNL_TX(chnl_tx[chnl]), 
+                     .CHNL_TX_ACK(chnl_tx_ack[chnl]), 
+                     .CHNL_TX_LAST(chnl_tx_last[chnl]), 
+                     .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), 
+                     .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), 
+                     .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), 
+                     .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
+                     );    
+        end
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/" "../..")
+// End:
+
diff --git a/fpga/xilinx/vc707/VC707_Gen2x8If128/ip/PCIeGen2x8If128.xci b/fpga/xilinx/vc707/VC707_Gen2x8If128/ip/PCIeGen2x8If128.xci
new file mode 100644
index 0000000..84864a0
--- /dev/null
+++ b/fpga/xilinx/vc707/VC707_Gen2x8If128/ip/PCIeGen2x8If128.xci
@@ -0,0 +1,479 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>PCIeGen2x8If128</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie_7x" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Advanced</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">PCIeGen2x8If128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_Port_Type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Maximum_Link_Width">X8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Link_Speed">5.0_GT/s</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Width">128_bit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.User_Clk_Freq">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IO_Base_Limit_Registers">Disabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Prefetchable_Memory_Base_Limit_Registers">Disabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Vendor_ID">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_ID">7028</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Revision_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Subsystem_Vendor_ID">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Subsystem_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Class_Code_Base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Class_Code_Sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Class_Code_Interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Base_Class_Menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Sub_Class_Interface_Menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cardbus_CIS_Pointer">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Cap_Slot_Implemented">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Max_Payload_Size">256_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Extended_Tag_Field">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Extended_Tag_Default">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phantom_Functions">No_function_number_bits_used</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Acceptable_L0s_Latency">Maximum_of_64_ns</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Acceptable_L1_Latency">No_limit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cpl_Finite">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cpl_Timeout_Disable_Sup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cpl_Timeout_Range">Range_B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Buf_Opt_BMA">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Perf_Level">High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dll_Link_Active_Cap">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RCB">64_byte</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Trgt_Link_Speed">4&apos;h2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Hw_Auton_Spd_Disable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.De_emph">-3.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Slot_Clock_Cfg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Root_Cap_CRS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Attn_Butn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Ctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_MRL">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Attn_Ind">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Ind">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_HotPlug_Surprise">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_HotPlug_Cap">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Elec_Interlock">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_No_Cmd_Comp_Sup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Limit_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Limit_Scale">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Physical_Slot_Num">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IntX_Generation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Legacy_Interrupt">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_64b">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Multiple_Message_Capable">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_Vec_Mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_Size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_Offset">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_PBA_Offset">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_Specific_Initialization">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3hot_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3cold_PME_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Soft_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DSN_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VC_Cap_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VC_Cap_Reject_Snoop">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VSEC_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCI_CFG_Space">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCI_CFG_Space_Addr">3F</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXT_PCI_CFG_Space">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXT_PCI_CFG_Space_Addr">3FF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Xlnx_Ref_Board">VC707</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Blk_Locn">X1Y0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Trans_Buf_Pipeline">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_unlock">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pme_to">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_cor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_nfl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_ftl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_inta">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pm_pme">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pme_to_ack">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Receive_NP_Request">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ACK_NAK_Timer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACK_NAK_Timeout_Func">Absolute</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACK_NAK_Timeout_Value">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Replay_Timer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Replay_Timeout_Func">Add</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Replay_Timeout_Value">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Lane_Reversal">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Upconfigure_Capable">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Force_No_Scrambling">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Tx_ASPM_L0s">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Downstream_Link_Num">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_INV_REQ">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_PRS_RESPONSE">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Silicon_Rev">GES_and_Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pcie_fast_config">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Debug_Ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Ref_Clk_Freq">100_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cost_Table">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_Atomic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ATOMICOP32_Completer_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ATOMICOP64_Completer_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CAS128_Completer_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TPH_Completer_Supported">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARI_Forwarding_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AtomicOp_Routing_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASPM_Optionality">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Check_Capable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Gen_Capable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Multiheader">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Permit_Root_Error_Update">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Correctable_Internal_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Header_Log_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Receiver_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Surprise_Down">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Flow_Control_Protocol_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Completion_Timeout">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Completer_Abort">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Receiver_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ACS_Violation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Uncorrectable_Internal_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_MC_Blocked_TLP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_AtomicOp_Egress_Blocked">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_TLP_Prefix_Blocked">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optional_Error_Support">000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Num">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR0_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR1_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR2_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR3_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR4_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR5_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECRC_Check">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECRC_Check_Trim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Rx_Poisoned_Resp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_gt_common">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.shared_logic_in_core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pl_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_mgmt_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ctl_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_status_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rcv_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_fc_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.err_reporting_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_pipe_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_startup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_mode_sim">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">PCIeGen2x8If128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dev_port_type">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_dev_port_type">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_header_type">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_upstream_facing">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.max_lnk_wdt">001000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.max_lnk_spd">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gen1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pci_exp_int_freq">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_pcie_fast_config">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_0">FFFFFC00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_5">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.xrom_bar">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.cost_table">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ven_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dev_id">7028</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.rev_id">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.subsys_ven_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.subsys_id">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.class_code">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.cardbus_cis_ptr">00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_pcie_cap_slot_implemented">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_ll_ack_timeout_enable">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_ll_replay_timeout_enable">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_ll_replay_timeout_func">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_dis_lane_reverse">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_upconfig_capable">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_disable_tx_aspm_l0s">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_pcie_dbg_ports">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pci_exp_ref_freq">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xlnx_ref_board">VC707</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_ur_atomic">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_link_cap_aspm_optionality">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_aer_cap_on">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rbar_cap_on">FALSE</spirit:configurableElementValue>
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diff --git a/fpga/xilinx/vc707/VC707_Gen2x8If128/prj/VC707_Gen2x8If128.xpr b/fpga/xilinx/vc707/VC707_Gen2x8If128/prj/VC707_Gen2x8If128.xpr
new file mode 100644
index 0000000..1445ba4
--- /dev/null
+++ b/fpga/xilinx/vc707/VC707_Gen2x8If128/prj/VC707_Gen2x8If128.xpr
@@ -0,0 +1,785 @@
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+      <File Path="$PPRDIR/../../../../riffa_hdl/recv_credit_flow_ctrl.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rx_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/interrupt.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_multiplexer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rx_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/engine_layer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/xilinx.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/translation_xilinx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/riffa.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/chnl_tester.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../riffa_wrapper_vc707.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../hdl/VC707Gen2x8If128.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/altera.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="VC707Gen2x8If128"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../constr/VC707_Top.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/VC707_Top.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="VC707Gen2x8If128"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="PCIeGen2x8If128" Type="BlockSrcs" RelSrcDir="$PSRCDIR/PCIeGen2x8If128">
+      <File Path="$PPRDIR/../ip/PCIeGen2x8If128.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="PCIeGen2x8If128"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="9">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1761-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen2x8If128_synth_1" Type="Ft3:Synth" SrcSet="PCIeGen2x8If128" Part="xc7vx485tffg1761-2" ConstrsSet="PCIeGen2x8If128" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/PCIeGen2x8If128_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1761-2" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen2x8If128_impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1761-2" ConstrsSet="PCIeGen2x8If128" Description="Vivado Implementation Defaults" SynthRun="PCIeGen2x8If128_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+  </Runs>
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</Project>
diff --git a/fpga/xilinx/vc707/riffa_wrapper_vc707.v b/fpga/xilinx/vc707/riffa_wrapper_vc707.v
new file mode 100644
index 0000000..8ef15b4
--- /dev/null
+++ b/fpga/xilinx/vc707/riffa_wrapper_vc707.v
@@ -0,0 +1,635 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            riffa_wrapper_vc707.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         RIFFA wrapper for the VC707 Development board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "xilinx.vh"
+`include "ultrascale.vh"
+`include "functions.vh"
+`timescale 1ps / 1ps
+module riffa_wrapper_vc707
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Bit-Width from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      // 4-Byte Name for this FPGA
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     // Interface: Xilinx RX 
+     input [C_PCI_DATA_WIDTH-1:0]                 M_AXIS_RX_TDATA,
+     input [(C_PCI_DATA_WIDTH/8)-1:0]             M_AXIS_RX_TKEEP,
+     input                                        M_AXIS_RX_TLAST,
+     input                                        M_AXIS_RX_TVALID,
+     output                                       M_AXIS_RX_TREADY,
+     input [`SIG_XIL_RX_TUSER_W-1:0]              M_AXIS_RX_TUSER,
+     output                                       RX_NP_OK,
+     output                                       RX_NP_REQ,
+
+     // Interface: Xilinx TX
+     output [C_PCI_DATA_WIDTH-1:0]                S_AXIS_TX_TDATA,
+     output [(C_PCI_DATA_WIDTH/8)-1:0]            S_AXIS_TX_TKEEP,
+     output                                       S_AXIS_TX_TLAST,
+     output                                       S_AXIS_TX_TVALID,
+     input                                        S_AXIS_TX_TREADY,
+     output [`SIG_XIL_TX_TUSER_W-1:0]             S_AXIS_TX_TUSER,
+     output                                       TX_CFG_GNT,
+
+     // Interface: Xilinx Configuration 
+     input [`SIG_BUSID_W-1:0]                     CFG_BUS_NUMBER,
+     input [`SIG_DEVID_W-1:0]                     CFG_DEVICE_NUMBER,
+     input [`SIG_FNID_W-1:0]                      CFG_FUNCTION_NUMBER,
+     input [`SIG_CFGREG_W-1:0]                    CFG_COMMAND,
+     input [`SIG_CFGREG_W-1:0]                    CFG_DCOMMAND,
+     input [`SIG_CFGREG_W-1:0]                    CFG_LSTATUS,
+     input [`SIG_CFGREG_W-1:0]                    CFG_LCOMMAND,
+
+     // Interface: Xilinx Flow Control
+     input [`SIG_FC_CPLD_W-1:0]                   FC_CPLD,
+     input [`SIG_FC_CPLH_W-1:0]                   FC_CPLH,
+     output [`SIG_FC_SEL_W-1:0]                   FC_SEL,
+    
+     // Interface: Xilinx Interrupt
+     input                                        CFG_INTERRUPT_MSIEN,
+     input                                        CFG_INTERRUPT_RDY,
+     output                                       CFG_INTERRUPT,
+
+     input                                        USER_CLK,
+     input                                        USER_RESET,
+    
+     // RIFFA Interface Signals
+     output                                       RST_OUT,
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_CLK, // Channel read clock
+     output [C_NUM_CHNL-1:0]                      CHNL_RX, // Channel read receive signal
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_ACK, // Channel read received signal
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_LAST, // Channel last read
+     output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
+     output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
+     output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   CHNL_RX_DATA, // Channel read data
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_DATA_VALID, // Channel read data valid
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_DATA_REN, // Channel read data has been recieved
+
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_CLK, // Channel write clock
+     input [C_NUM_CHNL-1:0]                       CHNL_TX, // Channel write receive signal
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_ACK, // Channel write acknowledgement signal
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_LAST, // Channel last write
+     input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]  CHNL_TX_LEN, // Channel write length (in 32 bit words)
+     input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]  CHNL_TX_OFF, // Channel write offset
+     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]    CHNL_TX_DATA, // Channel write data
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_DATA_VALID, // Channel write data valid
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_DATA_REN // Channel write data has been recieved
+
+     );
+    localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
+    localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
+    // ALTERA, XILINX or ULTRASCALE
+    localparam C_VENDOR = "XILINX";
+
+    localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
+    localparam C_PIPELINE_OUTPUT = 1;
+    localparam C_PIPELINE_INPUT = 1;
+    localparam C_DEPTH_PACKETS = 10;
+
+    wire                                          clk;
+    wire                                          rst_in;
+
+    // Interface: RXC Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxc_data;
+    wire                                          rxc_data_valid;
+    wire                                          rxc_data_start_flag;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxc_data_word_enable;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxc_meta_fdwbe;
+    wire                                          rxc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxc_meta_ldwbe;
+    wire [`SIG_TAG_W-1:0]                         rxc_meta_tag;
+    wire [`SIG_LOWADDR_W-1:0]                     rxc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        rxc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         rxc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     rxc_meta_bytes_remaining;
+    wire [`SIG_CPLID_W-1:0]                       rxc_meta_completer_id;
+    wire                                          rxc_meta_ep;
+
+    // Interface: RXR Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxr_data;
+    wire                                          rxr_data_valid;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxr_data_word_enable;
+    wire                                          rxr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxr_meta_fdwbe;
+    wire                                          rxr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxr_meta_ldwbe;
+    wire [`SIG_TC_W-1:0]                          rxr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        rxr_meta_attr;
+    wire [`SIG_TAG_W-1:0]                         rxr_meta_tag;
+    wire [`SIG_TYPE_W-1:0]                        rxr_meta_type;
+    wire [`SIG_ADDR_W-1:0]                        rxr_meta_addr;
+    wire [`SIG_BARDECODE_W-1:0]                   rxr_meta_bar_decoded;
+    wire [`SIG_REQID_W-1:0]                       rxr_meta_requester_id;
+    wire [`SIG_LEN_W-1:0]                         rxr_meta_length;
+    wire                                          rxr_meta_ep;
+    
+    // interface: TXC Engine
+    wire                                          txc_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txc_data;
+    wire                                          txc_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_start_offset;
+    wire                                          txc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_end_offset;
+    wire                                          txc_data_ready;
+
+    wire                                          txc_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txc_meta_fdwbe;
+    wire [`SIG_LBE_W-1:0]                         txc_meta_ldwbe;
+    wire [`SIG_LOWADDR_W-1:0]                     txc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        txc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         txc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     txc_meta_byte_count;
+    wire [`SIG_TAG_W-1:0]                         txc_meta_tag;
+    wire [`SIG_REQID_W-1:0]                       txc_meta_requester_id;
+    wire [`SIG_TC_W-1:0]                          txc_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txc_meta_attr;
+    wire                                          txc_meta_ep;
+    wire                                          txc_meta_ready;
+    wire                                          txc_sent;
+
+    // Interface: TXR Engine
+    wire                                          txr_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txr_data;
+    wire                                          txr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_start_offset;
+    wire                                          txr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_end_offset;
+    wire                                          txr_data_ready;
+
+    wire                                          txr_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txr_meta_fdwbe; 
+    wire [`SIG_LBE_W-1:0]                         txr_meta_ldwbe;
+    wire [`SIG_ADDR_W-1:0]                        txr_meta_addr;
+    wire [`SIG_LEN_W-1:0]                         txr_meta_length;
+    wire [`SIG_TAG_W-1:0]                         txr_meta_tag;
+    wire [`SIG_TC_W-1:0]                          txr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txr_meta_attr;
+    wire [`SIG_TYPE_W-1:0]                        txr_meta_type;
+    wire                                          txr_meta_ep;
+    wire                                          txr_meta_ready;
+    wire                                          txr_sent;
+
+    // Classic Interface Wires
+    wire                                          rx_tlp_ready;
+    wire [C_PCI_DATA_WIDTH-1:0]                   rx_tlp;
+    wire                                          rx_tlp_end_flag;
+    wire [`SIG_OFFSET_W-1:0]                      rx_tlp_end_offset;
+    wire                                          rx_tlp_start_flag;
+    wire [`SIG_OFFSET_W-1:0]                      rx_tlp_start_offset;
+    wire                                          rx_tlp_valid;
+    wire [`SIG_BARDECODE_W-1:0]                   rx_tlp_bar_decode;
+    
+    wire                                          tx_tlp_ready;
+    wire [C_PCI_DATA_WIDTH-1:0]                   tx_tlp;
+    wire                                          tx_tlp_end_flag;
+    wire [`SIG_OFFSET_W-1:0]                      tx_tlp_end_offset;
+    wire                                          tx_tlp_start_flag;
+    wire [`SIG_OFFSET_W-1:0]                      tx_tlp_start_offset;
+    wire                                          tx_tlp_valid;
+    
+    // Unconnected Wires (Used in ultrascale interface)
+    // Interface: RQ (TXC)
+    wire                                          s_axis_rq_tlast_nc;
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_rq_tdata_nc;
+    wire [`SIG_RQ_TUSER_W-1:0]                    s_axis_rq_tuser_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_rq_tkeep_nc;
+    wire                                          s_axis_rq_tready_nc = 0;
+    wire                                          s_axis_rq_tvalid_nc;
+    // Interface: RC (RXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_rc_tdata_nc = 0;
+    wire [`SIG_RC_TUSER_W-1:0]                    m_axis_rc_tuser_nc = 0;
+    wire                                          m_axis_rc_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_rc_tkeep_nc = 0;
+    wire                                          m_axis_rc_tvalid_nc = 0;
+    wire                                          m_axis_rc_tready_nc;
+    // Interface: CQ (RXR)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_cq_tdata_nc = 0;
+    wire [`SIG_CQ_TUSER_W-1:0]                    m_axis_cq_tuser_nc = 0;
+    wire                                          m_axis_cq_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_cq_tkeep_nc = 0;
+    wire                                          m_axis_cq_tvalid_nc = 0;
+    wire                                          m_axis_cq_tready_nc = 0;
+    // Interface: CC (TXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_cc_tdata_nc;
+    wire [`SIG_CC_TUSER_W-1:0]                    s_axis_cc_tuser_nc;
+    wire                                          s_axis_cc_tlast_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_cc_tkeep_nc;
+    wire                                          s_axis_cc_tvalid_nc;
+    wire                                          s_axis_cc_tready_nc = 0;
+
+    // Interface: Configuration
+    wire                                          config_bus_master_enable;
+    wire [`SIG_CPLID_W-1:0]                       config_completer_id;
+    wire                                          config_cpl_boundary_sel;
+    wire                                          config_interrupt_msienable;
+    wire [`SIG_LINKRATE_W-1:0]                    config_link_rate;
+    wire [`SIG_LINKWIDTH_W-1:0]                   config_link_width;
+    wire [`SIG_MAXPAYLOAD_W-1:0]                  config_max_payload_size;
+    wire [`SIG_MAXREAD_W-1:0]                     config_max_read_request_size;
+    wire [`SIG_FC_CPLD_W-1:0]                     config_max_cpl_data;
+    wire [`SIG_FC_CPLH_W-1:0]                     config_max_cpl_hdr;
+
+    wire                                          intr_msi_request;
+    wire                                          intr_msi_rdy;
+
+    genvar                                        chnl;
+
+    reg                                           rRxTlpValid;
+    reg                                           rRxTlpEndFlag;
+
+    assign clk = USER_CLK;
+    assign rst_in = USER_RESET;
+
+    translation_xilinx
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH))
+    trans
+        (
+         // Outputs
+         .RX_TLP                        (rx_tlp[C_PCI_DATA_WIDTH-1:0]),
+         .RX_TLP_VALID                  (rx_tlp_valid),
+         .RX_TLP_START_FLAG             (rx_tlp_start_flag),
+         .RX_TLP_START_OFFSET           (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RX_TLP_END_FLAG               (rx_tlp_end_flag),
+         .RX_TLP_END_OFFSET             (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RX_TLP_BAR_DECODE             (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]),
+         .TX_TLP_READY                  (tx_tlp_ready),
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE      (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH             (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE              (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE  (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE       (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE    (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL       (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA           (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR            (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+         .INTR_MSI_RDY                  (intr_msi_rdy),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+         .RX_TLP_READY                  (rx_tlp_ready),
+         .TX_TLP                        (tx_tlp[C_PCI_DATA_WIDTH-1:0]),
+         .TX_TLP_VALID                  (tx_tlp_valid),
+         .TX_TLP_START_FLAG             (tx_tlp_start_flag),
+         .TX_TLP_START_OFFSET           (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TX_TLP_END_FLAG               (tx_tlp_end_flag),
+         .TX_TLP_END_OFFSET             (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .INTR_MSI_REQUEST              (intr_msi_request),
+         /*AUTOINST*/
+         // Outputs
+         .M_AXIS_RX_TREADY              (M_AXIS_RX_TREADY),
+         .RX_NP_OK                      (RX_NP_OK),
+         .RX_NP_REQ                     (RX_NP_REQ),
+         .S_AXIS_TX_TDATA               (S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_TX_TKEEP               (S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .S_AXIS_TX_TLAST               (S_AXIS_TX_TLAST),
+         .S_AXIS_TX_TVALID              (S_AXIS_TX_TVALID),
+         .S_AXIS_TX_TUSER               (S_AXIS_TX_TUSER[`SIG_XIL_TX_TUSER_W-1:0]),
+         .TX_CFG_GNT                    (TX_CFG_GNT),
+         .FC_SEL                        (FC_SEL[`SIG_FC_SEL_W-1:0]),
+         .CFG_INTERRUPT                 (CFG_INTERRUPT),
+         // Inputs
+         .M_AXIS_RX_TDATA               (M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RX_TKEEP               (M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .M_AXIS_RX_TLAST               (M_AXIS_RX_TLAST),
+         .M_AXIS_RX_TVALID              (M_AXIS_RX_TVALID),
+         .M_AXIS_RX_TUSER               (M_AXIS_RX_TUSER[`SIG_XIL_RX_TUSER_W-1:0]),
+         .S_AXIS_TX_TREADY              (S_AXIS_TX_TREADY),
+         .CFG_BUS_NUMBER                (CFG_BUS_NUMBER[`SIG_BUSID_W-1:0]),
+         .CFG_DEVICE_NUMBER             (CFG_DEVICE_NUMBER[`SIG_DEVID_W-1:0]),
+         .CFG_FUNCTION_NUMBER           (CFG_FUNCTION_NUMBER[`SIG_FNID_W-1:0]),
+         .CFG_COMMAND                   (CFG_COMMAND[`SIG_CFGREG_W-1:0]),
+         .CFG_DCOMMAND                  (CFG_DCOMMAND[`SIG_CFGREG_W-1:0]),
+         .CFG_LSTATUS                   (CFG_LSTATUS[`SIG_CFGREG_W-1:0]),
+         .CFG_LCOMMAND                  (CFG_LCOMMAND[`SIG_CFGREG_W-1:0]),
+         .FC_CPLD                       (FC_CPLD[`SIG_FC_CPLD_W-1:0]),
+         .FC_CPLH                       (FC_CPLH[`SIG_FC_CPLH_W-1:0]),
+         .CFG_INTERRUPT_MSIEN           (CFG_INTERRUPT_MSIEN),
+         .CFG_INTERRUPT_RDY             (CFG_INTERRUPT_RDY));
+
+    engine_layer
+        #(// Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_BYTES/4),
+          .C_VENDOR                     (C_VENDOR))
+    engine_layer_inst
+        (// Outputs
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+         // Unconnected Outputs
+         .TX_TLP                        (tx_tlp),
+         .TX_TLP_VALID                  (tx_tlp_valid),
+         .TX_TLP_START_FLAG             (tx_tlp_start_flag),
+         .TX_TLP_START_OFFSET           (tx_tlp_start_offset),
+         .TX_TLP_END_FLAG               (tx_tlp_end_flag),
+         .TX_TLP_END_OFFSET             (tx_tlp_end_offset),
+
+         .RX_TLP_READY                  (rx_tlp_ready),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+         // Unconnected Inputs
+         .RX_TLP                        (rx_tlp),
+         .RX_TLP_VALID                  (rx_tlp_valid),
+         .RX_TLP_START_FLAG             (rx_tlp_start_flag),
+         .RX_TLP_START_OFFSET           (rx_tlp_start_offset),
+         .RX_TLP_END_FLAG               (rx_tlp_end_flag),
+         .RX_TLP_END_OFFSET             (rx_tlp_end_offset),
+         .RX_TLP_BAR_DECODE             (rx_tlp_bar_decode),
+
+         .TX_TLP_READY                  (tx_tlp_ready),
+         // Outputs
+         .M_AXIS_CQ_TREADY              (m_axis_cq_tready_nc),
+         .M_AXIS_RC_TREADY              (m_axis_rc_tready_nc),
+         .S_AXIS_CC_TVALID              (s_axis_cc_tvalid_nc),
+         .S_AXIS_CC_TLAST               (s_axis_cc_tlast_nc),
+         .S_AXIS_CC_TDATA               (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (s_axis_rq_tvalid_nc),
+         .S_AXIS_RQ_TLAST               (s_axis_rq_tlast_nc),
+         .S_AXIS_RQ_TDATA               (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (m_axis_cq_tvalid_nc),
+         .M_AXIS_CQ_TLAST               (m_axis_cq_tlast_nc),
+         .M_AXIS_CQ_TDATA               (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (m_axis_rc_tvalid_nc),
+         .M_AXIS_RC_TLAST               (m_axis_rc_tlast_nc),
+         .M_AXIS_RC_TDATA               (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (s_axis_cc_tready_nc),
+         .S_AXIS_RQ_TREADY              (s_axis_rq_tready_nc)
+         /*AUTOINST*/);
+
+    riffa
+        #(.C_TAG_WIDTH                  (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_MAX_READ_REQ_BYTES         (C_MAX_READ_REQ_BYTES),
+          .C_VENDOR                     (C_VENDOR),
+          .C_FPGA_NAME                  (C_FPGA_NAME),
+          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS))
+    riffa_inst
+        (// Outputs
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+
+         .INTR_MSI_REQUEST              (intr_msi_request),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),         
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE      (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH             (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE              (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE  (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE       (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE    (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL       (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA           (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR            (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+        
+         .INTR_MSI_RDY                  (intr_msi_rdy),
+
+         /*AUTOINST*/
+         // Outputs
+         .RST_OUT                       (RST_OUT),
+         .CHNL_RX                       (CHNL_RX[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_RX_OFF                   (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_RX_DATA                  (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
+         // Inputs
+         .CHNL_RX_CLK                   (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (CHNL_TX[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_TX_OFF                   (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_TX_DATA                  (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("../../engine/" "../../riffa/")
+// End:
diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64/bit/VC709Gen1x8If64.bit b/fpga/xilinx/vc709/VC709_Gen1x8If64/bit/VC709Gen1x8If64.bit
new file mode 100644
index 0000000..df8ff40
Binary files /dev/null and b/fpga/xilinx/vc709/VC709_Gen1x8If64/bit/VC709Gen1x8If64.bit differ
diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64/constr/VC709_Top.xdc b/fpga/xilinx/vc709/VC709_Gen1x8If64/constr/VC709_Top.xdc
new file mode 100644
index 0000000..36212f7
--- /dev/null
+++ b/fpga/xilinx/vc709/VC709_Gen1x8If64/constr/VC709_Top.xdc
@@ -0,0 +1,137 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            VC709_Top.xdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Xilinx Design Constraints for the VC709 board.
+# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin
+# 
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+#
+#########################################################################################################################
+# User Constraints
+#########################################################################################################################
+
+###############################################################################
+# User Time Names / User Time Groups / Time Specs
+###############################################################################
+
+###############################################################################
+# User Physical Constraints
+###############################################################################
+
+#
+# LED Status Indicators for Example Design.
+# LED 0-2 should be all ON if link is up and functioning correctly
+# LED 3 should be blinking if user application is receiving valid clock
+#
+
+#System Reset, User Reset, User Link Up, User Clk Heartbeat
+set_property PACKAGE_PIN AM39 [get_ports {LED[0]}]
+set_property PACKAGE_PIN AN39 [get_ports {LED[1]}]
+set_property PACKAGE_PIN AR37 [get_ports {LED[2]}]
+set_property PACKAGE_PIN AT37 [get_ports {LED[3]}]
+set_property PACKAGE_PIN AR35 [get_ports {LED[4]}]
+set_property PACKAGE_PIN AP41 [get_ports {LED[5]}]
+set_property PACKAGE_PIN AP42 [get_ports {LED[6]}]
+set_property PACKAGE_PIN AU39 [get_ports {LED[7]}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[7]}]
+
+set_false_path -to [get_ports -filter NAME=~LED*]
+
+#########################################################################################################################
+# End User Constraints
+#########################################################################################################################
+#
+#
+#
+#########################################################################################################################
+# PCIE Core Constraints
+#########################################################################################################################
+
+#
+# SYS reset (input) signal.  The sys_reset_n signal should be
+# obtained from the PCI Express interface if possible.  For
+# slot based form factors, a system reset signal is usually
+# present on the connector.  For cable based form factors, a
+# system reset signal may not be available.  In this case, the
+# system reset signal must be generated locally by some form of
+# supervisory circuit.  You may change the IOSTANDARD and LOC
+# to suit your requirements and VCCO voltage banking rules.
+# Some 7 series devices do not have 3.3 V I/Os available.
+# Therefore the appropriate level shift is required to operate
+# with these devices that contain only 1.8 V banks.
+#
+
+set_property PACKAGE_PIN AV35 [get_ports PCIE_RESET_N]
+set_property IOSTANDARD LVCMOS18 [get_ports PCIE_RESET_N]
+set_property PULLUP true [get_ports PCIE_RESET_N]
+
+#
+#
+# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
+# signals are the PCI Express reference clock. Virtex-7 GT
+# Transceiver architecture requires the use of a dedicated clock
+# resources (FPGA input pins) associated with each GT Transceiver.
+# To use these pins an IBUFDS primitive (refclk_ibuf) is
+# instantiated in user's design.
+# Please refer to the Virtex-7 GT Transceiver User Guide
+# (UG) for guidelines regarding clock resource selection.
+#
+set_property LOC IBUFDS_GTE2_X1Y11 [get_cells refclk_ibuf]
+
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O]
+
+###############################################################################
+# Physical Constraints
+###############################################################################
+
+set_false_path -from [get_ports PCIE_RESET_N]
+###############################################################################
+# End
+###############################################################################
diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64/hdl/VC709Gen1x8If64.v b/fpga/xilinx/vc709/VC709_Gen1x8If64/hdl/VC709Gen1x8If64.v
new file mode 100644
index 0000000..1774bf1
--- /dev/null
+++ b/fpga/xilinx/vc709/VC709_Gen1x8If64/hdl/VC709Gen1x8If64.v
@@ -0,0 +1,481 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            VC709Gen1x8If64.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Xilinx VC709 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "ultrascale.vh"
+`timescale 1ps / 1ps
+module VC709Gen1x8If64
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 12,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 64,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 6
+      ) 
+    (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
+     output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXP,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXN,
+
+     output [7:0]                   LED,
+     input                          PCIE_REFCLK_P,
+     input                          PCIE_REFCLK_N,
+     input                          PCIE_RESET_N
+     );
+
+    // Clocks, etc
+    wire                            user_lnk_up;
+    wire                            user_clk;
+    wire                            user_reset;
+    wire                            pcie_refclk;
+    wire                            pcie_reset_n;
+
+    // Interface: RQ (TXC)
+    wire                            s_axis_rq_tlast;
+    wire [C_PCI_DATA_WIDTH-1:0]     s_axis_rq_tdata;
+    wire [`SIG_RQ_TUSER_W-1:0]      s_axis_rq_tuser;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
+    wire                             s_axis_rq_tready;
+    wire                             s_axis_rq_tvalid;
+    // Interface: RC (RXC)
+    wire [C_PCI_DATA_WIDTH-1:0]      m_axis_rc_tdata;
+    wire [`SIG_RC_TUSER_W-1:0]       m_axis_rc_tuser;
+    wire                             m_axis_rc_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
+    wire                             m_axis_rc_tvalid;
+    wire                             m_axis_rc_tready;
+    // Interface: CQ (RXR)
+    wire [C_PCI_DATA_WIDTH-1:0]      m_axis_cq_tdata;
+    wire [`SIG_CQ_TUSER_W-1:0]       m_axis_cq_tuser;
+    wire                             m_axis_cq_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
+    wire                             m_axis_cq_tvalid;
+    wire                             m_axis_cq_tready;
+    // Interface: CC (TXC)
+    wire [C_PCI_DATA_WIDTH-1:0]      s_axis_cc_tdata;
+    wire [`SIG_CC_TUSER_W-1:0]       s_axis_cc_tuser;
+    wire                             s_axis_cc_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
+    wire                             s_axis_cc_tvalid;
+    wire                             s_axis_cc_tready;
+
+    // Configuration (CFG) Interface                                           
+    wire [3:0]                       pcie_rq_seq_num;
+    wire                             pcie_rq_seq_num_vld;
+    wire [5:0]                       pcie_rq_tag;
+    wire                             pcie_rq_tag_vld;
+    wire                             pcie_cq_np_req;
+    wire [5:0]                       pcie_cq_np_req_count;
+
+    wire                             cfg_phy_link_down;
+    wire [3:0]                       cfg_negotiated_width; // CONFIG_LINK_WIDTH
+    wire [2:0]                       cfg_current_speed; // CONFIG_LINK_RATE
+    wire [2:0]                       cfg_max_payload; // CONFIG_MAX_PAYLOAD
+    wire [2:0]                       cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
+    wire [7:0]                       cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
+    wire [5:0]                       cfg_function_power_state; // Ignorable but not removable
+    wire [11:0]                      cfg_vf_status; // Ignorable but not removable
+    wire [17:0]                      cfg_vf_power_state; // Ignorable but not removable
+    wire [1:0]                       cfg_link_power_state; // Ignorable but not removable
+
+    // Error Reporting Interface
+    wire                             cfg_err_cor_out;
+    wire                             cfg_err_nonfatal_out;
+    wire                             cfg_err_fatal_out;
+
+    wire                             cfg_ltr_enable;
+    wire [5:0]                       cfg_ltssm_state;// TODO: Connect to LED's
+    wire [1:0]                       cfg_rcb_status;
+    wire [1:0]                       cfg_dpa_substate_change;
+    wire [1:0]                       cfg_obff_enable;
+    wire                             cfg_pl_status_change;
+
+    wire [1:0]                       cfg_tph_requester_enable;
+    wire [5:0]                       cfg_tph_st_mode;
+    wire [5:0]                       cfg_vf_tph_requester_enable;
+    wire [17:0]                      cfg_vf_tph_st_mode;
+    wire [7:0]                       cfg_fc_ph;
+    wire [11:0]                      cfg_fc_pd;
+    wire [7:0]                       cfg_fc_nph;
+    wire [11:0]                      cfg_fc_npd;
+    wire [7:0]                       cfg_fc_cplh;
+    wire [11:0]                      cfg_fc_cpld;
+    wire [2:0]                       cfg_fc_sel;
+
+    // Interrupt Interface Signals
+    wire [3:0]                       cfg_interrupt_int;
+    wire [1:0]                       cfg_interrupt_pending;
+    wire                             cfg_interrupt_sent;
+    wire [1:0]                       cfg_interrupt_msi_enable;
+    wire [5:0]                       cfg_interrupt_msi_vf_enable;
+    wire [5:0]                       cfg_interrupt_msi_mmenable;
+    wire                             cfg_interrupt_msi_mask_update;
+    wire [31:0]                      cfg_interrupt_msi_data;
+    wire [3:0]                       cfg_interrupt_msi_select;
+    wire [31:0]                      cfg_interrupt_msi_int;
+    wire [63:0]                      cfg_interrupt_msi_pending_status;
+    wire                             cfg_interrupt_msi_sent;
+    wire                             cfg_interrupt_msi_fail;
+    wire [2:0]                       cfg_interrupt_msi_attr;
+    wire                             cfg_interrupt_msi_tph_present;
+    wire [1:0]                       cfg_interrupt_msi_tph_type;
+    wire [8:0]                       cfg_interrupt_msi_tph_st_tag;
+    wire [2:0]                       cfg_interrupt_msi_function_number;
+
+    wire                             rst_out;
+    wire [C_NUM_CHNL-1:0]            chnl_rx_clk; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx_ack; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_rx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_ren;
+
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_clk; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_tx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_ren;
+
+    genvar                                     chnl;
+
+    IBUF 
+        #()  
+    pci_reset_n_ibuf 
+        (.O(pcie_reset_n), 
+         .I(PCIE_RESET_N));
+
+    IBUFDS_GTE2 
+        #()
+    refclk_ibuf 
+        (.O(pcie_refclk), 
+         .ODIV2(), 
+         .I(PCIE_REFCLK_P), 
+         .CEB(1'b0), 
+         .IB(PCIE_REFCLK_N));
+
+    OBUF 
+        #() 
+    led_0_obuf 
+        (.O(LED[0]),
+         .I(cfg_ltssm_state[0]));
+    OBUF 
+        #() 
+    led_1_obuf 
+        (.O(LED[1]),
+         .I(cfg_ltssm_state[1]));
+    OBUF 
+        #() 
+    led_2_obuf 
+        (.O(LED[2]),
+         .I(cfg_ltssm_state[2]));
+    OBUF 
+        #() 
+    led_3_obuf 
+        (.O(LED[3]),
+         .I(cfg_ltssm_state[3]));
+    OBUF 
+        #() 
+    led_4_obuf 
+        (.O(LED[4]),
+         .I(cfg_ltssm_state[4]));
+    OBUF 
+        #() 
+    led_5_obuf 
+        (.O(LED[5]),
+         .I(cfg_ltssm_state[5]));
+    OBUF 
+        #() 
+    led_6_obuf 
+        (.O(LED[6]),
+         .I(pcie_reset_n));
+    OBUF 
+        #() 
+    led_7_obuf 
+        (.O(LED[7]),
+         .I(rst_out));
+
+    // Core Top Level Wrapper
+    PCIeGen1x8If64  
+        #()
+    pcie3_7x_0_i 
+        (//---------------------------------------------------------------------
+         //  PCI Express (pci_exp) Interface                                    
+         //---------------------------------------------------------------------
+         .pci_exp_txn                                    ( PCI_EXP_TXN ),
+         .pci_exp_txp                                    ( PCI_EXP_TXP ),
+         .pci_exp_rxn                                    ( PCI_EXP_RXN ),
+         .pci_exp_rxp                                    ( PCI_EXP_RXP ),
+
+         //---------------------------------------------------------------------
+         //  AXI Interface                                                      
+         //---------------------------------------------------------------------
+         .user_clk                                       ( user_clk ),
+         .user_reset                                     ( user_reset ),
+         .user_lnk_up                                    ( user_lnk_up ),
+         .user_app_rdy                                   ( ),
+
+         .s_axis_rq_tlast                                ( s_axis_rq_tlast ),
+         .s_axis_rq_tdata                                ( s_axis_rq_tdata ),
+         .s_axis_rq_tuser                                ( s_axis_rq_tuser ),
+         .s_axis_rq_tkeep                                ( s_axis_rq_tkeep ),
+         .s_axis_rq_tready                               ( s_axis_rq_tready ),
+         .s_axis_rq_tvalid                               ( s_axis_rq_tvalid ),
+
+         .m_axis_rc_tdata                                ( m_axis_rc_tdata ),
+         .m_axis_rc_tuser                                ( m_axis_rc_tuser ),
+         .m_axis_rc_tlast                                ( m_axis_rc_tlast ),
+         .m_axis_rc_tkeep                                ( m_axis_rc_tkeep ),
+         .m_axis_rc_tvalid                               ( m_axis_rc_tvalid ),
+         .m_axis_rc_tready                               ( {22{m_axis_rc_tready}} ),
+
+         .m_axis_cq_tdata                                ( m_axis_cq_tdata ),
+         .m_axis_cq_tuser                                ( m_axis_cq_tuser ),
+         .m_axis_cq_tlast                                ( m_axis_cq_tlast ),
+         .m_axis_cq_tkeep                                ( m_axis_cq_tkeep ),
+         .m_axis_cq_tvalid                               ( m_axis_cq_tvalid ),
+         .m_axis_cq_tready                               ( {22{m_axis_cq_tready}} ),
+
+         .s_axis_cc_tdata                                ( s_axis_cc_tdata ),
+         .s_axis_cc_tuser                                ( s_axis_cc_tuser ),
+         .s_axis_cc_tlast                                ( s_axis_cc_tlast ),
+         .s_axis_cc_tkeep                                ( s_axis_cc_tkeep ),
+         .s_axis_cc_tvalid                               ( s_axis_cc_tvalid ),
+         .s_axis_cc_tready                               ( s_axis_cc_tready ),
+
+         //---------------------------------------------------------------------
+         //  Configuration (CFG) Interface                                      
+         //---------------------------------------------------------------------
+         .pcie_rq_seq_num                                ( pcie_rq_seq_num ),
+         .pcie_rq_seq_num_vld                            ( pcie_rq_seq_num_vld ),
+         .pcie_rq_tag                                    ( pcie_rq_tag ),
+         .pcie_rq_tag_vld                                ( pcie_rq_tag_vld ),
+         .pcie_cq_np_req                                 ( pcie_cq_np_req ),
+         .pcie_cq_np_req_count                           ( pcie_cq_np_req_count ),
+         .cfg_phy_link_down                              ( cfg_phy_link_down ),
+         .cfg_phy_link_status                            ( cfg_phy_link_status),
+         .cfg_negotiated_width                           ( cfg_negotiated_width ),
+         .cfg_current_speed                              ( cfg_current_speed ),
+         .cfg_max_payload                                ( cfg_max_payload ),
+         .cfg_max_read_req                               ( cfg_max_read_req ),
+         .cfg_function_status                            ( cfg_function_status ),
+         .cfg_function_power_state                       ( cfg_function_power_state ),
+         .cfg_vf_status                                  ( cfg_vf_status ),
+         .cfg_vf_power_state                             ( cfg_vf_power_state ),
+         .cfg_link_power_state                           ( cfg_link_power_state ),
+         // Error Reporting Interface
+         .cfg_err_cor_out                                ( cfg_err_cor_out ),
+         .cfg_err_nonfatal_out                           ( cfg_err_nonfatal_out ),
+         .cfg_err_fatal_out                              ( cfg_err_fatal_out ),
+         .cfg_ltr_enable                                 ( cfg_ltr_enable ),
+         .cfg_ltssm_state                                ( cfg_ltssm_state ),
+         .cfg_rcb_status                                 ( cfg_rcb_status ),
+         .cfg_dpa_substate_change                        ( cfg_dpa_substate_change ),
+         .cfg_obff_enable                                ( cfg_obff_enable ),
+         .cfg_pl_status_change                           ( cfg_pl_status_change ),
+         .cfg_tph_requester_enable                       ( cfg_tph_requester_enable ),
+         .cfg_tph_st_mode                                ( cfg_tph_st_mode ),
+         .cfg_vf_tph_requester_enable                    ( cfg_vf_tph_requester_enable ),
+         .cfg_vf_tph_st_mode                             ( cfg_vf_tph_st_mode ),
+         .cfg_fc_ph                                      ( cfg_fc_ph ),
+         .cfg_fc_pd                                      ( cfg_fc_pd ),
+         .cfg_fc_nph                                     ( cfg_fc_nph ),
+         .cfg_fc_npd                                     ( cfg_fc_npd ),
+         .cfg_fc_cplh                                    ( cfg_fc_cplh ),
+         .cfg_fc_cpld                                    ( cfg_fc_cpld ),
+         .cfg_fc_sel                                     ( cfg_fc_sel ),
+         //---------------------------------------------------------------------
+         // EP Only                                                             
+         //---------------------------------------------------------------------
+         // Interrupt Interface Signals
+         .cfg_interrupt_int                              ( cfg_interrupt_int ),
+         .cfg_interrupt_pending                          ( cfg_interrupt_pending ),
+         .cfg_interrupt_sent                             ( cfg_interrupt_sent ),
+         .cfg_interrupt_msi_enable                       ( cfg_interrupt_msi_enable ),
+         .cfg_interrupt_msi_vf_enable                    ( cfg_interrupt_msi_vf_enable ),
+         .cfg_interrupt_msi_mmenable                     ( cfg_interrupt_msi_mmenable ),
+         .cfg_interrupt_msi_mask_update                  ( cfg_interrupt_msi_mask_update ),
+         .cfg_interrupt_msi_data                         ( cfg_interrupt_msi_data ),
+         .cfg_interrupt_msi_select                       ( cfg_interrupt_msi_select ),
+         .cfg_interrupt_msi_int                          ( cfg_interrupt_msi_int ),
+         .cfg_interrupt_msi_pending_status               ( cfg_interrupt_msi_pending_status ),
+         .cfg_interrupt_msi_sent                         ( cfg_interrupt_msi_sent ),
+         .cfg_interrupt_msi_fail                         ( cfg_interrupt_msi_fail ),
+         .cfg_interrupt_msi_attr                         ( cfg_interrupt_msi_attr ),
+         .cfg_interrupt_msi_tph_present                  ( cfg_interrupt_msi_tph_present ),
+         .cfg_interrupt_msi_tph_type                     ( cfg_interrupt_msi_tph_type ),
+         .cfg_interrupt_msi_tph_st_tag                   ( cfg_interrupt_msi_tph_st_tag ),
+         .cfg_interrupt_msi_function_number              ( cfg_interrupt_msi_function_number ),
+
+         //---------------------------------------------------------------------
+         //  System(SYS) Interface                                              
+         //---------------------------------------------------------------------
+         .sys_clk                                        (pcie_refclk),
+         .sys_reset                                      (~pcie_reset_n));
+
+    riffa_wrapper_vc709
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (// Outputs
+         .M_AXIS_CQ_TREADY              (m_axis_cq_tready),
+         .M_AXIS_RC_TREADY              (m_axis_rc_tready),
+         .S_AXIS_CC_TVALID              (s_axis_cc_tvalid),
+         .S_AXIS_CC_TLAST               (s_axis_cc_tlast),
+         .S_AXIS_CC_TDATA               (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (s_axis_rq_tvalid),
+         .S_AXIS_RQ_TLAST               (s_axis_rq_tlast),
+         .S_AXIS_RQ_TDATA               (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
+         .USER_CLK                      (user_clk),
+         .USER_RESET                    (user_reset),
+         .CFG_INTERRUPT_INT             (cfg_interrupt_int[3:0]),
+         .CFG_INTERRUPT_PENDING         (cfg_interrupt_pending[1:0]),
+         .CFG_INTERRUPT_MSI_SELECT      (cfg_interrupt_msi_select[3:0]),
+         .CFG_INTERRUPT_MSI_INT         (cfg_interrupt_msi_int[31:0]),
+         .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
+         .CFG_INTERRUPT_MSI_ATTR        (cfg_interrupt_msi_attr[2:0]),
+         .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
+         .CFG_INTERRUPT_MSI_TPH_TYPE    (cfg_interrupt_msi_tph_type[1:0]),
+         .CFG_INTERRUPT_MSI_TPH_ST_TAG  (cfg_interrupt_msi_tph_st_tag[8:0]),
+         .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
+         .CFG_FC_SEL                    (cfg_fc_sel[2:0]),
+         .PCIE_CQ_NP_REQ                (pcie_cq_np_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (m_axis_cq_tvalid),
+         .M_AXIS_CQ_TLAST               (m_axis_cq_tlast),
+         .M_AXIS_CQ_TDATA               (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (m_axis_rc_tvalid),
+         .M_AXIS_RC_TLAST               (m_axis_rc_tlast),
+         .M_AXIS_RC_TDATA               (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (s_axis_cc_tready),
+         .S_AXIS_RQ_TREADY              (s_axis_rq_tready),
+         .CFG_INTERRUPT_MSI_ENABLE      (cfg_interrupt_msi_enable[1:0]),
+         .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
+         .CFG_INTERRUPT_MSI_DATA        (cfg_interrupt_msi_data[31:0]),
+         .CFG_INTERRUPT_MSI_SENT        (cfg_interrupt_msi_sent),
+         .CFG_INTERRUPT_MSI_FAIL        (cfg_interrupt_msi_fail),
+         .CFG_FC_CPLH                   (cfg_fc_cplh[7:0]),
+         .CFG_FC_CPLD                   (cfg_fc_cpld[11:0]),
+         .CFG_NEGOTIATED_WIDTH          (cfg_negotiated_width[3:0]),
+         .CFG_CURRENT_SPEED             (cfg_current_speed[2:0]),
+         .CFG_MAX_PAYLOAD               (cfg_max_payload[2:0]),
+         .CFG_MAX_READ_REQ              (cfg_max_read_req[2:0]),
+         .CFG_FUNCTION_STATUS           (cfg_function_status[7:0]),
+         .CFG_RCB_STATUS                (cfg_rcb_status[1:0]),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+
+    generate
+        for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
+            chnl_tester 
+                    #(
+                      .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                      ) 
+            module1 
+                    (.CLK(user_clk),
+                     .RST(rst_out),    // riffa_reset includes riffa_endpoint resets
+                     // Rx interface
+                     .CHNL_RX_CLK(chnl_rx_clk[chnl]), 
+                     .CHNL_RX(chnl_rx[chnl]), 
+                     .CHNL_RX_ACK(chnl_rx_ack[chnl]), 
+                     .CHNL_RX_LAST(chnl_rx_last[chnl]), 
+                     .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), 
+                     .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), 
+                     .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), 
+                     .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
+                     // Tx interface
+                     .CHNL_TX_CLK(chnl_tx_clk[chnl]), 
+                     .CHNL_TX(chnl_tx[chnl]), 
+                     .CHNL_TX_ACK(chnl_tx_ack[chnl]), 
+                     .CHNL_TX_LAST(chnl_tx_last[chnl]), 
+                     .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), 
+                     .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), 
+                     .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), 
+                     .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
+                     );    
+        end
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/")
+// End:
+
diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64/ip/PCIeGen1x8If64.xci b/fpga/xilinx/vc709/VC709_Gen1x8If64/ip/PCIeGen1x8If64.xci
new file mode 100644
index 0000000..83388c7
--- /dev/null
+++ b/fpga/xilinx/vc709/VC709_Gen1x8If64/ip/PCIeGen1x8If64.xci
@@ -0,0 +1,677 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>PCIeGen1x8If64</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie3_7x" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.device_port_type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xlnx_ref_board">VC709</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xlnx_ref_board">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">2.5_GT/s</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">X8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXISTEN_IF_RC_STRADDLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_client_tag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_CLASS_CODE">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEVICE_ID">7018</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_OBFF_SUPPORT">00_Not_Supported</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_REVISION_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_CLASS_CODE">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_DEVICE_ID">7011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_REVISION_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_VER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK">0001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_pf0_enable_reg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TL_PF_ENABLE_REG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">PCIeGen1x8If64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_vc_cap_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_blk_locn">X0Y1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_pb_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pb_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.alignment_mode">DWORD_Aligned</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_rev">Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dev_cap_max_payload">512_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_tphr_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sub_class_interface_menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.extended_tag_field">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_ari_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vendor_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_tphr_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_aer_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dsn_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_cap_ver">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msi_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dpa_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_pcie_cfg_space_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ari_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.perf_level">Extreme</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_width">64_bit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_aer_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dsn_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msi_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dpa_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dev_cap_max_payload">512_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ltr_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Advanced</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.shared_logic_in_core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_gt_common">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tx_fc_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_fc_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ext_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_status_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.per_func_status_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_mgmt_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rcv_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_tx_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ctl_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pcie_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_pipe_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_msi_per_vec_masking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_startup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tandem_mode">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_freq">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.aspm_support">No_ASPM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE_EXT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_msg_route">2FFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_rx_msg_intfc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_mode_sim">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_powerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USER_CLK2_FREQ">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_CAP_ASPM_SUPPORT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.REF_CLK_FREQ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_LINK_SPEED">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ARI_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXT_FUNC">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CQ_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_STRADDLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RQ_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_CHECK_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_GEN_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR0_APERTURE_SIZE">0b00011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR0_CONTROL">0b100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR1_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR1_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR2_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR2_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR3_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR3_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR4_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR4_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR5_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR5_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_CLASS_CODE">0x058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_VENDOR_ID">0x10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEVICE_ID">0x7018</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_LTR_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_OBFF_SUPPORT">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_EXT_TAG_SUPPORTED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_MAX_PAYLOAD_SIZE">0b010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DSN_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_INTERRUPT_PIN">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LTR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSI_CAP_NEXTPTR">0xC0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PB_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_NEXTPTR">0x90</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE0">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE1">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE2">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE0">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE1">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE2">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_REVISION_ID">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR0_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR0_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR1_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR1_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR2_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR2_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR3_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR3_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR4_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR4_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR5_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR5_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_TOTAL_VF">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_VER">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">0x00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID">0x10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SUBSYSTEM_ID">0x0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_VC_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SPARE_WORD1">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_ECRC_CHECK_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_ECRC_GEN_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR0_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR0_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR1_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR1_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR2_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR2_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR3_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR3_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR4_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR4_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR5_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR5_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_CLASS_CODE">0x058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DEVICE_ID">0x7011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DEV_CAP_MAX_PAYLOAD_SIZE">0b010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DSN_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_EXPANSION_ROM_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_INTERRUPT_PIN">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSI_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PB_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_REVISION_ID">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR0_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR0_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR1_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR1_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR2_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR2_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR3_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR3_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR4_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR4_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR5_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR5_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_TOTAL_VF">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_VER">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK">0x0001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE">0x00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SUBSYSTEM_ID">0x0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_UPSTREAM_FACING">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SRIOV_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_CD">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_CH">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_NPD">0x028</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_NPH">0x20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_PD">0x198</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_PH">0x20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_LEGACY_MODE_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_PF_ENABLE_REG">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_PM_CAP_NEXTPTR">&quot;00000000&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_PM_CAP_NEXTPTR">&quot;00000000&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_PM_CAP_NEXTPTR">&quot;00000000&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_PM_CAP_NEXTPTR">&quot;00000000&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_PM_CAP_NEXTPTR">&quot;00000000&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_PM_CAP_NEXTPTR">&quot;00000000&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.COMPLETION_SPACE">16KB</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y0_ucf">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y3_ucf">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y2_ucf">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y1_ucf">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_revision">Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.xlnx_ref_board">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_blk_locn">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SHARED_LOGIC_IN_CORE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PIPE_SIM">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MSI_EN">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MSIX_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_EXT_CLK">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_EXT_GT_COMMON">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_CH_GT_DRP">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_STATUS_IF">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TX_FC_IF">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_EXT_IF">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_FC_IF">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PER_FUNC_STATUS_IF">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_MGMT_IF">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RCV_MSG_IF">FALSE</spirit:configurableElementValue>
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new file mode 100644
index 0000000..c32b490
--- /dev/null
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@@ -0,0 +1,779 @@
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+      <File Path="$PPRDIR/../../../../riffa_hdl/txc_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel_128.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue_output.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxr_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_multiplexer_64.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel_64.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxr_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/txr_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/txr_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/interrupt_controller.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue_input.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/riffa.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/registers.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/recv_credit_flow_ctrl.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rx_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/interrupt.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_multiplexer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rx_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/engine_layer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/riffa.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/chnl_tester.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../riffa_wrapper_vc709.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../hdl/VC709Gen1x8If64.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/xilinx.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/altera.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="VC709Gen1x8If64"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../constr/VC709_Top.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/VC709_Top.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="VC709Gen1x8If64"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="SimMode" Val="post-implementation"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="PCIeGen1x8If64" Type="BlockSrcs" RelSrcDir="$PSRCDIR/PCIeGen1x8If64">
+      <File Path="$PPRDIR/../ip/PCIeGen1x8If64.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="PCIeGen1x8If64"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="9">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx690tffg1761-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen1x8If64_synth_1" Type="Ft3:Synth" SrcSet="PCIeGen1x8If64" Part="xc7vx690tffg1761-2" ConstrsSet="PCIeGen1x8If64" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/PCIeGen1x8If64_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1761-2" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen1x8If64_impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1761-2" ConstrsSet="PCIeGen1x8If64" Description="Vivado Implementation Defaults" SynthRun="PCIeGen1x8If64_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+  </Runs>
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</Project>
diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128/bit/VC709Gen2x8If128.bit b/fpga/xilinx/vc709/VC709_Gen2x8If128/bit/VC709Gen2x8If128.bit
new file mode 100644
index 0000000..a1e88e0
Binary files /dev/null and b/fpga/xilinx/vc709/VC709_Gen2x8If128/bit/VC709Gen2x8If128.bit differ
diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128/constr/VC709_Top.xdc b/fpga/xilinx/vc709/VC709_Gen2x8If128/constr/VC709_Top.xdc
new file mode 100644
index 0000000..527f05f
--- /dev/null
+++ b/fpga/xilinx/vc709/VC709_Gen2x8If128/constr/VC709_Top.xdc
@@ -0,0 +1,139 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            VC709_Top.xdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Xilinx Design Constraints for the VC709 board.
+# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin
+# 
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+#
+#########################################################################################################################
+# User Constraints
+#########################################################################################################################
+
+###############################################################################
+# User Time Names / User Time Groups / Time Specs
+###############################################################################
+
+###############################################################################
+# User Physical Constraints
+###############################################################################
+
+#
+# LED Status Indicators for Example Design.
+# LED 0-2 should be all ON if link is up and functioning correctly
+# LED 3 should be blinking if user application is receiving valid clock
+#
+
+#System Reset, User Reset, User Link Up, User Clk Heartbeat
+set_property PACKAGE_PIN AM39 [get_ports {LED[0]}]
+set_property PACKAGE_PIN AN39 [get_ports {LED[1]}]
+set_property PACKAGE_PIN AR37 [get_ports {LED[2]}]
+set_property PACKAGE_PIN AT37 [get_ports {LED[3]}]
+set_property PACKAGE_PIN AR35 [get_ports {LED[4]}]
+set_property PACKAGE_PIN AP41 [get_ports {LED[5]}]
+set_property PACKAGE_PIN AP42 [get_ports {LED[6]}]
+set_property PACKAGE_PIN AU39 [get_ports {LED[7]}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[7]}]
+
+set_false_path -to [get_ports -filter NAME=~LED*]
+
+#########################################################################################################################
+# End User Constraints
+#########################################################################################################################
+#
+#
+#
+#########################################################################################################################
+# PCIE Core Constraints
+#########################################################################################################################
+
+#
+# SYS reset (input) signal.  The sys_reset_n signal should be
+# obtained from the PCI Express interface if possible.  For
+# slot based form factors, a system reset signal is usually
+# present on the connector.  For cable based form factors, a
+# system reset signal may not be available.  In this case, the
+# system reset signal must be generated locally by some form of
+# supervisory circuit.  You may change the IOSTANDARD and LOC
+# to suit your requirements and VCCO voltage banking rules.
+# Some 7 series devices do not have 3.3 V I/Os available.
+# Therefore the appropriate level shift is required to operate
+# with these devices that contain only 1.8 V banks.
+#
+
+set_property PACKAGE_PIN AV35 [get_ports PCIE_RESET_N]
+set_property IOSTANDARD LVCMOS18 [get_ports PCIE_RESET_N]
+set_property PULLUP true [get_ports PCIE_RESET_N]
+
+#
+#
+# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
+# signals are the PCI Express reference clock. Virtex-7 GT
+# Transceiver architecture requires the use of a dedicated clock
+# resources (FPGA input pins) associated with each GT Transceiver.
+# To use these pins an IBUFDS primitive (refclk_ibuf) is
+# instantiated in user's design.
+# Please refer to the Virtex-7 GT Transceiver User Guide
+# (UG) for guidelines regarding clock resource selection.
+#
+set_property LOC IBUFDS_GTE2_X1Y11 [get_cells refclk_ibuf]
+
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O]
+
+###############################################################################
+# Physical Constraints
+###############################################################################
+
+set_false_path -from [get_ports PCIE_RESET_N]
+###############################################################################
+# End
+###############################################################################
+
+
diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128/hdl/VC709Gen2x8If128.v b/fpga/xilinx/vc709/VC709_Gen2x8If128/hdl/VC709Gen2x8If128.v
new file mode 100644
index 0000000..a13afb4
--- /dev/null
+++ b/fpga/xilinx/vc709/VC709_Gen2x8If128/hdl/VC709Gen2x8If128.v
@@ -0,0 +1,481 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            VC709Gen2x8If128.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Xilinx VC709 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "ultrascale.vh"
+`timescale 1ps / 1ps
+module VC709Gen2x8If128
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 12,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 6
+      ) 
+    (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
+     output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXP,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXN,
+
+     output [7:0]                   LED,
+     input                          PCIE_REFCLK_P,
+     input                          PCIE_REFCLK_N,
+     input                          PCIE_RESET_N
+     );
+
+    // Clocks, etc
+    wire                            user_lnk_up;
+    wire                            user_clk;
+    wire                            user_reset;
+    wire                            pcie_refclk;
+    wire                            pcie_reset_n;
+
+    // Interface: RQ (TXC)
+    wire                            s_axis_rq_tlast;
+    wire [C_PCI_DATA_WIDTH-1:0]     s_axis_rq_tdata;
+    wire [`SIG_RQ_TUSER_W-1:0]      s_axis_rq_tuser;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
+    wire                             s_axis_rq_tready;
+    wire                             s_axis_rq_tvalid;
+    // Interface: RC (RXC)
+    wire [C_PCI_DATA_WIDTH-1:0]      m_axis_rc_tdata;
+    wire [`SIG_RC_TUSER_W-1:0]       m_axis_rc_tuser;
+    wire                             m_axis_rc_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
+    wire                             m_axis_rc_tvalid;
+    wire                             m_axis_rc_tready;
+    // Interface: CQ (RXR)
+    wire [C_PCI_DATA_WIDTH-1:0]      m_axis_cq_tdata;
+    wire [`SIG_CQ_TUSER_W-1:0]       m_axis_cq_tuser;
+    wire                             m_axis_cq_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
+    wire                             m_axis_cq_tvalid;
+    wire                             m_axis_cq_tready;
+    // Interface: CC (TXC)
+    wire [C_PCI_DATA_WIDTH-1:0]      s_axis_cc_tdata;
+    wire [`SIG_CC_TUSER_W-1:0]       s_axis_cc_tuser;
+    wire                             s_axis_cc_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
+    wire                             s_axis_cc_tvalid;
+    wire                             s_axis_cc_tready;
+
+    // Configuration (CFG) Interface                                           
+    wire [3:0]                       pcie_rq_seq_num;
+    wire                             pcie_rq_seq_num_vld;
+    wire [5:0]                       pcie_rq_tag;
+    wire                             pcie_rq_tag_vld;
+    wire                             pcie_cq_np_req;
+    wire [5:0]                       pcie_cq_np_req_count;
+
+    wire                             cfg_phy_link_down;
+    wire [3:0]                       cfg_negotiated_width; // CONFIG_LINK_WIDTH
+    wire [2:0]                       cfg_current_speed; // CONFIG_LINK_RATE
+    wire [2:0]                       cfg_max_payload; // CONFIG_MAX_PAYLOAD
+    wire [2:0]                       cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
+    wire [7:0]                       cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
+    wire [5:0]                       cfg_function_power_state; // Ignorable but not removable
+    wire [11:0]                      cfg_vf_status; // Ignorable but not removable
+    wire [17:0]                      cfg_vf_power_state; // Ignorable but not removable
+    wire [1:0]                       cfg_link_power_state; // Ignorable but not removable
+
+    // Error Reporting Interface
+    wire                             cfg_err_cor_out;
+    wire                             cfg_err_nonfatal_out;
+    wire                             cfg_err_fatal_out;
+
+    wire                             cfg_ltr_enable;
+    wire [5:0]                       cfg_ltssm_state;// TODO: Connect to LED's
+    wire [1:0]                       cfg_rcb_status;
+    wire [1:0]                       cfg_dpa_substate_change;
+    wire [1:0]                       cfg_obff_enable;
+    wire                             cfg_pl_status_change;
+
+    wire [1:0]                       cfg_tph_requester_enable;
+    wire [5:0]                       cfg_tph_st_mode;
+    wire [5:0]                       cfg_vf_tph_requester_enable;
+    wire [17:0]                      cfg_vf_tph_st_mode;
+    wire [7:0]                       cfg_fc_ph;
+    wire [11:0]                      cfg_fc_pd;
+    wire [7:0]                       cfg_fc_nph;
+    wire [11:0]                      cfg_fc_npd;
+    wire [7:0]                       cfg_fc_cplh;
+    wire [11:0]                      cfg_fc_cpld;
+    wire [2:0]                       cfg_fc_sel;
+
+    // Interrupt Interface Signals
+    wire [3:0]                       cfg_interrupt_int;
+    wire [1:0]                       cfg_interrupt_pending;
+    wire                             cfg_interrupt_sent;
+    wire [1:0]                       cfg_interrupt_msi_enable;
+    wire [5:0]                       cfg_interrupt_msi_vf_enable;
+    wire [5:0]                       cfg_interrupt_msi_mmenable;
+    wire                             cfg_interrupt_msi_mask_update;
+    wire [31:0]                      cfg_interrupt_msi_data;
+    wire [3:0]                       cfg_interrupt_msi_select;
+    wire [31:0]                      cfg_interrupt_msi_int;
+    wire [63:0]                      cfg_interrupt_msi_pending_status;
+    wire                             cfg_interrupt_msi_sent;
+    wire                             cfg_interrupt_msi_fail;
+    wire [2:0]                       cfg_interrupt_msi_attr;
+    wire                             cfg_interrupt_msi_tph_present;
+    wire [1:0]                       cfg_interrupt_msi_tph_type;
+    wire [8:0]                       cfg_interrupt_msi_tph_st_tag;
+    wire [2:0]                       cfg_interrupt_msi_function_number;
+
+    wire                             rst_out;
+    wire [C_NUM_CHNL-1:0]            chnl_rx_clk; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx_ack; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_rx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_ren;
+
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_clk; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_tx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_ren;
+
+    genvar                                     chnl;
+
+    IBUF 
+        #()  
+    pci_reset_n_ibuf 
+        (.O(pcie_reset_n), 
+         .I(PCIE_RESET_N));
+
+    IBUFDS_GTE2 
+        #()
+    refclk_ibuf 
+        (.O(pcie_refclk), 
+         .ODIV2(), 
+         .I(PCIE_REFCLK_P), 
+         .CEB(1'b0), 
+         .IB(PCIE_REFCLK_N));
+
+    OBUF 
+        #() 
+    led_0_obuf 
+        (.O(LED[0]),
+         .I(cfg_ltssm_state[0]));
+    OBUF 
+        #() 
+    led_1_obuf 
+        (.O(LED[1]),
+         .I(cfg_ltssm_state[1]));
+    OBUF 
+        #() 
+    led_2_obuf 
+        (.O(LED[2]),
+         .I(cfg_ltssm_state[2]));
+    OBUF 
+        #() 
+    led_3_obuf 
+        (.O(LED[3]),
+         .I(cfg_ltssm_state[3]));
+    OBUF 
+        #() 
+    led_4_obuf 
+        (.O(LED[4]),
+         .I(cfg_ltssm_state[4]));
+    OBUF 
+        #() 
+    led_5_obuf 
+        (.O(LED[5]),
+         .I(cfg_ltssm_state[5]));
+    OBUF 
+        #() 
+    led_6_obuf 
+        (.O(LED[6]),
+         .I(pcie_reset_n));
+    OBUF 
+        #() 
+    led_7_obuf 
+        (.O(LED[7]),
+         .I(rst_out));
+
+    // Core Top Level Wrapper
+    PCIeGen2x8If128  
+        #()
+    pcie3_7x_0_i 
+        (//---------------------------------------------------------------------
+         //  PCI Express (pci_exp) Interface                                    
+         //---------------------------------------------------------------------
+         .pci_exp_txn                                    ( PCI_EXP_TXN ),
+         .pci_exp_txp                                    ( PCI_EXP_TXP ),
+         .pci_exp_rxn                                    ( PCI_EXP_RXN ),
+         .pci_exp_rxp                                    ( PCI_EXP_RXP ),
+
+         //---------------------------------------------------------------------
+         //  AXI Interface                                                      
+         //---------------------------------------------------------------------
+         .user_clk                                       ( user_clk ),
+         .user_reset                                     ( user_reset ),
+         .user_lnk_up                                    ( user_lnk_up ),
+         .user_app_rdy                                   ( ),
+
+         .s_axis_rq_tlast                                ( s_axis_rq_tlast ),
+         .s_axis_rq_tdata                                ( s_axis_rq_tdata ),
+         .s_axis_rq_tuser                                ( s_axis_rq_tuser ),
+         .s_axis_rq_tkeep                                ( s_axis_rq_tkeep ),
+         .s_axis_rq_tready                               ( s_axis_rq_tready ),
+         .s_axis_rq_tvalid                               ( s_axis_rq_tvalid ),
+
+         .m_axis_rc_tdata                                ( m_axis_rc_tdata ),
+         .m_axis_rc_tuser                                ( m_axis_rc_tuser ),
+         .m_axis_rc_tlast                                ( m_axis_rc_tlast ),
+         .m_axis_rc_tkeep                                ( m_axis_rc_tkeep ),
+         .m_axis_rc_tvalid                               ( m_axis_rc_tvalid ),
+         .m_axis_rc_tready                               ( {22{m_axis_rc_tready}} ),
+
+         .m_axis_cq_tdata                                ( m_axis_cq_tdata ),
+         .m_axis_cq_tuser                                ( m_axis_cq_tuser ),
+         .m_axis_cq_tlast                                ( m_axis_cq_tlast ),
+         .m_axis_cq_tkeep                                ( m_axis_cq_tkeep ),
+         .m_axis_cq_tvalid                               ( m_axis_cq_tvalid ),
+         .m_axis_cq_tready                               ( {22{m_axis_cq_tready}} ),
+
+         .s_axis_cc_tdata                                ( s_axis_cc_tdata ),
+         .s_axis_cc_tuser                                ( s_axis_cc_tuser ),
+         .s_axis_cc_tlast                                ( s_axis_cc_tlast ),
+         .s_axis_cc_tkeep                                ( s_axis_cc_tkeep ),
+         .s_axis_cc_tvalid                               ( s_axis_cc_tvalid ),
+         .s_axis_cc_tready                               ( s_axis_cc_tready ),
+
+         //---------------------------------------------------------------------
+         //  Configuration (CFG) Interface                                      
+         //---------------------------------------------------------------------
+         .pcie_rq_seq_num                                ( pcie_rq_seq_num ),
+         .pcie_rq_seq_num_vld                            ( pcie_rq_seq_num_vld ),
+         .pcie_rq_tag                                    ( pcie_rq_tag ),
+         .pcie_rq_tag_vld                                ( pcie_rq_tag_vld ),
+         .pcie_cq_np_req                                 ( pcie_cq_np_req ),
+         .pcie_cq_np_req_count                           ( pcie_cq_np_req_count ),
+         .cfg_phy_link_down                              ( cfg_phy_link_down ),
+         .cfg_phy_link_status                            ( cfg_phy_link_status),
+         .cfg_negotiated_width                           ( cfg_negotiated_width ),
+         .cfg_current_speed                              ( cfg_current_speed ),
+         .cfg_max_payload                                ( cfg_max_payload ),
+         .cfg_max_read_req                               ( cfg_max_read_req ),
+         .cfg_function_status                            ( cfg_function_status ),
+         .cfg_function_power_state                       ( cfg_function_power_state ),
+         .cfg_vf_status                                  ( cfg_vf_status ),
+         .cfg_vf_power_state                             ( cfg_vf_power_state ),
+         .cfg_link_power_state                           ( cfg_link_power_state ),
+         // Error Reporting Interface
+         .cfg_err_cor_out                                ( cfg_err_cor_out ),
+         .cfg_err_nonfatal_out                           ( cfg_err_nonfatal_out ),
+         .cfg_err_fatal_out                              ( cfg_err_fatal_out ),
+         .cfg_ltr_enable                                 ( cfg_ltr_enable ),
+         .cfg_ltssm_state                                ( cfg_ltssm_state ),
+         .cfg_rcb_status                                 ( cfg_rcb_status ),
+         .cfg_dpa_substate_change                        ( cfg_dpa_substate_change ),
+         .cfg_obff_enable                                ( cfg_obff_enable ),
+         .cfg_pl_status_change                           ( cfg_pl_status_change ),
+         .cfg_tph_requester_enable                       ( cfg_tph_requester_enable ),
+         .cfg_tph_st_mode                                ( cfg_tph_st_mode ),
+         .cfg_vf_tph_requester_enable                    ( cfg_vf_tph_requester_enable ),
+         .cfg_vf_tph_st_mode                             ( cfg_vf_tph_st_mode ),
+         .cfg_fc_ph                                      ( cfg_fc_ph ),
+         .cfg_fc_pd                                      ( cfg_fc_pd ),
+         .cfg_fc_nph                                     ( cfg_fc_nph ),
+         .cfg_fc_npd                                     ( cfg_fc_npd ),
+         .cfg_fc_cplh                                    ( cfg_fc_cplh ),
+         .cfg_fc_cpld                                    ( cfg_fc_cpld ),
+         .cfg_fc_sel                                     ( cfg_fc_sel ),
+         //---------------------------------------------------------------------
+         // EP Only                                                             
+         //---------------------------------------------------------------------
+         // Interrupt Interface Signals
+         .cfg_interrupt_int                              ( cfg_interrupt_int ),
+         .cfg_interrupt_pending                          ( cfg_interrupt_pending ),
+         .cfg_interrupt_sent                             ( cfg_interrupt_sent ),
+         .cfg_interrupt_msi_enable                       ( cfg_interrupt_msi_enable ),
+         .cfg_interrupt_msi_vf_enable                    ( cfg_interrupt_msi_vf_enable ),
+         .cfg_interrupt_msi_mmenable                     ( cfg_interrupt_msi_mmenable ),
+         .cfg_interrupt_msi_mask_update                  ( cfg_interrupt_msi_mask_update ),
+         .cfg_interrupt_msi_data                         ( cfg_interrupt_msi_data ),
+         .cfg_interrupt_msi_select                       ( cfg_interrupt_msi_select ),
+         .cfg_interrupt_msi_int                          ( cfg_interrupt_msi_int ),
+         .cfg_interrupt_msi_pending_status               ( cfg_interrupt_msi_pending_status ),
+         .cfg_interrupt_msi_sent                         ( cfg_interrupt_msi_sent ),
+         .cfg_interrupt_msi_fail                         ( cfg_interrupt_msi_fail ),
+         .cfg_interrupt_msi_attr                         ( cfg_interrupt_msi_attr ),
+         .cfg_interrupt_msi_tph_present                  ( cfg_interrupt_msi_tph_present ),
+         .cfg_interrupt_msi_tph_type                     ( cfg_interrupt_msi_tph_type ),
+         .cfg_interrupt_msi_tph_st_tag                   ( cfg_interrupt_msi_tph_st_tag ),
+         .cfg_interrupt_msi_function_number              ( cfg_interrupt_msi_function_number ),
+
+         //---------------------------------------------------------------------
+         //  System(SYS) Interface                                              
+         //---------------------------------------------------------------------
+         .sys_clk                                        (pcie_refclk),
+         .sys_reset                                      (~pcie_reset_n));
+
+    riffa_wrapper_vc709
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (// Outputs
+         .M_AXIS_CQ_TREADY              (m_axis_cq_tready),
+         .M_AXIS_RC_TREADY              (m_axis_rc_tready),
+         .S_AXIS_CC_TVALID              (s_axis_cc_tvalid),
+         .S_AXIS_CC_TLAST               (s_axis_cc_tlast),
+         .S_AXIS_CC_TDATA               (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (s_axis_rq_tvalid),
+         .S_AXIS_RQ_TLAST               (s_axis_rq_tlast),
+         .S_AXIS_RQ_TDATA               (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
+         .USER_CLK                      (user_clk),
+         .USER_RESET                    (user_reset),
+         .CFG_INTERRUPT_INT             (cfg_interrupt_int[3:0]),
+         .CFG_INTERRUPT_PENDING         (cfg_interrupt_pending[1:0]),
+         .CFG_INTERRUPT_MSI_SELECT      (cfg_interrupt_msi_select[3:0]),
+         .CFG_INTERRUPT_MSI_INT         (cfg_interrupt_msi_int[31:0]),
+         .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
+         .CFG_INTERRUPT_MSI_ATTR        (cfg_interrupt_msi_attr[2:0]),
+         .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
+         .CFG_INTERRUPT_MSI_TPH_TYPE    (cfg_interrupt_msi_tph_type[1:0]),
+         .CFG_INTERRUPT_MSI_TPH_ST_TAG  (cfg_interrupt_msi_tph_st_tag[8:0]),
+         .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
+         .CFG_FC_SEL                    (cfg_fc_sel[2:0]),
+         .PCIE_CQ_NP_REQ                (pcie_cq_np_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (m_axis_cq_tvalid),
+         .M_AXIS_CQ_TLAST               (m_axis_cq_tlast),
+         .M_AXIS_CQ_TDATA               (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (m_axis_rc_tvalid),
+         .M_AXIS_RC_TLAST               (m_axis_rc_tlast),
+         .M_AXIS_RC_TDATA               (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (s_axis_cc_tready),
+         .S_AXIS_RQ_TREADY              (s_axis_rq_tready),
+         .CFG_INTERRUPT_MSI_ENABLE      (cfg_interrupt_msi_enable[1:0]),
+         .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
+         .CFG_INTERRUPT_MSI_DATA        (cfg_interrupt_msi_data[31:0]),
+         .CFG_INTERRUPT_MSI_SENT        (cfg_interrupt_msi_sent),
+         .CFG_INTERRUPT_MSI_FAIL        (cfg_interrupt_msi_fail),
+         .CFG_FC_CPLH                   (cfg_fc_cplh[7:0]),
+         .CFG_FC_CPLD                   (cfg_fc_cpld[11:0]),
+         .CFG_NEGOTIATED_WIDTH          (cfg_negotiated_width[3:0]),
+         .CFG_CURRENT_SPEED             (cfg_current_speed[2:0]),
+         .CFG_MAX_PAYLOAD               (cfg_max_payload[2:0]),
+         .CFG_MAX_READ_REQ              (cfg_max_read_req[2:0]),
+         .CFG_FUNCTION_STATUS           (cfg_function_status[7:0]),
+         .CFG_RCB_STATUS                (cfg_rcb_status[1:0]),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+
+    generate
+        for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
+            chnl_tester 
+                    #(
+                      .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                      ) 
+            module1 
+                    (.CLK(user_clk),
+                     .RST(rst_out),    // riffa_reset includes riffa_endpoint resets
+                     // Rx interface
+                     .CHNL_RX_CLK(chnl_rx_clk[chnl]), 
+                     .CHNL_RX(chnl_rx[chnl]), 
+                     .CHNL_RX_ACK(chnl_rx_ack[chnl]), 
+                     .CHNL_RX_LAST(chnl_rx_last[chnl]), 
+                     .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), 
+                     .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), 
+                     .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), 
+                     .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
+                     // Tx interface
+                     .CHNL_TX_CLK(chnl_tx_clk[chnl]), 
+                     .CHNL_TX(chnl_tx[chnl]), 
+                     .CHNL_TX_ACK(chnl_tx_ack[chnl]), 
+                     .CHNL_TX_LAST(chnl_tx_last[chnl]), 
+                     .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), 
+                     .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), 
+                     .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), 
+                     .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
+                     );    
+        end
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/")
+// End:
+
diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128/ip/PCIeGen2x8If128.xci b/fpga/xilinx/vc709/VC709_Gen2x8If128/ip/PCIeGen2x8If128.xci
new file mode 100644
index 0000000..63effe8
--- /dev/null
+++ b/fpga/xilinx/vc709/VC709_Gen2x8If128/ip/PCIeGen2x8If128.xci
@@ -0,0 +1,677 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>PCIeGen2x8If128</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie3_7x" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.device_port_type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xlnx_ref_board">VC709</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xlnx_ref_board">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">5.0_GT/s</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">X8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXISTEN_IF_RC_STRADDLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_client_tag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_CLASS_CODE">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEVICE_ID">7028</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_OBFF_SUPPORT">00_Not_Supported</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_REVISION_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_CLASS_CODE">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_DEVICE_ID">7011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_REVISION_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_VER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK">0001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_pf0_enable_reg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TL_PF_ENABLE_REG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">PCIeGen2x8If128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_vc_cap_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_blk_locn">X0Y1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_pb_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pb_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.alignment_mode">DWORD_Aligned</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_rev">Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dev_cap_max_payload">512_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_tphr_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sub_class_interface_menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.extended_tag_field">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_ari_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vendor_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_tphr_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_aer_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dsn_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_cap_ver">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msi_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dpa_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_pcie_cfg_space_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ari_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.perf_level">Extreme</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_width">128_bit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_aer_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dsn_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msi_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dpa_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dev_cap_max_payload">512_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ltr_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Advanced</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.shared_logic_in_core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_gt_common">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tx_fc_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_fc_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ext_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_status_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.per_func_status_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_mgmt_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rcv_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_tx_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ctl_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pcie_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_pipe_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_msi_per_vec_masking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_startup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tandem_mode">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_freq">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.aspm_support">No_ASPM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE_EXT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_msg_route">2FFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_rx_msg_intfc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_mode_sim">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_powerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USER_CLK2_FREQ">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_CAP_ASPM_SUPPORT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_WIDTH">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.REF_CLK_FREQ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_LINK_SPEED">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ARI_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXT_FUNC">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CQ_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_STRADDLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RQ_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_CHECK_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_GEN_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR0_APERTURE_SIZE">0b00011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR0_CONTROL">0b100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR1_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR1_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR2_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR2_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR3_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR3_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR4_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR4_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR5_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR5_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_CLASS_CODE">0x058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_VENDOR_ID">0x10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEVICE_ID">0x7028</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_LTR_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_OBFF_SUPPORT">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_EXT_TAG_SUPPORTED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_MAX_PAYLOAD_SIZE">0b010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DSN_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_INTERRUPT_PIN">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LTR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSI_CAP_NEXTPTR">0xC0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PB_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_NEXTPTR">0x90</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE1">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE2">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE0">0x00000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE2">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_REVISION_ID">0x00</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR0_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR1_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR2_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR2_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR3_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR4_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR4_CONTROL">0b000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_VER">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">0x00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID">0x10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SUBSYSTEM_ID">0x0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_VC_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SPARE_WORD1">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_ECRC_CHECK_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_ECRC_GEN_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR0_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR0_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR1_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR1_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR2_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR2_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR3_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR3_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR4_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR4_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR5_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR5_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_CLASS_CODE">0x058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DEVICE_ID">0x7011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DEV_CAP_MAX_PAYLOAD_SIZE">0b010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DSN_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_EXPANSION_ROM_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_INTERRUPT_PIN">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSI_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PB_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_REVISION_ID">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR0_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR0_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR1_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR1_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR2_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR2_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR3_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR3_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR4_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR4_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR5_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR5_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_TOTAL_VF">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_VER">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK">0x0001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE">0x00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SUBSYSTEM_ID">0x0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_UPSTREAM_FACING">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SRIOV_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_CD">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_CH">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_NPD">0x028</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_NPH">0x20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_PD">0x198</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_PH">0x20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_LEGACY_MODE_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_PF_ENABLE_REG">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
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diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128/prj/VC709_Gen2x8If128.xpr b/fpga/xilinx/vc709/VC709_Gen2x8If128/prj/VC709_Gen2x8If128.xpr
new file mode 100644
index 0000000..cb3f6d5
--- /dev/null
+++ b/fpga/xilinx/vc709/VC709_Gen2x8If128/prj/VC709_Gen2x8If128.xpr
@@ -0,0 +1,778 @@
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+<!--                                                         -->
+<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.   -->
+
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+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../riffa_wrapper_vc709.v">
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+      </File>
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+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="VC709Gen2x8If128"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../constr/VC709_Top.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
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+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/VC709_Top.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="VC709Gen2x8If128"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="PCIeGen2x8If128" Type="BlockSrcs" RelSrcDir="$PSRCDIR/PCIeGen2x8If128">
+      <File Path="$PPRDIR/../ip/PCIeGen2x8If128.xci">
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+      </File>
+      <Config>
+        <Option Name="TopModule" Val="PCIeGen2x8If128"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="9">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx690tffg1761-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen2x8If128_synth_1" Type="Ft3:Synth" SrcSet="PCIeGen2x8If128" Part="xc7vx690tffg1761-2" ConstrsSet="PCIeGen2x8If128" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/PCIeGen2x8If128_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1761-2" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen2x8If128_impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1761-2" ConstrsSet="PCIeGen2x8If128" Description="Vivado Implementation Defaults" SynthRun="PCIeGen2x8If128_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+  </Runs>
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</Project>
diff --git a/fpga/xilinx/vc709/VC709_Gen3x4If128/bit/README.txt b/fpga/xilinx/vc709/VC709_Gen3x4If128/bit/README.txt
new file mode 100644
index 0000000..e69de29
diff --git a/fpga/xilinx/vc709/VC709_Gen3x4If128/bit/VC709Gen3x4If128.bit b/fpga/xilinx/vc709/VC709_Gen3x4If128/bit/VC709Gen3x4If128.bit
new file mode 100644
index 0000000..5999acf
Binary files /dev/null and b/fpga/xilinx/vc709/VC709_Gen3x4If128/bit/VC709Gen3x4If128.bit differ
diff --git a/fpga/xilinx/vc709/VC709_Gen3x4If128/constr/VC709_Top.xdc b/fpga/xilinx/vc709/VC709_Gen3x4If128/constr/VC709_Top.xdc
new file mode 100644
index 0000000..36212f7
--- /dev/null
+++ b/fpga/xilinx/vc709/VC709_Gen3x4If128/constr/VC709_Top.xdc
@@ -0,0 +1,137 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            VC709_Top.xdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Xilinx Design Constraints for the VC709 board.
+# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin
+# 
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+#
+#########################################################################################################################
+# User Constraints
+#########################################################################################################################
+
+###############################################################################
+# User Time Names / User Time Groups / Time Specs
+###############################################################################
+
+###############################################################################
+# User Physical Constraints
+###############################################################################
+
+#
+# LED Status Indicators for Example Design.
+# LED 0-2 should be all ON if link is up and functioning correctly
+# LED 3 should be blinking if user application is receiving valid clock
+#
+
+#System Reset, User Reset, User Link Up, User Clk Heartbeat
+set_property PACKAGE_PIN AM39 [get_ports {LED[0]}]
+set_property PACKAGE_PIN AN39 [get_ports {LED[1]}]
+set_property PACKAGE_PIN AR37 [get_ports {LED[2]}]
+set_property PACKAGE_PIN AT37 [get_ports {LED[3]}]
+set_property PACKAGE_PIN AR35 [get_ports {LED[4]}]
+set_property PACKAGE_PIN AP41 [get_ports {LED[5]}]
+set_property PACKAGE_PIN AP42 [get_ports {LED[6]}]
+set_property PACKAGE_PIN AU39 [get_ports {LED[7]}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[7]}]
+
+set_false_path -to [get_ports -filter NAME=~LED*]
+
+#########################################################################################################################
+# End User Constraints
+#########################################################################################################################
+#
+#
+#
+#########################################################################################################################
+# PCIE Core Constraints
+#########################################################################################################################
+
+#
+# SYS reset (input) signal.  The sys_reset_n signal should be
+# obtained from the PCI Express interface if possible.  For
+# slot based form factors, a system reset signal is usually
+# present on the connector.  For cable based form factors, a
+# system reset signal may not be available.  In this case, the
+# system reset signal must be generated locally by some form of
+# supervisory circuit.  You may change the IOSTANDARD and LOC
+# to suit your requirements and VCCO voltage banking rules.
+# Some 7 series devices do not have 3.3 V I/Os available.
+# Therefore the appropriate level shift is required to operate
+# with these devices that contain only 1.8 V banks.
+#
+
+set_property PACKAGE_PIN AV35 [get_ports PCIE_RESET_N]
+set_property IOSTANDARD LVCMOS18 [get_ports PCIE_RESET_N]
+set_property PULLUP true [get_ports PCIE_RESET_N]
+
+#
+#
+# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
+# signals are the PCI Express reference clock. Virtex-7 GT
+# Transceiver architecture requires the use of a dedicated clock
+# resources (FPGA input pins) associated with each GT Transceiver.
+# To use these pins an IBUFDS primitive (refclk_ibuf) is
+# instantiated in user's design.
+# Please refer to the Virtex-7 GT Transceiver User Guide
+# (UG) for guidelines regarding clock resource selection.
+#
+set_property LOC IBUFDS_GTE2_X1Y11 [get_cells refclk_ibuf]
+
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O]
+
+###############################################################################
+# Physical Constraints
+###############################################################################
+
+set_false_path -from [get_ports PCIE_RESET_N]
+###############################################################################
+# End
+###############################################################################
diff --git a/fpga/xilinx/vc709/VC709_Gen3x4If128/hdl/VC709Gen3x4If128.v b/fpga/xilinx/vc709/VC709_Gen3x4If128/hdl/VC709Gen3x4If128.v
new file mode 100644
index 0000000..dbe2bf9
--- /dev/null
+++ b/fpga/xilinx/vc709/VC709_Gen3x4If128/hdl/VC709Gen3x4If128.v
@@ -0,0 +1,481 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            VC709Gen3x4If128.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Xilinx VC709 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "ultrascale.vh"
+`timescale 1ps / 1ps
+module VC709Gen3x4If128
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 12,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  4,
+      // Settings from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
+     output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXP,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXN,
+
+     output [7:0]                   LED,
+     input                          PCIE_REFCLK_P,
+     input                          PCIE_REFCLK_N,
+     input                          PCIE_RESET_N
+     );
+
+    // Clocks, etc
+    wire                            user_lnk_up;
+    wire                            user_clk;
+    wire                            user_reset;
+    wire                            pcie_refclk;
+    wire                            pcie_reset_n;
+
+    // Interface: RQ (TXC)
+    wire                            s_axis_rq_tlast;
+    wire [C_PCI_DATA_WIDTH-1:0]     s_axis_rq_tdata;
+    wire [`SIG_RQ_TUSER_W-1:0]      s_axis_rq_tuser;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
+    wire                             s_axis_rq_tready;
+    wire                             s_axis_rq_tvalid;
+    // Interface: RC (RXC)
+    wire [C_PCI_DATA_WIDTH-1:0]      m_axis_rc_tdata;
+    wire [`SIG_RC_TUSER_W-1:0]       m_axis_rc_tuser;
+    wire                             m_axis_rc_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
+    wire                             m_axis_rc_tvalid;
+    wire                             m_axis_rc_tready;
+    // Interface: CQ (RXR)
+    wire [C_PCI_DATA_WIDTH-1:0]      m_axis_cq_tdata;
+    wire [`SIG_CQ_TUSER_W-1:0]       m_axis_cq_tuser;
+    wire                             m_axis_cq_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
+    wire                             m_axis_cq_tvalid;
+    wire                             m_axis_cq_tready;
+    // Interface: CC (TXC)
+    wire [C_PCI_DATA_WIDTH-1:0]      s_axis_cc_tdata;
+    wire [`SIG_CC_TUSER_W-1:0]       s_axis_cc_tuser;
+    wire                             s_axis_cc_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
+    wire                             s_axis_cc_tvalid;
+    wire                             s_axis_cc_tready;
+
+    // Configuration (CFG) Interface                                           
+    wire [3:0]                       pcie_rq_seq_num;
+    wire                             pcie_rq_seq_num_vld;
+    wire [5:0]                       pcie_rq_tag;
+    wire                             pcie_rq_tag_vld;
+    wire                             pcie_cq_np_req;
+    wire [5:0]                       pcie_cq_np_req_count;
+
+    wire                             cfg_phy_link_down;
+    wire [3:0]                       cfg_negotiated_width; // CONFIG_LINK_WIDTH
+    wire [2:0]                       cfg_current_speed; // CONFIG_LINK_RATE
+    wire [2:0]                       cfg_max_payload; // CONFIG_MAX_PAYLOAD
+    wire [2:0]                       cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
+    wire [7:0]                       cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
+    wire [5:0]                       cfg_function_power_state; // Ignorable but not removable
+    wire [11:0]                      cfg_vf_status; // Ignorable but not removable
+    wire [17:0]                      cfg_vf_power_state; // Ignorable but not removable
+    wire [1:0]                       cfg_link_power_state; // Ignorable but not removable
+
+    // Error Reporting Interface
+    wire                             cfg_err_cor_out;
+    wire                             cfg_err_nonfatal_out;
+    wire                             cfg_err_fatal_out;
+
+    wire                             cfg_ltr_enable;
+    wire [5:0]                       cfg_ltssm_state;// TODO: Connect to LED's
+    wire [1:0]                       cfg_rcb_status;
+    wire [1:0]                       cfg_dpa_substate_change;
+    wire [1:0]                       cfg_obff_enable;
+    wire                             cfg_pl_status_change;
+
+    wire [1:0]                       cfg_tph_requester_enable;
+    wire [5:0]                       cfg_tph_st_mode;
+    wire [5:0]                       cfg_vf_tph_requester_enable;
+    wire [17:0]                      cfg_vf_tph_st_mode;
+    wire [7:0]                       cfg_fc_ph;
+    wire [11:0]                      cfg_fc_pd;
+    wire [7:0]                       cfg_fc_nph;
+    wire [11:0]                      cfg_fc_npd;
+    wire [7:0]                       cfg_fc_cplh;
+    wire [11:0]                      cfg_fc_cpld;
+    wire [2:0]                       cfg_fc_sel;
+
+    // Interrupt Interface Signals
+    wire [3:0]                       cfg_interrupt_int;
+    wire [1:0]                       cfg_interrupt_pending;
+    wire                             cfg_interrupt_sent;
+    wire [1:0]                       cfg_interrupt_msi_enable;
+    wire [5:0]                       cfg_interrupt_msi_vf_enable;
+    wire [5:0]                       cfg_interrupt_msi_mmenable;
+    wire                             cfg_interrupt_msi_mask_update;
+    wire [31:0]                      cfg_interrupt_msi_data;
+    wire [3:0]                       cfg_interrupt_msi_select;
+    wire [31:0]                      cfg_interrupt_msi_int;
+    wire [63:0]                      cfg_interrupt_msi_pending_status;
+    wire                             cfg_interrupt_msi_sent;
+    wire                             cfg_interrupt_msi_fail;
+    wire [2:0]                       cfg_interrupt_msi_attr;
+    wire                             cfg_interrupt_msi_tph_present;
+    wire [1:0]                       cfg_interrupt_msi_tph_type;
+    wire [8:0]                       cfg_interrupt_msi_tph_st_tag;
+    wire [2:0]                       cfg_interrupt_msi_function_number;
+
+    wire                             rst_out;
+    wire [C_NUM_CHNL-1:0]            chnl_rx_clk; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx_ack; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_rx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_ren;
+
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_clk; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_tx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_ren;
+
+    genvar                                     chnl;
+
+    IBUF 
+        #()  
+    pci_reset_n_ibuf 
+        (.O(pcie_reset_n), 
+         .I(PCIE_RESET_N));
+
+    IBUFDS_GTE2 
+        #()
+    refclk_ibuf 
+        (.O(pcie_refclk), 
+         .ODIV2(), 
+         .I(PCIE_REFCLK_P), 
+         .CEB(1'b0), 
+         .IB(PCIE_REFCLK_N));
+
+    OBUF 
+        #() 
+    led_0_obuf 
+        (.O(LED[0]),
+         .I(cfg_ltssm_state[0]));
+    OBUF 
+        #() 
+    led_1_obuf 
+        (.O(LED[1]),
+         .I(cfg_ltssm_state[1]));
+    OBUF 
+        #() 
+    led_2_obuf 
+        (.O(LED[2]),
+         .I(cfg_ltssm_state[2]));
+    OBUF 
+        #() 
+    led_3_obuf 
+        (.O(LED[3]),
+         .I(cfg_ltssm_state[3]));
+    OBUF 
+        #() 
+    led_4_obuf 
+        (.O(LED[4]),
+         .I(cfg_ltssm_state[4]));
+    OBUF 
+        #() 
+    led_5_obuf 
+        (.O(LED[5]),
+         .I(cfg_ltssm_state[5]));
+    OBUF 
+        #() 
+    led_6_obuf 
+        (.O(LED[6]),
+         .I(pcie_reset_n));
+    OBUF 
+        #() 
+    led_7_obuf 
+        (.O(LED[7]),
+         .I(rst_out));
+
+    // Core Top Level Wrapper
+    PCIeGen3x4If128  
+        #()
+    pcie3_7x_0_i 
+        (//---------------------------------------------------------------------
+         //  PCI Express (pci_exp) Interface                                    
+         //---------------------------------------------------------------------
+         .pci_exp_txn                                    ( PCI_EXP_TXN ),
+         .pci_exp_txp                                    ( PCI_EXP_TXP ),
+         .pci_exp_rxn                                    ( PCI_EXP_RXN ),
+         .pci_exp_rxp                                    ( PCI_EXP_RXP ),
+
+         //---------------------------------------------------------------------
+         //  AXI Interface                                                      
+         //---------------------------------------------------------------------
+         .user_clk                                       ( user_clk ),
+         .user_reset                                     ( user_reset ),
+         .user_lnk_up                                    ( user_lnk_up ),
+         .user_app_rdy                                   ( ),
+
+         .s_axis_rq_tlast                                ( s_axis_rq_tlast ),
+         .s_axis_rq_tdata                                ( s_axis_rq_tdata ),
+         .s_axis_rq_tuser                                ( s_axis_rq_tuser ),
+         .s_axis_rq_tkeep                                ( s_axis_rq_tkeep ),
+         .s_axis_rq_tready                               ( s_axis_rq_tready ),
+         .s_axis_rq_tvalid                               ( s_axis_rq_tvalid ),
+
+         .m_axis_rc_tdata                                ( m_axis_rc_tdata ),
+         .m_axis_rc_tuser                                ( m_axis_rc_tuser ),
+         .m_axis_rc_tlast                                ( m_axis_rc_tlast ),
+         .m_axis_rc_tkeep                                ( m_axis_rc_tkeep ),
+         .m_axis_rc_tvalid                               ( m_axis_rc_tvalid ),
+         .m_axis_rc_tready                               ( {22{m_axis_rc_tready}} ),
+
+         .m_axis_cq_tdata                                ( m_axis_cq_tdata ),
+         .m_axis_cq_tuser                                ( m_axis_cq_tuser ),
+         .m_axis_cq_tlast                                ( m_axis_cq_tlast ),
+         .m_axis_cq_tkeep                                ( m_axis_cq_tkeep ),
+         .m_axis_cq_tvalid                               ( m_axis_cq_tvalid ),
+         .m_axis_cq_tready                               ( {22{m_axis_cq_tready}} ),
+
+         .s_axis_cc_tdata                                ( s_axis_cc_tdata ),
+         .s_axis_cc_tuser                                ( s_axis_cc_tuser ),
+         .s_axis_cc_tlast                                ( s_axis_cc_tlast ),
+         .s_axis_cc_tkeep                                ( s_axis_cc_tkeep ),
+         .s_axis_cc_tvalid                               ( s_axis_cc_tvalid ),
+         .s_axis_cc_tready                               ( s_axis_cc_tready ),
+
+         //---------------------------------------------------------------------
+         //  Configuration (CFG) Interface                                      
+         //---------------------------------------------------------------------
+         .pcie_rq_seq_num                                ( pcie_rq_seq_num ),
+         .pcie_rq_seq_num_vld                            ( pcie_rq_seq_num_vld ),
+         .pcie_rq_tag                                    ( pcie_rq_tag ),
+         .pcie_rq_tag_vld                                ( pcie_rq_tag_vld ),
+         .pcie_cq_np_req                                 ( pcie_cq_np_req ),
+         .pcie_cq_np_req_count                           ( pcie_cq_np_req_count ),
+         .cfg_phy_link_down                              ( cfg_phy_link_down ),
+         .cfg_phy_link_status                            ( cfg_phy_link_status),
+         .cfg_negotiated_width                           ( cfg_negotiated_width ),
+         .cfg_current_speed                              ( cfg_current_speed ),
+         .cfg_max_payload                                ( cfg_max_payload ),
+         .cfg_max_read_req                               ( cfg_max_read_req ),
+         .cfg_function_status                            ( cfg_function_status ),
+         .cfg_function_power_state                       ( cfg_function_power_state ),
+         .cfg_vf_status                                  ( cfg_vf_status ),
+         .cfg_vf_power_state                             ( cfg_vf_power_state ),
+         .cfg_link_power_state                           ( cfg_link_power_state ),
+         // Error Reporting Interface
+         .cfg_err_cor_out                                ( cfg_err_cor_out ),
+         .cfg_err_nonfatal_out                           ( cfg_err_nonfatal_out ),
+         .cfg_err_fatal_out                              ( cfg_err_fatal_out ),
+         .cfg_ltr_enable                                 ( cfg_ltr_enable ),
+         .cfg_ltssm_state                                ( cfg_ltssm_state ),
+         .cfg_rcb_status                                 ( cfg_rcb_status ),
+         .cfg_dpa_substate_change                        ( cfg_dpa_substate_change ),
+         .cfg_obff_enable                                ( cfg_obff_enable ),
+         .cfg_pl_status_change                           ( cfg_pl_status_change ),
+         .cfg_tph_requester_enable                       ( cfg_tph_requester_enable ),
+         .cfg_tph_st_mode                                ( cfg_tph_st_mode ),
+         .cfg_vf_tph_requester_enable                    ( cfg_vf_tph_requester_enable ),
+         .cfg_vf_tph_st_mode                             ( cfg_vf_tph_st_mode ),
+         .cfg_fc_ph                                      ( cfg_fc_ph ),
+         .cfg_fc_pd                                      ( cfg_fc_pd ),
+         .cfg_fc_nph                                     ( cfg_fc_nph ),
+         .cfg_fc_npd                                     ( cfg_fc_npd ),
+         .cfg_fc_cplh                                    ( cfg_fc_cplh ),
+         .cfg_fc_cpld                                    ( cfg_fc_cpld ),
+         .cfg_fc_sel                                     ( cfg_fc_sel ),
+         //---------------------------------------------------------------------
+         // EP Only                                                             
+         //---------------------------------------------------------------------
+         // Interrupt Interface Signals
+         .cfg_interrupt_int                              ( cfg_interrupt_int ),
+         .cfg_interrupt_pending                          ( cfg_interrupt_pending ),
+         .cfg_interrupt_sent                             ( cfg_interrupt_sent ),
+         .cfg_interrupt_msi_enable                       ( cfg_interrupt_msi_enable ),
+         .cfg_interrupt_msi_vf_enable                    ( cfg_interrupt_msi_vf_enable ),
+         .cfg_interrupt_msi_mmenable                     ( cfg_interrupt_msi_mmenable ),
+         .cfg_interrupt_msi_mask_update                  ( cfg_interrupt_msi_mask_update ),
+         .cfg_interrupt_msi_data                         ( cfg_interrupt_msi_data ),
+         .cfg_interrupt_msi_select                       ( cfg_interrupt_msi_select ),
+         .cfg_interrupt_msi_int                          ( cfg_interrupt_msi_int ),
+         .cfg_interrupt_msi_pending_status               ( cfg_interrupt_msi_pending_status ),
+         .cfg_interrupt_msi_sent                         ( cfg_interrupt_msi_sent ),
+         .cfg_interrupt_msi_fail                         ( cfg_interrupt_msi_fail ),
+         .cfg_interrupt_msi_attr                         ( cfg_interrupt_msi_attr ),
+         .cfg_interrupt_msi_tph_present                  ( cfg_interrupt_msi_tph_present ),
+         .cfg_interrupt_msi_tph_type                     ( cfg_interrupt_msi_tph_type ),
+         .cfg_interrupt_msi_tph_st_tag                   ( cfg_interrupt_msi_tph_st_tag ),
+         .cfg_interrupt_msi_function_number              ( cfg_interrupt_msi_function_number ),
+
+         //---------------------------------------------------------------------
+         //  System(SYS) Interface                                              
+         //---------------------------------------------------------------------
+         .sys_clk                                        (pcie_refclk),
+         .sys_reset                                      (~pcie_reset_n));
+
+    riffa_wrapper_vc709
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (// Outputs
+         .M_AXIS_CQ_TREADY              (m_axis_cq_tready),
+         .M_AXIS_RC_TREADY              (m_axis_rc_tready),
+         .S_AXIS_CC_TVALID              (s_axis_cc_tvalid),
+         .S_AXIS_CC_TLAST               (s_axis_cc_tlast),
+         .S_AXIS_CC_TDATA               (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (s_axis_rq_tvalid),
+         .S_AXIS_RQ_TLAST               (s_axis_rq_tlast),
+         .S_AXIS_RQ_TDATA               (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
+         .USER_CLK                      (user_clk),
+         .USER_RESET                    (user_reset),
+         .CFG_INTERRUPT_INT             (cfg_interrupt_int[3:0]),
+         .CFG_INTERRUPT_PENDING         (cfg_interrupt_pending[1:0]),
+         .CFG_INTERRUPT_MSI_SELECT      (cfg_interrupt_msi_select[3:0]),
+         .CFG_INTERRUPT_MSI_INT         (cfg_interrupt_msi_int[31:0]),
+         .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
+         .CFG_INTERRUPT_MSI_ATTR        (cfg_interrupt_msi_attr[2:0]),
+         .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
+         .CFG_INTERRUPT_MSI_TPH_TYPE    (cfg_interrupt_msi_tph_type[1:0]),
+         .CFG_INTERRUPT_MSI_TPH_ST_TAG  (cfg_interrupt_msi_tph_st_tag[8:0]),
+         .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
+         .CFG_FC_SEL                    (cfg_fc_sel[2:0]),
+         .PCIE_CQ_NP_REQ                (pcie_cq_np_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (m_axis_cq_tvalid),
+         .M_AXIS_CQ_TLAST               (m_axis_cq_tlast),
+         .M_AXIS_CQ_TDATA               (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (m_axis_rc_tvalid),
+         .M_AXIS_RC_TLAST               (m_axis_rc_tlast),
+         .M_AXIS_RC_TDATA               (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (s_axis_cc_tready),
+         .S_AXIS_RQ_TREADY              (s_axis_rq_tready),
+         .CFG_INTERRUPT_MSI_ENABLE      (cfg_interrupt_msi_enable[1:0]),
+         .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
+         .CFG_INTERRUPT_MSI_DATA        (cfg_interrupt_msi_data[31:0]),
+         .CFG_INTERRUPT_MSI_SENT        (cfg_interrupt_msi_sent),
+         .CFG_INTERRUPT_MSI_FAIL        (cfg_interrupt_msi_fail),
+         .CFG_FC_CPLH                   (cfg_fc_cplh[7:0]),
+         .CFG_FC_CPLD                   (cfg_fc_cpld[11:0]),
+         .CFG_NEGOTIATED_WIDTH          (cfg_negotiated_width[3:0]),
+         .CFG_CURRENT_SPEED             (cfg_current_speed[2:0]),
+         .CFG_MAX_PAYLOAD               (cfg_max_payload[2:0]),
+         .CFG_MAX_READ_REQ              (cfg_max_read_req[2:0]),
+         .CFG_FUNCTION_STATUS           (cfg_function_status[7:0]),
+         .CFG_RCB_STATUS                (cfg_rcb_status[1:0]),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+
+    generate
+        for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
+            chnl_tester 
+                    #(
+                      .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                      ) 
+            module1 
+                    (.CLK(user_clk),
+                     .RST(rst_out),    // riffa_reset includes riffa_endpoint resets
+                     // Rx interface
+                     .CHNL_RX_CLK(chnl_rx_clk[chnl]), 
+                     .CHNL_RX(chnl_rx[chnl]), 
+                     .CHNL_RX_ACK(chnl_rx_ack[chnl]), 
+                     .CHNL_RX_LAST(chnl_rx_last[chnl]), 
+                     .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), 
+                     .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), 
+                     .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), 
+                     .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
+                     // Tx interface
+                     .CHNL_TX_CLK(chnl_tx_clk[chnl]), 
+                     .CHNL_TX(chnl_tx[chnl]), 
+                     .CHNL_TX_ACK(chnl_tx_ack[chnl]), 
+                     .CHNL_TX_LAST(chnl_tx_last[chnl]), 
+                     .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), 
+                     .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), 
+                     .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), 
+                     .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
+                     );    
+        end
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/")
+// End:
+
diff --git a/fpga/xilinx/vc709/VC709_Gen3x4If128/ip/PCIeGen3x4If128.xci b/fpga/xilinx/vc709/VC709_Gen3x4If128/ip/PCIeGen3x4If128.xci
new file mode 100644
index 0000000..36ab2f5
--- /dev/null
+++ b/fpga/xilinx/vc709/VC709_Gen3x4If128/ip/PCIeGen3x4If128.xci
@@ -0,0 +1,677 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>PCIeGen3x4If128</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie3_7x" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.device_port_type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xlnx_ref_board">VC709</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xlnx_ref_board">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">8.0_GT/s</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">X4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXISTEN_IF_RC_STRADDLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_client_tag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_CLASS_CODE">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEVICE_ID">7034</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_OBFF_SUPPORT">00_Not_Supported</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_REVISION_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_CLASS_CODE">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_DEVICE_ID">7011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_REVISION_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_VER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK">0001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_pf0_enable_reg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TL_PF_ENABLE_REG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">PCIeGen3x4If128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_vc_cap_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_blk_locn">X0Y1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_pb_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pb_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.alignment_mode">DWORD_Aligned</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_rev">Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dev_cap_max_payload">256_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_tphr_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sub_class_interface_menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.extended_tag_field">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_ari_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vendor_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_tphr_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_aer_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dsn_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_cap_ver">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msi_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dpa_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_pcie_cfg_space_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ari_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.perf_level">Extreme</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_width">128_bit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_aer_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dsn_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msi_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dpa_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dev_cap_max_payload">512_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ltr_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Advanced</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.shared_logic_in_core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_gt_common">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tx_fc_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_fc_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ext_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_status_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.per_func_status_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_mgmt_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rcv_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_tx_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ctl_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pcie_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_pipe_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_msi_per_vec_masking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_startup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tandem_mode">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_freq">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.aspm_support">No_ASPM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE_EXT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_msg_route">2FFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_rx_msg_intfc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_mode_sim">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_powerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USER_CLK2_FREQ">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_CAP_ASPM_SUPPORT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_WIDTH">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.REF_CLK_FREQ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_LINK_SPEED">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ARI_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXT_FUNC">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CQ_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_STRADDLE">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_UPSTREAM_FACING">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SRIOV_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_CD">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_CH">0x00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_NPH">0x20</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_PH">0x20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_LEGACY_MODE_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_PF_ENABLE_REG">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_PM_CAP_NEXTPTR">&quot;00000000&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_PM_CAP_NEXTPTR">&quot;00000000&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_PM_CAP_NEXTPTR">&quot;00000000&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y0_ucf">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.xlnx_ref_board">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_blk_locn">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SHARED_LOGIC_IN_CORE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PIPE_SIM">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MSI_EN">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MSIX_EN">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_EXT_GT_COMMON">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_CH_GT_DRP">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PER_FUNC_STATUS_IF">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_MGMT_IF">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RCV_MSG_IF">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_TX_MSG_IF">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_CTL_IF">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_DRP">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TRANSCEIVER_CTRL_STATUS_PORTS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_ENABLE_CLIENT_TAG">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_USE_MODE">2.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_FAST_CONFIG">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_PIPE_INTERFACE">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.POWER_DOWN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtex7</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD">xilinx.com:vc709:part0:1.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2014.4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/xilinx/vc709/VC709_Gen3x4If128/prj/VC709_Gen3x4If128.xpr b/fpga/xilinx/vc709/VC709_Gen3x4If128/prj/VC709_Gen3x4If128.xpr
new file mode 100644
index 0000000..a8e2f3a
--- /dev/null
+++ b/fpga/xilinx/vc709/VC709_Gen3x4If128/prj/VC709_Gen3x4If128.xpr
@@ -0,0 +1,779 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2014.4 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="2" Path="/home/drichmond/Research/repositories/git/RIFFA-devel/riffa_2.2.0/source/fpga/xilinx/vc709/VC709_Gen3x4If128/prj/VC709_Gen3x4If128.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="ee5dbb325de3470e81ad85e793306c9a"/>
+    <Option Name="Part" Val="xc7vx690tffg1761-2"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="BoardPart" Val="xilinx.com:vc709:part0:1.5"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../../../../riffa_hdl/shiftreg.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/functions.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/scsdpram.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/fifo.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/ff.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/ram_2clk_1w_1r.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/types.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/trellis.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/widths.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/offset_flag_to_one_hot.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/syncff.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
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+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/altera.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="VC709Gen3x4If128"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../constr/VC709_Top.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/VC709_Top.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="VC709Gen3x4If128"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="SimMode" Val="post-implementation"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="PCIeGen3x4If128" Type="BlockSrcs" RelSrcDir="$PSRCDIR/PCIeGen3x4If128">
+      <File Path="$PPRDIR/../ip/PCIeGen3x4If128.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="PCIeGen3x4If128"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="9">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx690tffg1761-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen3x4If128_synth_1" Type="Ft3:Synth" SrcSet="PCIeGen3x4If128" Part="xc7vx690tffg1761-2" ConstrsSet="PCIeGen3x4If128" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/PCIeGen3x4If128_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1761-2" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen3x4If128_impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1761-2" ConstrsSet="PCIeGen3x4If128" Description="Vivado Implementation Defaults" SynthRun="PCIeGen3x4If128_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+  </Runs>
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</Project>
diff --git a/fpga/xilinx/vc709/riffa_wrapper_vc709.v b/fpga/xilinx/vc709/riffa_wrapper_vc709.v
new file mode 100644
index 0000000..523afbc
--- /dev/null
+++ b/fpga/xilinx/vc709/riffa_wrapper_vc709.v
@@ -0,0 +1,584 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            riffa_wrapper_vc709.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         RIFFA wrapper for the VC709 Development board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "ultrascale.vh"
+`include "functions.vh"
+`timescale 1ps / 1ps
+module riffa_wrapper_vc709
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Bit-Width from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      // 4-Byte Name for this FPGA
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     //Interface: CQ Ultrascale (RXR)
+     input                                        M_AXIS_CQ_TVALID,
+     input                                        M_AXIS_CQ_TLAST,
+     input [C_PCI_DATA_WIDTH-1:0]                 M_AXIS_CQ_TDATA,
+     input [(C_PCI_DATA_WIDTH/32)-1:0]            M_AXIS_CQ_TKEEP,
+     input [`SIG_CQ_TUSER_W-1:0]                  M_AXIS_CQ_TUSER,
+     output                                       M_AXIS_CQ_TREADY,
+
+     //Interface: RC Ultrascale (RXC)
+     input                                        M_AXIS_RC_TVALID,
+     input                                        M_AXIS_RC_TLAST,
+     input [C_PCI_DATA_WIDTH-1:0]                 M_AXIS_RC_TDATA,
+     input [(C_PCI_DATA_WIDTH/32)-1:0]            M_AXIS_RC_TKEEP,
+     input [`SIG_RC_TUSER_W-1:0]                  M_AXIS_RC_TUSER,
+     output                                       M_AXIS_RC_TREADY,
+
+     //Interface: CC Ultrascale (TXC)
+     input                                        S_AXIS_CC_TREADY,
+     output                                       S_AXIS_CC_TVALID,
+     output                                       S_AXIS_CC_TLAST,
+     output [C_PCI_DATA_WIDTH-1:0]                S_AXIS_CC_TDATA,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]           S_AXIS_CC_TKEEP,
+     output [`SIG_CC_TUSER_W-1:0]                 S_AXIS_CC_TUSER,
+    
+     //Interface: RQ Ultrascale (TXR) 
+     input                                        S_AXIS_RQ_TREADY,
+     output                                       S_AXIS_RQ_TVALID,
+     output                                       S_AXIS_RQ_TLAST,
+     output [C_PCI_DATA_WIDTH-1:0]                S_AXIS_RQ_TDATA,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]           S_AXIS_RQ_TKEEP,
+     output [`SIG_RQ_TUSER_W-1:0]                 S_AXIS_RQ_TUSER,
+
+     input                                        USER_CLK,
+     input                                        USER_RESET,
+
+     output [3:0]                                 CFG_INTERRUPT_INT,
+     output [1:0]                                 CFG_INTERRUPT_PENDING,
+     input [1:0]                                  CFG_INTERRUPT_MSI_ENABLE,
+     input                                        CFG_INTERRUPT_MSI_MASK_UPDATE,
+     input [31:0]                                 CFG_INTERRUPT_MSI_DATA,
+     output [3:0]                                 CFG_INTERRUPT_MSI_SELECT,
+     output [31:0]                                CFG_INTERRUPT_MSI_INT,
+     output [63:0]                                CFG_INTERRUPT_MSI_PENDING_STATUS,
+     input                                        CFG_INTERRUPT_MSI_SENT,
+     input                                        CFG_INTERRUPT_MSI_FAIL,
+     output [2:0]                                 CFG_INTERRUPT_MSI_ATTR,
+     output                                       CFG_INTERRUPT_MSI_TPH_PRESENT,
+     output [1:0]                                 CFG_INTERRUPT_MSI_TPH_TYPE,
+     output [8:0]                                 CFG_INTERRUPT_MSI_TPH_ST_TAG,
+     output [2:0]                                 CFG_INTERRUPT_MSI_FUNCTION_NUMBER,
+
+     input [7:0]                                  CFG_FC_CPLH,
+     input [11:0]                                 CFG_FC_CPLD,
+     output [2:0]                                 CFG_FC_SEL,
+
+     input [3:0]                                  CFG_NEGOTIATED_WIDTH, // CONFIG_LINK_WIDTH
+     input [2:0]                                  CFG_CURRENT_SPEED, // CONFIG_LINK_RATE
+     input [2:0]                                  CFG_MAX_PAYLOAD, // CONFIG_MAX_PAYLOAD
+     input [2:0]                                  CFG_MAX_READ_REQ, // CONFIG_MAX_READ_REQUEST
+     input [7:0]                                  CFG_FUNCTION_STATUS, // [2] = CONFIG_BUS_MASTER_ENABLE
+     input [1:0]                                  CFG_RCB_STATUS,
+    
+     output                                       PCIE_CQ_NP_REQ,
+
+     // RIFFA Interface Signals
+     output                                       RST_OUT,
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_CLK, // Channel read clock
+     output [C_NUM_CHNL-1:0]                      CHNL_RX, // Channel read receive signal
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_ACK, // Channel read received signal
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_LAST, // Channel last read
+     output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
+     output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
+     output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   CHNL_RX_DATA, // Channel read data
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_DATA_VALID, // Channel read data valid
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_DATA_REN, // Channel read data has been recieved
+
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_CLK, // Channel write clock
+     input [C_NUM_CHNL-1:0]                       CHNL_TX, // Channel write receive signal
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_ACK, // Channel write acknowledgement signal
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_LAST, // Channel last write
+     input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]  CHNL_TX_LEN, // Channel write length (in 32 bit words)
+     input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]  CHNL_TX_OFF, // Channel write offset
+     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]    CHNL_TX_DATA, // Channel write data
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_DATA_VALID, // Channel write data valid
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_DATA_REN // Channel write data has been recieved
+
+     );
+    localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
+    localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
+    // ALTERA, XILINX or ULTRASCALE
+    localparam C_VENDOR = "ULTRASCALE";
+
+    localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
+    localparam C_PIPELINE_OUTPUT = 1;
+    localparam C_PIPELINE_INPUT = 1;
+
+    wire                                          clk;
+    wire                                          rst_in;
+
+    // Interface: RXC Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxc_data;
+    wire                                          rxc_data_valid;
+    wire                                          rxc_data_start_flag;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxc_data_word_enable;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxc_meta_fdwbe;
+    wire                                          rxc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxc_meta_ldwbe;
+    wire [`SIG_TAG_W-1:0]                         rxc_meta_tag;
+    wire [`SIG_LOWADDR_W-1:0]                     rxc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        rxc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         rxc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     rxc_meta_bytes_remaining;
+    wire [`SIG_CPLID_W-1:0]                       rxc_meta_completer_id;
+    wire                                          rxc_meta_ep;
+
+    // Interface: RXR Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxr_data;
+    wire                                          rxr_data_valid;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxr_data_word_enable;
+    wire                                          rxr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxr_meta_fdwbe;
+    wire                                          rxr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxr_meta_ldwbe;
+    wire [`SIG_TC_W-1:0]                          rxr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        rxr_meta_attr;
+    wire [`SIG_TAG_W-1:0]                         rxr_meta_tag;
+    wire [`SIG_TYPE_W-1:0]                        rxr_meta_type;
+    wire [`SIG_ADDR_W-1:0]                        rxr_meta_addr;
+    wire [`SIG_BARDECODE_W-1:0]                   rxr_meta_bar_decoded;
+    wire [`SIG_REQID_W-1:0]                       rxr_meta_requester_id;
+    wire [`SIG_LEN_W-1:0]                         rxr_meta_length;
+    wire                                          rxr_meta_ep;
+    
+    // interface: TXC Engine
+    wire                                          txc_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txc_data;
+    wire                                          txc_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_start_offset;
+    wire                                          txc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_end_offset;
+    wire                                          txc_data_ready;
+
+    wire                                          txc_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txc_meta_fdwbe;
+    wire [`SIG_LBE_W-1:0]                         txc_meta_ldwbe;
+    wire [`SIG_LOWADDR_W-1:0]                     txc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        txc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         txc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     txc_meta_byte_count;
+    wire [`SIG_TAG_W-1:0]                         txc_meta_tag;
+    wire [`SIG_REQID_W-1:0]                       txc_meta_requester_id;
+    wire [`SIG_TC_W-1:0]                          txc_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txc_meta_attr;
+    wire                                          txc_meta_ep;
+    wire                                          txc_meta_ready;
+    wire                                          txc_sent;
+
+    // Interface: TXR Engine
+    wire                                          txr_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txr_data;
+    wire                                          txr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_start_offset;
+    wire                                          txr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_end_offset;
+    wire                                          txr_data_ready;
+
+    wire                                          txr_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txr_meta_fdwbe; 
+    wire [`SIG_LBE_W-1:0]                         txr_meta_ldwbe;
+    wire [`SIG_ADDR_W-1:0]                        txr_meta_addr;
+    wire [`SIG_LEN_W-1:0]                         txr_meta_length;
+    wire [`SIG_TAG_W-1:0]                         txr_meta_tag;
+    wire [`SIG_TC_W-1:0]                          txr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txr_meta_attr;
+    wire [`SIG_TYPE_W-1:0]                        txr_meta_type;
+    wire                                          txr_meta_ep;
+    wire                                          txr_meta_ready;
+    wire                                          txr_sent;
+
+    // Unconnected Wires (Used in classic interface)
+    wire                                          wRxTlpReady_nc;
+    wire [C_PCI_DATA_WIDTH-1:0]                   wRxTlp_nc = 0;
+    wire                                          wRxTlpEndFlag_nc = 0;
+    wire [`SIG_OFFSET_W-1:0]                      wRxTlpEndOffset_nc = 0;
+    wire                                          wRxTlpStartFlag_nc = 0;
+    wire [`SIG_OFFSET_W-1:0]                      wRxTlpStartOffset_nc = 0;
+    wire                                          wRxTlpValid_nc = 0;
+    wire [`SIG_BARDECODE_W-1:0]                   wRxTlpBarDecode_nc = 0;
+    
+    wire                                          wTxTlpReady_nc = 0;
+    wire [C_PCI_DATA_WIDTH-1:0]                   wTxTlp_nc;
+    wire                                          wTxTlpEndFlag_nc;
+    wire [`SIG_OFFSET_W-1:0]                      wTxTlpEndOffset_nc;
+    wire                                          wTxTlpStartFlag_nc;
+    wire [`SIG_OFFSET_W-1:0]                      wTxTlpStartOffset_nc;
+    wire                                          wTxTlpValid_nc;
+
+    //--------------------------------------------------------------------------
+
+    // Interface: Configuration
+    wire                                          config_bus_master_enable;
+    wire [`SIG_CPLID_W-1:0]                       config_completer_id;
+    wire                                          config_cpl_boundary_sel;
+    wire                                          config_interrupt_msienable;
+    wire [`SIG_LINKRATE_W-1:0]                    config_link_rate;
+    wire [`SIG_LINKWIDTH_W-1:0]                   config_link_width;
+    wire [`SIG_MAXPAYLOAD_W-1:0]                  config_max_payload_size;
+    wire [`SIG_MAXREAD_W-1:0]                     config_max_read_request_size;
+    wire [`SIG_FC_CPLD_W-1:0]                     config_max_cpl_data;
+    wire [`SIG_FC_CPLH_W-1:0]                     config_max_cpl_hdr;
+
+    wire                                          intr_msi_request;
+    wire                                          intr_msi_rdy;
+
+    genvar                                        chnl;
+
+    assign clk = USER_CLK;
+    assign rst_in = USER_RESET;
+
+    assign config_completer_id = 0; // Not used in ULTRASCALE implementation
+    assign config_bus_master_enable = CFG_FUNCTION_STATUS[2];
+    assign config_link_width = {2'b00,CFG_NEGOTIATED_WIDTH}; // CONFIG_LINK_WIDTH
+    assign config_link_rate = CFG_CURRENT_SPEED[2]? 2'b11 : CFG_CURRENT_SPEED[2] ? 2'b10 : 2'b01;
+    assign config_max_payload_size = CFG_MAX_PAYLOAD; // CONFIG_MAX_PAYLOAD
+    assign config_max_read_request_size = CFG_MAX_READ_REQ; // CONFIG_MAX_READ_REQUEST
+    assign config_cpl_boundary_sel =  CFG_RCB_STATUS[0];
+    assign config_interrupt_msienable = CFG_INTERRUPT_MSI_ENABLE[0];
+    assign config_max_cpl_data = CFG_FC_CPLD;    
+    assign config_max_cpl_hdr = CFG_FC_CPLH;    
+
+    assign CFG_FC_SEL = 3'b001; // Always display credit maximum for the signals below
+    assign CFG_INTERRUPT_MSI_INT = {31'b0,intr_msi_request};
+    assign CFG_INTERRUPT_MSI_SELECT = 0;
+    assign CFG_INTERRUPT_INT = 0;
+    assign CFG_INTERRUPT_PENDING = 0;
+    assign CFG_INTERRUPT_MSI_SELECT = 0;
+    assign CFG_INTERRUPT_MSI_PENDING_STATUS = {63'b0,intr_msi_request};
+    assign CFG_INTERRUPT_MSI_ATTR = 0;
+    assign CFG_INTERRUPT_MSI_TPH_PRESENT = 0;
+    assign CFG_INTERRUPT_MSI_TPH_ST_TAG = 0;
+    assign CFG_INTERRUPT_MSI_TPH_TYPE = 0;
+    assign CFG_INTERRUPT_MSI_FUNCTION_NUMBER = 0;
+    
+    assign intr_msi_rdy = CFG_INTERRUPT_MSI_SENT & ~CFG_INTERRUPT_MSI_FAIL;
+
+    assign PCIE_CQ_NP_REQ = 1;
+    
+    engine_layer
+        #(// Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_BYTES/4),
+          .C_VENDOR                     (C_VENDOR))
+    engine_layer_inst
+        (// Outputs
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+         // Unconnected Outputs
+         .TX_TLP                        (wTxTlp_nc),
+         .TX_TLP_VALID                  (wTxTlpValid_nc),
+         .TX_TLP_START_FLAG             (wTxTlpStartFlag_nc),
+         .TX_TLP_START_OFFSET           (wTxTlpStartOffset_nc),
+         .TX_TLP_END_FLAG               (wTxTlpEndFlag_nc),
+         .TX_TLP_END_OFFSET             (wTxTlpEndOffset_nc),
+
+         .RX_TLP_READY                  (wRxTlpReady_nc),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+         // Unconnected Inputs
+         .RX_TLP                        (wRxTlp_nc),
+         .RX_TLP_VALID                  (wRxTlpValid_nc),
+         .RX_TLP_START_FLAG             (wRxTlpStartFlag_nc),
+         .RX_TLP_START_OFFSET           (wRxTlpStartOffset_nc),
+         .RX_TLP_END_FLAG               (wRxTlpEndFlag_nc),
+         .RX_TLP_END_OFFSET             (wRxTlpEndOffset_nc),
+         .RX_TLP_BAR_DECODE             (wRxTlpBarDecode_nc),
+
+         .TX_TLP_READY                  (wTxTlpReady_nc),
+         /*AUTOINST*/
+         // Outputs
+         .M_AXIS_CQ_TREADY              (M_AXIS_CQ_TREADY),
+         .M_AXIS_RC_TREADY              (M_AXIS_RC_TREADY),
+         .S_AXIS_CC_TVALID              (S_AXIS_CC_TVALID),
+         .S_AXIS_CC_TLAST               (S_AXIS_CC_TLAST),
+         .S_AXIS_CC_TDATA               (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (S_AXIS_RQ_TVALID),
+         .S_AXIS_RQ_TLAST               (S_AXIS_RQ_TLAST),
+         .S_AXIS_RQ_TDATA               (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (M_AXIS_CQ_TVALID),
+         .M_AXIS_CQ_TLAST               (M_AXIS_CQ_TLAST),
+         .M_AXIS_CQ_TDATA               (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (M_AXIS_CQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (M_AXIS_CQ_TUSER[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (M_AXIS_RC_TVALID),
+         .M_AXIS_RC_TLAST               (M_AXIS_RC_TLAST),
+         .M_AXIS_RC_TDATA               (M_AXIS_RC_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (M_AXIS_RC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (M_AXIS_RC_TUSER[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (S_AXIS_CC_TREADY),
+         .S_AXIS_RQ_TREADY              (S_AXIS_RQ_TREADY));
+
+    riffa
+        #(.C_TAG_WIDTH                  (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_MAX_READ_REQ_BYTES         (C_MAX_READ_REQ_BYTES),
+          .C_VENDOR                     (C_VENDOR),
+          .C_FPGA_NAME                  (C_FPGA_NAME))
+    riffa_inst
+        (// Outputs
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+
+         .INTR_MSI_REQUEST              (intr_msi_request),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),         
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE      (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH             (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE              (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE  (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE       (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE    (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL       (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA           (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR            (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+        
+         .INTR_MSI_RDY                  (intr_msi_rdy),
+
+         /*AUTOINST*/
+         // Outputs
+         .RST_OUT                       (RST_OUT),
+         .CHNL_RX                       (CHNL_RX[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_RX_OFF                   (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_RX_DATA                  (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
+         // Inputs
+         .CHNL_RX_CLK                   (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (CHNL_TX[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_TX_OFF                   (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_TX_DATA                  (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("../../engine/" "../../riffa/")
+// End:
+
diff --git a/fpga/xilinx/zc706/ZC706_Gen2x4If128/bit/ZC706Gen2x4If128.bit b/fpga/xilinx/zc706/ZC706_Gen2x4If128/bit/ZC706Gen2x4If128.bit
new file mode 100644
index 0000000..d706a9c
Binary files /dev/null and b/fpga/xilinx/zc706/ZC706_Gen2x4If128/bit/ZC706Gen2x4If128.bit differ
diff --git a/fpga/xilinx/zc706/ZC706_Gen2x4If128/constr/ZC706_Top.xdc b/fpga/xilinx/zc706/ZC706_Gen2x4If128/constr/ZC706_Top.xdc
new file mode 100644
index 0000000..108e53c
--- /dev/null
+++ b/fpga/xilinx/zc706/ZC706_Gen2x4If128/constr/ZC706_Top.xdc
@@ -0,0 +1,129 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            ZC706_Top.xdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Xilinx Design Constraints for the ZC706 board.
+# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin
+# 
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+##
+#########################################################################################################################
+# User Constraints
+#########################################################################################################################
+
+###############################################################################
+# User Time Names / User Time Groups / Time Specs
+###############################################################################
+
+###############################################################################
+# User Physical Constraints
+###############################################################################
+
+#
+# LED Status Indicators for Example Design.
+# LED 0-2 should be all ON if link is up and functioning correctly
+# LED 3 should be blinking if user application is receiving valid clock
+#
+
+#System Reset, User Reset, User Link Up, User Clk Heartbeat
+
+
+#########################################################################################################################
+# End User Constraints
+#########################################################################################################################
+#
+#
+#
+#########################################################################################################################
+# PCIE Core Constraints
+#########################################################################################################################
+
+#
+# SYS reset (input) signal.  The sys_reset_n signal should be
+# obtained from the PCI Express interface if possible.  For
+# slot based form factors, a system reset signal is usually
+# present on the connector.  For cable based form factors, a
+# system reset signal may not be available.  In this case, the
+# system reset signal must be generated locally by some form of
+# supervisory circuit.  You may change the IOSTANDARD and LOC
+# to suit your requirements and VCCO voltage banking rules.
+# Some 7 series devices do not have 3.3 V I/Os available.
+# Therefore the appropriate level shift is required to operate
+# with these devices that contain only 1.8 V banks.
+#
+set_property IOSTANDARD LVCMOS15 [get_ports PCIE_RESET_N]
+set_property PACKAGE_PIN AK23 [get_ports PCIE_RESET_N]
+set_property PULLUP true [get_ports PCIE_RESET_N]
+
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[1]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[2]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[3]}]
+set_property PACKAGE_PIN W21 [get_ports {LED[0]}]
+set_property PACKAGE_PIN G2 [get_ports {LED[1]}]
+set_property PACKAGE_PIN Y21 [get_ports {LED[2]}]
+set_property PACKAGE_PIN A17 [get_ports {LED[3]}]
+set_false_path -to [get_ports -filter NAME=~LED*]
+#
+#
+# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
+# signals are the PCI Express reference clock. Virtex-7 GT
+# Transceiver architecture requires the use of a dedicated clock
+# resources (FPGA input pins) associated with each GT Transceiver.
+# To use these pins an IBUFDS primitive (refclk_ibuf) is
+# instantiated in user's design.
+# Please refer to the Virtex-7 GT Transceiver User Guide
+# (UG) for guidelines regarding clock resource selection.
+#
+
+set_property LOC IBUFDS_GTE2_X0Y6 [get_cells refclk_ibuf]
+
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O]
+
+###############################################################################
+# Physical Constraints
+###############################################################################
+
+set_false_path -from [get_ports PCIE_RESET_N]
+###############################################################################
+# End
+###############################################################################
+
diff --git a/fpga/xilinx/zc706/ZC706_Gen2x4If128/hdl/ZC706Gen2x4If128.v b/fpga/xilinx/zc706/ZC706_Gen2x4If128/hdl/ZC706Gen2x4If128.v
new file mode 100644
index 0000000..3fae523
--- /dev/null
+++ b/fpga/xilinx/zc706/ZC706_Gen2x4If128/hdl/ZC706Gen2x4If128.v
@@ -0,0 +1,402 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            ZC706Gen2x4If128.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Xilinx ZC706 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "tlp.vh"
+`include "xilinx.vh"
+`timescale 1ps / 1ps
+module ZC706Gen2x4If128
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 12,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  4,
+      // Settings from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      )
+    (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
+     output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXP,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXN,
+
+     output [3:0]                   LED,
+     input                          PCIE_REFCLK_P,
+     input                          PCIE_REFCLK_N,
+     input                          PCIE_RESET_N
+     );
+
+    wire                            pcie_refclk;
+    wire                            pcie_reset_n;
+
+    wire                            user_clk;
+    wire                            user_reset;
+    wire                            user_lnk_up;
+    wire                            user_app_rdy;
+    
+    wire                            s_axis_tx_tready;
+    wire [C_PCI_DATA_WIDTH-1 : 0]   s_axis_tx_tdata;
+    wire [(C_PCI_DATA_WIDTH/8)-1 : 0] s_axis_tx_tkeep;
+    wire                              s_axis_tx_tlast;
+    wire                              s_axis_tx_tvalid;
+    wire [`SIG_XIL_TX_TUSER_W : 0]    s_axis_tx_tuser;
+    
+    wire [C_PCI_DATA_WIDTH-1 : 0]     m_axis_rx_tdata;
+    wire [(C_PCI_DATA_WIDTH/8)-1 : 0] m_axis_rx_tkeep;
+    wire                              m_axis_rx_tlast;
+    wire                              m_axis_rx_tvalid;
+    wire                              m_axis_rx_tready;
+    wire [`SIG_XIL_RX_TUSER_W - 1 : 0] m_axis_rx_tuser;
+    
+    wire                               tx_cfg_gnt;
+    wire                               rx_np_ok;
+    wire                               rx_np_req;
+    wire                               cfg_turnoff_ok;
+    wire                               cfg_trn_pending;
+    wire                               cfg_pm_halt_aspm_l0s;
+    wire                               cfg_pm_halt_aspm_l1;
+    wire                               cfg_pm_force_state_en;
+    wire [1:0]                         cfg_pm_force_state;
+    wire                               cfg_pm_wake;
+    wire [63:0]                        cfg_dsn;
+
+    wire [11 : 0]                      fc_cpld;
+    wire [7 : 0]                       fc_cplh;
+    wire [11 : 0]                      fc_npd;
+    wire [7 : 0]                       fc_nph;
+    wire [11 : 0]                      fc_pd;
+    wire [7 : 0]                       fc_ph;
+    wire [2 : 0]                       fc_sel;
+    
+    wire [15 : 0]                      cfg_status;
+    wire [15 : 0]                      cfg_command;
+    wire [15 : 0]                      cfg_dstatus;
+    wire [15 : 0]                      cfg_dcommand;
+    wire [15 : 0]                      cfg_lstatus;
+    wire [15 : 0]                      cfg_lcommand;
+    wire [15 : 0]                      cfg_dcommand2;
+    
+    wire [2 : 0]                       cfg_pcie_link_state;
+    wire                               cfg_pmcsr_pme_en;
+    wire [1 : 0]                       cfg_pmcsr_powerstate;
+    wire                               cfg_pmcsr_pme_status;
+    wire                               cfg_received_func_lvl_rst;
+    wire [4 : 0]                       cfg_pciecap_interrupt_msgnum;
+    wire                               cfg_to_turnoff;
+    wire [7 : 0]                       cfg_bus_number;
+    wire [4 : 0]                       cfg_device_number;
+    wire [2 : 0]                       cfg_function_number;
+
+    wire                               cfg_interrupt;
+    wire                               cfg_interrupt_rdy;
+    wire                               cfg_interrupt_assert;
+    wire [7 : 0]                       cfg_interrupt_di;
+    wire [7 : 0]                       cfg_interrupt_do;
+    wire [2 : 0]                       cfg_interrupt_mmenable;
+    wire                               cfg_interrupt_msien;
+    wire                               cfg_interrupt_msixenable;
+    wire                               cfg_interrupt_msixfm;
+    wire                               cfg_interrupt_stat;
+    
+
+
+    wire                               rst_out;
+    wire [C_NUM_CHNL-1:0]              chnl_rx_clk; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx_ack; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_rx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_ren;
+
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_clk; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_tx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_ren;
+
+    genvar                                     chnl;
+
+    assign cfg_turnoff_ok = 0;
+    assign cfg_trn_pending = 0;
+    assign cfg_pm_halt_aspm_l0s = 0;
+    assign cfg_pm_halt_aspm_l1 = 0;
+    assign cfg_pm_force_state_en = 0;
+    assign cfg_pm_force_state = 0;
+    assign cfg_dsn = 0;
+    assign cfg_interrupt_assert = 0;
+    assign cfg_interrupt_di = 0;
+    assign cfg_interrupt_stat = 0;
+    assign cfg_pciecap_interrupt_msgnum = 0;
+    assign cfg_turnoff_ok = 0;
+    assign cfg_pm_wake = 0;
+    
+    IBUF 
+        #()  
+    pci_reset_n_ibuf 
+        (.O(pcie_reset_n), 
+         .I(PCIE_RESET_N));
+
+    IBUFDS_GTE2 
+        #()
+    refclk_ibuf 
+        (.O(pcie_refclk), 
+         .ODIV2(), 
+         .I(PCIE_REFCLK_P), 
+         .CEB(1'b0), 
+         .IB(PCIE_REFCLK_N));
+
+    // Core Top Level Wrapper
+
+    PCIeGen2x4If128 PCIeGen2x4If128_i
+        (//---------------------------------------------------------------------
+         // PCI Express (pci_exp) Interface                                     
+         //---------------------------------------------------------------------
+         // Tx
+         .pci_exp_txn                               ( PCI_EXP_TXN ),
+         .pci_exp_txp                               ( PCI_EXP_TXP ),
+        
+         // Rx
+         .pci_exp_rxn                               ( PCI_EXP_RXN ),
+         .pci_exp_rxp                               ( PCI_EXP_RXP ),
+        
+         //---------------------------------------------------------------------
+         // AXI-S Interface                                                     
+         //---------------------------------------------------------------------
+         // Common
+         .user_clk_out                              ( user_clk ),
+         .user_reset_out                            ( user_reset ),
+         .user_lnk_up                               ( user_lnk_up ),
+         .user_app_rdy                              ( user_app_rdy ),
+        
+         // TX
+         .s_axis_tx_tready                          ( s_axis_tx_tready ),
+         .s_axis_tx_tdata                           ( s_axis_tx_tdata ),
+         .s_axis_tx_tkeep                           ( s_axis_tx_tkeep ),
+         .s_axis_tx_tuser                           ( s_axis_tx_tuser ),
+         .s_axis_tx_tlast                           ( s_axis_tx_tlast ),
+         .s_axis_tx_tvalid                          ( s_axis_tx_tvalid ),
+        
+         // Rx
+         .m_axis_rx_tdata                           ( m_axis_rx_tdata ),
+         .m_axis_rx_tkeep                           ( m_axis_rx_tkeep ),
+         .m_axis_rx_tlast                           ( m_axis_rx_tlast ),
+         .m_axis_rx_tvalid                          ( m_axis_rx_tvalid ),
+         .m_axis_rx_tready                          ( m_axis_rx_tready ),
+         .m_axis_rx_tuser                           ( m_axis_rx_tuser ),
+
+         .tx_cfg_gnt                                ( tx_cfg_gnt ),
+         .rx_np_ok                                  ( rx_np_ok ),
+         .rx_np_req                                 ( rx_np_req ),
+         .cfg_trn_pending                           ( cfg_trn_pending ),
+         .cfg_pm_halt_aspm_l0s                      ( cfg_pm_halt_aspm_l0s ),
+         .cfg_pm_halt_aspm_l1                       ( cfg_pm_halt_aspm_l1 ),
+         .cfg_pm_force_state_en                     ( cfg_pm_force_state_en ),
+         .cfg_pm_force_state                        ( cfg_pm_force_state ),
+         .cfg_dsn                                   ( cfg_dsn ),
+         .cfg_turnoff_ok                            ( cfg_turnoff_ok ),
+         .cfg_pm_wake                               ( cfg_pm_wake ),
+         .cfg_pm_send_pme_to                        ( 1'b0 ),
+         .cfg_ds_bus_number                         ( 8'b0 ),
+         .cfg_ds_device_number                      ( 5'b0 ),
+         .cfg_ds_function_number                    ( 3'b0 ),
+         //---------------------------------------------------------------------
+         // Flow Control Interface                                              
+         //---------------------------------------------------------------------
+         .fc_cpld                                   ( fc_cpld ),
+         .fc_cplh                                   ( fc_cplh ),
+         .fc_npd                                    ( fc_npd ),
+         .fc_nph                                    ( fc_nph ),
+         .fc_pd                                     ( fc_pd ),
+         .fc_ph                                     ( fc_ph ),
+         .fc_sel                                    ( fc_sel ),
+         
+         //---------------------------------------------------------------------
+         // Configuration (CFG) Interface                                       
+         //---------------------------------------------------------------------
+         .cfg_device_number                         ( cfg_device_number ),
+         .cfg_dcommand2                             ( cfg_dcommand2 ),
+         .cfg_pmcsr_pme_status                      ( cfg_pmcsr_pme_status ),
+         .cfg_status                                ( cfg_status ),
+         .cfg_to_turnoff                            ( cfg_to_turnoff ),
+         .cfg_received_func_lvl_rst                 ( cfg_received_func_lvl_rst ),
+         .cfg_dcommand                              ( cfg_dcommand ),
+         .cfg_bus_number                            ( cfg_bus_number ),
+         .cfg_function_number                       ( cfg_function_number ),
+         .cfg_command                               ( cfg_command ),
+         .cfg_dstatus                               ( cfg_dstatus ),
+         .cfg_lstatus                               ( cfg_lstatus ),
+         .cfg_pcie_link_state                       ( cfg_pcie_link_state ),
+         .cfg_lcommand                              ( cfg_lcommand ),
+         .cfg_pmcsr_pme_en                          ( cfg_pmcsr_pme_en ),
+         .cfg_pmcsr_powerstate                      ( cfg_pmcsr_powerstate ),
+         
+         //------------------------------------------------//
+         // EP Only                                        //
+         //------------------------------------------------//
+         .cfg_interrupt                             ( cfg_interrupt ),
+         .cfg_interrupt_rdy                         ( cfg_interrupt_rdy ),
+         .cfg_interrupt_assert                      ( cfg_interrupt_assert ),
+         .cfg_interrupt_di                          ( cfg_interrupt_di ),
+         .cfg_interrupt_do                          ( cfg_interrupt_do ),
+         .cfg_interrupt_mmenable                    ( cfg_interrupt_mmenable ),
+         .cfg_interrupt_msienable                   ( cfg_interrupt_msien ),
+         .cfg_interrupt_msixenable                  ( cfg_interrupt_msixenable ),
+         .cfg_interrupt_msixfm                      ( cfg_interrupt_msixfm ),
+         .cfg_interrupt_stat                        ( cfg_interrupt_stat ),
+         .cfg_pciecap_interrupt_msgnum              ( cfg_pciecap_interrupt_msgnum ),
+         //---------------------------------------------------------------------
+         // System  (SYS) Interface                                             
+         //---------------------------------------------------------------------
+         .sys_clk                                    ( pcie_refclk ),
+         .sys_rst_n                                  ( pcie_reset_n )
+         
+         );
+
+
+    riffa_wrapper_zc706
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .CFG_INTERRUPT                 (cfg_interrupt),
+         .M_AXIS_RX_TREADY              (m_axis_rx_tready),
+         .S_AXIS_TX_TDATA               (s_axis_tx_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_TX_TKEEP               (s_axis_tx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .S_AXIS_TX_TLAST               (s_axis_tx_tlast),
+         .S_AXIS_TX_TVALID              (s_axis_tx_tvalid),
+         .S_AXIS_TX_TUSER               (s_axis_tx_tuser[`SIG_XIL_TX_TUSER_W-1:0]),
+         .FC_SEL                        (fc_sel[`SIG_FC_SEL_W-1:0]),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .M_AXIS_RX_TDATA               (m_axis_rx_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RX_TKEEP               (m_axis_rx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .M_AXIS_RX_TLAST               (m_axis_rx_tlast),
+         .M_AXIS_RX_TVALID              (m_axis_rx_tvalid),
+         .M_AXIS_RX_TUSER               (m_axis_rx_tuser[`SIG_XIL_RX_TUSER_W-1:0]),
+         .S_AXIS_TX_TREADY              (s_axis_tx_tready),
+         .CFG_BUS_NUMBER                (cfg_bus_number[`SIG_BUSID_W-1:0]),
+         .CFG_DEVICE_NUMBER             (cfg_device_number[`SIG_DEVID_W-1:0]),
+         .CFG_FUNCTION_NUMBER           (cfg_function_number[`SIG_FNID_W-1:0]),
+         .CFG_COMMAND                   (cfg_command[`SIG_CFGREG_W-1:0]),
+         .CFG_DCOMMAND                  (cfg_dcommand[`SIG_CFGREG_W-1:0]),
+         .CFG_LSTATUS                   (cfg_lstatus[`SIG_CFGREG_W-1:0]),
+         .CFG_LCOMMAND                  (cfg_lcommand[`SIG_CFGREG_W-1:0]),
+         .FC_CPLD                       (fc_cpld[`SIG_FC_CPLD_W-1:0]),
+         .FC_CPLH                       (fc_cplh[`SIG_FC_CPLH_W-1:0]),
+         .CFG_INTERRUPT_MSIEN           (cfg_interrupt_msien),
+         .CFG_INTERRUPT_RDY             (cfg_interrupt_rdy),
+         .USER_CLK                      (user_clk),
+         .USER_RESET                    (user_reset),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]),
+         .RX_NP_OK                      (rx_np_ok),
+         .RX_NP_REQ                     (rx_np_req),
+         .TX_CFG_GNT                    (tx_cfg_gnt)
+         /*AUTOINST*/);
+
+
+    generate
+        for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
+            chnl_tester 
+                    #(
+                      .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                      ) 
+            module1 
+                    (.CLK(user_clk),
+                     .RST(rst_out),    // riffa_reset includes riffa_endpoint resets
+                     // Rx interface
+                     .CHNL_RX_CLK(chnl_rx_clk[chnl]), 
+                     .CHNL_RX(chnl_rx[chnl]), 
+                     .CHNL_RX_ACK(chnl_rx_ack[chnl]), 
+                     .CHNL_RX_LAST(chnl_rx_last[chnl]), 
+                     .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), 
+                     .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), 
+                     .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), 
+                     .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
+                     // Tx interface
+                     .CHNL_TX_CLK(chnl_tx_clk[chnl]), 
+                     .CHNL_TX(chnl_tx[chnl]), 
+                     .CHNL_TX_ACK(chnl_tx_ack[chnl]), 
+                     .CHNL_TX_LAST(chnl_tx_last[chnl]), 
+                     .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), 
+                     .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), 
+                     .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), 
+                     .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
+                     );    
+        end
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/")
+// End:
+
diff --git a/fpga/xilinx/zc706/ZC706_Gen2x4If128/ip/PCIeGen2x4If128.xci b/fpga/xilinx/zc706/ZC706_Gen2x4If128/ip/PCIeGen2x4If128.xci
new file mode 100644
index 0000000..9099db0
--- /dev/null
+++ b/fpga/xilinx/zc706/ZC706_Gen2x4If128/ip/PCIeGen2x4If128.xci
@@ -0,0 +1,479 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Prefetchable">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Scale">Kilobytes</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Type">N/A</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IO_Base_Limit_Registers">Disabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Prefetchable_Memory_Base_Limit_Registers">Disabled</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Revision_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Subsystem_Vendor_ID">10EE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Class_Code_Base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Class_Code_Sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Class_Code_Interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Base_Class_Menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Sub_Class_Interface_Menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cardbus_CIS_Pointer">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Cap_Slot_Implemented">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Max_Payload_Size">256_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Extended_Tag_Field">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Extended_Tag_Default">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phantom_Functions">No_function_number_bits_used</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Acceptable_L0s_Latency">Maximum_of_64_ns</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Acceptable_L1_Latency">No_limit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cpl_Finite">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cpl_Timeout_Disable_Sup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cpl_Timeout_Range">Range_B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Buf_Opt_BMA">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Perf_Level">High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dll_Link_Active_Cap">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RCB">64_byte</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Trgt_Link_Speed">4&apos;h2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Hw_Auton_Spd_Disable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.De_emph">-3.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Slot_Clock_Cfg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Root_Cap_CRS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Attn_Butn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Ctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_MRL">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Attn_Ind">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Ind">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_HotPlug_Surprise">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_HotPlug_Cap">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Elec_Interlock">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_No_Cmd_Comp_Sup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Limit_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Limit_Scale">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Physical_Slot_Num">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IntX_Generation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Legacy_Interrupt">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_64b">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Multiple_Message_Capable">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_Vec_Mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_Size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_Offset">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_PBA_Offset">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_Specific_Initialization">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3hot_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3cold_PME_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Soft_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DSN_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VC_Cap_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VC_Cap_Reject_Snoop">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VSEC_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCI_CFG_Space">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCI_CFG_Space_Addr">3F</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXT_PCI_CFG_Space">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXT_PCI_CFG_Space_Addr">3FF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Xlnx_Ref_Board">ZC706</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Blk_Locn">X0Y0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Trans_Buf_Pipeline">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_unlock">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pme_to">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_cor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_nfl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_ftl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_inta">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pm_pme">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pme_to_ack">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Receive_NP_Request">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ACK_NAK_Timer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACK_NAK_Timeout_Func">Absolute</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACK_NAK_Timeout_Value">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Replay_Timer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Replay_Timeout_Func">Add</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Replay_Timeout_Value">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Lane_Reversal">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Upconfigure_Capable">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Force_No_Scrambling">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Tx_ASPM_L0s">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Downstream_Link_Num">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_INV_REQ">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_PRS_RESPONSE">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Silicon_Rev">GES_and_Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pcie_fast_config">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Debug_Ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Ref_Clk_Freq">100_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cost_Table">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_Atomic">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ATOMICOP64_Completer_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CAS128_Completer_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TPH_Completer_Supported">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARI_Forwarding_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AtomicOp_Routing_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASPM_Optionality">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Check_Capable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Gen_Capable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Multiheader">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Permit_Root_Error_Update">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Header_Log_Overflow">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Surprise_Down">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Flow_Control_Protocol_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Completion_Timeout">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Completer_Abort">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Receiver_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Error">false</spirit:configurableElementValue>
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diff --git a/fpga/xilinx/zc706/ZC706_Gen2x4If128/prj/ZC706_Gen2x4If128.xpr b/fpga/xilinx/zc706/ZC706_Gen2x4If128/prj/ZC706_Gen2x4If128.xpr
new file mode 100644
index 0000000..f7fd491
--- /dev/null
+++ b/fpga/xilinx/zc706/ZC706_Gen2x4If128/prj/ZC706_Gen2x4If128.xpr
@@ -0,0 +1,786 @@
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+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_multiplexer_128.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tlp.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxc_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/ultrascale.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxc_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel_32.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/txc_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/txc_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel_128.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue_output.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxr_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_multiplexer_64.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel_64.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxr_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/txr_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/txr_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/interrupt_controller.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue_input.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/riffa.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/registers.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/recv_credit_flow_ctrl.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rx_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/interrupt.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_multiplexer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rx_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/engine_layer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/xilinx.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/translation_xilinx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/riffa.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/chnl_tester.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../riffa_wrapper_zc706.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../hdl/ZC706Gen2x4If128.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/altera.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="ZC706Gen2x4If128"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../constr/ZC706_Top.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/ZC706_Top.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="ZC706Gen2x4If128"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="SimMode" Val="post-implementation"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="PCIeGen2x4If128" Type="BlockSrcs" RelSrcDir="$PSRCDIR/PCIeGen2x4If128">
+      <File Path="$PPRDIR/../ip/PCIeGen2x4If128.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="PCIeGen2x4If128"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="9">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z045ffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen2x4If128_synth_1" Type="Ft3:Synth" SrcSet="PCIeGen2x4If128" Part="xc7z045ffg900-2" ConstrsSet="PCIeGen2x4If128" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/PCIeGen2x4If128_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen2x4If128_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="PCIeGen2x4If128" Description="Vivado Implementation Defaults" SynthRun="PCIeGen2x4If128_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+  </Runs>
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</Project>
diff --git a/fpga/xilinx/zc706/ZC706_Gen2x4If64/bit/ZC706Gen2x4If64.bit b/fpga/xilinx/zc706/ZC706_Gen2x4If64/bit/ZC706Gen2x4If64.bit
new file mode 100644
index 0000000..f0a6ae3
Binary files /dev/null and b/fpga/xilinx/zc706/ZC706_Gen2x4If64/bit/ZC706Gen2x4If64.bit differ
diff --git a/fpga/xilinx/zc706/ZC706_Gen2x4If64/constr/ZC706_Top.xdc b/fpga/xilinx/zc706/ZC706_Gen2x4If64/constr/ZC706_Top.xdc
new file mode 100644
index 0000000..33905cf
--- /dev/null
+++ b/fpga/xilinx/zc706/ZC706_Gen2x4If64/constr/ZC706_Top.xdc
@@ -0,0 +1,129 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            ZC706_Top.xdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Xilinx Design Constraints for the ZC706 board.
+# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin
+# 
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+#
+#########################################################################################################################
+# User Constraints
+#########################################################################################################################
+
+###############################################################################
+# User Time Names / User Time Groups / Time Specs
+###############################################################################
+
+###############################################################################
+# User Physical Constraints
+###############################################################################
+
+#
+# LED Status Indicators for Example Design.
+# LED 0-2 should be all ON if link is up and functioning correctly
+# LED 3 should be blinking if user application is receiving valid clock
+#
+
+#System Reset, User Reset, User Link Up, User Clk Heartbeat
+
+
+#########################################################################################################################
+# End User Constraints
+#########################################################################################################################
+#
+#
+#
+#########################################################################################################################
+# PCIE Core Constraints
+#########################################################################################################################
+
+#
+# SYS reset (input) signal.  The sys_reset_n signal should be
+# obtained from the PCI Express interface if possible.  For
+# slot based form factors, a system reset signal is usually
+# present on the connector.  For cable based form factors, a
+# system reset signal may not be available.  In this case, the
+# system reset signal must be generated locally by some form of
+# supervisory circuit.  You may change the IOSTANDARD and LOC
+# to suit your requirements and VCCO voltage banking rules.
+# Some 7 series devices do not have 3.3 V I/Os available.
+# Therefore the appropriate level shift is required to operate
+# with these devices that contain only 1.8 V banks.
+#
+set_property IOSTANDARD LVCMOS15 [get_ports PCIE_RESET_N]
+set_property PACKAGE_PIN AK23 [get_ports PCIE_RESET_N]
+set_property PULLUP true [get_ports PCIE_RESET_N]
+
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[1]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[2]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[3]}]
+set_property PACKAGE_PIN W21 [get_ports {LED[0]}]
+set_property PACKAGE_PIN G2 [get_ports {LED[1]}]
+set_property PACKAGE_PIN Y21 [get_ports {LED[2]}]
+set_property PACKAGE_PIN A17 [get_ports {LED[3]}]
+set_false_path -to [get_ports -filter NAME=~LED*]
+#
+#
+# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
+# signals are the PCI Express reference clock. Virtex-7 GT
+# Transceiver architecture requires the use of a dedicated clock
+# resources (FPGA input pins) associated with each GT Transceiver.
+# To use these pins an IBUFDS primitive (refclk_ibuf) is
+# instantiated in user's design.
+# Please refer to the Virtex-7 GT Transceiver User Guide
+# (UG) for guidelines regarding clock resource selection.
+#
+
+set_property LOC IBUFDS_GTE2_X0Y6 [get_cells refclk_ibuf]
+
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O]
+
+###############################################################################
+# Physical Constraints
+###############################################################################
+
+set_false_path -from [get_ports PCIE_RESET_N]
+###############################################################################
+# End
+###############################################################################
+
diff --git a/fpga/xilinx/zc706/ZC706_Gen2x4If64/hdl/ZC706Gen2x4If64.v b/fpga/xilinx/zc706/ZC706_Gen2x4If64/hdl/ZC706Gen2x4If64.v
new file mode 100644
index 0000000..27927d9
--- /dev/null
+++ b/fpga/xilinx/zc706/ZC706_Gen2x4If64/hdl/ZC706Gen2x4If64.v
@@ -0,0 +1,404 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            ZC706Gen2x4If64.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Xilinx ZC706 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "tlp.vh"
+`include "xilinx.vh"
+`timescale 1ps / 1ps
+module ZC706Gen2x4If64
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 12,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  4,
+      // Settings from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 64,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
+     output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXP,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXN,
+
+     output [3:0]                   LED,
+     input                          PCIE_REFCLK_P,
+     input                          PCIE_REFCLK_N,
+     input                          PCIE_RESET_N
+     );
+
+    wire                            pcie_refclk;
+    wire                            pcie_reset_n;
+
+    wire                            user_clk;
+    wire                            user_reset;
+    wire                            user_lnk_up;
+    wire                            user_app_rdy;
+    
+    wire                            s_axis_tx_tready;
+    wire [C_PCI_DATA_WIDTH-1 : 0]   s_axis_tx_tdata;
+    wire [(C_PCI_DATA_WIDTH/8)-1 : 0] s_axis_tx_tkeep;
+    wire                              s_axis_tx_tlast;
+    wire                              s_axis_tx_tvalid;
+    wire [`SIG_XIL_TX_TUSER_W : 0]    s_axis_tx_tuser;
+    
+    wire [C_PCI_DATA_WIDTH-1 : 0]     m_axis_rx_tdata;
+    wire [(C_PCI_DATA_WIDTH/8)-1 : 0] m_axis_rx_tkeep;
+    wire                              m_axis_rx_tlast;
+    wire                              m_axis_rx_tvalid;
+    wire                              m_axis_rx_tready;
+    wire [`SIG_XIL_RX_TUSER_W - 1 : 0] m_axis_rx_tuser;
+    
+    wire                               tx_cfg_gnt;
+    wire                               rx_np_ok;
+    wire                               rx_np_req;
+    wire                               cfg_turnoff_ok;
+    wire                               cfg_trn_pending;
+    wire                               cfg_pm_halt_aspm_l0s;
+    wire                               cfg_pm_halt_aspm_l1;
+    wire                               cfg_pm_force_state_en;
+    wire [1:0]                         cfg_pm_force_state;
+    wire                               cfg_pm_wake;
+    wire [63:0]                        cfg_dsn;
+
+    wire [11 : 0]                      fc_cpld;
+    wire [7 : 0]                       fc_cplh;
+    wire [11 : 0]                      fc_npd;
+    wire [7 : 0]                       fc_nph;
+    wire [11 : 0]                      fc_pd;
+    wire [7 : 0]                       fc_ph;
+    wire [2 : 0]                       fc_sel;
+    
+    wire [15 : 0]                      cfg_status;
+    wire [15 : 0]                      cfg_command;
+    wire [15 : 0]                      cfg_dstatus;
+    wire [15 : 0]                      cfg_dcommand;
+    wire [15 : 0]                      cfg_lstatus;
+    wire [15 : 0]                      cfg_lcommand;
+    wire [15 : 0]                      cfg_dcommand2;
+    
+    wire [2 : 0]                       cfg_pcie_link_state;
+    wire                               cfg_pmcsr_pme_en;
+    wire [1 : 0]                       cfg_pmcsr_powerstate;
+    wire                               cfg_pmcsr_pme_status;
+    wire                               cfg_received_func_lvl_rst;
+    wire [4 : 0]                       cfg_pciecap_interrupt_msgnum;
+    wire                               cfg_to_turnoff;
+    wire [7 : 0]                       cfg_bus_number;
+    wire [4 : 0]                       cfg_device_number;
+    wire [2 : 0]                       cfg_function_number;
+
+    wire                               cfg_interrupt;
+    wire                               cfg_interrupt_rdy;
+    wire                               cfg_interrupt_assert;
+    wire [7 : 0]                       cfg_interrupt_di;
+    wire [7 : 0]                       cfg_interrupt_do;
+    wire [2 : 0]                       cfg_interrupt_mmenable;
+    wire                               cfg_interrupt_msien;
+    wire                               cfg_interrupt_msixenable;
+    wire                               cfg_interrupt_msixfm;
+    wire                               cfg_interrupt_stat;
+    
+
+
+    wire                               rst_out;
+    wire [C_NUM_CHNL-1:0]              chnl_rx_clk; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx_ack; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_rx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_ren;
+
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_clk; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_tx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_ren;
+
+    genvar                                     chnl;
+
+    assign cfg_turnoff_ok = 0;
+    assign cfg_trn_pending = 0;
+    assign cfg_pm_halt_aspm_l0s = 0;
+    assign cfg_pm_halt_aspm_l1 = 0;
+    assign cfg_pm_force_state_en = 0;
+    assign cfg_pm_force_state = 0;
+    assign cfg_dsn = 0;
+    assign cfg_interrupt_assert = 0;
+    assign cfg_interrupt_di = 0;
+    assign cfg_interrupt_stat = 0;
+    assign cfg_pciecap_interrupt_msgnum = 0;
+    assign cfg_turnoff_ok = 0;
+    assign cfg_pm_wake = 0;
+
+    IBUF 
+        #()  
+    pci_reset_n_ibuf 
+        (.O(pcie_reset_n), 
+         .I(PCIE_RESET_N));
+
+    IBUFDS_GTE2 
+        #()
+    refclk_ibuf 
+        (.O(pcie_refclk), 
+         .ODIV2(), 
+         .I(PCIE_REFCLK_P), 
+         .CEB(1'b0), 
+         .IB(PCIE_REFCLK_N));
+
+    // Core Top Level Wrapper
+
+    PCIeGen2x4If64 PCIeGen2x4If64_i
+        (
+        
+         //---------------------------------------------------------------------
+         // PCI Express (pci_exp) Interface                                     
+         //---------------------------------------------------------------------
+         // Tx
+         .pci_exp_txn                               ( PCI_EXP_TXN ),
+         .pci_exp_txp                               ( PCI_EXP_TXP ),
+        
+         // Rx
+         .pci_exp_rxn                               ( PCI_EXP_RXN ),
+         .pci_exp_rxp                               ( PCI_EXP_RXP ),
+        
+         //---------------------------------------------------------------------
+         // AXI-S Interface                                                     
+         //---------------------------------------------------------------------
+         // Common
+         .user_clk_out                              ( user_clk ),
+         .user_reset_out                            ( user_reset ),
+         .user_lnk_up                               ( user_lnk_up ),
+         .user_app_rdy                              ( user_app_rdy ),
+        
+         // TX
+         .s_axis_tx_tready                          ( s_axis_tx_tready ),
+         .s_axis_tx_tdata                           ( s_axis_tx_tdata ),
+         .s_axis_tx_tkeep                           ( s_axis_tx_tkeep ),
+         .s_axis_tx_tuser                           ( s_axis_tx_tuser ),
+         .s_axis_tx_tlast                           ( s_axis_tx_tlast ),
+         .s_axis_tx_tvalid                          ( s_axis_tx_tvalid ),
+        
+         // Rx
+         .m_axis_rx_tdata                           ( m_axis_rx_tdata ),
+         .m_axis_rx_tkeep                           ( m_axis_rx_tkeep ),
+         .m_axis_rx_tlast                           ( m_axis_rx_tlast ),
+         .m_axis_rx_tvalid                          ( m_axis_rx_tvalid ),
+         .m_axis_rx_tready                          ( m_axis_rx_tready ),
+         .m_axis_rx_tuser                           ( m_axis_rx_tuser ),
+
+         .tx_cfg_gnt                                ( tx_cfg_gnt ),
+         .rx_np_ok                                  ( rx_np_ok ),
+         .rx_np_req                                 ( rx_np_req ),
+         .cfg_trn_pending                           ( cfg_trn_pending ),
+         .cfg_pm_halt_aspm_l0s                      ( cfg_pm_halt_aspm_l0s ),
+         .cfg_pm_halt_aspm_l1                       ( cfg_pm_halt_aspm_l1 ),
+         .cfg_pm_force_state_en                     ( cfg_pm_force_state_en ),
+         .cfg_pm_force_state                        ( cfg_pm_force_state ),
+         .cfg_dsn                                   ( cfg_dsn ),
+         .cfg_turnoff_ok                            ( cfg_turnoff_ok ),
+         .cfg_pm_wake                               ( cfg_pm_wake ),
+         .cfg_pm_send_pme_to                        ( 1'b0 ),
+         .cfg_ds_bus_number                         ( 8'b0 ),
+         .cfg_ds_device_number                      ( 5'b0 ),
+         .cfg_ds_function_number                    ( 3'b0 ),
+         //---------------------------------------------------------------------
+         // Flow Control Interface                                              
+         //---------------------------------------------------------------------
+         .fc_cpld                                   ( fc_cpld ),
+         .fc_cplh                                   ( fc_cplh ),
+         .fc_npd                                    ( fc_npd ),
+         .fc_nph                                    ( fc_nph ),
+         .fc_pd                                     ( fc_pd ),
+         .fc_ph                                     ( fc_ph ),
+         .fc_sel                                    ( fc_sel ),
+         
+         //---------------------------------------------------------------------
+         // Configuration (CFG) Interface                                       
+         //---------------------------------------------------------------------
+         .cfg_device_number                         ( cfg_device_number ),
+         .cfg_dcommand2                             ( cfg_dcommand2 ),
+         .cfg_pmcsr_pme_status                      ( cfg_pmcsr_pme_status ),
+         .cfg_status                                ( cfg_status ),
+         .cfg_to_turnoff                            ( cfg_to_turnoff ),
+         .cfg_received_func_lvl_rst                 ( cfg_received_func_lvl_rst ),
+         .cfg_dcommand                              ( cfg_dcommand ),
+         .cfg_bus_number                            ( cfg_bus_number ),
+         .cfg_function_number                       ( cfg_function_number ),
+         .cfg_command                               ( cfg_command ),
+         .cfg_dstatus                               ( cfg_dstatus ),
+         .cfg_lstatus                               ( cfg_lstatus ),
+         .cfg_pcie_link_state                       ( cfg_pcie_link_state ),
+         .cfg_lcommand                              ( cfg_lcommand ),
+         .cfg_pmcsr_pme_en                          ( cfg_pmcsr_pme_en ),
+         .cfg_pmcsr_powerstate                      ( cfg_pmcsr_powerstate ),
+         
+         //------------------------------------------------//
+         // EP Only                                        //
+         //------------------------------------------------//
+         .cfg_interrupt                             ( cfg_interrupt ),
+         .cfg_interrupt_rdy                         ( cfg_interrupt_rdy ),
+         .cfg_interrupt_assert                      ( cfg_interrupt_assert ),
+         .cfg_interrupt_di                          ( cfg_interrupt_di ),
+         .cfg_interrupt_do                          ( cfg_interrupt_do ),
+         .cfg_interrupt_mmenable                    ( cfg_interrupt_mmenable ),
+         .cfg_interrupt_msienable                   ( cfg_interrupt_msien ),
+         .cfg_interrupt_msixenable                  ( cfg_interrupt_msixenable ),
+         .cfg_interrupt_msixfm                      ( cfg_interrupt_msixfm ),
+         .cfg_interrupt_stat                        ( cfg_interrupt_stat ),
+         .cfg_pciecap_interrupt_msgnum              ( cfg_pciecap_interrupt_msgnum ),
+         //---------------------------------------------------------------------
+         // System  (SYS) Interface                                             
+         //---------------------------------------------------------------------
+         .sys_clk                                    ( pcie_refclk ),
+         .sys_rst_n                                  ( pcie_reset_n )
+         
+         );
+
+
+    riffa_wrapper_zc706
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .CFG_INTERRUPT                 (cfg_interrupt),
+         .M_AXIS_RX_TREADY              (m_axis_rx_tready),
+         .S_AXIS_TX_TDATA               (s_axis_tx_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_TX_TKEEP               (s_axis_tx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .S_AXIS_TX_TLAST               (s_axis_tx_tlast),
+         .S_AXIS_TX_TVALID              (s_axis_tx_tvalid),
+         .S_AXIS_TX_TUSER               (s_axis_tx_tuser[`SIG_XIL_TX_TUSER_W-1:0]),
+         .FC_SEL                        (fc_sel[`SIG_FC_SEL_W-1:0]),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .M_AXIS_RX_TDATA               (m_axis_rx_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RX_TKEEP               (m_axis_rx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .M_AXIS_RX_TLAST               (m_axis_rx_tlast),
+         .M_AXIS_RX_TVALID              (m_axis_rx_tvalid),
+         .M_AXIS_RX_TUSER               (m_axis_rx_tuser[`SIG_XIL_RX_TUSER_W-1:0]),
+         .S_AXIS_TX_TREADY              (s_axis_tx_tready),
+         .CFG_BUS_NUMBER                (cfg_bus_number[`SIG_BUSID_W-1:0]),
+         .CFG_DEVICE_NUMBER             (cfg_device_number[`SIG_DEVID_W-1:0]),
+         .CFG_FUNCTION_NUMBER           (cfg_function_number[`SIG_FNID_W-1:0]),
+         .CFG_COMMAND                   (cfg_command[`SIG_CFGREG_W-1:0]),
+         .CFG_DCOMMAND                  (cfg_dcommand[`SIG_CFGREG_W-1:0]),
+         .CFG_LSTATUS                   (cfg_lstatus[`SIG_CFGREG_W-1:0]),
+         .CFG_LCOMMAND                  (cfg_lcommand[`SIG_CFGREG_W-1:0]),
+         .FC_CPLD                       (fc_cpld[`SIG_FC_CPLD_W-1:0]),
+         .FC_CPLH                       (fc_cplh[`SIG_FC_CPLH_W-1:0]),
+         .CFG_INTERRUPT_MSIEN           (cfg_interrupt_msien),
+         .CFG_INTERRUPT_RDY             (cfg_interrupt_rdy),
+         .USER_CLK                      (user_clk),
+         .USER_RESET                    (user_reset),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]),
+         .RX_NP_OK                      (rx_np_ok),
+         .RX_NP_REQ                     (rx_np_req),
+         .TX_CFG_GNT                    (tx_cfg_gnt)
+         /*AUTOINST*/);
+
+
+    generate
+        for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
+            chnl_tester 
+                    #(
+                      .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                      ) 
+            module1 
+                    (.CLK(user_clk),
+                     .RST(rst_out),    // riffa_reset includes riffa_endpoint resets
+                     // Rx interface
+                     .CHNL_RX_CLK(chnl_rx_clk[chnl]), 
+                     .CHNL_RX(chnl_rx[chnl]), 
+                     .CHNL_RX_ACK(chnl_rx_ack[chnl]), 
+                     .CHNL_RX_LAST(chnl_rx_last[chnl]), 
+                     .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), 
+                     .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), 
+                     .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), 
+                     .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
+                     // Tx interface
+                     .CHNL_TX_CLK(chnl_tx_clk[chnl]), 
+                     .CHNL_TX(chnl_tx[chnl]), 
+                     .CHNL_TX_ACK(chnl_tx_ack[chnl]), 
+                     .CHNL_TX_LAST(chnl_tx_last[chnl]), 
+                     .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), 
+                     .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), 
+                     .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), 
+                     .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
+                     );    
+        end
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/")
+// End:
+
diff --git a/fpga/xilinx/zc706/ZC706_Gen2x4If64/ip/PCIeGen2x4If64.xci b/fpga/xilinx/zc706/ZC706_Gen2x4If64/ip/PCIeGen2x4If64.xci
new file mode 100644
index 0000000..9fa1985
--- /dev/null
+++ b/fpga/xilinx/zc706/ZC706_Gen2x4If64/ip/PCIeGen2x4If64.xci
@@ -0,0 +1,479 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>PCIeGen2x4If64</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie_7x" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Advanced</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">PCIeGen2x4If64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_Port_Type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Maximum_Link_Width">X4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Link_Speed">5.0_GT/s</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Width">64_bit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.User_Clk_Freq">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IO_Base_Limit_Registers">Disabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Prefetchable_Memory_Base_Limit_Registers">Disabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Vendor_ID">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_ID">7024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Revision_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Subsystem_Vendor_ID">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Subsystem_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Class_Code_Base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Class_Code_Sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Class_Code_Interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Base_Class_Menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Sub_Class_Interface_Menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cardbus_CIS_Pointer">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Cap_Slot_Implemented">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Max_Payload_Size">256_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Extended_Tag_Field">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Extended_Tag_Default">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phantom_Functions">No_function_number_bits_used</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Acceptable_L0s_Latency">Maximum_of_64_ns</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Acceptable_L1_Latency">No_limit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cpl_Finite">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cpl_Timeout_Disable_Sup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cpl_Timeout_Range">Range_B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Buf_Opt_BMA">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Perf_Level">High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dll_Link_Active_Cap">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RCB">64_byte</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Trgt_Link_Speed">4&apos;h2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Hw_Auton_Spd_Disable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.De_emph">-3.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Slot_Clock_Cfg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Root_Cap_CRS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Attn_Butn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Ctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_MRL">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Attn_Ind">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Ind">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_HotPlug_Surprise">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_HotPlug_Cap">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Elec_Interlock">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_No_Cmd_Comp_Sup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Limit_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Limit_Scale">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Physical_Slot_Num">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IntX_Generation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Legacy_Interrupt">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_64b">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Multiple_Message_Capable">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_Vec_Mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_Size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_Offset">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_PBA_Offset">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_Specific_Initialization">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3hot_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3cold_PME_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Soft_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DSN_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VC_Cap_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VC_Cap_Reject_Snoop">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VSEC_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCI_CFG_Space">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCI_CFG_Space_Addr">3F</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXT_PCI_CFG_Space">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXT_PCI_CFG_Space_Addr">3FF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Xlnx_Ref_Board">ZC706</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Blk_Locn">X0Y0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Trans_Buf_Pipeline">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_unlock">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pme_to">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_cor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_nfl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_ftl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_inta">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pm_pme">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pme_to_ack">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Receive_NP_Request">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ACK_NAK_Timer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACK_NAK_Timeout_Func">Absolute</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACK_NAK_Timeout_Value">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Replay_Timer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Replay_Timeout_Func">Add</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Replay_Timeout_Value">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Lane_Reversal">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Upconfigure_Capable">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Force_No_Scrambling">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Tx_ASPM_L0s">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Downstream_Link_Num">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_INV_REQ">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_PRS_RESPONSE">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Silicon_Rev">GES_and_Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pcie_fast_config">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Debug_Ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Ref_Clk_Freq">100_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cost_Table">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_Atomic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ATOMICOP32_Completer_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ATOMICOP64_Completer_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CAS128_Completer_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TPH_Completer_Supported">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARI_Forwarding_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AtomicOp_Routing_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASPM_Optionality">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Check_Capable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Gen_Capable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Multiheader">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Permit_Root_Error_Update">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Correctable_Internal_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Header_Log_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Receiver_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Surprise_Down">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Flow_Control_Protocol_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Completion_Timeout">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Completer_Abort">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Receiver_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ACS_Violation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Uncorrectable_Internal_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_MC_Blocked_TLP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_AtomicOp_Egress_Blocked">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_TLP_Prefix_Blocked">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optional_Error_Support">000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Num">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR0_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR1_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR2_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR3_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR4_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR5_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECRC_Check">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECRC_Check_Trim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Rx_Poisoned_Resp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_gt_common">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.shared_logic_in_core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pl_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_mgmt_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ctl_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_status_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rcv_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_fc_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.err_reporting_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_pipe_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_startup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_mode_sim">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">PCIeGen2x4If64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dev_port_type">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_dev_port_type">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_header_type">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_upstream_facing">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.max_lnk_wdt">000100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.max_lnk_spd">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gen1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pci_exp_int_freq">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_pcie_fast_config">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_0">FFFFFC00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_5">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.xrom_bar">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.cost_table">1</spirit:configurableElementValue>
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new file mode 100644
index 0000000..bed0e71
--- /dev/null
+++ b/fpga/xilinx/zc706/ZC706_Gen2x4If64/prj/ZC706_Gen2x4If64.xpr
@@ -0,0 +1,786 @@
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+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/interrupt_controller.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue_input.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/riffa.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/registers.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/recv_credit_flow_ctrl.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rx_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/interrupt.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_multiplexer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rx_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/engine_layer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/xilinx.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/translation_xilinx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/riffa.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/chnl_tester.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../riffa_wrapper_zc706.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../hdl/ZC706Gen2x4If64.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/altera.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="ZC706Gen2x4If64"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../constr/ZC706_Top.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/ZC706_Top.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="ZC706Gen2x4If64"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="SimMode" Val="post-implementation"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="PCIeGen2x4If64" Type="BlockSrcs" RelSrcDir="$PSRCDIR/PCIeGen2x4If64">
+      <File Path="$PPRDIR/../ip/PCIeGen2x4If64.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="PCIeGen2x4If64"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="9">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z045ffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen2x4If64_synth_1" Type="Ft3:Synth" SrcSet="PCIeGen2x4If64" Part="xc7z045ffg900-2" ConstrsSet="PCIeGen2x4If64" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/PCIeGen2x4If64_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen2x4If64_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="PCIeGen2x4If64" Description="Vivado Implementation Defaults" SynthRun="PCIeGen2x4If64_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+  </Runs>
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</Project>
diff --git a/fpga/xilinx/zc706/riffa_wrapper_zc706.v b/fpga/xilinx/zc706/riffa_wrapper_zc706.v
new file mode 100644
index 0000000..3cd9420
--- /dev/null
+++ b/fpga/xilinx/zc706/riffa_wrapper_zc706.v
@@ -0,0 +1,635 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            riffa_wrapper_zc706.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         RIFFA wrapper for the ZC706 Development board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "xilinx.vh"
+`include "ultrascale.vh"
+`include "functions.vh"
+`timescale 1ps / 1ps
+module riffa_wrapper_zc706
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Bit-Width from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      // 4-Byte Name for this FPGA
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     // Interface: Xilinx RX 
+     input [C_PCI_DATA_WIDTH-1:0]                 M_AXIS_RX_TDATA,
+     input [(C_PCI_DATA_WIDTH/8)-1:0]             M_AXIS_RX_TKEEP,
+     input                                        M_AXIS_RX_TLAST,
+     input                                        M_AXIS_RX_TVALID,
+     output                                       M_AXIS_RX_TREADY,
+     input [`SIG_XIL_RX_TUSER_W-1:0]              M_AXIS_RX_TUSER,
+     output                                       RX_NP_OK,
+     output                                       RX_NP_REQ,
+
+     // Interface: Xilinx TX
+     output [C_PCI_DATA_WIDTH-1:0]                S_AXIS_TX_TDATA,
+     output [(C_PCI_DATA_WIDTH/8)-1:0]            S_AXIS_TX_TKEEP,
+     output                                       S_AXIS_TX_TLAST,
+     output                                       S_AXIS_TX_TVALID,
+     input                                        S_AXIS_TX_TREADY,
+     output [`SIG_XIL_TX_TUSER_W-1:0]             S_AXIS_TX_TUSER,
+     output                                       TX_CFG_GNT,
+
+     // Interface: Xilinx Configuration 
+     input [`SIG_BUSID_W-1:0]                     CFG_BUS_NUMBER,
+     input [`SIG_DEVID_W-1:0]                     CFG_DEVICE_NUMBER,
+     input [`SIG_FNID_W-1:0]                      CFG_FUNCTION_NUMBER,
+     input [`SIG_CFGREG_W-1:0]                    CFG_COMMAND,
+     input [`SIG_CFGREG_W-1:0]                    CFG_DCOMMAND,
+     input [`SIG_CFGREG_W-1:0]                    CFG_LSTATUS,
+     input [`SIG_CFGREG_W-1:0]                    CFG_LCOMMAND,
+
+     // Interface: Xilinx Flow Control
+     input [`SIG_FC_CPLD_W-1:0]                   FC_CPLD,
+     input [`SIG_FC_CPLH_W-1:0]                   FC_CPLH,
+     output [`SIG_FC_SEL_W-1:0]                   FC_SEL,
+    
+     // Interface: Xilinx Interrupt
+     input                                        CFG_INTERRUPT_MSIEN,
+     input                                        CFG_INTERRUPT_RDY,
+     output                                       CFG_INTERRUPT,
+
+     input                                        USER_CLK,
+     input                                        USER_RESET,
+
+     // RIFFA Interface Signals
+     output                                       RST_OUT,
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_CLK, // Channel read clock
+     output [C_NUM_CHNL-1:0]                      CHNL_RX, // Channel read receive signal
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_ACK, // Channel read received signal
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_LAST, // Channel last read
+     output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
+     output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
+     output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   CHNL_RX_DATA, // Channel read data
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_DATA_VALID, // Channel read data valid
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_DATA_REN, // Channel read data has been recieved
+
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_CLK, // Channel write clock
+     input [C_NUM_CHNL-1:0]                       CHNL_TX, // Channel write receive signal
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_ACK, // Channel write acknowledgement signal
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_LAST, // Channel last write
+     input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]  CHNL_TX_LEN, // Channel write length (in 32 bit words)
+     input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]  CHNL_TX_OFF, // Channel write offset
+     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]    CHNL_TX_DATA, // Channel write data
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_DATA_VALID, // Channel write data valid
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_DATA_REN // Channel write data has been recieved
+
+     );
+    localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
+    localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
+    // ALTERA, XILINX or ULTRASCALE
+    localparam C_VENDOR = "XILINX";
+
+    localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
+    localparam C_PIPELINE_OUTPUT = 1;
+    localparam C_PIPELINE_INPUT = 1;
+    localparam C_DEPTH_PACKETS = 10;
+
+    wire                                          clk;
+    wire                                          rst_in;
+
+    // Interface: RXC Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxc_data;
+    wire                                          rxc_data_valid;
+    wire                                          rxc_data_start_flag;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxc_data_word_enable;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxc_meta_fdwbe;
+    wire                                          rxc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxc_meta_ldwbe;
+    wire [`SIG_TAG_W-1:0]                         rxc_meta_tag;
+    wire [`SIG_LOWADDR_W-1:0]                     rxc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        rxc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         rxc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     rxc_meta_bytes_remaining;
+    wire [`SIG_CPLID_W-1:0]                       rxc_meta_completer_id;
+    wire                                          rxc_meta_ep;
+
+    // Interface: RXR Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxr_data;
+    wire                                          rxr_data_valid;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxr_data_word_enable;
+    wire                                          rxr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxr_meta_fdwbe;
+    wire                                          rxr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxr_meta_ldwbe;
+    wire [`SIG_TC_W-1:0]                          rxr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        rxr_meta_attr;
+    wire [`SIG_TAG_W-1:0]                         rxr_meta_tag;
+    wire [`SIG_TYPE_W-1:0]                        rxr_meta_type;
+    wire [`SIG_ADDR_W-1:0]                        rxr_meta_addr;
+    wire [`SIG_BARDECODE_W-1:0]                   rxr_meta_bar_decoded;
+    wire [`SIG_REQID_W-1:0]                       rxr_meta_requester_id;
+    wire [`SIG_LEN_W-1:0]                         rxr_meta_length;
+    wire                                          rxr_meta_ep;
+    
+    // interface: TXC Engine
+    wire                                          txc_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txc_data;
+    wire                                          txc_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_start_offset;
+    wire                                          txc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_end_offset;
+    wire                                          txc_data_ready;
+
+    wire                                          txc_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txc_meta_fdwbe;
+    wire [`SIG_LBE_W-1:0]                         txc_meta_ldwbe;
+    wire [`SIG_LOWADDR_W-1:0]                     txc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        txc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         txc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     txc_meta_byte_count;
+    wire [`SIG_TAG_W-1:0]                         txc_meta_tag;
+    wire [`SIG_REQID_W-1:0]                       txc_meta_requester_id;
+    wire [`SIG_TC_W-1:0]                          txc_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txc_meta_attr;
+    wire                                          txc_meta_ep;
+    wire                                          txc_meta_ready;
+    wire                                          txc_sent;
+
+    // Interface: TXR Engine
+    wire                                          txr_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txr_data;
+    wire                                          txr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_start_offset;
+    wire                                          txr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_end_offset;
+    wire                                          txr_data_ready;
+
+    wire                                          txr_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txr_meta_fdwbe; 
+    wire [`SIG_LBE_W-1:0]                         txr_meta_ldwbe;
+    wire [`SIG_ADDR_W-1:0]                        txr_meta_addr;
+    wire [`SIG_LEN_W-1:0]                         txr_meta_length;
+    wire [`SIG_TAG_W-1:0]                         txr_meta_tag;
+    wire [`SIG_TC_W-1:0]                          txr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txr_meta_attr;
+    wire [`SIG_TYPE_W-1:0]                        txr_meta_type;
+    wire                                          txr_meta_ep;
+    wire                                          txr_meta_ready;
+    wire                                          txr_sent;
+
+    // Classic Interface Wires
+    wire                                          rx_tlp_ready;
+    wire [C_PCI_DATA_WIDTH-1:0]                   rx_tlp;
+    wire                                          rx_tlp_end_flag;
+    wire [`SIG_OFFSET_W-1:0]                      rx_tlp_end_offset;
+    wire                                          rx_tlp_start_flag;
+    wire [`SIG_OFFSET_W-1:0]                      rx_tlp_start_offset;
+    wire                                          rx_tlp_valid;
+    wire [`SIG_BARDECODE_W-1:0]                   rx_tlp_bar_decode;
+    
+    wire                                          tx_tlp_ready;
+    wire [C_PCI_DATA_WIDTH-1:0]                   tx_tlp;
+    wire                                          tx_tlp_end_flag;
+    wire [`SIG_OFFSET_W-1:0]                      tx_tlp_end_offset;
+    wire                                          tx_tlp_start_flag;
+    wire [`SIG_OFFSET_W-1:0]                      tx_tlp_start_offset;
+    wire                                          tx_tlp_valid;
+    
+    // Unconnected Wires (Used in ultrascale interface)
+    // Interface: RQ (TXC)
+    wire                                          s_axis_rq_tlast_nc;
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_rq_tdata_nc;
+    wire [`SIG_RQ_TUSER_W-1:0]                    s_axis_rq_tuser_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_rq_tkeep_nc;
+    wire                                          s_axis_rq_tready_nc = 0;
+    wire                                          s_axis_rq_tvalid_nc;
+    // Interface: RC (RXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_rc_tdata_nc = 0;
+    wire [`SIG_RC_TUSER_W-1:0]                    m_axis_rc_tuser_nc = 0;
+    wire                                          m_axis_rc_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_rc_tkeep_nc = 0;
+    wire                                          m_axis_rc_tvalid_nc = 0;
+    wire                                          m_axis_rc_tready_nc;
+    // Interface: CQ (RXR)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_cq_tdata_nc = 0;
+    wire [`SIG_CQ_TUSER_W-1:0]                    m_axis_cq_tuser_nc = 0;
+    wire                                          m_axis_cq_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_cq_tkeep_nc = 0;
+    wire                                          m_axis_cq_tvalid_nc = 0;
+    wire                                          m_axis_cq_tready_nc = 0;
+    // Interface: CC (TXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_cc_tdata_nc;
+    wire [`SIG_CC_TUSER_W-1:0]                    s_axis_cc_tuser_nc;
+    wire                                          s_axis_cc_tlast_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_cc_tkeep_nc;
+    wire                                          s_axis_cc_tvalid_nc;
+    wire                                          s_axis_cc_tready_nc = 0;
+
+    // Interface: Configuration
+    wire                                          config_bus_master_enable;
+    wire [`SIG_CPLID_W-1:0]                       config_completer_id;
+    wire                                          config_cpl_boundary_sel;
+    wire                                          config_interrupt_msienable;
+    wire [`SIG_LINKRATE_W-1:0]                    config_link_rate;
+    wire [`SIG_LINKWIDTH_W-1:0]                   config_link_width;
+    wire [`SIG_MAXPAYLOAD_W-1:0]                  config_max_payload_size;
+    wire [`SIG_MAXREAD_W-1:0]                     config_max_read_request_size;
+    wire [`SIG_FC_CPLD_W-1:0]                     config_max_cpl_data;
+    wire [`SIG_FC_CPLH_W-1:0]                     config_max_cpl_hdr;
+
+    wire                                          intr_msi_request;
+    wire                                          intr_msi_rdy;
+
+    genvar                                        chnl;
+
+    reg                                           rRxTlpValid;
+    reg                                           rRxTlpEndFlag;
+
+    assign clk = USER_CLK;
+    assign rst_in = USER_RESET;
+    
+    translation_xilinx
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH))
+    trans
+        (
+         // Outputs
+         .RX_TLP                        (rx_tlp[C_PCI_DATA_WIDTH-1:0]),
+         .RX_TLP_VALID                  (rx_tlp_valid),
+         .RX_TLP_START_FLAG             (rx_tlp_start_flag),
+         .RX_TLP_START_OFFSET           (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RX_TLP_END_FLAG               (rx_tlp_end_flag),
+         .RX_TLP_END_OFFSET             (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RX_TLP_BAR_DECODE             (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]),
+         .TX_TLP_READY                  (tx_tlp_ready),
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE      (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH             (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE              (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE  (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE       (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE    (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL       (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA           (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR            (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+         .INTR_MSI_RDY                  (intr_msi_rdy),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+         .RX_TLP_READY                  (rx_tlp_ready),
+         .TX_TLP                        (tx_tlp[C_PCI_DATA_WIDTH-1:0]),
+         .TX_TLP_VALID                  (tx_tlp_valid),
+         .TX_TLP_START_FLAG             (tx_tlp_start_flag),
+         .TX_TLP_START_OFFSET           (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TX_TLP_END_FLAG               (tx_tlp_end_flag),
+         .TX_TLP_END_OFFSET             (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .INTR_MSI_REQUEST              (intr_msi_request),
+         /*AUTOINST*/
+         // Outputs
+         .M_AXIS_RX_TREADY              (M_AXIS_RX_TREADY),
+         .RX_NP_OK                      (RX_NP_OK),
+         .RX_NP_REQ                     (RX_NP_REQ),
+         .S_AXIS_TX_TDATA               (S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_TX_TKEEP               (S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .S_AXIS_TX_TLAST               (S_AXIS_TX_TLAST),
+         .S_AXIS_TX_TVALID              (S_AXIS_TX_TVALID),
+         .S_AXIS_TX_TUSER               (S_AXIS_TX_TUSER[`SIG_XIL_TX_TUSER_W-1:0]),
+         .TX_CFG_GNT                    (TX_CFG_GNT),
+         .FC_SEL                        (FC_SEL[`SIG_FC_SEL_W-1:0]),
+         .CFG_INTERRUPT                 (CFG_INTERRUPT),
+         // Inputs
+         .M_AXIS_RX_TDATA               (M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RX_TKEEP               (M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .M_AXIS_RX_TLAST               (M_AXIS_RX_TLAST),
+         .M_AXIS_RX_TVALID              (M_AXIS_RX_TVALID),
+         .M_AXIS_RX_TUSER               (M_AXIS_RX_TUSER[`SIG_XIL_RX_TUSER_W-1:0]),
+         .S_AXIS_TX_TREADY              (S_AXIS_TX_TREADY),
+         .CFG_BUS_NUMBER                (CFG_BUS_NUMBER[`SIG_BUSID_W-1:0]),
+         .CFG_DEVICE_NUMBER             (CFG_DEVICE_NUMBER[`SIG_DEVID_W-1:0]),
+         .CFG_FUNCTION_NUMBER           (CFG_FUNCTION_NUMBER[`SIG_FNID_W-1:0]),
+         .CFG_COMMAND                   (CFG_COMMAND[`SIG_CFGREG_W-1:0]),
+         .CFG_DCOMMAND                  (CFG_DCOMMAND[`SIG_CFGREG_W-1:0]),
+         .CFG_LSTATUS                   (CFG_LSTATUS[`SIG_CFGREG_W-1:0]),
+         .CFG_LCOMMAND                  (CFG_LCOMMAND[`SIG_CFGREG_W-1:0]),
+         .FC_CPLD                       (FC_CPLD[`SIG_FC_CPLD_W-1:0]),
+         .FC_CPLH                       (FC_CPLH[`SIG_FC_CPLH_W-1:0]),
+         .CFG_INTERRUPT_MSIEN           (CFG_INTERRUPT_MSIEN),
+         .CFG_INTERRUPT_RDY             (CFG_INTERRUPT_RDY));
+
+    engine_layer
+        #(// Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_BYTES/4),
+          .C_VENDOR                     (C_VENDOR))
+    engine_layer_inst
+        (// Outputs
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+         // Unconnected Outputs
+         .TX_TLP                        (tx_tlp),
+         .TX_TLP_VALID                  (tx_tlp_valid),
+         .TX_TLP_START_FLAG             (tx_tlp_start_flag),
+         .TX_TLP_START_OFFSET           (tx_tlp_start_offset),
+         .TX_TLP_END_FLAG               (tx_tlp_end_flag),
+         .TX_TLP_END_OFFSET             (tx_tlp_end_offset),
+
+         .RX_TLP_READY                  (rx_tlp_ready),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+         // Unconnected Inputs
+         .RX_TLP                        (rx_tlp),
+         .RX_TLP_VALID                  (rx_tlp_valid),
+         .RX_TLP_START_FLAG             (rx_tlp_start_flag),
+         .RX_TLP_START_OFFSET           (rx_tlp_start_offset),
+         .RX_TLP_END_FLAG               (rx_tlp_end_flag),
+         .RX_TLP_END_OFFSET             (rx_tlp_end_offset),
+         .RX_TLP_BAR_DECODE             (rx_tlp_bar_decode),
+
+         .TX_TLP_READY                  (tx_tlp_ready),
+         // Outputs
+         .M_AXIS_CQ_TREADY              (m_axis_cq_tready_nc),
+         .M_AXIS_RC_TREADY              (m_axis_rc_tready_nc),
+         .S_AXIS_CC_TVALID              (s_axis_cc_tvalid_nc),
+         .S_AXIS_CC_TLAST               (s_axis_cc_tlast_nc),
+         .S_AXIS_CC_TDATA               (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (s_axis_rq_tvalid_nc),
+         .S_AXIS_RQ_TLAST               (s_axis_rq_tlast_nc),
+         .S_AXIS_RQ_TDATA               (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (m_axis_cq_tvalid_nc),
+         .M_AXIS_CQ_TLAST               (m_axis_cq_tlast_nc),
+         .M_AXIS_CQ_TDATA               (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (m_axis_rc_tvalid_nc),
+         .M_AXIS_RC_TLAST               (m_axis_rc_tlast_nc),
+         .M_AXIS_RC_TDATA               (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (s_axis_cc_tready_nc),
+         .S_AXIS_RQ_TREADY              (s_axis_rq_tready_nc)
+         /*AUTOINST*/);
+
+    riffa
+        #(.C_TAG_WIDTH                  (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_MAX_READ_REQ_BYTES         (C_MAX_READ_REQ_BYTES),
+          .C_VENDOR                     (C_VENDOR),
+          .C_FPGA_NAME                  (C_FPGA_NAME),
+          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS))
+    riffa_inst
+        (// Outputs
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+
+         .INTR_MSI_REQUEST              (intr_msi_request),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),         
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE      (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH             (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE              (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE  (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE       (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE    (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL       (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA           (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR            (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+        
+         .INTR_MSI_RDY                  (intr_msi_rdy),
+
+         /*AUTOINST*/
+         // Outputs
+         .RST_OUT                       (RST_OUT),
+         .CHNL_RX                       (CHNL_RX[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_RX_OFF                   (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_RX_DATA                  (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
+         // Inputs
+         .CHNL_RX_CLK                   (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (CHNL_TX[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_TX_OFF                   (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_TX_DATA                  (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("../../engine/" "../../riffa/")
+// End:
diff --git a/java/COMPILE.txt b/java/COMPILE.txt
new file mode 100644
index 0000000..e73a88c
--- /dev/null
+++ b/java/COMPILE.txt
@@ -0,0 +1,68 @@
+Java JNI libraries have already been compiled for 32 and 64 bit versions of 
+Windows and Linux. However, if you want to build your own, see below.
+
+
+FOR LINUX
+=======================
+Compile the Java source:
+
+javac -source 1.4 -target 1.4 -bootclasspath jdk1.4_rt.jar:jdk1.4_tools.jar -extdirs "" edu/ucsd/cs/riffa/*.java
+javah -jni -o jriffa.h edu.ucsd.cs.riffa.Fpga
+
+The -source -target -bootclasspath -extdirs flags on the javac command are used
+to provide JDK 1.4 backwards compatibility. They are not needed if you are 
+compiling this for your own JDK version.
+
+Compile the JNI wrapper source:
+
+gcc -I/usr/lib/jvm/java-7-oracle/include -I/usr/lib/jvm/java-7-oracle/include/linux -fpic -c -ojriffa.o jriffa.c
+gcc -shared -o libjriffa.so jriffa.o -lriffa
+
+Note that the riffa C/C++ library must already be installed on the system. The 
+include directories may be different on your system. You'll need to adjust 
+accordingly. You will also want to determine what value your Java JVM provides 
+for system property os.arch. This will determine i386 (32 bit) or amd64 (64 bit) 
+for the path below.
+
+Create the riffa.jar:
+
+cp libjriffa.so native/[i386|amd64]/Linux
+
+jar cvf riffa.jar edu/ucsd/cs/riffa/*.class native/i386/Linux/* native/amd64/Linux/*
+
+You can include other libraries in the jar. These are just the Linux ones.
+
+
+FOR WINDOWS
+=======================
+Compile the Java source:
+
+javac -source 1.4 -target 1.4 -bootclasspath jdk1.4_rt.jar;jdk1.4_tools.jar -extdirs "" edu\ucsd\cs\riffa\*.java
+javah -jni -o jriffa.h edu.ucsd.cs.riffa.Fpga
+
+The -source -target -bootclasspath -extdirs flags on the javac command are used
+to provide JDK 1.4 backwards compatibility. They are not needed if you are 
+compiling this for your own JDK version.
+
+Compile the JNI wrapper source:
+
+gcc -I"C:\Program Files\Java\jdk1.7.0_21\include" -I"C:\Program Files\Java\jdk1.7.0_21\include\win32" -I<path to dir containing riffa.h> -fpic -c -ojriffa.o jriffa.c
+gcc -shared -o libjriffa.dll jriffa.o -L<path to dir containing riffa.dll or riffa.lib> -lriffa
+
+Use the mingw gcc compiler or Microsoft's Visual Studio. Do not use the cygwin 
+gcc compiler as it will add a dependency for the cygwin.dll.
+
+Note that the riffa C/C++ library must already be installed on the system. The 
+include directories may be different on your system. You'll need to adjust 
+accordingly. You will also want to determine what value your Java JVM provides 
+for system property os.arch. This will determine x86 (32 bit) or amd64 (64 bit)
+for the path below.
+
+Create the riffa.jar:
+
+copy libjriffa.dll native\[x86|amd64]\Windows
+
+jar cvf riffa.jar edu\ucsd\cs\riffa\*.class native\x86\Windows\* native\amd64\Windows\*
+
+You can include other libraries in the jar. These are just the Windows ones.
+
diff --git a/java/README.txt b/java/README.txt
new file mode 100644
index 0000000..251bb41
--- /dev/null
+++ b/java/README.txt
@@ -0,0 +1,20 @@
+To use the Java bindings simply include the riffa.jar in your classpath while
+compiling and running. Everything has already been included in this jar.
+
+To compile the sample application:
+
+javac -cp riffa.jar SampleApp.java
+
+
+To run the sample sample application:
+
+java -cp riffa.jar;. SampleApp
+
+or for Linux:
+
+java -cp riffa.jar:. SampleApp
+
+
+Note that the riffa driver and C/C++ library must already be installed on the 
+system.
+
diff --git a/java/SampleApp.java b/java/SampleApp.java
new file mode 100644
index 0000000..77b1ca1
--- /dev/null
+++ b/java/SampleApp.java
@@ -0,0 +1,57 @@
+import edu.ucsd.cs.riffa.*;
+
+public class SampleApp {
+
+	public static void main(String[] args) {
+		try {
+			// Print out the installed RIFFA FPGAs
+			FpgaInfo info = Fpga.list();
+			System.out.println(info);
+
+			// Exercise the chnl_tester module.
+			int amt = 200;
+			java.nio.ByteBuffer byteBufRecv = java.nio.ByteBuffer.allocateDirect(amt);
+			java.nio.IntBuffer intBufRecv = byteBufRecv.asIntBuffer();
+			java.nio.ByteBuffer byteBufSend = java.nio.ByteBuffer.allocateDirect(amt);
+			java.nio.IntBuffer intBufSend = byteBufSend.asIntBuffer();
+
+			// Initialize the byteBufSendfers for send and receive. Note that 
+			// Java stores numbers in big endian format. The chnl_tester module
+			// expects them in little endian. So we need to byte swap.
+			byte tmp0, tmp1;
+			for (int i=0; i < amt/4; i++) {
+				intBufRecv.put(i, 0);
+				intBufSend.put(i, i+1);
+				tmp0 = byteBufSend.get((i*4)+0);
+				tmp1 = byteBufSend.get((i*4)+1);
+				byteBufSend.put((i*4)+0, byteBufSend.get((i*4)+3));
+				byteBufSend.put((i*4)+1, byteBufSend.get((i*4)+2));
+				byteBufSend.put((i*4)+2, tmp1);
+				byteBufSend.put((i*4)+3, tmp0);
+				byteBufSend.put(i*4, (byte)(i+1));
+				System.out.printf("%d - %02x%02x%02x%02x\n", i+1,
+					byteBufSend.get((i*4)+3), byteBufSend.get((i*4)+2), byteBufSend.get((i*4)+1), byteBufSend.get(i*4));
+			}
+
+			Fpga fpga = Fpga.open(0);
+			int s = fpga.send(0, byteBufSend, amt/4, 0, true, 0);
+			int r = fpga.recv(0, byteBufRecv, 0);
+			fpga.close();
+
+			System.out.println(s + " words sent");
+			System.out.println(r + " words recvd");
+
+			// If using the chnl_tester module, the values returned will be in
+			// little endian format. Thus they'll be interpreted incorrectly in
+			// Java (unless byte swapped of course).
+			for (int i=0; i < amt/4; i++){
+				System.out.printf("%d) %d - %02x%02x%02x%02x\n", i+1, intBufRecv.get(i),
+					byteBufRecv.get((i*4)+3), byteBufRecv.get((i*4)+2), byteBufRecv.get((i*4)+1), byteBufRecv.get(i*4));
+			}
+		}
+		catch (Exception ex) {
+			ex.printStackTrace();
+		}
+	}
+
+}
diff --git a/java/edu/ucsd/cs/riffa/Fpga.java b/java/edu/ucsd/cs/riffa/Fpga.java
new file mode 100644
index 0000000..2007b99
--- /dev/null
+++ b/java/edu/ucsd/cs/riffa/Fpga.java
@@ -0,0 +1,212 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+/*
+ * Filename: Fpga.java
+ * Version: 2.0
+ * Description: Java API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+/**
+ * Represents a FPGA accessible by RIFFA. The usage pattern is:
+ *    Fpga f = Fpga.open(...);
+ *    f.send(...);
+ *    f.recv(...);
+ *    f.close(...);
+ *
+ * The static method list can be used to get a listing of the FPGAs installed in
+ * the system and their ids. You'll need the FPGA id to pass to the open method.
+ * If only 1 FPGA is installed in the system, it's id will always be 0.
+ *
+ * In the send and recv methods below use java.nio.ByteBuffer instead of a
+ * byte[] to represent the data for sending and buffer for receiving data. The
+ * java.nio.ByteBuffer class is used because the underlying byte[] can easily be
+ * accessed. But more importantly, it has methods to reinterpret the underlying
+ * byte[] into other primitive array types (e.g. int[]) without copying the
+ * contents of the array. Copying arrays (especially large arrays) will reduce
+ * throughput considerably and is best to be avoided. Use the allocateDirect
+ * method on ByteBuffer to create a new instance. Then use one of the asXXXBufer
+ * methods to acquire the appropriate java.nio.Buffer subclass. The example
+ * below illustrates this:
+ *    java.nio.ByteBuffer bb = java.nio.ByteBuffer.allocateDirect(NUM_INTS*4);
+ *    java.nio.IntBuffer ib = bb.asIntBuffer();
+ *    for (i = 0; i < NUM_INTS; i++)
+ *        ib.put(i, ...)
+ *    Fpga f = Fpga.open(0);
+ *    fpga.send(0, bb, NUM_INTS, 0, true, 0L);
+ */
+package edu.ucsd.cs.riffa;
+
+import java.nio.ByteBuffer;
+
+public class Fpga {
+	private Long ptr;
+
+	private native int jFpgaList(FpgaInfo info);
+	private native long jFpgaOpen(int id);
+	private native void jFpgaClose(long fpga);
+	private native int jFpgaSend(long fpga, int chnl, ByteBuffer data, int len, int destoff, int last, long timeout);
+	private native int jFpgaRecv(long fpga, int chnl, ByteBuffer data, long timeout);
+	private native void jFpgaReset(long fpga);
+
+	/* Expects the JNI library to be libjriffa.so or libjriffa.dll */
+	static {
+		NativeLibLoader.loadLibrary("jriffa");
+	}
+
+	/**
+	 * Default constructor.
+	 */
+	private Fpga() {
+		ptr = null;
+	}
+
+	/**
+	 * Populates and returns a FpgaInfo object with all FPGAs registered in the
+	 * system. Returns a FpgaInfo object on success. Returns null on error.
+	 *
+	 * @returns A FpgaInfo object on success or null.
+	 */
+	public static FpgaInfo list() {
+		FpgaInfo info = new FpgaInfo();
+		Fpga fpga = new Fpga();
+		if (fpga.jFpgaList(info) == 0)
+			return info;
+		else
+			return null;
+	}
+
+	/**
+	 * Initializes the FPGA specified by id. On success, returns a Fpga object.
+	 * On error, returns null. Each FPGA must be opened before any channels can
+	 * be accessed. Once opened, any number of threads can use the Fpga object.
+	 *
+ 	 * @param id - Identifier for the FPGA (in single FPGA installations, this
+	 * is always 0).
+	 * @returns Fpga object or null.
+	 */
+	public static Fpga open(int id) {
+		Fpga fpga = new Fpga();
+		fpga.ptr = new Long(fpga.jFpgaOpen(id));
+		return fpga;
+	}
+
+	/**
+	 * Cleans up memory/resources for the FPGA represented by this instance.
+	 */
+	public void close() {
+		this.jFpgaClose(this.ptr.longValue());
+		ptr = null;
+	}
+
+	/**
+	 * Sends len words (4 byte words) from data to FPGA channel chnl on the FPGA
+	 * represented by this Fpga object. The FPGA channel will be sent len,
+	 * destoff, and last. The value of destoff is used to support sending data
+	 * across multiple send transactions. Note that only the low 31 bits of
+	 * offset are sent. If last is true the channel should interpret the end of
+	 * this send as the end of a transaction. If last is false, the channel
+	 * should wait for additional sends before the end of the transaction. If
+	 * timeout is non-zero, this call will send data and wait up to timeout ms
+	 * for the FPGA to respond (between packets) before timing out. If timeout
+	 * is zero, this call may block indefinitely. Multiple threads sending on
+	 * the same channel may result in corrupt data or error. This function is
+	 * thread safe across channels. Returns the number of words sent.
+	 *
+ 	 * @param chnl - Channel number over which to communicate.
+ 	 * @param data - java.nio.ByteBuffer holding the byte[] send. Note that the
+	 * data transfer unit is a 32 bit word.
+ 	 * @param len - Length of data to send, in (32 bit) words. Thus a value of 4
+	 * means send 16 bytes.
+ 	 * @param destoff - Value sent to FPGA core to indicate where to start
+	 * writing this data. Only the least significant 31 bits are sent (not all
+	 * 32).
+ 	 * @param last - If true, this transfer is the last in a sequence of
+	 * transfers. If false, this transfer is not the last in a sequence of
+	 * transfers(more transfers to come).
+ 	 * @param timeout - Timeout value in ms. If 0, no timeout is specified.
+	 * Otherwise, the PC will wait up to timeout ms in between PC/FPGA
+	 * communications.
+	 * @returns The number of words sent.
+	 */
+	public int send(int chnl, ByteBuffer data, int len, int destoff, boolean last, long timeout) {
+		int s = this.jFpgaSend(this.ptr.longValue(), chnl, data, len, destoff, (last ? 1 : 0), timeout);
+		if (s == -1)
+			throw new RuntimeException("Unble to access ByteBuffer direct memory.");
+		return s;
+	}
+
+	/**
+	 * Receives data from the FPGA channel chnl to the java.nio.ByteBuffer
+	 * object, on the FPGA represented by this Fpga object. The FPGA channel can
+	 * send any amount of data, so the java.nio.ByteBuffer should be large
+	 * enough to accommodate. The FPGA will specify an offset value which will
+	 * determine where received data will start being written. If the amount of
+	 * data plus offset exceed the size of the data array, then the additional
+	 * data will be discarded. If timeout is non-zero, this call will wait up to
+	 * timeout ms for the FPGA to respond (between packets) before timing out.
+	 * If timeout is zero, this call may block indefinitely. Multiple threads
+	 * receiving on the same channel may result in corrupt data or error. This
+	 * function is thread safe across channels. Returns the number of words
+	 * written to the java.nio.ByteBuffer.
+	 *
+ 	 * @param chnl - Channel number over which to communicate.
+ 	 * @param data - java.nio.ByteBuffer into which received data will be
+	 * written.
+ 	 * @param timeout - Timeout value in ms. If 0, no timeout is specified.
+	 * Otherwise, the PC will wait up to timeout ms in between PC/FPGA
+	 * communications.
+	 * @returns The number of words written to the java.nio.ByteBuffer.
+	 */
+	public int recv(int chnl, ByteBuffer data, long timeout) {
+		int r = this.jFpgaRecv(this.ptr.longValue(), chnl, data, timeout);
+		if (r == -1)
+			throw new RuntimeException("Unble to access ByteBuffer direct memory.");
+		return r;
+	}
+
+	/**
+	 * Resets the state of the FPGA and all channels. This is meant to be used
+	 * as an alternative to rebooting if an error occurs while sending or
+	 * receiving. Calling this function while other threads are sending or
+	 * receiving will result in unexpected behavior.
+	 */
+	public void reset() {
+		this.jFpgaReset(this.ptr.longValue());
+	}
+}
+
diff --git a/java/edu/ucsd/cs/riffa/FpgaInfo.java b/java/edu/ucsd/cs/riffa/FpgaInfo.java
new file mode 100644
index 0000000..f270e5f
--- /dev/null
+++ b/java/edu/ucsd/cs/riffa/FpgaInfo.java
@@ -0,0 +1,206 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+/*
+ * Filename: FpgaInfo.java
+ * Version: 2.0
+ * Description: Java API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+/**
+ * Value object to hold information about all the installed FPGA accessible by 
+ * RIFFA.
+ */
+package edu.ucsd.cs.riffa;
+
+public class FpgaInfo {
+	private static final int NUM_FPGAS = 5;
+	private int numFpgas;
+	private int[] numChannels;
+	private int[] id;
+	private int[] vendorId;
+	private int[] deviceId;
+	private String[] name;
+
+	/**
+	 * Default constructor.
+	 */
+	public FpgaInfo() {
+		this.numFpgas = 0;
+		this.name = new String[NUM_FPGAS];
+		this.id = new int[NUM_FPGAS];
+		this.numChannels = new int[NUM_FPGAS];
+		this.deviceId = new int[NUM_FPGAS];
+		this.vendorId = new int[NUM_FPGAS];
+	}
+	
+	/**
+	 * Returns the number of RIFFA accessible FPGAs installed in the system.
+	 *
+	 * @returns Number of RIFFA accessible FPGAs installed in the system.
+	 */
+	public int getNumFpgas() {
+		return this.numFpgas;
+	}
+	
+	/**
+	 * Sets the number of RIFFA accessible FPGAs installed in the system.
+	 *
+	 * @param val - Number of RIFFA accessible FPGAs installed in the system.
+	 */
+	public void setNumFpgas(int val) {
+		this.numFpgas = val;		
+	}
+
+	/**
+	 * Returns the number of RIFFA channels configured on the FPGA at position 
+	 * pos.
+	 *
+	 * @returns Number of RIFFA channels configured on the FPGA at position pos.
+	 */
+	public int getNumChannels(int pos) {
+		return this.numChannels[pos];
+	}
+	
+	/**
+	 * Sets the number of RIFFA channels configured on the FPGA at position pos.
+	 *
+	 * @param pos - Position of FPGA.
+	 * @param val - Number of RIFFA channels configured on the FPGA at position 
+	 * pos.
+	 */
+	public void setNumChannels(int pos, int val) {
+		this.numChannels[pos] = val;		
+	}
+
+	/**
+	 * Returns the FPGA id at position pos. This id is used to open the FPGA on 
+	 * the Fpga's open method.
+	 *
+	 * @returns FPGA id at position pos..
+	 */
+	public int getId(int pos) {
+		return this.id[pos];
+	}
+	
+	/**
+	 * Sets the FPGA id at position pos.
+	 *
+	 * @param pos - Position of FPGA.
+	 * @param val - FPGA id at position pos.
+	 */
+	public void setId(int pos, int val) {
+		this.id[pos] = val;		
+	}
+
+	/**
+	 * Returns the name of the FPGA at position pos. This is typically the PCIe 
+	 * bus and slot number.
+	 *
+	 * @returns Name of the FPGA at position pos.
+	 */
+	public String getName(int pos) {
+		return this.name[pos];
+	}
+	
+	/**
+	 * Sets the name of the FPGA at position pos.
+	 *
+	 * @param pos - Position of FPGA.
+	 * @param val - Name of the FPGA at position pos.
+	 */
+	public void setName(int pos, String val) {
+		this.name[pos] = val;		
+	}
+
+	/**
+	 * Returns the FPGA vendor id at position pos.
+	 *
+	 * @returns The FPGA vendor id at position pos.
+	 */
+	public int getVendorId(int pos) {
+		return this.vendorId[pos];
+	}
+	
+	/**
+	 * Sets the FPGA vendor id at position pos.
+	 *
+	 * @param pos - Position of FPGA.
+	 * @param val - The FPGA vendor id at position pos.
+	 */
+	public void setVendorId(int pos, int val) {
+		this.vendorId[pos] = val;		
+	}
+
+	/**
+	 * Returns the FPGA device id at position pos.
+	 *
+	 * @returns The FPGA device id at position pos.
+	 */
+	public int getDeviceId(int pos) {
+		return this.deviceId[pos];
+	}
+	
+	/**
+	 * Sets the FPGA device id at position pos.
+	 *
+	 * @param pos - Position of FPGA.
+	 * @param val - The FPGA device id at position pos.
+	 */
+	public void setDeviceId(int pos, int val) {
+		this.deviceId[pos] = val;		
+	}
+
+	/**
+	 * Returns a nicely formatted listing of all the RIFFA FPGAs detected.
+	 * 
+	 * @returns a nicely formatted String of all the RIFFA FPGAs detected.
+	 */
+	public String toString() {
+		StringBuffer buffy = new StringBuffer();
+		String eol = System.getProperty("line.separator");
+		buffy.append("num fpgas: " + this.numFpgas + eol);
+		for (int i=0; i < this.numFpgas; i++) {
+			buffy.append("id: " + this.id[i] + eol);
+			buffy.append("name: " + this.name[i] + eol);
+			buffy.append("num channels: " + this.numChannels[i] + eol);
+			buffy.append("vendor id: " + Integer.toHexString(this.vendorId[i]) + eol);
+			buffy.append("device id: " + Integer.toHexString(this.deviceId[i]) + eol);
+		}
+		return buffy.toString();
+	}
+}
diff --git a/java/edu/ucsd/cs/riffa/NativeLibLoader.java b/java/edu/ucsd/cs/riffa/NativeLibLoader.java
new file mode 100644
index 0000000..ab99d86
--- /dev/null
+++ b/java/edu/ucsd/cs/riffa/NativeLibLoader.java
@@ -0,0 +1,142 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+/*
+ * Filename: NativeLibLoader.java
+ * Version: 2.0
+ * Description: Java API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+/**
+ * Utility to load the JNI RIFFA library.
+ */
+package edu.ucsd.cs.riffa;
+
+import java.io.BufferedOutputStream;
+import java.io.File;
+import java.io.FileOutputStream;
+import java.io.IOException;
+import java.io.InputStream;
+import java.io.OutputStream;
+import java.net.URL;
+import java.util.ArrayList;
+import java.util.Collection;
+import java.util.Enumeration;
+import java.util.List;
+import java.util.jar.JarEntry;
+import java.util.jar.JarFile;
+
+public class NativeLibLoader {
+
+	/**
+	 * Default constructor.
+	 */
+	private NativeLibLoader() { }
+
+	/**
+	 * Returns a String representing the platform. Format: ${os.arch}/${os.name}
+	 *
+	 * @returns A String representing the platform.
+	 */
+	public static String getCurrentPlatformIdentifier() {
+		String osName = System.getProperty("os.name");
+		if (osName.toLowerCase().indexOf("windows") > -1) {
+			osName = "Windows";
+		}
+		return System.getProperty("os.arch") + "/" + osName;
+	}
+
+	/**
+	 * Loads a library from the same ClassLoader as this class at the path:
+	 * /native/${os.arch}/${os.path}/lib[libName].[so|dll]
+	 * If no such path is found, attemts to load the library by name using the
+	 * System.loadLibrary function which searches the java.library.path system
+	 * property.
+	 *
+	 * @param libName - Library name, without the lib prefix or any suffix.
+	 */
+	public static void loadLibrary(String libName) {
+		boolean usingEmbedded = false;
+		// Attempt to locate embedded native library within JAR at:
+		// /native/${os.arch}/${os.name}/lib[libName].[so|dll]
+		String[] exts = new String[] { "so", "dll" };
+		StringBuffer url = new StringBuffer();
+		url.append("/native/");
+		url.append(getCurrentPlatformIdentifier());
+		url.append("/lib");
+		url.append(libName);
+		url.append(".");
+		URL nativeLibraryUrl = null;
+		// Loop through extensions, stopping after finding first one
+		for (int i=0; i < exts.length; i++) {
+			nativeLibraryUrl = NativeLibLoader.class.getResource(url.toString() + exts[i]);
+			if (nativeLibraryUrl != null)
+				break;
+		}
+
+		if (nativeLibraryUrl != null) {
+			// Native library found within JAR, extract and load
+			try {
+				final File libfile = File.createTempFile(libName + "-", ".lib");
+				libfile.deleteOnExit(); // just in case
+
+				final InputStream in = nativeLibraryUrl.openStream();
+				final OutputStream out = new BufferedOutputStream(new FileOutputStream(libfile));
+
+				int len = 0;
+				byte[] buffer = new byte[8192];
+				while ((len = in.read(buffer)) > -1)
+					out.write(buffer, 0, len);
+				out.close();
+				in.close();
+
+				System.load(libfile.getAbsolutePath());
+
+				libfile.delete();
+
+				usingEmbedded = true;
+
+			} catch (IOException x) {
+				// mission failed, do nothing
+			}
+		}
+
+		// If not loaded, try loading using the java.library.path
+		if (!usingEmbedded)
+			System.loadLibrary(libName);
+	}
+}
diff --git a/java/jriffa.c b/java/jriffa.c
new file mode 100644
index 0000000..dcb75fb
--- /dev/null
+++ b/java/jriffa.c
@@ -0,0 +1,122 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+/*
+ * Filename: jriffa.c
+ * Version: 2.0
+ * Description: Java JNI library for calling RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#include <limits.h>
+#include <riffa.h>
+#include "jriffa.h"
+#include <stdio.h>
+
+JNIEXPORT jint JNICALL Java_edu_ucsd_cs_riffa_Fpga_jFpgaList(JNIEnv *env, jobject obj, jobject info) {
+	int r;
+	int i;
+	fpga_info_list list;
+	jclass cls;
+	jstring name;
+	jmethodID setNumFpgas;
+	jmethodID setName;
+	jmethodID setId;
+	jmethodID setNumChannels;
+	jmethodID setVendorId;
+	jmethodID setDeviceId;
+	if ((r = fpga_list(&list)) == 0) {
+		cls = (*env)->FindClass(env, "edu/ucsd/cs/riffa/FpgaInfo");
+		setNumFpgas = (*env)->GetMethodID(env, cls, "setNumFpgas", "(I)V");
+		(*env)->CallVoidMethod(env, info, setNumFpgas, list.num_fpgas);
+		for (i = 0; i < list.num_fpgas; i++) {
+			setName = (*env)->GetMethodID(env, cls, "setName", "(ILjava/lang/String;)V");
+			name = (*env)->NewStringUTF(env, list.name[i]);
+			(*env)->CallVoidMethod(env, info, setName, i, name);
+			setNumChannels = (*env)->GetMethodID(env, cls, "setNumChannels", "(II)V");
+			(*env)->CallVoidMethod(env, info, setNumChannels, i, list.num_chnls[i]);
+			setId = (*env)->GetMethodID(env, cls, "setId", "(II)V");
+			(*env)->CallVoidMethod(env, info, setId, i, list.id[i]);
+			setVendorId = (*env)->GetMethodID(env, cls, "setVendorId", "(II)V");
+			(*env)->CallVoidMethod(env, info, setVendorId, i, list.vendor_id[i]);
+			setDeviceId = (*env)->GetMethodID(env, cls, "setDeviceId", "(II)V");
+			(*env)->CallVoidMethod(env, info, setDeviceId, i, list.device_id[i]);
+		}
+	}
+	return r;
+}
+
+JNIEXPORT jlong JNICALL Java_edu_ucsd_cs_riffa_Fpga_jFpgaOpen(JNIEnv *env, jobject obj, jint id) {
+	fpga_t * fpga = fpga_open((int)id);
+	return (jlong)fpga;
+}
+
+JNIEXPORT void JNICALL Java_edu_ucsd_cs_riffa_Fpga_jFpgaClose(JNIEnv *env, jobject obj, jlong fpga) {
+	fpga_close((fpga_t *)fpga);
+}
+
+JNIEXPORT jint JNICALL Java_edu_ucsd_cs_riffa_Fpga_jFpgaSend(JNIEnv *env, jobject obj, jlong fpga,
+	jint chnl, jobject buffer, jint len, jint destoff, jint last, jlong timeout) {
+	jlong datalen;
+	unsigned int ulen;
+	unsigned int lgt;
+	void * data;
+	data = (*env)->GetDirectBufferAddress(env, buffer);
+	datalen = (*env)->GetDirectBufferCapacity(env, buffer);
+	if (data == NULL || datalen == -1)
+		return -1; // Means cannot get access to ByteBuffer underlying pointer
+	ulen = (unsigned int)len;
+	lgt = (ulen > (datalen>>2) ? (datalen>>2) : ulen);
+	return fpga_send((fpga_t *)fpga, chnl, data, lgt, destoff, last, timeout);
+}
+
+JNIEXPORT jint JNICALL Java_edu_ucsd_cs_riffa_Fpga_jFpgaRecv(JNIEnv *env, jobject obj, jlong fpga,
+	jint chnl, jobject buffer, jlong timeout) {
+	jlong datalen;
+	unsigned int lgt;
+	void * data;
+	data = (*env)->GetDirectBufferAddress(env, buffer);
+	datalen = (*env)->GetDirectBufferCapacity(env, buffer);
+	if (data == NULL || datalen == -1)
+		return -1; // Means cannot get access to ByteBuffer underlying pointer
+	lgt = (datalen>>2);
+	return fpga_recv((fpga_t *)fpga, chnl, data, lgt, timeout);
+}
+
+JNIEXPORT void JNICALL Java_edu_ucsd_cs_riffa_Fpga_jFpgaReset(JNIEnv *env, jobject obj, jlong fpga) {
+	fpga_reset((fpga_t *)fpga);
+}
+
diff --git a/java/jriffa.h b/java/jriffa.h
new file mode 100644
index 0000000..f6454f2
--- /dev/null
+++ b/java/jriffa.h
@@ -0,0 +1,61 @@
+/* DO NOT EDIT THIS FILE - it is machine generated */
+#include <jni.h>
+/* Header for class edu_ucsd_cs_riffa_Fpga */
+
+#ifndef _Included_edu_ucsd_cs_riffa_Fpga
+#define _Included_edu_ucsd_cs_riffa_Fpga
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+ * Class:     edu_ucsd_cs_riffa_Fpga
+ * Method:    jFpgaList
+ * Signature: (Ledu/ucsd/cs/riffa/FpgaInfo;)I
+ */
+JNIEXPORT jint JNICALL Java_edu_ucsd_cs_riffa_Fpga_jFpgaList
+  (JNIEnv *, jobject, jobject);
+
+/*
+ * Class:     edu_ucsd_cs_riffa_Fpga
+ * Method:    jFpgaOpen
+ * Signature: (I)J
+ */
+JNIEXPORT jlong JNICALL Java_edu_ucsd_cs_riffa_Fpga_jFpgaOpen
+  (JNIEnv *, jobject, jint);
+
+/*
+ * Class:     edu_ucsd_cs_riffa_Fpga
+ * Method:    jFpgaClose
+ * Signature: (J)V
+ */
+JNIEXPORT void JNICALL Java_edu_ucsd_cs_riffa_Fpga_jFpgaClose
+  (JNIEnv *, jobject, jlong);
+
+/*
+ * Class:     edu_ucsd_cs_riffa_Fpga
+ * Method:    jFpgaSend
+ * Signature: (JILjava/nio/ByteBuffer;IIIJ)I
+ */
+JNIEXPORT jint JNICALL Java_edu_ucsd_cs_riffa_Fpga_jFpgaSend
+  (JNIEnv *, jobject, jlong, jint, jobject, jint, jint, jint, jlong);
+
+/*
+ * Class:     edu_ucsd_cs_riffa_Fpga
+ * Method:    jFpgaRecv
+ * Signature: (JILjava/nio/ByteBuffer;J)I
+ */
+JNIEXPORT jint JNICALL Java_edu_ucsd_cs_riffa_Fpga_jFpgaRecv
+  (JNIEnv *, jobject, jlong, jint, jobject, jlong);
+
+/*
+ * Class:     edu_ucsd_cs_riffa_Fpga
+ * Method:    jFpgaReset
+ * Signature: (J)V
+ */
+JNIEXPORT void JNICALL Java_edu_ucsd_cs_riffa_Fpga_jFpgaReset
+  (JNIEnv *, jobject, jlong);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/java/native/amd64/Linux/libjriffa.so b/java/native/amd64/Linux/libjriffa.so
new file mode 100644
index 0000000..a3c0093
Binary files /dev/null and b/java/native/amd64/Linux/libjriffa.so differ
diff --git a/java/native/amd64/Windows/libjriffa.dll b/java/native/amd64/Windows/libjriffa.dll
new file mode 100644
index 0000000..3df0452
Binary files /dev/null and b/java/native/amd64/Windows/libjriffa.dll differ
diff --git a/java/native/i386/Linux/libjriffa.so b/java/native/i386/Linux/libjriffa.so
new file mode 100644
index 0000000..b113552
Binary files /dev/null and b/java/native/i386/Linux/libjriffa.so differ
diff --git a/java/native/x86/Windows/libjriffa.dll b/java/native/x86/Windows/libjriffa.dll
new file mode 100644
index 0000000..db79125
Binary files /dev/null and b/java/native/x86/Windows/libjriffa.dll differ
diff --git a/java/riffa.jar b/java/riffa.jar
new file mode 100644
index 0000000..7756a2e
Binary files /dev/null and b/java/riffa.jar differ
diff --git a/matlab/README.txt b/matlab/README.txt
new file mode 100644
index 0000000..224721d
--- /dev/null
+++ b/matlab/README.txt
@@ -0,0 +1,12 @@
+To use the Matlab bindings simply include the Riffa.m class in your Matlab
+working directory.
+
+Note that the riffa driver and C/C++ library must already be installed on the 
+system.
+
+On Windows platforms you'll need to have the riffa.h header file in the working
+directory as well (as there is no default include directory on Windows).
+
+The first time you load the RIFFA bindings, several auto-generated files will be
+produced. This will require that Matlab has access to a C compiler. This is
+often taken care of during Matlab install.
diff --git a/matlab/Riffa.m b/matlab/Riffa.m
new file mode 100755
index 0000000..2e628dc
--- /dev/null
+++ b/matlab/Riffa.m
@@ -0,0 +1,256 @@
+% ----------------------------------------------------------------------
+% Copyright (c) 2015, The Regents of the University of California All
+% rights reserved.
+% 
+% Redistribution and use in source and binary forms, with or without
+% modification, are permitted provided that the following conditions are
+% met:
+% 
+%     * Redistributions of source code must retain the above copyright
+%       notice, this list of conditions and the following disclaimer.
+% 
+%     * Redistributions in binary form must reproduce the above
+%       copyright notice, this list of conditions and the following
+%       disclaimer in the documentation and/or other materials provided
+%       with the distribution.
+% 
+%     * Neither the name of The Regents of the University of California
+%       nor the names of its contributors may be used to endorse or
+%       promote products derived from this software without specific
+%       prior written permission.
+% 
+% THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+% "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+% LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+% A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+% UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+% INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+% BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+% OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+% ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+% TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+% USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+% DAMAGE.
+% ----------------------------------------------------------------------
+classdef Riffa < handle
+    % Riffa RIFFA 2.0 interface for Matlab R2008a or greater.
+
+    properties (Hidden)
+        fpga_t;
+        libname;		
+    end
+
+    properties (SetAccess = private)
+        id;
+        closed; %If this value is non-zero then the FPGA is closed
+    end
+    
+
+    methods 
+        function obj = Riffa(id_num)
+            % Constructs a Riffa instance for FPGA with id id_num.
+            if (nargin ~= 1)
+                error('You must specify the FPGA id number.');
+            end
+            
+			obj.libname = Riffa.load_lib();
+            obj.fpga_t = calllib(obj.libname,'fpga_open',id_num);
+            if isNull(obj.fpga_t)
+                obj.closed = -1;
+                error('While attempting to access FPGA.')
+			end
+            obj.id = id_num;
+            obj.closed = 0;
+        end
+        
+        
+        function close(obj)
+            % Closes the Riffa instance. Once closed, this instance is no longer
+			% usable. 
+            if (obj.closed ~= 0)
+                error('This Riffa instance is closed.');
+            end
+            if isNull(obj.fpga_t)
+                obj.closed = -1;
+                error('Riffa FPGA handle is NULL!')
+            end
+            calllib(obj.libname,'fpga_close',obj.fpga_t);
+            obj.closed = 1;
+        end
+        
+        
+        function sent = send(obj, chnl, data, length, offset, last, timeout)
+			% Sends length words (4 byte words) from data to FPGA channel chnl.  
+			% The FPGA channel will be sent length, destoff, and last. If last 
+			% is 1, the channel should interpret the end of this send as the end
+			% of a transaction. If last is 0, the channel should wait for 
+			% additional sends before the end of the transaction. If timeout is 
+			% non-zero, this call will send data and wait up to timeout ms for 
+			% the FPGA to respond (between packets) before timing out. If
+			% timeout is zero, this call may block indefinitely. Returns the 
+			% number of words sent. 
+            if obj.closed ~= 0
+                error('This Riffa instance is closed.');
+            end
+            if isNull(obj.fpga_t)
+                obj.closed = -1;
+                error('Riffa FPGA handle is NULL!')
+            end
+            if nargin ~= 7
+                error('Usage: words_sent = send(chnl, data, length, offset, last, timeout)')
+            end
+            if length < 0
+                error('Length (arg 3) must be non-negative');
+            end
+            if offset < 0
+                error('Offset (arg 4) must be non-negative');
+            end
+            if timeout < 0
+                error('Timeout (arg 6) must be non-negative');
+            end
+			fpgaptr = libpointer('fpga_tPtr', obj.fpga_t);
+            sent = calllib(obj.libname, 'fpga_send', fpgaptr, int32(chnl), ...
+				data, int32(length), int32(offset), int32(last), int64(timeout));
+        end
+        
+                
+        function [recvd, data] = recv(obj, chnl, length, timeout)
+			% Receives data from the FPGA channel chnl and returns it in the 
+			% data variable. The FPGA channel can send any amount of data, but
+			% only length words will be returned. The FPGA channel will specify 
+			% an offset which will determine where in the returned data object
+			% the data will start being written. If the amount of data (plus 
+			% offset) exceed the length specified, then additional data will be 
+			% discarded. If timeout is non-zero, this call will wait up to 
+			% timeout ms for the FPGA to respond (between packets) before 
+			% timing out. If timeout is zero, this call may block indefinitely. 
+			% Returns the number of words received to the data variable. 
+            if obj.closed ~= 0
+                error('This Riffa instance is closed.');
+            end
+            if isNull(obj.fpga_t)
+                obj.closed = -1;
+                error('Riffa FPGA handle is NULL!')
+            end
+            if nargin ~= 4 
+                error('Usage: words_recvd = recv(chnl, length, timeout)')
+            end
+            if length < 0
+                error('Length (arg 3) must be positive');
+            end
+            if timeout < 0
+                error('Timeout (arg 4) must be positive');
+            end
+			dataptr = libpointer('voidPtr', int32(zeros(1, length)));
+			fpgaptr = libpointer('fpga_tPtr', obj.fpga_t);
+            recvd = calllib(obj.libname, 'fpga_recv', fpgaptr, int32(chnl), ...
+				dataptr, int32(length), int64(timeout));
+			recvd = min(recvd, length);
+			data = dataptr.Value;
+			data = data(1:recvd);
+        end
+        
+        
+        function reset(obj)
+			% Resets all FPGA channels connected to this Riffa instance.
+            if obj.closed ~= 0
+                error('This Riffa instance is closed.');
+            end
+            if isNull(obj.fpga_t)
+                obj.closed = -1;
+                error('Riffa FPGA handle is NULL!')
+            end
+            calllib(obj.libname,'fpga_reset',obj.fpga_t);
+            
+        end
+    end 
+
+    
+    methods (Static) 
+        function fpga_info_list = list()
+			% Returns a fpga_info_list with all FPGAs registered in the system.
+			libname = Riffa.load_lib();
+            mstruct_list = struct('num_fpgas', 0,...
+                'id', [0,0,0,0,0],...
+                'num_chnls', [0,0,0,0,0],...
+                'name', int8(zeros(1,80)),...
+                'vendor_id',[0,0,0,0,0],...
+                'device_id',[0,0,0,0,0]);
+            
+            cstruct_list = libstruct('fpga_info_list',mstruct_list);
+            rc = calllib(libname,'fpga_list',cstruct_list);
+            fpga_info_list = get(cstruct_list);
+            if rc ~= 0
+                fpga_info_list.num_fpgas = 0;
+                error('Error populating the fpga_info_list struct.');
+            end
+
+            for i=1:fpga_info_list.num_fpgas
+                fpga_info_list.names{i} = char(fpga_info_list.name(((i-1)*16)+1:(i*16)));
+            end
+            
+			fpga_info_list.id = fpga_info_list.id(1:fpga_info_list.num_fpgas);
+			fpga_info_list.num_chnls = fpga_info_list.num_chnls(1:fpga_info_list.num_fpgas);
+			fpga_info_list.vendor_id = fpga_info_list.vendor_id(1:fpga_info_list.num_fpgas);
+			fpga_info_list.device_id = fpga_info_list.device_id(1:fpga_info_list.num_fpgas);
+        end
+    end
+
+
+    methods (Static,Hidden,Access=private) 
+        function libname = load_lib()
+			% Loads the system library and returns the library name.
+            if ispc == 1
+                %disp('Running Windows platform');
+                sharedlibrary = 'C://Windows/System32/riffa.dll';
+				header = 'riffa.h';
+				libname = 'riffa';
+            elseif isunix == 1
+                %disp ('Running Unix platform');
+                sharedlibrary = '/usr/local/lib/libriffa.so';
+				header = '/usr/local/include/riffa.h';
+				libname = 'libriffa';
+            else
+                error('Not running a compatible OS.')
+            end              
+                        
+            if not (libisloaded(libname))
+                protoname = 'riffa_proto';
+                protoext = '.m';
+                if exist(strcat(protoname, protoext), 'file') ~= 2
+                    disp('Creating initial RIFFA library prototype for MATLAB.');
+                    loadlibrary(sharedlibrary, header, 'mfilename', protoname);
+                    buf = {};
+                    d = 0;
+                    searchexp = '''name''\s*,\s*''int8#''';
+                    replaceexp = '''name'', ''int8#80''';
+                    fd = fopen(strcat(protoname, protoext), 'r');
+                    while ~feof(fd)
+                       s = fgetl(fd);
+                       r = regexprep(s, searchexp, replaceexp);
+                       buf = vertcat(buf, r);
+                       d = or(d, ~isequal(r, s));                       
+                    end
+                    fclose(fd);
+                    if d == 1
+                        fd = fopen(strcat(protoname, protoext), 'w+');
+                        for i=1:size(buf, 1)
+                           fprintf(fd,'%s\n', buf{i});
+                        end
+                        fclose(fd);
+                        unloadlibrary(libname);
+                        disp('RIFFA library prototype created.');
+                        disp('This version of MATLAB has a bug that requires ');
+                        disp('you exit and restart MATLAB before continuing.');
+                        disp('You should only have to do this once, ever.');
+                        error('Exit MATLAB and restart please.');
+                    end
+                end
+                disp('Loading RIFFA library.')
+                loadlibrary(sharedlibrary, @riffa_proto);
+            end
+    	end
+	end
+    
+end
+
diff --git a/python/COMPILE.txt b/python/COMPILE.txt
new file mode 100644
index 0000000..b19a8e1
--- /dev/null
+++ b/python/COMPILE.txt
@@ -0,0 +1,5 @@
+No compilation is necessary. However to create a distribution simply execute:
+
+python setup.py sdist
+
+
diff --git a/python/MANIFEST b/python/MANIFEST
new file mode 100644
index 0000000..b42085f
--- /dev/null
+++ b/python/MANIFEST
@@ -0,0 +1,4 @@
+# file GENERATED by distutils, do NOT edit
+README.txt
+riffa.py
+setup.py
diff --git a/python/README.txt b/python/README.txt
new file mode 100644
index 0000000..0cb689a
--- /dev/null
+++ b/python/README.txt
@@ -0,0 +1,9 @@
+To install the Python bindings for RIFFA:
+
+1) Decompress the riffa-2.0 archive in the dist subdirectory
+2) Run: python setup.py install
+
+If you have any questions feel free to check out the 
+RIFFA website at http://cseweb.ucsd.edu/~mdjacobs
+
+
diff --git a/python/dist/README.txt b/python/dist/README.txt
new file mode 100644
index 0000000..d5d03f4
--- /dev/null
+++ b/python/dist/README.txt
@@ -0,0 +1,9 @@
+To install the Python bindings for RIFFA:
+
+1) Decompress the riffa-2.0 archive
+2) Run: python setup.py install
+
+If you have any questions feel free to check out the 
+RIFFA website at http://cseweb.ucsd.edu/~mdjacobs
+
+
diff --git a/python/dist/riffa-2.0.zip b/python/dist/riffa-2.0.zip
new file mode 100644
index 0000000..538bee7
Binary files /dev/null and b/python/dist/riffa-2.0.zip differ
diff --git a/python/riffa.py b/python/riffa.py
new file mode 100644
index 0000000..9633f4a
--- /dev/null
+++ b/python/riffa.py
@@ -0,0 +1,169 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+# Filename: riffa.py
+# Version: 2.0
+# Description: Python module for RIFFA.
+# Author: Matthew Jacobsen
+# History: @mattj: Initial release. Version 2.0.
+
+import ctypes
+import platform
+
+NUM_FPGAS = 5
+
+if platform.system() == "Linux":
+	libriffa = ctypes.CDLL("libriffa.so.1")
+else:
+	libriffa = ctypes.CDLL("riffa.dll")
+
+class FpgaInfoList(ctypes.Structure):
+	_fields_ = [("num_fpgas", ctypes.c_int),
+				("id", ctypes.c_int * NUM_FPGAS),
+				("num_chnls", ctypes.c_int * NUM_FPGAS),
+				("name", (ctypes.c_char * 16) * NUM_FPGAS),
+				("vendor_id", ctypes.c_int * NUM_FPGAS),
+				("device_id", ctypes.c_int * NUM_FPGAS)]
+	def __str__(self):
+		strl = []
+		strl.append("num fpgas: %d" % self.num_fpgas) 
+		for i in range(self.num_fpgas):
+			strl.append("fpga (%d) id: %d" % (i, self.id[i]))
+			strl.append("fpga (%d) name: %s" % (i, self.name[i].value))
+			strl.append("fpga (%d) num_chnls: %d" % (i, self.num_chnls[i]))
+			strl.append("fpga (%d) vendor_id: %x" % (i, self.vendor_id[i]))
+			strl.append("fpga (%d) device_id: %x" % (i, self.device_id[i]))
+		return '\n'.join(strl)
+
+
+# Populates and returns a FpgaInfoList with all FPGAs registered in the system.
+# Returns None on error.
+def fpga_list():
+	s = FpgaInfoList()
+	rc = libriffa.fpga_list(ctypes.byref(s))
+	if (rc == 0):
+		return s
+	else:
+		return None
+
+
+# Initializes the FPGA specified by id. On success, returns a descriptor. On 
+# error, returns None. Each FPGA must be opened before any channels can be 
+# accessed. Once opened, any number of threads can use the descriptor.
+def fpga_open(id):
+	return libriffa.fpga_open(id)
+
+# Cleans up memory/resources for the FPGA specified by the fd descriptor.
+def fpga_close(fd):
+	libriffa.fpga_close(fd)
+
+
+# Sends length words (4 byte words) from data to FPGA channel chnl using the 
+# fd descriptor. The data parameter must implement the buffer protocol 
+# interface so that a memoryview can be created from it. The FPGA channel will 
+# be sent length, destoff, and last. If last is True, the channel should 
+# interpret the end of this send as the end of a transaction. If last is False, 
+# the channel should wait for additional sends before the end of the 
+# transaction. If timeout is non-zero, this call will send data and wait up to 
+# timeout ms for the FPGA to respond (between packets) before timing out. If 
+# timeout is zero, this call may block indefinitely. Multiple threads sending 
+# on the same channel may result in corrupt data or error. This function is 
+# thread safe across channels. Returns the number of words sent. 
+def fpga_send(fd, chnl, data, length, destoff, last, timeout):
+	ptr = 0
+	datalen = 0
+	ilast = 0
+	if last:
+		ilast = 1
+	if length > 0:
+		
+		# Pre 3.0 workaround for array types (they don't implement the 3.0 
+		# buffer protocol interface despite documentation to the contrary).
+		if hasattr(data, 'buffer_info') and hasattr(data, 'itemsize'):
+			(ptr, datalen) = data.buffer_info()
+			datalen = datalen * data.itemsize
+		else:
+			m = memoryview(data)
+			obj = ctypes.py_object(m)
+			a = ctypes.c_void_p()
+			l = ctypes.c_size_t()
+			ctypes.pythonapi.PyObject_AsReadBuffer(obj, ctypes.byref(a), ctypes.byref(l))
+			ptr = a.value
+			datalen = l.value
+		if length > (datalen/4):
+			length = (datalen/4)
+	return libriffa.fpga_send(fd, chnl, ptr, length, destoff, ilast, timeout)
+
+
+# Receives data from the FPGA channel chnl to the supplied data object, using 
+# the fd descriptor. The supplied data object must implement the buffer 
+# protocol interface so that a memoryview can be created from it. The FPGA 
+# channel can send any amount of data, so the data object's backing array must
+# be large enough to accommodate. The FPGA channel will specify an offset which 
+# will determine where in the data object's backing array the data will start
+# being written. If the amount of data (plus offset) exceed the size of the 
+# data object's backing array, then additional data will be discarded. If 
+# timeout is non-zero, this call will wait up to timeout ms for the FPGA to 
+# respond (between packets) before timing out. If timeout is zero, this call 
+# may block indefinitely. Multiple threads receiving on the same channel may 
+# result in corrupt data or error. This function is thread safe across channels.
+# Returns the number of words received to the data array. 
+def fpga_recv(fd, chnl, data, timeout):
+	ptr = 0
+	datalen = 0
+	if data is not None:
+		# Pre 3.0 workaround for array types (they don't implement the 3.0 
+		# buffer protocol interface despite documentation to the contrary).
+		if hasattr(data, 'buffer_info') and hasattr(data, 'itemsize'):
+			(ptr, datalen) = data.buffer_info()
+			datalen = datalen * data.itemsize
+		else:
+			m = memoryview(data)
+			obj = ctypes.py_object(m)
+			a = ctypes.c_void_p()
+			l = ctypes.c_size_t()
+			ctypes.pythonapi.PyObject_AsReadBuffer(obj, ctypes.byref(a), ctypes.byref(l))
+			ptr = a.value
+			datalen = l.value
+	return libriffa.fpga_recv(fd, chnl, ptr, datalen/4, timeout)
+
+
+# Resets the state of the FPGA and all transfers across all channels. This is
+# meant to be used as an alternative to rebooting if an error occurs while 
+# sending/receiving. Calling this function while other threads are sending or
+# receiving will result in unexpected behavior.
+def fpga_reset(fd):
+	libriffa.fpga_reset(fd)
+
+
diff --git a/python/sample_app/sampleapp.py b/python/sample_app/sampleapp.py
new file mode 100644
index 0000000..98928b4
--- /dev/null
+++ b/python/sample_app/sampleapp.py
@@ -0,0 +1,22 @@
+# This sample application works with the chnl_tester module which receives data
+# and sends data back.
+
+import array
+import riffa
+
+amt = 200
+sent = 0
+recv = 0
+dataSend = array.array('I', range(amt+1))
+dataSend = dataSend[1:]
+dataRecv = array.array('I', [0]*amt)
+
+fd = riffa.fpga_open(0)
+sent = riffa.fpga_send(fd, 0, dataSend, amt, 0, True, 0)
+if (sent != 0):
+	recv = riffa.fpga_recv(fd, 0, dataRecv, 0)
+
+riffa.fpga_close(fd)
+print(dataSend)
+print(dataRecv)
+
diff --git a/python/setup.py b/python/setup.py
new file mode 100644
index 0000000..7bf6419
--- /dev/null
+++ b/python/setup.py
@@ -0,0 +1,84 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+# Filename: setup.py
+# Version: 2.0
+# Description: Python setup script for RIFFA.
+# Author: Matthew Jacobsen
+# History: @mattj: Initial release. Version 2.0.
+
+from distutils.core import setup
+setup(name='riffa',
+      version='2.0',
+      description='RIFFA 2.0 Python Library',
+      author='Matt Jacobsen',
+      author_email='mdjacobs@cs.ucsd.edu',
+      url='http://cseweb.ucsd.edu/~mdjacobs',
+      platforms='Linux,Windows',
+      license='Other/Proprietary License',
+      py_modules=['riffa'],
+      long_description='''
+Copyright (c) 2015, The Regents of the University of California All
+rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+    * Redistributions in binary form must reproduce the above
+      copyright notice, this list of conditions and the following
+      disclaimer in the documentation and/or other materials provided
+      with the distribution.
+
+    * Neither the name of The Regents of the University of California
+      nor the names of its contributors may be used to endorse or
+      promote products derived from this software without specific
+      prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+DAMAGE.'''
+      )