Initial commit of RIFFA development repository (RIFFA 2.2)

LICENSE

@@ -1,28 +1,34 @@
-Copyright (c) 2015, drichmond
-All rights reserved.
+----------------------------------------------------------------------
+Copyright (c) 2015, The Regents of the University of California All
+rights reserved.
 
 Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are
+met:
 
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
 
-* Redistributions in binary form must reproduce the above copyright notice,
-  this list of conditions and the following disclaimer in the documentation
-  and/or other materials provided with the distribution.
+    * Redistributions in binary form must reproduce the above
+      copyright notice, this list of conditions and the following
+      disclaimer in the documentation and/or other materials provided
+      with the distribution.
 
-* Neither the name of riffa-stable nor the names of its
-  contributors may be used to endorse or promote products derived from
-  this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+    * Neither the name of The Regents of the University of California
+      nor the names of its contributors may be used to endorse or
+      promote products derived from this software without specific
+      prior written permission.
 
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+DAMAGE.
+----------------------------------------------------------------------

c_c++/linux/x64/README.txt

@@ -0,0 +1,3 @@
+The Linux C/C++ library is compiled and installed with the kernel driver. This
+directory contains a sample application subdirectory that you can use to test
+your design. 

c_c++/linux/x64/sample_app/Makefile

@@ -0,0 +1,27 @@
+program_NAME := testutil
+program_C_SRCS := $(wildcard *.c)
+program_CXX_SRCS := $(wildcard *.cpp)
+program_C_OBJS := ${program_C_SRCS:.c=.o}
+program_CXX_OBJS := ${program_CXX_SRCS:.cpp=.o}
+program_OBJS := $(program_C_OBJS) $(program_CXX_OBJS)
+program_INCLUDE_DIRS :=
+program_LIBRARY_DIRS :=
+program_LIBRARIES := riffa
+CPPFLAGS += -g
+
+CPPFLAGS += $(foreach includedir,$(program_INCLUDE_DIRS),-I$(includedir))
+LDFLAGS += $(foreach librarydir,$(program_LIBRARY_DIRS),-L$(librarydir))
+LDFLAGS += $(foreach library,$(program_LIBRARIES),-l$(library))
+
+.PHONY: all clean distclean
+
+all: $(program_NAME)
+
+$(program_NAME): $(program_OBJS)
+	$(CC) $(CPPFLAGS) $(program_OBJS) -o $(program_NAME) $(LDFLAGS)
+
+clean:
+	@- $(RM) $(program_NAME)
+	@- $(RM) $(program_OBJS)
+
+distclean: clean

c_c++/linux/x64/sample_app/README.txt

@@ -0,0 +1,8 @@
+The testutil example application works with the Verilog chnl_tester module
+which receives data and then sends data back to the workstation. 
+
+To compile the example application:
+
+make
+
+The riffa C/C++ library must be installed (it gets installed with the driver).

c_c++/linux/x64/sample_app/testutil.c

@@ -0,0 +1,145 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include "timer.h"
+#include "riffa.h"
+
+int main(int argc, char** argv) {
+	fpga_t * fpga;
+	fpga_info_list info;
+	int option;
+	int i;
+	int id;
+	int chnl;
+	size_t numWords;
+	int sent;
+	int recvd;
+	unsigned int * sendBuffer;
+	unsigned int * recvBuffer;
+	GET_TIME_INIT(3);
+
+	if (argc < 2) {
+		printf("Usage: %s <option>\n", argv[0]);
+		return -1;
+	}
+
+	option = atoi(argv[1]);
+
+	if (option == 0) {	// List FPGA info
+		// Populate the fpga_info_list struct
+		if (fpga_list(&info) != 0) {
+			printf("Error populating fpga_info_list\n");
+			return -1;
+		}
+		printf("Number of devices: %d\n", info.num_fpgas);
+		for (i = 0; i < info.num_fpgas; i++) {
+			printf("%d: id:%d\n", i, info.id[i]);
+			printf("%d: num_chnls:%d\n", i, info.num_chnls[i]);
+			printf("%d: name:%s\n", i, info.name[i]);
+			printf("%d: vendor id:%04X\n", i, info.vendor_id[i]);
+			printf("%d: device id:%04X\n", i, info.device_id[i]);
+		}
+	}
+	else if (option == 1) { // Reset FPGA
+		if (argc < 3) {
+			printf("Usage: %s %d <fpga id>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Reset
+		fpga_reset(fpga);
+
+		// Done with device
+        fpga_close(fpga);
+	}
+	else if (option == 2) { // Send data, receive data
+		if (argc < 5) {
+			printf("Usage: %s %d <fpga id> <chnl> <num words to transfer>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+		chnl = atoi(argv[3]);
+		numWords = atoi(argv[4]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Malloc the arrays
+		sendBuffer = (unsigned int *)malloc(numWords<<2);
+		if (sendBuffer == NULL) {
+			printf("Could not malloc memory for sendBuffer\n");
+			fpga_close(fpga);
+			return -1;
+	    }
+		recvBuffer = (unsigned int *)malloc(numWords<<2);
+		if (recvBuffer == NULL) {
+			printf("Could not malloc memory for recvBuffer\n");
+			free(sendBuffer);
+			fpga_close(fpga);
+			return -1;
+	    }
+
+		// Initialize the data
+		for (i = 0; i < numWords; i++) {
+			sendBuffer[i] = i+1;
+			recvBuffer[i] = 0;
+		}
+
+		GET_TIME_VAL(0);
+
+		// Send the data
+		sent = fpga_send(fpga, chnl, sendBuffer, numWords, 0, 1, 25000);
+		printf("words sent: %d\n", sent);
+
+		GET_TIME_VAL(1);
+
+		if (sent != 0) {
+			// Recv the data
+			recvd = fpga_recv(fpga, chnl, recvBuffer, numWords, 25000);
+			printf("words recv: %d\n", recvd);
+		}
+
+		GET_TIME_VAL(2);
+
+		// Done with device
+        fpga_close(fpga);
+
+		// Display some data
+		for (i = 0; i < 20; i++) {
+			printf("recvBuffer[%d]: %d\n", i, recvBuffer[i]);
+		}
+
+		// Check the data
+		if (recvd != 0) {
+			for (i = 4; i < recvd; i++) {
+				if (recvBuffer[i] != sendBuffer[i]) {
+					printf("recvBuffer[%d]: %d, expected %d\n", i, recvBuffer[i], sendBuffer[i]);
+					break;
+				}
+			}
+
+			printf("send bw: %f MB/s %fms\n",
+				sent*4.0/1024/1024/((TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0))/1000.0),
+				(TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0)) );
+
+			printf("recv bw: %f MB/s %fms\n",
+				recvd*4.0/1024/1024/((TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1))/1000.0),
+				(TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1)) );
+		}
+	}
+
+	return 0;
+}

c_c++/linux/x64/sample_app/timer.h

@@ -0,0 +1,8 @@
+#include <sys/time.h>
+
+#define GET_TIME_INIT(num) struct timeval _timers[num]
+
+#define GET_TIME_VAL(num) gettimeofday(&_timers[num], NULL)
+
+#define TIME_VAL_TO_MS(num) (((double)_timers[num].tv_sec*1000.0) + ((double)_timers[num].tv_usec/1000.0))
+

c_c++/linux/x86/README.txt

@@ -0,0 +1,3 @@
+The Linux C/C++ library is compiled and installed with the kernel driver. This
+directory contains a sample application subdirectory that you can use to test
+your design. 

c_c++/linux/x86/sample_app/Makefile

@@ -0,0 +1,27 @@
+program_NAME := testutil
+program_C_SRCS := $(wildcard *.c)
+program_CXX_SRCS := $(wildcard *.cpp)
+program_C_OBJS := ${program_C_SRCS:.c=.o}
+program_CXX_OBJS := ${program_CXX_SRCS:.cpp=.o}
+program_OBJS := $(program_C_OBJS) $(program_CXX_OBJS)
+program_INCLUDE_DIRS :=
+program_LIBRARY_DIRS :=
+program_LIBRARIES := riffa
+CPPFLAGS += -g
+
+CPPFLAGS += $(foreach includedir,$(program_INCLUDE_DIRS),-I$(includedir))
+LDFLAGS += $(foreach librarydir,$(program_LIBRARY_DIRS),-L$(librarydir))
+LDFLAGS += $(foreach library,$(program_LIBRARIES),-l$(library))
+
+.PHONY: all clean distclean
+
+all: $(program_NAME)
+
+$(program_NAME): $(program_OBJS)
+	$(CC) $(CPPFLAGS) $(program_OBJS) -o $(program_NAME) $(LDFLAGS)
+
+clean:
+	@- $(RM) $(program_NAME)
+	@- $(RM) $(program_OBJS)
+
+distclean: clean

c_c++/linux/x86/sample_app/README.txt

@@ -0,0 +1,8 @@
+The testutil example application works with the Verilog chnl_tester module
+which receives data and then sends data back to the workstation. 
+
+To compile the example application:
+
+make
+
+The riffa C/C++ library must be installed (it gets installed with the driver).

c_c++/linux/x86/sample_app/testutil.c

@@ -0,0 +1,145 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include "timer.h"
+#include "riffa.h"
+
+int main(int argc, char** argv) {
+	fpga_t * fpga;
+	fpga_info_list info;
+	int option;
+	int i;
+	int id;
+	int chnl;
+	size_t numWords;
+	int sent;
+	int recvd;
+	unsigned int * sendBuffer;
+	unsigned int * recvBuffer;
+	GET_TIME_INIT(3);
+
+	if (argc < 2) {
+		printf("Usage: %s <option>\n", argv[0]);
+		return -1;
+	}
+
+	option = atoi(argv[1]);
+
+	if (option == 0) {	// List FPGA info
+		// Populate the fpga_info_list struct
+		if (fpga_list(&info) != 0) {
+			printf("Error populating fpga_info_list\n");
+			return -1;
+		}
+		printf("Number of devices: %d\n", info.num_fpgas);
+		for (i = 0; i < info.num_fpgas; i++) {
+			printf("%d: id:%d\n", i, info.id[i]);
+			printf("%d: num_chnls:%d\n", i, info.num_chnls[i]);
+			printf("%d: name:%s\n", i, info.name[i]);
+			printf("%d: vendor id:%04X\n", i, info.vendor_id[i]);
+			printf("%d: device id:%04X\n", i, info.device_id[i]);
+		}
+	}
+	else if (option == 1) { // Reset FPGA
+		if (argc < 3) {
+			printf("Usage: %s %d <fpga id>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Reset
+		fpga_reset(fpga);
+
+		// Done with device
+        fpga_close(fpga);
+	}
+	else if (option == 2) { // Send data, receive data
+		if (argc < 5) {
+			printf("Usage: %s %d <fpga id> <chnl> <num words to transfer>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+		chnl = atoi(argv[3]);
+		numWords = atoi(argv[4]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Malloc the arrays
+		sendBuffer = (unsigned int *)malloc(numWords<<2);
+		if (sendBuffer == NULL) {
+			printf("Could not malloc memory for sendBuffer\n");
+			fpga_close(fpga);
+			return -1;
+	    }
+		recvBuffer = (unsigned int *)malloc(numWords<<2);
+		if (recvBuffer == NULL) {
+			printf("Could not malloc memory for recvBuffer\n");
+			free(sendBuffer);
+			fpga_close(fpga);
+			return -1;
+	    }
+
+		// Initialize the data
+		for (i = 0; i < numWords; i++) {
+			sendBuffer[i] = i+1;
+			recvBuffer[i] = 0;
+		}
+
+		GET_TIME_VAL(0);
+
+		// Send the data
+		sent = fpga_send(fpga, chnl, sendBuffer, numWords, 0, 1, 25000);
+		printf("words sent: %d\n", sent);
+
+		GET_TIME_VAL(1);
+
+		if (sent != 0) {
+			// Recv the data
+			recvd = fpga_recv(fpga, chnl, recvBuffer, numWords, 25000);
+			printf("words recv: %d\n", recvd);
+		}
+
+		GET_TIME_VAL(2);
+
+		// Done with device
+        fpga_close(fpga);
+
+		// Display some data
+		for (i = 0; i < 20; i++) {
+			printf("recvBuffer[%d]: %d\n", i, recvBuffer[i]);
+		}
+
+		// Check the data
+		if (recvd != 0) {
+			for (i = 4; i < recvd; i++) {
+				if (recvBuffer[i] != sendBuffer[i]) {
+					printf("recvBuffer[%d]: %d, expected %d\n", i, recvBuffer[i], sendBuffer[i]);
+					break;
+				}
+			}
+
+			printf("send bw: %f MB/s %fms\n",
+				sent*4.0/1024/1024/((TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0))/1000.0),
+				(TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0)) );
+
+			printf("recv bw: %f MB/s %fms\n",
+				recvd*4.0/1024/1024/((TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1))/1000.0),
+				(TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1)) );
+		}
+	}
+
+	return 0;
+}

c_c++/linux/x86/sample_app/timer.h

@@ -0,0 +1,8 @@
+#include <sys/time.h>
+
+#define GET_TIME_INIT(num) struct timeval _timers[num]
+
+#define GET_TIME_VAL(num) gettimeofday(&_timers[num], NULL)
+
+#define TIME_VAL_TO_MS(num) (((double)_timers[num].tv_sec*1000.0) + ((double)_timers[num].tv_usec/1000.0))
+

c_c++/windows/x64/README.txt

@@ -0,0 +1,14 @@
+To build the C/C++ library:
+
+windres.exe riffa.rc resource.o
+gcc.exe -m64 -c -o riffa.o riffa.c -D RIFFA_EXPORTS
+gcc.exe -m64 -o riffa.dll riffa.o resource.o -s -shared -Wl,--subsystem,windows,--out-implib,riffa.lib -luser32 -lsetupapi
+del riffa.lib
+gendef riffa.dll
+lib /def:riffa.def /machine:X64 /out:riffa.lib
+
+This will compile the resource file for the dll (metadata properties for the 
+.dll). This will also produce a .dll and .lib file. The .dll is the dynamic
+library. The .lib file is the import library. You will want to copy the .dll
+into say Windows\System32. You will want to use the .h file and the .lib files
+when compiling and linking your applications.

c_c++/windows/x64/riffa.c

@@ -0,0 +1,431 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.c
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#define INITGUID
+
+#include <windows.h>
+#include <setupapi.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "riffa_driver.h"
+#include "riffa.h"
+
+// The structure used to hold data transfer information
+typedef struct RIFFA_FPGA_CHNL_IO {
+	UINT32					Id;
+	UINT32					Chnl;
+	UINT32					Length;
+	UINT32					Offset;
+	UINT32					Last;
+	UINT64					Timeout;
+} RIFFA_FPGA_CHNL_IO, * PRIFFA_FPGA_CHNL_IO;
+
+// Represents the FPGA device
+struct fpga_t
+{
+	HANDLE dev;
+	int id;
+};
+
+HANDLE get_device(UINT32 index, BOOLEAN overlapped);
+DWORD fill_device_info(fpga_info_list * info);
+
+fpga_t * RIFFACALL fpga_open(int id) {
+	fpga_t * fpga;
+
+	// Allocate space for the fpga_dev
+	fpga = (fpga_t *)malloc(sizeof(fpga_t));
+	if (fpga == NULL)
+		return NULL;
+	fpga->id = id;
+
+	// Open the device handle.
+	fpga->dev = get_device(id, TRUE);
+	if (fpga->dev == INVALID_HANDLE_VALUE) {
+		free(fpga);
+		return NULL;
+	}
+
+	return fpga;
+}
+
+void RIFFACALL fpga_close(fpga_t * fpga) {
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return;
+	}
+
+	// Close the device handle.
+	CloseHandle(fpga->dev);
+	fpga->dev = NULL;
+
+	// Free the fpga_t struct
+	free(fpga);
+}
+
+int RIFFACALL fpga_send(fpga_t * fpga, int chnl, void * data, int len,
+	int destoff, int last, long long timeout) {
+	RIFFA_FPGA_CHNL_IO io;
+	OVERLAPPED overlapStruct = {0};
+	HANDLE evt;
+	BOOLEAN status;
+	ULONG wordsReturned;
+
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return 0;
+	}
+
+	// Initialize the RIFFA_FPGA_CHNL_IO struct
+	io.Id = fpga->id;
+	io.Chnl = chnl;
+	io.Length = len;
+	io.Offset = destoff;
+	io.Last = last;
+	io.Timeout = timeout;
+
+	// Create a thread specific event to wait on.
+	evt = CreateEvent(NULL, TRUE, TRUE, NULL);
+	overlapStruct.hEvent = evt;
+
+	// Call IOCTL with IOCTL_RIFFA_SEND
+	status = DeviceIoControl(fpga->dev, IOCTL_RIFFA_SEND, (LPVOID)&io,
+		sizeof(io), data, (len<<2), &wordsReturned, &overlapStruct);
+	if(!status) {
+		// Should be the IO Pending error
+		if(GetLastError() == ERROR_IO_PENDING) {
+			// Wait for the IOCTL to complete and get the return value
+			WaitForSingleObject(evt, INFINITE);
+			status = GetOverlappedResult(fpga->dev, &overlapStruct,
+				&wordsReturned, FALSE);
+			if(!status) {
+				if (GetLastError() == ERROR_OPERATION_ABORTED)
+					printf("Operation timed out or was aborted\n");
+				else
+					printf("Error in GetOverlappedResult: %d\n", GetLastError());
+			}
+		}
+		else {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+		}
+	}
+	return wordsReturned;
+}
+
+int RIFFACALL fpga_recv(fpga_t * fpga, int chnl, void * data, int len,
+	long long timeout) {
+	RIFFA_FPGA_CHNL_IO io;
+	OVERLAPPED overlapStruct = {0};
+	HANDLE evt;
+	BOOLEAN status;
+	ULONG wordsReturned;
+
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return 0;
+	}
+
+	// Initialize the RIFFA_FPGA_CHNL_IO struct
+	io.Id = fpga->id;
+	io.Chnl = chnl;
+	io.Length = len;
+	io.Timeout = timeout;
+
+	// Create a thread specific event to wait on.
+	evt = CreateEvent(NULL, TRUE, TRUE, NULL);
+	overlapStruct.hEvent = evt;
+
+	// Call IOCTL with IOCTL_RIFFA_RECV
+	status = DeviceIoControl(fpga->dev, IOCTL_RIFFA_RECV, (LPVOID)&io,
+		sizeof(io), data, (len<<2), &wordsReturned, &overlapStruct);
+	if(!status) {
+		// Should be the IO Pending error
+		if(GetLastError() == ERROR_IO_PENDING) {
+			// Wait for the IOCTL to complete and get the return value
+			WaitForSingleObject(evt, INFINITE);
+			status = GetOverlappedResult(fpga->dev, &overlapStruct,
+				&wordsReturned, FALSE);
+			if(!status) {
+				if (GetLastError() == ERROR_OPERATION_ABORTED)
+					printf("Operation timed out or was aborted\n");
+				else
+					printf("Error in GetOverlappedResult: %d\n", GetLastError());
+			}
+		}
+		else {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+		}
+	}
+	return wordsReturned;
+}
+
+void RIFFACALL fpga_reset(fpga_t * fpga) {
+	BOOLEAN status;
+	OVERLAPPED overlapStruct = {0};
+	ULONG wordsReturned;
+
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return;
+	}
+
+	// Call IOCTL with IOCTL_RIFFA_RESET. Must use the overlapped struct as the
+	// device was opened with overlap support.
+	status = DeviceIoControl(fpga->dev, IOCTL_RIFFA_RESET, NULL, 0, NULL, 0,
+		&wordsReturned, &overlapStruct);
+	if(!status) {
+		// Should be the IO Pending error
+		if(GetLastError() == ERROR_IO_PENDING) {
+			// Wait for the IOCTL to complete and get the return value
+			status = GetOverlappedResult(fpga->dev, &overlapStruct,
+				&wordsReturned, TRUE);
+			if(!status)
+				printf("Error in GetOverlappedResult: %d\n", GetLastError());
+		}
+		else {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+		}
+	}
+}
+
+int RIFFACALL fpga_list(fpga_info_list * list) {
+	// Populate the fpga_info_list struct
+	list->num_fpgas = 0;
+	return (int)fill_device_info(list);
+}
+
+/**
+ * Returns a handle to the FPGA device specified by index. On failure, returns
+ * an INVALID_HANDLE_VALUE. If the value of overlapped is TRUE, the device
+ * handle will be opened with flag FILE_FLAG_OVERLAPPED to signal that future
+ * operations will use overlapped IO. If the value of overlapped is FALSE, the
+ * device handle will be opened with flag FILE_ATTRIBUTE_NORMAL and no
+ * overlapped IO can be used with the returned device handle.
+ */
+HANDLE get_device(UINT32 index, BOOLEAN overlapped) {
+    PSP_DEVICE_INTERFACE_DETAIL_DATA devIntfDetail;
+    SP_DEVICE_INTERFACE_DATA devIntfData;
+    SP_DEVINFO_DATA devInfoData;
+    SECURITY_ATTRIBUTES secAttr;
+    HDEVINFO devInfo;
+    BOOLEAN status = TRUE;
+    ULONG size;
+    HANDLE dev;
+    DWORD flags;
+
+    //  Retreive the device information for all RIFFA devices.
+    devInfo = SetupDiGetClassDevs(&GUID_RIFFA_INTERFACE, NULL, NULL,
+    	DIGCF_DEVICEINTERFACE | DIGCF_PRESENT);
+	if (devInfo == INVALID_HANDLE_VALUE) {
+        printf("SetupDiGetClassDevs failed, Error: %d\n", GetLastError());
+        return INVALID_HANDLE_VALUE;
+	}
+
+    //  Initialize the appropriate data structures for the SetupDi calls.
+    devIntfData.cbSize = sizeof(SP_DEVICE_INTERFACE_DATA);
+    devInfoData.cbSize = sizeof(SP_DEVINFO_DATA);
+
+    //  Get information for specific device.
+    status = SetupDiEnumDeviceInterfaces(devInfo, NULL, (LPGUID)&GUID_RIFFA_INTERFACE,
+    	index, &devIntfData);
+    if (!status) {
+        printf("SetupDiEnumDeviceInterfaces failed, Error: %d\n", GetLastError());
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+    // Determine the size required for the devIntfData
+    SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, NULL, 0, &size, NULL);
+    if (GetLastError() != ERROR_INSUFFICIENT_BUFFER) {
+        printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+    devIntfDetail = (PSP_DEVICE_INTERFACE_DETAIL_DATA)malloc(size);
+    if (!devIntfDetail) {
+        printf("Insufficient memory.\n");
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+    // Initialize structure and retrieve data.
+    devIntfDetail->cbSize = sizeof(SP_DEVICE_INTERFACE_DETAIL_DATA);
+    status = SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, devIntfDetail,
+    	size, NULL, &devInfoData);
+    if (!status) {
+        printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+        free(devIntfDetail);
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+	// Prepare the security attributes for interitance.
+	secAttr.nLength = sizeof(SECURITY_ATTRIBUTES);
+	secAttr.bInheritHandle = TRUE;
+	secAttr.lpSecurityDescriptor = NULL;
+
+	// Get the device handle itself (finally!)
+	flags = (overlapped ? FILE_FLAG_OVERLAPPED : FILE_ATTRIBUTE_NORMAL);
+	flags = flags | FILE_FLAG_NO_BUFFERING;
+	dev = CreateFile(devIntfDetail->DevicePath, GENERIC_READ|GENERIC_WRITE,
+		FILE_SHARE_READ | FILE_SHARE_WRITE, &secAttr, OPEN_EXISTING, flags, NULL);
+	if (dev == INVALID_HANDLE_VALUE) {
+		printf("CreateFile failed.  Error:%d\n", GetLastError());
+        free(devIntfDetail);
+		SetupDiDestroyDeviceInfoList(devInfo);
+		return INVALID_HANDLE_VALUE;
+	}
+	free(devIntfDetail);
+	SetupDiDestroyDeviceInfoList(devInfo);
+
+    return dev;
+}
+
+/**
+ * Populates the specified fpga_info_list struct with FPGA information. Returns
+ * zero on success. On failure, returns an error code (positive value).
+ */
+DWORD fill_device_info(fpga_info_list * info) {
+    PSP_DEVICE_INTERFACE_DETAIL_DATA devIntfDetail;
+    SP_DEVICE_INTERFACE_DATA devIntfData;
+    SP_DEVINFO_DATA devInfoData;
+    HDEVINFO devInfo;
+    BOOLEAN status = TRUE;
+    ULONG size;
+    UINT32 i;
+    ULONG wordsReturned;
+    HANDLE dev;
+
+    //  Retreive the device information for all RIFFA devices.
+    devInfo = SetupDiGetClassDevs(&GUID_RIFFA_INTERFACE, NULL, NULL,
+    	DIGCF_DEVICEINTERFACE | DIGCF_PRESENT);
+	if (devInfo == INVALID_HANDLE_VALUE) {
+        printf("SetupDiGetClassDevs failed, Error: %d\n", GetLastError());
+        return GetLastError();
+	}
+
+    //  Initialize the appropriate data structures for the SetupDi calls.
+    devIntfData.cbSize = sizeof(SP_DEVICE_INTERFACE_DATA);
+    devInfoData.cbSize = sizeof(SP_DEVINFO_DATA);
+
+    //  Loop through the device list.
+    i = 0;
+    while (SetupDiEnumDeviceInterfaces(devInfo, NULL, (LPGUID)&GUID_RIFFA_INTERFACE,
+    	i, &devIntfData)) {
+        // Determine the size required for the devIntfData
+        SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, NULL, 0, &size, NULL);
+        if (GetLastError() != ERROR_INSUFFICIENT_BUFFER) {
+            printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+			SetupDiDestroyDeviceInfoList(devInfo);
+            return GetLastError();
+        }
+
+		// Create the SP_DEVICE_INTERFACE_DETAIL_DATA
+        devIntfDetail = (PSP_DEVICE_INTERFACE_DETAIL_DATA)malloc(size);
+        if (!devIntfDetail) {
+            printf("Insufficient memory.\n");
+			SetupDiDestroyDeviceInfoList(devInfo);
+            return ERROR_NOT_ENOUGH_MEMORY;
+        }
+
+		// Initialize structure and retrieve data.
+		devIntfDetail->cbSize = sizeof(SP_DEVICE_INTERFACE_DETAIL_DATA);
+		status = SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, devIntfDetail,
+			size, NULL, &devInfoData);
+		if (!status) {
+			printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+	        free(devIntfDetail);
+			SetupDiDestroyDeviceInfoList(devInfo);
+			return GetLastError();
+		}
+
+		// Get the device handle itself (no overlap)
+		dev = CreateFile(devIntfDetail->DevicePath, GENERIC_READ|GENERIC_WRITE,
+			FILE_SHARE_READ | FILE_SHARE_WRITE, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL);
+		if (dev == INVALID_HANDLE_VALUE) {
+			printf("CreateFile failed.  Error:%d\n", GetLastError());
+	        free(devIntfDetail);
+			SetupDiDestroyDeviceInfoList(devInfo);
+			return GetLastError();
+		}
+
+		// Call IOCTL with IOCTL_RIFFA_LIST
+		status = DeviceIoControl(dev, IOCTL_RIFFA_LIST, (LPVOID)&i, sizeof(i),
+			(LPVOID)info, sizeof(*info), &wordsReturned, NULL);
+		if (!status) {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+	        CloseHandle(dev);
+	        free(devIntfDetail);
+			SetupDiDestroyDeviceInfoList(devInfo);
+			return GetLastError();
+		}
+		info->num_fpgas = info->num_fpgas + 1;
+
+		// Done with the device
+		CloseHandle(dev);
+		free(devIntfDetail);
+
+        // Cycle through the available devices.
+        i++;
+    }
+
+	// Done with the DeviceInfo
+	SetupDiDestroyDeviceInfoList(devInfo);
+
+	return 0;
+}
+
+
+

c_c++/windows/x64/riffa.def

@@ -0,0 +1,13 @@
+;
+; Definition file of riffa.dll
+; Automatic generated by gendef
+; written by Kai Tietz 2008
+;
+LIBRARY "riffa.dll"
+EXPORTS
+fpga_close
+fpga_list
+fpga_open
+fpga_recv
+fpga_reset
+fpga_send

c_c++/windows/x64/riffa.h

@@ -0,0 +1,150 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.h
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#ifndef RIFFA_H
+#define RIFFA_H
+
+// Must RIFFA_EXPORTS *only* when building the DLL.
+#ifdef RIFFA_EXPORTS
+  #define RIFFAAPI __declspec(dllexport)
+#else
+  #define RIFFAAPI __declspec(dllimport)
+#endif
+
+// Define calling convention in one place, for convenience.
+#define RIFFACALL __cdecl
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Maximum number of RIFFA FPGAs
+#define RIFFA_MAX_NUM_FPGAS (5)
+
+// Holds FPGA information for installed RIFFA FPGAs
+struct fpga_info_list
+{
+	int num_fpgas;
+	int id[RIFFA_MAX_NUM_FPGAS];
+	int num_chnls[RIFFA_MAX_NUM_FPGAS];
+	char name[RIFFA_MAX_NUM_FPGAS][16];
+	int vendor_id[RIFFA_MAX_NUM_FPGAS];
+	int device_id[RIFFA_MAX_NUM_FPGAS];
+};
+typedef struct fpga_info_list fpga_info_list;
+
+// Represents the FPGA device
+struct fpga_t;
+typedef struct fpga_t fpga_t;
+
+/**
+ * Populates the fpga_info_list pointer with all FPGAs registered in the system.
+ * Returns 0 on success, non-zero on error.
+ */
+RIFFAAPI int RIFFACALL fpga_list(fpga_info_list * list);
+
+/**
+ * Initializes the FPGA specified by id. On success, returns a pointer to a
+ * fpga_t struct. On error, returns NULL. Each FPGA must be opened before any
+ * channels can be accessed. Once opened, any number of threads can use the
+ * fpga_t struct.
+ */
+RIFFAAPI fpga_t * RIFFACALL fpga_open(int id);
+
+/**
+ * Cleans up memory/resources for the FPGA specified by the fd descriptor.
+ */
+RIFFAAPI void RIFFACALL fpga_close(fpga_t * fpga);
+
+/**
+ * Sends len words (4 byte words) from data to FPGA channel chnl using the
+ * fpga_t struct. The FPGA channel will be sent len, destoff, and last. If last
+ * is 1, the channel should interpret the end of this send as the end of a
+ * transaction. If last is 0, the channel should wait for additional sends
+ * before the end of the transaction. If timeout is non-zero, this call will
+ * send data and wait up to timeout ms for the FPGA to respond (between
+ * packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads sending on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words sent.
+ */
+RIFFAAPI int RIFFACALL fpga_send(fpga_t * fpga, int chnl, void * data, int len,
+	int destoff, int last, long long timeout);
+
+/**
+ * Receives data from the FPGA channel chnl to the data pointer, using the
+ * fpga_t struct. The FPGA channel can send any amount of data, so the data
+ * array should be large enough to accommodate. The len parameter specifies the
+ * actual size of the data buffer in words (4 byte words). The FPGA channel will
+ * specify an offset which will determine where in the data array the data will
+ * start being written. If the amount of data (plus offset) exceed the size of
+ * the data array (len), then that data will be discarded. If timeout is
+ * non-zero, this call will wait up to timeout ms for the FPGA to respond
+ * (between packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads receiving on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words received to the data array.
+ */
+RIFFAAPI int RIFFACALL fpga_recv(fpga_t * fpga, int chnl, void * data, int len,
+	long long timeout);
+
+/**
+ * Resets the state of the FPGA and all transfers across all channels. This is
+ * meant to be used as an alternative to rebooting if an error occurs while
+ * sending/receiving. Calling this function while other threads are sending or
+ * receiving will result in unexpected behavior.
+ */
+RIFFAAPI void RIFFACALL fpga_reset(fpga_t * fpga);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

c_c++/windows/x64/riffa.rc

@@ -0,0 +1,83 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.rc
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+1 VERSIONINFO
+ FILEVERSION 1,0,0,0
+ PRODUCTVERSION 2,0,0,0
+ FILEFLAGSMASK 0x17L
+#ifdef _DEBUG
+ FILEFLAGS 0x1L
+#else
+ FILEFLAGS 0x0L
+#endif
+ FILEOS 0x4L
+ FILETYPE 0x1L
+ FILESUBTYPE 0x0L
+BEGIN
+    BLOCK "StringFileInfo"
+    BEGIN
+        BLOCK "040904b0"
+        BEGIN
+            VALUE "Comments", "RIFFA 64 bit Windows Library"
+            VALUE "CompanyName", "University of California, San Diego"
+            VALUE "FileDescription", "User 64 bit library for RIFFA."
+            VALUE "FileVersion", "1, 0, 0, 0"
+            VALUE "InternalName", "RIFFA"
+            VALUE "LegalCopyright", "Copyright <20> 2011 The Regents of the University of California. All Rights Reserved."
+            VALUE "OriginalFilename", "riffa.dll"
+            VALUE "ProductName", "RIFFA Library"
+            VALUE "ProductVersion", "2, 0, 0, 0"
+        END
+    END
+    BLOCK "VarFileInfo"
+    BEGIN
+        VALUE "Translation", 0x409, 1200
+    END
+END

c_c++/windows/x64/riffa_driver.h

@@ -0,0 +1,19 @@
+//
+// The following value is arbitrarily chosen from the space defined
+// by Microsoft as being "for non-Microsoft use"
+//
+//
+// {40d49fb9-6085-4e1d-8753-822be944d7bb}
+DEFINE_GUID (GUID_RIFFA_INTERFACE,
+   0x40d49fb9, 0x6085, 0x4e1d, 0x87, 0x53, 0x82, 0x2b, 0xe9, 0x44, 0xd7, 0xbb);
+
+// The IOCTL function codes from 0x800 to 0xFFF are for customer use.
+#define IOCTL_RIFFA_SEND \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x900, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)
+#define IOCTL_RIFFA_RECV \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x901, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)
+#define IOCTL_RIFFA_LIST \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x902, METHOD_OUT_DIRECT ,FILE_ANY_ACCESS)
+#define IOCTL_RIFFA_RESET \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x903, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)
+

c_c++/windows/x64/sample_app/README.txt

@@ -0,0 +1,10 @@
+The testutil example application works with the Verilog chnl_tester module
+which receives data and then sends data back to the workstation. 
+
+To compile the example application:
+
+gcc.exe -o testutil.exe testutil.c -L. -lriffa
+
+The riffa.lib import library must be in the directory specified by the -L 
+parameter (in this example, the current directory). The riffa.h header must be
+in the same directory as testutil.c.

c_c++/windows/x64/sample_app/riffa.h

@@ -0,0 +1,150 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.h
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#ifndef RIFFA_H
+#define RIFFA_H
+
+// Must RIFFA_EXPORTS *only* when building the DLL.
+#ifdef RIFFA_EXPORTS
+  #define RIFFAAPI __declspec(dllexport)
+#else
+  #define RIFFAAPI __declspec(dllimport)
+#endif
+
+// Define calling convention in one place, for convenience.
+#define RIFFACALL __cdecl
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Maximum number of RIFFA FPGAs
+#define RIFFA_MAX_NUM_FPGAS (5)
+
+// Holds FPGA information for installed RIFFA FPGAs
+struct fpga_info_list
+{
+	int num_fpgas;
+	int id[RIFFA_MAX_NUM_FPGAS];
+	int num_chnls[RIFFA_MAX_NUM_FPGAS];
+	char name[RIFFA_MAX_NUM_FPGAS][16];
+	int vendor_id[RIFFA_MAX_NUM_FPGAS];
+	int device_id[RIFFA_MAX_NUM_FPGAS];
+};
+typedef struct fpga_info_list fpga_info_list;
+
+// Represents the FPGA device
+struct fpga_t;
+typedef struct fpga_t fpga_t;
+
+/**
+ * Populates the fpga_info_list pointer with all FPGAs registered in the system.
+ * Returns 0 on success, non-zero on error.
+ */
+RIFFAAPI int RIFFACALL fpga_list(fpga_info_list * list);
+
+/**
+ * Initializes the FPGA specified by id. On success, returns a pointer to a
+ * fpga_t struct. On error, returns NULL. Each FPGA must be opened before any
+ * channels can be accessed. Once opened, any number of threads can use the
+ * fpga_t struct.
+ */
+RIFFAAPI fpga_t * RIFFACALL fpga_open(int id);
+
+/**
+ * Cleans up memory/resources for the FPGA specified by the fd descriptor.
+ */
+RIFFAAPI void RIFFACALL fpga_close(fpga_t * fpga);
+
+/**
+ * Sends len words (4 byte words) from data to FPGA channel chnl using the
+ * fpga_t struct. The FPGA channel will be sent len, destoff, and last. If last
+ * is 1, the channel should interpret the end of this send as the end of a
+ * transaction. If last is 0, the channel should wait for additional sends
+ * before the end of the transaction. If timeout is non-zero, this call will
+ * send data and wait up to timeout ms for the FPGA to respond (between
+ * packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads sending on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words sent.
+ */
+RIFFAAPI int RIFFACALL fpga_send(fpga_t * fpga, int chnl, void * data, int len,
+	int destoff, int last, long long timeout);
+
+/**
+ * Receives data from the FPGA channel chnl to the data pointer, using the
+ * fpga_t struct. The FPGA channel can send any amount of data, so the data
+ * array should be large enough to accommodate. The len parameter specifies the
+ * actual size of the data buffer in words (4 byte words). The FPGA channel will
+ * specify an offset which will determine where in the data array the data will
+ * start being written. If the amount of data (plus offset) exceed the size of
+ * the data array (len), then that data will be discarded. If timeout is
+ * non-zero, this call will wait up to timeout ms for the FPGA to respond
+ * (between packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads receiving on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words received to the data array.
+ */
+RIFFAAPI int RIFFACALL fpga_recv(fpga_t * fpga, int chnl, void * data, int len,
+	long long timeout);
+
+/**
+ * Resets the state of the FPGA and all transfers across all channels. This is
+ * meant to be used as an alternative to rebooting if an error occurs while
+ * sending/receiving. Calling this function while other threads are sending or
+ * receiving will result in unexpected behavior.
+ */
+RIFFAAPI void RIFFACALL fpga_reset(fpga_t * fpga);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

c_c++/windows/x64/sample_app/testutil.c

@@ -0,0 +1,146 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include <windows.h>
+#include "timer.h"
+#include "riffa.h"
+
+int main(int argc, char** argv) {
+	fpga_t * fpga;
+	fpga_info_list info;
+	int option;
+	int i;
+	int id;
+	int chnl;
+	size_t numWords;
+	int sent;
+	int recvd;
+	unsigned int * sendBuffer;
+	unsigned int * recvBuffer;
+	GET_TIME_INIT(3);
+
+	if (argc < 2) {
+		printf("Usage: %s <option>\n", argv[0]);
+		return -1;
+	}
+
+	option = atoi(argv[1]);
+
+	if (option == 0) {	// List FPGA info
+		// Populate the fpga_info_list struct
+		if (fpga_list(&info) != 0) {
+			printf("Error populating fpga_info_list\n");
+			return -1;
+		}
+		printf("Number of devices: %d\n", info.num_fpgas);
+		for (i = 0; i < info.num_fpgas; i++) {
+			printf("%d: id:%d\n", i, info.id[i]);
+			printf("%d: num_chnls:%d\n", i, info.num_chnls[i]);
+			printf("%d: name:%s\n", i, info.name[i]);
+			printf("%d: vendor id:%04X\n", i, info.vendor_id[i]);
+			printf("%d: device id:%04X\n", i, info.device_id[i]);
+		}
+	}
+	else if (option == 1) { // Reset FPGA
+		if (argc < 3) {
+			printf("Usage: %s %d <fpga id>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Reset
+		fpga_reset(fpga);
+
+		// Done with device
+        fpga_close(fpga);
+	}
+	else if (option == 2) { // Send data, receive data
+		if (argc < 5) {
+			printf("Usage: %s %d <fpga id> <chnl> <num words to transfer>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+		chnl = atoi(argv[3]);
+		numWords = atoi(argv[4]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Malloc the arrays
+		sendBuffer = (unsigned int *)malloc(numWords<<2);
+		if (sendBuffer == NULL) {
+			printf("Could not malloc memory for sendBuffer\n");
+			fpga_close(fpga);
+			return -1;
+	    }
+		recvBuffer = (unsigned int *)malloc(numWords<<2);
+		if (recvBuffer == NULL) {
+			printf("Could not malloc memory for recvBuffer\n");
+			free(sendBuffer);
+			fpga_close(fpga);
+			return -1;
+	    }
+
+		// Initialize the data
+		for (i = 0; i < numWords; i++) {
+			sendBuffer[i] = i+1;
+			recvBuffer[i] = 0;
+		}
+
+		GET_TIME_VAL(0);
+
+		// Send the data
+		sent = fpga_send(fpga, chnl, sendBuffer, numWords, 0, 1, 25000);
+		printf("words sent: %d\n", sent);
+
+		GET_TIME_VAL(1);
+
+		if (sent != 0) {
+			// Recv the data
+			recvd = fpga_recv(fpga, chnl, recvBuffer, numWords, 25000);
+			printf("words recv: %d\n", recvd);
+		}
+
+		GET_TIME_VAL(2);
+
+		// Done with device
+        fpga_close(fpga);
+
+		// Display some data
+		for (i = 0; i < 20; i++) {
+			printf("recvBuffer[%d]: %d\n", i, recvBuffer[i]);
+		}
+
+		// Check the data
+		if (recvd != 0) {
+			for (i = 4; i < recvd; i++) {
+				if (recvBuffer[i] != sendBuffer[i]) {
+					printf("recvBuffer[%d]: %d, expected %d\n", i, recvBuffer[i], sendBuffer[i]);
+					break;
+				}
+			}
+
+			printf("send bw: %f MB/s %fms\n",
+				sent*4.0/1024/1024/((TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0))/1000.0),
+				(TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0)) );
+
+			printf("recv bw: %f MB/s %fms\n",
+				recvd*4.0/1024/1024/((TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1))/1000.0),
+				(TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1)) );
+		}
+	}
+
+	return 0;
+}

c_c++/windows/x64/sample_app/timer.h

@@ -0,0 +1,7 @@
+#include <windows.h>
+
+#define GET_TIME_INIT(num) LARGE_INTEGER _timers[num]; LARGE_INTEGER _freq; QueryPerformanceFrequency(&_freq)
+
+#define GET_TIME_VAL(num) QueryPerformanceCounter(&_timers[num])
+
+#define TIME_VAL_TO_MS(num) ((double)_timers[num].QuadPart*1000.0/_freq.QuadPart)

c_c++/windows/x86/README.txt

@@ -0,0 +1,14 @@
+To build the C/C++ library:
+
+windres.exe riffa.rc resource.o
+gcc.exe -c -o riffa.o riffa.c -D RIFFA_EXPORTS
+gcc.exe -o riffa.dll riffa.o resource.o -s -shared -Wl,--subsystem,windows,--out-implib,riffa.lib -luser32 -lsetupapi
+del riffa.lib
+gendef riffa.dll
+lib /def:riffa.def /machine:x86 /out:riffa.lib
+
+This will compile the resource file for the dll (metadata properties for the 
+.dll). This will also produce a .dll and .lib file. The .dll is the dynamic
+library. The .lib file is the import library. You will want to copy the .dll
+into say Windows\System32. You will want to use the .h file and the .lib files
+when compiling and linking your applications.

c_c++/windows/x86/riffa.c

@@ -0,0 +1,431 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.c
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#define INITGUID
+
+#include <windows.h>
+#include <setupapi.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "riffa_driver.h"
+#include "riffa.h"
+
+// The structure used to hold data transfer information
+typedef struct RIFFA_FPGA_CHNL_IO {
+	UINT32					Id;
+	UINT32					Chnl;
+	UINT32					Length;
+	UINT32					Offset;
+	UINT32					Last;
+	UINT64					Timeout;
+} RIFFA_FPGA_CHNL_IO, * PRIFFA_FPGA_CHNL_IO;
+
+// Represents the FPGA device
+struct fpga_t
+{
+	HANDLE dev;
+	int id;
+};
+
+HANDLE get_device(UINT32 index, BOOLEAN overlapped);
+DWORD fill_device_info(fpga_info_list * info);
+
+fpga_t * RIFFACALL fpga_open(int id) {
+	fpga_t * fpga;
+
+	// Allocate space for the fpga_dev
+	fpga = (fpga_t *)malloc(sizeof(fpga_t));
+	if (fpga == NULL)
+		return NULL;
+	fpga->id = id;
+
+	// Open the device handle.
+	fpga->dev = get_device(id, TRUE);
+	if (fpga->dev == INVALID_HANDLE_VALUE) {
+		free(fpga);
+		return NULL;
+	}
+
+	return fpga;
+}
+
+void RIFFACALL fpga_close(fpga_t * fpga) {
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return;
+	}
+
+	// Close the device handle.
+	CloseHandle(fpga->dev);
+	fpga->dev = NULL;
+
+	// Free the fpga_t struct
+	free(fpga);
+}
+
+int RIFFACALL fpga_send(fpga_t * fpga, int chnl, void * data, int len,
+	int destoff, int last, long long timeout) {
+	RIFFA_FPGA_CHNL_IO io;
+	OVERLAPPED overlapStruct = {0};
+	HANDLE evt;
+	BOOLEAN status;
+	ULONG wordsReturned;
+
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return 0;
+	}
+
+	// Initialize the RIFFA_FPGA_CHNL_IO struct
+	io.Id = fpga->id;
+	io.Chnl = chnl;
+	io.Length = len;
+	io.Offset = destoff;
+	io.Last = last;
+	io.Timeout = timeout;
+
+	// Create a thread specific event to wait on.
+	evt = CreateEvent(NULL, TRUE, TRUE, NULL);
+	overlapStruct.hEvent = evt;
+
+	// Call IOCTL with IOCTL_RIFFA_SEND
+	status = DeviceIoControl(fpga->dev, IOCTL_RIFFA_SEND, (LPVOID)&io,
+		sizeof(io), data, (len<<2), &wordsReturned, &overlapStruct);
+	if(!status) {
+		// Should be the IO Pending error
+		if(GetLastError() == ERROR_IO_PENDING) {
+			// Wait for the IOCTL to complete and get the return value
+			WaitForSingleObject(evt, INFINITE);
+			status = GetOverlappedResult(fpga->dev, &overlapStruct,
+				&wordsReturned, FALSE);
+			if(!status) {
+				if (GetLastError() == ERROR_OPERATION_ABORTED)
+					printf("Operation timed out or was aborted\n");
+				else
+					printf("Error in GetOverlappedResult: %d\n", GetLastError());
+			}
+		}
+		else {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+		}
+	}
+	return wordsReturned;
+}
+
+int RIFFACALL fpga_recv(fpga_t * fpga, int chnl, void * data, int len,
+	long long timeout) {
+	RIFFA_FPGA_CHNL_IO io;
+	OVERLAPPED overlapStruct = {0};
+	HANDLE evt;
+	BOOLEAN status;
+	ULONG wordsReturned;
+
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return 0;
+	}
+
+	// Initialize the RIFFA_FPGA_CHNL_IO struct
+	io.Id = fpga->id;
+	io.Chnl = chnl;
+	io.Length = len;
+	io.Timeout = timeout;
+
+	// Create a thread specific event to wait on.
+	evt = CreateEvent(NULL, TRUE, TRUE, NULL);
+	overlapStruct.hEvent = evt;
+
+	// Call IOCTL with IOCTL_RIFFA_RECV
+	status = DeviceIoControl(fpga->dev, IOCTL_RIFFA_RECV, (LPVOID)&io,
+		sizeof(io), data, (len<<2), &wordsReturned, &overlapStruct);
+	if(!status) {
+		// Should be the IO Pending error
+		if(GetLastError() == ERROR_IO_PENDING) {
+			// Wait for the IOCTL to complete and get the return value
+			WaitForSingleObject(evt, INFINITE);
+			status = GetOverlappedResult(fpga->dev, &overlapStruct,
+				&wordsReturned, FALSE);
+			if(!status) {
+				if (GetLastError() == ERROR_OPERATION_ABORTED)
+					printf("Operation timed out or was aborted\n");
+				else
+					printf("Error in GetOverlappedResult: %d\n", GetLastError());
+			}
+		}
+		else {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+		}
+	}
+	return wordsReturned;
+}
+
+void RIFFACALL fpga_reset(fpga_t * fpga) {
+	BOOLEAN status;
+	OVERLAPPED overlapStruct = {0};
+	ULONG wordsReturned;
+
+	// Validate the device handle
+	if (fpga->dev == NULL || fpga->dev == INVALID_HANDLE_VALUE) {
+		printf("Invalid fpga_t device handle\n");
+		return;
+	}
+
+	// Call IOCTL with IOCTL_RIFFA_RESET. Must use the overlapped struct as the
+	// device was opened with overlap support.
+	status = DeviceIoControl(fpga->dev, IOCTL_RIFFA_RESET, NULL, 0, NULL, 0,
+		&wordsReturned, &overlapStruct);
+	if(!status) {
+		// Should be the IO Pending error
+		if(GetLastError() == ERROR_IO_PENDING) {
+			// Wait for the IOCTL to complete and get the return value
+			status = GetOverlappedResult(fpga->dev, &overlapStruct,
+				&wordsReturned, TRUE);
+			if(!status)
+				printf("Error in GetOverlappedResult: %d\n", GetLastError());
+		}
+		else {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+		}
+	}
+}
+
+int RIFFACALL fpga_list(fpga_info_list * list) {
+	// Populate the fpga_info_list struct
+	list->num_fpgas = 0;
+	return (int)fill_device_info(list);
+}
+
+/**
+ * Returns a handle to the FPGA device specified by index. On failure, returns
+ * an INVALID_HANDLE_VALUE. If the value of overlapped is TRUE, the device
+ * handle will be opened with flag FILE_FLAG_OVERLAPPED to signal that future
+ * operations will use overlapped IO. If the value of overlapped is FALSE, the
+ * device handle will be opened with flag FILE_ATTRIBUTE_NORMAL and no
+ * overlapped IO can be used with the returned device handle.
+ */
+HANDLE get_device(UINT32 index, BOOLEAN overlapped) {
+    PSP_DEVICE_INTERFACE_DETAIL_DATA devIntfDetail;
+    SP_DEVICE_INTERFACE_DATA devIntfData;
+    SP_DEVINFO_DATA devInfoData;
+    SECURITY_ATTRIBUTES secAttr;
+    HDEVINFO devInfo;
+    BOOLEAN status = TRUE;
+    ULONG size;
+    HANDLE dev;
+    DWORD flags;
+
+    //  Retreive the device information for all RIFFA devices.
+    devInfo = SetupDiGetClassDevs(&GUID_RIFFA_INTERFACE, NULL, NULL,
+    	DIGCF_DEVICEINTERFACE | DIGCF_PRESENT);
+	if (devInfo == INVALID_HANDLE_VALUE) {
+        printf("SetupDiGetClassDevs failed, Error: %d\n", GetLastError());
+        return INVALID_HANDLE_VALUE;
+	}
+
+    //  Initialize the appropriate data structures for the SetupDi calls.
+    devIntfData.cbSize = sizeof(SP_DEVICE_INTERFACE_DATA);
+    devInfoData.cbSize = sizeof(SP_DEVINFO_DATA);
+
+    //  Get information for specific device.
+    status = SetupDiEnumDeviceInterfaces(devInfo, NULL, (LPGUID)&GUID_RIFFA_INTERFACE,
+    	index, &devIntfData);
+    if (!status) {
+        printf("SetupDiEnumDeviceInterfaces failed, Error: %d\n", GetLastError());
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+    // Determine the size required for the devIntfData
+    SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, NULL, 0, &size, NULL);
+    if (GetLastError() != ERROR_INSUFFICIENT_BUFFER) {
+        printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+    devIntfDetail = (PSP_DEVICE_INTERFACE_DETAIL_DATA)malloc(size);
+    if (!devIntfDetail) {
+        printf("Insufficient memory.\n");
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+    // Initialize structure and retrieve data.
+    devIntfDetail->cbSize = sizeof(SP_DEVICE_INTERFACE_DETAIL_DATA);
+    status = SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, devIntfDetail,
+    	size, NULL, &devInfoData);
+    if (!status) {
+        printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+        free(devIntfDetail);
+		SetupDiDestroyDeviceInfoList(devInfo);
+        return INVALID_HANDLE_VALUE;
+    }
+
+	// Prepare the security attributes for interitance.
+	secAttr.nLength = sizeof(SECURITY_ATTRIBUTES);
+	secAttr.bInheritHandle = TRUE;
+	secAttr.lpSecurityDescriptor = NULL;
+
+	// Get the device handle itself (finally!)
+	flags = (overlapped ? FILE_FLAG_OVERLAPPED : FILE_ATTRIBUTE_NORMAL);
+	flags = flags | FILE_FLAG_NO_BUFFERING;
+	dev = CreateFile(devIntfDetail->DevicePath, GENERIC_READ|GENERIC_WRITE,
+		FILE_SHARE_READ | FILE_SHARE_WRITE, &secAttr, OPEN_EXISTING, flags, NULL);
+	if (dev == INVALID_HANDLE_VALUE) {
+		printf("CreateFile failed.  Error:%d\n", GetLastError());
+        free(devIntfDetail);
+		SetupDiDestroyDeviceInfoList(devInfo);
+		return INVALID_HANDLE_VALUE;
+	}
+	free(devIntfDetail);
+	SetupDiDestroyDeviceInfoList(devInfo);
+
+    return dev;
+}
+
+/**
+ * Populates the specified fpga_info_list struct with FPGA information. Returns
+ * zero on success. On failure, returns an error code (positive value).
+ */
+DWORD fill_device_info(fpga_info_list * info) {
+    PSP_DEVICE_INTERFACE_DETAIL_DATA devIntfDetail;
+    SP_DEVICE_INTERFACE_DATA devIntfData;
+    SP_DEVINFO_DATA devInfoData;
+    HDEVINFO devInfo;
+    BOOLEAN status = TRUE;
+    ULONG size;
+    UINT32 i;
+    ULONG wordsReturned;
+    HANDLE dev;
+
+    //  Retreive the device information for all RIFFA devices.
+    devInfo = SetupDiGetClassDevs(&GUID_RIFFA_INTERFACE, NULL, NULL,
+    	DIGCF_DEVICEINTERFACE | DIGCF_PRESENT);
+	if (devInfo == INVALID_HANDLE_VALUE) {
+        printf("SetupDiGetClassDevs failed, Error: %d\n", GetLastError());
+        return GetLastError();
+	}
+
+    //  Initialize the appropriate data structures for the SetupDi calls.
+    devIntfData.cbSize = sizeof(SP_DEVICE_INTERFACE_DATA);
+    devInfoData.cbSize = sizeof(SP_DEVINFO_DATA);
+
+    //  Loop through the device list.
+    i = 0;
+    while (SetupDiEnumDeviceInterfaces(devInfo, NULL, (LPGUID)&GUID_RIFFA_INTERFACE,
+    	i, &devIntfData)) {
+        // Determine the size required for the devIntfData
+        SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, NULL, 0, &size, NULL);
+        if (GetLastError() != ERROR_INSUFFICIENT_BUFFER) {
+            printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+			SetupDiDestroyDeviceInfoList(devInfo);
+            return GetLastError();
+        }
+
+		// Create the SP_DEVICE_INTERFACE_DETAIL_DATA
+        devIntfDetail = (PSP_DEVICE_INTERFACE_DETAIL_DATA)malloc(size);
+        if (!devIntfDetail) {
+            printf("Insufficient memory.\n");
+			SetupDiDestroyDeviceInfoList(devInfo);
+            return ERROR_NOT_ENOUGH_MEMORY;
+        }
+
+		// Initialize structure and retrieve data.
+		devIntfDetail->cbSize = sizeof(SP_DEVICE_INTERFACE_DETAIL_DATA);
+		status = SetupDiGetDeviceInterfaceDetail(devInfo, &devIntfData, devIntfDetail,
+			size, NULL, &devInfoData);
+		if (!status) {
+			printf("SetupDiGetDeviceInterfaceDetail failed, Error: %d\n", GetLastError());
+	        free(devIntfDetail);
+			SetupDiDestroyDeviceInfoList(devInfo);
+			return GetLastError();
+		}
+
+		// Get the device handle itself (no overlap)
+		dev = CreateFile(devIntfDetail->DevicePath, GENERIC_READ|GENERIC_WRITE,
+			FILE_SHARE_READ | FILE_SHARE_WRITE, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL);
+		if (dev == INVALID_HANDLE_VALUE) {
+			printf("CreateFile failed.  Error:%d\n", GetLastError());
+	        free(devIntfDetail);
+			SetupDiDestroyDeviceInfoList(devInfo);
+			return GetLastError();
+		}
+
+		// Call IOCTL with IOCTL_RIFFA_LIST
+		status = DeviceIoControl(dev, IOCTL_RIFFA_LIST, (LPVOID)&i, sizeof(i),
+			(LPVOID)info, sizeof(*info), &wordsReturned, NULL);
+		if (!status) {
+			printf("Error in DeviceIoControl: %d\n", GetLastError());
+	        CloseHandle(dev);
+	        free(devIntfDetail);
+			SetupDiDestroyDeviceInfoList(devInfo);
+			return GetLastError();
+		}
+		info->num_fpgas = info->num_fpgas + 1;
+
+		// Done with the device
+		CloseHandle(dev);
+		free(devIntfDetail);
+
+        // Cycle through the available devices.
+        i++;
+    }
+
+	// Done with the DeviceInfo
+	SetupDiDestroyDeviceInfoList(devInfo);
+
+	return 0;
+}
+
+
+

c_c++/windows/x86/riffa.def

@@ -0,0 +1,13 @@
+;
+; Definition file of riffa.dll
+; Automatic generated by gendef
+; written by Kai Tietz 2008
+;
+LIBRARY "riffa.dll"
+EXPORTS
+fpga_close
+fpga_list
+fpga_open
+fpga_recv
+fpga_reset
+fpga_send

c_c++/windows/x86/riffa.h

@@ -0,0 +1,150 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.h
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#ifndef RIFFA_H
+#define RIFFA_H
+
+// Must RIFFA_EXPORTS *only* when building the DLL.
+#ifdef RIFFA_EXPORTS
+  #define RIFFAAPI __declspec(dllexport)
+#else
+  #define RIFFAAPI __declspec(dllimport)
+#endif
+
+// Define calling convention in one place, for convenience.
+#define RIFFACALL __cdecl
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Maximum number of RIFFA FPGAs
+#define RIFFA_MAX_NUM_FPGAS (5)
+
+// Holds FPGA information for installed RIFFA FPGAs
+struct fpga_info_list
+{
+	int num_fpgas;
+	int id[RIFFA_MAX_NUM_FPGAS];
+	int num_chnls[RIFFA_MAX_NUM_FPGAS];
+	char name[RIFFA_MAX_NUM_FPGAS][16];
+	int vendor_id[RIFFA_MAX_NUM_FPGAS];
+	int device_id[RIFFA_MAX_NUM_FPGAS];
+};
+typedef struct fpga_info_list fpga_info_list;
+
+// Represents the FPGA device
+struct fpga_t;
+typedef struct fpga_t fpga_t;
+
+/**
+ * Populates the fpga_info_list pointer with all FPGAs registered in the system.
+ * Returns 0 on success, non-zero on error.
+ */
+RIFFAAPI int RIFFACALL fpga_list(fpga_info_list * list);
+
+/**
+ * Initializes the FPGA specified by id. On success, returns a pointer to a
+ * fpga_t struct. On error, returns NULL. Each FPGA must be opened before any
+ * channels can be accessed. Once opened, any number of threads can use the
+ * fpga_t struct.
+ */
+RIFFAAPI fpga_t * RIFFACALL fpga_open(int id);
+
+/**
+ * Cleans up memory/resources for the FPGA specified by the fd descriptor.
+ */
+RIFFAAPI void RIFFACALL fpga_close(fpga_t * fpga);
+
+/**
+ * Sends len words (4 byte words) from data to FPGA channel chnl using the
+ * fpga_t struct. The FPGA channel will be sent len, destoff, and last. If last
+ * is 1, the channel should interpret the end of this send as the end of a
+ * transaction. If last is 0, the channel should wait for additional sends
+ * before the end of the transaction. If timeout is non-zero, this call will
+ * send data and wait up to timeout ms for the FPGA to respond (between
+ * packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads sending on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words sent.
+ */
+RIFFAAPI int RIFFACALL fpga_send(fpga_t * fpga, int chnl, void * data, int len,
+	int destoff, int last, long long timeout);
+
+/**
+ * Receives data from the FPGA channel chnl to the data pointer, using the
+ * fpga_t struct. The FPGA channel can send any amount of data, so the data
+ * array should be large enough to accommodate. The len parameter specifies the
+ * actual size of the data buffer in words (4 byte words). The FPGA channel will
+ * specify an offset which will determine where in the data array the data will
+ * start being written. If the amount of data (plus offset) exceed the size of
+ * the data array (len), then that data will be discarded. If timeout is
+ * non-zero, this call will wait up to timeout ms for the FPGA to respond
+ * (between packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads receiving on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words received to the data array.
+ */
+RIFFAAPI int RIFFACALL fpga_recv(fpga_t * fpga, int chnl, void * data, int len,
+	long long timeout);
+
+/**
+ * Resets the state of the FPGA and all transfers across all channels. This is
+ * meant to be used as an alternative to rebooting if an error occurs while
+ * sending/receiving. Calling this function while other threads are sending or
+ * receiving will result in unexpected behavior.
+ */
+RIFFAAPI void RIFFACALL fpga_reset(fpga_t * fpga);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

c_c++/windows/x86/riffa.rc

@@ -0,0 +1,83 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.rc
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+1 VERSIONINFO
+ FILEVERSION 1,0,0,0
+ PRODUCTVERSION 2,0,0,0
+ FILEFLAGSMASK 0x17L
+#ifdef _DEBUG
+ FILEFLAGS 0x1L
+#else
+ FILEFLAGS 0x0L
+#endif
+ FILEOS 0x4L
+ FILETYPE 0x1L
+ FILESUBTYPE 0x0L
+BEGIN
+    BLOCK "StringFileInfo"
+    BEGIN
+        BLOCK "040904b0"
+        BEGIN
+            VALUE "Comments", "RIFFA 64 bit Windows Library"
+            VALUE "CompanyName", "University of California, San Diego"
+            VALUE "FileDescription", "User 32 bit library for RIFFA."
+            VALUE "FileVersion", "1, 0, 0, 0"
+            VALUE "InternalName", "RIFFA"
+            VALUE "LegalCopyright", "Copyright <20> 2011 The Regents of the University of California. All Rights Reserved."
+            VALUE "OriginalFilename", "riffa.dll"
+            VALUE "ProductName", "RIFFA Library"
+            VALUE "ProductVersion", "2, 0, 0, 0"
+        END
+    END
+    BLOCK "VarFileInfo"
+    BEGIN
+        VALUE "Translation", 0x409, 1200
+    END
+END

c_c++/windows/x86/riffa_driver.h

@@ -0,0 +1,23 @@
+//
+// The following value is arbitrarily chosen from the space defined
+// by Microsoft as being "for non-Microsoft use"
+//
+//
+// {40d49fb9-6085-4e1d-8753-822be944d7bb}
+DEFINE_GUID (GUID_RIFFA_INTERFACE,
+   0x40d49fb9, 0x6085, 0x4e1d, 0x87, 0x53, 0x82, 0x2b, 0xe9, 0x44, 0xd7, 0xbb);
+
+// The IOCTL function codes from 0x800 to 0xFFF are for customer use.
+#define CTL_CODE( DeviceType, Function, Method, Access ) (                 \
+    ((DeviceType) << 16) | ((Access) << 14) | ((Function) << 2) | (Method) \
+)
+
+#define IOCTL_RIFFA_SEND \
+    CTL_CODE(0x00000022, 0x900, 2, 0)
+#define IOCTL_RIFFA_RECV \
+    CTL_CODE(0x00000022, 0x901, 2, 0)
+#define IOCTL_RIFFA_LIST \
+    CTL_CODE(0x00000022, 0x902, 2 ,0)
+#define IOCTL_RIFFA_RESET \
+    CTL_CODE(0x00000022, 0x903, 2, 0)
+

c_c++/windows/x86/sample_app/README.txt

@@ -0,0 +1,10 @@
+The testutil example application works with the Verilog chnl_tester module
+which receives data and then sends data back to the workstation. 
+
+To compile the example application:
+
+gcc.exe -o testutil.exe testutil.c -L. -lriffa
+
+The riffa.lib import library must be in the directory specified by the -L 
+parameter (in this example, the current directory). The riffa.h header must be
+in the same directory as testutil.c.

c_c++/windows/x86/sample_app/riffa.h

@@ -0,0 +1,150 @@
+/*******************************************************************************
+ * This software is Copyright © 2012 The Regents of the University of
+ * California. All Rights Reserved.
+ *
+ * Permission to copy, modify, and distribute this software and its
+ * documentation for educational, research and non-profit purposes, without fee,
+ * and without a written agreement is hereby granted, provided that the above
+ * copyright notice, this paragraph and the following three paragraphs appear in
+ * all copies.
+ *
+ * Permission to make commercial use of this software may be obtained by
+ * contacting:
+ * Technology Transfer Office
+ * 9500 Gilman Drive, Mail Code 0910
+ * University of California
+ * La Jolla, CA 92093-0910
+ * (858) 534-5815
+ * invent@ucsd.edu
+ *
+ * This software program and documentation are copyrighted by The Regents of the
+ * University of California. The software program and documentation are supplied
+ * "as is", without any accompanying services from The Regents. The Regents does
+ * not warrant that the operation of the program will be uninterrupted or error-
+ * free. The end-user understands that the program was developed for research
+ * purposes and is advised not to rely exclusively on the program for any
+ * reason.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+ * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
+ * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+ * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+/*
+ * Filename: riffa.h
+ * Version: 2.0
+ * Description: Windows PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#ifndef RIFFA_H
+#define RIFFA_H
+
+// Must RIFFA_EXPORTS *only* when building the DLL.
+#ifdef RIFFA_EXPORTS
+  #define RIFFAAPI __declspec(dllexport)
+#else
+  #define RIFFAAPI __declspec(dllimport)
+#endif
+
+// Define calling convention in one place, for convenience.
+#define RIFFACALL __cdecl
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Maximum number of RIFFA FPGAs
+#define RIFFA_MAX_NUM_FPGAS (5)
+
+// Holds FPGA information for installed RIFFA FPGAs
+struct fpga_info_list
+{
+	int num_fpgas;
+	int id[RIFFA_MAX_NUM_FPGAS];
+	int num_chnls[RIFFA_MAX_NUM_FPGAS];
+	char name[RIFFA_MAX_NUM_FPGAS][16];
+	int vendor_id[RIFFA_MAX_NUM_FPGAS];
+	int device_id[RIFFA_MAX_NUM_FPGAS];
+};
+typedef struct fpga_info_list fpga_info_list;
+
+// Represents the FPGA device
+struct fpga_t;
+typedef struct fpga_t fpga_t;
+
+/**
+ * Populates the fpga_info_list pointer with all FPGAs registered in the system.
+ * Returns 0 on success, non-zero on error.
+ */
+RIFFAAPI int RIFFACALL fpga_list(fpga_info_list * list);
+
+/**
+ * Initializes the FPGA specified by id. On success, returns a pointer to a
+ * fpga_t struct. On error, returns NULL. Each FPGA must be opened before any
+ * channels can be accessed. Once opened, any number of threads can use the
+ * fpga_t struct.
+ */
+RIFFAAPI fpga_t * RIFFACALL fpga_open(int id);
+
+/**
+ * Cleans up memory/resources for the FPGA specified by the fd descriptor.
+ */
+RIFFAAPI void RIFFACALL fpga_close(fpga_t * fpga);
+
+/**
+ * Sends len words (4 byte words) from data to FPGA channel chnl using the
+ * fpga_t struct. The FPGA channel will be sent len, destoff, and last. If last
+ * is 1, the channel should interpret the end of this send as the end of a
+ * transaction. If last is 0, the channel should wait for additional sends
+ * before the end of the transaction. If timeout is non-zero, this call will
+ * send data and wait up to timeout ms for the FPGA to respond (between
+ * packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads sending on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words sent.
+ */
+RIFFAAPI int RIFFACALL fpga_send(fpga_t * fpga, int chnl, void * data, int len,
+	int destoff, int last, long long timeout);
+
+/**
+ * Receives data from the FPGA channel chnl to the data pointer, using the
+ * fpga_t struct. The FPGA channel can send any amount of data, so the data
+ * array should be large enough to accommodate. The len parameter specifies the
+ * actual size of the data buffer in words (4 byte words). The FPGA channel will
+ * specify an offset which will determine where in the data array the data will
+ * start being written. If the amount of data (plus offset) exceed the size of
+ * the data array (len), then that data will be discarded. If timeout is
+ * non-zero, this call will wait up to timeout ms for the FPGA to respond
+ * (between packets) before timing out. If timeout is zero, this call may block
+ * indefinitely. Multiple threads receiving on the same channel may result in
+ * corrupt data or error. This function is thread safe across channels.
+ * Returns the number of words received to the data array.
+ */
+RIFFAAPI int RIFFACALL fpga_recv(fpga_t * fpga, int chnl, void * data, int len,
+	long long timeout);
+
+/**
+ * Resets the state of the FPGA and all transfers across all channels. This is
+ * meant to be used as an alternative to rebooting if an error occurs while
+ * sending/receiving. Calling this function while other threads are sending or
+ * receiving will result in unexpected behavior.
+ */
+RIFFAAPI void RIFFACALL fpga_reset(fpga_t * fpga);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

c_c++/windows/x86/sample_app/testutil.c

@@ -0,0 +1,146 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include <windows.h>
+#include "timer.h"
+#include "riffa.h"
+
+int main(int argc, char** argv) {
+	fpga_t * fpga;
+	fpga_info_list info;
+	int option;
+	int i;
+	int id;
+	int chnl;
+	size_t numWords;
+	int sent;
+	int recvd;
+	unsigned int * sendBuffer;
+	unsigned int * recvBuffer;
+	GET_TIME_INIT(3);
+
+	if (argc < 2) {
+		printf("Usage: %s <option>\n", argv[0]);
+		return -1;
+	}
+
+	option = atoi(argv[1]);
+
+	if (option == 0) {	// List FPGA info
+		// Populate the fpga_info_list struct
+		if (fpga_list(&info) != 0) {
+			printf("Error populating fpga_info_list\n");
+			return -1;
+		}
+		printf("Number of devices: %d\n", info.num_fpgas);
+		for (i = 0; i < info.num_fpgas; i++) {
+			printf("%d: id:%d\n", i, info.id[i]);
+			printf("%d: num_chnls:%d\n", i, info.num_chnls[i]);
+			printf("%d: name:%s\n", i, info.name[i]);
+			printf("%d: vendor id:%04X\n", i, info.vendor_id[i]);
+			printf("%d: device id:%04X\n", i, info.device_id[i]);
+		}
+	}
+	else if (option == 1) { // Reset FPGA
+		if (argc < 3) {
+			printf("Usage: %s %d <fpga id>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Reset
+		fpga_reset(fpga);
+
+		// Done with device
+        fpga_close(fpga);
+	}
+	else if (option == 2) { // Send data, receive data
+		if (argc < 5) {
+			printf("Usage: %s %d <fpga id> <chnl> <num words to transfer>\n", argv[0], option);
+			return -1;
+		}
+
+		id = atoi(argv[2]);
+		chnl = atoi(argv[3]);
+		numWords = atoi(argv[4]);
+
+		// Get the device with id
+		fpga = fpga_open(id);
+		if (fpga == NULL) {
+			printf("Could not get FPGA %d\n", id);
+			return -1;
+	    }
+
+		// Malloc the arrays
+		sendBuffer = (unsigned int *)malloc(numWords<<2);
+		if (sendBuffer == NULL) {
+			printf("Could not malloc memory for sendBuffer\n");
+			fpga_close(fpga);
+			return -1;
+	    }
+		recvBuffer = (unsigned int *)malloc(numWords<<2);
+		if (recvBuffer == NULL) {
+			printf("Could not malloc memory for recvBuffer\n");
+			free(sendBuffer);
+			fpga_close(fpga);
+			return -1;
+	    }
+
+		// Initialize the data
+		for (i = 0; i < numWords; i++) {
+			sendBuffer[i] = i+1;
+			recvBuffer[i] = 0;
+		}
+
+		GET_TIME_VAL(0);
+
+		// Send the data
+		sent = fpga_send(fpga, chnl, sendBuffer, numWords, 0, 1, 25000);
+		printf("words sent: %d\n", sent);
+
+		GET_TIME_VAL(1);
+
+		if (sent != 0) {
+			// Recv the data
+			recvd = fpga_recv(fpga, chnl, recvBuffer, numWords, 25000);
+			printf("words recv: %d\n", recvd);
+		}
+
+		GET_TIME_VAL(2);
+
+		// Done with device
+        fpga_close(fpga);
+
+		// Display some data
+		for (i = 0; i < 20; i++) {
+			printf("recvBuffer[%d]: %d\n", i, recvBuffer[i]);
+		}
+
+		// Check the data
+		if (recvd != 0) {
+			for (i = 4; i < recvd; i++) {
+				if (recvBuffer[i] != sendBuffer[i]) {
+					printf("recvBuffer[%d]: %d, expected %d\n", i, recvBuffer[i], sendBuffer[i]);
+					break;
+				}
+			}
+
+			printf("send bw: %f MB/s %fms\n",
+				sent*4.0/1024/1024/((TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0))/1000.0),
+				(TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0)) );
+
+			printf("recv bw: %f MB/s %fms\n",
+				recvd*4.0/1024/1024/((TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1))/1000.0),
+				(TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1)) );
+		}
+	}
+
+	return 0;
+}

c_c++/windows/x86/sample_app/timer.h

@@ -0,0 +1,7 @@
+#include <windows.h>
+
+#define GET_TIME_INIT(num) LARGE_INTEGER _timers[num]; LARGE_INTEGER _freq; QueryPerformanceFrequency(&_freq)
+
+#define GET_TIME_VAL(num) QueryPerformanceCounter(&_timers[num])
+
+#define TIME_VAL_TO_MS(num) ((double)_timers[num].QuadPart*1000.0/_freq.QuadPart)

driver/linux/Makefile

@@ -0,0 +1,155 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+
+# Filename: Makefile
+# Version: 2.0
+# Description: Makefile for Linux PCIe device driver for RIFFA.
+# Author: Matthew Jacobsen
+# History: @mattj: Initial release. Version 2.0.
+
+# You must specify the following variables. You can leave the defaults if you
+# like, but make sure they will work in your system.
+# The VENDOR_ID _must_ match what is configured on your FPGA's PCIe endpoint 
+# header. Xilinx has a VENDOR_ID = 10EE.
+NAME := riffa
+VENDOR_ID0 := 10EE
+VENDOR_ID1 := 1172
+MAJNUM := 100
+
+# Build variables
+KVER := $(shell uname -r)
+KDIR := /lib/modules/`uname -r`/build
+RHR := /etc/redhat-release
+LIB_SRCS := riffa.c
+LIB_OBJS := $(patsubst %.c,%.o,$(LIB_SRCS))
+LIB_HDR := riffa.h
+LIB_VER_MAJ := 1
+LIB_VER_MIN := 0
+LIB_VER := $(LIB_VER_MAJ).$(LIB_VER_MIN)
+DRVR_HDR := riffa_driver.h
+DBUGVAL := DBUG
+
+obj-m += $(NAME).o
+$(NAME)-y := riffa_driver.o circ_queue.o
+
+# Helper functions
+define assert
+  $(if $1,,$(error Assertion failed: $2))
+endef
+define assert-not-null
+  $(call assert,$($1),The variable "$1" is null, please specify it.)
+endef
+define assert-variables
+	$(call assert-not-null,NAME)
+	$(call assert-not-null,MAJNUM)
+	$(call assert-not-null,VENDOR_ID0)
+	$(call assert-not-null,VENDOR_ID1)
+	@printf "Compiling driver for kernel: %s with the following values\n" $(KVER)
+	@printf "     NAME: '%s'\n" $(NAME)
+	@printf "   MAJNUM: '%s'\n" $(MAJNUM)
+	@printf "VENDOR_ID0: '%s'\n" $(VENDOR_ID0)
+	@printf "VENDOR_ID1: '%s'\n" $(VENDOR_ID1)
+	@printf "\n"
+endef
+
+all: builddvr
+debug: CC += -DDEBUG -g
+debug: DBUGVAL = DEBUG
+debug: builddvr
+builddvr: $(NAME).ko $(NAME).so.$(LIB_VER)
+
+$(NAME).ko: *.c *.h
+	$(call assert-variables)
+	sed -i 's/#define MAJOR_NUM [^\n]*/#define MAJOR_NUM $(MAJNUM)/g' $(DRVR_HDR)
+	sed -i 's/#define DEVICE_NAME [^\n]*/#define DEVICE_NAME "$(NAME)"/g' $(DRVR_HDR)
+	sed -i 's/#define VENDOR_ID0 [^\n]*/#define VENDOR_ID0 0x$(VENDOR_ID0)/g' $(DRVR_HDR)
+	sed -i 's/#define VENDOR_ID1 [^\n]*/#define VENDOR_ID1 0x$(VENDOR_ID1)/g' $(DRVR_HDR)
+	sed -i 's/#define DEBUG [^\n]*/#define DBUG 1/g' $(DRVR_HDR)
+	sed -i 's/#define DBUG [^\n]*/#define $(DBUGVAL) 1/g' $(DRVR_HDR)
+	make -C $(KDIR) SUBDIRS=`pwd` modules
+	rm -rf $(LIB_OBJS)
+
+$(NAME).so.$(LIB_VER): $(LIB_OBJS)
+	$(CC) -shared -Wl,-soname,lib$(NAME).so.$(LIB_VER_MAJ) -o lib$@ $^
+
+$(LIB_OBJS): $(LIB_SRCS)
+	$(CC) -g -Wall -fPIC -c $^
+
+load: $(NAME).ko
+	insmod $(NAME).ko
+	
+unload:
+	rmmod $(NAME)
+
+clean:
+	rm -Rf *.ko *.cmd *.o *.so *.so.* .*.cmd Module.symvers Module.markers modules.order *.mod.c .tmp_versions
+
+setup:
+	if [ -f "$(RHR)" ]; then yum install kernel-devel-`uname -r`;\
+	else apt-get install linux-headers-`uname -r`; fi
+
+install: $(NAME).so.$(LIB_VER) $(NAME).ko 
+	mkdir -p /lib/modules/$(KVER)/kernel/drivers/$(NAME)
+	cp $(NAME).ko /lib/modules/$(KVER)/kernel/drivers/$(NAME)/
+	if [ -f "$(RHR)" ]; then\
+		printf "%b\n" "#!/bin/sh\nexec /sbin/modprobe $(NAME) >/dev/null 2>&1" > /etc/sysconfig/modules/$(NAME).modules;\
+		chmod 755 /etc/sysconfig/modules/$(NAME).modules;\
+	else\
+		if ! grep -Fxq "$(NAME)" /etc/modules; then echo "$(NAME)" >> /etc/modules; fi;\
+	fi
+	printf "%b\n" "KERNEL==\"$(NAME)\", MODE=\"777\", GROUP=\"root\"" > /etc/udev/rules.d/99-$(NAME).rules
+	printf "/usr/local/lib\n" > $(NAME).conf
+	mv $(NAME).conf /etc/ld.so.conf.d/
+	cp $(DRVR_HDR) /usr/local/include/
+	cp $(LIB_HDR) /usr/local/include/
+	mv lib$(NAME).so.1.0 /usr/local/lib
+	ln -sf /usr/local/lib/lib$(NAME).so.$(LIB_VER) /usr/local/lib/lib$(NAME).so.$(LIB_VER_MAJ)
+	ln -sf /usr/local/lib/lib$(NAME).so.$(LIB_VER) /usr/local/lib/lib$(NAME).so
+	ldconfig
+	depmod
+
+uninstall: 
+	rm -f /usr/local/lib/lib$(NAME).so*
+	rm -f /usr/local/include/$(LIB_HDR)
+	rm -f /usr/local/include/$(DRVR_HDR)
+	rm -f /etc/ld.so.conf.d/$(NAME).conf
+	rm -rf /lib/modules/$(KVER)/kernel/drivers/$(NAME)
+	rm -f /etc/udev/rules.d/99-$(NAME).rules
+	if [ -f "$(RHR)" ]; then rm -f /etc/sysconfig/modules/$(NAME).modules;\
+	else cp /etc/modules ./etc.modules.bak; sed -i '/$(NAME)/d' /etc/modules; fi
+	ldconfig
+	depmod
+
+

driver/linux/README.txt

@@ -0,0 +1,38 @@
+You must build the Linux driver against the version of the Linux kernel you have
+installed. This will require the Linux kernel headers. After you've built the
+driver you can install it in your system so that it loads at boot time. If the
+driver is installed and there is a RIFFA 2.0.1 capable FPGA installed as well, 
+the driver will detect it. Output in the system log will provide additional 
+information. This makefile will also build and install the C/C++ native library.
+
+Ensure you have the kernel headers installed:
+
+sudo make setup
+
+This will attempt to install the kernel headers using your system's package
+manager. You can skip this step if you've already installed the kernel headers.
+
+Compile the driver and C/C++ library:
+
+make
+
+or 
+
+make debug
+
+Using make debug will compile in code to output debug messages to the system log
+at runtime. These messages are useful when developing your design. However they
+pollute your system log and incur some overhead. So you may want to install the
+non-debug version after you've completed development.
+
+Install the driver and library:
+
+sudo make install
+
+The system will be configured to load the driver at boot time. The C/C++ library
+will be installed in the default library path. The header files will be placed
+in the default include path. You will want to reboot after you've installed for
+the driver to be (re)loaded.
+
+When compiling an application you should only need to include the <riffa.h> 
+header file and link with -lriffa.

driver/linux/circ_queue.c

@@ -0,0 +1,188 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+/*
+ * Filename: circ_queue.c
+ * Version: 1.0
+ * Description: A lock-free single-producer circular queue implementation 
+ *   modeled after the more elaborate C++ version from Faustino Frechilla at:
+ *   http://www.codeproject.com/Articles/153898/Yet-another-implementation-of-a-lock-free-circular
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 1.0.
+ */
+
+#include <linux/slab.h>
+#include "circ_queue.h"
+
+circ_queue * init_circ_queue(int len)
+{
+	int i;
+	circ_queue * q;
+
+	q = kzalloc(sizeof(circ_queue), GFP_KERNEL);
+	if (q == NULL) {
+		printk(KERN_ERR "Not enough memory to allocate circ_queue");
+		return NULL;
+	}
+
+	atomic_set(&q->writeIndex, 0);
+	atomic_set(&q->readIndex, 0);
+	q->len = len;
+
+	q->vals = (unsigned int**) kzalloc(len*sizeof(unsigned int*), GFP_KERNEL);  
+	if (q->vals == NULL) {
+		printk(KERN_ERR "Not enough memory to allocate circ_queue array");
+		return NULL;
+	}
+	for (i = 0; i < len; i++) {
+		q->vals[i] = (unsigned int*) kzalloc(2*sizeof(unsigned int), GFP_KERNEL);
+		if (q->vals[i] == NULL) {
+			printk(KERN_ERR "Not enough memory to allocate circ_queue array position");
+			return NULL;
+		}
+	}
+
+	return q;
+}
+
+/**
+ * Internal function to help count. Returns the queue size normalized position.
+ */
+unsigned int queue_count_to_index(unsigned int count, unsigned int len)
+{
+	return (count % len);
+}
+
+int push_circ_queue(circ_queue * q, unsigned int val1, unsigned int val2)
+{
+	unsigned int currReadIndex;
+	unsigned int currWriteIndex;
+
+	currWriteIndex = atomic_read(&q->writeIndex);
+	currReadIndex  = atomic_read(&q->readIndex);
+	if (queue_count_to_index(currWriteIndex+1, q->len) == queue_count_to_index(currReadIndex, q->len)) {
+		// The queue is full
+		return 1;
+	}
+
+	// Save the data into the queue
+	q->vals[queue_count_to_index(currWriteIndex, q->len)][0] = val1;
+	q->vals[queue_count_to_index(currWriteIndex, q->len)][1] = val2;
+	// Increment atomically write index. Now a consumer thread can read
+	// the piece of data that was just stored.
+	atomic_inc(&q->writeIndex);
+
+	return 0;
+}
+
+int pop_circ_queue(circ_queue * q, unsigned int * val1, unsigned int * val2)
+{
+	unsigned int currReadIndex;
+	unsigned int currMaxReadIndex;
+
+	do
+	{
+		currReadIndex = atomic_read(&q->readIndex);
+		currMaxReadIndex = atomic_read(&q->writeIndex);
+		if (queue_count_to_index(currReadIndex, q->len) == queue_count_to_index(currMaxReadIndex, q->len)) {
+			// The queue is empty or a producer thread has allocate space in the queue
+			// but is waiting to commit the data into it
+			return 1;
+		}
+
+		// Retrieve the data from the queue
+		*val1 = q->vals[queue_count_to_index(currReadIndex, q->len)][0];
+		*val2 = q->vals[queue_count_to_index(currReadIndex, q->len)][1];
+
+		// Try to perfrom now the CAS operation on the read index. If we succeed
+		// label & val already contain what q->readIndex pointed to before we 
+		// increased it.
+		if (atomic_cmpxchg(&q->readIndex, currReadIndex, currReadIndex+1) == currReadIndex) {
+			// The lable & val were retrieved from the queue. Note that the
+			// data inside the label or value arrays are not deleted.
+			return 0;
+		}
+
+		// Failed to retrieve the elements off the queue. Someone else must
+		// have read the element stored at countToIndex(currReadIndex)
+		// before we could perform the CAS operation.       
+	} while(1); // keep looping to try again!
+
+	return 1;
+}
+
+int circ_queue_empty(circ_queue * q)
+{
+	unsigned int currReadIndex;
+	unsigned int currMaxReadIndex;
+
+	currReadIndex = atomic_read(&q->readIndex);
+	currMaxReadIndex = atomic_read(&q->writeIndex);
+	if (queue_count_to_index(currReadIndex, q->len) == queue_count_to_index(currMaxReadIndex, q->len)) {
+		// The queue is empty or a producer thread has allocate space in the queue
+		// but is waiting to commit the data into it
+		return 1;
+	}
+	return 0;
+}
+
+int circ_queue_full(circ_queue * q)
+{
+	unsigned int currReadIndex;
+	unsigned int currWriteIndex;
+
+	currWriteIndex = atomic_read(&q->writeIndex);
+	currReadIndex  = atomic_read(&q->readIndex);
+	if (queue_count_to_index(currWriteIndex+1, q->len) == queue_count_to_index(currReadIndex, q->len)) {
+		// The queue is full
+		return 1;
+	}
+	return 0;
+}
+
+void free_circ_queue(circ_queue * q)
+{
+	int i;
+
+	if (q == NULL)
+		return;
+
+	for (i = 0; i < q->len; i++) {  
+		kfree(q->vals[i]);  
+	}
+	kfree(q->vals);
+	kfree(q);
+}
+

driver/linux/circ_queue.h

@@ -0,0 +1,96 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+/*
+ * Filename: circ_queue.h
+ * Version: 1.0
+ * Description: A lock-free single-producer circular queue implementation 
+ *   modeled after the more elaborate C++ version from Faustino Frechilla at:
+ *   http://www.codeproject.com/Articles/153898/Yet-another-implementation-of-a-lock-free-circular
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 1.0.
+ */
+#ifndef CIRC_QUEUE_H
+#define CIRC_QUEUE_H
+
+#include <asm/atomic.h>
+
+/* Struct for the circular queue. */
+struct circ_queue {
+	atomic_t writeIndex;
+	atomic_t readIndex;
+	unsigned int ** vals;
+	unsigned int len;
+};
+typedef struct circ_queue circ_queue;
+
+/**
+ * Initializes a circ_queue with depth/length len. Returns non-NULL on success, 
+ * NULL if there was a problem creating the queue.
+ */
+circ_queue * init_circ_queue(int len);
+
+/**
+ * Pushes a pair of unsigned int values into the specified queue at the head. 
+ * Returns 0 on success, non-zero if there is no more space in the queue.
+ */
+int push_circ_queue(circ_queue * q, unsigned int val1, unsigned int val2);
+
+/**
+ * Pops a pair of unsigned int values out of the specified queue from the tail.
+ * Returns 0 on success, non-zero if the queue is empty.
+ */
+int pop_circ_queue(circ_queue * q, unsigned int * val1, unsigned int * val2);
+
+/**
+ * Returns 1 if the circ_queue is empty, 0 otherwise. Note, this is not a 
+ * synchronized function. If another thread is accessing this circ_queue, the
+ * return value may not be valid.
+ */
+int circ_queue_empty(circ_queue * q);
+
+/**
+ * Returns 1 if the circ_queue is full, 0 otherwise. Note, this is not a 
+ * synchronized function. If another thread is accessing this circ_queue, the
+ * return value may not be valid.
+ */
+int circ_queue_full(circ_queue * q);
+
+/**
+ * Frees the resources associated with the specified circ_queue.
+ */
+void free_circ_queue(circ_queue * q);
+
+#endif

driver/linux/riffa.c

@@ -0,0 +1,131 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+/*
+ * Filename: riffa.c
+ * Version: 2.0
+ * Description: Linux PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include "riffa.h"
+
+struct fpga_t
+{
+	int fd;
+	int id;
+};
+
+fpga_t * fpga_open(int id) 
+{
+	fpga_t * fpga;
+
+	// Allocate space for the fpga_dev
+	fpga = (fpga_t *)malloc(sizeof(fpga_t));
+	if (fpga == NULL)
+		return NULL;
+	fpga->id = id;	
+
+	// Open the device file.
+	fpga->fd = open("/dev/" DEVICE_NAME, O_RDWR | O_SYNC);
+	if (fpga->fd < 0) {
+		free(fpga); 
+		return NULL;
+	}
+	
+	return fpga;
+}
+
+void fpga_close(fpga_t * fpga) 
+{
+	// Close the device file.
+	close(fpga->fd);
+	free(fpga);
+}
+
+int fpga_send(fpga_t * fpga, int chnl, void * data, int len, int destoff, 
+	int last, long long timeout)
+{
+	fpga_chnl_io io;
+
+	io.id = fpga->id;
+	io.chnl = chnl;
+	io.len = len;
+	io.offset = destoff;
+	io.last = last;
+	io.timeout = timeout;
+	io.data = (char *)data;
+
+	return ioctl(fpga->fd, IOCTL_SEND, &io);
+}
+
+int fpga_recv(fpga_t * fpga, int chnl, void * data, int len, long long timeout)
+{
+	fpga_chnl_io io;
+
+	io.id = fpga->id;
+	io.chnl = chnl;
+	io.len = len;
+	io.timeout = timeout;
+	io.data = (char *)data;
+
+	return ioctl(fpga->fd, IOCTL_RECV, &io);
+}
+
+void fpga_reset(fpga_t * fpga)
+{
+	ioctl(fpga->fd, IOCTL_RESET, fpga->id);
+}
+
+int fpga_list(fpga_info_list * list) {
+	int fd;
+	int rc;
+
+	fd = open("/dev/" DEVICE_NAME, O_RDWR | O_SYNC);
+	if (fd < 0)
+		return fd;
+	rc = ioctl(fd, IOCTL_LIST, list);
+	close(fd);
+	return rc;
+}
+
+
+

driver/linux/riffa.h

@@ -0,0 +1,120 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+/*
+ * Filename: riffa.h
+ * Version: 2.0
+ * Description: Linux PCIe communications API for RIFFA.
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#ifndef RIFFA_H
+#define RIFFA_H
+
+#include "riffa_driver.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct fpga_t;
+typedef struct fpga_t fpga_t;
+
+/**
+ * Populates the fpga_info_list pointer with all FPGAs registered in the system.
+ * Returns 0 on success, a negative value on error.
+ */
+int fpga_list(fpga_info_list * list);
+
+/**
+ * Initializes the FPGA specified by id. On success, returns a pointer to a 
+ * fpga_t struct. On error, returns NULL. Each FPGA must be opened before any 
+ * channels can be accessed. Once opened, any number of threads can use the 
+ * fpga_t struct.
+ */
+fpga_t * fpga_open(int id);
+
+/**
+ * Cleans up memory/resources for the FPGA specified by the fd descriptor.
+ */
+void fpga_close(fpga_t * fpga);
+
+/**
+ * Sends len words (4 byte words) from data to FPGA channel chnl using the 
+ * fpga_t struct. The FPGA channel will be sent len, destoff, and last. If last
+ * is 1, the channel should interpret the end of this send as the end of a
+ * transaction. If last is 0, the channel should wait for additional sends 
+ * before the end of the transaction. If timeout is non-zero, this call will 
+ * send data and wait up to timeout ms for the FPGA to respond (between
+ * packets) before timing out. If timeout is zero, this call may block 
+ * indefinitely. Multiple threads sending on the same channel may result in 
+ * corrupt data or error. This function is thread safe across channels.
+ * On success, returns the number of words sent. On error returns a negative 
+ * value. 
+ */
+int fpga_send(fpga_t * fpga, int chnl, void * data, int len, int destoff, 
+	int last, long long timeout);
+
+/**
+ * Receives data from the FPGA channel chnl to the data pointer, using the 
+ * fpga_t struct. The FPGA channel can send any amount of data, so the data 
+ * array should be large enough to accommodate. The len parameter specifies the
+ * actual size of the data buffer in words (4 byte words). The FPGA channel will
+ * specify an offset which will determine where in the data array the data will
+ * start being written. If the amount of data (plus offset) exceed the size of
+ * the data array (len), then that data will be discarded. If timeout is 
+ * non-zero, this call will wait up to timeout ms for the FPGA to respond 
+ * (between packets) before timing out. If timeout is zero, this call may block 
+ * indefinitely. Multiple threads receiving on the same channel may result in 
+ * corrupt data or error. This function is thread safe across channels.
+ * On success, returns the number of words written to the data array. On error 
+ * returns a negative value. 
+ */
+int fpga_recv(fpga_t * fpga, int chnl, void * data, int len, long long timeout);
+
+/**
+ * Resets the state of the FPGA and all transfers across all channels. This is
+ * meant to be used as an alternative to rebooting if an error occurs while 
+ * sending/receiving. Calling this function while other threads are sending or
+ * receiving will result in unexpected behavior.
+ */
+void fpga_reset(fpga_t * fpga);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

driver/linux/riffa_driver.h

@@ -0,0 +1,131 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+
+/*
+ * Filename: riffa_driver.h
+ * Version: 2.0
+ * Description: Linux PCIe device driver for RIFFA. Uses Linux kernel APIs in
+ *  version 2.6.27+ (tested on version 2.6.32 - 3.3.0).
+ * Author: Matthew Jacobsen
+ * History: @mattj: Initial release. Version 2.0.
+ */
+
+#ifndef RIFFA_DRIVER_H
+#define RIFFA_DRIVER_H
+
+#include <linux/ioctl.h>
+
+#define DBUG 1
+
+#ifdef DEBUG
+#define DEBUG_MSG(...) printk(__VA_ARGS__)
+#else
+#define DEBUG_MSG(...)
+#endif
+
+
+// The major device number. We can't rely on dynamic registration because ioctls
+// need to know it.
+#define MAJOR_NUM 100
+#define DEVICE_NAME "riffa"
+#define VENDOR_ID0 0x10EE
+#define VENDOR_ID1 0x1172
+
+// Message events for readmsgs/writemsgs queues.
+#define EVENT_TXN_LEN				1
+#define EVENT_TXN_OFFLAST			2
+#define EVENT_TXN_DONE				3
+#define EVENT_SG_BUF_READ			4
+
+// Constants and device offsets
+#define NUM_FPGAS					5 	// max # of FPGAs to support in a single PC
+#define MAX_CHNLS					12	// max # of channels per FPGA
+#define MAX_BUS_WIDTH_PARAM			4	// max bus width parameter
+#define SG_BUF_SIZE					(4*1024)	// size of shared SG buffer
+#define SG_ELEMS					200 // # of SG elements to transfer at a time
+#define SPILL_BUF_SIZE				(4*1024)	// size of shared spill common buffer
+
+#define RX_SG_LEN_REG_OFF			0x0	// config offset for RX SG buf length
+#define RX_SG_ADDR_LO_REG_OFF		0x1	// config offset for RX SG buf low addr
+#define RX_SG_ADDR_HI_REG_OFF		0x2	// config offset for RX SG buf high addr
+#define RX_LEN_REG_OFF				0x3	// config offset for RX txn length
+#define RX_OFFLAST_REG_OFF			0x4	// config offset for RX txn last/offset
+#define RX_TNFR_LEN_REG_OFF			0xD	// config offset for RX transfer length
+#define TX_SG_LEN_REG_OFF			0x5	// config offset for TX SG buf length
+#define TX_SG_ADDR_LO_REG_OFF		0x6	// config offset for TX SG buf low addr
+#define TX_SG_ADDR_HI_REG_OFF		0x7	// config offset for TX SG buf high addr
+#define TX_LEN_REG_OFF				0x8	// config offset for TX txn length
+#define TX_OFFLAST_REG_OFF			0x9	// config offset for TX txn last/offset
+#define TX_TNFR_LEN_REG_OFF			0xE	// config offset for TX transfer length
+
+#define INFO_REG_OFF				0xA	// config offset for link info
+
+#define IRQ_REG0_OFF				0xB	// config offset for interrupt reg 0
+#define IRQ_REG1_OFF				0xC	// config offset for interrupt reg 1
+
+
+// Structs
+struct fpga_chnl_io
+{
+	int id;
+	int chnl;
+	unsigned int len;
+	unsigned int offset;
+	unsigned int last;
+	unsigned long long timeout;
+	char * data;
+};
+typedef struct fpga_chnl_io fpga_chnl_io;
+
+struct fpga_info_list
+{
+	int num_fpgas;
+	int id[NUM_FPGAS];
+	int num_chnls[NUM_FPGAS];
+	char name[NUM_FPGAS][16];
+	int vendor_id[NUM_FPGAS];
+	int device_id[NUM_FPGAS];
+};
+typedef struct fpga_info_list fpga_info_list;
+
+// IOCTLs
+#define IOCTL_SEND _IOW(MAJOR_NUM, 1, fpga_chnl_io *)
+#define IOCTL_RECV _IOR(MAJOR_NUM, 2, fpga_chnl_io *)
+#define IOCTL_LIST _IOR(MAJOR_NUM, 3, fpga_info_list *)
+#define IOCTL_RESET _IOW(MAJOR_NUM, 4, int)
+
+
+
+#endif

driver/windows/README.txt

@@ -0,0 +1,40 @@
+To build the Windows driver:
+
+1) Install Windows Driver Development Kit supporting Windows 7 (tested on 
+   version 7600.16385.1).
+2) Open a DDK command window environment for Windows 7 (which ever version 
+   you're targeting).
+3) Move to the directory containing this README.txt and run: build -ceZ
+4) The driver should be built and ready in the output directory along with a
+   Windows 7 catalog file and the coinstaller DLLs.
+
+A few notes:
+
+- You will need to sign the driver (riffa.sys) and catalog file (riffa.cat) 
+  before you can install it on a x64 Windows 7 or Vista computer. The build 
+  process will attempt to sign the catalog file with the UCSD certificate. You
+  don't have that, so you won't get a signed driver simply by building. You'll
+  need to get a certificate from a certificate authority that is capable of 
+  cross-certificate kernel driver signing. See this page for more details:
+  http://msdn.microsoft.com/en-us/windows/hardware/gg487315.aspx
+    
+- Debugging on Windows is difficult because there exists no kernel log file.
+  Drivers are supposed to log messages using a trace events framework which is
+  overly complex and requires developer tools to first collect the output and
+  then more (different) tools to make the output human readable. Instead, this
+  driver writes normal log messages via a kernel debugger facility. To see the
+  messages you'll need the Windows Development Kit debugger (WinDbg) or a small
+  utility called DbgView. DbgView is a standalone kernel debug viewer that can
+  be downloaded from Microsoft here:
+  http://technet.microsoft.com/en-us/sysinternals/bb896647.aspx
+  Just start with administrator privileges and be sure to enable Capture Kernel, 
+  Capture Events, and Capture Verbose Kernel Output.
+
+- Building with the checked environment will produce a version of the driver
+  with verbose debugging output. Building with the free environment will 
+  produce a version of the driver with minimal messaging output. The debug 
+  version will have a "(Debug)" label in the Windows device manager, so you 
+  can tell which version is installed.
+
+- Inno Setup scripts produce a Windows Installer. You may use our script if you
+  like.

driver/windows/dirs

@@ -0,0 +1,2 @@
+DIRS= \
+     sys

driver/windows/install/install.bat

@@ -0,0 +1,25 @@
+@echo off
+
+rmdir /s /q build
+md build
+md build\x86
+md build\x64
+
+copy win7.iss .\build
+copy license.txt .\build
+
+xcopy /E /H /K /I /Y %1 .\build\x86
+xcopy /E /H /K /I /Y %2 .\build\x64
+xcopy /E /H /K /I /Y ..\..\..\c_c++\windows .\build\c_c++
+xcopy /E /H /K /I /Y ..\..\..\java .\build\java
+xcopy /E /H /K /I /Y ..\..\..\python .\build\python
+xcopy /E /H /K /I /Y ..\..\..\matlab .\build\matlab
+
+if "%3" == "chk" (
+    "c:\program files\inno setup 5\iscc.exe" /dDebug="1" /o.\build .\build\win7.iss 
+) else (
+    "c:\program files\inno setup 5\iscc.exe" /o.\build .\build\win7.iss 
+)
+signtool sign /v /s my /n "University of California, San Diego" /t http://timestamp.verisign.com/scripts/timestamp.dll .\build\setup.exe
+
+

driver/windows/install/license.txt

@@ -0,0 +1,34 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+//
+// * Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// * Redistributions in binary form must reproduce the above
+// copyright notice, this list of conditions and the following
+// disclaimer in the documentation and/or other materials provided
+// with the distribution.
+//
+// * Neither the name of The Regents of the University of California
+// nor the names of its contributors may be used to endorse or
+// promote products derived from this software without specific
+// prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------

driver/windows/install/win7.iss

@@ -0,0 +1,87 @@
+; -- 64Bit.iss --
+; Demonstrates installation of a program built for the x64 (a.k.a. AMD64)
+; architecture.
+; To successfully run this installation and the program it installs,
+; you must have a "x64" edition of Windows.
+
+; SEE THE DOCUMENTATION FOR DETAILS ON CREATING .ISS SCRIPT FILES!
+#ifdef Debug
+#define DebugMsg1 "%n%nNOTE: This version has been compiled to output additional debug messages (with some performance overhead)."
+#else
+#define DebugMsg1 ""
+#endif
+
+[Setup]
+AppName=RIFFA
+AppVersion=2.0
+AppPublisher=University of California, San Diego
+AppPublisherURL=https://sites.google.com/a/eng.ucsd.edu/matt-jacobsen/riffa
+AppCopyright=Copyright (C) 2012 The Regents of the University of California. All Rights Reserved.
+LicenseFile=license.txt
+PrivilegesRequired=admin
+MinVersion=6.1
+OnlyBelowVersion=6.2
+DisableProgramGroupPage=yes
+Compression=lzma2
+SolidCompression=yes
+UsePreviousAppDir=no
+DefaultDirName={pf}\Riffa
+OutputDir=outputdir
+; "ArchitecturesInstallIn64BitMode=x64" requests that the install be
+; done in "64-bit mode" on x64, meaning it should use the native
+; 64-bit Program Files directory and the 64-bit view of the registry.
+ArchitecturesInstallIn64BitMode=x64
+
+[Messages]
+WelcomeLabel1=Welcome to the [name] Setup Wizard
+WelcomeLabel2=This will install the [name/ver] FPGA drivers and C/C++ bindings on your computer.{#DebugMsg1}%n%nSee the install program directory for details on installing other language bindings.%n%nIt is recommended that you close all other applications and disable any anti virus before continuing.
+FinishedLabelNoIcons=Setup has finished installing [name/ver] on your computer.%n%nAny [name] compatible FPGA devices should be detected upon reboot.
+
+[Dirs]
+Name: "{app}\c_c++"; Permissions: users-modify
+Name: "{app}\java"; Permissions: users-modify
+Name: "{app}\python"; Permissions: users-modify
+Name: "{app}\matlab"; Permissions: users-modify
+
+[Files]
+Source: "c_c++\x86\riffa.lib"; DestDir: "{app}\c_c++"; DestName: "riffa32.lib"
+Source: "c_c++\x86\riffa.h"; DestDir: "{app}\c_c++"; Check: "not IsWin64"
+Source: "c_c++\x86\sample_app\README.txt"; DestDir: "{app}\c_c++"; Check: "not IsWin64"
+Source: "c_c++\x86\sample_app\timer.h"; DestDir: "{app}\c_c++"; Check: "not IsWin64"
+Source: "c_c++\x86\sample_app\testutil.c"; DestDir: "{app}\c_c++"; Check: "not IsWin64"
+Source: "c_c++\x86\sample_app\testutil.exe"; DestDir: "{app}\c_c++"; Check: "not IsWin64"
+Source: "c_c++\x64\riffa.lib"; DestDir: "{app}\c_c++"; DestName: "riffa64.lib"; Check: IsWin64
+Source: "c_c++\x64\riffa.h"; DestDir: "{app}\c_c++"; Check: IsWin64
+Source: "c_c++\x64\sample_app\README.txt"; DestDir: "{app}\c_c++"; Check: IsWin64
+Source: "c_c++\x64\sample_app\timer.h"; DestDir: "{app}\c_c++"; Check: IsWin64
+Source: "c_c++\x64\sample_app\testutil.c"; DestDir: "{app}\c_c++"; Check: IsWin64
+Source: "c_c++\x64\sample_app\testutil.exe"; DestDir: "{app}\c_c++"; Check: IsWin64
+
+Source: "java\README.txt"; DestDir: "{app}\java"
+Source: "java\riffa.jar"; DestDir: "{app}\java"
+Source: "java\SampleApp.java"; DestDir: "{app}\java"
+
+Source: "matlab\README.txt"; DestDir: "{app}\matlab"
+Source: "matlab\Riffa.m"; DestDir: "{app}\matlab"
+
+Source: "python\dist\README.txt"; DestDir: "{app}\python"
+Source: "python\dist\riffa-2.0.zip"; DestDir: "{app}\python"
+Source: "python\sample_app\sampleapp.py"; DestDir: "{app}\python"
+
+Source: "x86\riffa.sys"; DestDir: "{tmp}"; Check: "not IsWin64"
+Source: "x86\riffa.inf"; DestDir: "{tmp}"; Check: "not IsWin64"
+Source: "x86\riffa.cat"; DestDir: "{tmp}"; Check: "not IsWin64"
+Source: "x86\WdfCoInstaller01009.dll"; DestDir: "{tmp}"; Check: "not IsWin64"
+Source: "x86\WdfCoInstaller01009_chk.dll"; DestDir: "{tmp}"; Check: "not IsWin64"
+Source: "x64\riffa.sys"; DestDir: "{tmp}"; Check: IsWin64
+Source: "x64\riffa.inf"; DestDir: "{tmp}"; Check: IsWin64
+Source: "x64\riffa.cat"; DestDir: "{tmp}"; Check: IsWin64
+Source: "x64\WdfCoInstaller01009.dll"; DestDir: "{tmp}"; Check: IsWin64
+Source: "x64\WdfCoInstaller01009_chk.dll"; DestDir: "{tmp}"; Check: IsWin64
+
+Source: "c_c++\x86\riffa.dll"; DestDir: {sys}; Flags: 32bit
+Source: "c_c++\x64\riffa.dll"; DestDir: {sys}; Flags: 64bit; Check: IsWin64
+
+[Run]
+Filename: "{sys}\pnputil.exe"; Parameters: " -i -a {tmp}\riffa.inf"; WorkingDir: "{tmp}"; Description: "Install driver"; StatusMsg: "Installing drivers..."; Flags: runascurrentuser runhidden;
+

driver/windows/sys/makefile

@@ -0,0 +1,7 @@
+#
+# DO NOT EDIT THIS FILE!!!  Edit .\sources. if you want to add a new source
+# file to this component.  This file merely indirects to the real make file
+# that is shared by all the components of Windows
+#
+!INCLUDE $(NTMAKEENV)\makefile.def
+

driver/windows/sys/makefile.inc

@@ -0,0 +1,28 @@
+_LNG=$(LANGUAGE)
+_INX=.
+STAMP=stampinf -f $@ -a $(_BUILDARCH) -k $(KMDF_VERSION_MAJOR).$(KMDF_VERSION_MINOR)
+
+
+$(OBJ_PATH)\$(O)\$(INF_NAME).inf: $(_INX)\$(INF_NAME).inx
+    copy $(_INX)\$(@B).inx $@
+    $(STAMP)
+!   if "$(DDKBUILDENV)" == "chk"
+        echo RIFFA.DEBUG=" (Debug)" >> $@
+!   else    
+        echo RIFFA.DEBUG="" >> $@
+!   endif    
+
+
+POST:
+    copy $(BASEDIR)\redist\wdf\$(_BUILDARCH)\WdfCoInstaller*.dll $(OBJ_PATH)\$(O)
+!   if "$(DDK_TARGET_OS)" == "Win7"
+!       if "$(_BUILDARCH)" == "x86"
+            inf2cat /driver:$(OBJ_PATH)\$(O) /os:7_x86
+!       else 
+            inf2cat /driver:$(OBJ_PATH)\$(O) /os:7_x64
+!       endif 
+!   endif 
+    signtool sign /v /ac "$(_INX)\GlobalSign Root CA.crt" /s my /n "University of California, San Diego" /t http://timestamp.verisign.com/scripts/timestamp.dll $(OBJ_PATH)\$(O)\$(INF_NAME).cat
+    signtool sign /v /ac "$(_INX)\GlobalSign Root CA.crt" /s my /n "University of California, San Diego" /t http://timestamp.verisign.com/scripts/timestamp.dll $(OBJ_PATH)\$(O)\$(INF_NAME).sys
+
+    

driver/windows/sys/precomp.h

@@ -0,0 +1,21 @@
+#define WIN9X_COMPAT_SPINLOCK
+#include <ntddk.h>
+#pragma warning(disable:4201)  // nameless struct/union warning
+
+#include <stdarg.h>
+#include <wdf.h>
+#include <ntstrsafe.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+#pragma warning(default:4201)
+
+#include <initguid.h> // required for GUID definitions
+#include <wdmguid.h>  // required for WMILIB_CONTEXT
+
+
+#include "riffa_driver.h"
+#include "riffa_private.h"
+#include "trace.h"
+
+

driver/windows/sys/riffa.inx

@@ -0,0 +1,108 @@
+
+[Version]
+Signature="$WINDOWS NT$"
+Class=FPGA
+ClassGuid={78A1C341-4539-11d3-B88D-00C04FAD5171}
+Provider=%UCSD%
+DriverVer=03/20/2003,6.00.3790
+CatalogFile=riffa.cat
+
+[DestinationDirs]
+DefaultDestDir = 12
+
+; ================= Class section =====================
+
+[ClassInstall32]
+Addreg=FPGAClassReg     
+
+[FPGAClassReg]
+HKR,,,0,%ClassName%
+HKR,,Icon,,-5
+HKR,,DeviceCharacteristics,0x10001,0x100     ;Use same security checks on relative opens
+HKR,,Security,,"D:P(A;;GA;;;WD)" ;Allow generic all access to all. 
+;HKR,,Security,,"D:P(A;;GA;;;SY)(A;;GA;;;BA)" ;Allow generic all access to system and built-in Admin. 
+
+; ================= Device Install section =====================
+
+[ControlFlags]
+ExcludeFromSelect=*
+
+[Manufacturer]
+%UCSD%=UCSD,NT$ARCH$
+
+[SourceDisksFiles]
+riffa.sys=1
+
+[SourceDisksNames]
+1=%DISK_NAME%,
+
+; For Win2K
+[UCSD]
+; DisplayName                        Section           DeviceId           CompatibleId
+; -----------                        -------           --------           ------------
+%RIFFA.XILINXDESC%%RIFFA.DEBUG%=     RIFFA_Inst,       PCI\VEN_10EE,      PCI\VEN_10EE
+%RIFFA.ALTERADESC%%RIFFA.DEBUG%=     RIFFA_Inst,       PCI\VEN_1172,      PCI\VEN_1172
+
+; For XP and later
+[UCSD.NT$ARCH$]
+; DisplayName                        Section           DeviceId           CompatibleId
+; -----------                        -------           --------           ------------
+%RIFFA.XILINXDESC%%RIFFA.DEBUG%=     RIFFA_Inst,       PCI\VEN_10EE,      PCI\VEN_10EE
+%RIFFA.ALTERADESC%%RIFFA.DEBUG%=     RIFFA_Inst,       PCI\VEN_1172,      PCI\VEN_1172
+
+[RIFFA_Inst.NT]
+CopyFiles=RIFFA.CopyFiles
+
+[RIFFA.CopyFiles]
+riffa.sys
+
+[RIFFA_Inst.NT.HW]
+AddReg=RIFFA.HwReg 
+
+[RIFFA.HwReg]
+HKR,"Interrupt Management",,0x00000010
+HKR,"Interrupt Management\MessageSignaledInterruptProperties",,0x00000010
+HKR,"Interrupt Management\MessageSignaledInterruptProperties",MSISupported,0x00010001,1
+
+[RIFFA_Inst.NT.Services]
+AddService=RIFFA,0x00000002,RIFFA_Service 
+
+[RIFFA_Service]
+DisplayName    = %RIFFA.SVCDESC%                            
+ServiceType    = 1                  ; SERVICE_KERNEL_DRIVER
+StartType      = 3                  ; SERVICE_DEMAND_START
+ErrorControl   = 1                  ; SERVICE_ERROR_NORMAL
+ServiceBinary  = %12%\riffa.sys                            
+AddReg         = RIFFA_Parameters_AddReg
+
+;-------------- Coinstaller installation
+[DestinationDirs]
+CoInstaller_CopyFiles = 11
+
+[RIFFA_Inst.NT.CoInstallers]
+AddReg=CoInstaller_AddReg
+CopyFiles=CoInstaller_CopyFiles
+
+[CoInstaller_CopyFiles]
+WdfCoInstaller$KMDFCOINSTALLERVERSION$.dll
+
+[SourceDisksFiles]
+WdfCoInstaller$KMDFCOINSTALLERVERSION$.dll=1 ; make sure the number matches with SourceDisksNames
+
+[CoInstaller_AddReg]
+HKR,,CoInstallers32,0x00010000, "WdfCoInstaller$KMDFCOINSTALLERVERSION$.dll,WdfCoInstaller"
+
+[RIFFA_Inst.NT.Wdf]
+KmdfService = RIFFA, RIFFA_wdfsect
+
+[RIFFA_wdfsect]
+KmdfLibraryVersion = $KMDFVERSION$
+
+[Strings]
+UCSD = "University of California, San Diego"
+ClassName = "RIFFA Devices"
+RIFFA.SVCDESC = "Driver Service for RIFFA FPGAs"
+RIFFA.XILINXDESC = "Xilinx(R) FPGA"
+RIFFA.ALTERADESC = "Altera(R) FPGA"
+DISK_NAME = "RIFFA Install Disk"
+

driver/windows/sys/riffa.rc

@@ -0,0 +1,15 @@
+#include <windows.h>
+
+#include <ntverp.h>
+
+#define VER_FILETYPE                VFT_DRV
+#define VER_FILESUBTYPE             VFT2_DRV_SYSTEM
+#define VER_FILEDESCRIPTION_STR     "WDF Driver for RIFFA"
+#define VER_INTERNALNAME_STR        "riffa.sys"
+#define VER_ORIGINALFILENAME_STR    "riffa.sys"
+
+#include "common.ver"
+
+
+
+

driver/windows/sys/riffa_driver.h

@@ -0,0 +1,19 @@
+//
+// The following value is arbitrarily chosen from the space defined
+// by Microsoft as being "for non-Microsoft use"
+//
+//
+// {40d49fb9-6085-4e1d-8753-822be944d7bb}
+DEFINE_GUID (GUID_RIFFA_INTERFACE,
+   0x40d49fb9, 0x6085, 0x4e1d, 0x87, 0x53, 0x82, 0x2b, 0xe9, 0x44, 0xd7, 0xbb);
+
+// The IOCTL function codes from 0x800 to 0xFFF are for customer use.
+#define IOCTL_RIFFA_SEND \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x900, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)
+#define IOCTL_RIFFA_RECV \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x901, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)
+#define IOCTL_RIFFA_LIST \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x902, METHOD_OUT_DIRECT ,FILE_ANY_ACCESS)
+#define IOCTL_RIFFA_RESET \
+    CTL_CODE(FILE_DEVICE_UNKNOWN, 0x903, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)
+

driver/windows/sys/riffa_private.h

@@ -0,0 +1,187 @@
+#if !defined(_RIFFA_H_)
+#define _RIFFA_H_
+
+// Adjusts register offsets for each channel
+#define CHNL_REG(c, o) (((c)<<4) + o)
+
+// Register offsets
+#define RIFFA_RX_SG_LEN_REG			0x0
+#define RIFFA_RX_SG_ADDR_LO_REG		0x1
+#define RIFFA_RX_SG_ADDR_HI_REG		0x2
+#define RIFFA_RX_LEN_REG			0x3
+#define RIFFA_RX_OFFLAST_REG		0x4
+#define RIFFA_TX_SG_LEN_REG			0x5
+#define RIFFA_TX_SG_ADDR_LO_REG		0x6
+#define RIFFA_TX_SG_ADDR_HI_REG		0x7
+#define RIFFA_TX_LEN_REG			0x8
+#define RIFFA_TX_OFFLAST_REG		0x9
+#define RIFFA_INFO_REG				0xA
+#define RIFFA_IRQ_0_REG				0xB
+#define RIFFA_IRQ_1_REG				0xC
+#define RIFFA_RX_TNFR_LEN_REG		0xD
+#define RIFFA_TX_TNFR_LEN_REG		0xE
+
+// Size of common buffer for scatter gather elements
+#define RIFFA_MIN_SG_BUF_SIZE (4*1024)
+
+// Size of common buffer for receive data spill
+#define RIFFA_SPILL_BUF_SIZE (4*1024)
+
+// Maximum number of scatter gather elements for each transfer
+#define RIFFA_MIN_NUM_SG_ELEMS (200)
+
+// Maximum bus width (multiply by 32 to get bit width)
+#define RIFFA_MAX_BUS_WIDTH_PARAM (4)
+
+// Maximum DMA transfer size (in bytes).
+#define RIFFA_MAX_TNFR_LEN (0xFFFFFFFF)
+
+// Number of DMA channels supported
+#define RIFFA_MAX_NUM_CHNLS (12)
+
+// Maximum number of RIFFA FPGAs
+#define RIFFA_MAX_NUM_FPGAS (5)
+
+// The structure used to hold data transfer information
+typedef struct RIFFA_FPGA_CHNL_IO {
+	UINT32					Id;
+	UINT32					Chnl;
+	UINT32					Length;
+	UINT32					Offset;
+	UINT32					Last;
+	UINT64					Timeout;
+} RIFFA_FPGA_CHNL_IO, * PRIFFA_FPGA_CHNL_IO;
+
+// The structure used to hold FPGA information
+typedef struct RIFFA_FPGA_INFO {
+	UINT32					num_fpgas;
+	UINT32					id[RIFFA_MAX_NUM_FPGAS];
+	UINT32					num_chnls[RIFFA_MAX_NUM_FPGAS];
+	CHAR					name[RIFFA_MAX_NUM_FPGAS][16];
+	UINT32					vendor_id[RIFFA_MAX_NUM_FPGAS];
+	UINT32					device_id[RIFFA_MAX_NUM_FPGAS];
+} RIFFA_FPGA_INFO, * PRIFFA_FPGA_INFO;
+
+// Struct for holding DMA transaction state
+typedef struct CHNL_DIR_STATE {
+	LONG					Ready;
+	LONG					InUse;
+	LONG					ReqdDone;
+	UINT64					Length;
+	UINT64					Offset;
+	UINT32					Last;
+	UINT64					Timeout;
+	UINT64					Capacity;
+	UINT64					Provided;
+	UINT64					ProvidedPrev;
+	UINT64					Confirmed;
+	UINT64					ConfirmedPrev;
+	UINT64					SpillAfter;
+	PSCATTER_GATHER_LIST	SgList;
+	UINT32					SgPos;
+	UINT32					ActiveCount;
+	UINT32					Cancel;
+	WDFSPINLOCK				SpinLock;
+	WDFTIMER				Timer;
+	WDFREQUEST				Request;
+	WDFDMATRANSACTION 		DmaTransaction;
+	WDFCOMMONBUFFER 		CommonBuffer;
+	PULONG 					CommonBufferBase;
+	PHYSICAL_ADDRESS 		CommonBufferBaseLA;	// Logical Address
+} CHNL_DIR_STATE, *PCHNL_DIR_STATE;
+
+// Struct for holding interrupt signals and data
+typedef struct INTR_CHNL_DIR_DATA {
+	BOOLEAN 				NewTxn;
+	UINT32 					OffLast;
+	UINT32 					Length;
+	BOOLEAN 				SgRead;
+	BOOLEAN 				Done;
+} INTR_CHNL_DIR_DATA, *PINTR_CHNL_DIR_DATA;
+
+// The device extension for the device object
+typedef struct _DEVICE_EXTENSION {
+	WDFDEVICE 				Device;
+	PULONG 					Bar0;
+	UINT32 					Bar0Length;
+	UINT32					MaxNumScatterGatherElems;
+	WDFINTERRUPT 			Interrupt;
+	WDFDMAENABLER 			DmaEnabler;
+	WDFQUEUE 				IoctlQueue;
+	UINT32 					NumChnls;
+	UINT32 					VendorId;
+	UINT32 					DeviceId;
+	CHAR 					Name[16];
+	INTR_CHNL_DIR_DATA		IntrData[2 * RIFFA_MAX_NUM_CHNLS];	// Send is the first bank,
+	CHNL_DIR_STATE			Chnl[(2*RIFFA_MAX_NUM_CHNLS)];		// recv is the second bank
+	WDFCOMMONBUFFER 		SpillBuffer;
+	PUCHAR 					SpillBufferBase;
+	PHYSICAL_ADDRESS 		SpillBufferBaseLA;	// Logical Address
+} DEVICE_EXTENSION, *PDEVICE_EXTENSION;
+
+// The request extension for the request object
+typedef struct _REQUEST_EXTENSION {
+	UINT32 					Chnl;
+} REQUEST_EXTENSION, *PREQUEST_EXTENSION;
+
+// The timer extension for the timer object
+typedef struct _TIMER_EXTENSION {
+	UINT32 					Chnl;
+} TIMER_EXTENSION, *PTIMER_EXTENSION;
+
+// This will generate the function named RiffaGetDeviceContext to be used for
+// retreiving the DEVICE_EXTENSION pointer.
+WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(DEVICE_EXTENSION, RiffaGetDeviceContext)
+
+// This will generate the function named RiffaGetTimerContext to be used for
+// retreiving the TIMER_EXTENSION pointer.
+WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(TIMER_EXTENSION, RiffaGetTimerContext)
+
+// This will generate the function named RiffaGetRequestContext to be used for
+// retreiving the REQUEST_EXTENSION pointer.
+WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(REQUEST_EXTENSION, RiffaGetRequestContext)
+
+
+// Function prototypes
+DRIVER_INITIALIZE DriverEntry;
+
+EVT_WDF_DRIVER_DEVICE_ADD RiffaEvtDeviceAdd;
+EVT_WDF_OBJECT_CONTEXT_CLEANUP RiffaEvtDriverContextCleanup;
+
+EVT_WDF_DEVICE_PREPARE_HARDWARE RiffaEvtDevicePrepareHardware;
+EVT_WDF_DEVICE_RELEASE_HARDWARE RiffaEvtDeviceReleaseHardware;
+NTSTATUS RiffaReadHardwareIds(IN PDEVICE_EXTENSION DevExt);
+
+EVT_WDF_INTERRUPT_ISR RiffaEvtInterruptIsr;
+EVT_WDF_INTERRUPT_DPC RiffaEvtInterruptDpc;
+BOOLEAN RiffaProcessInterrupt(IN PDEVICE_EXTENSION DevExt, IN UINT32 Offset, IN UINT32 Vect);
+
+EVT_WDF_IO_QUEUE_IO_DEVICE_CONTROL  RiffaEvtIoDeviceControl;
+VOID RiffaIoctlSend(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,
+	IN size_t OutputBufferLength, IN size_t InputBufferLength);
+VOID RiffaIoctlRecv(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,
+	IN size_t OutputBufferLength, IN size_t InputBufferLength);
+VOID RiffaIoctlList(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,
+	IN size_t OutputBufferLength, IN size_t InputBufferLength);
+VOID RiffaIoctlReset(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request);
+
+BOOLEAN RiffaThreadEnter(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl);
+BOOLEAN RiffaThreadExit(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl);
+VOID RiffaCompleteRequest(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl, IN NTSTATUS Status);
+EVT_WDF_REQUEST_CANCEL RiffaEvtRequestCancel;
+EVT_WDF_TIMER RiffaEvtTimerFunc;
+
+VOID RiffaStartRecvTransaction(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl);
+NTSTATUS RiffaStartDmaTransaction(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,
+	IN UINT64 Length, IN UINT64 Offset, IN WDF_DMA_DIRECTION DmaDirection);
+VOID RiffaProgramScatterGather(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl);
+VOID RiffaTransactionComplete(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,
+	IN UINT32 Transferred, IN NTSTATUS Status);
+VOID RiffaProgramSend(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl, IN UINT32 Length,
+	IN UINT32 Offset, IN UINT32 Last);
+EVT_WDF_PROGRAM_DMA RiffaEvtProgramDma;
+
+#pragma warning(disable:4127) // avoid conditional expression is constant error with W4
+
+#endif
+

driver/windows/sys/sources

@@ -0,0 +1,40 @@
+TARGETNAME=riffa
+TARGETTYPE=DRIVER
+
+
+KMDF_VERSION_MAJOR=1
+
+INF_NAME=riffa
+NTTARGETFILE0=$(OBJ_PATH)\$(O)\$(INF_NAME).inf
+NTTARGETFILE2=POST
+PASS0_BINPLACE=$(NTTARGETFILE0)
+
+TARGETLIBS=$(TARGETLIBS) \
+           $(DDK_LIB_PATH)\ntstrsafe.lib
+
+PRECOMPILED_INCLUDE=precomp.h
+PRECOMPILED_PCH=precomp.pch
+PRECOMPILED_OBJ=precomp.obj
+
+#C_DEFINES = $(C_DEFINES) -DASSOC_WRITE_REQUEST_WITH_DMA_TRANSACTION=1
+
+SOURCES= riffa.rc  \
+         riffa.c
+         
+# Generate WPP tracing code
+# $(SOURCES)   -- run software preprocessor on files listed in SOURCES
+# -km          -- use kernel mode
+# -func        -- define function we'll use for tracing
+#                 This would map all TraceEvents calls to 
+#                 DoTraceMessage.
+#
+RUN_WPP= $(SOURCES)                             \
+         -km                                    \
+         -func:TraceEvents(LEVEL,FLAGS,MSG,...) \
+         -gen:{km-WdfDefault.tpl}*.tmh
+         
+TARGET_DESTINATION=wdf
+
+# Temporarily excuse usage of serviceability impairing macros in code...
+ALLOW_DATE_TIME=1
+

driver/windows/sys/trace.h

@@ -0,0 +1,31 @@
+#include <evntrace.h> // For TRACE_LEVEL definitions
+
+//
+// If software tracing is defined in the sources file..
+// WPP_DEFINE_CONTROL_GUID specifies the GUID used for this driver.
+// *** REPLACE THE GUID WITH YOUR OWN UNIQUE ID ***
+// WPP_DEFINE_BIT allows setting debug bit masks to selectively print.
+// The names defined in the WPP_DEFINE_BIT call define the actual names
+// that are used to control the level of tracing for the control guid
+// specified.
+//
+// Name of the logger is RIFFA and the guid is
+//   {CA630800-D4D4-4457-8983-DFBBFCAC5542}
+//   (0xca630800, 0xd4d4, 0x4457, 0x89, 0x83, 0xdf, 0xbb, 0xfc, 0xac, 0x55, 0x42);
+//
+
+#define WPP_CHECK_FOR_NULL_STRING  //to prevent exceptions due to NULL strings
+
+#define WPP_CONTROL_GUIDS \
+    WPP_DEFINE_CONTROL_GUID(RiffaTraceGuid, (ca630800, D4D4, 4457,8983, DFBBFCAC5542),\
+        WPP_DEFINE_BIT(DBG_INIT)             /* bit  0 = 0x00000001 */ \
+        WPP_DEFINE_BIT(DBG_PNP)              /* bit  1 = 0x00000002 */ \
+        /* You can have up to 32 defines. If you want more than that,\
+            you have to provide another trace control GUID */\
+        )
+
+
+#define WPP_LEVEL_FLAGS_LOGGER(lvl,flags) WPP_LEVEL_LOGGER(flags)
+#define WPP_LEVEL_FLAGS_ENABLED(lvl, flags) (WPP_LEVEL_ENABLED(flags) && WPP_CONTROL(WPP_BIT_ ## flags).Level  >= lvl)
+
+

driver/windows/win7install.bat

@@ -0,0 +1,8 @@
+@echo off
+
+set OLDDIR=%CD%
+set BDIR1=%CD%\sys\obj%_BUILDTYPE%_%DDK_TARGET_OS%_x86\i386
+set BDIR2=%CD%\sys\obj%_BUILDTYPE%_%DDK_TARGET_OS%_amd64\amd64
+chdir /d %CD%\install
+call install.bat %BDIR1% %BDIR2% %_BUILDTYPE%
+chdir /d %OLDDIR%

fpga/altera/de4/DE4Gen1x8If64/constr/DE4Gen1x8If64.sdc

@@ -0,0 +1,64 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            DE4Gen1x8If64.sdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Synopsys Design Constraints for the DE4 board.
+# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+# Oscillator clk (50 MHz Input)
+create_clock -name OSCILLATOR_CLK -period 20 [get_ports {OSC_50_BANK2}]
+
+# Refclk (100 MHz differential input)
+create_clock -period "100 MHz" -name {refclk} [get_ports {PCIE_REFCLK}]
+
+# 50 MHZ PLL Clock
+create_generated_clock -name clk50 -source [get_ports {OSC_50_BANK2}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[0]}]
+
+# 125 MHZ PLL Clock
+create_generated_clock -name clk125 -multiply_by 5 -divide_by 2 -source [get_ports {OSC_50_BANK2}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[1]}]
+
+# 250 MHZ PLL Clock
+create_generated_clock -name clk250 -multiply_by 5 -source [get_ports {OSC_50_BANK2}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[2]}]
+
+derive_pll_clocks 
+derive_clock_uncertainty
+
+# Imported from IP Compiler user guide
+set_clock_groups -exclusive -group [get_clocks { refclk*clkout }] -group [get_clocks { *div0*coreclkout}]
+set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }] -group [get_clocks { *central_clk_div1* }]
+

fpga/altera/de4/DE4Gen1x8If64/hdl/DE4Gen1x8If64.v

@@ -0,0 +1,417 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            DE4Gen1x8If64.v
+// Version:             
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Altera Stratix IV IP Compiler for PCI Express
+//                      module and the Terasic DE4 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`timescale 1ps / 1ps
+module DE4Gen1x8If64
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 12,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Quartus IP Library
+      parameter C_PCI_DATA_WIDTH = 64,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     input                    OSC_50_BANK2,
+     input                    OSC_50_BANK3,
+     input                    OSC_50_BANK4,
+     input                    OSC_50_BANK5,
+     input                    OSC_50_BANK6,
+     input                    PCIE_RESET_N,
+     input                    PCIE_REFCLK,
+     input [C_NUM_LANES-1:0]  PCIE_RX_IN,
+     output [C_NUM_LANES-1:0] PCIE_TX_OUT,
+     output [7:0]             LED
+     );
+
+    // ----------PLL Signals----------
+    wire                      clk50;
+    wire                      clk125;
+    wire                      clk250;
+    wire                      locked;
+    wire                      inclk0;
+
+    // ----------PCIe Core Signals----------
+    // ----------PCIe Clocks----------
+    wire                      pld_clk;
+    wire                      reconfig_clk;
+    wire                      core_clk_out;
+    wire                      fixedclk_serdes;
+    wire                      refclk;
+    wire                      rc_pll_locked;
+    wire                      cal_blk_clk;
+
+    // ----------PCIe Resets----------
+    wire [  4: 0]             pex_msi_num;
+    wire                      pll_powerdown;
+    wire                      reset_status;
+    wire                      crst;
+    wire                      npor;
+    wire                      srst;
+    wire                      gxb_powerdown;
+
+    // ----------PCIe Transaction layer configuration ----------
+    wire [  3: 0]             tl_cfg_add;
+    wire [ 31: 0]             tl_cfg_ctl;
+    wire                      tl_cfg_ctl_wr;
+    wire [ 52: 0]             tl_cfg_sts;
+    wire                      tl_cfg_sts_wr;
+    wire [ 19: 0]             ko_cpl_spc_vc0;
+    
+    // ----------PCIe Local Management Interface----------
+    wire                      lmi_ack;
+    wire [ 31: 0]             lmi_dout;
+    wire [ 11: 0]             lmi_addr;
+    wire [ 31: 0]             lmi_din;
+    wire                      lmi_rden;
+    wire                      lmi_wren;
+
+    // ----------PCIe Interrupt Interface   ----------
+    wire                      app_int_ack;
+    wire                      app_msi_ack;
+    wire                      app_int_sts;
+    wire                      app_msi_req;
+
+    // ----------PCIe Status Signals----------
+    wire                      hotrst_exit;
+    wire                      l2_exit;
+    wire [3:0]                lane_act;
+    wire [4:0]                ltssm;
+    wire                      pme_to_sr;
+    wire                      suc_spd_neg;
+
+    // ----------PCIe RX Interface----------
+    wire                      rx_st_mask0;
+    wire [  7: 0]             rx_st_bardec0;
+    wire [ 15: 0]             rx_st_be0;
+    wire [0:0]                rx_st_sop0;
+    wire [0:0]                rx_st_eop0;
+    wire [0:0]                rx_st_err0;
+    wire [0:0]                rx_st_valid0;
+    wire [0:0]                rx_st_empty0;
+    wire                      rx_st_ready0;
+    wire [C_PCI_DATA_WIDTH-1:0] rx_st_data0;
+
+    // ----------PCIe TX Interface----------
+    wire [0:0]                   tx_st_sop0;
+    wire [0:0]                   tx_st_eop0;
+    wire [0:0]                   tx_st_err0;
+    wire [0:0]                   tx_st_valid0;
+    wire [0:0]                   tx_st_empty0;
+    wire                         tx_st_ready0;
+    wire [C_PCI_DATA_WIDTH-1:0]  tx_st_data0;
+
+    // ----------ALTGX Signals----------
+    wire                         busy;
+    wire                         busy_altgxb_reconfig;
+    wire [33:0]                  reconfig_fromgxb;
+    wire [3:0]                   reconfig_togxb;
+
+    // ----------Resets ----------
+    reg [4:0]                    rRstCtr,_rRstCtr;
+    reg [2:0]                    rRstSync,_rRstSync;
+    wire                         wSyncRst;
+    
+    always @(*) begin
+        _rRstSync = {rRstSync[1:0], ~npor};
+        _rRstCtr = rRstCtr;
+        if (rRstSync[2]) begin
+            _rRstCtr = 0;
+        end else if (~rRstCtr[4]) begin
+            _rRstCtr = rRstCtr + 1;
+        end
+    end
+    
+    always @(posedge pld_clk) begin
+        rRstSync <= _rRstSync;
+        rRstCtr <= _rRstCtr;
+    end
+
+    assign wSyncRst = ~ rRstCtr[4];
+    assign srst = wSyncRst;
+    assign crst = wSyncRst;
+
+    // ----------PLL assignments----------
+    assign inclk0 = OSC_50_BANK2;
+    assign fixedclk_serdes = clk125;
+
+    assign reconfig_clk = clk50;
+
+    // ----------PCIe Resets----------
+    assign npor = PCIE_RESET_N;
+    assign gxb_powerdown = ~ npor;
+    assign pll_powerdown = ~ npor;
+    
+    // ----------PCIe Clocks / PLLs----------
+    assign refclk = PCIE_REFCLK;
+    assign pld_clk = core_clk_out;
+    assign cal_blk_clk = reconfig_clk;
+
+    // ----------ALTGX----------
+    assign busy = busy_altgxb_reconfig;
+
+    // -------------------- BEGIN ALTERA IP INSTANTIATION  --------------------
+    ALTPLL50I50O125O250O ALTPLL50I50O125O250O_inst
+        (
+         // Outputs
+         .c0                               (clk50),
+         .c1                               (clk125),
+         .c2                               (clk250),
+         .locked                           (locked),
+         // Inputs
+         .inclk0                           (inclk0));
+
+    ALTGXPCIeGen1x8
+        altgx_inst
+            (
+             // Outputs
+             .busy                           (busy),
+             .reconfig_togxb                 (reconfig_togxb[3:0]),
+             // Inputs
+             .reconfig_clk                   (reconfig_clk),
+             .reconfig_fromgxb               (reconfig_fromgxb[33:0]));
+
+    PCIeGen1x8If64 
+        pcie_inst
+            (
+             // Outputs
+             .app_int_ack                      (app_int_ack),
+             .app_msi_ack                      (app_msi_ack),
+             .core_clk_out                     (core_clk_out),
+             .hotrst_exit                      (hotrst_exit),
+             .l2_exit                          (l2_exit),
+             .lane_act                         (lane_act[3:0]),
+             .lmi_ack                          (lmi_ack),
+             .lmi_dout                         (lmi_dout[31:0]),
+             .ltssm                            (ltssm[4:0]),
+             .rc_pll_locked                    (rc_pll_locked),
+             .reconfig_fromgxb                 (reconfig_fromgxb[33:0]),
+             .reset_status                     (reset_status),
+             .rx_st_bardec0                    (rx_st_bardec0[7:0]),
+             .rx_st_be0                        (rx_st_be0[7:0]),
+             .rx_st_data0                      (rx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+             .rx_st_eop0                       (rx_st_eop0),
+             .rx_st_err0                       (rx_st_err0),
+             .rx_st_sop0                       (rx_st_sop0),
+             .rx_st_valid0                     (rx_st_valid0),
+             .suc_spd_neg                      (suc_spd_neg),// Gen 2 successful
+             .tl_cfg_add                       (tl_cfg_add[3:0]), 
+             .tl_cfg_ctl                       (tl_cfg_ctl[31:0]),
+             .tl_cfg_ctl_wr                    (tl_cfg_ctl_wr),
+             .tl_cfg_sts                       (tl_cfg_sts[52:0]),
+             .tl_cfg_sts_wr                    (tl_cfg_sts_wr),
+             .ko_cpl_spc_vc0                   (ko_cpl_spc_vc0),
+             .tx_out0                          (PCIE_TX_OUT[0]),
+             .tx_out1                          (PCIE_TX_OUT[1]),
+             .tx_out2                          (PCIE_TX_OUT[2]),
+             .tx_out3                          (PCIE_TX_OUT[3]),
+             .tx_out4                          (PCIE_TX_OUT[4]),
+             .tx_out5                          (PCIE_TX_OUT[5]),
+             .tx_out6                          (PCIE_TX_OUT[6]),
+             .tx_out7                          (PCIE_TX_OUT[7]),
+             .tx_st_ready0                     (tx_st_ready0),
+             // Inputs
+             .app_int_sts                      (app_int_sts),
+             .app_msi_num                      (5'b00000),
+             .app_msi_req                      (app_msi_req),
+             .app_msi_tc                       (3'b000),
+             .busy_altgxb_reconfig             (busy_altgxb_reconfig),
+             .cal_blk_clk                      (cal_blk_clk),
+             .crst                             (crst),
+             .fixedclk_serdes                  (fixedclk_serdes),
+             .gxb_powerdown                    (gxb_powerdown),
+             .pll_powerdown                    (pll_powerdown),
+             .lmi_addr                         (lmi_addr[11:0]),
+             .lmi_din                          (lmi_din[31:0]),
+             .lmi_rden                         (lmi_rden),
+             .lmi_wren                         (lmi_wren),
+             .npor                             (npor),
+             .pex_msi_num                      (pex_msi_num[4:0]),
+             .pld_clk                          (pld_clk),
+             .reconfig_clk                     (reconfig_clk),
+             .reconfig_togxb                   (reconfig_togxb[3:0]),
+             .refclk                           (refclk),
+             .rx_in0                           (PCIE_RX_IN[0]),
+             .rx_in1                           (PCIE_RX_IN[1]),
+             .rx_in2                           (PCIE_RX_IN[2]),
+             .rx_in3                           (PCIE_RX_IN[3]),
+             .rx_in4                           (PCIE_RX_IN[4]),
+             .rx_in5                           (PCIE_RX_IN[5]),
+             .rx_in6                           (PCIE_RX_IN[6]),
+             .rx_in7                           (PCIE_RX_IN[7]),
+             .rx_st_ready0                     (rx_st_ready0),
+             .srst                             (srst),
+             .tx_st_data0                      (tx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+             .tx_st_eop0                       (tx_st_eop0),
+             .tx_st_err0                       (tx_st_err0),
+             .tx_st_sop0                       (tx_st_sop0),
+             .tx_st_valid0                     (tx_st_valid0));
+
+    // -------------------- END ALTERA IP INSTANTIATION  --------------------
+    // -------------------- BEGIN RIFFA INSTANTAION --------------------
+
+    // ----------RIFFA channel interface----------
+    wire [C_NUM_CHNL-1:0]        chnl_rx_clk;
+    wire [C_NUM_CHNL-1:0]        chnl_rx;
+    wire [C_NUM_CHNL-1:0]        chnl_rx_ack;
+    wire [C_NUM_CHNL-1:0]        chnl_rx_last;
+    wire [(C_NUM_CHNL*32)-1:0]   chnl_rx_len;
+    wire [(C_NUM_CHNL*31)-1:0]   chnl_rx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_ren;
+    
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_clk;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_last;
+    wire [(C_NUM_CHNL*32)-1:0]               chnl_tx_len;
+    wire [(C_NUM_CHNL*31)-1:0]               chnl_tx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_ren;
+
+    wire                                     chnl_reset;
+    wire                                     chnl_clk;
+    wire                                     rst_out;
+
+    assign chnl_clk = pld_clk;
+    assign chnl_reset = rst_out;
+    
+    riffa_wrapper_de4
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .RX_ST_READY                   (rx_st_ready0),
+         .TX_ST_DATA                    (tx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (tx_st_valid0[0:0]),
+         .TX_ST_EOP                     (tx_st_eop0[0:0]),
+         .TX_ST_SOP                     (tx_st_sop0[0:0]),
+         .TX_ST_EMPTY                   (tx_st_empty0[0:0]),
+         .APP_MSI_REQ                   (app_msi_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .RX_ST_DATA                    (rx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (rx_st_eop0[0:0]),
+         .RX_ST_SOP                     (rx_st_sop0[0:0]),
+         .RX_ST_VALID                   (rx_st_valid0[0:0]),
+         .RX_ST_EMPTY                   (rx_st_empty0[0:0]),
+         .TX_ST_READY                   (tx_st_ready0),
+         .TL_CFG_CTL                    (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (ko_cpl_spc_vc0[7:0]),
+         .KO_CPL_SPC_DATA               (ko_cpl_spc_vc0[19:8]),
+         .APP_MSI_ACK                   (app_msi_ack),
+         .PLD_CLK                       (pld_clk),
+         .RESET_STATUS                  (reset_status),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+
+    // --------------------  END RIFFA INSTANTAION --------------------
+    // --------------------  BEGIN USER CODE  --------------------
+    genvar                                   i;
+    generate
+        for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
+            // Instantiate and assign modules to RIFFA channels. Users should 
+            // replace the chnl_tester instantiation with their own core.
+            chnl_tester 
+                 #(
+                   .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                   )
+            chnl_tester_i
+                 (
+
+                  .CLK(chnl_clk),
+                  .RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
+                  // Rx interface
+                  .CHNL_RX_CLK(chnl_rx_clk[i]), 
+                  .CHNL_RX(chnl_rx[i]), 
+                  .CHNL_RX_ACK(chnl_rx_ack[i]), 
+                  .CHNL_RX_LAST(chnl_rx_last[i]), 
+                  .CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]), 
+                  .CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
+                  // Tx interface
+                  .CHNL_TX_CLK(chnl_tx_clk[i]), 
+                  .CHNL_TX(chnl_tx[i]), 
+                  .CHNL_TX_ACK(chnl_tx_ack[i]), 
+                  .CHNL_TX_LAST(chnl_tx_last[i]), 
+                  .CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]), 
+                  .CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
+                  );    
+        end
+    endgenerate
+    // --------------------  END USER CODE  --------------------
+endmodule // DE4_PCIe

fpga/altera/de4/DE4Gen1x8If64/prj/DE4Gen1x8If64.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 16:41:16  June 09, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:41:16  June 09, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "DE4Gen1x8If64"

fpga/altera/de4/DE4Gen1x8If64/prj/DE4Gen1x8If64.qsf

@@ -0,0 +1,277 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 11:42:13  March 24, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		DE4Gen1x8If64_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Stratix IV"
+set_global_assignment -name DEVICE EP4SGX230KF40C2
+set_global_assignment -name TOP_LEVEL_ENTITY DE4Gen1x8If64
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:42:13  MARCH 24, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION "14.1.0 SP0.19"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+################################################################################
+# Oscillators & External Clocks
+################################################################################
+
+set_location_assignment PIN_AC35 -to OSC_50_BANK2
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK2
+set_location_assignment PIN_AV22 -to OSC_50_BANK3
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK3
+set_location_assignment PIN_AV19 -to OSC_50_BANK4
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK4
+set_location_assignment PIN_AC6 -to OSC_50_BANK5
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK5
+set_location_assignment PIN_AB6 -to OSC_50_BANK6
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK6
+
+################################################################################
+# LED's
+################################################################################
+
+set_location_assignment PIN_V28 -to LED[0]
+set_location_assignment PIN_W28 -to LED[1]
+set_location_assignment PIN_R29 -to LED[2]
+set_location_assignment PIN_P29 -to LED[3]
+set_location_assignment PIN_N29 -to LED[4]
+set_location_assignment PIN_M29 -to LED[5]
+set_location_assignment PIN_M30 -to LED[6]
+set_location_assignment PIN_N30 -to LED[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[*]
+
+################################################################################
+# PCIE Connections
+################################################################################
+
+set_location_assignment PIN_AN38 -to PCIE_REFCLK
+set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK
+set_instance_assignment -name INPUT_TERMINATION OFF -to PCIE_REFCLK
+
+set_location_assignment PIN_AN39 -to "PCIE_REFCLK(n)"
+
+set_location_assignment PIN_V30 -to PCIE_RESET_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_RESET_N
+
+################################################################################
+#PCIE RX_IN 0
+################################################################################
+set_location_assignment PIN_AU38 -to PCIE_RX_IN[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[0]
+################################################################################
+#PCIE RX_IN 1
+################################################################################
+set_location_assignment PIN_AR38 -to PCIE_RX_IN[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[1]
+################################################################################
+#PCIE RX_IN 2
+################################################################################
+set_location_assignment PIN_AJ38 -to PCIE_RX_IN[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[2]
+################################################################################
+#PCIE RX_IN 3
+################################################################################
+set_location_assignment PIN_AG38 -to PCIE_RX_IN[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[3]
+################################################################################
+#PCIE RX_IN 4
+################################################################################
+set_location_assignment PIN_AE38 -to PCIE_RX_IN[4]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[4]
+################################################################################
+#PCIE RX_IN 5
+################################################################################
+set_location_assignment PIN_AC38 -to PCIE_RX_IN[5]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[5]
+################################################################################
+#PCIE RX_IN 6
+################################################################################
+set_location_assignment PIN_U38 -to PCIE_RX_IN[6]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[6]
+################################################################################
+#PCIE RX_IN 7
+################################################################################
+set_location_assignment PIN_R38 -to PCIE_RX_IN[7]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[7]
+################################################################################
+#PCIE TX_OUT 0
+################################################################################
+set_location_assignment PIN_AT36 -to PCIE_TX_OUT[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[0]
+################################################################################
+#PCIE TX_OUT 1
+################################################################################
+set_location_assignment PIN_AP36 -to PCIE_TX_OUT[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[1]
+################################################################################
+#PCIE TX_OUT 2
+################################################################################
+set_location_assignment PIN_AH36 -to PCIE_TX_OUT[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[2]
+################################################################################
+#PCIE TX_OUT 3
+################################################################################
+set_location_assignment PIN_AF36 -to PCIE_TX_OUT[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[3]
+################################################################################
+#PCIE TX_OUT 4
+################################################################################
+set_location_assignment PIN_AD36 -to PCIE_TX_OUT[4]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[4]
+################################################################################
+#PCIE TX_OUT 5
+################################################################################
+set_location_assignment PIN_AB36 -to PCIE_TX_OUT[5]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[5]
+################################################################################
+#PCIE TX_OUT 6
+################################################################################
+set_location_assignment PIN_T36 -to PCIE_TX_OUT[6]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[6]
+################################################################################
+#PCIE TX_OUT 7
+################################################################################
+set_location_assignment PIN_P36 -to PCIE_TX_OUT[7]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[7]
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+
+set_global_assignment -name SDC_FILE ../constr/DE4Gen1x8If64.sdc
+set_global_assignment -name VERILOG_FILE ../hdl/DE4Gen1x8If64.v
+set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de4.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ohtb.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
+set_global_assignment -name QIP_FILE ../ip/ALTGXPCIeGen1x8.qip
+set_global_assignment -name QIP_FILE ../ip/ALTPLL50I50O125O250O.qip
+set_global_assignment -name QIP_FILE ../ip/PCIeGen1x8If64.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

fpga/altera/de4/DE4Gen2x8If128/constr/DE4Gen2x8If128.sdc

@@ -0,0 +1,65 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            DE4Gen2x8If128.sdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Synopsys Design Constraints for the DE4 board.
+# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+# Oscillator clk (50 MHz Input)
+create_clock -name OSCILLATOR_CLK -period 20 [get_ports {OSC_50_BANK2}]
+
+# Refclk (100 MHz differential input)
+create_clock -period "100 MHz" -name {refclk} [get_ports {PCIE_REFCLK}]
+
+# 50 MHZ PLL Clock
+create_generated_clock -name clk50 -source [get_ports {OSC_50_BANK2}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[0]}]
+
+# 125 MHZ PLL Clock
+create_generated_clock -name clk125 -multiply_by 5 -divide_by 2 -source [get_ports {OSC_50_BANK2}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[1]}]
+
+# 250 MHZ PLL Clock
+create_generated_clock -name clk250 -multiply_by 5 -source [get_ports {OSC_50_BANK2}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[2]}]
+
+derive_pll_clocks 
+derive_clock_uncertainty
+
+
+# Imported from IP Compiler user guide
+set_clock_groups -exclusive -group [get_clocks { refclk*clkout }] -group [get_clocks { *div0*coreclkout}]
+set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }] -group [get_clocks { *central_clk_div1* }]
+

fpga/altera/de4/DE4Gen2x8If128/hdl/DE4Gen2x8If128.v

@@ -0,0 +1,402 @@
+//----------------------------------------------------------------------------
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            DE4Gen2x8If128.v
+// Version:             
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Altera Stratix IV IP Compiler for PCI Express
+//                      module and the Terasic DE4 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`timescale 1ps / 1ps
+module DE4Gen2x8If128
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Quartus IP Library
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     input                    OSC_50_BANK2,
+     input                    OSC_50_BANK3,
+     input                    OSC_50_BANK4,
+     input                    OSC_50_BANK5,
+     input                    OSC_50_BANK6,
+     input                    PCIE_RESET_N,
+     input                    PCIE_REFCLK,
+     input [C_NUM_LANES-1:0]  PCIE_RX_IN,
+     output [C_NUM_LANES-1:0] PCIE_TX_OUT,
+     output [7:0]             LED
+     );
+
+    // ----------PLL Signals----------
+    wire                      clk50;
+    wire                      clk125;
+    wire                      clk250;
+    wire                      locked;
+    wire                      inclk0;
+
+    // ----------PCIe Core Signals----------
+    // ----------PCIe Clocks----------
+    wire                      pld_clk;
+    wire                      reconfig_clk;
+    wire                      core_clk_out;
+    wire                      fixedclk_serdes;
+    wire                      refclk;
+    wire                      rc_pll_locked;
+    wire                      cal_blk_clk;
+
+    // ----------PCIe Resets----------
+    wire                      pll_powerdown;
+    wire                      reset_status;
+    wire                      crst;
+    wire                      npor;
+    wire                      srst;
+    wire                      gxb_powerdown;
+
+    // ----------PCIe Transaction layer configuration ----------
+    wire [  3: 0]             tl_cfg_add;
+    wire [ 31: 0]             tl_cfg_ctl;
+    wire                      tl_cfg_ctl_wr;
+    wire [ 52: 0]             tl_cfg_sts;
+    wire                      tl_cfg_sts_wr;
+    wire [ 19: 0]             ko_cpl_spc_vc0;
+    // ----------PCIe Interrupt Interface----------
+    wire                      app_int_ack;
+    wire                      app_msi_ack;
+    wire                      app_int_sts;
+    wire                      app_msi_req;
+
+    // ----------PCIe Status Signals----------
+    wire                      hotrst_exit;
+    wire                      l2_exit;
+    wire                      dlup_exit;
+    wire [3:0]                lane_act;
+    wire [4:0]                ltssm;
+    wire                      pme_to_sr;
+    wire                      suc_spd_neg;
+
+    // ----------PCIe RX Interface----------
+    wire                      rx_st_mask0;
+    wire [  7: 0]             rx_st_bardec0;
+    wire [ 15: 0]             rx_st_be0;
+    wire [0:0]                rx_st_sop0;
+    wire [0:0]                rx_st_eop0;
+    wire [0:0]                rx_st_err0;
+    wire [0:0]                rx_st_valid0;
+    wire [0:0]                rx_st_empty0;
+    wire                      rx_st_ready0;
+    wire [C_PCI_DATA_WIDTH-1:0] rx_st_data0;
+
+    // ----------PCIe TX Interface----------
+    wire [0:0]                  tx_st_sop0;
+    wire [0:0]                  tx_st_eop0;
+    wire [0:0]                  tx_st_err0;
+    wire [0:0]                  tx_st_valid0;
+    wire [0:0]                  tx_st_empty0;
+    wire                        tx_st_ready0;
+    wire [C_PCI_DATA_WIDTH-1:0] tx_st_data0;
+
+    // ----------ALTGX Signals----------
+    wire                        busy;
+    wire                        busy_altgxb_reconfig;
+    wire [33:0]                 reconfig_fromgxb;
+    wire [3:0]                  reconfig_togxb;
+
+    // ----------Resets ----------
+    reg [4:0]                   rPCIRstCtr=0,_rPCIRstCtr=0;
+    reg [2:0]                   rRstSync=0,_rRstSync=0;
+    wire                        wSyncRst;
+    always @(*) begin
+        _rRstSync = {rRstSync[1:0], ~npor};
+        _rPCIRstCtr = rPCIRstCtr;
+        if (rRstSync[2]) begin
+            _rPCIRstCtr = 0;
+        end else if (~rPCIRstCtr[4]) begin
+            _rPCIRstCtr = rPCIRstCtr + 1;
+        end
+    end
+    
+    always @(posedge pld_clk) begin
+        rRstSync <= _rRstSync;
+        rPCIRstCtr <= _rPCIRstCtr;
+    end
+
+    assign wSyncRst = ~ rPCIRstCtr[4];
+    assign srst = wSyncRst;
+    assign crst = wSyncRst;
+    
+    // ----------PLL assignments----------
+    assign inclk0 = OSC_50_BANK2;
+    assign fixedclk_serdes = clk125;
+    assign reconfig_clk = clk50;
+
+    // ----------PCIe Resets----------
+    assign npor = PCIE_RESET_N;
+    assign gxb_powerdown = ~ npor;
+    assign pll_powerdown = ~ npor;
+    
+    // ----------PCIe Clocks / PLLs----------
+    assign refclk = PCIE_REFCLK;
+    assign pld_clk = core_clk_out;
+    assign cal_blk_clk = reconfig_clk;
+
+    // ----------ALTGX----------
+    assign busy = busy_altgxb_reconfig;
+
+    // -------------------- BEGIN ALTERA IP INSTANTIATION  --------------------
+    ALTPLL50I50O125O250O ALTPLL50I50O125O250O_inst
+        (
+         // Outputs
+         .c0                               (clk50),
+         .c1                               (clk125),
+         .c2                               (clk250),
+         .locked                           (locked),
+         // Inputs
+         .inclk0                           (inclk0));
+
+    ALTGXPCIeGen2x8
+        altgx_inst
+            (
+             // Outputs
+             .busy                           (busy),
+             .reconfig_togxb                 (reconfig_togxb[3:0]),
+             // Inputs
+             .reconfig_clk                   (reconfig_clk),
+             .reconfig_fromgxb               (reconfig_fromgxb[33:0]));
+
+    PCIeGen2x8If128
+        pcie_inst
+            (
+             // Outputs
+             .app_int_ack                      (app_int_ack),
+             .app_msi_ack                      (app_msi_ack),
+             .core_clk_out                     (core_clk_out),
+             .hotrst_exit                      (hotrst_exit),
+             .l2_exit                          (l2_exit),
+             .dlup_exit                        (dlup_exit),
+             .lane_act                         (lane_act[3:0]),
+             .ltssm                            (ltssm[4:0]),
+             .rc_pll_locked                    (rc_pll_locked),
+             .reconfig_fromgxb                 (reconfig_fromgxb[33:0]),
+             .reset_status                     (reset_status),
+             .rx_st_bardec0                    (rx_st_bardec0[7:0]),
+             .rx_st_be0                        (rx_st_be0[7:0]),
+             .rx_st_data0                      (rx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+             .rx_st_eop0                       (rx_st_eop0),
+             .rx_st_err0                       (rx_st_err0),
+             .rx_st_sop0                       (rx_st_sop0),
+             .rx_st_empty0                     (rx_st_empty0),
+             .rx_st_valid0                     (rx_st_valid0),
+             .suc_spd_neg                      (suc_spd_neg),// Gen 2 successful
+             .tl_cfg_add                       (tl_cfg_add[3:0]), 
+             .tl_cfg_ctl                       (tl_cfg_ctl[31:0]),
+             .tl_cfg_ctl_wr                    (tl_cfg_ctl_wr),
+             .tl_cfg_sts                       (tl_cfg_sts[52:0]),
+             .tl_cfg_sts_wr                    (tl_cfg_sts_wr),
+             .ko_cpl_spc_vc0                   (ko_cpl_spc_vc0),
+             .tx_out0                          (PCIE_TX_OUT[0]),
+             .tx_out1                          (PCIE_TX_OUT[1]),
+             .tx_out2                          (PCIE_TX_OUT[2]),
+             .tx_out3                          (PCIE_TX_OUT[3]),
+             .tx_out4                          (PCIE_TX_OUT[4]),
+             .tx_out5                          (PCIE_TX_OUT[5]),
+             .tx_out6                          (PCIE_TX_OUT[6]),
+             .tx_out7                          (PCIE_TX_OUT[7]),
+             .tx_st_ready0                     (tx_st_ready0),
+             // Inputs
+             .app_int_sts                      (app_int_sts),
+             .app_msi_req                      (app_msi_req),
+             .busy_altgxb_reconfig             (busy_altgxb_reconfig),
+             .cal_blk_clk                      (cal_blk_clk),
+             .crst                             (crst),
+             .fixedclk_serdes                  (fixedclk_serdes),
+             .gxb_powerdown                    (gxb_powerdown),
+             .pll_powerdown                    (pll_powerdown),
+             .npor                             (npor),
+             .pld_clk                          (pld_clk),
+             .reconfig_clk                     (reconfig_clk),
+             .reconfig_togxb                   (reconfig_togxb[3:0]),
+             .refclk                           (refclk),
+             .rx_in0                           (PCIE_RX_IN[0]),
+             .rx_in1                           (PCIE_RX_IN[1]),
+             .rx_in2                           (PCIE_RX_IN[2]),
+             .rx_in3                           (PCIE_RX_IN[3]),
+             .rx_in4                           (PCIE_RX_IN[4]),
+             .rx_in5                           (PCIE_RX_IN[5]),
+             .rx_in6                           (PCIE_RX_IN[6]),
+             .rx_in7                           (PCIE_RX_IN[7]),
+             .rx_st_ready0                     (rx_st_ready0),
+             .srst                             (srst),
+             .tx_st_data0                      (tx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+             .tx_st_eop0                       (tx_st_eop0),
+             .tx_st_err0                       (1'b0),
+             .tx_st_sop0                       (tx_st_sop0),
+             .tx_st_empty0                     (tx_st_empty0),
+             .tx_st_valid0                     (tx_st_valid0));
+
+    // -------------------- END ALTERA IP INSTANTIATION  --------------------
+    // -------------------- BEGIN RIFFA INSTANTAION --------------------
+
+    // ----------RIFFA channel interface----------
+    wire [C_NUM_CHNL-1:0]        chnl_rx_clk;
+    wire [C_NUM_CHNL-1:0]        chnl_rx;
+    wire [C_NUM_CHNL-1:0]        chnl_rx_ack;
+    wire [C_NUM_CHNL-1:0]        chnl_rx_last;
+    wire [(C_NUM_CHNL*32)-1:0]   chnl_rx_len;
+    wire [(C_NUM_CHNL*31)-1:0]   chnl_rx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_ren;
+    
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_clk;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_last;
+    wire [(C_NUM_CHNL*32)-1:0]               chnl_tx_len;
+    wire [(C_NUM_CHNL*31)-1:0]               chnl_tx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_ren;
+
+    wire                                     chnl_reset;
+    wire                                     chnl_clk;
+    wire                                     rst_out;
+
+    assign chnl_clk = pld_clk;
+    assign chnl_reset = rst_out;
+    
+    riffa_wrapper_de4
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .RX_ST_READY                   (rx_st_ready0),
+         .TX_ST_DATA                    (tx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (tx_st_valid0[0:0]),
+         .TX_ST_EOP                     (tx_st_eop0[0:0]),
+         .TX_ST_SOP                     (tx_st_sop0[0:0]),
+         .TX_ST_EMPTY                   (tx_st_empty0[0:0]),
+         .APP_MSI_REQ                   (app_msi_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .RX_ST_DATA                    (rx_st_data0[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (rx_st_eop0[0:0]),
+         .RX_ST_SOP                     (rx_st_sop0[0:0]),
+         .RX_ST_VALID                   (rx_st_valid0[0:0]),
+         .RX_ST_EMPTY                   (rx_st_empty0[0:0]),
+         .TX_ST_READY                   (tx_st_ready0),
+         .TL_CFG_CTL                    (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER                (ko_cpl_spc_vc0[7:0]),
+         .KO_CPL_SPC_DATA                  (ko_cpl_spc_vc0[19:8]),
+         .APP_MSI_ACK                   (app_msi_ack),
+         .PLD_CLK                       (pld_clk),
+         .RESET_STATUS                  (reset_status),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+    
+    // --------------------  END RIFFA INSTANTAION --------------------
+    // --------------------  BEGIN USER CODE  --------------------
+    genvar                                   i;
+    generate
+        for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
+            // Instantiate and assign modules to RIFFA channels. Users should 
+            // replace the chnl_tester instantiation with their own core.
+            chnl_tester 
+                 #(
+                   .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                   )
+            chnl_tester_i
+                 (
+
+                  .CLK(chnl_clk),
+                  .RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
+                  // Rx interface
+                  .CHNL_RX_CLK(chnl_rx_clk[i]), 
+                  .CHNL_RX(chnl_rx[i]), 
+                  .CHNL_RX_ACK(chnl_rx_ack[i]), 
+                  .CHNL_RX_LAST(chnl_rx_last[i]), 
+                  .CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]), 
+                  .CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
+                  // Tx interface
+                  .CHNL_TX_CLK(chnl_tx_clk[i]), 
+                  .CHNL_TX(chnl_tx[i]), 
+                  .CHNL_TX_ACK(chnl_tx_ack[i]), 
+                  .CHNL_TX_LAST(chnl_tx_last[i]), 
+                  .CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]), 
+                  .CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
+                  );    
+        end
+    endgenerate
+    // --------------------  END USER CODE  --------------------
+endmodule // DE4Gen2x8If128
+

fpga/altera/de4/DE4Gen2x8If128/prj/DE4Gen2x8If128.qpf

@@ -0,0 +1,32 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.0.0 Build 200 06/17/2014 SJ Full Version
+# Date created = 14:57:09  July 21, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "14.0"
+DATE = "14:57:09  July 21, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "DE4Gen2x8If128"
+PROJECT_REVISION = "WAR"

fpga/altera/de4/DE4Gen2x8If128/prj/DE4Gen2x8If128.qsf

@@ -0,0 +1,275 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 11:42:13  March 24, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		DE4Gen2x8If128_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Stratix IV"
+set_global_assignment -name DEVICE EP4SGX230KF40C2
+set_global_assignment -name TOP_LEVEL_ENTITY DE4Gen2x8If128
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:42:13  MARCH 24, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION "14.1.0 SP0.19"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+################################################################################
+# Oscillators & External Clocks
+################################################################################
+
+set_location_assignment PIN_AC35 -to OSC_50_BANK2
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK2
+set_location_assignment PIN_AV22 -to OSC_50_BANK3
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK3
+set_location_assignment PIN_AV19 -to OSC_50_BANK4
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK4
+set_location_assignment PIN_AC6 -to OSC_50_BANK5
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK5
+set_location_assignment PIN_AB6 -to OSC_50_BANK6
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK6
+################################################################################
+# LED's
+################################################################################
+
+set_location_assignment PIN_V28 -to LED[0]
+set_location_assignment PIN_W28 -to LED[1]
+set_location_assignment PIN_R29 -to LED[2]
+set_location_assignment PIN_P29 -to LED[3]
+set_location_assignment PIN_N29 -to LED[4]
+set_location_assignment PIN_M29 -to LED[5]
+set_location_assignment PIN_M30 -to LED[6]
+set_location_assignment PIN_N30 -to LED[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[*]
+
+################################################################################
+# PCIE Connections
+################################################################################
+
+
+set_location_assignment PIN_AN38 -to PCIE_REFCLK
+set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK
+set_instance_assignment -name INPUT_TERMINATION OFF -to PCIE_REFCLK
+
+set_location_assignment PIN_AN39 -to "PCIE_REFCLK(n)"
+
+set_location_assignment PIN_V30 -to PCIE_RESET_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_RESET_N
+
+################################################################################
+#PCIE RX_IN 0
+################################################################################
+set_location_assignment PIN_AU38 -to PCIE_RX_IN[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[0]
+################################################################################
+#PCIE RX_IN 1
+################################################################################
+set_location_assignment PIN_AR38 -to PCIE_RX_IN[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[1]
+################################################################################
+#PCIE RX_IN 2
+################################################################################
+set_location_assignment PIN_AJ38 -to PCIE_RX_IN[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[2]
+################################################################################
+#PCIE RX_IN 3
+################################################################################
+set_location_assignment PIN_AG38 -to PCIE_RX_IN[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[3]
+################################################################################
+#PCIE RX_IN 4
+################################################################################
+set_location_assignment PIN_AE38 -to PCIE_RX_IN[4]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[4]
+################################################################################
+#PCIE RX_IN 5
+################################################################################
+set_location_assignment PIN_AC38 -to PCIE_RX_IN[5]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[5]
+################################################################################
+#PCIE RX_IN 6
+################################################################################
+set_location_assignment PIN_U38 -to PCIE_RX_IN[6]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[6]
+################################################################################
+#PCIE RX_IN 7
+################################################################################
+set_location_assignment PIN_R38 -to PCIE_RX_IN[7]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_IN[7]
+################################################################################
+#PCIE TX_OUT 0
+################################################################################
+set_location_assignment PIN_AT36 -to PCIE_TX_OUT[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[0]
+################################################################################
+#PCIE TX_OUT 1
+################################################################################
+set_location_assignment PIN_AP36 -to PCIE_TX_OUT[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[1]
+################################################################################
+#PCIE TX_OUT 2
+################################################################################
+set_location_assignment PIN_AH36 -to PCIE_TX_OUT[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[2]
+################################################################################
+#PCIE TX_OUT 3
+################################################################################
+set_location_assignment PIN_AF36 -to PCIE_TX_OUT[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[3]
+################################################################################
+#PCIE TX_OUT 4
+################################################################################
+set_location_assignment PIN_AD36 -to PCIE_TX_OUT[4]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[4]
+################################################################################
+#PCIE TX_OUT 5
+################################################################################
+set_location_assignment PIN_AB36 -to PCIE_TX_OUT[5]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[5]
+################################################################################
+#PCIE TX_OUT 6
+################################################################################
+set_location_assignment PIN_T36 -to PCIE_TX_OUT[6]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[6]
+################################################################################
+#PCIE TX_OUT 7
+################################################################################
+set_location_assignment PIN_P36 -to PCIE_TX_OUT[7]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_OUT[7]
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name SDC_FILE ../constr/DE4Gen2x8If128.sdc
+set_global_assignment -name VERILOG_FILE ../hdl/DE4Gen2x8If128.v
+set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de4.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ohtb.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
+set_global_assignment -name QIP_FILE ../ip/ALTGXPCIeGen2x8.qip
+set_global_assignment -name QIP_FILE ../ip/ALTPLL50I50O125O250O.qip
+set_global_assignment -name QIP_FILE ../ip/PCIeGen2x8If128.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

fpga/altera/de4/riffa_wrapper_de4.v

@@ -0,0 +1,615 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            riffa_wrapper_de4.v
+// Version:             1.00a
+// Verilog Standard:    Verilog-2001
+// Description:         Wrapper file for all riffa logic for Altera DE4 boards
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`include "ultrascale.vh"
+`include "functions.vh"
+`timescale 1ps / 1ps
+module riffa_wrapper_de4
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Bit-Width from Quartus IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     // Interface: Altera RX 
+     input [C_PCI_DATA_WIDTH-1:0]                 RX_ST_DATA,
+     input [0:0]                                  RX_ST_EOP,
+     input [0:0]                                  RX_ST_SOP,
+     input [0:0]                                  RX_ST_VALID,
+     output                                       RX_ST_READY,
+     input [0:0]                                  RX_ST_EMPTY,
+
+     // Interface: Altera TX
+     output [C_PCI_DATA_WIDTH-1:0]                TX_ST_DATA,
+     output [0:0]                                 TX_ST_VALID,
+     input                                        TX_ST_READY,
+     output [0:0]                                 TX_ST_EOP,
+     output [0:0]                                 TX_ST_SOP,
+     output [0:0]                                 TX_ST_EMPTY,
+
+     // Interface: Altera Config
+     input [`SIG_CFG_CTL_W-1:0]                   TL_CFG_CTL,
+     input [`SIG_CFG_ADD_W-1:0]                   TL_CFG_ADD,
+     input [`SIG_CFG_STS_W-1:0]                   TL_CFG_STS,
+
+     // Interface: Altera Flow Control
+     input [`SIG_KO_CPLH_W-1:0]                   KO_CPL_SPC_HEADER,
+     input [`SIG_KO_CPLD_W-1:0]                   KO_CPL_SPC_DATA,
+    
+     // Interface: Altera Interrupt
+     input                                        APP_MSI_ACK,
+     output                                       APP_MSI_REQ,
+
+     // Interface: Altera CLK/RESET
+     input                                        PLD_CLK,
+     input                                        RESET_STATUS,
+    
+
+     // RIFFA Interface Signals
+     output                                       RST_OUT,
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_CLK, // Channel read clock
+     output [C_NUM_CHNL-1:0]                      CHNL_RX, // Channel read receive signal
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_ACK, // Channel read received signal
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_LAST, // Channel last read
+     output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
+     output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
+     output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   CHNL_RX_DATA, // Channel read data
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_DATA_VALID, // Channel read data valid
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_DATA_REN, // Channel read data has been recieved
+
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_CLK, // Channel write clock
+     input [C_NUM_CHNL-1:0]                       CHNL_TX, // Channel write receive signal
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_ACK, // Channel write acknowledgement signal
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_LAST, // Channel last write
+     input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]  CHNL_TX_LEN, // Channel write length (in 32 bit words)
+     input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]  CHNL_TX_OFF, // Channel write offset
+     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]    CHNL_TX_DATA, // Channel write data
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_DATA_VALID, // Channel write data valid
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_DATA_REN // Channel write data has been recieved
+
+     );
+    localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
+    localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
+    localparam C_VENDOR = "ALTERA";
+
+    localparam C_ALTERA_TX_READY_LATENCY = 2;
+    localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
+    localparam C_PIPELINE_OUTPUT = 1;
+    localparam C_PIPELINE_INPUT = 1;
+
+    wire                                          clk;
+    wire                                          rst_in;
+
+    // Interface: RXC Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxc_data;
+    wire                                          rxc_data_valid;
+    wire                                          rxc_data_start_flag;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxc_data_word_enable;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxc_meta_fdwbe;
+    wire                                          rxc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxc_meta_ldwbe;
+    wire [`SIG_TAG_W-1:0]                         rxc_meta_tag;
+    wire [`SIG_LOWADDR_W-1:0]                     rxc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        rxc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         rxc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     rxc_meta_bytes_remaining;
+    wire [`SIG_CPLID_W-1:0]                       rxc_meta_completer_id;
+    wire                                          rxc_meta_ep;
+
+    // Interface: RXR Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxr_data;
+    wire                                          rxr_data_valid;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxr_data_word_enable;
+    wire                                          rxr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxr_meta_fdwbe;
+    wire                                          rxr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxr_meta_ldwbe;
+    wire [`SIG_TC_W-1:0]                          rxr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        rxr_meta_attr;
+    wire [`SIG_TAG_W-1:0]                         rxr_meta_tag;
+    wire [`SIG_TYPE_W-1:0]                        rxr_meta_type;
+    wire [`SIG_ADDR_W-1:0]                        rxr_meta_addr;
+    wire [`SIG_BARDECODE_W-1:0]                   rxr_meta_bar_decoded;
+    wire [`SIG_REQID_W-1:0]                       rxr_meta_requester_id;
+    wire [`SIG_LEN_W-1:0]                         rxr_meta_length;
+    wire                                          rxr_meta_ep;
+    
+    // interface: TXC Engine
+    wire                                          txc_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txc_data;
+    wire                                          txc_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_start_offset;
+    wire                                          txc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_end_offset;
+    wire                                          txc_data_ready;
+
+    wire                                          txc_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txc_meta_fdwbe;
+    wire [`SIG_LBE_W-1:0]                         txc_meta_ldwbe;
+    wire [`SIG_LOWADDR_W-1:0]                     txc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        txc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         txc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     txc_meta_byte_count;
+    wire [`SIG_TAG_W-1:0]                         txc_meta_tag;
+    wire [`SIG_REQID_W-1:0]                       txc_meta_requester_id;
+    wire [`SIG_TC_W-1:0]                          txc_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txc_meta_attr;
+    wire                                          txc_meta_ep;
+    wire                                          txc_meta_ready;
+    wire                                          txc_sent;
+
+    // Interface: TXR Engine
+    wire                                          txr_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txr_data;
+    wire                                          txr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_start_offset;
+    wire                                          txr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_end_offset;
+    wire                                          txr_data_ready;
+
+    wire                                          txr_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txr_meta_fdwbe; 
+    wire [`SIG_LBE_W-1:0]                         txr_meta_ldwbe;
+    wire [`SIG_ADDR_W-1:0]                        txr_meta_addr;
+    wire [`SIG_LEN_W-1:0]                         txr_meta_length;
+    wire [`SIG_TAG_W-1:0]                         txr_meta_tag;
+    wire [`SIG_TC_W-1:0]                          txr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txr_meta_attr;
+    wire [`SIG_TYPE_W-1:0]                        txr_meta_type;
+    wire                                          txr_meta_ep;
+    wire                                          txr_meta_ready;
+    wire                                          txr_sent;
+
+    // Classic Interface Wires
+    wire                                          wRxTlpReady;
+    wire [C_PCI_DATA_WIDTH-1:0]                   wRxTlp;
+    wire                                          wRxTlpEndFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wRxTlpEndOffset;
+    wire                                          wRxTlpStartFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wRxTlpStartOffset;
+    wire                                          wRxTlpValid;
+    wire [`SIG_BARDECODE_W-1:0]                   wRxTlpBarDecode;
+    
+    wire                                          wTxTlpReady;
+    wire [C_PCI_DATA_WIDTH-1:0]                   wTxTlp;
+    wire                                          wTxTlpEndFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wTxTlpEndOffset;
+    wire                                          wTxTlpStartFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wTxTlpStartOffset;
+    wire                                          wTxTlpValid;
+    
+    // Unconnected Wires (Used in ultrascale interface)
+    // Interface: RQ (TXC)
+    wire                                          s_axis_rq_tlast_nc;
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_rq_tdata_nc;
+    wire [`SIG_RQ_TUSER_W-1:0]                    s_axis_rq_tuser_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_rq_tkeep_nc;
+    wire                                          s_axis_rq_tready_nc = 0;
+    wire                                          s_axis_rq_tvalid_nc;
+    // Interface: RC (RXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_rc_tdata_nc = 0;
+    wire [`SIG_RC_TUSER_W-1:0]                    m_axis_rc_tuser_nc = 0;
+    wire                                          m_axis_rc_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_rc_tkeep_nc = 0;
+    wire                                          m_axis_rc_tvalid_nc = 0;
+    wire                                          m_axis_rc_tready_nc;
+    // Interface: CQ (RXR)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_cq_tdata_nc = 0;
+    wire [`SIG_CQ_TUSER_W-1:0]                    m_axis_cq_tuser_nc = 0;
+    wire                                          m_axis_cq_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_cq_tkeep_nc = 0;
+    wire                                          m_axis_cq_tvalid_nc = 0;
+    wire                                          m_axis_cq_tready_nc = 0;
+    // Interface: CC (TXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_cc_tdata_nc;
+    wire [`SIG_CC_TUSER_W-1:0]                    s_axis_cc_tuser_nc;
+    wire                                          s_axis_cc_tlast_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_cc_tkeep_nc;
+    wire                                          s_axis_cc_tvalid_nc;
+    wire                                          s_axis_cc_tready_nc = 0;
+
+    // Interface: Configuration
+    wire                                          config_bus_master_enable;
+    wire [`SIG_CPLID_W-1:0]                       config_completer_id;
+    wire                                          config_cpl_boundary_sel;
+    wire                                          config_interrupt_msienable;
+    wire [`SIG_LINKRATE_W-1:0]                    config_link_rate;
+    wire [`SIG_LINKWIDTH_W-1:0]                   config_link_width;
+    wire [`SIG_MAXPAYLOAD_W-1:0]                  config_max_payload_size;
+    wire [`SIG_MAXREAD_W-1:0]                     config_max_read_request_size;
+    wire [`SIG_FC_CPLD_W-1:0]                     config_max_cpl_data;
+    wire [`SIG_FC_CPLH_W-1:0]                     config_max_cpl_hdr;
+
+    wire                                          intr_msi_request;
+    wire                                          intr_msi_rdy;
+
+    genvar                                        chnl;
+
+    assign clk = PLD_CLK;
+    assign rst_in = RESET_STATUS;
+
+    translation_altera
+        #(
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH))
+    trans
+        (
+         // Outputs
+         .RX_TLP                            (wRxTlp[C_PCI_DATA_WIDTH-1:0]),
+         .RX_TLP_VALID                      (wRxTlpValid),
+         .RX_TLP_START_FLAG                 (wRxTlpStartFlag),
+         .RX_TLP_START_OFFSET               (wRxTlpStartOffset[`SIG_OFFSET_W-1:0]),
+         .RX_TLP_END_FLAG                   (wRxTlpEndFlag),
+         .RX_TLP_END_OFFSET                 (wRxTlpEndOffset[`SIG_OFFSET_W-1:0]),
+         .RX_TLP_BAR_DECODE                 (wRxTlpBarDecode[`SIG_BARDECODE_W-1:0]),
+         .TX_TLP_READY                      (wTxTlpReady),
+         .CONFIG_COMPLETER_ID               (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE          (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH                 (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE                  (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE      (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE           (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE        (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL           (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA               (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR                (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+         .INTR_MSI_RDY                      (intr_msi_rdy),
+         // Inputs
+         .CLK                               (clk),
+         .RST_IN                            (rst_in),
+         .RX_TLP_READY                      (wRxTlpReady),
+         .TX_TLP                            (wTxTlp[C_PCI_DATA_WIDTH-1:0]),
+         .TX_TLP_VALID                      (wTxTlpValid),
+         .TX_TLP_START_FLAG                 (wTxTlpStartFlag),
+         .TX_TLP_START_OFFSET               (wTxTlpStartOffset[`SIG_OFFSET_W-1:0]),
+         .TX_TLP_END_FLAG                   (wTxTlpEndFlag),
+         .TX_TLP_END_OFFSET                 (wTxTlpEndOffset[`SIG_OFFSET_W-1:0]),
+         .INTR_MSI_REQUEST                  (intr_msi_request),
+         /*AUTOINST*/
+         // Outputs
+         .RX_ST_READY                   (RX_ST_READY),
+         .TX_ST_DATA                    (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (TX_ST_VALID[0:0]),
+         .TX_ST_EOP                     (TX_ST_EOP[0:0]),
+         .TX_ST_SOP                     (TX_ST_SOP[0:0]),
+         .TX_ST_EMPTY                   (TX_ST_EMPTY[0:0]),
+         .APP_MSI_REQ                   (APP_MSI_REQ),
+         // Inputs
+         .RX_ST_DATA                    (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (RX_ST_EOP[0:0]),
+         .RX_ST_SOP                     (RX_ST_SOP[0:0]),
+         .RX_ST_VALID                   (RX_ST_VALID[0:0]),
+         .RX_ST_EMPTY                   (RX_ST_EMPTY[0:0]),
+         .TX_ST_READY                   (TX_ST_READY),
+         .TL_CFG_CTL                    (TL_CFG_CTL[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (TL_CFG_ADD[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (TL_CFG_STS[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (KO_CPL_SPC_HEADER[`SIG_FC_CPLH_W-1:0]),
+         .KO_CPL_SPC_DATA               (KO_CPL_SPC_DATA[`SIG_FC_CPLD_W-1:0]),
+         .APP_MSI_ACK                   (APP_MSI_ACK));
+
+    engine_layer
+        #(// Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_BYTES/4),
+          .C_VENDOR                     (C_VENDOR))
+    engine_layer_inst
+        (// Outputs
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+         // Unconnected Outputs
+         .TX_TLP                        (wTxTlp),
+         .TX_TLP_VALID                  (wTxTlpValid),
+         .TX_TLP_START_FLAG             (wTxTlpStartFlag),
+         .TX_TLP_START_OFFSET           (wTxTlpStartOffset),
+         .TX_TLP_END_FLAG               (wTxTlpEndFlag),
+         .TX_TLP_END_OFFSET             (wTxTlpEndOffset),
+
+         .RX_TLP_READY                  (wRxTlpReady),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+         // Unconnected Inputs
+         .RX_TLP                        (wRxTlp),
+         .RX_TLP_VALID                  (wRxTlpValid),
+         .RX_TLP_START_FLAG             (wRxTlpStartFlag),
+         .RX_TLP_START_OFFSET           (wRxTlpStartOffset),
+         .RX_TLP_END_FLAG               (wRxTlpEndFlag),
+         .RX_TLP_END_OFFSET             (wRxTlpEndOffset),
+         .RX_TLP_BAR_DECODE             (wRxTlpBarDecode),
+
+         .TX_TLP_READY                  (wTxTlpReady),
+         // Outputs
+         .M_AXIS_CQ_TREADY              (m_axis_cq_tready_nc),
+         .M_AXIS_RC_TREADY              (m_axis_rc_tready_nc),
+         .S_AXIS_CC_TVALID              (s_axis_cc_tvalid_nc),
+         .S_AXIS_CC_TLAST               (s_axis_cc_tlast_nc),
+         .S_AXIS_CC_TDATA               (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (s_axis_rq_tvalid_nc),
+         .S_AXIS_RQ_TLAST               (s_axis_rq_tlast_nc),
+         .S_AXIS_RQ_TDATA               (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (m_axis_cq_tvalid_nc),
+         .M_AXIS_CQ_TLAST               (m_axis_cq_tlast_nc),
+         .M_AXIS_CQ_TDATA               (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (m_axis_rc_tvalid_nc),
+         .M_AXIS_RC_TLAST               (m_axis_rc_tlast_nc),
+         .M_AXIS_RC_TDATA               (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (s_axis_cc_tready_nc),
+         .S_AXIS_RQ_TREADY              (s_axis_rq_tready_nc)
+         /*AUTOINST*/);
+
+    riffa
+        #(.C_TAG_WIDTH                  (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_MAX_READ_REQ_BYTES         (C_MAX_READ_REQ_BYTES),
+          .C_VENDOR                     (C_VENDOR),
+          .C_FPGA_NAME                  (C_FPGA_NAME))
+    riffa_inst
+        (// Outputs
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+
+         .INTR_MSI_REQUEST              (intr_msi_request),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),         
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE      (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH             (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE              (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE  (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE       (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE    (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL       (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA           (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR            (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+        
+         .INTR_MSI_RDY                  (intr_msi_rdy),
+
+         /*AUTOINST*/
+         // Outputs
+         .RST_OUT                       (RST_OUT),
+         .CHNL_RX                       (CHNL_RX[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_RX_OFF                   (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_RX_DATA                  (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
+         // Inputs
+         .CHNL_RX_CLK                   (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (CHNL_TX[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_TX_OFF                   (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_TX_DATA                  (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("../../engine/" "../../riffa/" "../../trans")
+// End:
+

fpga/altera/de5/DE5Gen1x8If64/constr/DE5Gen1x8If64.sdc

@@ -0,0 +1,95 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            DE5Gen1x8If64.sdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Synopsys Design Constraints for the DE5 board.
+# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}]
+create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}]
+
+################################################################################
+# 13.1 Workround for http://www.altera.com/support/kdb/solutions/rd12162013_581.html?GSA_pos=1&WT.oss_r=1&WT.oss=adce_off_r
+################################################################################
+
+# set_false_path -to [get_registers *|*.adce_off_r[0]]
+# set_false_path -to [get_registers *|*.adce_on_rr[0]]
+# set_false_path -to [get_registers *|reset_sync_pldclk_r[*]]
+
+################################################################################
+# End Workround 
+################################################################################
+
+derive_pll_clocks -create_base_clocks
+derive_clock_uncertainty
+
+################################################################################
+# Imports from Example Design
+################################################################################
+
+######################################################################
+# HIP Soft reset controller SDC constraints (Gen 3 only)
+set_false_path -to   [get_registers *altpcie_rs_serdes|fifo_err_sync_r[0]]
+set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*]
+
+# HIP testin pins SDC constraints
+set_false_path -from [get_pins -compatibility_mode *hip_ctrl*]
+
+######################################################################
+# Constraints for CV SIG asynchonous logic
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|test_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqout[*]}]
+                                                                                                                                                
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqber[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_lf[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_fs[*]}]

fpga/altera/de5/DE5Gen1x8If64/hdl/DE5Gen1x8If64.v

@@ -0,0 +1,523 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            DE5Gen1x8If64
+// Version:             
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Altera Stratix V Hard IP for PCI Express
+//                      module and the Terasic DE5 net Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`timescale 1ps / 1ps
+module DE5Gen1x8If64
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Quartus IP Library
+      parameter C_PCI_DATA_WIDTH = 64,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      )
+    (
+     // ----------LEDs----------
+     output [7:0]             LED,
+
+     // ----------PCIE----------
+     input                    PCIE_RESET_N,
+     input                    PCIE_REFCLK,
+
+     // ----------PCIE Serial RX----------
+     input [C_NUM_LANES-1:0]  PCIE_RX_IN,
+
+     // ----------PCIE Serial TX----------
+     output [C_NUM_LANES-1:0] PCIE_TX_OUT,
+
+     // ----------Oscillators----------
+     input                    OSC_BANK3D_50MHZ
+     );
+
+    wire                      npor;
+    wire                      pin_perst;
+
+    // ----------LMI Interface----------
+    wire [11:0]               lmi_addr;
+    wire [31:0]               lmi_din;
+    wire                      lmi_rden;
+    wire                      lmi_wren;
+    wire                      lmi_ack;
+    wire [31:0]               lmi_dout;
+
+    // ----------TL Config interface----------
+    wire [3:0]                tl_cfg_add;
+    wire [31:0]               tl_cfg_ctl;
+    wire [52:0]               tl_cfg_sts;
+
+    // ----------Rx/TX Interfaces----------
+    wire [0:0]                rx_st_sop;
+    wire [0:0]                rx_st_eop;
+    wire [0:0]                rx_st_err;
+    wire [0:0]                rx_st_valid;
+    wire [0:0]                rx_st_empty;
+    wire                      rx_st_ready;
+    wire [63:0]               rx_st_data;
+
+    wire [7:0]                rx_st_bar;
+    wire                      rx_st_mask;
+
+    wire [0:0]                tx_st_sop;
+    wire [0:0]                tx_st_eop;
+    wire [0:0]                tx_st_err;
+    wire [0:0]                tx_st_valid;
+    wire [0:0]                tx_st_empty;
+    wire                      tx_st_ready;
+    wire [63:0]               tx_st_data;
+
+    // ----------Clocks----------
+    wire                      pld_clk;
+    wire                      coreclkout_hip;
+    wire                      refclk;
+    wire                      pld_core_ready;
+    wire                      reset_status;
+    wire                      serdes_pll_locked;
+    wire                      pld_clk_inuse;
+
+    // ----------Reconfiguration busses----------
+    wire [699:0]              reconfig_to_xcvr;
+    wire [505:0]              reconfig_from_xcvr;
+
+    // ----------Interrupt Interfaces----------
+    wire                      app_int_sts;
+    wire [4:0]                app_msi_num;
+    wire                      app_msi_req;
+    wire [2:0]                app_msi_tc;
+    wire                      app_int_ack;
+    wire                      app_msi_ack;
+
+    // ----------Link status signals----------
+    wire                      derr_cor_ext_rcv;
+    wire                      derr_cor_ext_rpl;
+    wire                      derr_rpl;
+    wire                      dlup;
+    wire                      dlup_exit;
+    wire                      ev128ns;
+    wire                      ev1us;
+    wire                      hotrst_exit;
+    wire [3:0]                int_status;
+    wire                      l2_exit;
+    wire [3:0]                lane_act;
+    wire [4:0]                ltssmstate;
+    wire                      rx_par_err;
+    wire [1:0]                tx_par_err;
+    wire                      cfg_par_err;
+    wire [1:0]                currentspeed;
+    wire [7:0]                ko_cpl_spc_header;
+    wire [11:0]               ko_cpl_spc_data;
+
+    // ----------Link Status Signals (Driver)----------
+    wire                      derr_cor_ext_rcv_drv;
+    wire                      derr_cor_ext_rpl_drv;
+    wire                      derr_rpl_drv;
+    wire                      dlup_drv;
+    wire                      dlup_exit_drv;
+    wire                      ev128ns_drv;
+    wire                      ev1us_drv;
+    wire                      hotrst_exit_drv;
+    wire [3:0]                int_status_drv;
+    wire                      l2_exit_drv;
+    wire [3:0]                lane_act_drv;
+    wire [4:0]                ltssmstate_drv;
+    wire                      rx_par_err_drv;
+    wire [1:0]                tx_par_err_drv;
+    wire                      cfg_par_err_drv;
+    wire [7:0]                ko_cpl_spc_header_drv;
+    wire [11:0]               ko_cpl_spc_data_drv;
+
+
+    // ----------Reconfiguration Controller signals----------
+    wire                      reconfig_busy;
+    wire                      mgmt_clk_clk;
+    wire                      mgmt_rst_reset;
+
+    wire [6:0]                reconfig_mgmt_address;
+    wire                      reconfig_mgmt_read;
+    wire [31:0]               reconfig_mgmt_readdata;
+    wire                      reconfig_mgmt_waitrequest;
+    wire                      reconfig_mgmt_write;
+    wire [31:0]               reconfig_mgmt_writedata;
+
+    // ----------Reconfiguration Driver signals----------
+    wire                      reconfig_xcvr_clk;
+    wire                      reconfig_xcvr_rst;
+
+    wire [7:0]                rx_in;
+    wire [7:0]                tx_out;
+
+    // ----------Serial interfaces----------
+    assign rx_in = PCIE_RX_IN;
+    assign PCIE_TX_OUT = tx_out;
+
+    // ----------Clocks----------
+    assign pld_clk = coreclkout_hip;
+    assign mgmt_clk_clk = PCIE_REFCLK;
+    assign reconfig_xcvr_clk = PCIE_REFCLK;
+    assign refclk = PCIE_REFCLK;
+    assign pld_core_ready = serdes_pll_locked;
+    
+    // ----------Resets----------
+    assign reconfig_xcvr_rst = 1'b0;
+    assign mgmt_rst_reset = 1'b0;
+    assign pin_perst = PCIE_RESET_N;
+    assign npor = PCIE_RESET_N;
+
+    // ----------LED's----------
+    assign LED[7:0] = 8'hff;
+
+    // -------------------- BEGIN ALTERA IP INSTANTIATION  --------------------
+    // Transciever driver (Required for Gen1)
+    altpcie_reconfig_driver 
+        #(.number_of_reconfig_interfaces(10),
+          .gen123_lane_rate_mode_hwtcl("Gen1 (2.5 Gbps)"), // This must be changed between generations
+          .INTENDED_DEVICE_FAMILY("Stratix V"))
+    XCVRDriverGen1x8_inst
+        (
+         // Outputs
+         .reconfig_mgmt_address            (reconfig_mgmt_address[6:0]),
+         .reconfig_mgmt_read               (reconfig_mgmt_read),
+         .reconfig_mgmt_write              (reconfig_mgmt_write),
+         .reconfig_mgmt_writedata          (reconfig_mgmt_writedata[31:0]),
+        
+         // Inputs
+         .pld_clk                          (pld_clk),
+        
+         .reconfig_xcvr_rst                (reconfig_xcvr_rst),
+         .reconfig_mgmt_readdata           (reconfig_mgmt_readdata[31:0]),
+         .reconfig_mgmt_waitrequest        (reconfig_mgmt_waitrequest),
+         .reconfig_xcvr_clk                (reconfig_xcvr_clk),
+         .reconfig_busy                    (reconfig_busy),
+
+         // Link Status signals
+         .derr_cor_ext_rcv_drv             (derr_cor_ext_rcv_drv),
+         .derr_cor_ext_rpl_drv             (derr_cor_ext_rpl_drv),
+         .derr_rpl_drv                     (derr_rpl_drv),
+         .dlup_drv                         (dlup_drv),
+         .dlup_exit_drv                    (dlup_exit_drv),
+         .ev128ns_drv                      (ev128ns_drv),
+         .ev1us_drv                        (ev1us_drv),
+         .hotrst_exit_drv                  (hotrst_exit_drv),
+         .int_status_drv                   (int_status_drv[3:0]),
+         .l2_exit_drv                      (l2_exit_drv),
+         .lane_act_drv                     (lane_act_drv[3:0]),
+         .ltssmstate_drv                   (ltssmstate_drv[4:0]),
+         .rx_par_err_drv                   (rx_par_err_drv),
+         .tx_par_err_drv                   (tx_par_err_drv[1:0]),
+         .cfg_par_err_drv                  (cfg_par_err_drv),
+         .ko_cpl_spc_header_drv            (ko_cpl_spc_header_drv[7:0]),
+         .ko_cpl_spc_data_drv              (ko_cpl_spc_data_drv[11:0]),
+         .currentspeed                     (currentspeed[1:0]));
+
+    assign derr_cor_ext_rcv_drv = derr_cor_ext_rcv;
+    assign derr_cor_ext_rpl_drv = derr_cor_ext_rpl;
+    assign derr_rpl_drv = derr_rpl;
+    assign dlup_drv = dlup;
+    assign dlup_exit_drv = dlup_exit;
+    assign ev128ns_drv = ev128ns;
+    assign ev1us_drv = ev1us;
+    assign hotrst_exit_drv = hotrst_exit;
+    assign int_status_drv = int_status;
+    assign l2_exit_drv = l2_exit;
+    assign lane_act_drv = lane_act;
+    assign ltssmstate_drv = ltssmstate;
+    assign rx_par_err_drv = rx_par_err;
+    assign tx_par_err_drv = tx_par_err;
+    assign cfg_par_err_drv = cfg_par_err;
+    assign ko_cpl_spc_header_drv = ko_cpl_spc_header;
+    assign ko_cpl_spc_data_drv = ko_cpl_spc_data;
+
+    XCVRCtrlGen1x8 XCVRCtrlGen1x8_inst
+        (
+         // Outputs
+         .reconfig_busy                    (reconfig_busy),
+         .reconfig_mgmt_readdata           (reconfig_mgmt_readdata[31:0]),
+         .reconfig_mgmt_waitrequest        (reconfig_mgmt_waitrequest),
+         .reconfig_to_xcvr                 (reconfig_to_xcvr[699:0]),
+         // Inputs
+         .mgmt_clk_clk                     (mgmt_clk_clk),
+         .mgmt_rst_reset                   (mgmt_rst_reset),
+         .reconfig_mgmt_address            (reconfig_mgmt_address[6:0]),
+         .reconfig_mgmt_read               (reconfig_mgmt_read),
+         .reconfig_mgmt_write              (reconfig_mgmt_write),
+         .reconfig_mgmt_writedata          (reconfig_mgmt_writedata[31:0]),
+         .reconfig_from_xcvr               (reconfig_from_xcvr[459:0]));
+
+
+    // PCIE Core
+    PCIeGen1x8If64 PCIeGen1x8If64_inst
+        (
+         // Outputs
+         // Local Management Interface
+         .lmi_ack                          (lmi_ack),
+         .lmi_dout                         (lmi_dout[31:0]),
+         .tl_cfg_add                       (tl_cfg_add[3:0]),
+         .tl_cfg_ctl                       (tl_cfg_ctl[31:0]),
+         .tl_cfg_sts                       (tl_cfg_sts[52:0]),
+         
+         // RX Interface      
+         .rx_st_sop                        (rx_st_sop[0:0]),
+         .rx_st_eop                        (rx_st_eop[0:0]),
+         .rx_st_err                        (rx_st_err[0:0]),
+         .rx_st_valid                      (rx_st_valid[0:0]),
+         .rx_st_data                       (rx_st_data[63:0]),
+         .rx_st_bar                        (rx_st_bar[7:0]),
+         // TX Interface      
+         .tx_st_ready                      (tx_st_ready),
+         
+         .coreclkout_hip                   (coreclkout_hip),
+         .reset_status                     (reset_status),
+         .serdes_pll_locked                (serdes_pll_locked),
+         .pld_clk_inuse                    (pld_clk_inuse),
+
+         // Reconfiguration Interface
+         .reconfig_from_xcvr               (reconfig_from_xcvr[459:0]),
+         
+         .tx_out0                          (tx_out[0]),
+         .tx_out1                          (tx_out[1]),
+         .tx_out2                          (tx_out[2]),
+         .tx_out3                          (tx_out[3]),
+         .tx_out4                          (tx_out[4]),
+         .tx_out5                          (tx_out[5]),
+         .tx_out6                          (tx_out[6]),
+         .tx_out7                          (tx_out[7]),
+
+         .app_int_ack                      (app_int_ack),
+         .app_msi_ack                      (app_msi_ack),
+
+         // Link status signals
+         .derr_cor_ext_rcv                 (derr_cor_ext_rcv),
+         .derr_cor_ext_rpl                 (derr_cor_ext_rpl),
+         .derr_rpl                         (derr_rpl),
+         .dlup                             (dlup),
+         .dlup_exit                        (dlup_exit),
+         .ev128ns                          (ev128ns),
+         .ev1us                            (ev1us),
+         .hotrst_exit                      (hotrst_exit),
+         .int_status                       (int_status[3:0]),
+         .l2_exit                          (l2_exit),
+         .lane_act                         (lane_act[3:0]),
+         .ltssmstate                       (ltssmstate[4:0]),
+         .rx_par_err                       (rx_par_err),
+         .tx_par_err                       (tx_par_err[1:0]),
+         .cfg_par_err                      (cfg_par_err),
+         .ko_cpl_spc_header                (ko_cpl_spc_header[7:0]),
+         .ko_cpl_spc_data                  (ko_cpl_spc_data[11:0]),
+         .currentspeed                     (currentspeed[1:0]),
+         
+         // Inputs
+         // Resets
+         .npor                             (npor),
+         .pin_perst                        (pin_perst),
+
+         // Clocks
+         .pld_clk                          (pld_clk),
+         .refclk                           (refclk),
+         .pld_core_ready                   (pld_core_ready),
+
+         // Local management Interface
+         .lmi_addr                         (lmi_addr[11:0]),
+         .lmi_din                          (lmi_din[31:0]),
+         .lmi_rden                         (lmi_rden),
+         .lmi_wren                         (lmi_wren),
+         
+         // RX Interface
+         .rx_st_ready                      (rx_st_ready),
+         .rx_st_mask                       (rx_st_mask),
+
+         // TX Interface
+         .tx_st_sop                        (tx_st_sop[0:0]),
+         .tx_st_eop                        (tx_st_eop[0:0]),
+         .tx_st_err                        (tx_st_err[0:0]),
+         .tx_st_valid                      (tx_st_valid[0:0]),
+         .tx_st_data                       (tx_st_data[63:0]),
+
+         // Reconfiguration Interface
+         .reconfig_to_xcvr                 (reconfig_to_xcvr[699:0]),
+
+         // RX Serial interface
+         .rx_in0                           (rx_in[0]),
+         .rx_in1                           (rx_in[1]),
+         .rx_in2                           (rx_in[2]),
+         .rx_in3                           (rx_in[3]),
+         .rx_in4                           (rx_in[4]),
+         .rx_in5                           (rx_in[5]),
+         .rx_in6                           (rx_in[6]),
+         .rx_in7                           (rx_in[7]),
+
+         // Interrupt Interface
+         .app_int_sts                      (app_int_sts),
+         .app_msi_num                      (app_msi_num[4:0]),
+         .app_msi_req                      (app_msi_req),
+         .app_msi_tc                       (app_msi_tc[2:0]),
+         .simu_mode_pipe                   (1'b0));
+
+    // -------------------- END ALTERA IP INSTANTIATION  --------------------
+    // -------------------- BEGIN RIFFA INSTANTAION --------------------
+
+    // RIFFA channel interface
+    wire                      rst_out;
+    wire [C_NUM_CHNL-1:0]     chnl_rx_clk;
+    wire [C_NUM_CHNL-1:0]     chnl_rx;
+    wire [C_NUM_CHNL-1:0]     chnl_rx_ack;
+    wire [C_NUM_CHNL-1:0]     chnl_rx_last;
+    wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len;
+    wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_ren;
+    
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_clk;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_last;
+    wire [(C_NUM_CHNL*32)-1:0]               chnl_tx_len;
+    wire [(C_NUM_CHNL*31)-1:0]               chnl_tx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_ren;
+
+    wire                                     chnl_reset;
+    wire                                     chnl_clk;
+    wire                                     riffa_reset;
+    wire                                     riffa_clk;
+
+    assign chnl_clk = pld_clk;
+    assign chnl_reset = rst_out;
+    
+    riffa_wrapper_de5
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .RX_ST_READY                   (rx_st_ready),
+         .TX_ST_DATA                    (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (tx_st_valid[0:0]),
+         .TX_ST_EOP                     (tx_st_eop[0:0]),
+         .TX_ST_SOP                     (tx_st_sop[0:0]),
+         .TX_ST_EMPTY                   (tx_st_empty[0:0]),
+         .APP_MSI_REQ                   (app_msi_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .RX_ST_DATA                    (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (rx_st_eop[0:0]),
+         .RX_ST_SOP                     (rx_st_sop[0:0]),
+         .RX_ST_VALID                   (rx_st_valid[0:0]),
+         .RX_ST_EMPTY                   (rx_st_empty[0:0]),
+         .TX_ST_READY                   (tx_st_ready),
+         .TL_CFG_CTL                    (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]),
+         .KO_CPL_SPC_DATA               (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]),
+         .APP_MSI_ACK                   (app_msi_ack),
+         .PLD_CLK                       (pld_clk),
+         .RESET_STATUS                  (reset_status),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+
+    // --------------------  END RIFFA INSTANTAION --------------------
+    // --------------------  BEGIN USER CODE  --------------------
+    genvar                                   i;
+    generate
+        for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
+            // Instantiate and assign modules to RIFFA channels. Users should 
+            // replace the chnl_tester instantiation with their own core.
+            chnl_tester 
+                 #(
+                   .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                   )
+            chnl_tester_i
+                 (
+
+                  .CLK(chnl_clk),
+                  .RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
+                  // Rx interface
+                  .CHNL_RX_CLK(chnl_rx_clk[i]), 
+                  .CHNL_RX(chnl_rx[i]), 
+                  .CHNL_RX_ACK(chnl_rx_ack[i]), 
+                  .CHNL_RX_LAST(chnl_rx_last[i]), 
+                  .CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]), 
+                  .CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
+                  // Tx interface
+                  .CHNL_TX_CLK(chnl_tx_clk[i]), 
+                  .CHNL_TX(chnl_tx[i]), 
+                  .CHNL_TX_ACK(chnl_tx_ack[i]), 
+                  .CHNL_TX_LAST(chnl_tx_last[i]), 
+                  .CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]), 
+                  .CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
+                  );    
+        end
+    endgenerate
+    // --------------------  END USER CODE  --------------------
+endmodule

fpga/altera/de5/DE5Gen1x8If64/prj/DE5Gen1x8If64.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 16:27:01  June 09, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:27:01  June 09, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "DE5Gen1x8If64"

fpga/altera/de5/DE5Gen1x8If64/prj/DE5Gen1x8If64.qsf

@@ -0,0 +1,476 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 11:03:06  March 21, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		DE5Gen1x8If64_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Stratix V"
+set_global_assignment -name DEVICE 5SGXEA7N2F45C2
+set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen1x8If64
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06  MARCH 21, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
+
+################################################################################
+# Timing SDC Files
+################################################################################
+
+################################################################################
+# PCIE Connections
+################################################################################
+# PCIe clk (100 MHz)
+set_location_assignment PIN_AK38 -to PCIE_REFCLK
+set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK
+
+set_location_assignment PIN_AK39 -to "PCIE_REFCLK(n)"
+set_instance_assignment -name IO_STANDARD HCSL -to "PCIE_REFCLK(n)"
+
+set_location_assignment PIN_AU33 -to PCIE_RESET_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_RESET_N
+
+################################################################################
+#PCIE Pins
+################################################################################
+# Settings from SV PCIE User Guide (AV-ST)
+# 100 Ohm Termination 
+# 1.5V PCML 
+# XCVR_VCCR_VCCT_VOLTAGE 0_9V (GEN 1/2 CMU)
+# XCVR_VCCA_VOLTAGE 2_5V (GEN 1/2 CMU)
+# We use CMU PLL's (http://www.altera.com/literature/hb/stratix-v/stx5_52003.pdf)
+
+################################################################################
+#PCIE RX_IN 0
+################################################################################
+
+set_location_assignment PIN_BB43 -to PCIE_RX_IN[0]
+set_location_assignment PIN_BB44 -to "PCIE_RX_IN[0](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[0]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[0](n)"
+
+################################################################################
+#PCIE RX_IN 1
+################################################################################
+
+set_location_assignment PIN_BA41 -to PCIE_RX_IN[1]
+set_location_assignment PIN_BA42 -to "PCIE_RX_IN[1](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[1]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[1](n)"
+
+################################################################################
+#PCIE RX_IN 2
+################################################################################
+
+set_location_assignment PIN_AW41 -to PCIE_RX_IN[2]
+set_location_assignment PIN_AW42 -to "PCIE_RX_IN[2](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[2]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[2](n)"
+
+################################################################################
+#PCIE RX_IN 3
+################################################################################
+
+set_location_assignment PIN_AY43 -to PCIE_RX_IN[3]
+set_location_assignment PIN_AY44 -to "PCIE_RX_IN[3](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[3]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[3](n)"
+
+################################################################################
+#PCIE RX_IN 4
+################################################################################
+
+set_location_assignment PIN_AT43 -to PCIE_RX_IN[4]
+set_location_assignment PIN_AT44 -to "PCIE_RX_IN[4](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[4]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[4](n)"
+
+################################################################################
+#PCIE RX_IN 5
+################################################################################
+
+set_location_assignment PIN_AP43 -to PCIE_RX_IN[5]
+set_location_assignment PIN_AP44 -to "PCIE_RX_IN[5](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[5]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[5](n)"
+
+################################################################################
+#PCIE RX_IN 6
+################################################################################
+
+set_location_assignment PIN_AM43 -to PCIE_RX_IN[6]
+set_location_assignment PIN_AM44 -to "PCIE_RX_IN[6](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[6]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[6](n)"
+
+################################################################################
+#PCIE RX_IN 7
+################################################################################
+
+set_location_assignment PIN_AK43 -to PCIE_RX_IN[7]
+set_location_assignment PIN_AK44 -to "PCIE_RX_IN[7](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_RX_IN[7]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_RX_IN[7](n)"
+
+################################################################################
+#PCIE TX_OUT 0
+################################################################################
+set_location_assignment PIN_AY39 -to PCIE_TX_OUT[0]
+set_location_assignment PIN_AY40 -to "PCIE_TX_OUT[0](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[0]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[0](n)"
+
+################################################################################
+#PCIE TX_OUT 1
+################################################################################
+set_location_assignment PIN_AV39 -to PCIE_TX_OUT[1]
+set_location_assignment PIN_AV40 -to "PCIE_TX_OUT[1](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[1]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[1](n)"
+
+################################################################################
+#PCIE TX_OUT 2
+################################################################################
+set_location_assignment PIN_AT39 -to PCIE_TX_OUT[2]
+set_location_assignment PIN_AT40 -to "PCIE_TX_OUT[2](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[2]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[2](n)"
+
+################################################################################
+#PCIE TX_OUT 3
+################################################################################
+set_location_assignment PIN_AU41 -to PCIE_TX_OUT[3]
+set_location_assignment PIN_AU42 -to "PCIE_TX_OUT[3](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[3]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[3](n)"
+
+################################################################################
+#PCIE TX_OUT 4
+################################################################################
+set_location_assignment PIN_AN41 -to PCIE_TX_OUT[4]
+set_location_assignment PIN_AN42 -to "PCIE_TX_OUT[4](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[4]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[4](n)"
+
+################################################################################
+#PCIE TX_OUT 5
+################################################################################
+set_location_assignment PIN_AL41 -to PCIE_TX_OUT[5]
+set_location_assignment PIN_AL42 -to "PCIE_TX_OUT[5](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[5]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[5](n)"
+
+################################################################################
+#PCIE TX_OUT 6
+################################################################################
+set_location_assignment PIN_AJ41 -to PCIE_TX_OUT[6]
+set_location_assignment PIN_AJ42 -to "PCIE_TX_OUT[6](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[6]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[6](n)"
+
+################################################################################
+#PCIE TX_OUT 7
+################################################################################
+
+set_location_assignment PIN_AG41 -to PCIE_TX_OUT[7]
+set_location_assignment PIN_AG42 -to "PCIE_TX_OUT[7](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to PCIE_TX_OUT[7]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN1 -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 2_5V -to "PCIE_TX_OUT[7](n)"
+
+################################################################################
+# LED's
+################################################################################
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7]
+
+set_location_assignment PIN_AW37 -to LED[0]
+set_location_assignment PIN_AV37 -to LED[1]
+set_location_assignment PIN_BB36 -to LED[2]
+set_location_assignment PIN_BB39 -to LED[3]
+set_location_assignment PIN_AH15 -to LED[4]
+set_location_assignment PIN_AH13 -to LED[5]
+set_location_assignment PIN_AJ13 -to LED[6]
+set_location_assignment PIN_AJ14 -to LED[7]
+
+################################################################################
+# OSCILLATORS
+################################################################################
+
+set_location_assignment PIN_BC28 -to OSC_BANK3D_50MHZ
+set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_BANK3D_50MHZ
+
+################################################################################
+# End Custom Instantiations
+################################################################################
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name SDC_FILE ../constr/DE5Gen1x8If64.sdc
+set_global_assignment -name SIP_FILE ../ip/XCVRCtrlGen1x8.sip
+set_global_assignment -name QIP_FILE ../ip/XCVRCtrlGen1x8.qip
+set_global_assignment -name SIP_FILE ../ip/PCIeGen1x8If64.sip
+set_global_assignment -name QIP_FILE ../ip/PCIeGen1x8If64.qip
+set_global_assignment -name VERILOG_FILE ../hdl/DE5Gen1x8If64.v
+set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ohtb.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

fpga/altera/de5/DE5Gen2x8If128/constr/DE5Gen2x8If128.sdc

@@ -0,0 +1,96 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            DE5Gen2x8If128.sdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Synopsys Design Constraints for the DE5 board.
+# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}]
+create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}]
+
+################################################################################
+# 13.1 Workround for http://www.altera.com/support/kdb/solutions/rd12162013_581.html?GSA_pos=1&WT.oss_r=1&WT.oss=adce_off_r
+################################################################################
+
+set_false_path -to [get_registers *|*.adce_off_r[0]]
+set_false_path -to [get_registers *|*.adce_on_rr[0]]
+set_false_path -to [get_registers *|reset_sync_pldclk_r[*]]
+
+################################################################################
+# End Workround 
+################################################################################
+
+derive_pll_clocks -create_base_clocks
+derive_clock_uncertainty
+
+################################################################################
+# Imports from Example Design (altera/13.1/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/)
+################################################################################
+
+######################################################################
+# HIP Soft reset controller SDC constraints
+set_false_path -to   [get_registers *altpcie_rs_serdes|fifo_err_sync_r[0]]
+set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*]
+
+# HIP testin pins SDC constraints
+set_false_path -from [get_pins -compatibility_mode *hip_ctrl*]
+
+######################################################################
+# Constraints for CV SIG asynchonous logic
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|test_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqout[*]}]
+                                                                                                                                                
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqber[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_lf[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_fs[*]}]

fpga/altera/de5/DE5Gen2x8If128/hdl/DE5Gen2x8If128.v

@@ -0,0 +1,526 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            DE5Gen2x8If128
+// Version:             
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Altera Stratix V Hard IP for PCI Express
+//                      module and the Terasic DE5 net Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`timescale 1ps / 1ps
+module DE5Gen2x8If128
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Quartus IP Library
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     // ----------LEDs----------
+     output [7:0]             LED,
+
+     // ----------PCIE----------
+     input                    PCIE_RESET_N,
+     input                    PCIE_REFCLK,
+
+     // ----------PCIE Serial RX----------
+     input [C_NUM_LANES-1:0]  PCIE_RX_IN,
+
+     // ----------PCIE Serial TX----------
+     output [C_NUM_LANES-1:0] PCIE_TX_OUT,
+
+     // ----------Oscillators----------
+     input                    OSC_BANK3D_50MHZ
+     );
+
+    wire                      npor;
+    wire                      pin_perst;
+
+    // ----------LMI Interface----------
+    wire [11:0]               lmi_addr;
+    wire [31:0]               lmi_din;
+    wire                      lmi_rden;
+    wire                      lmi_wren;
+    wire                      lmi_ack;
+    wire [31:0]               lmi_dout;
+
+    // ----------TL Config interface----------
+    wire [3:0]                tl_cfg_add;
+    wire [31:0]               tl_cfg_ctl;
+    wire [52:0]               tl_cfg_sts;
+
+    // ----------Rx/TX Interfaces----------
+    wire [0:0]                rx_st_sop;
+    wire [0:0]                rx_st_eop;
+    wire [0:0]                rx_st_err;
+    wire [0:0]                rx_st_valid;
+    wire [0:0]                rx_st_empty;
+    wire                      rx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0] rx_st_data;
+
+    wire [7:0]                  rx_st_bar;
+    wire                        rx_st_mask;
+
+    wire [0:0]                  tx_st_sop;
+    wire [0:0]                  tx_st_eop;
+    wire [0:0]                  tx_st_err;
+    wire [0:0]                  tx_st_valid;
+    wire [0:0]                  tx_st_empty;
+    wire                        tx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0] tx_st_data;
+
+    // ----------Clocks----------
+    wire                        pld_clk;
+    wire                        coreclkout_hip;
+    wire                        refclk;
+    wire                        pld_core_ready;
+    wire                        reset_status;
+    wire                        serdes_pll_locked;
+    wire                        pld_clk_inuse;
+
+    // ----------Reconfiguration busses----------
+    wire [699:0]                reconfig_to_xcvr;
+    wire [505:0]                reconfig_from_xcvr;
+
+    // ----------Interrupt Interfaces----------
+    wire                        app_int_sts;
+    wire [4:0]                  app_msi_num;
+    wire                        app_msi_req;
+    wire [2:0]                  app_msi_tc;
+    wire                        app_int_ack;
+    wire                        app_msi_ack;
+
+    // ----------Link status signals----------
+    wire                        derr_cor_ext_rcv;
+    wire                        derr_cor_ext_rpl;
+    wire                        derr_rpl;
+    wire                        dlup;
+    wire                        dlup_exit;
+    wire                        ev128ns;
+    wire                        ev1us;
+    wire                        hotrst_exit;
+    wire [3:0]                  int_status;
+    wire                        l2_exit;
+    wire [3:0]                  lane_act;
+    wire [4:0]                  ltssmstate;
+    wire                        rx_par_err;
+    wire [1:0]                  tx_par_err;
+    wire                        cfg_par_err;
+    wire [1:0]                  currentspeed;
+    wire [7:0]                  ko_cpl_spc_header;
+    wire [11:0]                 ko_cpl_spc_data;
+
+    // ----------Link Status Signals (Driver)----------
+    wire                        derr_cor_ext_rcv_drv;
+    wire                        derr_cor_ext_rpl_drv;
+    wire                        derr_rpl_drv;
+    wire                        dlup_drv;
+    wire                        dlup_exit_drv;
+    wire                        ev128ns_drv;
+    wire                        ev1us_drv;
+    wire                        hotrst_exit_drv;
+    wire [3:0]                  int_status_drv;
+    wire                        l2_exit_drv;
+    wire [3:0]                  lane_act_drv;
+    wire [4:0]                  ltssmstate_drv;
+    wire                        rx_par_err_drv;
+    wire [1:0]                  tx_par_err_drv;
+    wire                        cfg_par_err_drv;
+    wire [7:0]                  ko_cpl_spc_header_drv;
+    wire [11:0]                 ko_cpl_spc_data_drv;
+
+
+    // ----------Reconfiguration Controller signals----------
+    wire                        reconfig_busy;
+    wire                        mgmt_clk_clk;
+    wire                        mgmt_rst_reset;
+
+    wire [6:0]                  reconfig_mgmt_address;
+    wire                        reconfig_mgmt_read;
+    wire [31:0]                 reconfig_mgmt_readdata;
+    wire                        reconfig_mgmt_waitrequest;
+    wire                        reconfig_mgmt_write;
+    wire [31:0]                 reconfig_mgmt_writedata;
+
+    // ----------Reconfiguration Driver signals----------
+    wire                        reconfig_xcvr_clk;
+    wire                        reconfig_xcvr_rst;
+
+    wire [7:0]                  rx_in;
+    wire [7:0]                  tx_out;
+
+    // ----------Serial interfaces----------
+    assign rx_in = PCIE_RX_IN;
+    assign PCIE_TX_OUT = tx_out;
+
+    // ----------Clocks----------
+    assign pld_clk = coreclkout_hip;
+    assign mgmt_clk_clk = PCIE_REFCLK;
+    assign reconfig_xcvr_clk = PCIE_REFCLK;
+    assign refclk = PCIE_REFCLK;
+    assign pld_core_ready = serdes_pll_locked;
+    
+    // ----------Resets----------
+    assign reconfig_xcvr_rst = 1'b0;
+    assign mgmt_rst_reset = 1'b0;
+    assign pin_perst = PCIE_RESET_N;
+    assign npor = PCIE_RESET_N;
+
+    // ----------LED's----------
+    assign LED[7:0] = 8'hff;
+
+    // -------------------- BEGIN ALTERA IP INSTANTIATION  --------------------
+    // Transciever driver (Required for Gen1)
+    altpcie_reconfig_driver 
+        #(.number_of_reconfig_interfaces(10),
+          .gen123_lane_rate_mode_hwtcl("Gen2 (5.0 Gbps)"),
+          .INTENDED_DEVICE_FAMILY("Stratix V"))
+    XCVRDriverGen2x8_inst
+        (
+         // Outputs
+         .reconfig_mgmt_address            (reconfig_mgmt_address[6:0]),
+         .reconfig_mgmt_read               (reconfig_mgmt_read),
+         .reconfig_mgmt_write              (reconfig_mgmt_write),
+         .reconfig_mgmt_writedata          (reconfig_mgmt_writedata[31:0]),
+        
+         .cal_busy_in                      (),
+         // Inputs
+         .pld_clk                          (pld_clk),
+        
+         .reconfig_xcvr_rst                (reconfig_xcvr_rst),
+         .reconfig_mgmt_readdata           (reconfig_mgmt_readdata[31:0]),
+         .reconfig_mgmt_waitrequest        (reconfig_mgmt_waitrequest),
+         .reconfig_xcvr_clk                (reconfig_xcvr_clk),
+         .reconfig_busy                    (reconfig_busy),
+
+         // Link Status signals
+         .derr_cor_ext_rcv_drv             (derr_cor_ext_rcv_drv),
+         .derr_cor_ext_rpl_drv             (derr_cor_ext_rpl_drv),
+         .derr_rpl_drv                     (derr_rpl_drv),
+         .dlup_drv                         (dlup_drv),
+         .dlup_exit_drv                    (dlup_exit_drv),
+         .ev128ns_drv                      (ev128ns_drv),
+         .ev1us_drv                        (ev1us_drv),
+         .hotrst_exit_drv                  (hotrst_exit_drv),
+         .int_status_drv                   (int_status_drv[3:0]),
+         .l2_exit_drv                      (l2_exit_drv),
+         .lane_act_drv                     (lane_act_drv[3:0]),
+         .ltssmstate_drv                   (ltssmstate_drv[4:0]),
+         .rx_par_err_drv                   (rx_par_err_drv),
+         .tx_par_err_drv                   (tx_par_err_drv[1:0]),
+         .cfg_par_err_drv                  (cfg_par_err_drv),
+         .ko_cpl_spc_header_drv            (ko_cpl_spc_header_drv[7:0]),
+         .ko_cpl_spc_data_drv              (ko_cpl_spc_data_drv[11:0]),
+         .currentspeed                     (currentspeed[1:0]));
+
+    assign derr_cor_ext_rcv_drv = derr_cor_ext_rcv;
+    assign derr_cor_ext_rpl_drv = derr_cor_ext_rpl;
+    assign derr_rpl_drv = derr_rpl;
+    assign dlup_drv = dlup;
+    assign dlup_exit_drv = dlup_exit;
+    assign ev128ns_drv = ev128ns;
+    assign ev1us_drv = ev1us;
+    assign hotrst_exit_drv = hotrst_exit;
+    assign int_status_drv = int_status;
+    assign l2_exit_drv = l2_exit;
+    assign lane_act_drv = lane_act;
+    assign ltssmstate_drv = ltssmstate;
+    assign rx_par_err_drv = rx_par_err;
+    assign tx_par_err_drv = tx_par_err;
+    assign cfg_par_err_drv = cfg_par_err;
+    assign ko_cpl_spc_header_drv = ko_cpl_spc_header;
+    assign ko_cpl_spc_data_drv = ko_cpl_spc_data;
+
+    XCVRCtrlGen2x8 XCVRCtrlGen2x8_inst
+        (
+         // Outputs
+         .reconfig_busy                    (reconfig_busy),
+         .reconfig_mgmt_readdata           (reconfig_mgmt_readdata[31:0]),
+         .reconfig_mgmt_waitrequest        (reconfig_mgmt_waitrequest),
+         .reconfig_to_xcvr                 (reconfig_to_xcvr[699:0]),
+         // Inputs
+         .mgmt_clk_clk                     (mgmt_clk_clk),
+         .mgmt_rst_reset                   (mgmt_rst_reset),
+         .reconfig_mgmt_address            (reconfig_mgmt_address[6:0]),
+         .reconfig_mgmt_read               (reconfig_mgmt_read),
+         .reconfig_mgmt_write              (reconfig_mgmt_write),
+         .reconfig_mgmt_writedata          (reconfig_mgmt_writedata[31:0]),
+         .reconfig_from_xcvr               (reconfig_from_xcvr[459:0]));
+
+
+    // PCIE Core
+    PCIeGen2x8If128 PCIeGen2x8If128_inst
+        (
+         // Outputs
+         // Local Management Interface
+         .lmi_ack                          (lmi_ack),
+         .lmi_dout                         (lmi_dout[31:0]),
+         .tl_cfg_add                       (tl_cfg_add[3:0]),
+         .tl_cfg_ctl                       (tl_cfg_ctl[31:0]),
+         .tl_cfg_sts                       (tl_cfg_sts[52:0]),
+         
+         // RX Interface      
+         .rx_st_sop                        (rx_st_sop[0:0]),
+         .rx_st_eop                        (rx_st_eop[0:0]),
+         .rx_st_err                        (rx_st_err[0:0]),
+         .rx_st_valid                      (rx_st_valid[0:0]),
+         .rx_st_empty                      (rx_st_empty[0:0]),
+         .rx_st_data                       (rx_st_data[127:0]),
+         .rx_st_bar                        (rx_st_bar[7:0]),
+         // TX Interface      
+         .tx_st_ready                      (tx_st_ready),
+         
+         .coreclkout_hip                   (coreclkout_hip),
+         .reset_status                     (reset_status),
+         .serdes_pll_locked                (serdes_pll_locked),
+         .pld_clk_inuse                    (pld_clk_inuse),
+
+         // Reconfiguration Interface
+         .reconfig_from_xcvr               (reconfig_from_xcvr[459:0]),
+         
+         .tx_out0                          (tx_out[0]),
+         .tx_out1                          (tx_out[1]),
+         .tx_out2                          (tx_out[2]),
+         .tx_out3                          (tx_out[3]),
+         .tx_out4                          (tx_out[4]),
+         .tx_out5                          (tx_out[5]),
+         .tx_out6                          (tx_out[6]),
+         .tx_out7                          (tx_out[7]),
+
+         .app_int_ack                      (app_int_ack),
+         .app_msi_ack                      (app_msi_ack),
+
+         // Link status signals
+         .derr_cor_ext_rcv                 (derr_cor_ext_rcv),
+         .derr_cor_ext_rpl                 (derr_cor_ext_rpl),
+         .derr_rpl                         (derr_rpl),
+         .dlup                             (dlup),
+         .dlup_exit                        (dlup_exit),
+         .ev128ns                          (ev128ns),
+         .ev1us                            (ev1us),
+         .hotrst_exit                      (hotrst_exit),
+         .int_status                       (int_status[3:0]),
+         .l2_exit                          (l2_exit),
+         .lane_act                         (lane_act[3:0]),
+         .ltssmstate                       (ltssmstate[4:0]),
+         .rx_par_err                       (rx_par_err),
+         .tx_par_err                       (tx_par_err[1:0]),
+         .cfg_par_err                      (cfg_par_err),
+         .ko_cpl_spc_header                (ko_cpl_spc_header[7:0]),
+         .ko_cpl_spc_data                  (ko_cpl_spc_data[11:0]),
+         .currentspeed                     (currentspeed[1:0]),
+         
+         // Inputs
+         // Resets
+         .npor                             (npor),
+         .pin_perst                        (pin_perst),
+
+         // Clocks
+         .pld_clk                          (pld_clk),
+         .refclk                           (refclk),
+         .pld_core_ready                   (pld_core_ready),
+
+         // Local management Interface
+         .lmi_addr                         (lmi_addr[11:0]),
+         .lmi_din                          (lmi_din[31:0]),
+         .lmi_rden                         (lmi_rden),
+         .lmi_wren                         (lmi_wren),
+         
+         // RX Interface
+         .rx_st_ready                      (rx_st_ready),
+         .rx_st_mask                       (rx_st_mask),
+
+         // TX Interface
+         .tx_st_sop                        (tx_st_sop[0:0]),
+         .tx_st_eop                        (tx_st_eop[0:0]),
+         .tx_st_err                        (tx_st_err[0:0]),
+         .tx_st_valid                      (tx_st_valid[0:0]),
+         .tx_st_empty                      (tx_st_empty[0:0]),
+         .tx_st_data                       (tx_st_data[127:0]),
+
+         // Reconfiguration Interface
+         .reconfig_to_xcvr                 (reconfig_to_xcvr[699:0]),
+
+         // RX Serial interface
+         .rx_in0                           (rx_in[0]),
+         .rx_in1                           (rx_in[1]),
+         .rx_in2                           (rx_in[2]),
+         .rx_in3                           (rx_in[3]),
+         .rx_in4                           (rx_in[4]),
+         .rx_in5                           (rx_in[5]),
+         .rx_in6                           (rx_in[6]),
+         .rx_in7                           (rx_in[7]),
+
+         // Interrupt Interface
+         .app_int_sts                      (app_int_sts),
+         .app_msi_num                      (app_msi_num[4:0]),
+         .app_msi_req                      (app_msi_req),
+         .app_msi_tc                       (app_msi_tc[2:0]),
+         .simu_mode_pipe                   (1'b0));
+    
+    // -------------------- END ALTERA IP INSTANTIATION  --------------------
+    // -------------------- BEGIN RIFFA INSTANTAION --------------------
+
+    // RIFFA channel interface
+    wire                        rst_out;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_clk;
+    wire [C_NUM_CHNL-1:0]       chnl_rx;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_ack;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_last;
+    wire [(C_NUM_CHNL*32)-1:0]  chnl_rx_len;
+    wire [(C_NUM_CHNL*31)-1:0]  chnl_rx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_ren;
+    
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_clk;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_last;
+    wire [(C_NUM_CHNL*32)-1:0]               chnl_tx_len;
+    wire [(C_NUM_CHNL*31)-1:0]               chnl_tx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_ren;
+
+    wire                                     chnl_reset;
+    wire                                     chnl_clk;
+    wire                                     riffa_reset;
+    wire                                     riffa_clk;
+
+    assign chnl_clk = pld_clk;
+    assign chnl_reset = rst_out;
+    
+    riffa_wrapper_de5
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .RX_ST_READY                   (rx_st_ready),
+         .TX_ST_DATA                    (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (tx_st_valid[0:0]),
+         .TX_ST_EOP                     (tx_st_eop[0:0]),
+         .TX_ST_SOP                     (tx_st_sop[0:0]),
+         .TX_ST_EMPTY                   (tx_st_empty[0:0]),
+         .APP_MSI_REQ                   (app_msi_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .RX_ST_DATA                    (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (rx_st_eop[0:0]),
+         .RX_ST_SOP                     (rx_st_sop[0:0]),
+         .RX_ST_VALID                   (rx_st_valid[0:0]),
+         .RX_ST_EMPTY                   (rx_st_empty[0:0]),
+         .TX_ST_READY                   (tx_st_ready),
+         .TL_CFG_CTL                    (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]),
+         .KO_CPL_SPC_DATA               (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]),
+         .APP_MSI_ACK                   (app_msi_ack),
+         .PLD_CLK                       (pld_clk),
+         .RESET_STATUS                  (reset_status),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+
+    // --------------------  END RIFFA INSTANTAION --------------------
+    // --------------------  BEGIN USER CODE  --------------------
+    genvar                                   i;
+    generate
+        for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
+            // Instantiate and assign modules to RIFFA channels. Users should 
+            // replace the chnl_tester instantiation with their own core.
+            chnl_tester 
+                 #(
+                   .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                   )
+            chnl_tester_i
+                 (
+
+                  .CLK(chnl_clk),
+                  .RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
+                  // Rx interface
+                  .CHNL_RX_CLK(chnl_rx_clk[i]), 
+                  .CHNL_RX(chnl_rx[i]), 
+                  .CHNL_RX_ACK(chnl_rx_ack[i]), 
+                  .CHNL_RX_LAST(chnl_rx_last[i]), 
+                  .CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]), 
+                  .CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
+                  // Tx interface
+                  .CHNL_TX_CLK(chnl_tx_clk[i]), 
+                  .CHNL_TX(chnl_tx[i]), 
+                  .CHNL_TX_ACK(chnl_tx_ack[i]), 
+                  .CHNL_TX_LAST(chnl_tx_last[i]), 
+                  .CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]), 
+                  .CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
+                  );    
+        end
+    endgenerate
+    // --------------------  END USER CODE  --------------------
+endmodule

fpga/altera/de5/DE5Gen2x8If128/prj/DE5Gen2x8If128.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 16:15:54  June 09, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:15:54  June 09, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "DE5Gen2x8If128"

fpga/altera/de5/DE5Gen2x8If128/prj/DE5Gen2x8If128.qsf

@@ -0,0 +1,501 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 11:03:06  March 21, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		DE5Gen2x8If128_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Stratix V"
+set_global_assignment -name DEVICE 5SGXEA7N2F45C2
+set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen2x8If128
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06  MARCH 21, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
+
+################################################################################
+# Timing SDC Files
+################################################################################
+
+################################################################################
+# PCIE Connections
+################################################################################
+# PCIe clk (100 MHz)
+set_location_assignment PIN_AK38 -to PCIE_REFCLK
+set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK
+
+set_location_assignment PIN_AU33 -to PCIE_RESET_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_RESET_N
+
+################################################################################
+#PCIE Pins
+################################################################################
+# Settings from SV PCIE User Guide (AV-ST)
+# - 1.5V PCML 
+# - XCVR_VCCR_VCCT_VOLTAGE 1_0V 
+# - XCVR_VCCA_VOLTAGE 3_0V 
+# (SV User guide recommends VCCR/VCCT = 0_9 and VCCA = 2_5 , but link does not 
+# train correctly if these settings are used)
+# 
+# We use CMU PLL's (http://www.altera.com/literature/hb/stratix-v/stx5_52003.pdf)
+# Errata: http://www.altera.com/support/kdb/solutions/rd10112012_529.html
+################################################################################
+# Gloabal PCIE assignments (Use if signal problems exist)
+################################################################################
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[*]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[*]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[*]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[*](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[*]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[*]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[*](n)"
+
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_TX_OUT[*]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_TX_OUT[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_TX_OUT[*]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_TX_OUT[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_TX_OUT[*]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_TX_OUT[*](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_TX_OUT[*]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_TX_OUT[*](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_TX_OUT[*]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_TX_OUT[*](n)"
+
+################################################################################
+#PCIE RX_IN 0
+################################################################################
+
+set_location_assignment PIN_BB43 -to PCIE_RX_IN[0]
+set_location_assignment PIN_BB44 -to "PCIE_RX_IN[0](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[0]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[0](n)"
+
+################################################################################
+#PCIE RX_IN 1
+################################################################################
+
+set_location_assignment PIN_BA41 -to PCIE_RX_IN[1]
+set_location_assignment PIN_BA42 -to "PCIE_RX_IN[1](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[1]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[1](n)"
+
+################################################################################
+#PCIE RX_IN 2
+################################################################################
+
+set_location_assignment PIN_AW41 -to PCIE_RX_IN[2]
+set_location_assignment PIN_AW42 -to "PCIE_RX_IN[2](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[2]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[2](n)"
+
+################################################################################
+#PCIE RX_IN 3
+################################################################################
+
+set_location_assignment PIN_AY43 -to PCIE_RX_IN[3]
+set_location_assignment PIN_AY44 -to "PCIE_RX_IN[3](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[3]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[3](n)"
+
+################################################################################
+#PCIE RX_IN 4
+################################################################################
+
+set_location_assignment PIN_AT43 -to PCIE_RX_IN[4]
+set_location_assignment PIN_AT44 -to "PCIE_RX_IN[4](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[4]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[4]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[4](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[4](n)"
+
+################################################################################
+#PCIE RX_IN 5
+################################################################################
+
+set_location_assignment PIN_AP43 -to PCIE_RX_IN[5]
+set_location_assignment PIN_AP44 -to "PCIE_RX_IN[5](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[5]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[5]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[5](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[5](n)"
+
+################################################################################
+#PCIE RX_IN 6
+################################################################################
+
+set_location_assignment PIN_AM43 -to PCIE_RX_IN[6]
+set_location_assignment PIN_AM44 -to "PCIE_RX_IN[6](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[6]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[6]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[6](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[6](n)"
+
+################################################################################
+#PCIE RX_IN 7
+################################################################################
+
+set_location_assignment PIN_AK43 -to PCIE_RX_IN[7]
+set_location_assignment PIN_AK44 -to "PCIE_RX_IN[7](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[7]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[7]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[7](n)"
+
+################################################################################
+#PCIE TX_OUT 0
+################################################################################
+set_location_assignment PIN_AY39 -to PCIE_TX_OUT[0]
+set_location_assignment PIN_AY40 -to "PCIE_TX_OUT[0](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[0]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[0](n)"
+
+################################################################################
+#PCIE TX_OUT 1
+################################################################################
+set_location_assignment PIN_AV39 -to PCIE_TX_OUT[1]
+set_location_assignment PIN_AV40 -to "PCIE_TX_OUT[1](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[1]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[1](n)"
+
+################################################################################
+#PCIE TX_OUT 2
+################################################################################
+set_location_assignment PIN_AT39 -to PCIE_TX_OUT[2]
+set_location_assignment PIN_AT40 -to "PCIE_TX_OUT[2](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[2]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[2](n)"
+
+################################################################################
+#PCIE TX_OUT 3
+################################################################################
+set_location_assignment PIN_AU41 -to PCIE_TX_OUT[3]
+set_location_assignment PIN_AU42 -to "PCIE_TX_OUT[3](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[3]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[3](n)"
+
+################################################################################
+#PCIE TX_OUT 4
+################################################################################
+set_location_assignment PIN_AN41 -to PCIE_TX_OUT[4]
+set_location_assignment PIN_AN42 -to "PCIE_TX_OUT[4](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[4]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[4]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[4](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[4](n)"
+
+################################################################################
+#PCIE TX_OUT 5
+################################################################################
+set_location_assignment PIN_AL41 -to PCIE_TX_OUT[5]
+set_location_assignment PIN_AL42 -to "PCIE_TX_OUT[5](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[5]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[5]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[5](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[5](n)"
+
+################################################################################
+#PCIE TX_OUT 6
+################################################################################
+set_location_assignment PIN_AJ41 -to PCIE_TX_OUT[6]
+set_location_assignment PIN_AJ42 -to "PCIE_TX_OUT[6](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[6]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[6]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[6](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[6](n)"
+
+################################################################################
+#PCIE TX_OUT 7
+################################################################################
+
+set_location_assignment PIN_AG41 -to PCIE_TX_OUT[7]
+set_location_assignment PIN_AG42 -to "PCIE_TX_OUT[7](n)"
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[7]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[7]
+
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN2 -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[7](n)"
+
+################################################################################
+# LED's
+################################################################################
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7]
+
+set_location_assignment PIN_AW37 -to LED[0]
+set_location_assignment PIN_AV37 -to LED[1]
+set_location_assignment PIN_BB36 -to LED[2]
+set_location_assignment PIN_BB39 -to LED[3]
+set_location_assignment PIN_AH15 -to LED[4]
+set_location_assignment PIN_AH13 -to LED[5]
+set_location_assignment PIN_AJ13 -to LED[6]
+set_location_assignment PIN_AJ14 -to LED[7]
+
+################################################################################
+# OSCILLATORS
+################################################################################
+
+set_location_assignment PIN_BC28 -to OSC_BANK3D_50MHZ
+set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_BANK3D_50MHZ
+
+################################################################################
+# End Custom Instantiations
+################################################################################
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name SDC_FILE ../constr/DE5Gen2x8If128.sdc
+set_global_assignment -name VERILOG_FILE ../hdl/DE5Gen2x8If128.v
+set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ohtb.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
+set_global_assignment -name QIP_FILE ../ip/PCIeGen2x8If128.qip
+set_global_assignment -name SIP_FILE ../ip/PCIeGen2x8If128.sip
+set_global_assignment -name QIP_FILE ../ip/XCVRCtrlGen2x8.qip
+set_global_assignment -name SIP_FILE ../ip/XCVRCtrlGen2x8.sip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

fpga/altera/de5/DE5Gen3x4If128/constr/DE5Gen3x4If128.sdc

@@ -0,0 +1,97 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            DE5Gen3x4If128.sdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Synopsys Design Constraints for the DE5 board.
+# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}]
+
+create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}]
+
+################################################################################
+# 13.1 Workround for http://www.altera.com/support/kdb/solutions/rd12162013_581.html?GSA_pos=1&WT.oss_r=1&WT.oss=adce_off_r
+################################################################################
+
+set_false_path -to [get_registers *|*.adce_off_r[0]]
+set_false_path -to [get_registers *|*.adce_on_rr[0]]
+set_false_path -to [get_registers *|reset_sync_pldclk_r[*]]
+
+################################################################################
+# End Workround 
+################################################################################
+
+derive_pll_clocks -create_base_clocks
+derive_clock_uncertainty
+
+################################################################################
+# Imports from Example Design (altera/13.1/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/)
+################################################################################
+
+######################################################################
+# HIP Soft reset controller SDC constraints
+set_false_path -to   [get_registers *altpcie_rs_serdes|fifo_err_sync_r[0]]
+set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*]
+
+# HIP testin pins SDC constraints
+set_false_path -from [get_pins -compatibility_mode *hip_ctrl*]
+
+######################################################################
+# Constraints for CV SIG asynchonous logic
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|test_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqout[*]}]
+                                                                                                                                                
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqber[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_lf[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_fs[*]}]

fpga/altera/de5/DE5Gen3x4If128/hdl/DE5Gen3x4If128.v

@@ -0,0 +1,520 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            DE5Gen3x4If128
+// Version:             
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Altera Stratix V Hard IP for PCI Express
+//                      module and the Terasic DE5 net Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`timescale 1ps / 1ps
+module DE5Gen3x4If128
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Quartus IP Library
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     // ----------LEDs----------
+     output [7:0]             LED,
+
+     // ----------PCIE----------
+     input                    PCIE_RESET_N,
+     input                    PCIE_REFCLK,
+
+     // ----------PCIE Serial RX----------
+     input [C_NUM_LANES-1:0]  PCIE_RX_IN,
+
+     // ----------PCIE Serial TX----------
+     output [C_NUM_LANES-1:0] PCIE_TX_OUT,
+
+     // ----------Oscillators----------
+     input                    OSC_BANK3D_50MHZ
+     );
+
+    wire                      npor;
+    wire                      pin_perst;
+
+    // ----------LMI Interface----------
+    wire [11:0]               lmi_addr;
+    wire [31:0]               lmi_din;
+    wire                      lmi_rden;
+    wire                      lmi_wren;
+    wire                      lmi_ack;
+    wire [31:0]               lmi_dout;
+
+    // ----------TL Config interface----------
+    wire [3:0]                tl_cfg_add;
+    wire [31:0]               tl_cfg_ctl;
+    wire [52:0]               tl_cfg_sts;
+
+    // ----------Rx/TX Interfaces----------
+    wire [0:0]                rx_st_sop;
+    wire [0:0]                rx_st_eop;
+    wire [0:0]                rx_st_err;
+    wire [0:0]                rx_st_valid;
+    wire [0:0]                rx_st_empty;
+    wire                      rx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0] rx_st_data;
+
+    wire [7:0]                  rx_st_bar;
+    wire                        rx_st_mask;
+
+    wire [0:0]                  tx_st_sop;
+    wire [0:0]                  tx_st_eop;
+    wire [0:0]                  tx_st_err;
+    wire [0:0]                  tx_st_valid;
+    wire [0:0]                  tx_st_empty;
+    wire                        tx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0] tx_st_data;
+
+    // ----------Clocks----------
+    wire                        pld_clk;
+    wire                        coreclkout_hip;
+    wire                        refclk;
+    wire                        pld_core_ready;
+    wire                        reset_status;
+    wire                        serdes_pll_locked;
+    wire                        pld_clk_inuse;
+
+    // ----------Reconfiguration busses----------
+    wire [699:0]                reconfig_to_xcvr;
+    wire [505:0]                reconfig_from_xcvr;
+
+    // ----------Interrupt Interfaces----------
+    wire                        app_int_sts;
+    wire [4:0]                  app_msi_num;
+    wire                        app_msi_req;
+    wire [2:0]                  app_msi_tc;
+    wire                        app_int_ack;
+    wire                        app_msi_ack;
+
+    // ----------Link status signals----------
+    wire                        derr_cor_ext_rcv;
+    wire                        derr_cor_ext_rpl;
+    wire                        derr_rpl;
+    wire                        dlup;
+    wire                        dlup_exit;
+    wire                        ev128ns;
+    wire                        ev1us;
+    wire                        hotrst_exit;
+    wire [3:0]                  int_status;
+    wire                        l2_exit;
+    wire [3:0]                  lane_act;
+    wire [4:0]                  ltssmstate;
+    wire                        rx_par_err;
+    wire [1:0]                  tx_par_err;
+    wire                        cfg_par_err;
+    wire [1:0]                  currentspeed;
+    wire [7:0]                  ko_cpl_spc_header;
+    wire [11:0]                 ko_cpl_spc_data;
+
+    // ----------Link Status Signals (Driver)----------
+    wire                        derr_cor_ext_rcv_drv;
+    wire                        derr_cor_ext_rpl_drv;
+    wire                        derr_rpl_drv;
+    wire                        dlup_drv;
+    wire                        dlup_exit_drv;
+    wire                        ev128ns_drv;
+    wire                        ev1us_drv;
+    wire                        hotrst_exit_drv;
+    wire [3:0]                  int_status_drv;
+    wire                        l2_exit_drv;
+    wire [3:0]                  lane_act_drv;
+    wire [4:0]                  ltssmstate_drv;
+    wire                        rx_par_err_drv;
+    wire [1:0]                  tx_par_err_drv;
+    wire                        cfg_par_err_drv;
+    wire [7:0]                  ko_cpl_spc_header_drv;
+    wire [11:0]                 ko_cpl_spc_data_drv;
+
+
+    // ----------Reconfiguration Controller signals----------
+    wire                        reconfig_busy;
+    wire                        mgmt_clk_clk;
+    wire                        mgmt_rst_reset;
+
+    wire [6:0]                  reconfig_mgmt_address;
+    wire                        reconfig_mgmt_read;
+    wire [31:0]                 reconfig_mgmt_readdata;
+    wire                        reconfig_mgmt_waitrequest;
+    wire                        reconfig_mgmt_write;
+    wire [31:0]                 reconfig_mgmt_writedata;
+
+    // ----------Reconfiguration Driver signals----------
+    wire                        reconfig_xcvr_clk;
+    wire                        reconfig_xcvr_rst;
+
+    wire [7:0]                  rx_in;
+    wire [7:0]                  tx_out;
+
+    // ----------Serial interfaces----------
+    assign rx_in = PCIE_RX_IN;
+    assign PCIE_TX_OUT = tx_out;
+
+    // ----------Clocks----------
+    assign pld_clk = coreclkout_hip;
+    assign mgmt_clk_clk = PCIE_REFCLK;
+    assign reconfig_xcvr_clk = PCIE_REFCLK;
+    assign refclk = PCIE_REFCLK;
+    assign pld_core_ready = serdes_pll_locked;
+    
+    // ----------Resets----------
+    assign reconfig_xcvr_rst = 1'b0;
+    assign mgmt_rst_reset = 1'b0;
+    assign pin_perst = PCIE_RESET_N;
+    assign npor = PCIE_RESET_N;
+
+    // ----------LED's----------
+    assign LED[7:0] = 8'hff;
+
+    // -------------------- BEGIN ALTERA IP INSTANTIATION  --------------------
+    // Transciever driver (Required for Gen1)
+   // Transciever driver (Required for Gen3)
+   altpcie_reconfig_driver 
+     #(.number_of_reconfig_interfaces(6),
+       .gen123_lane_rate_mode_hwtcl("Gen3 (8.0 Gbps)"),
+       .INTENDED_DEVICE_FAMILY("Stratix V"))
+   XCVRDriverGen3x4_inst
+     (
+      // Outputs
+      .reconfig_mgmt_address            (reconfig_mgmt_address[6:0]),
+      .reconfig_mgmt_read               (reconfig_mgmt_read),
+      .reconfig_mgmt_write              (reconfig_mgmt_write),
+      .reconfig_mgmt_writedata          (reconfig_mgmt_writedata[31:0]),
+      
+      // Inputs
+      .pld_clk                          (pld_clk),
+      
+      .reconfig_xcvr_rst                (reconfig_xcvr_rst),
+      .reconfig_mgmt_readdata           (reconfig_mgmt_readdata[31:0]),
+      .reconfig_mgmt_waitrequest        (reconfig_mgmt_waitrequest),
+      .reconfig_xcvr_clk                (reconfig_xcvr_clk),
+      .reconfig_busy                    (reconfig_busy),
+
+      // Link Status signals
+      .derr_cor_ext_rcv_drv             (derr_cor_ext_rcv_drv),
+      .derr_cor_ext_rpl_drv             (derr_cor_ext_rpl_drv),
+      .derr_rpl_drv                     (derr_rpl_drv),
+      .dlup_drv                         (dlup_drv),
+      .dlup_exit_drv                    (dlup_exit_drv),
+      .ev128ns_drv                      (ev128ns_drv),
+      .ev1us_drv                        (ev1us_drv),
+      .hotrst_exit_drv                  (hotrst_exit_drv),
+      .int_status_drv                   (int_status_drv[3:0]),
+      .l2_exit_drv                      (l2_exit_drv),
+      .lane_act_drv                     (lane_act_drv[3:0]),
+      .ltssmstate_drv                   (ltssmstate_drv[4:0]),
+      .rx_par_err_drv                   (rx_par_err_drv),
+      .tx_par_err_drv                   (tx_par_err_drv[1:0]),
+      .cfg_par_err_drv                  (cfg_par_err_drv),
+      .ko_cpl_spc_header_drv            (ko_cpl_spc_header_drv[7:0]),
+      .ko_cpl_spc_data_drv              (ko_cpl_spc_data_drv[11:0]),
+      .currentspeed                     (currentspeed[1:0]));
+
+    assign derr_cor_ext_rcv_drv = derr_cor_ext_rcv;
+    assign derr_cor_ext_rpl_drv = derr_cor_ext_rpl;
+    assign derr_rpl_drv = derr_rpl;
+    assign dlup_drv = dlup;
+    assign dlup_exit_drv = dlup_exit;
+    assign ev128ns_drv = ev128ns;
+    assign ev1us_drv = ev1us;
+    assign hotrst_exit_drv = hotrst_exit;
+    assign int_status_drv = int_status;
+    assign l2_exit_drv = l2_exit;
+    assign lane_act_drv = lane_act;
+    assign ltssmstate_drv = ltssmstate;
+    assign rx_par_err_drv = rx_par_err;
+    assign tx_par_err_drv = tx_par_err;
+    assign cfg_par_err_drv = cfg_par_err;
+    assign ko_cpl_spc_header_drv = ko_cpl_spc_header;
+    assign ko_cpl_spc_data_drv = ko_cpl_spc_data;
+
+    XCVRCtrlGen3x4 XCVRCtrlGen3x4_inst
+        (
+         // Outputs
+         .reconfig_busy                    (reconfig_busy),
+         .reconfig_mgmt_readdata           (reconfig_mgmt_readdata[31:0]),
+         .reconfig_mgmt_waitrequest        (reconfig_mgmt_waitrequest),
+         .reconfig_to_xcvr                 (reconfig_to_xcvr[699:0]),
+         // Inputs
+         .mgmt_clk_clk                     (mgmt_clk_clk),
+         .mgmt_rst_reset                   (mgmt_rst_reset),
+         .reconfig_mgmt_address            (reconfig_mgmt_address[6:0]),
+         .reconfig_mgmt_read               (reconfig_mgmt_read),
+         .reconfig_mgmt_write              (reconfig_mgmt_write),
+         .reconfig_mgmt_writedata          (reconfig_mgmt_writedata[31:0]),
+         .reconfig_from_xcvr               (reconfig_from_xcvr[459:0]));
+
+
+    // PCIE Core
+    PCIeGen3x4If128 PCIeGen3x4If128_inst
+        (
+         // Outputs
+         // Local Management Interface
+         .lmi_ack                          (lmi_ack),
+         .lmi_dout                         (lmi_dout[31:0]),
+         .tl_cfg_add                       (tl_cfg_add[3:0]),
+         .tl_cfg_ctl                       (tl_cfg_ctl[31:0]),
+         .tl_cfg_sts                       (tl_cfg_sts[52:0]),
+         
+         // RX Interface      
+         .rx_st_sop                        (rx_st_sop[0:0]),
+         .rx_st_eop                        (rx_st_eop[0:0]),
+         .rx_st_err                        (rx_st_err[0:0]),
+         .rx_st_valid                      (rx_st_valid[0:0]),
+         .rx_st_empty                      (rx_st_empty[0:0]),
+         .rx_st_data                       (rx_st_data[127:0]),
+         .rx_st_bar                        (rx_st_bar[7:0]),
+         // TX Interface      
+         .tx_st_ready                      (tx_st_ready),
+         
+         .coreclkout_hip                   (coreclkout_hip),
+         .reset_status                     (reset_status),
+         .serdes_pll_locked                (serdes_pll_locked),
+         .pld_clk_inuse                    (pld_clk_inuse),
+
+         // Reconfiguration Interface
+         .reconfig_from_xcvr               (reconfig_from_xcvr[459:0]),
+         
+         .tx_out0                          (tx_out[0]),
+         .tx_out1                          (tx_out[1]),
+         .tx_out2                          (tx_out[2]),
+         .tx_out3                          (tx_out[3]),
+
+
+         .app_int_ack                      (app_int_ack),
+         .app_msi_ack                      (app_msi_ack),
+
+         // Link status signals
+         .derr_cor_ext_rcv                 (derr_cor_ext_rcv),
+         .derr_cor_ext_rpl                 (derr_cor_ext_rpl),
+         .derr_rpl                         (derr_rpl),
+         .dlup                             (dlup),
+         .dlup_exit                        (dlup_exit),
+         .ev128ns                          (ev128ns),
+         .ev1us                            (ev1us),
+         .hotrst_exit                      (hotrst_exit),
+         .int_status                       (int_status[3:0]),
+         .l2_exit                          (l2_exit),
+         .lane_act                         (lane_act[3:0]),
+         .ltssmstate                       (ltssmstate[4:0]),
+         .rx_par_err                       (rx_par_err),
+         .tx_par_err                       (tx_par_err[1:0]),
+         .cfg_par_err                      (cfg_par_err),
+         .ko_cpl_spc_header                (ko_cpl_spc_header[7:0]),
+         .ko_cpl_spc_data                  (ko_cpl_spc_data[11:0]),
+         .currentspeed                     (currentspeed[1:0]),
+         
+         // Inputs
+         // Resets
+         .npor                             (npor),
+         .pin_perst                        (pin_perst),
+
+         // Clocks
+         .pld_clk                          (pld_clk),
+         .refclk                           (refclk),
+         .pld_core_ready                   (pld_core_ready),
+
+         // Local management Interface
+         .lmi_addr                         (lmi_addr[11:0]),
+         .lmi_din                          (lmi_din[31:0]),
+         .lmi_rden                         (lmi_rden),
+         .lmi_wren                         (lmi_wren),
+         
+         // RX Interface
+         .rx_st_ready                      (rx_st_ready),
+         .rx_st_mask                       (rx_st_mask),
+
+         // TX Interface
+         .tx_st_sop                        (tx_st_sop[0:0]),
+         .tx_st_eop                        (tx_st_eop[0:0]),
+         .tx_st_err                        (tx_st_err[0:0]),
+         .tx_st_valid                      (tx_st_valid[0:0]),
+         .tx_st_empty                      (tx_st_empty[0:0]),
+         .tx_st_data                       (tx_st_data[127:0]),
+
+         // Reconfiguration Interface
+         .reconfig_to_xcvr                 (reconfig_to_xcvr[699:0]),
+
+         // RX Serial interface
+         .rx_in0                           (rx_in[0]),
+         .rx_in1                           (rx_in[1]),
+         .rx_in2                           (rx_in[2]),
+         .rx_in3                           (rx_in[3]),
+
+
+         // Interrupt Interface
+         .app_int_sts                      (app_int_sts),
+         .app_msi_num                      (app_msi_num[4:0]),
+         .app_msi_req                      (app_msi_req),
+         .app_msi_tc                       (app_msi_tc[2:0]),
+         .simu_mode_pipe                   (1'b0));
+    
+    // -------------------- END ALTERA IP INSTANTIATION  --------------------
+    // -------------------- BEGIN RIFFA INSTANTAION --------------------
+
+    // RIFFA channel interface
+    wire                        rst_out;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_clk;
+    wire [C_NUM_CHNL-1:0]       chnl_rx;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_ack;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_last;
+    wire [(C_NUM_CHNL*32)-1:0]  chnl_rx_len;
+    wire [(C_NUM_CHNL*31)-1:0]  chnl_rx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_ren;
+    
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_clk;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_last;
+    wire [(C_NUM_CHNL*32)-1:0]               chnl_tx_len;
+    wire [(C_NUM_CHNL*31)-1:0]               chnl_tx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_ren;
+
+    wire                                     chnl_reset;
+    wire                                     chnl_clk;
+    wire                                     riffa_reset;
+    wire                                     riffa_clk;
+
+    assign chnl_clk = pld_clk;
+    assign chnl_reset = rst_out;
+    
+    riffa_wrapper_de5
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))/* TODO: Standardize*/
+    riffa
+        (
+         // Outputs
+         .RX_ST_READY                   (rx_st_ready),
+         .TX_ST_DATA                    (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (tx_st_valid[0:0]),
+         .TX_ST_EOP                     (tx_st_eop[0:0]),
+         .TX_ST_SOP                     (tx_st_sop[0:0]),
+         .TX_ST_EMPTY                   (tx_st_empty[0:0]),
+         .APP_MSI_REQ                   (app_msi_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .RX_ST_DATA                    (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (rx_st_eop[0:0]),
+         .RX_ST_SOP                     (rx_st_sop[0:0]),
+         .RX_ST_VALID                   (rx_st_valid[0:0]),
+         .RX_ST_EMPTY                   (rx_st_empty[0:0]),
+         .TX_ST_READY                   (tx_st_ready),
+         .TL_CFG_CTL                    (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]),
+         .KO_CPL_SPC_DATA               (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]),
+         .APP_MSI_ACK                   (app_msi_ack),
+         .PLD_CLK                       (pld_clk),
+         .RESET_STATUS                  (reset_status),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+
+    // --------------------  END RIFFA INSTANTAION --------------------
+    // --------------------  BEGIN USER CODE  --------------------
+    genvar                                   i;
+    generate
+        for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
+            // Instantiate and assign modules to RIFFA channels. Users should 
+            // replace the chnl_tester instantiation with their own core.
+            chnl_tester 
+                 #(
+                   .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                   )
+            chnl_tester_i
+                 (
+
+                  .CLK(chnl_clk),
+                  .RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
+                  // Rx interface
+                  .CHNL_RX_CLK(chnl_rx_clk[i]), 
+                  .CHNL_RX(chnl_rx[i]), 
+                  .CHNL_RX_ACK(chnl_rx_ack[i]), 
+                  .CHNL_RX_LAST(chnl_rx_last[i]), 
+                  .CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]), 
+                  .CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
+                  // Tx interface
+                  .CHNL_TX_CLK(chnl_tx_clk[i]), 
+                  .CHNL_TX(chnl_tx[i]), 
+                  .CHNL_TX_ACK(chnl_tx_ack[i]), 
+                  .CHNL_TX_LAST(chnl_tx_last[i]), 
+                  .CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]), 
+                  .CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
+                  );    
+        end
+    endgenerate
+    // --------------------  END USER CODE  --------------------
+endmodule

fpga/altera/de5/DE5Gen3x4If128/prj/DE5Gen3x4If128.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 16:21:12  June 09, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:21:12  June 09, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "DE5Gen3x4If128"

fpga/altera/de5/DE5Gen3x4If128/prj/DE5Gen3x4If128.qsf

@@ -0,0 +1,572 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+# Date created = 11:03:06  March 21, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		DE5Gen3x4If128_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Stratix V"
+set_global_assignment -name DEVICE 5SGXEA7N2F45C2
+set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen3x4If128
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06  MARCH 21, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
+
+################################################################################
+# Timing SDC Files
+################################################################################
+
+################################################################################
+# PCIE Connections
+################################################################################
+# PCIe clk (100 MHz)
+set_location_assignment PIN_AK38 -to PCIE_REFCLK
+
+set_location_assignment PIN_AK39 -to "PCIE_REFCLK(n)"
+
+set_location_assignment PIN_AU33 -to PCIE_RESET_N
+
+
+################################################################################
+#PCIE Pins
+################################################################################
+# Settings from SV PCIE User Guide (AV-ST)
+# 100 Ohm Termination 
+# 1.5V PCML 
+# XCVR_VCCR_VCCT_VOLTAGE 1_0V 
+# XCVR_VCCA_VOLTAGE 3_0V
+# We use CMU PLL's (http://www.altera.com/literature/hb/stratix-v/stx5_52003.pdf)
+# http://www.altera.com/support/kdb/downloads/rd08232012_334/quartusii-12.0sp2-2.dp9-readme.txt
+# Errata: http://www.altera.com/support/kdb/solutions/rd10112012_529.html
+
+################################################################################
+# Gloabal PCIE assignments (Use if signal problems exist)
+################################################################################
+
+################################################################################
+#PCIE RX_IN 0
+################################################################################
+
+set_location_assignment PIN_BB43 -to PCIE_RX_IN[0]
+set_location_assignment PIN_BB44 -to "PCIE_RX_IN[0](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 1
+################################################################################
+
+set_location_assignment PIN_BA41 -to PCIE_RX_IN[1]
+set_location_assignment PIN_BA42 -to "PCIE_RX_IN[1](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 2
+################################################################################
+
+set_location_assignment PIN_AW41 -to PCIE_RX_IN[2]
+set_location_assignment PIN_AW42 -to "PCIE_RX_IN[2](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 3
+################################################################################
+
+set_location_assignment PIN_AY43 -to PCIE_RX_IN[3]
+set_location_assignment PIN_AY44 -to "PCIE_RX_IN[3](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 4
+################################################################################
+
+# set_location_assignment PIN_AT43 -to PCIE_RX_IN[4]
+# set_location_assignment PIN_AT44 -to "PCIE_RX_IN[4](n)"
+
+
+
+################################################################################
+#PCIE RX_IN 5
+################################################################################
+
+# set_location_assignment PIN_AP43 -to PCIE_RX_IN[5]
+# set_location_assignment PIN_AP44 -to "PCIE_RX_IN[5](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 6
+################################################################################
+
+# set_location_assignment PIN_AM43 -to PCIE_RX_IN[6]
+# set_location_assignment PIN_AM44 -to "PCIE_RX_IN[6](n)"
+
+
+
+
+################################################################################
+#PCIE RX_IN 7
+################################################################################
+
+# set_location_assignment PIN_AK43 -to PCIE_RX_IN[7]
+# set_location_assignment PIN_AK44 -to "PCIE_RX_IN[7](n)"
+
+
+
+
+################################################################################
+#PCIE TX_OUT 0
+################################################################################
+set_location_assignment PIN_AY39 -to PCIE_TX_OUT[0]
+set_location_assignment PIN_AY40 -to "PCIE_TX_OUT[0](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 1
+################################################################################
+set_location_assignment PIN_AV39 -to PCIE_TX_OUT[1]
+set_location_assignment PIN_AV40 -to "PCIE_TX_OUT[1](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 2
+################################################################################
+set_location_assignment PIN_AT39 -to PCIE_TX_OUT[2]
+set_location_assignment PIN_AT40 -to "PCIE_TX_OUT[2](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 3
+################################################################################
+set_location_assignment PIN_AU41 -to PCIE_TX_OUT[3]
+set_location_assignment PIN_AU42 -to "PCIE_TX_OUT[3](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 4
+################################################################################
+# set_location_assignment PIN_AN41 -to PCIE_TX_OUT[4]
+# set_location_assignment PIN_AN42 -to "PCIE_TX_OUT[4](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 5
+################################################################################
+# set_location_assignment PIN_AL41 -to PCIE_TX_OUT[5]
+# set_location_assignment PIN_AL42 -to "PCIE_TX_OUT[5](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 6
+################################################################################
+# set_location_assignment PIN_AJ41 -to PCIE_TX_OUT[6]
+# set_location_assignment PIN_AJ42 -to "PCIE_TX_OUT[6](n)"
+
+
+
+################################################################################
+#PCIE TX_OUT 7
+################################################################################
+
+# set_location_assignment PIN_AG41 -to PCIE_TX_OUT[7]
+# set_location_assignment PIN_AG42 -to "PCIE_TX_OUT[7](n)"
+
+
+
+################################################################################
+# LED's
+################################################################################
+
+set_location_assignment PIN_AW37 -to LED[0]
+set_location_assignment PIN_AV37 -to LED[1]
+set_location_assignment PIN_BB36 -to LED[2]
+set_location_assignment PIN_BB39 -to LED[3]
+set_location_assignment PIN_AH15 -to LED[4]
+set_location_assignment PIN_AH13 -to LED[5]
+set_location_assignment PIN_AJ13 -to LED[6]
+set_location_assignment PIN_AJ14 -to LED[7]
+
+################################################################################
+# OSCILLATORS
+################################################################################
+
+set_location_assignment PIN_BC28 -to OSC_BANK3D_50MHZ
+
+################################################################################
+# End Custom Instantiations
+################################################################################
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK
+set_instance_assignment -name IO_STANDARD HCSL -to "PCIE_REFCLK(n)"
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_RESET_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_wake
+set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_smbclk
+set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_smbdata
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[0]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[0]
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[0]
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[0](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[1]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[1]
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[1]
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[1](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[2]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[2]
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[2]
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[2](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[3]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[3]
+set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[3](n)"
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[3]
+set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[3](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[4]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[4]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[4]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[4](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[5]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[5]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[5]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[5](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[6]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[6]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[6]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[6](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_RX_IN[7]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to PCIE_RX_IN[7]
+# set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_RX_SD_ON 1 -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "PCIE_RX_IN[7](n)"
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to PCIE_RX_IN[7]
+# set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "PCIE_RX_IN[7](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[0]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[0]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[0](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[1]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[1]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[1](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[2]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[2]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[2](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[3]
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[3]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[3](n)"
+set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[3](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[4]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[4]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[4]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[4]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[4](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[4](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[4](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[4](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[5]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[5]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[5]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[5]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[5](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[5](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[5](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[5](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[6]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[6]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[6]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[6]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[6](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[6](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[6](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[6](n)"
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[7]
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to PCIE_TX_OUT[7]
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to PCIE_TX_OUT[7]
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to PCIE_TX_OUT[7]
+# set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[7](n)"
+# set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "PCIE_TX_OUT[7](n)"
+# set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "PCIE_TX_OUT[7](n)"
+# set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "PCIE_TX_OUT[7](n)"
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_BANK3D_50MHZ
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name SDC_FILE ../constr/DE5Gen3x4If128.sdc
+set_global_assignment -name VERILOG_FILE ../hdl/DE5Gen3x4If128.v
+set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ohtb.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
+set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
+set_global_assignment -name SIP_FILE ../ip/XCVRCtrlGen3x4.sip
+set_global_assignment -name QIP_FILE ../ip/XCVRCtrlGen3x4.qip
+set_global_assignment -name QIP_FILE ../ip/PCIeGen3x4If128.qip
+set_global_assignment -name SIP_FILE ../ip/PCIeGen3x4If128.sip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

fpga/altera/de5/riffa_wrapper_de5.v

@@ -0,0 +1,614 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            riffa_wrapper_de5.v
+// Version:             1.00a
+// Verilog Standard:    Verilog-2001
+// Description:         Wrapper file for all riffa logic for Altera DE5 boards
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`include "ultrascale.vh"
+`include "functions.vh"
+`timescale 1ps / 1ps
+module riffa_wrapper_de5
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Bit-Width from Quartus IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (
+     // Interface: Altera RX 
+     input [C_PCI_DATA_WIDTH-1:0]                 RX_ST_DATA,
+     input [0:0]                                  RX_ST_EOP,
+     input [0:0]                                  RX_ST_SOP,
+     input [0:0]                                  RX_ST_VALID,
+     output                                       RX_ST_READY,
+     input [0:0]                                  RX_ST_EMPTY,
+
+     // Interface: Altera TX
+     output [C_PCI_DATA_WIDTH-1:0]                TX_ST_DATA,
+     output [0:0]                                 TX_ST_VALID,
+     input                                        TX_ST_READY,
+     output [0:0]                                 TX_ST_EOP,
+     output [0:0]                                 TX_ST_SOP,
+     output [0:0]                                 TX_ST_EMPTY,
+
+     // Interface: Altera Config
+     input [`SIG_CFG_CTL_W-1:0]                   TL_CFG_CTL,
+     input [`SIG_CFG_ADD_W-1:0]                   TL_CFG_ADD,
+     input [`SIG_CFG_STS_W-1:0]                   TL_CFG_STS,
+
+     // Interface: Altera Flow Control
+     input [`SIG_KO_CPLH_W-1:0]                   KO_CPL_SPC_HEADER,
+     input [`SIG_KO_CPLD_W-1:0]                   KO_CPL_SPC_DATA,
+    
+     // Interface: Altera Interrupt
+     input                                        APP_MSI_ACK,
+     output                                       APP_MSI_REQ,
+
+     // Interface: Altera CLK/RESET
+     input                                        PLD_CLK,
+     input                                        RESET_STATUS,
+
+     // RIFFA Interface Signals
+     output                                       RST_OUT,
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_CLK, // Channel read clock
+     output [C_NUM_CHNL-1:0]                      CHNL_RX, // Channel read receive signal
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_ACK, // Channel read received signal
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_LAST, // Channel last read
+     output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
+     output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
+     output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   CHNL_RX_DATA, // Channel read data
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_DATA_VALID, // Channel read data valid
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_DATA_REN, // Channel read data has been recieved
+
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_CLK, // Channel write clock
+     input [C_NUM_CHNL-1:0]                       CHNL_TX, // Channel write receive signal
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_ACK, // Channel write acknowledgement signal
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_LAST, // Channel last write
+     input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]  CHNL_TX_LEN, // Channel write length (in 32 bit words)
+     input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]  CHNL_TX_OFF, // Channel write offset
+     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]    CHNL_TX_DATA, // Channel write data
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_DATA_VALID, // Channel write data valid
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_DATA_REN // Channel write data has been recieved
+
+     );
+    localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
+    localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
+    localparam C_VENDOR = "ALTERA";
+
+    localparam C_ALTERA_TX_READY_LATENCY = 2;
+    localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
+    localparam C_PIPELINE_OUTPUT = 1;
+    localparam C_PIPELINE_INPUT = 1;
+
+    wire                                          clk;
+    wire                                          rst_in;
+
+    // Interface: RXC Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxc_data;
+    wire                                          rxc_data_valid;
+    wire                                          rxc_data_start_flag;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxc_data_word_enable;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxc_meta_fdwbe;
+    wire                                          rxc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxc_meta_ldwbe;
+    wire [`SIG_TAG_W-1:0]                         rxc_meta_tag;
+    wire [`SIG_LOWADDR_W-1:0]                     rxc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        rxc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         rxc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     rxc_meta_bytes_remaining;
+    wire [`SIG_CPLID_W-1:0]                       rxc_meta_completer_id;
+    wire                                          rxc_meta_ep;
+
+    // Interface: RXR Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxr_data;
+    wire                                          rxr_data_valid;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxr_data_word_enable;
+    wire                                          rxr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxr_meta_fdwbe;
+    wire                                          rxr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxr_meta_ldwbe;
+    wire [`SIG_TC_W-1:0]                          rxr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        rxr_meta_attr;
+    wire [`SIG_TAG_W-1:0]                         rxr_meta_tag;
+    wire [`SIG_TYPE_W-1:0]                        rxr_meta_type;
+    wire [`SIG_ADDR_W-1:0]                        rxr_meta_addr;
+    wire [`SIG_BARDECODE_W-1:0]                   rxr_meta_bar_decoded;
+    wire [`SIG_REQID_W-1:0]                       rxr_meta_requester_id;
+    wire [`SIG_LEN_W-1:0]                         rxr_meta_length;
+    wire                                          rxr_meta_ep;
+    
+    // interface: TXC Engine
+    wire                                          txc_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txc_data;
+    wire                                          txc_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_start_offset;
+    wire                                          txc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_end_offset;
+    wire                                          txc_data_ready;
+
+    wire                                          txc_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txc_meta_fdwbe;
+    wire [`SIG_LBE_W-1:0]                         txc_meta_ldwbe;
+    wire [`SIG_LOWADDR_W-1:0]                     txc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        txc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         txc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     txc_meta_byte_count;
+    wire [`SIG_TAG_W-1:0]                         txc_meta_tag;
+    wire [`SIG_REQID_W-1:0]                       txc_meta_requester_id;
+    wire [`SIG_TC_W-1:0]                          txc_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txc_meta_attr;
+    wire                                          txc_meta_ep;
+    wire                                          txc_meta_ready;
+    wire                                          txc_sent;
+
+    // Interface: TXR Engine
+    wire                                          txr_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txr_data;
+    wire                                          txr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_start_offset;
+    wire                                          txr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_end_offset;
+    wire                                          txr_data_ready;
+
+    wire                                          txr_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txr_meta_fdwbe; 
+    wire [`SIG_LBE_W-1:0]                         txr_meta_ldwbe;
+    wire [`SIG_ADDR_W-1:0]                        txr_meta_addr;
+    wire [`SIG_LEN_W-1:0]                         txr_meta_length;
+    wire [`SIG_TAG_W-1:0]                         txr_meta_tag;
+    wire [`SIG_TC_W-1:0]                          txr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txr_meta_attr;
+    wire [`SIG_TYPE_W-1:0]                        txr_meta_type;
+    wire                                          txr_meta_ep;
+    wire                                          txr_meta_ready;
+    wire                                          txr_sent;
+
+    // Classic Interface Wires
+    wire                                          wRxTlpReady;
+    wire [C_PCI_DATA_WIDTH-1:0]                   wRxTlp;
+    wire                                          wRxTlpEndFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wRxTlpEndOffset;
+    wire                                          wRxTlpStartFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wRxTlpStartOffset;
+    wire                                          wRxTlpValid;
+    wire [`SIG_BARDECODE_W-1:0]                   wRxTlpBarDecode;
+    
+    wire                                          wTxTlpReady;
+    wire [C_PCI_DATA_WIDTH-1:0]                   wTxTlp;
+    wire                                          wTxTlpEndFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wTxTlpEndOffset;
+    wire                                          wTxTlpStartFlag;
+    wire [`SIG_OFFSET_W-1:0]                      wTxTlpStartOffset;
+    wire                                          wTxTlpValid;
+    
+    // Unconnected Wires (Used in ultrascale interface)
+    // Interface: RQ (TXC)
+    wire                                          s_axis_rq_tlast_nc;
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_rq_tdata_nc;
+    wire [`SIG_RQ_TUSER_W-1:0]                    s_axis_rq_tuser_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_rq_tkeep_nc;
+    wire                                          s_axis_rq_tready_nc = 0;
+    wire                                          s_axis_rq_tvalid_nc;
+    // Interface: RC (RXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_rc_tdata_nc = 0;
+    wire [`SIG_RC_TUSER_W-1:0]                    m_axis_rc_tuser_nc = 0;
+    wire                                          m_axis_rc_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_rc_tkeep_nc = 0;
+    wire                                          m_axis_rc_tvalid_nc = 0;
+    wire                                          m_axis_rc_tready_nc;
+    // Interface: CQ (RXR)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_cq_tdata_nc = 0;
+    wire [`SIG_CQ_TUSER_W-1:0]                    m_axis_cq_tuser_nc = 0;
+    wire                                          m_axis_cq_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_cq_tkeep_nc = 0;
+    wire                                          m_axis_cq_tvalid_nc = 0;
+    wire                                          m_axis_cq_tready_nc = 0;
+    // Interface: CC (TXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_cc_tdata_nc;
+    wire [`SIG_CC_TUSER_W-1:0]                    s_axis_cc_tuser_nc;
+    wire                                          s_axis_cc_tlast_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_cc_tkeep_nc;
+    wire                                          s_axis_cc_tvalid_nc;
+    wire                                          s_axis_cc_tready_nc = 0;
+
+    // Interface: Configuration
+    wire                                          config_bus_master_enable;
+    wire [`SIG_CPLID_W-1:0]                       config_completer_id;
+    wire                                          config_cpl_boundary_sel;
+    wire                                          config_interrupt_msienable;
+    wire [`SIG_LINKRATE_W-1:0]                    config_link_rate;
+    wire [`SIG_LINKWIDTH_W-1:0]                   config_link_width;
+    wire [`SIG_MAXPAYLOAD_W-1:0]                  config_max_payload_size;
+    wire [`SIG_MAXREAD_W-1:0]                     config_max_read_request_size;
+    wire [`SIG_FC_CPLD_W-1:0]                     config_max_cpl_data;
+    wire [`SIG_FC_CPLH_W-1:0]                     config_max_cpl_hdr;
+
+    wire                                          intr_msi_request;
+    wire                                          intr_msi_rdy;
+
+    genvar                                        chnl;
+
+    assign clk = PLD_CLK;
+    assign rst_in = RESET_STATUS;
+
+    translation_altera
+        #(
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH))
+    trans
+        (
+         // Outputs
+         .RX_TLP                            (wRxTlp[C_PCI_DATA_WIDTH-1:0]),
+         .RX_TLP_VALID                      (wRxTlpValid),
+         .RX_TLP_START_FLAG                 (wRxTlpStartFlag),
+         .RX_TLP_START_OFFSET               (wRxTlpStartOffset[`SIG_OFFSET_W-1:0]),
+         .RX_TLP_END_FLAG                   (wRxTlpEndFlag),
+         .RX_TLP_END_OFFSET                 (wRxTlpEndOffset[`SIG_OFFSET_W-1:0]),
+         .RX_TLP_BAR_DECODE                 (wRxTlpBarDecode[`SIG_BARDECODE_W-1:0]),
+         .TX_TLP_READY                      (wTxTlpReady),
+         .CONFIG_COMPLETER_ID               (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE          (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH                 (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE                  (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE      (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE           (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE        (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL           (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA               (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR                (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+         .INTR_MSI_RDY                      (intr_msi_rdy),
+         // Inputs
+         .CLK                               (clk),
+         .RST_IN                            (rst_in),
+         .RX_TLP_READY                      (wRxTlpReady),
+         .TX_TLP                            (wTxTlp[C_PCI_DATA_WIDTH-1:0]),
+         .TX_TLP_VALID                      (wTxTlpValid),
+         .TX_TLP_START_FLAG                 (wTxTlpStartFlag),
+         .TX_TLP_START_OFFSET               (wTxTlpStartOffset[`SIG_OFFSET_W-1:0]),
+         .TX_TLP_END_FLAG                   (wTxTlpEndFlag),
+         .TX_TLP_END_OFFSET                 (wTxTlpEndOffset[`SIG_OFFSET_W-1:0]),
+         .INTR_MSI_REQUEST                  (intr_msi_request),
+         /*AUTOINST*/
+         // Outputs
+         .RX_ST_READY                   (RX_ST_READY),
+         .TX_ST_DATA                    (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (TX_ST_VALID[0:0]),
+         .TX_ST_EOP                     (TX_ST_EOP[0:0]),
+         .TX_ST_SOP                     (TX_ST_SOP[0:0]),
+         .TX_ST_EMPTY                   (TX_ST_EMPTY[0:0]),
+         .APP_MSI_REQ                   (APP_MSI_REQ),
+         // Inputs
+         .RX_ST_DATA                    (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (RX_ST_EOP[0:0]),
+         .RX_ST_SOP                     (RX_ST_SOP[0:0]),
+         .RX_ST_VALID                   (RX_ST_VALID[0:0]),
+         .RX_ST_EMPTY                   (RX_ST_EMPTY[0:0]),
+         .TX_ST_READY                   (TX_ST_READY),
+         .TL_CFG_CTL                    (TL_CFG_CTL[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (TL_CFG_ADD[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (TL_CFG_STS[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (KO_CPL_SPC_HEADER[`SIG_FC_CPLH_W-1:0]),
+         .KO_CPL_SPC_DATA               (KO_CPL_SPC_DATA[`SIG_FC_CPLD_W-1:0]),
+         .APP_MSI_ACK                   (APP_MSI_ACK));
+
+    engine_layer
+        #(// Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_BYTES/4),
+          .C_VENDOR                     (C_VENDOR))
+    engine_layer_inst
+        (// Outputs
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+         // Unconnected Outputs
+         .TX_TLP                        (wTxTlp),
+         .TX_TLP_VALID                  (wTxTlpValid),
+         .TX_TLP_START_FLAG             (wTxTlpStartFlag),
+         .TX_TLP_START_OFFSET           (wTxTlpStartOffset),
+         .TX_TLP_END_FLAG               (wTxTlpEndFlag),
+         .TX_TLP_END_OFFSET             (wTxTlpEndOffset),
+
+         .RX_TLP_READY                  (wRxTlpReady),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+         // Unconnected Inputs
+         .RX_TLP                        (wRxTlp),
+         .RX_TLP_VALID                  (wRxTlpValid),
+         .RX_TLP_START_FLAG             (wRxTlpStartFlag),
+         .RX_TLP_START_OFFSET           (wRxTlpStartOffset),
+         .RX_TLP_END_FLAG               (wRxTlpEndFlag),
+         .RX_TLP_END_OFFSET             (wRxTlpEndOffset),
+         .RX_TLP_BAR_DECODE             (wRxTlpBarDecode),
+
+         .TX_TLP_READY                  (wTxTlpReady),
+         // Outputs
+         .M_AXIS_CQ_TREADY              (m_axis_cq_tready_nc),
+         .M_AXIS_RC_TREADY              (m_axis_rc_tready_nc),
+         .S_AXIS_CC_TVALID              (s_axis_cc_tvalid_nc),
+         .S_AXIS_CC_TLAST               (s_axis_cc_tlast_nc),
+         .S_AXIS_CC_TDATA               (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (s_axis_rq_tvalid_nc),
+         .S_AXIS_RQ_TLAST               (s_axis_rq_tlast_nc),
+         .S_AXIS_RQ_TDATA               (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (m_axis_cq_tvalid_nc),
+         .M_AXIS_CQ_TLAST               (m_axis_cq_tlast_nc),
+         .M_AXIS_CQ_TDATA               (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (m_axis_rc_tvalid_nc),
+         .M_AXIS_RC_TLAST               (m_axis_rc_tlast_nc),
+         .M_AXIS_RC_TDATA               (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (s_axis_cc_tready_nc),
+         .S_AXIS_RQ_TREADY              (s_axis_rq_tready_nc)
+         /*AUTOINST*/);
+
+    riffa
+        #(.C_TAG_WIDTH                  (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_MAX_READ_REQ_BYTES         (C_MAX_READ_REQ_BYTES),
+          .C_VENDOR                     (C_VENDOR),
+          .C_FPGA_NAME                  (C_FPGA_NAME))
+    riffa_inst
+        (// Outputs
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+
+         .INTR_MSI_REQUEST              (intr_msi_request),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),         
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE      (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH             (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE              (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE  (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE       (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE    (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL       (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA           (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR            (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+        
+         .INTR_MSI_RDY                  (intr_msi_rdy),
+
+         /*AUTOINST*/
+         // Outputs
+         .RST_OUT                       (RST_OUT),
+         .CHNL_RX                       (CHNL_RX[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_RX_OFF                   (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_RX_DATA                  (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
+         // Inputs
+         .CHNL_RX_CLK                   (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (CHNL_TX[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_TX_OFF                   (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_TX_DATA                  (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("../../engine/" "../../riffa/" "../../trans")
+// End:
+

fpga/altera/de5_qsys/DE5Gen1x8If64/constr/DE5Gen1x8If64.sdc

@@ -0,0 +1,95 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            DE5Gen1x8If64.sdc (Qsys)
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Synopsys Design Constraints for the DE5 board.
+# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}]
+create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}]
+
+################################################################################
+# 13.1 Workround for http://www.altera.com/support/kdb/solutions/rd12162013_581.html?GSA_pos=1&WT.oss_r=1&WT.oss=adce_off_r
+################################################################################
+
+# set_false_path -to [get_registers *|*.adce_off_r[0]]
+# set_false_path -to [get_registers *|*.adce_on_rr[0]]
+# set_false_path -to [get_registers *|reset_sync_pldclk_r[*]]
+
+################################################################################
+# End Workround 
+################################################################################
+
+derive_pll_clocks -create_base_clocks
+derive_clock_uncertainty
+
+################################################################################
+# Imports from Example Design (altera/13.1/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/)
+################################################################################
+
+######################################################################
+# HIP Soft reset controller SDC constraints (Gen 3 only)
+set_false_path -to   [get_registers *altpcie_rs_serdes|fifo_err_sync_r[0]]
+set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*]
+
+# HIP testin pins SDC constraints
+set_false_path -from [get_pins -compatibility_mode *hip_ctrl*]
+
+######################################################################
+# Constraints for CV SIG asynchonous logic
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_wr_clk}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_req_rd_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_in_d0[*]}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_tls|altpcie_hip_vecsync:altpcie_hip_vecsync2|data_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|req_rd_clk_d0}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hip_eq_dprio:sigtesten.hip_eq_dprio_inst|altpcie_hip_vecsync2:vecsync_ltssm|altpcie_hip_vecsync:altpcie_hip_vecsync2|altpcie_hip_bitsync:u_ack_wr_clk|sync_regs[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|test_out[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqout[*]}]
+                                                                                                                                                
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_eqber[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_lf[*]}]
+
+set_false_path -from [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG122}] -to [get_keepers {*|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|hd_altpe3_hip_eq_bypass_ph3:sigtesten.ep_eq_bypass_ph3_inst|test_dbg_farend_fs[*]}]

fpga/altera/de5_qsys/DE5Gen1x8If64/hdl/DE5Gen1x8If64.v

@@ -0,0 +1,369 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            DE5Gen1x8If64.v
+// Version:             
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Altera Stratix V Avalong Streaming Interface to PCI
+//                      Express module and the Terasic DE5 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "altera.vh"
+`timescale 1ps / 1ps
+module DE5Gen1x8If64
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 12,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Quartus IP Library
+      parameter C_PCI_DATA_WIDTH = 64,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      )
+    (
+     // ----------LEDs----------
+     output [7:0]            LED,
+
+     // ----------PCIE----------
+     input                   PCIE_RESET_N,
+     input                   PCIE_REFCLK,
+
+     // ----------PCIE Serial RX----------
+     input [C_NUM_LANES-1:0] PCIE_RX_IN,
+
+     // ----------PCIE Serial TX----------
+     output [C_NUM_LANES-1:0]  PCIE_TX_OUT,
+
+     // ----------Oscillators----------
+     input                   OSC_BANK3D_50MHZ
+     );
+
+    wire                     npor;
+    wire                     pin_perst;
+
+    // ----------TL Config interface----------
+    wire [3:0]               tl_cfg_add;
+    wire [31:0]              tl_cfg_ctl;
+    wire [52:0]              tl_cfg_sts;
+
+    // ----------Rx/TX Interfaces----------
+    wire [0:0]               rx_st_sop;
+    wire [0:0]               rx_st_eop;
+    wire [0:0]               rx_st_err;
+    wire [0:0]               rx_st_valid;
+    wire                     rx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0] rx_st_data;
+    wire [0:0]                  rx_st_empty;
+    
+    wire [0:0]                  tx_st_sop;
+    wire [0:0]                  tx_st_eop;
+    wire [0:0]                  tx_st_err;
+    wire [0:0]                  tx_st_valid;
+    wire                        tx_st_ready;
+    wire [C_PCI_DATA_WIDTH-1:0] tx_st_data;
+    wire [0:0]                  tx_st_empty;
+    
+    // ----------Clocks & Locks----------
+    wire                        pld_clk;
+    wire                        coreclkout_hip;
+    wire                        refclk;
+    wire                        pld_core_ready;
+    wire                        reset_status;
+    wire                        serdes_pll_locked;
+
+    // ----------Interrupt Interfaces----------
+    wire                        app_msi_req;
+    wire                        app_msi_ack;
+    
+    // ----------Reconfiguration Controller signals----------
+    wire                        mgmt_clk_clk;
+    wire                        mgmt_rst_reset;
+
+    // ----------Reconfiguration Driver Signals----------
+    wire                        reconfig_xcvr_clk;
+    wire                        reconfig_xcvr_rst;
+
+    wire [7:0]                  rx_in;
+    wire [7:0]                  tx_out;
+    
+    // ------------Status Interface------------
+    wire                        derr_cor_ext_rcv;
+    wire                        derr_cor_ext_rpl;
+    wire                        derr_rpl;
+    wire                        dlup;
+    wire                        dlup_exit;
+    wire                        ev128ns;
+    wire                        ev1us;
+    wire                        hotrst_exit;
+    wire [3:0]                  int_status;
+    wire                        l2_exit;
+    wire [3:0]                  lane_act;
+    wire [4:0]                  ltssmstate;
+    wire                        rx_par_err;
+    wire [1:0]                  tx_par_err;
+    wire                        cfg_par_err;
+    wire [7:0]                  ko_cpl_spc_header;
+    wire [11:0]                 ko_cpl_spc_data;
+
+    // ----------Clocks----------
+    assign pld_clk = coreclkout_hip;
+    assign mgmt_clk_clk = PCIE_REFCLK;
+    assign reconfig_xcvr_clk = PCIE_REFCLK;
+    assign refclk = PCIE_REFCLK;
+    assign pld_core_ready = serdes_pll_locked;
+    
+    // ----------Resets----------
+    assign reconfig_xcvr_rst = 1'b0;
+    assign mgmt_rst_reset = 1'b0;
+    assign pin_perst = PCIE_RESET_N;
+    assign npor = PCIE_RESET_N;
+
+    // ----------LED's----------
+    assign LED[7:0] = 8'hff;
+    QSysDE5Gen1x8If64
+        pcie_system_inst
+            (
+             // Outputs
+             .rx_st_startofpacket              (rx_st_sop[0:0]),
+             .rx_st_endofpacket                (rx_st_eop[0:0]),
+             .rx_st_valid                      (rx_st_valid[0:0]),
+             .rx_st_data                       (rx_st_data[63:0]),
+             .tx_st_ready                      (tx_st_ready),
+             .pciehip_reset_status             (reset_status),
+             .pciehip_serdes_pll_locked        (serdes_pll_locked),
+             .pciecfg_tl_cfg_add               (tl_cfg_add[3:0]),
+             .pciecfg_tl_cfg_ctl               (tl_cfg_ctl[31:0]),
+             .pciecfg_tl_cfg_sts               (tl_cfg_sts[52:0]),
+             .pciecoreclk_clk                  (coreclkout_hip),
+             .pcieserial_tx_out0               (PCIE_TX_OUT[0]),
+             .pcieserial_tx_out1               (PCIE_TX_OUT[1]),
+             .pcieserial_tx_out2               (PCIE_TX_OUT[2]),
+             .pcieserial_tx_out3               (PCIE_TX_OUT[3]),
+             .pcieserial_tx_out4               (PCIE_TX_OUT[4]),
+             .pcieserial_tx_out5               (PCIE_TX_OUT[5]),
+             .pcieserial_tx_out6               (PCIE_TX_OUT[6]),
+             .pcieserial_tx_out7               (PCIE_TX_OUT[7]),
+             .pciemsi_app_int_ack              (app_int_ack),
+             .pciemsi_app_msi_ack              (app_msi_ack),
+             .pciestat_derr_cor_ext_rcv        (derr_cor_ext_rcv),
+             .pciestat_derr_cor_ext_rpl        (derr_cor_ext_rpl),
+             .pciestat_derr_rpl                (derr_rpl),
+             .pciestat_dlup                    (dlup),
+             .pciestat_dlup_exit               (dlup_exit),
+             .pciestat_ev128ns                 (ev128ns),
+             .pciestat_ev1us                   (ev1us),
+             .pciestat_hotrst_exit             (hotrst_exit),
+             .pciestat_int_status              (int_status),
+             .pciestat_l2_exit                 (l2_exit),
+             .pciestat_lane_act                (lane_act),
+             .pciestat_ltssmstate              (ltssmstate),
+             .pciestat_rx_par_err              (rx_par_err),
+             .pciestat_tx_par_err              (tx_par_err),
+             .pciestat_cfg_par_err             (cfg_par_err),
+             .pciestat_ko_cpl_spc_header       (ko_cpl_spc_header),
+             .pciestat_ko_cpl_spc_data         (ko_cpl_spc_data),
+             // Inputs
+             .rx_st_ready                      (rx_st_ready),
+             .tx_st_startofpacket              (tx_st_sop[0:0]),
+             .tx_st_endofpacket                (tx_st_eop[0:0]),
+             .tx_st_valid                      (tx_st_valid[0:0]),
+             .tx_st_data                       (tx_st_data[63:0]),
+             .pciehip_pld_core_ready           (pld_core_ready),
+             .pcienpor_npor                    (npor),
+             .pcienpor_pin_perst               (pin_perst),
+             .pcierefclk_clk                   (refclk),
+             .reconfigrefclk_clk               (reconfig_xcvr_clk),
+             .pciepld_clk                      (pld_clk),
+             .reconfigrst_reset                (reconfig_xcvr_rst),
+             .mgmtrst_reset                    (mgmt_rst_reset),
+             .mgmtclk_clk                      (mgmt_clk_clk),
+             .reconfigpldclk_clk               (pld_clk),
+             .pcieserial_rx_in0                (PCIE_RX_IN[0]),
+             .pcieserial_rx_in1                (PCIE_RX_IN[1]),
+             .pcieserial_rx_in2                (PCIE_RX_IN[2]),
+             .pcieserial_rx_in3                (PCIE_RX_IN[3]),
+             .pcieserial_rx_in4                (PCIE_RX_IN[4]),
+             .pcieserial_rx_in5                (PCIE_RX_IN[5]),
+             .pcieserial_rx_in6                (PCIE_RX_IN[6]),
+             .pcieserial_rx_in7                (PCIE_RX_IN[7]),
+             .pciemsi_app_msi_req              (app_msi_req),
+             .drvstat_derr_cor_ext_rcv         (derr_cor_ext_rcv),
+             .drvstat_derr_cor_ext_rpl         (derr_cor_ext_rpl),
+             .drvstat_derr_rpl                 (derr_rpl),
+             .drvstat_dlup                     (dlup),
+             .drvstat_dlup_exit                (dlup_exit),
+             .drvstat_ev128ns                  (ev128ns),
+             .drvstat_ev1us                    (ev1us),
+             .drvstat_hotrst_exit              (hotrst_exit),
+             .drvstat_int_status               (int_status),
+             .drvstat_l2_exit                  (l2_exit),
+             .drvstat_lane_act                 (lane_act),
+             .drvstat_ltssmstate               (ltssmstate),
+             .drvstat_rx_par_err               (rx_par_err),
+             .drvstat_tx_par_err               (tx_par_err),
+             .drvstat_cfg_par_err              (cfg_par_err),
+             .drvstat_ko_cpl_spc_header        (ko_cpl_spc_header),
+             .drvstat_ko_cpl_spc_data          (ko_cpl_spc_data));
+
+    // -------------------- END ALTERA IP INSTANTIATION  --------------------
+    // -------------------- BEGIN RIFFA INSTANTAION --------------------
+
+    // RIFFA channel interface
+    wire                        rst_out;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_clk;
+    wire [C_NUM_CHNL-1:0]       chnl_rx;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_ack;
+    wire [C_NUM_CHNL-1:0]       chnl_rx_last;
+    wire [(C_NUM_CHNL*32)-1:0]  chnl_rx_len;
+    wire [(C_NUM_CHNL*31)-1:0]  chnl_rx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_rx_data_ren;
+    
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_clk;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_last;
+    wire [(C_NUM_CHNL*32)-1:0]               chnl_tx_len;
+    wire [(C_NUM_CHNL*31)-1:0]               chnl_tx_off;
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_valid;
+    wire [C_NUM_CHNL-1:0]                    chnl_tx_data_ren;
+
+    wire                                     chnl_reset;
+    wire                                     chnl_clk;
+    wire                                     riffa_reset;
+    wire                                     riffa_clk;
+    assign riffa_reset = reset_status;
+    assign riffa_clk = pld_clk;
+    assign chnl_clk = pld_clk;
+    assign chnl_reset = rst_out;
+    
+    riffa_wrapper_de5
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .RX_ST_READY                   (rx_st_ready),
+         .TX_ST_DATA                    (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .TX_ST_VALID                   (tx_st_valid[0:0]),
+         .TX_ST_EOP                     (tx_st_eop[0:0]),
+         .TX_ST_SOP                     (tx_st_sop[0:0]),
+         .TX_ST_EMPTY                   (tx_st_empty[0:0]),
+         .APP_MSI_REQ                   (app_msi_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .RX_ST_DATA                    (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
+         .RX_ST_EOP                     (rx_st_eop[0:0]),
+         .RX_ST_SOP                     (rx_st_sop[0:0]),
+         .RX_ST_VALID                   (rx_st_valid[0:0]),
+         .RX_ST_EMPTY                   (rx_st_empty[0:0]),
+         .TX_ST_READY                   (tx_st_ready),
+         .TL_CFG_CTL                    (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
+         .TL_CFG_ADD                    (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
+         .TL_CFG_STS                    (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
+         .KO_CPL_SPC_HEADER             (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]),
+         .KO_CPL_SPC_DATA               (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]),
+         .APP_MSI_ACK                   (app_msi_ack),
+         .PLD_CLK                       (pld_clk),
+         .RESET_STATUS                  (reset_status),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
+
+    // --------------------  END RIFFA INSTANTAION --------------------
+    // --------------------  BEGIN USER CODE  --------------------
+    genvar                                   i;
+    generate
+        for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
+            // Instantiate and assign modules to RIFFA channels. Users should 
+            // replace the chnl_tester instantiation with their own core.
+            chnl_tester 
+                 #(
+                   .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                   )
+            chnl_tester_i
+                 (
+
+                  .CLK(chnl_clk),
+                  .RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
+                  // Rx interface
+                  .CHNL_RX_CLK(chnl_rx_clk[i]), 
+                  .CHNL_RX(chnl_rx[i]), 
+                  .CHNL_RX_ACK(chnl_rx_ack[i]), 
+                  .CHNL_RX_LAST(chnl_rx_last[i]), 
+                  .CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]), 
+                  .CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
+                  // Tx interface
+                  .CHNL_TX_CLK(chnl_tx_clk[i]), 
+                  .CHNL_TX(chnl_tx[i]), 
+                  .CHNL_TX_ACK(chnl_tx_ack[i]), 
+                  .CHNL_TX_LAST(chnl_tx_last[i]), 
+                  .CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]), 
+                  .CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]), 
+                  .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]), 
+                  .CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]), 
+                  .CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
+                  );    
+        end
+    endgenerate
+    // --------------------  END USER CODE  --------------------
+endmodule

fpga/altera/de5_qsys/DE5Gen1x8If64/ip/.qsys_edit/filters.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="14.1" />

fpga/altera/de5_qsys/DE5Gen1x8If64/ip/.qsys_edit/preferences.xml

@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <debug showDebugMenu="0" />
+ <systemtable filter="All Interfaces">
+  <columns>
+   <connections preferredWidth="143" />
+   <irq preferredWidth="34" />
+  </columns>
+ </systemtable>
+ <library expandedCategories="Project,Library" />
+ <window width="1682" height="1050" x="-1" y="0" />
+</preferences>