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Mega-commit (which I usually like to avoid, but this one didn't really come cleanly)

Browse Source 
The majority of this work can be summarized as: Makefiles have been added to
generate all of the boards, boards for each vendor, board, and projects for each
board.

To make things cleaner I renamed a few of the Xilinx projects, and may rename
the latera projects for consistency.

I removed the de5_qsys directory, and moved all projects into the de5 directory,
but those projects have a Q between DE5 and the PCIe specifications, ie
DE5QGen... (haven't updated the documentation)

Added c4dev board (untested)

Apologies to those of you who recently switched onto the DEVEL branch.
This commit is contained in:
Dustin Richmond 2016-01-20 17:46:39 -08:00
parent c209dac5d3
commit ad496b4c94
181 changed files with 2554 additions and 16069 deletions
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60
fpga/Makefile Normal file
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# ----------------------------------------------------------------------
# Copyright (c) 2015, The Regents of the University of California All
# rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
#
# * Redistributions in binary form must reproduce the above
# copyright notice, this list of conditions and the following
# disclaimer in the documentation and/or other materials provided
# with the distribution.
#
# * Neither the name of The Regents of the University of California
# nor the names of its contributors may be used to endorse or
# promote products derived from this software without specific
# prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
# DAMAGE.
# ----------------------------------------------------------------------
#include common.mk
MKPATH:=$(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
RIFFA_PATH:=$(MKPATH)/riffa_hdl
VENDORS:= xilinx altera
SUBDIRS = $(VENDORS)
all: $(VENDORS)
$(VENDORS)::
$(MAKE) -C $@ $(MAKECMDGOALS) RIFFA_PATH=$(RIFFA_PATH)
.PHONY:clean $(SUBDIRS)
clean: $(VENDORS)
rm -rf *~

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fpga/altera/Makefile Normal file
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VENDOR:=altera
CLASSIC:=de5 de4 de2i c4dev
CURRENT_PATH := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
RIFFA_PATH=$(CURRENT_PATH)/../riffa_hdl
all: $(VENDOR)
classic:$(CLASSIC)
$(VENDOR): $(CLASSIC)
$(CLASSIC)::
$(MAKE) -C $@ $(MAKECMDGOALS) RIFFA_PATH=$(RIFFA_PATH)
.PHONY:clean $(SUBDIRS)
clean: $(VENDOR)
rm -rf *~ .qsys_edit

23
fpga/altera/c4dev/C4DevGen1x4If64/Makefile Normal file
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# This make file expects the following variables to be set:
# RIFFA_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory.
# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to
# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory
WIDTH=64
TYPE=classic
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=ip/ALTGXPCIeGen1x4.qip ip/ALTPLL50I50O125O250O.qip ip/PCIeGen1x4If64.qip

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fpga/altera/c4dev/C4DevGen1x4If64/constr/C4DevGen1x4If64.sdc Normal file
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# Oscillator Clocks
create_clock -name CLK1_50 -period 20 [get_ports {CLK1_50}]
create_clock -name CLK2_50 -period 20 [get_ports {CLK2_50}]
create_clock -name CLK3_50 -period 20 [get_ports {CLK3_50}]
# Refclk (100 MHz differential input)
create_clock -period "100 MHz" -name {refclk} [get_ports {PCIE_REFCLK}]
# 50 MHZ PLL Clock
create_generated_clock -name clk50 -source [get_ports {CLK1_50}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[0]}]
# 125 MHZ PLL Clock
create_generated_clock -name clk125 -multiply_by 5 -divide_by 2 -source [get_ports {CLK1_50}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[1]}]
# 250 MHZ PLL Clock
create_generated_clock -name clk250 -multiply_by 5 -source [get_ports {CLK1_50}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[2]}]
derive_pll_clocks
derive_clock_uncertainty
# Imported from IP Compiler user guide
set_clock_groups -exclusive -group [get_clocks { refclk*clkout }] -group [get_clocks { *div0*coreclkout}]
set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }] -group [get_clocks { *central_clk_div1* }]

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fpga/altera/c4dev/C4DevGen1x4If64/hdl/C4DevGen1x4If64.v Normal file
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// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: C4DevGen1x4If64.v
// Version:
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Altera Cyclone IV IP Compiler for PCI Express
// module and the Terasic DE2i Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "functions.vh"
`include "riffa.vh"
`include "altera.vh"
module C4DevGen1x4If64
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 4,
// Settings from Quartus IP Library
parameter C_PCI_DATA_WIDTH = 64,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5)
(input CLK1_50,
input PCIE_RESET_N,
input PCIE_REFCLK,
input [C_NUM_LANES-1:0] PCIE_RX_IN,
output [C_NUM_LANES-1:0] PCIE_TX_OUT,
// ----------LEDs ----------
output [7:0] LED_G);
// ----------PLL Signals----------
wire clk50;
wire clk125;
wire clk250;
wire locked;
wire inclk0;
// ----------PCIe Core Signals----------
// ----------PCIe Clocks----------
wire pld_clk;
wire reconfig_clk;
wire core_clk_out;
wire fixedclk_serdes;
wire refclk;
wire rc_pll_locked;
wire cal_blk_clk;
// ----------PCIe Resets----------
wire [ 4: 0] pex_msi_num;
wire pll_powerdown;
wire reset_status;
wire crst;
wire npor;
wire srst;
wire gxb_powerdown;
// ----------PCIe Transaction layer configuration ----------
wire [ 3: 0] tl_cfg_add;
wire [ 31: 0] tl_cfg_ctl;
wire tl_cfg_ctl_wr;
wire [ 52: 0] tl_cfg_sts;
wire tl_cfg_sts_wr;
wire [ 19: 0] ko_cpl_spc_vc0;
// ----------PCIe Local Management Interface----------
wire lmi_ack;
wire [ 31: 0] lmi_dout;
wire [ 11: 0] lmi_addr;
wire [ 31: 0] lmi_din;
wire lmi_rden;
wire lmi_wren;
// ----------PCIe Interrupt Interface ----------
wire app_int_ack;
wire app_msi_ack;
wire app_int_sts;
wire app_msi_req;
// ----------PCIe Status Signals----------
wire hotrst_exit;
wire l2_exit;
wire [3:0] lane_act;
wire [4:0] ltssm;
wire pme_to_sr;
wire suc_spd_neg;
// ----------PCIe RX Interface----------
wire rx_st_mask0;
wire [ 7: 0] rx_st_bardec0;
wire [ 15: 0] rx_st_be0;
wire [0:0] rx_st_sop0;
wire [0:0] rx_st_eop0;
wire [0:0] rx_st_err0;
wire [0:0] rx_st_valid0;
wire [0:0] rx_st_empty0;
wire rx_st_ready0;
wire [C_PCI_DATA_WIDTH-1:0] rx_st_data0;
// ----------PCIe TX Interface----------
wire [0:0] tx_st_sop0;
wire [0:0] tx_st_eop0;
wire [0:0] tx_st_err0;
wire [0:0] tx_st_valid0;
wire [0:0] tx_st_empty0;
wire tx_st_ready0;
wire [C_PCI_DATA_WIDTH-1:0] tx_st_data0;
// ----------ALTGX Signals----------
wire busy;
wire busy_altgxb_reconfig;
wire [4:0] reconfig_fromgxb;
wire [3:0] reconfig_togxb;
// ----------Resets ----------
reg [4:0] rRstCtr,_rRstCtr;
reg [2:0] rRstSync,_rRstSync;
wire wSyncRst;
always @(*) begin
_rRstSync = {rRstSync[1:0], ~npor};
_rRstCtr = rRstCtr;
if (rRstSync[2]) begin
_rRstCtr = 0;
end else if (~rRstCtr[4]) begin
_rRstCtr = rRstCtr + 1;
end
end
always @(posedge pld_clk) begin
rRstSync <= _rRstSync;
rRstCtr <= _rRstCtr;
end
assign wSyncRst = ~ rRstCtr[4];
assign srst = wSyncRst;
assign crst = wSyncRst;
// ----------PLL assignments----------
assign inclk0 = CLK1_50;
assign fixedclk_serdes = clk125;
assign reconfig_clk = clk50;
// ----------PCIe Resets----------
assign npor = PCIE_RESET_N;
assign gxb_powerdown = ~ npor;
assign pll_powerdown = ~ npor;
// ----------PCIe Clocks / PLLs----------
assign refclk = PCIE_REFCLK;
assign pld_clk = core_clk_out;
assign cal_blk_clk = reconfig_clk;
// ----------ALTGX----------
assign busy = busy_altgxb_reconfig;
// -------------------- BEGIN ALTERA IP INSTANTIATION --------------------
ALTPLL50I50O125O250O ALTPLL50I50O125O250O_inst
(
// Outputs
.c0 (clk50),
.c1 (clk125),
.c2 (clk250),
.locked (locked),
// Inputs
.inclk0 (inclk0));
ALTGXPCIeGen1x4
altgx_inst
(
// Outputs
.busy (busy),
.reconfig_togxb (reconfig_togxb[3:0]),
// Inputs
.reconfig_clk (reconfig_clk),
.reconfig_fromgxb (reconfig_fromgxb[4:0]));
PCIeGen1x4If64
pcie_inst
(
// Outputs
.app_int_ack (app_int_ack),
.app_msi_ack (app_msi_ack),
.core_clk_out (core_clk_out),
.hotrst_exit (hotrst_exit),
.l2_exit (l2_exit),
.lane_act (lane_act[3:0]),
.lmi_ack (lmi_ack),
.lmi_dout (lmi_dout[31:0]),
.ltssm (ltssm[4:0]),
.rc_pll_locked (rc_pll_locked),
.reconfig_fromgxb (reconfig_fromgxb[4:0]),
.reset_status (reset_status),
.rx_st_bardec0 (rx_st_bardec0[7:0]),
.rx_st_be0 (rx_st_be0[7:0]),
.rx_st_data0 (rx_st_data0[C_PCI_DATA_WIDTH-1:0]),
.rx_st_eop0 (rx_st_eop0),
.rx_st_err0 (rx_st_err0),
.rx_st_sop0 (rx_st_sop0),
.rx_st_valid0 (rx_st_valid0),
.suc_spd_neg (suc_spd_neg),// Gen 2 successful
.tl_cfg_add (tl_cfg_add[3:0]),
.tl_cfg_ctl (tl_cfg_ctl[31:0]),
.tl_cfg_ctl_wr (tl_cfg_ctl_wr),
.tl_cfg_sts (tl_cfg_sts[52:0]),
.tl_cfg_sts_wr (tl_cfg_sts_wr),
.ko_cpl_spc_vc0 (ko_cpl_spc_vc0),
.tx_out0 (PCIE_TX_OUT[0]),
.tx_out1 (PCIE_TX_OUT[1]),
.tx_out2 (PCIE_TX_OUT[2]),
.tx_out3 (PCIE_TX_OUT[3]),
.tx_st_ready0 (tx_st_ready0),
// Inputs
.app_int_sts (app_int_sts),
.app_msi_num (5'b00000),
.app_msi_req (app_msi_req),
.app_msi_tc (3'b000),
.busy_altgxb_reconfig (busy_altgxb_reconfig),
.cal_blk_clk (cal_blk_clk),
.crst (crst),
.fixedclk_serdes (fixedclk_serdes),
.gxb_powerdown (gxb_powerdown),
.pll_powerdown (pll_powerdown),
.lmi_addr (lmi_addr[11:0]),
.lmi_din (lmi_din[31:0]),
.lmi_rden (lmi_rden),
.lmi_wren (lmi_wren),
.npor (npor),
.pex_msi_num (pex_msi_num[4:0]),
.pld_clk (pld_clk),
.reconfig_clk (reconfig_clk),
.reconfig_togxb (reconfig_togxb[3:0]),
.refclk (refclk),
.rx_in0 (PCIE_RX_IN[0]),
.rx_in1 (PCIE_RX_IN[1]),
.rx_in2 (PCIE_RX_IN[2]),
.rx_in3 (PCIE_RX_IN[3]),
.rx_st_ready0 (rx_st_ready0),
.srst (srst),
.tx_st_data0 (tx_st_data0[C_PCI_DATA_WIDTH-1:0]),
.tx_st_eop0 (tx_st_eop0),
.tx_st_err0 (tx_st_err0),
.tx_st_sop0 (tx_st_sop0),
.tx_st_valid0 (tx_st_valid0));
// -------------------- END ALTERA IP INSTANTIATION --------------------
// -------------------- BEGIN RIFFA INSTANTAION --------------------
// ----------RIFFA channel interface----------
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
wire chnl_reset;
wire chnl_clk;
wire rst_out;
assign chnl_clk = pld_clk;
assign chnl_reset = rst_out;
riffa_wrapper_c4dev
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(// Outputs
.RX_ST_READY (rx_st_ready0),
.TX_ST_DATA (tx_st_data0[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (tx_st_valid0[0:0]),
.TX_ST_EOP (tx_st_eop0[0:0]),
.TX_ST_SOP (tx_st_sop0[0:0]),
.TX_ST_EMPTY (tx_st_empty0[0:0]),
.APP_MSI_REQ (app_msi_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.RX_ST_DATA (rx_st_data0[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (rx_st_eop0[0:0]),
.RX_ST_SOP (rx_st_sop0[0:0]),
.RX_ST_VALID (rx_st_valid0[0:0]),
.RX_ST_EMPTY (rx_st_empty0[0:0]),
.TX_ST_READY (tx_st_ready0),
.TL_CFG_CTL (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
.TL_CFG_ADD (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
.TL_CFG_STS (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
.KO_CPL_SPC_HEADER (ko_cpl_spc_vc0[7:0]),
.KO_CPL_SPC_DATA (ko_cpl_spc_vc0[19:8]),
.APP_MSI_ACK (app_msi_ack),
.PLD_CLK (pld_clk),
.RESET_STATUS (reset_status),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
// -------------------- END RIFFA INSTANTAION --------------------
// -------------------- BEGIN USER CODE --------------------
genvar i;
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
// Instantiate and assign modules to RIFFA channels. Users should
// replace the chnl_tester instantiation with their own core.
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_i
(.CLK(chnl_clk),
.RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[i]),
.CHNL_RX(chnl_rx[i]),
.CHNL_RX_ACK(chnl_rx_ack[i]),
.CHNL_RX_LAST(chnl_rx_last[i]),
.CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]),
.CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[i]),
.CHNL_TX(chnl_tx[i]),
.CHNL_TX_ACK(chnl_tx_ack[i]),
.CHNL_TX_LAST(chnl_tx_last[i]),
.CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]),
.CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[i]));
end
endgenerate
// -------------------- END USER CODE --------------------
endmodule // DE2i_PCIe

6
fpga/altera/de5_qsys/DE5Gen2x8If128/prj/DE5Gen2x8If128.qpf → fpga/altera/c4dev/C4DevGen1x4If64/prj/C4DevGen1x4If64.qpf
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@ -18,13 +18,13 @@
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
# Date created = 16:15:54 June 09, 2014
# Date created = 12:52:42 March 20, 2014
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "16:15:54 June 09, 2014"
DATE = "12:52:42 March 20, 2014"
# Revisions
PROJECT_REVISION = "DE5Gen2x8If128"
PROJECT_REVISION = "C4DevGen1x4If64"

277
fpga/altera/c4dev/C4DevGen1x4If64/prj/C4DevGen1x4If64.qsf Normal file
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@ -0,0 +1,277 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
# Date created = 12:52:42 March 20, 2014
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# C4DevGen1x4If64_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV GX"
set_global_assignment -name DEVICE EP4CGX150DF31C7
set_global_assignment -name TOP_LEVEL_ENTITY C4DevGen1x4If64
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:52:42 MARCH 20, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "14.1.0 SP0.19"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
################################################################################
#Clocks
################################################################################
set_instance_assignment -name IO_STANDARD "1.8 V" -to CLK1_50
set_location_assignment PIN_AK16 -to CLK1_50
################################################################################
#PCIE -- Clocks, Resets
################################################################################
set_instance_assignment -name IO_STANDARD "1.8 V" -to PCIE_RESET_N
set_location_assignment PIN_A7 -to PCIE_RESET_N
set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK
set_location_assignment PIN_V15 -to PCIE_REFCLK
set_instance_assignment -name IO_STANDARD "1.8 V" -to PCIE_WAKE
set_location_assignment IOBANK8 -to PCIE_WAKE
################################################################################
#PCIE RX_IN 0
################################################################################
set_location_assignment PIN_AC2 -to PCIE_RX_IN[0]
set_location_assignment PIN_AC1 -to "PCIE_RX_IN[0](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[0]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[0](n)"
################################################################################
#PCIE RX_IN 1
################################################################################
set_location_assignment PIN_AA2 -to PCIE_RX_IN[1]
set_location_assignment PIN_AA1 -to "PCIE_RX_IN[1](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[1]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[1](n)"
################################################################################
#PCIE RX_IN 2
################################################################################
set_location_assignment PIN_W2 -to PCIE_RX_IN[2]
set_location_assignment PIN_W1 -to "PCIE_RX_IN[2](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[2]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[2](n)"
################################################################################
#PCIE RX_IN 3
################################################################################
set_location_assignment PIN_U2 -to PCIE_RX_IN[3]
set_location_assignment PIN_U1 -to "PCIE_RX_IN[3](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_IN[3]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_RX_IN[3](n)"
################################################################################
#PCIE TX_OUT 0
################################################################################
set_location_assignment PIN_AB4 -to PCIE_TX_OUT[0]
set_location_assignment PIN_AB3 -to "PCIE_TX_OUT[0](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[0]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[0](n)"
################################################################################
#PCIE TX_OUT 1
################################################################################
set_location_assignment PIN_Y4 -to PCIE_TX_OUT[1]
set_location_assignment PIN_Y3 -to "PCIE_TX_OUT[1](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[1]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[1](n)"
################################################################################
#PCIE TX_OUT 2
################################################################################
set_location_assignment PIN_V4 -to PCIE_TX_OUT[2]
set_location_assignment PIN_V3 -to "PCIE_TX_OUT[2](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[2]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[2](n)"
################################################################################
#PCIE TX_OUT 3
################################################################################
set_location_assignment PIN_T4 -to PCIE_TX_OUT[3]
set_location_assignment PIN_T3 -to "PCIE_TX_OUT[3](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_OUT[3]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "PCIE_TX_OUT[3](n)"
################################################################################
# Green LED's
################################################################################
set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[4]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[5]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[6]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_G[7]
set_location_assignment PIN_E4 -to LED_G[0]
set_location_assignment PIN_C7 -to LED_G[1]
set_location_assignment PIN_A4 -to LED_G[2]
set_location_assignment PIN_F6 -to LED_G[3]
set_location_assignment PIN_D4 -to LED_G[4]
set_location_assignment PIN_J9 -to LED_G[5]
set_location_assignment PIN_D12 -to LED_G[6]
set_location_assignment PIN_B6 -to LED_G[7]
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name QIP_FILE ../ip/PCIeGen1x4If64.qip
set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_c4dev.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_extender.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_channel_gate_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/shiftreg.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_requester.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_gate.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_controller.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_output.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue_input.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reorder_queue.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/registers.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/register.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/recv_credit_flow_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_2clk_1w_1r.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ram_1clk_1w_1r.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/pipeline.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/one_hot_mux.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_to_mask.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/offset_flag_to_one_hot.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/mux.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt_controller.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/interrupt.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo_packer_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/ff.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/engine_layer.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/demux.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/cross_domain_signal.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/counter.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/chnl_tester.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
set_global_assignment -name SDC_FILE ../constr/C4DevGen1x4If64.sdc
set_global_assignment -name VERILOG_FILE ../hdl/C4DevGen1x4If64.v
set_global_assignment -name QIP_FILE ../ip/ALTPLL50I50O125O250O.qip
set_global_assignment -name QIP_FILE ../ip/ALTGXPCIeGen1x4.qip
set_global_assignment -name SOURCE_FILE db/C4DevGen1x4If64.cmp.rdb
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

18
fpga/altera/c4dev/Makefile Normal file
View File

@ -0,0 +1,18 @@
BOARD=c4dev
BOARD_PROJECTS:=C4DevGen1x4If64
BOARD_PATH:=$(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v
SUBDIRS = $(BOARD_PROJECTS)
all: $(SUBDIRS)
$(SUBDIRS)::
$(MAKE) -C $@ $(MAKECMDGOALS) BOARD_HDL=$(BOARD_HDL) BOARD=$(BOARD)
.PHONY:clean $(SUBDIRS)
clean: $(SUBDIRS)
rm -rf *~

37
fpga/altera/c4dev/board.mk Normal file
View File

@ -0,0 +1,37 @@
BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v
# These rules impact
PROJECT_IP=
PROJECT_HDL=hdl/$(PROJECT).v $(BOARD_HDL) $(patsubst %, $(RIFFA_PATH)/%,$(RIFFA_HDL))
PROJECT_CONSTR=constr/$(PROJECT).sdc
PROJECT_FILE=prj/$(PROJECT).qsf prj/$(PROJECT).qpf
PROJECT_FILES=$(PROJECT_IP) $(PROJECT_CONSTR) $(PROJECT_QSRCS) $(PROJECT_HDL)
.PHONY:$(PROJECT)
$(PROJECT): bit/$(PROJECT).sof
@echo Compiling Project $@
bit/$(PROJECT).sof: $(PROJECT_FILES)
quartus_sh --flow compile prj/$(PROJECT).qpf
synthesis: bit/$(PROJECT).map.rpt
bit/$(PROJECT).map.rpt: $(PROJECT_FILES)
quartus_sh --flow analysis_and_synthesis prj/$(PROJECT).qpf
implementation:bit/$(PROJECT).fit.rpt
bit/$(PROJECT).fit.rpt: $(PROJECT_FILES)
quartus_sh --flow fitter prj/$(PROJECT).qpf
all:$(PROJECT)
clean:
rm -rf ip/.qsys_edit ip/*~
rm -rf prj/db prj/incremental_db prj/*txt prj/*.sopcinfo prj/*.qws prj/*~
rm -rf bit/*.done bit/*.smsg bit/*.rpt bit/*.summary bit/*.sld bit/*.pin bit/*.jdi bit/*~
rm -rf hdl/*~
rm -rf constr/*~
rm -rf *~
clean-bit:
rm -rf bit/*.sof

15
fpga/altera/de5_qsys/riffa_wrapper_de5.v → fpga/altera/c4dev/riffa_wrapper_c4dev.v
View File

@ -33,10 +33,10 @@
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: riffa_wrapper_de5.v
// Filename: riffa_wrapper_de2i.v
// Version: 1.00a
// Verilog Standard: Verilog-2001
// Description: Wrapper file for all riffa logic for Altera DE5 boards
// Description: Wrapper file for all riffa logic for Altera DE2I boards
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
@ -45,15 +45,15 @@
`include "ultrascale.vh"
`include "functions.vh"
`timescale 1ps / 1ps
module riffa_wrapper_de5
module riffa_wrapper_c4dev
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Bit-Width from Quartus IP Generator
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PCI_DATA_WIDTH = 64,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5,
parameter C_FPGA_ID = "ADE5")
(// Interface: Altera RX
parameter C_FPGA_ID = "C4DE")
(// Interface: Altera RX
input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,
input [0:0] RX_ST_EOP,
input [0:0] RX_ST_SOP,
@ -86,7 +86,6 @@ module riffa_wrapper_de5
input PLD_CLK,
input RESET_STATUS,
// RIFFA Interface Signals
output RST_OUT,
input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
@ -121,7 +120,6 @@ module riffa_wrapper_de5
wire clk;
wire rst_in;
wire done_txc_rst;
wire done_txr_rst;
wire done_rxr_rst;
@ -393,6 +391,7 @@ module riffa_wrapper_de5
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.RST_LOGIC (RST_OUT),
// Unconnected Outputs
.TX_TLP (tx_tlp),

23
fpga/altera/de2i/DE2Gen1x1If64/Makefile Normal file
View File

@ -0,0 +1,23 @@
# This make file expects the following variables to be set:
# RIFFA_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory.
# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to
# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory
WIDTH=64
TYPE=classic
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=ip/ALTGXPCIeGen1x1.qip ip/ALTPLL50I50O125O250O.qip ip/PCIeGen1x1If64.qip

BIN
fpga/altera/de2i/DE2Gen1x1If64/bit/DE2Gen1x1If64.sof
View File

Binary file not shown.

4
fpga/altera/de2i/DE2Gen1x1If64/prj/DE2Gen1x1If64.qsf
View File

@ -41,8 +41,8 @@ set_global_assignment -name DEVICE EP4CGX150DF31C7
set_global_assignment -name TOP_LEVEL_ENTITY DE2Gen1x1If64
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:52:42 MARCH 20, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name LAST_QUARTUS_VERSION "14.1.0 SP0.19"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

18
fpga/altera/de2i/Makefile Normal file
View File

@ -0,0 +1,18 @@
BOARD=de2i
BOARD_PROJECTS:= DE2Gen1x1If64
BOARD_PATH:=$(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v
SUBDIRS = $(BOARD_PROJECTS)
all: $(SUBDIRS)
$(SUBDIRS)::
$(MAKE) -C $@ $(MAKECMDGOALS) BOARD_HDL=$(BOARD_HDL) BOARD=$(BOARD)
.PHONY:clean $(SUBDIRS)
clean: $(SUBDIRS)
rm -rf *~

37
fpga/altera/de2i/board.mk Normal file
View File

@ -0,0 +1,37 @@
BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v
# These rules impact
PROJECT_IP=
PROJECT_HDL=hdl/$(PROJECT).v $(BOARD_HDL) $(patsubst %, $(RIFFA_PATH)/%,$(RIFFA_HDL))
PROJECT_CONSTR=constr/$(PROJECT).sdc
PROJECT_FILE=prj/$(PROJECT).qsf prj/$(PROJECT).qpf
PROJECT_FILES=$(PROJECT_IP) $(PROJECT_CONSTR) $(PROJECT_QSRCS) $(PROJECT_HDL)
.PHONY:$(PROJECT)
$(PROJECT): bit/$(PROJECT).sof
@echo Compiling Project $@
bit/$(PROJECT).sof: $(PROJECT_FILES)
quartus_sh --flow compile prj/$(PROJECT).qpf
synthesis: bit/$(PROJECT).map.rpt
bit/$(PROJECT).map.rpt: $(PROJECT_FILES)
quartus_sh --flow analysis_and_synthesis prj/$(PROJECT).qpf
implementation:bit/$(PROJECT).fit.rpt
bit/$(PROJECT).fit.rpt: $(PROJECT_FILES)
quartus_sh --flow fitter prj/$(PROJECT).qpf
all:$(PROJECT)
clean:
rm -rf ip/.qsys_edit ip/*~
rm -rf prj/db prj/incremental_db prj/*txt prj/*.sopcinfo prj/*.qws prj/*~
rm -rf bit/*.done bit/*.smsg bit/*.rpt bit/*.summary bit/*.sld bit/*.pin bit/*.jdi bit/*~
rm -rf hdl/*~
rm -rf constr/*~
rm -rf *~
clean-bit:
rm -rf bit/*.sof

23
fpga/altera/de4/DE4Gen1x8If64/Makefile Normal file
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@ -0,0 +1,23 @@
# This make file expects the following variables to be set:
# RIFFA_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory.
# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to
# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory
WIDTH=64
TYPE=classic
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=ip/ALTGXPCIeGen1x8.qip ip/ALTPLL50I50O125O250O.qip ip/PCIeGen1x8If64.qip

9
fpga/altera/de4/DE4Gen1x8If64/prj/DE4Gen1x8If64.qsf
View File

@ -42,7 +42,7 @@ set_global_assignment -name TOP_LEVEL_ENTITY DE4Gen1x8If64
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:42:13 MARCH 24, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
@ -180,7 +180,9 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name QIP_FILE ../ip/ALTGXPCIeGen1x8.qip
set_global_assignment -name QIP_FILE ../ip/ALTPLL50I50O125O250O.qip
set_global_assignment -name QIP_FILE ../ip/PCIeGen1x8If64.qip
set_global_assignment -name SDC_FILE ../constr/DE4Gen1x8If64.sdc
set_global_assignment -name VERILOG_FILE ../hdl/DE4Gen1x8If64.v
set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de4.v
@ -273,7 +275,4 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_controller.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_extender.v
set_global_assignment -name QIP_FILE ../ip/ALTGXPCIeGen1x8.qip
set_global_assignment -name QIP_FILE ../ip/ALTPLL50I50O125O250O.qip
set_global_assignment -name QIP_FILE ../ip/PCIeGen1x8If64.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

23
fpga/altera/de4/DE4Gen2x8If128/Makefile Normal file
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@ -0,0 +1,23 @@
# This make file expects the following variables to be set:
# RIFFA_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory.
# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to
# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory
WIDTH=64
TYPE=classic
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=ip/ALTGXPCIeGen2x8.qip ip/ALTPLL50I50O125O250O.qip ip/PCIeGen2x8If128.qip

BIN
fpga/altera/de4/DE4Gen2x8If128/bit/DE4Gen2x8If128.sof Normal file
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Binary file not shown.

2
fpga/altera/de4/DE4Gen2x8If128/prj/DE4Gen2x8If128.qsf
View File

@ -42,7 +42,7 @@ set_global_assignment -name TOP_LEVEL_ENTITY DE4Gen2x8If128
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:42:13 MARCH 24, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

18
fpga/altera/de4/Makefile Normal file
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@ -0,0 +1,18 @@
BOARD=de4
BOARD_PROJECTS:= DE4Gen1x8If64 DE4Gen2x8If128
BOARD_PATH:=$(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v
SUBDIRS = $(BOARD_PROJECTS)
all: $(SUBDIRS)
$(SUBDIRS)::
$(MAKE) -C $@ $(MAKECMDGOALS) BOARD_HDL=$(BOARD_HDL) BOARD=$(BOARD)
.PHONY:clean $(SUBDIRS)
clean: $(SUBDIRS)
rm -rf *~

37
fpga/altera/de4/board.mk Normal file
View File

@ -0,0 +1,37 @@
BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v
# These rules impact
PROJECT_IP=
PROJECT_HDL=hdl/$(PROJECT).v $(BOARD_HDL) $(patsubst %, $(RIFFA_PATH)/%,$(RIFFA_HDL))
PROJECT_CONSTR=constr/$(PROJECT).sdc
PROJECT_FILE=prj/$(PROJECT).qsf prj/$(PROJECT).qpf
PROJECT_FILES=$(PROJECT_IP) $(PROJECT_CONSTR) $(PROJECT_QSRCS) $(PROJECT_HDL)
.PHONY:$(PROJECT)
$(PROJECT): bit/$(PROJECT).sof
@echo Compiling Project $@
bit/$(PROJECT).sof: $(PROJECT_FILES)
quartus_sh --flow compile prj/$(PROJECT).qpf
synthesis: bit/$(PROJECT).map.rpt
bit/$(PROJECT).map.rpt: $(PROJECT_FILES)
quartus_sh --flow analysis_and_synthesis prj/$(PROJECT).qpf
implementation:bit/$(PROJECT).fit.rpt
bit/$(PROJECT).fit.rpt: $(PROJECT_FILES)
quartus_sh --flow fitter prj/$(PROJECT).qpf
all:$(PROJECT)
clean:
rm -rf ip/.qsys_edit ip/*~
rm -rf prj/db prj/incremental_db prj/*txt prj/*.sopcinfo prj/*.qws prj/*~
rm -rf bit/*.done bit/*.smsg bit/*.rpt bit/*.summary bit/*.sld bit/*.pin bit/*.jdi bit/*~
rm -rf hdl/*~
rm -rf constr/*~
rm -rf *~
clean-bit:
rm -rf bit/*.sof

23
fpga/altera/de5/DE5Gen1x8If64/Makefile Normal file
View File

@ -0,0 +1,23 @@
# This make file expects the following variables to be set:
# RIFFA_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory.
# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to
# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory
WIDTH=64
TYPE=classic
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=ip/XCVRCtrlGen1x8.sip ip/XCVRCtrlGen1x8.qip ip/PCIeGen1x8If64.sip ip/PCIeGen1x8If64.qip

13
fpga/altera/de5/DE5Gen1x8If64/prj/DE5Gen1x8If64.qsf
View File

@ -41,7 +41,8 @@ set_global_assignment -name DEVICE 5SGXEA7N2F45C2
set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen1x8If64
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06 MARCH 21, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
################################################################################
# Timing SDC Files
@ -386,9 +387,9 @@ set_global_assignment -name SIP_FILE ../ip/PCIeGen1x8If64.sip
set_global_assignment -name QIP_FILE ../ip/PCIeGen1x8If64.qip
set_global_assignment -name VERILOG_FILE ../hdl/DE5Gen1x8If64.v
set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_extender.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_controller.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
@ -403,13 +404,11 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
@ -417,7 +416,6 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
@ -427,9 +425,7 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_12
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
@ -437,7 +433,6 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_g
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v

23
fpga/altera/de5/DE5Gen2x8If128/Makefile Normal file
View File

@ -0,0 +1,23 @@
# This make file expects the following variables to be set:
# RIFFA_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory.
# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to
# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory
WIDTH=128
TYPE=classic
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=ip/XCVRCtrlGen2x8.sip ip/XCVRCtrlGen2x8.qip ip/PCIeGen2x8If128.sip ip/PCIeGen2x8If128.qip

20
fpga/altera/de5/DE5Gen2x8If128/prj/DE5Gen2x8If128.qsf
View File

@ -42,6 +42,7 @@ set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen2x8If128
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06 MARCH 21, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
################################################################################
# Timing SDC Files
@ -403,13 +404,16 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name QIP_FILE ../ip/PCIeGen2x8If128.qip
set_global_assignment -name SIP_FILE ../ip/PCIeGen2x8If128.sip
set_global_assignment -name QIP_FILE ../ip/XCVRCtrlGen2x8.qip
set_global_assignment -name SIP_FILE ../ip/XCVRCtrlGen2x8.sip
set_global_assignment -name SDC_FILE ../constr/DE5Gen2x8If128.sdc
set_global_assignment -name VERILOG_FILE ../hdl/DE5Gen2x8If128.v
set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_extender.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_controller.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
@ -424,13 +428,11 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
@ -438,7 +440,6 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
@ -448,9 +449,7 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_12
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
@ -458,7 +457,6 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_g
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
@ -494,8 +492,4 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
set_global_assignment -name QIP_FILE ../ip/PCIeGen2x8If128.qip
set_global_assignment -name SIP_FILE ../ip/PCIeGen2x8If128.sip
set_global_assignment -name QIP_FILE ../ip/XCVRCtrlGen2x8.qip
set_global_assignment -name SIP_FILE ../ip/XCVRCtrlGen2x8.sip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

23
fpga/altera/de5/DE5Gen3x4If128/Makefile Normal file
View File

@ -0,0 +1,23 @@
# This make file expects the following variables to be set:
# RIFFA_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory.
# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to
# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory
WIDTH=128
TYPE=classic
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=ip/XCVRCtrlGen3x4.sip ip/XCVRCtrlGen3x4.qip ip/PCIeGen3x4If128.sip ip/PCIeGen3x4If128.qip

11
fpga/altera/de5/DE5Gen3x4If128/prj/DE5Gen3x4If128.qsf
View File

@ -42,6 +42,7 @@ set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen3x4If128
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06 MARCH 21, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
################################################################################
# Timing SDC Files
@ -475,9 +476,15 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_BANK3D_50MHZ
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name SIP_FILE ../ip/XCVRCtrlGen3x4.sip
set_global_assignment -name QIP_FILE ../ip/XCVRCtrlGen3x4.qip
set_global_assignment -name QIP_FILE ../ip/PCIeGen3x4If128.qip
set_global_assignment -name SIP_FILE ../ip/PCIeGen3x4If128.sip
set_global_assignment -name SDC_FILE ../constr/DE5Gen3x4If128.sdc
set_global_assignment -name VERILOG_FILE ../hdl/DE5Gen3x4If128.v
set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_extender.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_controller.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
@ -565,8 +572,4 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
set_global_assignment -name SIP_FILE ../ip/XCVRCtrlGen3x4.sip
set_global_assignment -name QIP_FILE ../ip/XCVRCtrlGen3x4.qip
set_global_assignment -name QIP_FILE ../ip/PCIeGen3x4If128.qip
set_global_assignment -name SIP_FILE ../ip/PCIeGen3x4If128.sip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

23
fpga/altera/de5/DE5QGen1x8If64/Makefile Normal file
View File

@ -0,0 +1,23 @@
#This make file expects the following variables to be set:
# RIFFA_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory.
# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to
# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory
WIDTH=64
TYPE=classic
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=QSysDE5QGen1x8If64.qsys

BIN
fpga/altera/de5_qsys/DE5Gen1x8If64/bit/DE5Gen1x8If64.sof → fpga/altera/de5/DE5QGen1x8If64/bit/DE5QGen1x8If64.sof
View File

Binary file not shown.

0
fpga/altera/de5_qsys/DE5Gen1x8If64/constr/DE5Gen1x8If64.sdc → fpga/altera/de5/DE5QGen1x8If64/constr/DE5QGen1x8If64.sdc
View File

6
fpga/altera/de5_qsys/DE5Gen1x8If64/hdl/DE5Gen1x8If64.v → fpga/altera/de5/DE5QGen1x8If64/hdl/DE5QGen1x8If64.v
View File

@ -33,7 +33,7 @@
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: DE5Gen1x8If64.v
// Filename: DE5QGen1x8If64.v
// Version:
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
@ -45,7 +45,7 @@
`include "riffa.vh"
`include "altera.vh"
`timescale 1ps / 1ps
module DE5Gen1x8If64
module DE5QGen1x8If64
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 12,
// Number of PCIe Lanes
@ -155,7 +155,7 @@ module DE5Gen1x8If64
// ----------LED's----------
assign LED[7:0] = 8'hff;
QSysDE5Gen1x8If64
QSysDE5QGen1x8If64
pcie_system_inst
(
// Outputs

0
fpga/altera/de5_qsys/DE5Gen1x8If64/ip/QSysDE5Gen1x8If64.qsys → fpga/altera/de5/DE5QGen1x8If64/ip/QSysDE5QGen1x8If64.qsys
View File

0
fpga/altera/de5_qsys/DE5Gen1x8If64/ip/README.txt → fpga/altera/de5/DE5QGen1x8If64/ip/README.txt
View File

2
fpga/altera/de5_qsys/DE5Gen1x8If64/prj/DE5Gen1x8If64.qpf → fpga/altera/de5/DE5QGen1x8If64/prj/DE5QGen1x8If64.qpf
View File

@ -27,4 +27,4 @@ DATE = "16:27:01 June 09, 2014"
# Revisions
PROJECT_REVISION = "DE5Gen1x8If64"
PROJECT_REVISION = "DE5QGen1x8If64"

26
fpga/altera/de5_qsys/DE5Gen1x8If64/prj/DE5Gen1x8If64.qsf → fpga/altera/de5/DE5QGen1x8If64/prj/DE5QGen1x8If64.qsf
View File

@ -25,7 +25,7 @@
# Notes:
#
# 1) The default values for assignments are stored in the file:
# DE5Gen1x8If64_assignment_defaults.qdf
# DE5QGen1x8If64_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@ -38,11 +38,11 @@
set_global_assignment -name FAMILY "Stratix V"
set_global_assignment -name DEVICE 5SGXEA7N2F45C2
set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen1x8If64
set_global_assignment -name TOP_LEVEL_ENTITY DE5QGen1x8If64
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06 MARCH 21, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "14.1.0 SP0.19"
set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
################################################################################
# Timing SDC Files
################################################################################
@ -379,13 +379,14 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name SDC_FILE ../constr/DE5Gen1x8If64.sdc
set_global_assignment -name QSYS_FILE ../ip/QSysDE5Gen1x8If64.qsys
set_global_assignment -name VERILOG_FILE ../hdl/DE5Gen1x8If64.v
set_global_assignment -name SDC_FILE ../constr/DE5QGen1x8If64.sdc
set_global_assignment -name QSYS_FILE ../ip/QSysDE5QGen1x8If64.qsys
set_global_assignment -name VERILOG_FILE ../hdl/DE5QGen1x8If64.v
set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_extender.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_controller.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
@ -400,13 +401,11 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
@ -414,7 +413,6 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
@ -424,9 +422,7 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_12
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
@ -434,7 +430,6 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_g
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v
@ -470,5 +465,4 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/channel.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo_fwft.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/async_fifo.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

23
fpga/altera/de5/DE5QGen2x8If128/Makefile Normal file
View File

@ -0,0 +1,23 @@
#This make file expects the following variables to be set:
# RIFFA_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory.
# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to
# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory
WIDTH=128
TYPE=classic
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=QSysDE5QGen2x8If128.qsys

BIN
fpga/altera/de5_qsys/DE5Gen2x8If128/bit/DE5Gen2x8If128.sof → fpga/altera/de5/DE5QGen2x8If128/bit/DE5QGen2x8If128.sof
View File

Binary file not shown.

2
fpga/altera/de5_qsys/DE5Gen2x8If128/constr/DE5Gen2x8If128.sdc → fpga/altera/de5/DE5QGen2x8If128/constr/DE5QGen2x8If128.sdc
View File

@ -33,7 +33,7 @@
# DAMAGE.
# ----------------------------------------------------------------------
#----------------------------------------------------------------------------
# Filename: DE5Gen2x8If128.sdc (Qsys)
# Filename: DE5QGen2x8If128.sdc (Qsys)
# Version: 1.00.a
# Verilog Standard: Verilog-2001
# Description: Synopsys Design Constraints for the DE5 board.

6
fpga/altera/de5_qsys/DE5Gen2x8If128/hdl/DE5Gen2x8If128.v → fpga/altera/de5/DE5QGen2x8If128/hdl/DE5QGen2x8If128.v
View File

@ -33,7 +33,7 @@
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: DE5Gen2x8If128.v
// Filename: DE5QGen2x8If128.v
// Version:
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
@ -45,7 +45,7 @@
`include "riffa.vh"
`include "altera.vh"
`timescale 1ps / 1ps
module DE5Gen2x8If128
module DE5QGen2x8If128
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 12,
// Number of PCIe Lanes
@ -157,7 +157,7 @@ module DE5Gen2x8If128
assign LED[7:0] = 8'hff;
// -------------------- BEGIN ALTERA IP INSTANTIATION --------------------//
QSysDE5Gen2x8If128
QSysDE5QGen2x8If128
pcie_system_inst
(
// Outputs

0
fpga/altera/de5_qsys/DE5Gen2x8If128/ip/QSysDE5Gen2x8If128.qsys → fpga/altera/de5/DE5QGen2x8If128/ip/QSysDE5QGen2x8If128.qsys
View File

0
fpga/altera/de5_qsys/DE5Gen2x8If128/ip/README.txt → fpga/altera/de5/DE5QGen2x8If128/ip/README.txt
View File

31
fpga/altera/de5/DE5QGen2x8If128/prj/DE5QGen2x8If128.qpf Normal file
View File

@ -0,0 +1,31 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 15.0.0 Build 145 04/22/2015 SJ Full Version
# Date created = 11:11:58 January 20, 2016
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "15.0"
DATE = "11:11:58 January 20, 2016"
# Revisions
PROJECT_REVISION = "DE5QGen2x8If128"

23
fpga/altera/de5_qsys/DE5Gen2x8If128/prj/DE5Gen2x8If128.qsf → fpga/altera/de5/DE5QGen2x8If128/prj/DE5QGen2x8If128.qsf
View File

@ -25,7 +25,7 @@
# Notes:
#
# 1) The default values for assignments are stored in the file:
# DE5Gen2x8If128_assignment_defaults.qdf
# DE5QGen2x8If128_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@ -38,10 +38,11 @@
set_global_assignment -name FAMILY "Stratix V"
set_global_assignment -name DEVICE 5SGXEA7N2F45C2
set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen2x8If128
set_global_assignment -name TOP_LEVEL_ENTITY DE5QGen2x8If128
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06 MARCH 21, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "14.1.0 SP0.19"
set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
################################################################################
# Timing SDC Files
@ -403,13 +404,13 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name QSYS_FILE ../ip/QSysDE5Gen2x8If128.qsys
set_global_assignment -name SDC_FILE ../constr/DE5Gen2x8If128.sdc
set_global_assignment -name VERILOG_FILE ../hdl/DE5Gen2x8If128.v
set_global_assignment -name QSYS_FILE ../ip/QSysDE5QGen2x8If128.qsys
set_global_assignment -name SDC_FILE ../constr/DE5QGen2x8If128.sdc
set_global_assignment -name VERILOG_FILE ../hdl/DE5QGen2x8If128.v
set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_extender.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_controller.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_writer.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_monitor_128.v
@ -424,13 +425,11 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_buffer_32
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_port_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_all.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_multiplexer.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_hdr_fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_selector.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_engine.v
@ -438,7 +437,6 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_shift.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_pipeline.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_data_fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/tx_alignment_pipeline.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_xilinx.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/translation_altera.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/syncff.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sync_fifo.v
@ -448,9 +446,7 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_12
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/sg_list_reader_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/scsdpram.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxr_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rxc_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_requester_mux.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_reader.v
@ -458,7 +454,6 @@ set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_channel_g
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_64.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_port_32.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rx_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/rotate.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/riffa.v

23
fpga/altera/de5/DE5QGen3x4If128/Makefile Normal file
View File

@ -0,0 +1,23 @@
#This make file expects the following variables to be set:
# RIFFA_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory.
# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to
# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory
WIDTH=128
TYPE=classic
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=QSysDE5QGen3x4If128.qsys

BIN
fpga/altera/de5_qsys/DE5Gen3x4If128/bit/DE5Gen3x4If128.sof → fpga/altera/de5/DE5QGen3x4If128/bit/DE5QGen3x4If128.sof
View File

Binary file not shown.

2
fpga/altera/de5_qsys/DE5Gen3x4If128/constr/DE5Gen3x4If128.sdc → fpga/altera/de5/DE5QGen3x4If128/constr/DE5QGen3x4If128.sdc
View File

@ -33,7 +33,7 @@
# DAMAGE.
# ----------------------------------------------------------------------
#----------------------------------------------------------------------------
# Filename: DE5Gen3x4If128.sdc (Qsys)
# Filename: DE5QGen3x4If128.sdc (Qsys)
# Version: 1.00.a
# Verilog Standard: Verilog-2001
# Description: Synopsys Design Constraints for the DE5 board.

6
fpga/altera/de5_qsys/DE5Gen3x4If128/hdl/DE5Gen3x4If128.v → fpga/altera/de5/DE5QGen3x4If128/hdl/DE5QGen3x4If128.v
View File

@ -33,7 +33,7 @@
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: DE5Gen3x4If128.v
// Filename: DE5QGen3x4If128.v
// Version:
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
@ -45,7 +45,7 @@
`include "riffa.vh"
`include "altera.vh"
`timescale 1ps / 1ps
module DE5Gen3x4If128
module DE5QGen3x4If128
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 12,
// Number of PCIe Lanes
@ -157,7 +157,7 @@ module DE5Gen3x4If128
assign LED[7:0] = 8'hff;
// -------------------- BEGIN ALTERA IP INSTANTIATION --------------------//
QSysDE5Gen3x4If128
QSysDE5QGen3x4If128
pcie_system_inst
(
// Outputs

0
fpga/altera/de5_qsys/DE5Gen3x4If128/ip/QSysDE5Gen3x4If128.qsys → fpga/altera/de5/DE5QGen3x4If128/ip/QSysDE5QGen3x4If128.qsys
View File

0
fpga/altera/de5_qsys/DE5Gen3x4If128/ip/README.txt → fpga/altera/de5/DE5QGen3x4If128/ip/README.txt
View File

2
fpga/altera/de5_qsys/DE5Gen3x4If128/prj/DE5Gen3x4If128.qpf → fpga/altera/de5/DE5QGen3x4If128/prj/DE5QGen3x4If128.qpf
View File

@ -27,4 +27,4 @@ DATE = "16:21:12 June 09, 2014"
# Revisions
PROJECT_REVISION = "DE5Gen3x4If128"
PROJECT_REVISION = "DE5QGen3x4If128"

16
fpga/altera/de5_qsys/DE5Gen3x4If128/prj/DE5Gen3x4If128.qsf → fpga/altera/de5/DE5QGen3x4If128/prj/DE5QGen3x4If128.qsf
View File

@ -25,7 +25,7 @@
# Notes:
#
# 1) The default values for assignments are stored in the file:
# DE5Gen3x4If128_assignment_defaults.qdf
# DE5QGen3x4If128_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@ -38,11 +38,11 @@
set_global_assignment -name FAMILY "Stratix V"
set_global_assignment -name DEVICE 5SGXEA7N2F45C2
set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen3x4If128
set_global_assignment -name TOP_LEVEL_ENTITY DE5QGen3x4If128
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06 MARCH 21, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "14.1.0 SP0.19"
set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
################################################################################
# Timing SDC Files
################################################################################
@ -475,10 +475,12 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_BANK3D_50MHZ
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name SDC_FILE ../constr/DE5Gen3x4If128.sdc
set_global_assignment -name QSYS_FILE ../ip/QSysDE5Gen3x4If128.qsys
set_global_assignment -name VERILOG_FILE ../hdl/DE5Gen3x4If128.v
set_global_assignment -name SDC_FILE ../constr/DE5QGen3x4If128.sdc
set_global_assignment -name QSYS_FILE ../ip/QSysDE5QGen3x4If128.qsys
set_global_assignment -name VERILOG_FILE ../hdl/DE5QGen3x4If128.v
set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de5.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_extender.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_controller.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txc_engine_ultrascale.v

18
fpga/altera/de5/Makefile Normal file
View File

@ -0,0 +1,18 @@
BOARD=de5
BOARD_PROJECTS:= DE5QGen1x8If64 DE5QGen2x8If128 DE5QGen3x4If128 DE5Gen1x8If64 DE5Gen2x8If128 DE5Gen3x4If128
BOARD_PATH:=$(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v
SUBDIRS = $(BOARD_PROJECTS)
all: $(SUBDIRS)
$(SUBDIRS)::
$(MAKE) -C $@ $(MAKECMDGOALS) BOARD_HDL=$(BOARD_HDL) BOARD=$(BOARD)
.PHONY:clean $(SUBDIRS)
clean: $(SUBDIRS)
rm -rf *~

36
fpga/altera/de5/board.mk Normal file
View File

@ -0,0 +1,36 @@
BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v
# These rules impact
PROJECT_IP=
PROJECT_HDL=hdl/$(PROJECT).v $(BOARD_HDL) $(patsubst %, $(RIFFA_PATH)/%,$(RIFFA_HDL))
PROJECT_CONSTR=constr/$(PROJECT).sdc
PROJECT_FILE=prj/$(PROJECT).qsf prj/$(PROJECT).qpf
PROJECT_FILES=$(PROJECT_IP) $(PROJECT_CONSTR) $(PROJECT_QSRCS) $(PROJECT_HDL)
.PHONY:$(PROJECT)
$(PROJECT): bit/$(PROJECT).sof
@echo Compiling Project $@
bit/$(PROJECT).sof: $(PROJECT_FILES)
quartus_sh --flow compile prj/$(PROJECT).qpf
synthesis: bit/$(PROJECT).map.rpt
bit/$(PROJECT).map.rpt: $(PROJECT_FILES)
quartus_sh --flow analysis_and_synthesis prj/$(PROJECT).qpf
implementation:bit/$(PROJECT).fit.rpt
bit/$(PROJECT).fit.rpt: $(PROJECT_FILES)
quartus_sh --flow fitter prj/$(PROJECT).qpf
all:$(PROJECT)
clean:
rm -rf ip/.qsys_edit ip/*~
rm -rf prj/db prj/incremental_db prj/*txt prj/*.sopcinfo prj/*.qws prj/*~
rm -rf bit/*.done bit/*.smsg bit/*.rpt bit/*.summary bit/*.sld bit/*.pin bit/*.jdi bit/*~
rm -rf hdl/*~
rm -rf constr/*~
rm -rf *~
clean-bit:
rm -rf bit/*.sof

0
fpga/altera/de5_qsys/DE5Gen1x8If64/ip/.qsys_edit/QSysDE5Gen1x8If64_schematic.nlv
View File

2
fpga/altera/de5_qsys/DE5Gen1x8If64/ip/.qsys_edit/filters.xml
View File

@ -1,2 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<filters version="14.1" />

12
fpga/altera/de5_qsys/DE5Gen1x8If64/ip/.qsys_edit/preferences.xml
View File

@ -1,12 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<preferences>
<debug showDebugMenu="0" />
<systemtable filter="All Interfaces">
<columns>
<connections preferredWidth="143" />
<irq preferredWidth="34" />
</columns>
</systemtable>
<library expandedCategories="Project,Library" />
<window width="1682" height="1050" x="-1" y="0" />
</preferences>

18
fpga/xilinx/Makefile Normal file
View File

@ -0,0 +1,18 @@
VENDOR:=xilinx
ULTRASCALE:=NetFPGA adm7V3 kcu105 vc709 vcu108
CLASSIC:=ac701 kc705 vc707 zc706
CURRENT_PATH := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
RIFFA_PATH=$(CURRENT_PATH)/../riffa_hdl
all: $(VENDOR)
classic:$(CLASSIC)
ultrascale:$(ULTRASCALE)
$(VENDOR): $(CLASSIC) $(ULTRASCALE)
$(CLASSIC) $(ULTRASCALE)::
$(MAKE) -C $@ $(MAKECMDGOALS) RIFFA_PATH=$(RIFFA_PATH)
.PHONY:clean $(SUBDIRS)
clean: $(SUBDIRS) $(VENDOR)
rm -rf *.log *.jou .Xil *~

18
fpga/xilinx/NetFPGA/Makefile Normal file
View File

@ -0,0 +1,18 @@
BOARD:=NetFPGA
BOARD_PROJECTS:=NetFPGA_Gen1x8If64 NetFPGA_Gen2x8If128 NetFPGA_Gen3x4If128
BOARD_PATH:=$(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v
SUBDIRS = $(BOARD_PROJECTS)
all: $(SUBDIRS)
$(SUBDIRS)::
$(MAKE) -C $@ $(MAKECMDGOALS) BOARD_HDL=$(BOARD_HDL)
.PHONY:clean $(SUBDIRS)
clean: $(SUBDIRS)
rm -rf *.log *.jou .Xil *~

18
fpga/xilinx/NetFPGA/NetFPGA_Gen1x8If64/Makefile Normal file
View File

@ -0,0 +1,18 @@
WIDTH=64
TYPE=ultrascale
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=PCIeGen1x8If64.xci

0
fpga/xilinx/NetFPGA/NetFPGA_Gen1x8If64/constr/NetFPGA_Top.xdc → fpga/xilinx/NetFPGA/NetFPGA_Gen1x8If64/constr/NetFPGA_Gen1x8If64.xdc
View File

4
fpga/xilinx/NetFPGA/NetFPGA_Gen1x8If64/hdl/NetFPGAGen1x8If64.v → fpga/xilinx/NetFPGA/NetFPGA_Gen1x8If64/hdl/NetFPGA_Gen1x8If64.v
View File

@ -33,7 +33,7 @@
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: NetFPGAGen1x8If64.v
// Filename: NetFPGA_Gen1x8If64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
@ -44,7 +44,7 @@
`include "riffa.vh"
`include "ultrascale.vh"
`timescale 1ps / 1ps
module NetFPGAGen1x8If64
module NetFPGA_Gen1x8If64
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes

15
fpga/xilinx/NetFPGA/NetFPGA_Gen1x8If64/prj/NetFPGA_Gen1x8If64.xpr
View File

@ -680,14 +680,14 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../hdl/NetFPGAGen1x8If64.v">
<File Path="$PPRDIR/../hdl/NetFPGA_Gen1x8If64.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../hdl/NetFPGAGen1x8If128.v">
<File Path="$PPRDIR/../hdl/NetFPGA_Gen1x8If128.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
@ -708,20 +708,20 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="NetFPGAGen1x8If64"/>
<Option Name="TopModule" Val="NetFPGA_Gen1x8If64"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../constr/NetFPGA_Top.xdc">
<File Path="$PPRDIR/../constr/NetFPGA_Gen1x8If64.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/NetFPGA_Top.xdc"/>
<Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/NetFPGA_Gen1x8If64.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
@ -729,7 +729,7 @@
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="NetFPGAGen1x8If64"/>
<Option Name="TopModule" Val="NetFPGA_Gen1x8If64"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
@ -779,7 +779,7 @@
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1761-3" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1761-3" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<Step Id="init_design"/>
@ -792,7 +792,6 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="PCIeGen1x8If64_impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1761-3" ConstrsSet="PCIeGen1x8If64" Description="Vivado Implementation Defaults" SynthRun="PCIeGen1x8If64_synth_1">
<Strategy Version="1" Minor="2">

18
fpga/xilinx/NetFPGA/NetFPGA_Gen2x8If128/Makefile Normal file
View File

@ -0,0 +1,18 @@
WIDTH=128
TYPE=ultrascale
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=PCIeGen2x8If128.xci

0
fpga/xilinx/NetFPGA/NetFPGA_Gen2x8If128/constr/NetFPGA_Top.xdc → fpga/xilinx/NetFPGA/NetFPGA_Gen2x8If128/constr/NetFPGA_Gen2x8If128.xdc
View File

4
fpga/xilinx/NetFPGA/NetFPGA_Gen2x8If128/hdl/NetFPGAGen2x8If128.v → fpga/xilinx/NetFPGA/NetFPGA_Gen2x8If128/hdl/NetFPGA_Gen2x8If128.v
View File

@ -33,7 +33,7 @@
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: NetFPGAGen2x8If128.v
// Filename: NetFPGA_Gen2x8If128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
@ -44,7 +44,7 @@
`include "riffa.vh"
`include "ultrascale.vh"
`timescale 1ps / 1ps
module NetFPGAGen2x8If128
module NetFPGA_Gen2x8If128
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes

10
fpga/xilinx/NetFPGA/NetFPGA_Gen2x8If128/prj/NetFPGA_Gen2x8If128.xpr
View File

@ -680,7 +680,7 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../hdl/NetFPGAGen2x8If128.v">
<File Path="$PPRDIR/../hdl/NetFPGA_Gen2x8If128.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
@ -701,20 +701,20 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="NetFPGAGen2x8If128"/>
<Option Name="TopModule" Val="NetFPGA_Gen2x8If128"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../constr/NetFPGA_Top.xdc">
<File Path="$PPRDIR/../constr/NetFPGA_Gen2x8If128.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/NetFPGA_Top.xdc"/>
<Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/NetFPGA_Gen2x8If128.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
@ -722,7 +722,7 @@
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="NetFPGAGen2x8If128"/>
<Option Name="TopModule" Val="NetFPGA_Gen2x8If128"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>

18
fpga/xilinx/NetFPGA/NetFPGA_Gen3x4If128/Makefile Normal file
View File

@ -0,0 +1,18 @@
WIDTH=128
TYPE=ultrascale
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=PCIeGen3x4If128.xci

BIN
fpga/xilinx/NetFPGA/NetFPGA_Gen3x4If128/bit/NetFPGAGen3x4If128.bit
View File

Binary file not shown.

0
fpga/xilinx/NetFPGA/NetFPGA_Gen3x4If128/constr/NetFPGA_Top.xdc → fpga/xilinx/NetFPGA/NetFPGA_Gen3x4If128/constr/NetFPGA_Gen3x4If128.xdc
View File

2
fpga/xilinx/NetFPGA/NetFPGA_Gen3x4If128/hdl/NetFPGAGen3x4If128.v → fpga/xilinx/NetFPGA/NetFPGA_Gen3x4If128/hdl/NetFPGA_Gen3x4If128.v
View File

@ -44,7 +44,7 @@
`include "riffa.vh"
`include "ultrascale.vh"
`timescale 1ps / 1ps
module NetFPGAGen3x4If128
module NetFPGA_Gen3x4If128
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes

10
fpga/xilinx/NetFPGA/NetFPGA_Gen3x4If128/prj/NetFPGA_Gen3x4If128.xpr
View File

@ -680,7 +680,7 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../hdl/NetFPGAGen3x4If128.v">
<File Path="$PPRDIR/../hdl/NetFPGA_Gen3x4If128.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
@ -701,20 +701,20 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="NetFPGAGen3x4If128"/>
<Option Name="TopModule" Val="NetFPGA_Gen3x4If128"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../constr/NetFPGA_Top.xdc">
<File Path="$PPRDIR/../constr/NetFPGA_Gen3x4If128.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/NetFPGA_Top.xdc"/>
<Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/NetFPGA_Gen3x4If128.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
@ -722,7 +722,7 @@
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="NetFPGAGen3x4If128"/>
<Option Name="TopModule" Val="NetFPGA_Gen3x4If128"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>

32
fpga/xilinx/NetFPGA/board.mk Normal file
View File

@ -0,0 +1,32 @@
BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v
PROJECT_IP=
PROJECT_HDL=hdl/$(PROJECT).v $(BOARD_HDL) $(patsubst %, $(RIFFA_PATH)/%,$(RIFFA_HDL)) $(PROJECT_FILES)
PROJECT_CONSTR=constr/$(PROJECT).xdc
PROJECT_FILE=prj/$(PROJECT).xpr
PROJECT_FILES=$(PROJECT_IP) $(PROJECT_CONSTR) $(PROJECT_QSRCS) $(PROJECT_HDL)
.PHONY:$(PROJECT)
$(PROJECT): bit/$(PROJECT).bit
@echo Compiling Project $@
bit/$(PROJECT).bit: $($(PROJECT)_FILES)
echo "launch_runs impl_1 -to_step write_bitstream -jobs $(JOBS); wait_on_run impl_1" | vivado -mode tcl prj/$(PROJECT).xpr
mv prj/$(PROJECT).runs/impl_1/$(PROJECT).bit bit/
synthesis: prj/$(PROJECT).runs/synth_1
prj/$(PROJECT).runs/synth_1: $($(PROJECT)_FILES)
echo "launch_runs synth_1 -jobs $(JOBS); wait_on_run synth_1" | vivado -mode tcl prj/$(PROJECT).xpr
implementation:prj/$(PROJECT).runs/impl_1
prj/$(PROJECT).runs/impl_1: $($(PROJECT)_FILES)
echo "launch_runs impl_1 -jobs $(JOBS); wait_on_run impl1" | vivado -mode tcl prj/$(PROJECT).xpr
all:$(PROJECT)
clean:
rm -rf *.log *.jou *~ .Xil
rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~
rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~
clean-bit:
rm -rf bit/*.bit

18
fpga/xilinx/ac701/AC701_Gen1x4If64/Makefile Normal file
View File

@ -0,0 +1,18 @@
WIDTH=64
TYPE=classic
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=PCIeGen1x4If64.xci

BIN
fpga/xilinx/ac701/AC701_Gen1x4If64/bit/AC701Gen1x4If64.bit → fpga/xilinx/ac701/AC701_Gen1x4If64/bit/AC701_Gen1x4If64.bit
View File

Binary file not shown.

0
fpga/xilinx/ac701/AC701_Gen1x4If64/constr/AC701_Top.xdc → fpga/xilinx/ac701/AC701_Gen1x4If64/constr/AC701_Gen1x4If64.xdc
View File

2
fpga/xilinx/ac701/AC701_Gen1x4If64/hdl/AC701Gen1x4If64.v → fpga/xilinx/ac701/AC701_Gen1x4If64/hdl/AC701_Gen1x4If64.v
View File

@ -45,7 +45,7 @@
`include "tlp.vh"
`include "xilinx.vh"
`timescale 1ps / 1ps
module AC701Gen1x4If64
module AC701_Gen1x4If64
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes

10
fpga/xilinx/ac701/AC701_Gen1x4If64/ip/PCIeGen1x4If64.xci
View File

@ -7,7 +7,7 @@
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>PCIeGen1x4If64</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie_7x" spirit:version="3.0"/>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie_7x" spirit:version="3.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Advanced</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
@ -302,7 +302,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_trgt_lnk_spd">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_hw_auton_spd_disable">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_de_emph">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.slot_clk">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.slot_clk">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rcb">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_root_cap_crs">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_slot_cap_attn_butn">FALSE</spirit:configurableElementValue>
@ -455,6 +455,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_FC_IF">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_PIPE_INTERFACE">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_ASYNC_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg676</spirit:configurableElementValue>
@ -467,12 +468,13 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD">xilinx.com:ac701:part0:1.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2014.4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>

41
fpga/xilinx/ac701/AC701_Gen1x4If64/prj/AC701_Gen1x4If64.xpr
View File

@ -1,9 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.4 (64-bit) -->
<!-- Product Version: Vivado v2015.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/home/drichmond/Research/repositories/git/riffa/fpga/xilinx/ac701/AC701_Gen1x4If64/prj/AC701_Gen1x4If64.xpr">
<Project Version="7" Minor="5" Path="/home/drichmond/Research/repositories/git/riffa/fpga/xilinx/ac701/AC701_Gen1x4If64/prj/AC701_Gen1x4If64.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="91b0f64634d74c568297d2f88f9aee86"/>
@ -12,6 +12,8 @@
<Option Name="BoardPart" Val="xilinx.com:ac701:part0:1.1"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableCoreContainerForIPI" Val="FALSE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
@ -679,13 +681,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../riffa_wrapper_ac701.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../../riffa_hdl/chnl_tester.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@ -693,35 +688,36 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../hdl/AC701Gen1x4If64.v">
<File Path="$PPRDIR/../../riffa_wrapper_ac701.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../../riffa_hdl/altera.vh">
<File Path="$PPRDIR/../hdl/AC701_Gen1x4If64.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../ip/PCIeGen1x4If64.upgrade_log"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="AC701Gen1x4If64"/>
<Option Name="TopModule" Val="AC701_Gen1x4If64"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../constr/AC701_Top.xdc">
<File Path="$PPRDIR/../constr/AC701_Gen1x4If64.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/AC701_Top.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
@ -729,7 +725,7 @@
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="AC701Gen1x4If64"/>
<Option Name="TopModule" Val="AC701_Gen1x4If64"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
@ -755,7 +751,10 @@
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
@ -763,6 +762,9 @@
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg676-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
@ -774,7 +776,7 @@
</Run>
<Run Id="PCIeGen1x4If64_synth_1" Type="Ft3:Synth" SrcSet="PCIeGen1x4If64" Part="xc7a200tfbg676-2" ConstrsSet="PCIeGen1x4If64" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/PCIeGen1x4If64_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -796,7 +798,7 @@
</Run>
<Run Id="PCIeGen1x4If64_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-2" ConstrsSet="PCIeGen1x4If64" Description="Vivado Implementation Defaults" SynthRun="PCIeGen1x4If64_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@ -809,5 +811,4 @@
</Strategy>
</Run>
</Runs>
<HWSession Dir="hw_1" File="hw.xml"/>
</Project>

18
fpga/xilinx/ac701/AC701_Gen2x4If128/Makefile Normal file
View File

@ -0,0 +1,18 @@
WIDTH=128
TYPE=classic
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=PCIeGen1x4If64.xci

0
fpga/xilinx/ac701/AC701_Gen2x4If128/constr/AC701_Top.xdc → fpga/xilinx/ac701/AC701_Gen2x4If128/constr/AC701_Gen2x4If128.xdc
View File

0
fpga/xilinx/ac701/AC701_Gen2x4If128/hdl/AC701Gen2x4If128.v → fpga/xilinx/ac701/AC701_Gen2x4If128/hdl/AC701_Gen2x4If128.v
View File

10
fpga/xilinx/ac701/AC701_Gen2x4If128/ip/PCIeGen2x4If128.xci
View File

@ -7,7 +7,7 @@
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>PCIeGen2x4If128</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie_7x" spirit:version="3.0"/>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie_7x" spirit:version="3.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Advanced</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
@ -302,7 +302,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_trgt_lnk_spd">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_hw_auton_spd_disable">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_de_emph">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.slot_clk">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.slot_clk">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rcb">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_root_cap_crs">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_slot_cap_attn_butn">FALSE</spirit:configurableElementValue>
@ -455,6 +455,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_FC_IF">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_PIPE_INTERFACE">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_ASYNC_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg676</spirit:configurableElementValue>
@ -467,12 +468,13 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD">xilinx.com:ac701:part0:1.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2014.4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>

66
fpga/xilinx/ac701/AC701_Gen2x4If128/prj/AC701_Gen2x4If128.xpr
View File

@ -1,9 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.4 (64-bit) -->
<!-- Product Version: Vivado v2015.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/home/drichmond/Research/repositories/git/riffa/fpga/xilinx/ac701/AC701_Gen2x4If128/prj/AC701_Gen2x4If128.xpr">
<Project Version="7" Minor="5" Path="/home/drichmond/Research/repositories/git/riffa/fpga/xilinx/ac701/AC701_Gen2x4If128/prj/AC701_Gen2x4If128.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="91b0f64634d74c568297d2f88f9aee86"/>
@ -12,6 +12,8 @@
<Option Name="BoardPart" Val="xilinx.com:ac701:part0:1.1"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableCoreContainerForIPI" Val="FALSE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
@ -693,7 +695,14 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../hdl/AC701Gen2x4If128.v">
<File Path="$PPRDIR/../ip/PCIeGen2x4If128.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../hdl/AC701_Gen2x4If128.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
@ -702,10 +711,12 @@
</File>
<File Path="$PPRDIR/../../../../riffa_hdl/altera.vh">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../ip/PCIeGen2x4If128.upgrade_log"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="AC701Gen2x4If128"/>
@ -714,14 +725,14 @@
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../constr/AC701_Top.xdc">
<File Path="$PPRDIR/../constr/AC701_Gen2x4If128.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/AC701_Top.xdc"/>
<Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/AC701_Gen2x4If128.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
@ -735,19 +746,6 @@
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="PCIeGen2x4If128" Type="BlockSrcs" RelSrcDir="$PSRCDIR/PCIeGen2x4If128">
<File Path="$PPRDIR/../ip/PCIeGen2x4If128.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="PCIeGen2x4If128"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@ -755,7 +753,10 @@
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
@ -763,6 +764,9 @@
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg676-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
@ -772,13 +776,6 @@
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="PCIeGen2x4If128_synth_1" Type="Ft3:Synth" SrcSet="PCIeGen2x4If128" Part="xc7a200tfbg676-2" ConstrsSet="PCIeGen2x4If128" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/PCIeGen2x4If128_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-2" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
@ -794,20 +791,5 @@
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="PCIeGen2x4If128_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-2" ConstrsSet="PCIeGen2x4If128" Description="Vivado Implementation Defaults" SynthRun="PCIeGen2x4If128_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
<HWSession Dir="hw_1" File="hw.xml"/>
</Project>

18
fpga/xilinx/ac701/Makefile Normal file
View File

@ -0,0 +1,18 @@
BOARD:=ac701
BOARD_PROJECTS:=AC701_Gen1x4If64 AC701_Gen2x4If128
BOARD_PATH:=$(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v
SUBDIRS = $(BOARD_PROJECTS)
all: $(SUBDIRS)
$(SUBDIRS)::
$(MAKE) -C $@ $(MAKECMDGOALS) BOARD_HDL=$(BOARD_HDL)
.PHONY:clean $(SUBDIRS)
clean: $(SUBDIRS)
rm -rf *.log *.jou .Xil *~

32
fpga/xilinx/ac701/board.mk Normal file
View File

@ -0,0 +1,32 @@
BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v
PROJECT_IP=
PROJECT_HDL=hdl/$(PROJECT).v $(BOARD_HDL) $(patsubst %, $(RIFFA_PATH)/%,$(RIFFA_HDL)) $(PROJECT_FILES)
PROJECT_CONSTR=constr/$(PROJECT).xdc
PROJECT_FILE=prj/$(PROJECT).xpr
PROJECT_FILES=$(PROJECT_IP) $(PROJECT_CONSTR) $(PROJECT_QSRCS) $(PROJECT_HDL)
.PHONY:$(PROJECT)
$(PROJECT): bit/$(PROJECT).bit
@echo Compiling Project $@
bit/$(PROJECT).bit: $($(PROJECT)_FILES)
echo "launch_runs impl_1 -to_step write_bitstream -jobs $(JOBS); wait_on_run impl_1" | vivado -mode tcl prj/$(PROJECT).xpr
mv prj/$(PROJECT).runs/impl_1/$(PROJECT).bit bit/
synthesis: prj/$(PROJECT).runs/synth_1
prj/$(PROJECT).runs/synth_1: $($(PROJECT)_FILES)
echo "launch_runs synth_1 -jobs $(JOBS); wait_on_run synth_1" | vivado -mode tcl prj/$(PROJECT).xpr
implementation:prj/$(PROJECT).runs/impl_1
prj/$(PROJECT).runs/impl_1: $($(PROJECT)_FILES)
echo "launch_runs impl_1 -jobs $(JOBS); wait_on_run impl1" | vivado -mode tcl prj/$(PROJECT).xpr
all:$(PROJECT)
clean:
rm -rf *.log *.jou *~ .Xil
rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~
rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~
clean-bit:
rm -rf bit/*.bit

15575
fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/ip/PCIeGen3x4If128.xml
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File diff suppressed because it is too large Load Diff

18
fpga/xilinx/adm7V3/ADM7V3_Gen1x8If64/Makefile Normal file
View File

@ -0,0 +1,18 @@
WIDTH=64
TYPE=ultrascale
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=PCIeGen1x8If64.xci

0
fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/bit/ADM_PCIe_7V3Gen1x8If64.bit → fpga/xilinx/adm7V3/ADM7V3_Gen1x8If64/bit/ADM_PCIe_7V3Gen1x8If64.bit
View File

0
fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/constr/7V3_Top.xdc → fpga/xilinx/adm7V3/ADM7V3_Gen1x8If64/constr/ADM7V3_Gen1x8If64.xdc
View File

2
fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/hdl/ADM_PCIe_7V3Gen1x8If64.v → fpga/xilinx/adm7V3/ADM7V3_Gen1x8If64/hdl/ADM7V3_Gen1x8If64.v
View File

@ -44,7 +44,7 @@
`include "riffa.vh"
`include "ultrascale.vh"
`timescale 1ps / 1ps
module ADM_PCIe_7V3Gen1x8If64
module ADM7V3_Gen1x8If64
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes

12
fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/ip/PCIeGen1x8If64.xci → fpga/xilinx/adm7V3/ADM7V3_Gen1x8If64/ip/PCIeGen1x8If64.xci
View File

@ -7,7 +7,7 @@
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>PCIeGen1x8If64</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie3_7x" spirit:version="3.0"/>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie3_7x" spirit:version="4.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.device_port_type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xlnx_ref_board">None</spirit:configurableElementValue>
@ -28,7 +28,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
@ -399,7 +399,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_INTERRUPT_PIN">0x0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LTR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
@ -653,6 +653,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_ENABLE_MSG_ROUTE">0x00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_ENABLE_RX_MSG_INTFC">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.POWER_DOWN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DEV_PORT_TYPE">00</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7vx690t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg1157</spirit:configurableElementValue>
@ -665,12 +666,13 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2014.4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>

73
fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/prj/7V3_Gen1x8If64.xpr → fpga/xilinx/adm7V3/ADM7V3_Gen1x8If64/prj/ADM7V3_Gen1x8If64.xpr
View File

@ -1,9 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.4 (64-bit) -->
<!-- Product Version: Vivado v2015.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/home/drichmond/Research/repositories/git/riffa/fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/prj/7V3_Gen1x8If64.xpr">
<Project Version="7" Minor="5" Path="/home/drichmond/Research/repositories/git/riffa/fpga/xilinx/adm7V3/ADM7V3_Gen1x8If64/prj/ADM7V3_Gen1x8If64.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="0e6774b4d2f941beabc11dd88355dde5"/>
@ -12,6 +12,8 @@
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableCoreContainerForIPI" Val="FALSE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
@ -659,14 +661,21 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../riffa_wrapper_7V3.v">
<File Path="$PPRDIR/../../riffa_wrapper_ADM7V3.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../hdl/ADM_PCIe_7V3Gen1x8If64.v">
<File Path="$PPRDIR/../ip/PCIeGen1x8If64.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../hdl/ADM7V3_Gen1x8If64.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
@ -675,32 +684,35 @@
</File>
<File Path="$PPRDIR/../../../../riffa_hdl/xilinx.vh">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../../riffa_hdl/altera.vh">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../ip/PCIeGen1x8If64.upgrade_log"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="ADM_PCIe_7V3Gen1x8If64"/>
<Option Name="TopModule" Val="ADM7V3_Gen1x8If64"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../constr/7V3_Top.xdc">
<File Path="$PPRDIR/../constr/ADM7V3_Gen1x8If64.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/7V3_Top.xdc"/>
<Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/ADM7V3_Gen1x8If64.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
@ -708,26 +720,13 @@
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="ADM_PCIe_7V3Gen1x8If64"/>
<Option Name="TopModule" Val="ADM7V3_Gen1x8If64"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SimMode" Val="post-implementation"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="PCIeGen1x8If64" Type="BlockSrcs" RelSrcDir="$PSRCDIR/PCIeGen1x8If64">
<File Path="$PPRDIR/../ip/PCIeGen1x8If64.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="PCIeGen1x8If64"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@ -735,7 +734,10 @@
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
@ -743,6 +745,9 @@
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx690tffg1157-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
@ -752,13 +757,6 @@
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="PCIeGen1x8If64_synth_1" Type="Ft3:Synth" SrcSet="PCIeGen1x8If64" Part="xc7vx690tffg1157-2" ConstrsSet="PCIeGen1x8If64" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/PCIeGen1x8If64_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1157-2" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
@ -774,20 +772,5 @@
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="PCIeGen1x8If64_impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1157-2" ConstrsSet="PCIeGen1x8If64" Description="Vivado Implementation Defaults" SynthRun="PCIeGen1x8If64_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
<HWSession Dir="hw_1" File="hw.xml"/>
</Project>

18
fpga/xilinx/adm7V3/ADM7V3_Gen2x8If128/Makefile Normal file
View File

@ -0,0 +1,18 @@
WIDTH=128
TYPE=ultrascale
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=PCIeGen2x8If128.xci

0
fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/bit/ADM_PCIe_7V3Gen2x8If128.bit → fpga/xilinx/adm7V3/ADM7V3_Gen2x8If128/bit/ADM_PCIe_7V3Gen2x8If128.bit
View File

0
fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/constr/7V3_Top.xdc → fpga/xilinx/adm7V3/ADM7V3_Gen2x8If128/constr/ADM7V3_Gen2x8If128.xdc
View File

0
fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/hdl/ADM_PCIe_7V3Gen2x8If128.v → fpga/xilinx/adm7V3/ADM7V3_Gen2x8If128/hdl/ADM7V3_Gen2x8If128.v
View File

0
fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/ip/PCIeGen2x8If128.xci → fpga/xilinx/adm7V3/ADM7V3_Gen2x8If128/ip/PCIeGen2x8If128.xci
View File

14
fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/prj/7V3_Gen2x8If128.xpr → fpga/xilinx/adm7V3/ADM7V3_Gen2x8If128/prj/ADM7V3_Gen2x8If128.xpr
View File

@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/home/drichmond/Research/repositories/git/riffa/fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/prj/7V3_Gen2x8If128.xpr">
<Project Version="7" Minor="2" Path="/home/drichmond/Research/repositories/git/riffa/fpga/xilinx/adm7V3/ADM7V3_Gen2x8If128/prj/ADM7V3_Gen2x8If128.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="0e6774b4d2f941beabc11dd88355dde5"/>
@ -659,14 +659,14 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../riffa_wrapper_7V3.v">
<File Path="$PPRDIR/../../riffa_wrapper_adm7V3.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../hdl/ADM_PCIe_7V3Gen2x8If128.v">
<File Path="$PPRDIR/../hdl/ADM7V3_Gen2x8If128.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
@ -687,20 +687,20 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="ADM_PCIe_7V3Gen2x8If128"/>
<Option Name="TopModule" Val="ADM7V3_Gen2x8If128"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../constr/7V3_Top.xdc">
<File Path="$PPRDIR/../constr/ADM7V3_Gen2x8If128.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/7V3_Top.xdc"/>
<Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/ADM7V3_Gen2x8If128.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
@ -708,7 +708,7 @@
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="ADM_PCIe_7V3Gen2x8If128"/>
<Option Name="TopModule" Val="ADM7V3_Gen2x8If128"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SimMode" Val="post-implementation"/>

18
fpga/xilinx/adm7V3/ADM7V3_Gen3x4If128/Makefile Normal file
View File

@ -0,0 +1,18 @@
WIDTH=128
TYPE=ultrascale
CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
PROJECT=$(shell basename $(CURRENT_PATH))
ifndef RIFFA_PATH
RIFFA_PATH:=../../../riffa_hdl
endif
ifndef BOARD_PATH
BOARD_PATH:=..
endif
ifndef JOBS
JOBS=1
endif
include $(RIFFA_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk
PROJECT_IP+=PCIeGen3x4If128.xci

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