diff --git a/fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/bit/ADM_PCIe_7V3Gen1x8If64.bit b/fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/bit/ADM_PCIe_7V3Gen1x8If64.bit
index 7a8238b..b580140 100644
Binary files a/fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/bit/ADM_PCIe_7V3Gen1x8If64.bit and b/fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/bit/ADM_PCIe_7V3Gen1x8If64.bit differ
diff --git a/fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/hdl/ADM_PCIe_7V3Gen1x8If64.v b/fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/hdl/ADM_PCIe_7V3Gen1x8If64.v
index 2e226c2..6c3d35a 100644
--- a/fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/hdl/ADM_PCIe_7V3Gen1x8If64.v
+++ b/fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/hdl/ADM_PCIe_7V3Gen1x8If64.v
@@ -52,8 +52,7 @@ module ADM_PCIe_7V3Gen1x8If64
// Settings from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 64,
parameter C_MAX_PAYLOAD_BYTES = 256,
- parameter C_LOG_NUM_TAGS = 6
- )
+ parameter C_LOG_NUM_TAGS = 6)
(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
diff --git a/fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/prj/7V3_Gen1x8If64.xpr b/fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/prj/7V3_Gen1x8If64.xpr
index 7ce8a23..2819626 100644
--- a/fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/prj/7V3_Gen1x8If64.xpr
+++ b/fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/prj/7V3_Gen1x8If64.xpr
@@ -678,7 +678,6 @@
-
diff --git a/fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/constr/7V3_Top.xdc b/fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/constr/7V3_Top.xdc
new file mode 100644
index 0000000..8fd3cfb
--- /dev/null
+++ b/fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/constr/7V3_Top.xdc
@@ -0,0 +1,135 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above
+# copyright notice, this list of conditions and the following
+# disclaimer in the documentation and/or other materials provided
+# with the distribution.
+#
+# * Neither the name of The Regents of the University of California
+# nor the names of its contributors may be used to endorse or
+# promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename: 7V3_Top.xdc
+# Version: 1.00.a
+# Verilog Standard: Verilog-2001
+# Description: Xilinx Design Constraints for the Alpha Data 7V3 board.
+# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin
+#
+# Author: Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+#
+#########################################################################################################################
+# User Constraints
+#########################################################################################################################
+
+###############################################################################
+# User Time Names / User Time Groups / Time Specs
+###############################################################################
+
+###############################################################################
+# User Physical Constraints
+###############################################################################
+
+#
+# LED Status Indicators for Example Design.
+# LED 0-2 should be all ON if link is up and functioning correctly
+# LED 3 should be blinking if user application is receiving valid clock
+#
+
+#System Reset, User Reset, User Link Up, User Clk Heartbeat
+set_property PACKAGE_PIN AC33 [get_ports {LED[0]}]
+set_property PACKAGE_PIN V32 [get_ports {LED[1]}]
+set_property PACKAGE_PIN V33 [get_ports {LED[2]}]
+set_property PACKAGE_PIN AB31 [get_ports {LED[3]}]
+set_property PACKAGE_PIN AB32 [get_ports {LED[4]}]
+set_property PACKAGE_PIN U30 [get_ports {LED[5]}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[5]}]
+
+set_false_path -to [get_ports -filter NAME=~LED*]
+
+#########################################################################################################################
+# End User Constraints
+#########################################################################################################################
+#
+#
+#
+#########################################################################################################################
+# PCIE Core Constraints
+#########################################################################################################################
+
+#
+# SYS reset (input) signal. The sys_reset_n signal should be
+# obtained from the PCI Express interface if possible. For
+# slot based form factors, a system reset signal is usually
+# present on the connector. For cable based form factors, a
+# system reset signal may not be available. In this case, the
+# system reset signal must be generated locally by some form of
+# supervisory circuit. You may change the IOSTANDARD and LOC
+# to suit your requirements and VCCO voltage banking rules.
+# Some 7 series devices do not have 3.3 V I/Os available.
+# Therefore the appropriate level shift is required to operate
+# with these devices that contain only 1.8 V banks.
+#
+
+set_property PACKAGE_PIN W27 [get_ports PCIE_RESET_N]
+set_property IOSTANDARD LVCMOS18 [get_ports PCIE_RESET_N]
+set_property PULLUP true [get_ports PCIE_RESET_N]
+
+#
+#
+# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
+# signals are the PCI Express reference clock. Virtex-7 GT
+# Transceiver architecture requires the use of a dedicated clock
+# resources (FPGA input pins) associated with each GT Transceiver.
+# To use these pins an IBUFDS primitive (refclk_ibuf) is
+# instantiated in user's design.
+# Please refer to the Virtex-7 GT Transceiver User Guide
+# (UG) for guidelines regarding clock resource selection.
+#
+set_property LOC IBUFDS_GTE2_X1Y16 [get_cells refclk_ibuf]
+
+
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O]
+
+###############################################################################
+# Physical Constraints
+###############################################################################
+
+set_false_path -from [get_ports PCIE_RESET_N]
+###############################################################################
+# End
+###############################################################################
+
diff --git a/fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/hdl/ADM_PCIe_7V3Gen2x8If128.v b/fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/hdl/ADM_PCIe_7V3Gen2x8If128.v
new file mode 100644
index 0000000..8ec6d42
--- /dev/null
+++ b/fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/hdl/ADM_PCIe_7V3Gen2x8If128.v
@@ -0,0 +1,482 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+//
+// * Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// * Redistributions in binary form must reproduce the above
+// copyright notice, this list of conditions and the following
+// disclaimer in the documentation and/or other materials provided
+// with the distribution.
+//
+// * Neither the name of The Regents of the University of California
+// nor the names of its contributors may be used to endorse or
+// promote products derived from this software without specific
+// prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename: 7V3Gen2x8If128.v
+// Version: 1.00.a
+// Verilog Standard: Verilog-2001
+// Description: Top level module for RIFFA 2.2 reference design for the
+// the Xilinx 7V3 Development Board.
+// Author: Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "ultrascale.vh"
+`timescale 1ps / 1ps
+module ADM_PCIe_7V3Gen2x8If128
+ #(// Number of RIFFA Channels
+ parameter C_NUM_CHNL = 1,
+ // Number of PCIe Lanes
+ parameter C_NUM_LANES = 4,
+ // Settings from Vivado IP Generator
+ parameter C_PCI_DATA_WIDTH = 128,
+ parameter C_MAX_PAYLOAD_BYTES = 256,
+ parameter C_LOG_NUM_TAGS = 6
+ )
+ (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
+ output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
+ input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
+ input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
+
+ output [5:0] LED,
+ input PCIE_REFCLK_P,
+ input PCIE_REFCLK_N,
+ input PCIE_RESET_N
+ );
+
+ // Clocks, etc
+ wire user_lnk_up;
+ wire user_clk;
+ wire user_reset;
+ wire pcie_refclk;
+ wire pcie_reset_n;
+
+ // Interface: RQ (TXC)
+ wire s_axis_rq_tlast;
+ wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata;
+ wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser;
+ wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
+ wire s_axis_rq_tready;
+ wire s_axis_rq_tvalid;
+ // Interface: RC (RXC)
+ wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata;
+ wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser;
+ wire m_axis_rc_tlast;
+ wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
+ wire m_axis_rc_tvalid;
+ wire m_axis_rc_tready;
+ // Interface: CQ (RXR)
+ wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata;
+ wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser;
+ wire m_axis_cq_tlast;
+ wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
+ wire m_axis_cq_tvalid;
+ wire m_axis_cq_tready;
+ // Interface: CC (TXC)
+ wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata;
+ wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser;
+ wire s_axis_cc_tlast;
+ wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
+ wire s_axis_cc_tvalid;
+ wire s_axis_cc_tready;
+
+ // Configuration (CFG) Interface
+ wire [3:0] pcie_rq_seq_num;
+ wire pcie_rq_seq_num_vld;
+ wire [5:0] pcie_rq_tag;
+ wire pcie_rq_tag_vld;
+ wire pcie_cq_np_req;
+ wire [5:0] pcie_cq_np_req_count;
+
+ wire cfg_phy_link_down;
+ wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH
+ wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE
+ wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD
+ wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
+ wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
+ wire [5:0] cfg_function_power_state; // Ignorable but not removable
+ wire [11:0] cfg_vf_status; // Ignorable but not removable
+ wire [17:0] cfg_vf_power_state; // Ignorable but not removable
+ wire [1:0] cfg_link_power_state; // Ignorable but not removable
+
+ // Error Reporting Interface
+ wire cfg_err_cor_out;
+ wire cfg_err_nonfatal_out;
+ wire cfg_err_fatal_out;
+
+ wire cfg_ltr_enable;
+ wire [5:0] cfg_ltssm_state;// TODO: Connect to LED's
+ wire [1:0] cfg_rcb_status;
+ wire [1:0] cfg_dpa_substate_change;
+ wire [1:0] cfg_obff_enable;
+ wire cfg_pl_status_change;
+
+ wire [1:0] cfg_tph_requester_enable;
+ wire [5:0] cfg_tph_st_mode;
+ wire [5:0] cfg_vf_tph_requester_enable;
+ wire [17:0] cfg_vf_tph_st_mode;
+ wire [7:0] cfg_fc_ph;
+ wire [11:0] cfg_fc_pd;
+ wire [7:0] cfg_fc_nph;
+ wire [11:0] cfg_fc_npd;
+ wire [7:0] cfg_fc_cplh;
+ wire [11:0] cfg_fc_cpld;
+ wire [2:0] cfg_fc_sel;
+
+ // Interrupt Interface Signals
+ wire [3:0] cfg_interrupt_int;
+ wire [1:0] cfg_interrupt_pending;
+ wire cfg_interrupt_sent;
+ wire [1:0] cfg_interrupt_msi_enable;
+ wire [5:0] cfg_interrupt_msi_vf_enable;
+ wire [5:0] cfg_interrupt_msi_mmenable;
+ wire cfg_interrupt_msi_mask_update;
+ wire [31:0] cfg_interrupt_msi_data;
+ wire [3:0] cfg_interrupt_msi_select;
+ wire [31:0] cfg_interrupt_msi_int;
+ wire [63:0] cfg_interrupt_msi_pending_status;
+ wire cfg_interrupt_msi_sent;
+ wire cfg_interrupt_msi_fail;
+ wire [2:0] cfg_interrupt_msi_attr;
+ wire cfg_interrupt_msi_tph_present;
+ wire [1:0] cfg_interrupt_msi_tph_type;
+ wire [8:0] cfg_interrupt_msi_tph_st_tag;
+ wire [2:0] cfg_interrupt_msi_function_number;
+
+ wire rst_out;
+ wire [C_NUM_CHNL-1:0] chnl_rx_clk;
+ wire [C_NUM_CHNL-1:0] chnl_rx;
+ wire [C_NUM_CHNL-1:0] chnl_rx_ack;
+ wire [C_NUM_CHNL-1:0] chnl_rx_last;
+ wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
+ wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
+ wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+ wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
+ wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
+
+ wire [C_NUM_CHNL-1:0] chnl_tx_clk;
+ wire [C_NUM_CHNL-1:0] chnl_tx;
+ wire [C_NUM_CHNL-1:0] chnl_tx_ack;
+ wire [C_NUM_CHNL-1:0] chnl_tx_last;
+ wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
+ wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
+ wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+ wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
+ wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
+
+ genvar chnl;
+
+ IBUF
+ #()
+ pci_reset_n_ibuf
+ (.O(pcie_reset_n),
+ .I(PCIE_RESET_N));
+
+ IBUFDS_GTE2
+ #()
+ refclk_ibuf
+ (.O(pcie_refclk),
+ .ODIV2(),
+ .I(PCIE_REFCLK_P),
+ .CEB(1'b0),
+ .IB(PCIE_REFCLK_N));
+
+ OBUF
+ #()
+ led_0_obuf
+ (.O(LED[0]),
+ .I(cfg_ltssm_state[0]));
+ OBUF
+ #()
+ led_1_obuf
+ (.O(LED[1]),
+ .I(cfg_ltssm_state[1]));
+ OBUF
+ #()
+ led_2_obuf
+ (.O(LED[2]),
+ .I(cfg_ltssm_state[2]));
+ OBUF
+ #()
+ led_3_obuf
+ (.O(LED[3]),
+ .I(cfg_ltssm_state[3]));
+ OBUF
+ #()
+ led_4_obuf
+ (.O(LED[4]),
+ .I(cfg_ltssm_state[4]));
+ OBUF
+ #()
+ led_5_obuf
+ (.O(LED[5]),
+ .I(cfg_ltssm_state[5]));
+ OBUF
+ #()
+ led_6_obuf
+ (.O(LED[6]),
+ .I(pcie_reset_n));
+ OBUF
+ #()
+ led_7_obuf
+ (.O(LED[7]),
+ .I(rst_out));
+
+ // Core Top Level Wrapper
+ PCIeGen2x8If128
+ #()
+ pcie3_7x_0_i
+ (//---------------------------------------------------------------------
+ // PCI Express (pci_exp) Interface
+ //---------------------------------------------------------------------
+ .pci_exp_txn ( PCI_EXP_TXN ),
+ .pci_exp_txp ( PCI_EXP_TXP ),
+ .pci_exp_rxn ( PCI_EXP_RXN ),
+ .pci_exp_rxp ( PCI_EXP_RXP ),
+
+ //---------------------------------------------------------------------
+ // AXI Interface
+ //---------------------------------------------------------------------
+ .user_clk ( user_clk ),
+ .user_reset ( user_reset ),
+ .user_lnk_up ( user_lnk_up ),
+ .user_app_rdy ( ),
+
+ .s_axis_rq_tlast ( s_axis_rq_tlast ),
+ .s_axis_rq_tdata ( s_axis_rq_tdata ),
+ .s_axis_rq_tuser ( s_axis_rq_tuser ),
+ .s_axis_rq_tkeep ( s_axis_rq_tkeep ),
+ .s_axis_rq_tready ( s_axis_rq_tready ),
+ .s_axis_rq_tvalid ( s_axis_rq_tvalid ),
+
+ .m_axis_rc_tdata ( m_axis_rc_tdata ),
+ .m_axis_rc_tuser ( m_axis_rc_tuser ),
+ .m_axis_rc_tlast ( m_axis_rc_tlast ),
+ .m_axis_rc_tkeep ( m_axis_rc_tkeep ),
+ .m_axis_rc_tvalid ( m_axis_rc_tvalid ),
+ .m_axis_rc_tready ( {22{m_axis_rc_tready}} ),
+
+ .m_axis_cq_tdata ( m_axis_cq_tdata ),
+ .m_axis_cq_tuser ( m_axis_cq_tuser ),
+ .m_axis_cq_tlast ( m_axis_cq_tlast ),
+ .m_axis_cq_tkeep ( m_axis_cq_tkeep ),
+ .m_axis_cq_tvalid ( m_axis_cq_tvalid ),
+ .m_axis_cq_tready ( {22{m_axis_cq_tready}} ),
+
+ .s_axis_cc_tdata ( s_axis_cc_tdata ),
+ .s_axis_cc_tuser ( s_axis_cc_tuser ),
+ .s_axis_cc_tlast ( s_axis_cc_tlast ),
+ .s_axis_cc_tkeep ( s_axis_cc_tkeep ),
+ .s_axis_cc_tvalid ( s_axis_cc_tvalid ),
+ .s_axis_cc_tready ( s_axis_cc_tready ),
+
+ //---------------------------------------------------------------------
+ // Configuration (CFG) Interface
+ //---------------------------------------------------------------------
+ .pcie_rq_seq_num ( pcie_rq_seq_num ),
+ .pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ),
+ .pcie_rq_tag ( pcie_rq_tag ),
+ .pcie_rq_tag_vld ( pcie_rq_tag_vld ),
+ .pcie_cq_np_req ( pcie_cq_np_req ),
+ .pcie_cq_np_req_count ( pcie_cq_np_req_count ),
+ .cfg_phy_link_down ( cfg_phy_link_down ),
+ .cfg_phy_link_status ( cfg_phy_link_status),
+ .cfg_negotiated_width ( cfg_negotiated_width ),
+ .cfg_current_speed ( cfg_current_speed ),
+ .cfg_max_payload ( cfg_max_payload ),
+ .cfg_max_read_req ( cfg_max_read_req ),
+ .cfg_function_status ( cfg_function_status ),
+ .cfg_function_power_state ( cfg_function_power_state ),
+ .cfg_vf_status ( cfg_vf_status ),
+ .cfg_vf_power_state ( cfg_vf_power_state ),
+ .cfg_link_power_state ( cfg_link_power_state ),
+ // Error Reporting Interface
+ .cfg_err_cor_out ( cfg_err_cor_out ),
+ .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ),
+ .cfg_err_fatal_out ( cfg_err_fatal_out ),
+ .cfg_ltr_enable ( cfg_ltr_enable ),
+ .cfg_ltssm_state ( cfg_ltssm_state ),
+ .cfg_rcb_status ( cfg_rcb_status ),
+ .cfg_dpa_substate_change ( cfg_dpa_substate_change ),
+ .cfg_obff_enable ( cfg_obff_enable ),
+ .cfg_pl_status_change ( cfg_pl_status_change ),
+ .cfg_tph_requester_enable ( cfg_tph_requester_enable ),
+ .cfg_tph_st_mode ( cfg_tph_st_mode ),
+ .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ),
+ .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ),
+ .cfg_fc_ph ( cfg_fc_ph ),
+ .cfg_fc_pd ( cfg_fc_pd ),
+ .cfg_fc_nph ( cfg_fc_nph ),
+ .cfg_fc_npd ( cfg_fc_npd ),
+ .cfg_fc_cplh ( cfg_fc_cplh ),
+ .cfg_fc_cpld ( cfg_fc_cpld ),
+ .cfg_fc_sel ( cfg_fc_sel ),
+ //---------------------------------------------------------------------
+ // EP Only
+ //---------------------------------------------------------------------
+ // Interrupt Interface Signals
+ .cfg_interrupt_int ( cfg_interrupt_int ),
+ .cfg_interrupt_pending ( cfg_interrupt_pending ),
+ .cfg_interrupt_sent ( cfg_interrupt_sent ),
+ .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ),
+ .cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ),
+ .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ),
+ .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ),
+ .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ),
+ .cfg_interrupt_msi_select ( cfg_interrupt_msi_select ),
+ .cfg_interrupt_msi_int ( cfg_interrupt_msi_int ),
+ .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ),
+ .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ),
+ .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ),
+ .cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ),
+ .cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ),
+ .cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ),
+ .cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ),
+ .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ),
+
+ //---------------------------------------------------------------------
+ // System(SYS) Interface
+ //---------------------------------------------------------------------
+ .sys_clk (pcie_refclk),
+ .sys_reset (~pcie_reset_n));
+
+ riffa_wrapper_7V3
+ #(/*AUTOINSTPARAM*/
+ // Parameters
+ .C_NUM_CHNL (C_NUM_CHNL),
+ .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
+ .C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES),
+ .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS))
+ riffa
+ (// Outputs
+ .M_AXIS_CQ_TREADY (m_axis_cq_tready),
+ .M_AXIS_RC_TREADY (m_axis_rc_tready),
+ .S_AXIS_CC_TVALID (s_axis_cc_tvalid),
+ .S_AXIS_CC_TLAST (s_axis_cc_tlast),
+ .S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
+ .S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+ .S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
+ .S_AXIS_RQ_TVALID (s_axis_rq_tvalid),
+ .S_AXIS_RQ_TLAST (s_axis_rq_tlast),
+ .S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
+ .S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+ .S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
+ .USER_CLK (user_clk),
+ .USER_RESET (user_reset),
+ .CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]),
+ .CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]),
+ .CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]),
+ .CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]),
+ .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
+ .CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]),
+ .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
+ .CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]),
+ .CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]),
+ .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
+ .CFG_FC_SEL (cfg_fc_sel[2:0]),
+ .PCIE_CQ_NP_REQ (pcie_cq_np_req),
+ .RST_OUT (rst_out),
+ .CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
+ .CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
+ .CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+ .CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+ .CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+ .CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+ .CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
+ .CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+ // Inputs
+ .M_AXIS_CQ_TVALID (m_axis_cq_tvalid),
+ .M_AXIS_CQ_TLAST (m_axis_cq_tlast),
+ .M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
+ .M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+ .M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
+ .M_AXIS_RC_TVALID (m_axis_rc_tvalid),
+ .M_AXIS_RC_TLAST (m_axis_rc_tlast),
+ .M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
+ .M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+ .M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
+ .S_AXIS_CC_TREADY (s_axis_cc_tready),
+ .S_AXIS_RQ_TREADY (s_axis_rq_tready),
+ .CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]),
+ .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
+ .CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]),
+ .CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent),
+ .CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail),
+ .CFG_FC_CPLH (cfg_fc_cplh[7:0]),
+ .CFG_FC_CPLD (cfg_fc_cpld[11:0]),
+ .CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]),
+ .CFG_CURRENT_SPEED (cfg_current_speed[2:0]),
+ .CFG_MAX_PAYLOAD (cfg_max_payload[2:0]),
+ .CFG_MAX_READ_REQ (cfg_max_read_req[2:0]),
+ .CFG_FUNCTION_STATUS (cfg_function_status[7:0]),
+ .CFG_RCB_STATUS (cfg_rcb_status[1:0]),
+ .CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
+ .CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
+ .CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+ .CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
+ .CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
+ .CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
+ .CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+ .CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+ .CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+ .CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])
+ /*AUTOINST*/);
+
+ generate
+ for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
+ chnl_tester
+ #(/*AUTOINSTPARAM*/
+ // Parameters
+ .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
+ module1
+ (.CLK(user_clk),
+ .RST(rst_out), // riffa_reset includes riffa_endpoint resets
+ // Rx interface
+ .CHNL_RX_CLK(chnl_rx_clk[chnl]),
+ .CHNL_RX(chnl_rx[chnl]),
+ .CHNL_RX_ACK(chnl_rx_ack[chnl]),
+ .CHNL_RX_LAST(chnl_rx_last[chnl]),
+ .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]),
+ .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]),
+ .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
+ .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]),
+ .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
+ // Tx interface
+ .CHNL_TX_CLK(chnl_tx_clk[chnl]),
+ .CHNL_TX(chnl_tx[chnl]),
+ .CHNL_TX_ACK(chnl_tx_ack[chnl]),
+ .CHNL_TX_LAST(chnl_tx_last[chnl]),
+ .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]),
+ .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]),
+ .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
+ .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]),
+ .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
+ /*AUTOINST*/);
+ end
+ endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("../../../../riffa_hdl/" "../../")
+// End:
+
diff --git a/fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/ip/PCIeGen2x8If128.xci b/fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/ip/PCIeGen2x8If128.xci
new file mode 100644
index 0000000..bd1c9f2
--- /dev/null
+++ b/fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/ip/PCIeGen2x8If128.xci
@@ -0,0 +1,677 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ PCIeGen2x8If128
+
+
+ PCI_Express_Endpoint_device
+ None
+ false
+ 5.0_GT/s
+ X8
+ 100_MHz
+ false
+ false
+ false
+ false
+ 058000
+ 7028
+ false
+ false
+ false
+ 00_Not_Supported
+ false
+ false
+ NONE
+ false
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ false
+ false
+ false
+ 00
+ 0
+ N/A
+ 0000
+ 00000553
+ 0000
+ 0007
+ false
+ false
+ 058000
+ 7011
+ NONE
+ BAR_0
+ BAR_0
+ 000
+ 00000000
+ 00000000
+ 1_vector
+ 00
+ 0
+ 0
+ N/A
+ 0001
+ 00000553
+ 0000
+ 0007
+ true
+ false
+ false
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ PCIeGen2x8If128
+ false
+ false
+ false
+ 10EE
+ Kilobytes
+ 80
+ N/A
+ false
+ N/A
+ true
+ false
+ X0Y2
+ false
+ 05
+ false
+ false
+ false
+ N/A
+ false
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ 00
+ Kilobytes
+ N/A
+ Simple_communication_controllers
+ Generic_XT_compatible_serial_controller
+ Kilobytes
+ false
+ true
+ false
+ N/A
+ false
+ false
+ 00
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ Kilobytes
+ Kilobytes
+ Kilobytes
+ false
+ DWORD_Aligned
+ false
+ Production
+ false
+ false
+ 2
+ false
+ false
+ 2
+ true
+ Memory
+ false
+ false
+ Kilobytes
+ 1
+ false
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ false
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ false
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ false
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ false
+ N/A
+ false
+ Kilobytes
+ 2
+ Kilobytes
+ false
+ false
+ 2
+ Kilobytes
+ Kilobytes
+ 2
+ false
+ 512_bytes
+ false
+ 2
+ false
+ true
+ false
+ Kilobytes
+ 2
+ false
+ false
+ false
+ false
+ 2
+ false
+ false
+ false
+ Kilobytes
+ Simple_communication_controllers
+ Generic_XT_compatible_serial_controller
+ Memory
+ false
+ false
+ 2
+ Kilobytes
+ Kilobytes
+ 80
+ false
+ N/A
+ false
+ Kilobytes
+ 2
+ 2
+ false
+ false
+ false
+ N/A
+ 10EE
+ false
+ 2
+ N/A
+ 2
+ false
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ false
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ false
+ true
+ false
+ N/A
+ false
+ false
+ 0
+ 2
+ true
+ Kilobytes
+ false
+ N/A
+ false
+ Kilobytes
+ 2
+ false
+ Extreme
+ 05
+ 128_bit
+ false
+ Memory
+ 2
+ false
+ true
+ false
+ N/A
+ false
+ 2
+ true
+ false
+ false
+ N/A
+ false
+ 2
+ false
+ Kilobytes
+ 512_bytes
+ false
+ N/A
+ false
+ Advanced
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ false
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ None
+ 250
+ No_ASPM
+ false
+ Custom
+ false
+ 2FFFF
+ false
+ None
+ false
+ 2
+ 8
+ 4
+ 0
+ 128
+ 0
+ 3
+ FALSE
+ 0x00
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0b00011
+ 0b100
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0x80
+ 0x058000
+ 0x10EE
+ 0x7028
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ 00
+ FALSE
+ FALSE
+ FALSE
+ 0b010
+ 0x000
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x000
+ 0b00000
+ FALSE
+ 0x0
+ FALSE
+ 0x000
+ 0x00
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ 0xC0
+ 0x000
+ 0x90
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ 0x000
+ 0x00000
+ 0x00000
+ 0x00000
+ 0x00000
+ 0x00000
+ 0x00000
+ 0x00
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
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+ 0b00000
+ 0b000
+ 0x0000
+ 0x000
+ 0x0000
+ 0x0
+ 0x0000
+ 0x0000
+ 0x00000553
+ 0x0000
+ 0x10EE
+ 0x0007
+ FALSE
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ TRUE
+ FALSE
+ TRUE
+ FALSE
+ TRUE
+ FALSE
+ TRUE
+ FALSE
+ TRUE
+ FALSE
+ TRUE
+ FALSE
+ TRUE
+ FALSE
+ TRUE
+ FALSE
+ 0x000
+ 0x00000000
+ FALSE
+ FALSE
+ 0x000
+ 0x000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0x80
+ 0x058000
+ 0x7011
+ 0b010
+ 0x000
+ 0x000
+ 0b00000
+ FALSE
+ 0x0
+ 0x00
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ 0x00
+ 0x000
+ 0x00
+ FALSE
+ 0x000
+ 0x00
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0x0000
+ 0x000
+ 0x0000
+ 0x0
+ 0x0000
+ 0x0001
+ 0x00000553
+ 0x0000
+ 0x0007
+ FALSE
+ 0x000
+ TRUE
+ FALSE
+ 0x000
+ 0x00000000
+ 0x028
+ 0x20
+ 0x198
+ 0x20
+ FALSE
+ FALSE
+ FALSE
+ 0x80
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ "00000000"
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ "00000000"
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ "00000000"
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ "00000000"
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ "00000000"
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ "00000000"
+ 16KB
+ 0
+ 0
+ 1
+ 0
+ Production
+ 0
+ 2
+ FALSE
+ FALSE
+ TRUE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ TRUE
+ FALSE
+ FALSE
+ TRUE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ TRUE
+ 2.1
+ NONE
+ FALSE
+ FALSE
+ 0x00000
+ FALSE
+ FALSE
+ virtex7
+ xc7vx690t
+ ffg1157
+ -2
+ C
+
+ VERILOG
+ MIXED
+ TRUE
+ TRUE
+
+ TRUE
+ 2014.4
+ 4
+ OUT_OF_CONTEXT
+
+ .
+ .
+
+
+
+
diff --git a/fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/prj/7V3_Gen2x8If128.xpr b/fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/prj/7V3_Gen2x8If128.xpr
new file mode 100644
index 0000000..e686cd8
--- /dev/null
+++ b/fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/prj/7V3_Gen2x8If128.xpr
@@ -0,0 +1,790 @@
+
+
+
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diff --git a/fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/constr/7V3_Top.xdc b/fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/constr/7V3_Top.xdc
new file mode 100644
index 0000000..d83508b
--- /dev/null
+++ b/fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/constr/7V3_Top.xdc
@@ -0,0 +1,134 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above
+# copyright notice, this list of conditions and the following
+# disclaimer in the documentation and/or other materials provided
+# with the distribution.
+#
+# * Neither the name of The Regents of the University of California
+# nor the names of its contributors may be used to endorse or
+# promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename: 7V3_Top.xdc
+# Version: 1.00.a
+# Verilog Standard: Verilog-2001
+# Description: Xilinx Design Constraints for the Alpha Data 7V3 board.
+# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin
+#
+# Author: Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+#
+#########################################################################################################################
+# User Constraints
+#########################################################################################################################
+
+###############################################################################
+# User Time Names / User Time Groups / Time Specs
+###############################################################################
+
+###############################################################################
+# User Physical Constraints
+###############################################################################
+
+#
+# LED Status Indicators for Example Design.
+# LED 0-2 should be all ON if link is up and functioning correctly
+# LED 3 should be blinking if user application is receiving valid clock
+#
+
+#System Reset, User Reset, User Link Up, User Clk Heartbeat
+set_property PACKAGE_PIN AC33 [get_ports {LED[0]}]
+set_property PACKAGE_PIN V32 [get_ports {LED[1]}]
+set_property PACKAGE_PIN V33 [get_ports {LED[2]}]
+set_property PACKAGE_PIN AB31 [get_ports {LED[3]}]
+set_property PACKAGE_PIN AB32 [get_ports {LED[4]}]
+set_property PACKAGE_PIN U30 [get_ports {LED[5]}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LED[5]}]
+
+set_false_path -to [get_ports -filter NAME=~LED*]
+
+#########################################################################################################################
+# End User Constraints
+#########################################################################################################################
+#
+#
+#
+#########################################################################################################################
+# PCIE Core Constraints
+#########################################################################################################################
+
+#
+# SYS reset (input) signal. The sys_reset_n signal should be
+# obtained from the PCI Express interface if possible. For
+# slot based form factors, a system reset signal is usually
+# present on the connector. For cable based form factors, a
+# system reset signal may not be available. In this case, the
+# system reset signal must be generated locally by some form of
+# supervisory circuit. You may change the IOSTANDARD and LOC
+# to suit your requirements and VCCO voltage banking rules.
+# Some 7 series devices do not have 3.3 V I/Os available.
+# Therefore the appropriate level shift is required to operate
+# with these devices that contain only 1.8 V banks.
+#
+
+set_property PACKAGE_PIN W27 [get_ports PCIE_RESET_N]
+set_property IOSTANDARD LVCMOS18 [get_ports PCIE_RESET_N]
+set_property PULLUP true [get_ports PCIE_RESET_N]
+
+#
+#
+# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
+# signals are the PCI Express reference clock. Virtex-7 GT
+# Transceiver architecture requires the use of a dedicated clock
+# resources (FPGA input pins) associated with each GT Transceiver.
+# To use these pins an IBUFDS primitive (refclk_ibuf) is
+# instantiated in user's design.
+# Please refer to the Virtex-7 GT Transceiver User Guide
+# (UG) for guidelines regarding clock resource selection.
+#
+set_property LOC IBUFDS_GTE2_X1Y16 [get_cells refclk_ibuf]
+
+
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O]
+
+###############################################################################
+# Physical Constraints
+###############################################################################
+
+set_false_path -from [get_ports PCIE_RESET_N]
+###############################################################################
+# End
+###############################################################################
diff --git a/fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/hdl/ADM_PCIe_7V3Gen3x4If128.v b/fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/hdl/ADM_PCIe_7V3Gen3x4If128.v
new file mode 100644
index 0000000..b4e84ea
--- /dev/null
+++ b/fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/hdl/ADM_PCIe_7V3Gen3x4If128.v
@@ -0,0 +1,481 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+//
+// * Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// * Redistributions in binary form must reproduce the above
+// copyright notice, this list of conditions and the following
+// disclaimer in the documentation and/or other materials provided
+// with the distribution.
+//
+// * Neither the name of The Regents of the University of California
+// nor the names of its contributors may be used to endorse or
+// promote products derived from this software without specific
+// prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename: 7V3Gen3x4If128.v
+// Version: 1.00.a
+// Verilog Standard: Verilog-2001
+// Description: Top level module for RIFFA 2.2 reference design for the
+// the Xilinx 7V3 Development Board.
+// Author: Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "ultrascale.vh"
+`timescale 1ps / 1ps
+module ADM_PCIe_7V3Gen3x4If128
+ #(// Number of RIFFA Channels
+ parameter C_NUM_CHNL = 1,
+ // Number of PCIe Lanes
+ parameter C_NUM_LANES = 4,
+ // Settings from Vivado IP Generator
+ parameter C_PCI_DATA_WIDTH = 128,
+ parameter C_MAX_PAYLOAD_BYTES = 256,
+ parameter C_LOG_NUM_TAGS = 6)
+ (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
+ output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
+ input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
+ input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
+
+ output [5:0] LED,
+ input PCIE_REFCLK_P,
+ input PCIE_REFCLK_N,
+ input PCIE_RESET_N
+ );
+
+ // Clocks, etc
+ wire user_lnk_up;
+ wire user_clk;
+ wire user_reset;
+ wire pcie_refclk;
+ wire pcie_reset_n;
+
+ // Interface: RQ (TXC)
+ wire s_axis_rq_tlast;
+ wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata;
+ wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser;
+ wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
+ wire s_axis_rq_tready;
+ wire s_axis_rq_tvalid;
+ // Interface: RC (RXC)
+ wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata;
+ wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser;
+ wire m_axis_rc_tlast;
+ wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
+ wire m_axis_rc_tvalid;
+ wire m_axis_rc_tready;
+ // Interface: CQ (RXR)
+ wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata;
+ wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser;
+ wire m_axis_cq_tlast;
+ wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
+ wire m_axis_cq_tvalid;
+ wire m_axis_cq_tready;
+ // Interface: CC (TXC)
+ wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata;
+ wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser;
+ wire s_axis_cc_tlast;
+ wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
+ wire s_axis_cc_tvalid;
+ wire s_axis_cc_tready;
+
+ // Configuration (CFG) Interface
+ wire [3:0] pcie_rq_seq_num;
+ wire pcie_rq_seq_num_vld;
+ wire [5:0] pcie_rq_tag;
+ wire pcie_rq_tag_vld;
+ wire pcie_cq_np_req;
+ wire [5:0] pcie_cq_np_req_count;
+
+ wire cfg_phy_link_down;
+ wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH
+ wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE
+ wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD
+ wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
+ wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
+ wire [5:0] cfg_function_power_state; // Ignorable but not removable
+ wire [11:0] cfg_vf_status; // Ignorable but not removable
+ wire [17:0] cfg_vf_power_state; // Ignorable but not removable
+ wire [1:0] cfg_link_power_state; // Ignorable but not removable
+
+ // Error Reporting Interface
+ wire cfg_err_cor_out;
+ wire cfg_err_nonfatal_out;
+ wire cfg_err_fatal_out;
+
+ wire cfg_ltr_enable;
+ wire [5:0] cfg_ltssm_state;// TODO: Connect to LED's
+ wire [1:0] cfg_rcb_status;
+ wire [1:0] cfg_dpa_substate_change;
+ wire [1:0] cfg_obff_enable;
+ wire cfg_pl_status_change;
+
+ wire [1:0] cfg_tph_requester_enable;
+ wire [5:0] cfg_tph_st_mode;
+ wire [5:0] cfg_vf_tph_requester_enable;
+ wire [17:0] cfg_vf_tph_st_mode;
+ wire [7:0] cfg_fc_ph;
+ wire [11:0] cfg_fc_pd;
+ wire [7:0] cfg_fc_nph;
+ wire [11:0] cfg_fc_npd;
+ wire [7:0] cfg_fc_cplh;
+ wire [11:0] cfg_fc_cpld;
+ wire [2:0] cfg_fc_sel;
+
+ // Interrupt Interface Signals
+ wire [3:0] cfg_interrupt_int;
+ wire [1:0] cfg_interrupt_pending;
+ wire cfg_interrupt_sent;
+ wire [1:0] cfg_interrupt_msi_enable;
+ wire [5:0] cfg_interrupt_msi_vf_enable;
+ wire [5:0] cfg_interrupt_msi_mmenable;
+ wire cfg_interrupt_msi_mask_update;
+ wire [31:0] cfg_interrupt_msi_data;
+ wire [3:0] cfg_interrupt_msi_select;
+ wire [31:0] cfg_interrupt_msi_int;
+ wire [63:0] cfg_interrupt_msi_pending_status;
+ wire cfg_interrupt_msi_sent;
+ wire cfg_interrupt_msi_fail;
+ wire [2:0] cfg_interrupt_msi_attr;
+ wire cfg_interrupt_msi_tph_present;
+ wire [1:0] cfg_interrupt_msi_tph_type;
+ wire [8:0] cfg_interrupt_msi_tph_st_tag;
+ wire [2:0] cfg_interrupt_msi_function_number;
+
+ wire rst_out;
+ wire [C_NUM_CHNL-1:0] chnl_rx_clk;
+ wire [C_NUM_CHNL-1:0] chnl_rx;
+ wire [C_NUM_CHNL-1:0] chnl_rx_ack;
+ wire [C_NUM_CHNL-1:0] chnl_rx_last;
+ wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
+ wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
+ wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
+ wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
+ wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
+
+ wire [C_NUM_CHNL-1:0] chnl_tx_clk;
+ wire [C_NUM_CHNL-1:0] chnl_tx;
+ wire [C_NUM_CHNL-1:0] chnl_tx_ack;
+ wire [C_NUM_CHNL-1:0] chnl_tx_last;
+ wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
+ wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
+ wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
+ wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
+ wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
+
+ genvar chnl;
+
+ IBUF
+ #()
+ pci_reset_n_ibuf
+ (.O(pcie_reset_n),
+ .I(PCIE_RESET_N));
+
+ IBUFDS_GTE2
+ #()
+ refclk_ibuf
+ (.O(pcie_refclk),
+ .ODIV2(),
+ .I(PCIE_REFCLK_P),
+ .CEB(1'b0),
+ .IB(PCIE_REFCLK_N));
+
+ OBUF
+ #()
+ led_0_obuf
+ (.O(LED[0]),
+ .I(cfg_ltssm_state[0]));
+ OBUF
+ #()
+ led_1_obuf
+ (.O(LED[1]),
+ .I(cfg_ltssm_state[1]));
+ OBUF
+ #()
+ led_2_obuf
+ (.O(LED[2]),
+ .I(cfg_ltssm_state[2]));
+ OBUF
+ #()
+ led_3_obuf
+ (.O(LED[3]),
+ .I(cfg_ltssm_state[3]));
+ OBUF
+ #()
+ led_4_obuf
+ (.O(LED[4]),
+ .I(cfg_ltssm_state[4]));
+ OBUF
+ #()
+ led_5_obuf
+ (.O(LED[5]),
+ .I(cfg_ltssm_state[5]));
+ OBUF
+ #()
+ led_6_obuf
+ (.O(LED[6]),
+ .I(pcie_reset_n));
+ OBUF
+ #()
+ led_7_obuf
+ (.O(LED[7]),
+ .I(rst_out));
+
+ // Core Top Level Wrapper
+ PCIeGen3x4If128
+ #()
+ pcie3_7x_0_i
+ (//---------------------------------------------------------------------
+ // PCI Express (pci_exp) Interface
+ //---------------------------------------------------------------------
+ .pci_exp_txn ( PCI_EXP_TXN ),
+ .pci_exp_txp ( PCI_EXP_TXP ),
+ .pci_exp_rxn ( PCI_EXP_RXN ),
+ .pci_exp_rxp ( PCI_EXP_RXP ),
+
+ //---------------------------------------------------------------------
+ // AXI Interface
+ //---------------------------------------------------------------------
+ .user_clk ( user_clk ),
+ .user_reset ( user_reset ),
+ .user_lnk_up ( user_lnk_up ),
+ .user_app_rdy ( ),
+
+ .s_axis_rq_tlast ( s_axis_rq_tlast ),
+ .s_axis_rq_tdata ( s_axis_rq_tdata ),
+ .s_axis_rq_tuser ( s_axis_rq_tuser ),
+ .s_axis_rq_tkeep ( s_axis_rq_tkeep ),
+ .s_axis_rq_tready ( s_axis_rq_tready ),
+ .s_axis_rq_tvalid ( s_axis_rq_tvalid ),
+
+ .m_axis_rc_tdata ( m_axis_rc_tdata ),
+ .m_axis_rc_tuser ( m_axis_rc_tuser ),
+ .m_axis_rc_tlast ( m_axis_rc_tlast ),
+ .m_axis_rc_tkeep ( m_axis_rc_tkeep ),
+ .m_axis_rc_tvalid ( m_axis_rc_tvalid ),
+ .m_axis_rc_tready ( {22{m_axis_rc_tready}} ),
+
+ .m_axis_cq_tdata ( m_axis_cq_tdata ),
+ .m_axis_cq_tuser ( m_axis_cq_tuser ),
+ .m_axis_cq_tlast ( m_axis_cq_tlast ),
+ .m_axis_cq_tkeep ( m_axis_cq_tkeep ),
+ .m_axis_cq_tvalid ( m_axis_cq_tvalid ),
+ .m_axis_cq_tready ( {22{m_axis_cq_tready}} ),
+
+ .s_axis_cc_tdata ( s_axis_cc_tdata ),
+ .s_axis_cc_tuser ( s_axis_cc_tuser ),
+ .s_axis_cc_tlast ( s_axis_cc_tlast ),
+ .s_axis_cc_tkeep ( s_axis_cc_tkeep ),
+ .s_axis_cc_tvalid ( s_axis_cc_tvalid ),
+ .s_axis_cc_tready ( s_axis_cc_tready ),
+
+ //---------------------------------------------------------------------
+ // Configuration (CFG) Interface
+ //---------------------------------------------------------------------
+ .pcie_rq_seq_num ( pcie_rq_seq_num ),
+ .pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ),
+ .pcie_rq_tag ( pcie_rq_tag ),
+ .pcie_rq_tag_vld ( pcie_rq_tag_vld ),
+ .pcie_cq_np_req ( pcie_cq_np_req ),
+ .pcie_cq_np_req_count ( pcie_cq_np_req_count ),
+ .cfg_phy_link_down ( cfg_phy_link_down ),
+ .cfg_phy_link_status ( cfg_phy_link_status),
+ .cfg_negotiated_width ( cfg_negotiated_width ),
+ .cfg_current_speed ( cfg_current_speed ),
+ .cfg_max_payload ( cfg_max_payload ),
+ .cfg_max_read_req ( cfg_max_read_req ),
+ .cfg_function_status ( cfg_function_status ),
+ .cfg_function_power_state ( cfg_function_power_state ),
+ .cfg_vf_status ( cfg_vf_status ),
+ .cfg_vf_power_state ( cfg_vf_power_state ),
+ .cfg_link_power_state ( cfg_link_power_state ),
+ // Error Reporting Interface
+ .cfg_err_cor_out ( cfg_err_cor_out ),
+ .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ),
+ .cfg_err_fatal_out ( cfg_err_fatal_out ),
+ .cfg_ltr_enable ( cfg_ltr_enable ),
+ .cfg_ltssm_state ( cfg_ltssm_state ),
+ .cfg_rcb_status ( cfg_rcb_status ),
+ .cfg_dpa_substate_change ( cfg_dpa_substate_change ),
+ .cfg_obff_enable ( cfg_obff_enable ),
+ .cfg_pl_status_change ( cfg_pl_status_change ),
+ .cfg_tph_requester_enable ( cfg_tph_requester_enable ),
+ .cfg_tph_st_mode ( cfg_tph_st_mode ),
+ .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ),
+ .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ),
+ .cfg_fc_ph ( cfg_fc_ph ),
+ .cfg_fc_pd ( cfg_fc_pd ),
+ .cfg_fc_nph ( cfg_fc_nph ),
+ .cfg_fc_npd ( cfg_fc_npd ),
+ .cfg_fc_cplh ( cfg_fc_cplh ),
+ .cfg_fc_cpld ( cfg_fc_cpld ),
+ .cfg_fc_sel ( cfg_fc_sel ),
+ //---------------------------------------------------------------------
+ // EP Only
+ //---------------------------------------------------------------------
+ // Interrupt Interface Signals
+ .cfg_interrupt_int ( cfg_interrupt_int ),
+ .cfg_interrupt_pending ( cfg_interrupt_pending ),
+ .cfg_interrupt_sent ( cfg_interrupt_sent ),
+ .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ),
+ .cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ),
+ .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ),
+ .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ),
+ .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ),
+ .cfg_interrupt_msi_select ( cfg_interrupt_msi_select ),
+ .cfg_interrupt_msi_int ( cfg_interrupt_msi_int ),
+ .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ),
+ .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ),
+ .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ),
+ .cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ),
+ .cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ),
+ .cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ),
+ .cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ),
+ .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ),
+
+ //---------------------------------------------------------------------
+ // System(SYS) Interface
+ //---------------------------------------------------------------------
+ .sys_clk (pcie_refclk),
+ .sys_reset (~pcie_reset_n));
+
+ riffa_wrapper_7V3
+ #(/*AUTOINSTPARAM*/
+ // Parameters
+ .C_NUM_CHNL (C_NUM_CHNL),
+ .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
+ .C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES),
+ .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS))
+ riffa
+ (// Outputs
+ .M_AXIS_CQ_TREADY (m_axis_cq_tready),
+ .M_AXIS_RC_TREADY (m_axis_rc_tready),
+ .S_AXIS_CC_TVALID (s_axis_cc_tvalid),
+ .S_AXIS_CC_TLAST (s_axis_cc_tlast),
+ .S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
+ .S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+ .S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
+ .S_AXIS_RQ_TVALID (s_axis_rq_tvalid),
+ .S_AXIS_RQ_TLAST (s_axis_rq_tlast),
+ .S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
+ .S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+ .S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
+ .USER_CLK (user_clk),
+ .USER_RESET (user_reset),
+ .CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]),
+ .CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]),
+ .CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]),
+ .CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]),
+ .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
+ .CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]),
+ .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
+ .CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]),
+ .CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]),
+ .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
+ .CFG_FC_SEL (cfg_fc_sel[2:0]),
+ .PCIE_CQ_NP_REQ (pcie_cq_np_req),
+ .RST_OUT (rst_out),
+ .CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
+ .CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
+ .CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+ .CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+ .CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+ .CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+ .CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
+ .CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+ // Inputs
+ .M_AXIS_CQ_TVALID (m_axis_cq_tvalid),
+ .M_AXIS_CQ_TLAST (m_axis_cq_tlast),
+ .M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
+ .M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+ .M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
+ .M_AXIS_RC_TVALID (m_axis_rc_tvalid),
+ .M_AXIS_RC_TLAST (m_axis_rc_tlast),
+ .M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
+ .M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+ .M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
+ .S_AXIS_CC_TREADY (s_axis_cc_tready),
+ .S_AXIS_RQ_TREADY (s_axis_rq_tready),
+ .CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]),
+ .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
+ .CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]),
+ .CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent),
+ .CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail),
+ .CFG_FC_CPLH (cfg_fc_cplh[7:0]),
+ .CFG_FC_CPLD (cfg_fc_cpld[11:0]),
+ .CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]),
+ .CFG_CURRENT_SPEED (cfg_current_speed[2:0]),
+ .CFG_MAX_PAYLOAD (cfg_max_payload[2:0]),
+ .CFG_MAX_READ_REQ (cfg_max_read_req[2:0]),
+ .CFG_FUNCTION_STATUS (cfg_function_status[7:0]),
+ .CFG_RCB_STATUS (cfg_rcb_status[1:0]),
+ .CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
+ .CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
+ .CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+ .CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
+ .CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
+ .CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
+ .CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+ .CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+ .CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+ .CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])
+ /*AUTOINST*/);
+
+ generate
+ for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
+ chnl_tester
+ #(/*AUTOINSTPARAM*/
+ // Parameters
+ .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
+ module1
+ (.CLK(user_clk),
+ .RST(rst_out), // riffa_reset includes riffa_endpoint resets
+ // Rx interface
+ .CHNL_RX_CLK(chnl_rx_clk[chnl]),
+ .CHNL_RX(chnl_rx[chnl]),
+ .CHNL_RX_ACK(chnl_rx_ack[chnl]),
+ .CHNL_RX_LAST(chnl_rx_last[chnl]),
+ .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]),
+ .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]),
+ .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
+ .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]),
+ .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
+ // Tx interface
+ .CHNL_TX_CLK(chnl_tx_clk[chnl]),
+ .CHNL_TX(chnl_tx[chnl]),
+ .CHNL_TX_ACK(chnl_tx_ack[chnl]),
+ .CHNL_TX_LAST(chnl_tx_last[chnl]),
+ .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]),
+ .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]),
+ .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
+ .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]),
+ .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
+ /*AUTOINST*/);
+ end
+ endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("../../../../riffa_hdl/" "../../")
+// End:
+
diff --git a/fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/ip/PCIeGen3x4If128.xci b/fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/ip/PCIeGen3x4If128.xci
new file mode 100644
index 0000000..8aa4245
--- /dev/null
+++ b/fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/ip/PCIeGen3x4If128.xci
@@ -0,0 +1,677 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ PCIeGen3x4If128
+
+
+ PCI_Express_Endpoint_device
+ None
+ false
+ 8.0_GT/s
+ X4
+ 100_MHz
+ false
+ false
+ false
+ false
+ 058000
+ 7034
+ false
+ false
+ false
+ 00_Not_Supported
+ false
+ false
+ NONE
+ false
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ false
+ false
+ false
+ 00
+ 0
+ N/A
+ 0000
+ 00000553
+ 0000
+ 0007
+ false
+ false
+ 058000
+ 7011
+ NONE
+ BAR_0
+ BAR_0
+ 000
+ 00000000
+ 00000000
+ 1_vector
+ 00
+ 0
+ 0
+ N/A
+ 0001
+ 00000553
+ 0000
+ 0007
+ true
+ false
+ false
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ PCIeGen3x4If128
+ false
+ false
+ false
+ 10EE
+ Kilobytes
+ 80
+ N/A
+ false
+ N/A
+ true
+ false
+ X0Y2
+ false
+ 05
+ false
+ false
+ false
+ N/A
+ false
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ 00
+ Kilobytes
+ N/A
+ Simple_communication_controllers
+ Generic_XT_compatible_serial_controller
+ Kilobytes
+ false
+ true
+ false
+ N/A
+ false
+ false
+ 00
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ Kilobytes
+ Kilobytes
+ Kilobytes
+ false
+ DWORD_Aligned
+ false
+ Production
+ false
+ false
+ 2
+ false
+ false
+ 2
+ true
+ Memory
+ false
+ false
+ Kilobytes
+ 1
+ false
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ false
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ false
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ false
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ false
+ N/A
+ false
+ Kilobytes
+ 2
+ Kilobytes
+ false
+ false
+ 2
+ Kilobytes
+ Kilobytes
+ 2
+ false
+ 512_bytes
+ false
+ 2
+ false
+ true
+ false
+ Kilobytes
+ 2
+ false
+ false
+ false
+ false
+ 2
+ false
+ false
+ false
+ Kilobytes
+ Simple_communication_controllers
+ Generic_XT_compatible_serial_controller
+ Memory
+ false
+ false
+ 2
+ Kilobytes
+ Kilobytes
+ 80
+ false
+ N/A
+ false
+ Kilobytes
+ 2
+ 2
+ false
+ false
+ false
+ N/A
+ 10EE
+ false
+ 2
+ N/A
+ 2
+ false
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ false
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ false
+ true
+ false
+ N/A
+ false
+ false
+ 0
+ 2
+ true
+ Kilobytes
+ false
+ N/A
+ false
+ Kilobytes
+ 2
+ false
+ Extreme
+ 05
+ 128_bit
+ false
+ Memory
+ 2
+ false
+ true
+ false
+ N/A
+ false
+ 2
+ true
+ false
+ false
+ N/A
+ false
+ 2
+ false
+ Kilobytes
+ 512_bytes
+ false
+ N/A
+ false
+ Advanced
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ false
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ None
+ 250
+ No_ASPM
+ false
+ Custom
+ false
+ 2FFFF
+ false
+ None
+ false
+ 4
+ 4
+ 4
+ 0
+ 128
+ 0
+ 3
+ FALSE
+ 0x00
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ 0x300
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0b00011
+ 0b100
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0x80
+ 0x058000
+ 0x10EE
+ 0x7034
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ 00
+ FALSE
+ FALSE
+ FALSE
+ 0b010
+ 0x300
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x00
+ 0x300
+ 0b00000
+ FALSE
+ 0x0
+ FALSE
+ 0x300
+ 0x00
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ 0xC0
+ 0x274
+ 0x90
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ 0x300
+ 0x00000
+ 0x00000
+ 0x00000
+ 0x00000
+ 0x00000
+ 0x00000
+ 0x00
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0x0000
+ 0x300
+ 0x0000
+ 0x0
+ 0x0000
+ 0x0000
+ 0x00000553
+ 0x0000
+ 0x10EE
+ 0x0007
+ FALSE
+ 0x300
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0x000
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ TRUE
+ FALSE
+ TRUE
+ FALSE
+ TRUE
+ FALSE
+ TRUE
+ FALSE
+ TRUE
+ FALSE
+ TRUE
+ FALSE
+ TRUE
+ FALSE
+ TRUE
+ FALSE
+ 0x000
+ 0x00000000
+ FALSE
+ FALSE
+ 0x000
+ 0x000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0x80
+ 0x058000
+ 0x7011
+ 0b010
+ 0x000
+ 0x000
+ 0b00000
+ FALSE
+ 0x0
+ 0x00
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ 0x00
+ 0x000
+ 0x00
+ FALSE
+ 0x000
+ 0x00
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0b00000
+ 0b000
+ 0x0000
+ 0x000
+ 0x0000
+ 0x0
+ 0x0000
+ 0x0001
+ 0x00000553
+ 0x0000
+ 0x0007
+ FALSE
+ 0x000
+ TRUE
+ FALSE
+ 0x000
+ 0x00000000
+ 0x028
+ 0x20
+ 0x198
+ 0x20
+ FALSE
+ FALSE
+ FALSE
+ 0x80
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ "00000000"
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ "00000000"
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ "00000000"
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ "00000000"
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ "00000000"
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ "00000000"
+ 16KB
+ 0
+ 0
+ 1
+ 0
+ Production
+ 0
+ 2
+ FALSE
+ FALSE
+ TRUE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ TRUE
+ FALSE
+ FALSE
+ TRUE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ TRUE
+ 2.1
+ NONE
+ FALSE
+ FALSE
+ 0x00000
+ FALSE
+ FALSE
+ virtex7
+ xc7vx690t
+ ffg1157
+ -2
+ C
+
+ VERILOG
+ MIXED
+ TRUE
+ TRUE
+
+ TRUE
+ 2014.4
+ 4
+ OUT_OF_CONTEXT
+
+ .
+ .
+
+
+
+
diff --git a/fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/ip/PCIeGen3x4If128.xml b/fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/ip/PCIeGen3x4If128.xml
new file mode 100644
index 0000000..7f3f172
--- /dev/null
+++ b/fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/ip/PCIeGen3x4If128.xml
@@ -0,0 +1,15575 @@
+
+
+ xilinx.com
+ customized_ip
+ PCIeGen3x4If128
+ 1.0
+
+
+ m_axis_cq
+ m_axis_cq
+ The Completer Reqeust interface is used to transmit Completion TLP's to the Client Application
+
+
+
+
+
+
+ TDATA
+
+
+ m_axis_cq_tdata
+
+
+
+
+ TKEEP
+
+
+ m_axis_cq_tkeep
+
+
+
+
+ TLAST
+
+
+ m_axis_cq_tlast
+
+
+
+
+ TREADY
+
+
+ m_axis_cq_tready
+
+
+
+
+ TUSER
+
+
+ m_axis_cq_tuser
+
+
+
+
+ TVALID
+
+
+ m_axis_cq_tvalid
+
+
+
+
+
+ s_axis_cc
+ s_axis_cc
+ The Completer Completion Interface is used to transmit Completion TLP's
+
+
+
+
+
+
+ TDATA
+
+
+ s_axis_cc_tdata
+
+
+
+
+ TKEEP
+
+
+ s_axis_cc_tkeep
+
+
+
+
+ TLAST
+
+
+ s_axis_cc_tlast
+
+
+
+
+ TREADY
+
+
+ s_axis_cc_tready
+
+
+
+
+ TUSER
+
+
+ s_axis_cc_tuser
+
+
+
+
+ TVALID
+
+
+ s_axis_cc_tvalid
+
+
+
+
+
+ s_axis_rq
+ s_axis_rq
+ The Requestor Request interface received requests TLP's from the Client Application
+
+
+
+
+
+
+ TDATA
+
+
+ s_axis_rq_tdata
+
+
+
+
+ TKEEP
+
+
+ s_axis_rq_tkeep
+
+
+
+
+ TLAST
+
+
+ s_axis_rq_tlast
+
+
+
+
+ TREADY
+
+
+ s_axis_rq_tready
+
+
+
+
+ TUSER
+
+
+ s_axis_rq_tuser
+
+
+
+
+ TVALID
+
+
+ s_axis_rq_tvalid
+
+
+
+
+
+ m_axis_rc
+ m_axis_rc
+ The Requestor Completer interface transmits completions to the client application
+
+
+
+
+
+
+ TDATA
+
+
+ m_axis_rc_tdata
+
+
+
+
+ TKEEP
+
+
+ m_axis_rc_tkeep
+
+
+
+
+ TLAST
+
+
+ m_axis_rc_tlast
+
+
+
+
+ TREADY
+
+
+ m_axis_rc_tready
+
+
+
+
+ TUSER
+
+
+ m_axis_rc_tuser
+
+
+
+
+ TVALID
+
+
+ m_axis_rc_tvalid
+
+
+
+
+
+ icap
+ icap
+ ICAP Interface
+
+
+
+
+
+
+ clk
+
+
+ icap_clk
+
+
+
+
+ csib
+
+
+ icap_csib
+
+
+
+
+ i
+
+
+ icap_i
+
+
+
+
+ o
+
+
+ icap_o
+
+
+
+
+ rdwrb
+
+
+ icap_rdwrb
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ startup
+ startup
+ STARTUP interafce
+
+
+
+
+
+
+ cfgclk
+
+
+ startup_cfgclk
+
+
+
+
+ cfgmclk
+
+
+ startup_cfgmclk
+
+
+
+
+ clk
+
+
+ startup_clk
+
+
+
+
+ eos
+
+
+ startup_eos
+
+
+
+
+ gsr
+
+
+ startup_gsr
+
+
+
+
+ gts
+
+
+ startup_gts
+
+
+
+
+ keyclearb
+
+
+ startup_keyclearb
+
+
+
+
+ pack
+
+
+ startup_pack
+
+
+
+
+ preq
+
+
+ startup_preq
+
+
+
+
+ userdoneo
+
+
+ startup_usrdoneo
+
+
+
+
+ usrcclko
+
+
+ startup_usrcclko
+
+
+
+
+ usrclkts
+
+
+ startup_usrcclkts
+
+
+
+
+ usrdonets
+
+
+ startup_usrdonets
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie_7x_mgt
+ pcie_7x_mgt
+ PCIExpress Serial Link Interface
+
+
+
+
+
+
+ rxn
+
+
+ pci_exp_rxn
+
+
+
+
+ rxp
+
+
+ pci_exp_rxp
+
+
+
+
+ txn
+
+
+ pci_exp_txn
+
+
+
+
+ txp
+
+
+ pci_exp_txp
+
+
+
+
+
+ pipe_clock
+ pipe_clock
+ PCIExpress Enternal PIPE Clock interface
+
+
+
+
+
+
+ dclk_in
+
+
+ pipe_dclk_in
+
+
+
+
+ gen3_out
+
+
+ pipe_gen3_out
+
+
+
+
+ mmcm_lock_in
+
+
+ pipe_mmcm_lock_in
+
+
+
+
+ mmcm_rst_n
+
+
+ pipe_mmcm_rst_n
+
+
+
+
+ oobclk_in
+
+
+ pipe_oobclk_in
+
+
+
+
+ pclk_in
+
+
+ pipe_pclk_in
+
+
+
+
+ pclk_sel_out
+
+
+ pipe_pclk_sel_out
+
+
+
+
+ rxoutclk_in
+
+
+ pipe_rxoutclk_in
+
+
+
+
+ rxoutclk_out
+
+
+ pipe_rxoutclk_out
+
+
+
+
+ rxusrclk_in
+
+
+ pipe_rxusrclk_in
+
+
+
+
+ txoutclk_out
+
+
+ pipe_txoutclk_out
+
+
+
+
+ userclk1_in
+
+
+ pipe_userclk1_in
+
+
+
+
+ userclk2_in
+
+
+ pipe_userclk2_in
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ CLK.sys_clk
+ CLK.sys_clk
+ sys_clk interface
+
+
+
+
+
+
+ CLK
+
+
+ sys_clk
+
+
+
+
+
+ RST.sys_rst
+ RST.sys_rst
+ sys_rst interface
+
+
+
+
+
+
+ RST
+
+
+ sys_reset
+
+
+
+
+
+ POLARITY
+ ACTIVE_HIGH
+
+
+
+
+ CLK.user_clk
+ CLK.user_clk
+ user_clk interface
+
+
+
+
+
+
+ CLK
+
+
+ user_clk
+
+
+
+
+
+ ASSOCIATED_BUSIF
+ m_axis_cq:s_axis_cc:s_axis_rq:m_axis_rc
+
+
+ FREQ_HZ
+ 125000000
+
+
+ ASSOCIATED_RESET
+ user_reset
+
+
+
+
+ RST.user_reset
+ RST.user_reset
+ user_reset interface
+
+
+
+
+
+
+ RST
+
+
+ user_reset
+
+
+
+
+
+ POLARITY
+ ACTIVE_HIGH
+
+
+
+
+ pcie3_cfg_control
+ pcie3_cfg_control
+ It allows a broad range of information exchange between user application and the core
+
+
+
+
+
+
+ config_space_enable
+
+
+ cfg_config_space_enable
+
+
+
+
+ ds_bus_number
+
+
+ cfg_ds_bus_number
+
+
+
+
+ ds_device_number
+
+
+ cfg_ds_device_number
+
+
+
+
+ ds_function_number
+
+
+ cfg_ds_function_number
+
+
+
+
+ ds_port_number
+
+
+ cfg_ds_port_number
+
+
+
+
+ dsn
+
+
+ cfg_dsn
+
+
+
+
+ err_cor_in
+
+
+ cfg_err_cor_in
+
+
+
+
+ err_uncor_in
+
+
+ cfg_err_uncor_in
+
+
+
+
+ flr_done
+
+
+ cfg_flr_done
+
+
+
+
+ flr_in_process
+
+
+ cfg_flr_in_process
+
+
+
+
+ hot_reset_in
+
+
+ cfg_hot_reset_in
+
+
+
+
+ hot_reset_out
+
+
+ cfg_hot_reset_out
+
+
+
+
+ link_training_enable
+
+
+ cfg_link_training_enable
+
+
+
+
+ per_function_number
+
+
+ cfg_per_function_number
+
+
+
+
+ per_function_output_request
+
+
+ cfg_per_function_output_request
+
+
+
+
+ per_function_update_done
+
+
+ cfg_per_function_update_done
+
+
+
+
+ power_state_change_ack
+
+
+ cfg_power_state_change_ack
+
+
+
+
+ power_state_change_interrupt
+
+
+ cfg_power_state_change_interrupt
+
+
+
+
+ req_pm_transition_l23_ready
+
+
+ cfg_req_pm_transition_l23_ready
+
+
+
+
+ subsys_vend_id
+
+
+ cfg_subsys_vend_id
+
+
+
+
+ vf_flr_done
+
+
+ cfg_vf_flr_done
+
+
+
+
+ vf_flr_in_process
+
+
+ cfg_vf_flr_in_process
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie3_cfg_ext
+ pcie3_cfg_ext
+ Configuration Extend Interface
+
+
+
+
+
+
+ function_number
+
+
+ cfg_ext_function_number
+
+
+
+
+ read_data
+
+
+ cfg_ext_read_data
+
+
+
+
+ read_data_valid
+
+
+ cfg_ext_read_data_valid
+
+
+
+
+ read_received
+
+
+ cfg_ext_read_received
+
+
+
+
+ register_number
+
+
+ cfg_ext_register_number
+
+
+
+
+ write_byte_enable
+
+
+ cfg_ext_write_byte_enable
+
+
+
+
+ write_data
+
+
+ cfg_ext_write_data
+
+
+
+
+ write_received
+
+
+ cfg_ext_write_received
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie3_cfg_mesg_tx
+ pcie3_cfg_mesg_tx
+ Configuration Transmit Message Interface
+
+
+
+
+
+
+ TRANSMIT
+
+
+ cfg_msg_transmit
+
+
+
+
+ TRANSMIT_DATA
+
+
+ cfg_msg_transmit_data
+
+
+
+
+ TRANSMIT_DONE
+
+
+ cfg_msg_transmit_done
+
+
+
+
+ TRANSMIT_TYPE
+
+
+ cfg_msg_transmit_type
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie3_cfg_mesg_rcvd
+ pcie3_cfg_mesg_rcvd
+ Configuration Received Message Interface
+
+
+
+
+
+
+ recd
+
+
+ cfg_msg_received
+
+
+
+
+ recd_data
+
+
+ cfg_msg_received_data
+
+
+
+
+ recd_type
+
+
+ cfg_msg_received_type
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie3_cfg_status
+ pcie3_cfg_status
+ Configuration Status Interface
+
+
+
+
+
+
+ cq_np_req
+
+
+ pcie_cq_np_req
+
+
+
+
+ cq_np_req_count
+
+
+ pcie_cq_np_req_count
+
+
+
+
+ current_speed
+
+
+ cfg_current_speed
+
+
+
+
+ dpa_substate_change
+
+
+ cfg_dpa_substate_change
+
+
+
+
+ err_cor_out
+
+
+ cfg_err_cor_out
+
+
+
+
+ err_fatal_out
+
+
+ cfg_err_fatal_out
+
+
+
+
+ err_nonfatal_out
+
+
+ cfg_err_nonfatal_out
+
+
+
+
+ function_power_state
+
+
+ cfg_function_power_state
+
+
+
+
+ function_status
+
+
+ cfg_function_status
+
+
+
+
+ link_power_state
+
+
+ cfg_link_power_state
+
+
+
+
+ ltr_enable
+
+
+ cfg_ltr_enable
+
+
+
+
+ ltssm_state
+
+
+ cfg_ltssm_state
+
+
+
+
+ max_payload
+
+
+ cfg_max_payload
+
+
+
+
+ max_read_req
+
+
+ cfg_max_read_req
+
+
+
+
+ negotiated_width
+
+
+ cfg_negotiated_width
+
+
+
+
+ obff_enable
+
+
+ cfg_obff_enable
+
+
+
+
+ phy_link_down
+
+
+ cfg_phy_link_down
+
+
+
+
+ phy_link_status
+
+
+ cfg_phy_link_status
+
+
+
+
+ pl_status_change
+
+
+ cfg_pl_status_change
+
+
+
+
+ rcb_status
+
+
+ cfg_rcb_status
+
+
+
+
+ rq_seq_num
+
+
+ pcie_rq_seq_num
+
+
+
+
+ rq_seq_num_vld
+
+
+ pcie_rq_seq_num_vld
+
+
+
+
+ rq_tag
+
+
+ pcie_rq_tag
+
+
+
+
+ rq_tag_vld
+
+
+ pcie_rq_tag_vld
+
+
+
+
+ tph_requester_enable
+
+
+ cfg_tph_requester_enable
+
+
+
+
+ tph_st_mode
+
+
+ cfg_tph_st_mode
+
+
+
+
+ vf_power_state
+
+
+ cfg_vf_power_state
+
+
+
+
+ vf_status
+
+
+ cfg_vf_status
+
+
+
+
+ vf_tph_requester_enable
+
+
+ cfg_vf_tph_requester_enable
+
+
+
+
+ vf_tph_st_mode
+
+
+ cfg_vf_tph_st_mode
+
+
+
+
+
+
+ optional
+ true
+
+
+
+
+
+ pcie3_per_func_status
+ pcie3_per_func_status
+ Per Function Status Interface
+
+
+
+
+
+
+ STATUS_CONTROL
+
+
+ cfg_per_func_status_control
+
+
+
+
+ STATUS_DATA
+
+
+ cfg_per_func_status_data
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie3_transmit_fc
+ pcie3_transmit_fc
+ Transmit Flow Control Interfce
+
+
+
+
+
+
+ npd_av
+
+
+ pcie_tfc_npd_av
+
+
+
+
+ nph_av
+
+
+ pcie_tfc_nph_av
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie3_user_tph
+ pcie3_user_tph
+ PCIE TPH Interface
+
+
+
+
+
+
+ function_num
+
+
+ user_tph_function_num
+
+
+
+
+ stt_address
+
+
+ user_tph_stt_address
+
+
+
+
+ stt_read_data
+
+
+ user_tph_stt_read_data
+
+
+
+
+ stt_read_data_valid
+
+
+ user_tph_stt_read_data_valid
+
+
+
+
+ stt_read_enable
+
+
+ user_tph_stt_read_enable
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie_cfg_fc
+ pcie_cfg_fc
+ Configuration Flow Control INTERFACE
+
+
+
+
+
+
+ CPLD
+
+
+ cfg_fc_cpld
+
+
+
+
+ CPLH
+
+
+ cfg_fc_cplh
+
+
+
+
+ NPD
+
+
+ cfg_fc_npd
+
+
+
+
+ NPH
+
+
+ cfg_fc_nph
+
+
+
+
+ PD
+
+
+ cfg_fc_pd
+
+
+
+
+ PH
+
+
+ cfg_fc_ph
+
+
+
+
+ SEL
+
+
+ cfg_fc_sel
+
+
+
+
+
+
+ optional
+ true
+
+
+
+
+
+ pcie_cfg_mgmt
+ pcie_cfg_mgmt
+ PCIE Configuration Management Interface
+
+
+
+
+
+
+ ADDR
+
+
+ cfg_mgmt_addr
+
+
+
+
+ BYTE_EN
+
+
+ cfg_mgmt_byte_enable
+
+
+
+
+ READ_DATA
+
+
+ cfg_mgmt_read_data
+
+
+
+
+ READ_EN
+
+
+ cfg_mgmt_read
+
+
+
+
+ READ_WRITE_DONE
+
+
+ cfg_mgmt_read_write_done
+
+
+
+
+ TYPE1_CFG_REG_ACCESS
+
+
+ cfg_mgmt_type1_cfg_reg_access
+
+
+
+
+ WRITE_DATA
+
+
+ cfg_mgmt_write_data
+
+
+
+
+ WRITE_EN
+
+
+ cfg_mgmt_write
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie3_cfg_msi
+ pcie3_cfg_msi
+ PCIE MSI interrupt
+
+
+
+
+
+
+ attr
+
+
+ cfg_interrupt_msi_attr
+
+
+
+
+ data
+
+
+ cfg_interrupt_msi_data
+
+
+
+
+ enable
+
+
+ cfg_interrupt_msi_enable
+
+
+
+
+ fail
+
+
+ cfg_interrupt_msi_fail
+
+
+
+
+ function_number
+
+
+ cfg_interrupt_msi_function_number
+
+
+
+
+ int_vector
+
+
+ cfg_interrupt_msi_int
+
+
+
+
+ mask_update
+
+
+ cfg_interrupt_msi_mask_update
+
+
+
+
+ mmenable
+
+
+ cfg_interrupt_msi_mmenable
+
+
+
+
+ pending_status
+
+
+ cfg_interrupt_msi_pending_status
+
+
+
+
+ select
+
+
+ cfg_interrupt_msi_select
+
+
+
+
+ sent
+
+
+ cfg_interrupt_msi_sent
+
+
+
+
+ tph_present
+
+
+ cfg_interrupt_msi_tph_present
+
+
+
+
+ tph_st_tag
+
+
+ cfg_interrupt_msi_tph_st_tag
+
+
+
+
+ tph_type
+
+
+ cfg_interrupt_msi_tph_type
+
+
+
+
+ vf_enable
+
+
+ cfg_interrupt_msi_vf_enable
+
+
+
+
+
+
+ optional
+ true
+
+
+
+
+
+ pcie3_cfg_msix
+ pcie3_cfg_msix
+ PCIE MSIx Interrupt
+
+
+
+
+
+
+ address
+
+
+ cfg_interrupt_msix_address
+
+
+
+
+ data
+
+
+ cfg_interrupt_msix_data
+
+
+
+
+ enable
+
+
+ cfg_interrupt_msix_enable
+
+
+
+
+ fail
+
+
+ cfg_interrupt_msix_fail
+
+
+
+
+ int_vector
+
+
+ cfg_interrupt_msix_int
+
+
+
+
+ mask
+
+
+ cfg_interrupt_msix_mask
+
+
+
+
+ sent
+
+
+ cfg_interrupt_msix_sent
+
+
+
+
+ vf_enable
+
+
+ cfg_interrupt_msix_vf_enable
+
+
+
+
+ vf_mask
+
+
+ cfg_interrupt_msix_vf_mask
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie3_cfg_interrupt
+ pcie3_cfg_interrupt
+ PCIE Legacy Interrupt
+
+
+
+
+
+
+ INTx_VECTOR
+
+
+ cfg_interrupt_int
+
+
+
+
+ PENDING
+
+
+ cfg_interrupt_pending
+
+
+
+
+ SENT
+
+
+ cfg_interrupt_sent
+
+
+
+
+
+ pcie_ext_ch_gt
+ pcie_ext_ch_gt
+ channel DRP signals
+
+
+
+
+
+
+ DADDR
+
+
+ ext_ch_gt_drpaddr
+
+
+
+
+ DEN
+
+
+ ext_ch_gt_drpen
+
+
+
+
+ DI
+
+
+ ext_ch_gt_drpdi
+
+
+
+
+ DO
+
+
+ ext_ch_gt_drpdo
+
+
+
+
+ DRDY
+
+
+ ext_ch_gt_drprdy
+
+
+
+
+ DWE
+
+
+ ext_ch_gt_drpwe
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ transceiver_debug
+ transceiver_debug
+ Transceiver Debug Interface
+
+
+
+
+
+
+ cpll_lock
+
+
+ pipe_cpll_lock
+
+
+
+
+ debug
+
+
+ pipe_debug
+
+
+
+
+ debug_0
+
+
+ pipe_debug_0
+
+
+
+
+ debug_1
+
+
+ pipe_debug_1
+
+
+
+
+ debug_2
+
+
+ pipe_debug_2
+
+
+
+
+ debug_3
+
+
+ pipe_debug_3
+
+
+
+
+ debug_4
+
+
+ pipe_debug_4
+
+
+
+
+ debug_5
+
+
+ pipe_debug_5
+
+
+
+
+ debug_6
+
+
+ pipe_debug_6
+
+
+
+
+ debug_7
+
+
+ pipe_debug_7
+
+
+
+
+ debug_8
+
+
+ pipe_debug_8
+
+
+
+
+ debug_9
+
+
+ pipe_debug_9
+
+
+
+
+ dmonitorout
+
+
+ pipe_dmonitorout
+
+
+
+
+ drp_fsm
+
+
+ pipe_drp_fsm
+
+
+
+
+ eyescandataerror
+
+
+ pipe_eyescandataerror
+
+
+
+
+ gt_ch_drp_rdy
+
+
+ gt_ch_drp_rdy
+
+
+
+
+ loopback
+
+
+ pipe_loopback
+
+
+
+
+ qpll_lock
+
+
+ pipe_qpll_lock
+
+
+
+
+ qrst_fsm
+
+
+ pipe_qrst_fsm
+
+
+
+
+ qrst_idle
+
+
+ pipe_qrst_idle
+
+
+
+
+ rate_fsm
+
+
+ pipe_rate_fsm
+
+
+
+
+ rate_idle
+
+
+ pipe_rate_idle
+
+
+
+
+ rst_fsm
+
+
+ pipe_rst_fsm
+
+
+
+
+ rst_idle
+
+
+ pipe_rst_idle
+
+
+
+
+ rxbufstatus
+
+
+ pipe_rxbufstatus
+
+
+
+
+ rxcommadet
+
+
+ pipe_rxcommadet
+
+
+
+
+ rxdisperr
+
+
+ pipe_rxdisperr
+
+
+
+
+ rxdlysresetdone
+
+
+ pipe_rxdlysresetdone
+
+
+
+
+ rxnotintable
+
+
+ pipe_rxnotintable
+
+
+
+
+ rxphaligndone
+
+
+ pipe_rxphaligndone
+
+
+
+
+ rxpmaresetdone
+
+
+ pipe_rxpmaresetdone
+
+
+
+
+ rxprbscntreset
+
+
+ pipe_rxprbscntreset
+
+
+
+
+ rxprbserr
+
+
+ pipe_rxprbserr
+
+
+
+
+ rxprbssel
+
+
+ pipe_rxprbssel
+
+
+
+
+ rxstatus
+
+
+ pipe_rxstatus
+
+
+
+
+ rxsyncdone
+
+
+ pipe_rxsyncdone
+
+
+
+
+ sync_fsm_rx
+
+
+ pipe_sync_fsm_rx
+
+
+
+
+ sync_fsm_tx
+
+
+ pipe_sync_fsm_tx
+
+
+
+
+ txdlysresetdone
+
+
+ pipe_txdlysresetdone
+
+
+
+
+ txphaligndone
+
+
+ pipe_txphaligndone
+
+
+
+
+ txphinitdone
+
+
+ pipe_txphinitdone
+
+
+
+
+ txprbsforceerr
+
+
+ pipe_txprbsforceerr
+
+
+
+
+ txprbssel
+
+
+ pipe_txprbssel
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie3_sharedlogic_int_clk
+ pcie3_sharedlogic_int_clk
+ PCIe3 Shared logic interface
+
+
+
+
+
+
+ dclk
+
+
+ int_dclk_out
+
+
+
+
+ oobclk
+
+
+ int_oobclk_out
+
+
+
+
+ pclk_sel_slave
+
+
+ int_pclk_sel_slave
+
+
+
+
+ pclk_slave
+
+
+ int_pclk_out_slave
+
+
+
+
+ pipe_rxusrclk
+
+
+ int_pipe_rxusrclk_out
+
+
+
+
+ qplllock
+
+
+ int_qplllock_out
+
+
+
+
+ qplloutclk
+
+
+ int_qplloutclk_out
+
+
+
+
+ qplloutrefclk
+
+
+ int_qplloutrefclk_out
+
+
+
+
+ rxoutclk
+
+
+ int_rxoutclk_out
+
+
+
+
+ usrclk1
+
+
+ int_userclk1_out
+
+
+
+
+ usrclk2
+
+
+ int_userclk2_out
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie3_qpll_drp
+ pcie3_qpll_drp
+ PCIe Gen3 external gt_common Interface
+
+
+
+
+
+
+ clk
+
+
+ qpll_drp_clk
+
+
+
+
+ crscode
+
+
+ qpll_drp_crscode
+
+
+
+
+ done
+
+
+ qpll_drp_done
+
+
+
+
+ fsm
+
+
+ qpll_drp_fsm
+
+
+
+
+ gen3
+
+
+ qpll_drp_gen3
+
+
+
+
+ ovrd
+
+
+ qpll_drp_ovrd
+
+
+
+
+ qplld
+
+
+ qpll_qplld
+
+
+
+
+ qplllock
+
+
+ qpll_qplllock
+
+
+
+
+ qplloutclk
+
+
+ qpll_qplloutclk
+
+
+
+
+ qplloutrefclk
+
+
+ qpll_qplloutrefclk
+
+
+
+
+ qpllreset
+
+
+ qpll_qpllreset
+
+
+
+
+ reset
+
+
+ qpll_drp_reset
+
+
+
+
+ rst_n
+
+
+ qpll_drp_rst_n
+
+
+
+
+ start
+
+
+ qpll_drp_start
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie_drp
+ pcie_drp
+ PCIE DRP Interface
+
+
+
+
+
+
+ DADDR
+
+
+ pcie_drp_addr
+
+
+
+
+ DEN
+
+
+ pcie_drp_en
+
+
+
+
+ DI
+
+
+ pcie_drp_di
+
+
+
+
+ DO
+
+
+ pcie_drp_do
+
+
+
+
+ DRDY
+
+
+ pcie_drp_rdy
+
+
+
+
+ DWE
+
+
+ pcie_drp_we
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie3_ext_pipe_interface
+ pcie3_ext_pipe_interface
+ PCIE3 External PIPE Interface
+
+
+
+
+
+
+ commands_in
+
+
+ common_commands_in
+
+
+
+
+ commands_out
+
+
+ common_commands_out
+
+
+
+
+ rx_0_sigs
+
+
+ pipe_rx_0_sigs
+
+
+
+
+ rx_1_sigs
+
+
+ pipe_rx_1_sigs
+
+
+
+
+ rx_2_sigs
+
+
+ pipe_rx_2_sigs
+
+
+
+
+ rx_3_sigs
+
+
+ pipe_rx_3_sigs
+
+
+
+
+ rx_4_sigs
+
+
+ pipe_rx_4_sigs
+
+
+
+
+ rx_5_sigs
+
+
+ pipe_rx_5_sigs
+
+
+
+
+ rx_6_sigs
+
+
+ pipe_rx_6_sigs
+
+
+
+
+ rx_7_sigs
+
+
+ pipe_rx_7_sigs
+
+
+
+
+ tx_0_sigs
+
+
+ pipe_tx_0_sigs
+
+
+
+
+ tx_1_sigs
+
+
+ pipe_tx_1_sigs
+
+
+
+
+ tx_2_sigs
+
+
+ pipe_tx_2_sigs
+
+
+
+
+ tx_3_sigs
+
+
+ pipe_tx_3_sigs
+
+
+
+
+ tx_4_sigs
+
+
+ pipe_tx_4_sigs
+
+
+
+
+ tx_5_sigs
+
+
+ pipe_tx_5_sigs
+
+
+
+
+ tx_6_sigs
+
+
+ pipe_tx_6_sigs
+
+
+
+
+ tx_7_sigs
+
+
+ pipe_tx_7_sigs
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie3_powerdown_interface
+ pcie3_powerdown_interface
+ PCIE3 Powerdown Port Interface
+
+
+
+
+
+
+ cpllpd
+
+
+ cpllpd
+
+
+
+
+ powerdown
+
+
+ powerdown
+
+
+
+
+ qpllpd
+
+
+ qpllpd
+
+
+
+
+ rxpd
+
+
+ rxpd
+
+
+
+
+ txdetectrx
+
+
+ txdetectrx
+
+
+
+
+ txelecidle
+
+
+ txelecidle
+
+
+
+
+ txpd
+
+
+ txpd
+
+
+
+
+ txpdelecidlemode
+
+
+ txpdelecidlemode
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+
+
+
+ xilinx_elaboratesubcores
+ Elaborate Sub-Cores
+ :vivado.xilinx.com:elaborate.subcores
+
+ xilinx_elaboratesubcores_view_fileset
+
+
+
+ customizationCRC
+ a7feee67
+
+
+ customizationCRCversion
+ 4
+
+
+
+
+ xilinx_veriloginstantiationtemplate
+ Verilog Instantiation Template
+ verilogSource:vivado.xilinx.com:synthesis.template
+ verilog
+
+ xilinx_veriloginstantiationtemplate_view_fileset
+
+
+
+ customizationCRC
+ a7feee67
+
+
+ customizationCRCversion
+ 4
+
+
+ GENtimestamp
+ Tue Jul 28 21:25:54 UTC 2015
+
+
+ StaleAtRelink
+ false
+
+
+
+
+ xilinx_verilogsynthesis
+ Verilog Synthesis
+ verilogSource:vivado.xilinx.com:synthesis
+ verilog
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+ xilinx_verilogsynthesis_view_fileset
+
+
+
+ customizationCRC
+ a7feee67
+
+
+ customizationCRCversion
+ 4
+
+
+ GENtimestamp
+ Tue Jul 28 21:26:01 UTC 2015
+
+
+ StaleAtRelink
+ false
+
+
+
+
+ xilinx_verilogsynthesiswrapper
+ Verilog Synthesis Wrapper
+ verilogSource:vivado.xilinx.com:synthesis.wrapper
+ verilog
+
+ xilinx_verilogsynthesiswrapper_view_fileset
+
+
+
+ customizationCRC
+ a7feee67
+
+
+ customizationCRCversion
+ 4
+
+
+ GENtimestamp
+ Tue Jul 28 21:26:01 UTC 2015
+
+
+ StaleAtRelink
+ false
+
+
+
+
+ xilinx_verilogbehavioralsimulation
+ Verilog Simulation
+ verilogSource:vivado.xilinx.com:simulation
+ verilog
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+ xilinx_verilogbehavioralsimulation_view_fileset
+
+
+
+ customizationCRC
+ 08eb03a1
+
+
+ customizationCRCversion
+ 4
+
+
+ GENtimestamp
+ Tue Jul 28 21:26:01 UTC 2015
+
+
+ StaleAtRelink
+ false
+
+
+
+
+ xilinx_verilogsimulationwrapper
+ Verilog Simulation Wrapper
+ verilogSource:vivado.xilinx.com:simulation.wrapper
+ verilog
+
+ xilinx_verilogsimulationwrapper_view_fileset
+
+
+
+ customizationCRC
+ 08eb03a1
+
+
+ customizationCRCversion
+ 4
+
+
+ GENtimestamp
+ Tue Jul 28 21:26:02 UTC 2015
+
+
+ StaleAtRelink
+ false
+
+
+
+
+ xilinx_versioninformation
+ Version Information
+ :vivado.xilinx.com:docs.versioninfo
+
+ xilinx_versioninformation_view_fileset
+
+
+
+ customizationCRC
+ a7feee67
+
+
+ customizationCRCversion
+ 4
+
+
+ GENtimestamp
+ Tue Jul 28 21:26:02 UTC 2015
+
+
+ StaleAtRelink
+ false
+
+
+
+
+ xilinx_externalfiles
+ External Files
+ :vivado.xilinx.com:external.files
+
+ xilinx_externalfiles_view_fileset
+
+
+
+ customizationCRC
+ a7feee67
+
+
+ customizationCRCversion
+ 4
+
+
+ GENtimestamp
+ Thu Jan 01 00:00:00 UTC 1970
+
+
+ StaleAtRelink
+ false
+
+
+
+
+
+
+ pci_exp_txn
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ true
+
+
+
+
+
+ pci_exp_txp
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ true
+
+
+
+
+
+ pci_exp_rxn
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ true
+
+
+
+
+
+ pci_exp_rxp
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ true
+
+
+
+
+
+ int_pclk_out_slave
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ int_pipe_rxusrclk_out
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ int_rxoutclk_out
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ int_dclk_out
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ int_userclk1_out
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ int_userclk2_out
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ int_oobclk_out
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ int_qplllock_out
+
+ out
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ int_qplloutclk_out
+
+ out
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ int_qplloutrefclk_out
+
+ out
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ int_pclk_sel_slave
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_pclk_in
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_rxusrclk_in
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_rxoutclk_in
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_dclk_in
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_userclk1_in
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_userclk2_in
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_oobclk_in
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_mmcm_lock_in
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 1
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_txoutclk_out
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_rxoutclk_out
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_pclk_sel_out
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_gen3_out
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_mmcm_rst_n
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 1
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ user_clk
+
+ out
+
+
+ wire
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ true
+
+
+
+
+
+ user_reset
+
+ out
+
+
+ reg
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ true
+
+
+
+
+
+ user_lnk_up
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+ user_app_rdy
+
+ out
+
+
+ wire
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+ s_axis_rq_tlast
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ true
+
+
+
+
+
+ s_axis_rq_tdata
+
+ in
+
+ 127
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ true
+
+
+
+
+
+ s_axis_rq_tuser
+
+ in
+
+ 59
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ true
+
+
+
+
+
+ s_axis_rq_tkeep
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ true
+
+
+
+
+
+ s_axis_rq_tready
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ true
+
+
+
+
+
+ s_axis_rq_tvalid
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ true
+
+
+
+
+
+ m_axis_rc_tdata
+
+ out
+
+ 127
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ true
+
+
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+
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+
+
+ optional
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+
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+
+ cfg_subsys_vend_id
+
+ in
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+ 15
+ 0
+
+
+
+ std_logic_vector
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+ xilinx_verilogbehavioralsimulation
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+ 0x10EE
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+ optional
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+
+ cfg_dsn
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+ in
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+ 63
+ 0
+
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+ xilinx_verilogbehavioralsimulation
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+ 0
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+ optional
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+
+ cfg_power_state_change_ack
+
+ in
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+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
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+
+
+ 0
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+
+ optional
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+
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+
+
+ cfg_power_state_change_interrupt
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+ out
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+
+ std_logic
+ xilinx_verilogsynthesis
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+ optional
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+ cfg_err_cor_in
+
+ in
+
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+ std_logic
+ xilinx_verilogsynthesis
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+ 0
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+ cfg_err_uncor_in
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+ in
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+ 0
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+ optional
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+ cfg_flr_in_process
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+ out
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+ 1
+ 0
+
+
+
+ std_logic_vector
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+ optional
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+ cfg_flr_done
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+ in
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+ 1
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+
+
+
+ std_logic_vector
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+ 0
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+
+ optional
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+
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+ cfg_vf_flr_in_process
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+ 5
+ 0
+
+
+
+ std_logic_vector
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+
+
+
+ optional
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+
+ cfg_vf_flr_done
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+ in
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+ 5
+ 0
+
+
+
+ std_logic_vector
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+ xilinx_verilogbehavioralsimulation
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+
+
+ 0
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+
+ optional
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+
+
+
+
+
+ cfg_link_training_enable
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
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+
+
+ 1
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+
+
+
+
+ optional
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+
+
+
+
+
+ cfg_ext_read_received
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
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+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_ext_write_received
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_ext_register_number
+
+ out
+
+ 9
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
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+
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+ optional
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+
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+ cfg_ext_function_number
+
+ out
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+ 7
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+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
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+ optional
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+
+ cfg_ext_write_data
+
+ out
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+ 31
+ 0
+
+
+
+ std_logic_vector
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+
+
+
+
+
+
+ optional
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+
+
+
+
+
+ cfg_ext_write_byte_enable
+
+ out
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+ 3
+ 0
+
+
+
+ std_logic_vector
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+
+
+
+
+
+
+ optional
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+
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+
+ cfg_ext_read_data
+
+ in
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+ 31
+ 0
+
+
+
+ std_logic_vector
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+ 0
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+
+
+
+ optional
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+
+
+ cfg_ext_read_data_valid
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+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
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+
+
+ 0
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+
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+
+
+ optional
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+
+
+
+
+
+ cfg_interrupt_int
+
+ in
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+ 3
+ 0
+
+
+
+ std_logic_vector
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+ 0
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+
+
+
+
+ true
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+
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+
+
+ cfg_interrupt_pending
+
+ in
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+ 1
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+
+
+ std_logic_vector
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+ 0
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+
+
+ true
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+
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+
+
+ cfg_interrupt_sent
+
+ out
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+
+ std_logic
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+
+
+
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+
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+ true
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+
+
+
+ cfg_interrupt_msi_enable
+
+ out
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+ 1
+ 0
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+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
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+ optional
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+
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+
+
+ cfg_interrupt_msi_vf_enable
+
+ out
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+ 5
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
+
+
+
+ optional
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+
+
+
+
+
+ cfg_interrupt_msi_mmenable
+
+ out
+
+ 5
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
+
+
+
+
+ optional
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+
+
+
+
+
+ cfg_interrupt_msi_mask_update
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
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+
+
+
+
+
+ optional
+ true
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+
+
+
+
+ cfg_interrupt_msi_data
+
+ out
+
+ 31
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
+
+
+
+ optional
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+
+
+
+
+
+ cfg_interrupt_msi_select
+
+ in
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+ 3
+ 0
+
+
+
+ std_logic_vector
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+
+
+ 0
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+
+
+
+
+ optional
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+
+
+
+
+
+ cfg_interrupt_msi_int
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+ in
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+ 31
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
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+
+
+ 0
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+
+
+
+
+ optional
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+
+
+
+
+
+ cfg_interrupt_msi_pending_status
+
+ in
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+ 63
+ 0
+
+
+
+ std_logic_vector
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+
+
+ 0
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+
+
+
+
+ optional
+ true
+
+
+
+
+
+ cfg_interrupt_msi_sent
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+ out
+
+
+ std_logic
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+
+
+
+
+
+
+ optional
+ true
+
+
+
+
+
+ cfg_interrupt_msi_fail
+
+ out
+
+
+ std_logic
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+
+
+
+
+
+ optional
+ true
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+
+
+
+
+ cfg_interrupt_msix_enable
+
+ out
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+ 1
+ 0
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+
+
+ std_logic_vector
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+
+
+
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+ optional
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+
+
+
+
+
+ cfg_interrupt_msix_mask
+
+ out
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_interrupt_msix_vf_enable
+
+ out
+
+ 5
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_interrupt_msix_vf_mask
+
+ out
+
+ 5
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_interrupt_msix_data
+
+ in
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+ 31
+ 0
+
+
+
+ std_logic_vector
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+
+
+ 0
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+
+
+
+
+ optional
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+
+
+
+
+
+ cfg_interrupt_msix_address
+
+ in
+
+ 63
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
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+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_interrupt_msix_int
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_interrupt_msix_sent
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_interrupt_msix_fail
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_interrupt_msi_attr
+
+ in
+
+ 2
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
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+
+
+ 0
+
+
+
+
+
+ optional
+ true
+
+
+
+
+
+ cfg_interrupt_msi_tph_present
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
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+
+
+ 0
+
+
+
+
+
+ optional
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+
+
+
+
+
+ cfg_interrupt_msi_tph_type
+
+ in
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
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+
+
+ 0
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+
+
+
+
+ optional
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+
+
+
+
+ cfg_interrupt_msi_tph_st_tag
+
+ in
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+ 8
+ 0
+
+
+
+ std_logic_vector
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+
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+ 0
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+
+
+
+ optional
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+
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+
+
+ cfg_interrupt_msi_function_number
+
+ in
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+ 2
+ 0
+
+
+
+ std_logic_vector
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+ xilinx_verilogbehavioralsimulation
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+
+
+ 0
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+
+
+
+
+ optional
+ true
+
+
+
+
+
+ cfg_hot_reset_out
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
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+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_config_space_enable
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 1
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_req_pm_transition_l23_ready
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_hot_reset_in
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_ds_port_number
+
+ in
+
+ 7
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_ds_bus_number
+
+ in
+
+ 7
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_ds_device_number
+
+ in
+
+ 4
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cfg_ds_function_number
+
+ in
+
+ 2
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ user_tph_stt_address
+
+ in
+
+ 4
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ user_tph_function_num
+
+ in
+
+ 2
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
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+
+
+
+
+ optional
+ false
+
+
+
+
+
+ user_tph_stt_read_data
+
+ out
+
+ 31
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ user_tph_stt_read_data_valid
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ user_tph_stt_read_enable
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ sys_clk
+
+ in
+
+
+ wire
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ true
+
+
+
+
+
+ sys_reset
+
+ in
+
+
+ wire
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ true
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+
+
+
+
+ qpll_drp_crscode
+
+ in
+
+ 11
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ qpll_drp_fsm
+
+ in
+
+ 17
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ qpll_drp_done
+
+ in
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ qpll_drp_reset
+
+ in
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+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ qpll_qplllock
+
+ in
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+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ qpll_qplloutclk
+
+ in
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+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
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+
+
+
+
+ optional
+ false
+
+
+
+
+
+ qpll_qplloutrefclk
+
+ in
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+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ qpll_qplld
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+ out
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+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ qpll_qpllreset
+
+ out
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
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+
+
+ qpll_drp_clk
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+ out
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+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
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+
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+
+
+ qpll_drp_rst_n
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+ out
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+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
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+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ qpll_drp_ovrd
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
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+
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+ qpll_drp_gen3
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+ qpll_drp_start
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+ 2
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+ 0
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+ pipe_txprbsforceerr
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+ in
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+ 0
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+ pipe_rxprbscntreset
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+ 0
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+ pipe_loopback
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+ 0
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+ optional
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+ pipe_rxprbserr
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+ 0
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+ std_logic_vector
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+ pipe_rst_fsm
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+ pipe_qrst_fsm
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+ out
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+ std_logic_vector
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+ pipe_rate_fsm
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+ out
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+ 19
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+ std_logic_vector
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+ pipe_sync_fsm_tx
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+ out
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+ 23
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+ std_logic_vector
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+ pipe_sync_fsm_rx
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+ out
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+ optional
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+ pipe_drp_fsm
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+ out
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+ 27
+ 0
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+ std_logic_vector
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+ optional
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+ pipe_rst_idle
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+ out
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+ optional
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+ pipe_qrst_idle
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+ pipe_rate_idle
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+ out
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+ pipe_eyescandataerror
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+ out
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+ 3
+ 0
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+ std_logic_vector
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+ pipe_rxstatus
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+ out
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+ pipe_dmonitorout
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+ optional
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+ pipe_cpll_lock
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+ out
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+ 3
+ 0
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+ std_logic_vector
+ xilinx_verilogsynthesis
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+ optional
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+ pipe_qpll_lock
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+ out
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+ 0
+ 0
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+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+ optional
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+ pipe_rxpmaresetdone
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+ out
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+ 3
+ 0
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+ std_logic_vector
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+ optional
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+ pipe_rxbufstatus
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+ out
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+ 11
+ 0
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+ std_logic_vector
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+ optional
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+ pipe_txphaligndone
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+ out
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+ 3
+ 0
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+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+ optional
+ false
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+ pipe_txphinitdone
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+ out
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+ 3
+ 0
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+ std_logic_vector
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+ optional
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+
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+
+
+
+ pipe_txdlysresetdone
+
+ out
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+ 3
+ 0
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+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+ optional
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+ pipe_rxphaligndone
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+ out
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+ 3
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+ std_logic_vector
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+ optional
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+ pipe_rxdlysresetdone
+
+ out
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+ 3
+ 0
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+
+ std_logic_vector
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+ optional
+ false
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+ pipe_rxsyncdone
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+ out
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+ 3
+ 0
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+ std_logic_vector
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+ optional
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+ pipe_rxdisperr
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+ out
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+ 31
+ 0
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+ std_logic_vector
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+ optional
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+ pipe_rxnotintable
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+ out
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+ 31
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+ std_logic_vector
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+ optional
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+ pipe_rxcommadet
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+ 3
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+ std_logic_vector
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+ optional
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+ gt_ch_drp_rdy
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+ out
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+ 3
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+ std_logic_vector
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+ optional
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+ pipe_debug_0
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+ std_logic_vector
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+ optional
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+ std_logic_vector
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+ pipe_debug_2
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+ std_logic_vector
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+ optional
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+ ext_ch_gt_drpclk
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+ ext_ch_gt_drpaddr
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+ ext_ch_gt_drpdo
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+ icap_csib
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+ icap_rdwrb
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+ startup_eos_in
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+ 0
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+ startup_cfgclk
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+ startup_cfgmclk
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+ startup_keyclearb
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+ startup_usrcclko
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+ startup_usrcclkts
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+ startup_usrdoneo
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+ pcie_drp_clk
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+ pcie_drp_en
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+ pcie_drp_addr
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+ pcie_drp_di
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+ 0
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+ optional
+ false
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+
+
+
+
+ pcie_drp_do
+
+ out
+
+ 15
+ 0
+
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pcie_drp_rdy
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ common_commands_in
+
+ in
+
+ 25
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_rx_0_sigs
+
+ in
+
+ 83
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_rx_1_sigs
+
+ in
+
+ 83
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_rx_2_sigs
+
+ in
+
+ 83
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_rx_3_sigs
+
+ in
+
+ 83
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_rx_4_sigs
+
+ in
+
+ 83
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_rx_5_sigs
+
+ in
+
+ 83
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_rx_6_sigs
+
+ in
+
+ 83
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_rx_7_sigs
+
+ in
+
+ 83
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ common_commands_out
+
+ out
+
+ 16
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_tx_0_sigs
+
+ out
+
+ 69
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_tx_1_sigs
+
+ out
+
+ 69
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_tx_2_sigs
+
+ out
+
+ 69
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_tx_3_sigs
+
+ out
+
+ 69
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_tx_4_sigs
+
+ out
+
+ 69
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_tx_5_sigs
+
+ out
+
+ 69
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_tx_6_sigs
+
+ out
+
+ 69
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ pipe_tx_7_sigs
+
+ out
+
+ 69
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ cpllpd
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ txpd
+
+ in
+
+ 7
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ rxpd
+
+ in
+
+ 7
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ txpdelecidlemode
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ txdetectrx
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ txelecidle
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ qpllpd
+
+ in
+
+ 0
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ powerdown
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+
+
+ PL_LINK_CAP_MAX_LINK_SPEED
+ Pl Link Cap Max Link Speed
+ 4
+
+
+ PL_LINK_CAP_MAX_LINK_WIDTH
+ Pl Link Cap Max Link Width
+ 4
+
+
+ USER_CLK2_FREQ
+ User Clk2 Freq
+ 4
+
+
+ PF0_LINK_CAP_ASPM_SUPPORT
+ ASPM Support
+ 0
+
+
+ C_DATA_WIDTH
+ C Data Width
+ 128
+
+
+ REF_CLK_FREQ
+ Ref Clk Freq
+ 0
+
+
+ PCIE_LINK_SPEED
+ Pcie Link Speed
+ 3
+
+
+ KEEP_WIDTH
+ Keep Width
+ 4
+
+
+ ARI_CAP_ENABLE
+ Ari Cap Enable
+ FALSE
+
+
+ PF0_ARI_CAP_NEXT_FUNC
+ Pf0 ARI Cap Next Func
+ 0x00
+
+
+ AXISTEN_IF_CC_ALIGNMENT_MODE
+ Axisten If Cc Alignment Mode
+ FALSE
+
+
+ AXISTEN_IF_CQ_ALIGNMENT_MODE
+ Axisten If Cq Alignment Mode
+ FALSE
+
+
+ AXISTEN_IF_RC_ALIGNMENT_MODE
+ Axisten If Rc Alignment Mode
+ FALSE
+
+
+ AXISTEN_IF_RC_STRADDLE
+ Axisten If Rc Straddle
+ FALSE
+
+
+ AXISTEN_IF_RQ_ALIGNMENT_MODE
+ Axisten If Rq Alignment Mode
+ FALSE
+
+
+ PF0_AER_CAP_ECRC_CHECK_CAPABLE
+ Pf0 Aer Cap Ecrc Check Capable
+ FALSE
+
+
+ PF0_AER_CAP_ECRC_GEN_CAPABLE
+ Pf0 Aer Cap Ecrc Gen Capable
+ FALSE
+
+
+ PF0_AER_CAP_NEXTPTR
+ Pf0 Aer Cap Nextptr
+ 0x300
+
+
+ PF0_ARI_CAP_NEXTPTR
+ Pf0 Ari Cap Nextptr
+ 0x000
+
+
+ VF0_ARI_CAP_NEXTPTR
+ Vf0 Ari Cap Nextptr
+ 0x000
+
+
+ VF1_ARI_CAP_NEXTPTR
+ Vf1 Ari Cap Nextptr
+ 0x000
+
+
+ VF2_ARI_CAP_NEXTPTR
+ Vf2 Ari Cap Nextptr
+ 0x000
+
+
+ VF3_ARI_CAP_NEXTPTR
+ Vf3 Ari Cap Nextptr
+ 0x000
+
+
+ VF4_ARI_CAP_NEXTPTR
+ Vf4 Ari Cap Nextptr
+ 0x000
+
+
+ VF5_ARI_CAP_NEXTPTR
+ Vf5 Ari Cap Nextptr
+ 0x000
+
+
+ PF0_BAR0_APERTURE_SIZE
+ Pf0 Bar0 Aperture Size
+ 0b00011
+
+
+ PF0_BAR0_CONTROL
+ Pf0 Bar0 Control
+ 0b100
+
+
+ PF0_BAR1_APERTURE_SIZE
+ Pf0 Bar1 Aperture Size
+ 0b00000
+
+
+ PF0_BAR1_CONTROL
+ Pf0 Bar1 Control
+ 0b000
+
+
+ PF0_BAR2_APERTURE_SIZE
+ Pf0 Bar2 Aperture Size
+ 0b00000
+
+
+ PF0_BAR2_CONTROL
+ Pf0 Bar2 Control
+ 0b000
+
+
+ PF0_BAR3_APERTURE_SIZE
+ Pf0 Bar3 Aperture Size
+ 0b00000
+
+
+ PF0_BAR3_CONTROL
+ Pf0 Bar3 Control
+ 0b000
+
+
+ PF0_BAR4_APERTURE_SIZE
+ Pf0 Bar4 Aperture Size
+ 0b00000
+
+
+ PF0_BAR4_CONTROL
+ Pf0 Bar4 Control
+ 0b000
+
+
+ PF0_BAR5_APERTURE_SIZE
+ Pf0 Bar5 Aperture Size
+ 0b00000
+
+
+ PF0_BAR5_CONTROL
+ Pf0 Bar5 Control
+ 0b000
+
+
+ PF0_CAPABILITY_POINTER
+ Pf0 Capability Pointer
+ 0x80
+
+
+ PF0_CLASS_CODE
+ Pf0 Class Code
+ 0x058000
+
+
+ PF0_VENDOR_ID
+ Pf0 Vendor Id
+ 0x10EE
+
+
+ PF0_DEVICE_ID
+ Pf0 Device Id
+ 0x7034
+
+
+ PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT
+ Pf0 Dev Cap2 128b Cas Atomic Completer Support
+ FALSE
+
+
+ PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT
+ Pf0 Dev Cap2 32b Atomic Completer Support
+ FALSE
+
+
+ PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT
+ Pf0 Dev Cap2 64b Atomic Completer Support
+ FALSE
+
+
+ PF0_DEV_CAP2_LTR_SUPPORT
+ Pf0 Dev Cap2 Ltr Support
+ FALSE
+
+
+ PF0_DEV_CAP2_OBFF_SUPPORT
+ Pf0 Dev Cap2 Obff Support
+ 00
+
+
+ PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT
+ Pf0 Dev Cap2 Tph Completer Support
+ FALSE
+
+
+ PF0_DEV_CAP_EXT_TAG_SUPPORTED
+ Pf0 Dev Cap Ext Tag Supported
+ FALSE
+
+
+ PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE
+ Pf0 Dev Cap Function Level Reset Capable
+ FALSE
+
+
+ PF0_DEV_CAP_MAX_PAYLOAD_SIZE
+ Pf0 Dev Cap Max Payload Size
+ 0b010
+
+
+ PF0_DPA_CAP_NEXTPTR
+ Pf0 Dpa Cap Nextptr
+ 0x300
+
+
+ PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0
+ Pf0 DPA Cap Sub State Power Allocation0
+ 0x00
+
+
+ PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1
+ Pf0 DPA Cap Sub State Power Allocation1
+ 0x00
+
+
+ PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2
+ Pf0 DPA Cap Sub State Power Allocation2
+ 0x00
+
+
+ PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3
+ Pf0 DPA Cap Sub State Power Allocation3
+ 0x00
+
+
+ PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4
+ Pf0 DPA Cap Sub State Power Allocation4
+ 0x00
+
+
+ PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5
+ Pf0 DPA Cap Sub State Power Allocation5
+ 0x00
+
+
+ PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6
+ Pf0 DPA Cap Sub State Power Allocation6
+ 0x00
+
+
+ PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7
+ Pf0 DPA Cap Sub State Power Allocation7
+ 0x00
+
+
+ PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0
+ Pf1 DPA Cap Sub State Power Allocation0
+ 0x00
+
+
+ PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1
+ Pf1 DPA Cap Sub State Power Allocation1
+ 0x00
+
+
+ PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2
+ Pf1 DPA Cap Sub State Power Allocation2
+ 0x00
+
+
+ PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3
+ Pf1 DPA Cap Sub State Power Allocation3
+ 0x00
+
+
+ PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4
+ Pf1 DPA Cap Sub State Power Allocation4
+ 0x00
+
+
+ PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5
+ Pf1 DPA Cap Sub State Power Allocation5
+ 0x00
+
+
+ PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6
+ Pf1 DPA Cap Sub State Power Allocation6
+ 0x00
+
+
+ PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7
+ Pf1 DPA Cap Sub State Power Allocation7
+ 0x00
+
+
+ PF0_DSN_CAP_NEXTPTR
+ Pf0 Dsn Cap Nextptr
+ 0x300
+
+
+ PF0_EXPANSION_ROM_APERTURE_SIZE
+ Pf0 Expansion Rom Aperture Size
+ 0b00000
+
+
+ PF0_EXPANSION_ROM_ENABLE
+ Pf0 Expansion Rom Enable
+ FALSE
+
+
+ PF0_INTERRUPT_PIN
+ Pf0 Interrupt Pin
+ 0x0
+
+
+ PF0_LINK_STATUS_SLOT_CLOCK_CONFIG
+ Pf0 Link Status Slot Clock Config
+ FALSE
+
+
+ PF0_LTR_CAP_NEXTPTR
+ Pf0 Ltr Cap Nextptr
+ 0x300
+
+
+ PF0_MSIX_CAP_NEXTPTR
+ Pf0 Msix Cap Nextptr
+ 0x00
+
+
+ PF0_MSIX_CAP_PBA_BIR
+ Pf0 Msix Cap Pba Bir
+ 0
+
+
+ PF0_MSIX_CAP_PBA_OFFSET
+ Pf0 Msix Cap Pba Offset
+ 0x00000000
+
+
+ PF0_MSIX_CAP_TABLE_BIR
+ Pf0 Msix Cap Table Bir
+ 0
+
+
+ PF0_MSIX_CAP_TABLE_OFFSET
+ Pf0 Msix Cap Table Offset
+ 0x00000000
+
+
+ PF0_MSIX_CAP_TABLE_SIZE
+ Pf0 Msix Cap Table Size
+ 0x000
+
+
+ PF0_MSI_CAP_MULTIMSGCAP
+ Pf0 Msi Cap Multimsgcap
+ 0
+
+
+ PF0_MSI_CAP_NEXTPTR
+ Pf0 Msi Cap Nextptr
+ 0xC0
+
+
+ PF0_PB_CAP_NEXTPTR
+ Pf0 Pb Cap Nextptr
+ 0x274
+
+
+ PF0_PM_CAP_NEXTPTR
+ Pf0 Pm Cap Nextptr
+ 0x90
+
+
+ PF0_PM_CAP_PMESUPPORT_D0
+ Pf0 Pm Cap Pmesupport D0
+ FALSE
+
+
+ PF0_PM_CAP_PMESUPPORT_D1
+ Pf0 Pm Cap Pmesupport D1
+ FALSE
+
+
+ PF0_PM_CAP_PMESUPPORT_D3HOT
+ Pf0 Pm Cap Pmesupport D3hot
+ FALSE
+
+
+ PF0_PM_CAP_SUPP_D1_STATE
+ Pf0 Pm Cap Supp D1 State
+ FALSE
+
+
+ PF0_RBAR_CAP_ENABLE
+ Pf0 Rbar Cap Enable
+ FALSE
+
+
+ PF0_RBAR_CAP_NEXTPTR
+ Pf0 Rbar Cap Nextptr
+ 0x300
+
+
+ PF0_RBAR_CAP_SIZE0
+ Pf0 Rbar Cap Size0
+ 0x00000
+
+
+ PF0_RBAR_CAP_SIZE1
+ Pf0 Rbar Cap Size1
+ 0x00000
+
+
+ PF0_RBAR_CAP_SIZE2
+ Pf0 Rbar Cap Size2
+ 0x00000
+
+
+ PF1_RBAR_CAP_SIZE0
+ Pf1 Rbar Cap Size0
+ 0x00000
+
+
+ PF1_RBAR_CAP_SIZE1
+ Pf1 Rbar Cap Size1
+ 0x00000
+
+
+ PF1_RBAR_CAP_SIZE2
+ Pf1 Rbar Cap Size2
+ 0x00000
+
+
+ PF0_REVISION_ID
+ Pf0 Revision Id
+ 0x00
+
+
+ PF0_SRIOV_BAR0_APERTURE_SIZE
+ Pf0 Sriov Bar0 Aperture Size
+ 0b00000
+
+
+ PF0_SRIOV_BAR0_CONTROL
+ Pf0 Sriov Bar0 Control
+ 0b000
+
+
+ PF0_SRIOV_BAR1_APERTURE_SIZE
+ Pf0 Sriov Bar1 Aperture Size
+ 0b00000
+
+
+ PF0_SRIOV_BAR1_CONTROL
+ Pf0 Sriov Bar1 Control
+ 0b000
+
+
+ PF0_SRIOV_BAR2_APERTURE_SIZE
+ Pf0 Sriov Bar2 Aperture Size
+ 0b00000
+
+
+ PF0_SRIOV_BAR2_CONTROL
+ Pf0 Sriov Bar2 Control
+ 0b000
+
+
+ PF0_SRIOV_BAR3_APERTURE_SIZE
+ Pf0 Sriov Bar3 Aperture Size
+ 0b00000
+
+
+ PF0_SRIOV_BAR3_CONTROL
+ Pf0 Sriov Bar3 Control
+ 0b000
+
+
+ PF0_SRIOV_BAR4_APERTURE_SIZE
+ Pf0 Sriov Bar4 Aperture Size
+ 0b00000
+
+
+ PF0_SRIOV_BAR4_CONTROL
+ Pf0 Sriov Bar4 Control
+ 0b000
+
+
+ PF0_SRIOV_BAR5_APERTURE_SIZE
+ Pf0 Sriov Bar5 Aperture Size
+ 0b00000
+
+
+ PF0_SRIOV_BAR5_CONTROL
+ Pf0 Sriov Bar5 Control
+ 0b000
+
+
+ PF0_SRIOV_CAP_INITIAL_VF
+ Pf0 Sriov Cap Initial Vf
+ 0x0000
+
+
+ PF0_SRIOV_CAP_NEXTPTR
+ Pf0 Sriov Cap Nextptr
+ 0x300
+
+
+ PF0_SRIOV_CAP_TOTAL_VF
+ Pf0 Sriov Cap Total Vf
+ 0x0000
+
+
+ PF0_SRIOV_CAP_VER
+ Pf0 Sriov Cap Ver
+ 0x0
+
+
+ PF0_SRIOV_FIRST_VF_OFFSET
+ Pf0 Sriov First Vf Offset
+ 0x0000
+
+
+ PF0_SRIOV_FUNC_DEP_LINK
+ Pf0 Sriov Func Dep Link
+ 0x0000
+
+
+ PF0_SRIOV_SUPPORTED_PAGE_SIZE
+ Pf0 Sriov Supported Page Size
+ 0x00000553
+
+
+ PF0_SRIOV_VF_DEVICE_ID
+ Pf0 Sriov Vf Device Id
+ 0x0000
+
+
+ PF0_SUBSYSTEM_VENDOR_ID
+ Pf0 Subsystem Vendor Id
+ 0x10EE
+
+
+ PF0_SUBSYSTEM_ID
+ Pf0 Subsystem Id
+ 0x0007
+
+
+ PF0_TPHR_CAP_ENABLE
+ Pf0 Tphr Cap Enable
+ FALSE
+
+
+ PF0_TPHR_CAP_NEXTPTR
+ Pf0 Tphr Cap Nextptr
+ 0x300
+
+
+ VF0_TPHR_CAP_NEXTPTR
+ Vf0 Tphr Cap Nextptr
+ 0x000
+
+
+ VF1_TPHR_CAP_NEXTPTR
+ Vf1 Tphr Cap Nextptr
+ 0x000
+
+
+ VF2_TPHR_CAP_NEXTPTR
+ Vf2 Tphr Cap Nextptr
+ 0x000
+
+
+ VF3_TPHR_CAP_NEXTPTR
+ Vf3 Tphr Cap Nextptr
+ 0x000
+
+
+ VF4_TPHR_CAP_NEXTPTR
+ Vf4 Tphr Cap Nextptr
+ 0x000
+
+
+ VF5_TPHR_CAP_NEXTPTR
+ Vf5 Tphr Cap Nextptr
+ 0x000
+
+
+ PF0_TPHR_CAP_ST_MODE_SEL
+ Pf0 Tphr Cap St Mode Sel
+ 0x0
+
+
+ PF0_TPHR_CAP_ST_TABLE_LOC
+ Pf0 Tphr Cap St Table Loc
+ 0x0
+
+
+ PF0_TPHR_CAP_ST_TABLE_SIZE
+ Pf0 Tphr Cap St Table Size
+ 0x000
+
+
+ PF0_TPHR_CAP_VER
+ Pf0 Tphr Cap Ver
+ 0x1
+
+
+ PF1_TPHR_CAP_ST_MODE_SEL
+ Pf1 Tphr Cap St Mode Sel
+ 0x0
+
+
+ PF1_TPHR_CAP_ST_TABLE_LOC
+ Pf1 Tphr Cap St Table Loc
+ 0x0
+
+
+ PF1_TPHR_CAP_ST_TABLE_SIZE
+ Pf1 Tphr Cap St Table Size
+ 0x000
+
+
+ PF1_TPHR_CAP_VER
+ Pf1 Tphr Cap Ver
+ 0x1
+
+
+ VF0_TPHR_CAP_ST_MODE_SEL
+ Vf0 Tphr Cap St Mode Sel
+ 0x0
+
+
+ VF0_TPHR_CAP_ST_TABLE_LOC
+ Vf0 Tphr Cap St Table Loc
+ 0x0
+
+
+ VF0_TPHR_CAP_ST_TABLE_SIZE
+ Vf0 Tphr Cap St Table Size
+ 0x000
+
+
+ VF0_TPHR_CAP_VER
+ Vf0 Tphr Cap Ver
+ 0x1
+
+
+ VF1_TPHR_CAP_ST_MODE_SEL
+ Vf1 Tphr Cap St Mode Sel
+ 0x0
+
+
+ VF1_TPHR_CAP_ST_TABLE_LOC
+ Vf1 Tphr Cap St Table Loc
+ 0x0
+
+
+ VF1_TPHR_CAP_ST_TABLE_SIZE
+ Vf1 Tphr Cap St Table Size
+ 0x000
+
+
+ VF1_TPHR_CAP_VER
+ Vf1 Tphr Cap Ver
+ 0x1
+
+
+ VF2_TPHR_CAP_ST_MODE_SEL
+ Vf2 Tphr Cap St Mode Sel
+ 0x0
+
+
+ VF2_TPHR_CAP_ST_TABLE_LOC
+ Vf2 Tphr Cap St Table Loc
+ 0x0
+
+
+ VF2_TPHR_CAP_ST_TABLE_SIZE
+ Vf2 Tphr Cap St Table Size
+ 0x000
+
+
+ VF2_TPHR_CAP_VER
+ Vf2 Tphr Cap Ver
+ 0x1
+
+
+ VF3_TPHR_CAP_ST_MODE_SEL
+ Vf3 Tphr Cap St Mode Sel
+ 0x0
+
+
+ VF3_TPHR_CAP_ST_TABLE_LOC
+ Vf3 Tphr Cap St Table Loc
+ 0x0
+
+
+ VF3_TPHR_CAP_ST_TABLE_SIZE
+ Vf3 Tphr Cap St Table Size
+ 0x000
+
+
+ VF3_TPHR_CAP_VER
+ Vf3 Tphr Cap Ver
+ 0x1
+
+
+ VF4_TPHR_CAP_ST_MODE_SEL
+ Vf4 Tphr Cap St Mode Sel
+ 0x0
+
+
+ VF4_TPHR_CAP_ST_TABLE_LOC
+ Vf4 Tphr Cap St Table Loc
+ 0x0
+
+
+ VF4_TPHR_CAP_ST_TABLE_SIZE
+ Vf4 Tphr Cap St Table Size
+ 0x000
+
+
+ VF4_TPHR_CAP_VER
+ Vf4 Tphr Cap Ver
+ 0x1
+
+
+ VF5_TPHR_CAP_ST_MODE_SEL
+ Vf5 Tphr Cap St Mode Sel
+ 0x0
+
+
+ VF5_TPHR_CAP_ST_TABLE_LOC
+ Vf5 Tphr Cap St Table Loc
+ 0x0
+
+
+ VF5_TPHR_CAP_ST_TABLE_SIZE
+ Vf5 Tphr Cap St Table Size
+ 0x000
+
+
+ VF5_TPHR_CAP_VER
+ Vf5 Tphr Cap Ver
+ 0x1
+
+
+ PF0_TPHR_CAP_DEV_SPECIFIC_MODE
+ Pf0 Tphr Cap Dev Specific Mode
+ TRUE
+
+
+ PF0_TPHR_CAP_INT_VEC_MODE
+ Pf0 Tphr Cap Int Vec Mode
+ FALSE
+
+
+ PF1_TPHR_CAP_DEV_SPECIFIC_MODE
+ Pf1 Tphr Cap Dev Specific Mode
+ TRUE
+
+
+ PF1_TPHR_CAP_INT_VEC_MODE
+ Pf1 Tphr Cap Int Vec Mode
+ FALSE
+
+
+ VF0_TPHR_CAP_DEV_SPECIFIC_MODE
+ Vf0 Tphr Cap Dev Specific Mode
+ TRUE
+
+
+ VF0_TPHR_CAP_INT_VEC_MODE
+ Vf0 Tphr Cap Int Vec Mode
+ FALSE
+
+
+ VF1_TPHR_CAP_DEV_SPECIFIC_MODE
+ Vf1 Tphr Cap Dev Specific Mode
+ TRUE
+
+
+ VF1_TPHR_CAP_INT_VEC_MODE
+ Vf1 Tphr Cap Int Vec Mode
+ FALSE
+
+
+ VF2_TPHR_CAP_DEV_SPECIFIC_MODE
+ Vf2 Tphr Cap Dev Specific Mode
+ TRUE
+
+
+ VF2_TPHR_CAP_INT_VEC_MODE
+ Vf2 Tphr Cap Int Vec Mode
+ FALSE
+
+
+ VF3_TPHR_CAP_DEV_SPECIFIC_MODE
+ Vf3 Tphr Cap Dev Specific Mode
+ TRUE
+
+
+ VF3_TPHR_CAP_INT_VEC_MODE
+ Vf3 Tphr Cap Int Vec Mode
+ FALSE
+
+
+ VF4_TPHR_CAP_DEV_SPECIFIC_MODE
+ Vf4 Tphr Cap Dev Specific Mode
+ TRUE
+
+
+ VF4_TPHR_CAP_INT_VEC_MODE
+ Vf4 Tphr Cap Int Vec Mode
+ FALSE
+
+
+ VF5_TPHR_CAP_DEV_SPECIFIC_MODE
+ Vf5 Tphr Cap Dev Specific Mode
+ TRUE
+
+
+ VF5_TPHR_CAP_INT_VEC_MODE
+ Vf5 Tphr Cap Int Vec Mode
+ FALSE
+
+
+ PF0_VC_CAP_NEXTPTR
+ Pf0 Vc Cap Nextptr
+ 0x000
+
+
+ SPARE_WORD1
+ Secondary Pcie Extended Capability Nextptr
+ 0x00000000
+
+
+ PF1_AER_CAP_ECRC_CHECK_CAPABLE
+ Pf1 Aer Cap Ecrc Check Capable
+ FALSE
+
+
+ PF1_AER_CAP_ECRC_GEN_CAPABLE
+ Pf1 Aer Cap Ecrc Gen Capable
+ FALSE
+
+
+ PF1_AER_CAP_NEXTPTR
+ Pf1 Aer Cap Nextptr
+ 0x000
+
+
+ PF1_ARI_CAP_NEXTPTR
+ Pf1 Ari Cap Nextptr
+ 0x000
+
+
+ PF1_BAR0_APERTURE_SIZE
+ Pf1 Bar0 Aperture Size
+ 0b00000
+
+
+ PF1_BAR0_CONTROL
+ Pf1 Bar0 Control
+ 0b000
+
+
+ PF1_BAR1_APERTURE_SIZE
+ Pf1 Bar1 Aperture Size
+ 0b00000
+
+
+ PF1_BAR1_CONTROL
+ Pf1 Bar1 Control
+ 0b000
+
+
+ PF1_BAR2_APERTURE_SIZE
+ Pf1 Bar2 Aperture Size
+ 0b00000
+
+
+ PF1_BAR2_CONTROL
+ Pf1 Bar2 Control
+ 0b000
+
+
+ PF1_BAR3_APERTURE_SIZE
+ Pf1 Bar3 Aperture Size
+ 0b00000
+
+
+ PF1_BAR3_CONTROL
+ Pf1 Bar3 Control
+ 0b000
+
+
+ PF1_BAR4_APERTURE_SIZE
+ Pf1 Bar4 Aperture Size
+ 0b00000
+
+
+ PF1_BAR4_CONTROL
+ Pf1 Bar4 Control
+ 0b000
+
+
+ PF1_BAR5_APERTURE_SIZE
+ Pf1 Bar5 Aperture Size
+ 0b00000
+
+
+ PF1_BAR5_CONTROL
+ Pf1 Bar5 Control
+ 0b000
+
+
+ PF1_CAPABILITY_POINTER
+ Pf1 Capability Pointer
+ 0x80
+
+
+ PF1_CLASS_CODE
+ Pf1 Class Code
+ 0x058000
+
+
+ PF1_DEVICE_ID
+ Pf1 Device Id
+ 0x7011
+
+
+ PF1_DEV_CAP_MAX_PAYLOAD_SIZE
+ Pf1 Dev Cap Max Payload Size
+ 0b010
+
+
+ PF1_DPA_CAP_NEXTPTR
+ Pf1 Dpa Cap Nextptr
+ 0x000
+
+
+ PF1_DSN_CAP_NEXTPTR
+ Pf1 Dsn Cap Nextptr
+ 0x000
+
+
+ PF1_EXPANSION_ROM_APERTURE_SIZE
+ Pf1 Expansion Rom Aperture Size
+ 0b00000
+
+
+ PF1_EXPANSION_ROM_ENABLE
+ Pf1 Expansion Rom Enable
+ FALSE
+
+
+ PF1_INTERRUPT_PIN
+ Pf1 Interrupt Pin
+ 0x0
+
+
+ PF1_MSIX_CAP_NEXTPTR
+ Pf1 Msix Cap Nextptr
+ 0x00
+
+
+ PF1_MSIX_CAP_PBA_BIR
+ Pf1 Msix Cap Pba Bir
+ 0
+
+
+ PF1_MSIX_CAP_PBA_OFFSET
+ Pf1 Msix Cap Pba Offset
+ 0x00000000
+
+
+ PF1_MSIX_CAP_TABLE_BIR
+ Pf1 Msix Cap Table Bir
+ 0
+
+
+ PF1_MSIX_CAP_TABLE_OFFSET
+ Pf1 Msix Cap Table Offset
+ 0x00000000
+
+
+ PF1_MSIX_CAP_TABLE_SIZE
+ Pf1 Msix Cap Table Size
+ 0x000
+
+
+ PF1_MSI_CAP_MULTIMSGCAP
+ Pf1 Msi Cap Multimsgcap
+ 0
+
+
+ PF1_MSI_CAP_NEXTPTR
+ Pf1 Msi Cap Nextptr
+ 0x00
+
+
+ PF1_PB_CAP_NEXTPTR
+ Pf1 Pb Cap Nextptr
+ 0x000
+
+
+ PF1_PM_CAP_NEXTPTR
+ Pf1 Pm Cap Nextptr
+ 0x00
+
+
+ PF1_RBAR_CAP_ENABLE
+ Pf1 Rbar Cap Enable
+ FALSE
+
+
+ PF1_RBAR_CAP_NEXTPTR
+ Pf1 Rbar Cap Nextptr
+ 0x000
+
+
+ PF1_REVISION_ID
+ Pf1 Revision Id
+ 0x00
+
+
+ PF1_SRIOV_BAR0_APERTURE_SIZE
+ Pf1 Sriov Bar0 Aperture Size
+ 0b00000
+
+
+ PF1_SRIOV_BAR0_CONTROL
+ Pf1 Sriov Bar0 Control
+ 0b000
+
+
+ PF1_SRIOV_BAR1_APERTURE_SIZE
+ Pf1 Sriov Bar1 Aperture Size
+ 0b00000
+
+
+ PF1_SRIOV_BAR1_CONTROL
+ Pf1 Sriov Bar1 Control
+ 0b000
+
+
+ PF1_SRIOV_BAR2_APERTURE_SIZE
+ Pf1 Sriov Bar2 Aperture Size
+ 0b00000
+
+
+ PF1_SRIOV_BAR2_CONTROL
+ Pf1 Sriov Bar2 Control
+ 0b000
+
+
+ PF1_SRIOV_BAR3_APERTURE_SIZE
+ Pf1 Sriov Bar3 Aperture Size
+ 0b00000
+
+
+ PF1_SRIOV_BAR3_CONTROL
+ Pf1 Sriov Bar3 Control
+ 0b000
+
+
+ PF1_SRIOV_BAR4_APERTURE_SIZE
+ Pf1 Sriov Bar4 Aperture Size
+ 0b00000
+
+
+ PF1_SRIOV_BAR4_CONTROL
+ Pf1 Sriov Bar4 Control
+ 0b000
+
+
+ PF1_SRIOV_BAR5_APERTURE_SIZE
+ Pf1 Sriov Bar5 Aperture Size
+ 0b00000
+
+
+ PF1_SRIOV_BAR5_CONTROL
+ Pf1 Sriov Bar5 Control
+ 0b000
+
+
+ PF1_SRIOV_CAP_INITIAL_VF
+ Pf1 Sriov Cap Initial Vf
+ 0x0000
+
+
+ PF1_SRIOV_CAP_NEXTPTR
+ Pf1 Sriov Cap Nextptr
+ 0x000
+
+
+ PF1_SRIOV_CAP_TOTAL_VF
+ Pf1 Sriov Cap Total Vf
+ 0x0000
+
+
+ PF1_SRIOV_CAP_VER
+ Pf1 Sriov Cap Ver
+ 0x0
+
+
+ PF1_SRIOV_FIRST_VF_OFFSET
+ Pf1 Sriov First Vf Offset
+ 0x0000
+
+
+ PF1_SRIOV_FUNC_DEP_LINK
+ Pf1 Sriov Func Dep Link
+ 0x0001
+
+
+ PF1_SRIOV_SUPPORTED_PAGE_SIZE
+ Pf1 Sriov Supported Page Size
+ 0x00000553
+
+
+ PF1_SRIOV_VF_DEVICE_ID
+ Pf1 Sriov Vf Device Id
+ 0x0000
+
+
+ PF1_SUBSYSTEM_ID
+ Pf1 Subsystem Id
+ 0x0007
+
+
+ PF1_TPHR_CAP_ENABLE
+ Pf1 Tphr Cap Enable
+ FALSE
+
+
+ PF1_TPHR_CAP_NEXTPTR
+ Pf1 Tphr Cap Nextptr
+ 0x000
+
+
+ PL_UPSTREAM_FACING
+ Pl Upstream Facing
+ TRUE
+
+
+ SRIOV_CAP_ENABLE
+ Sriov Cap Enable
+ FALSE
+
+
+ TL_CREDITS_CD
+ Tl Credits Cd
+ 0x000
+
+
+ TL_CREDITS_CH
+ Tl Credits Ch
+ 0x00000000
+
+
+ TL_CREDITS_NPD
+ Tl Credits Npd
+ 0x028
+
+
+ TL_CREDITS_NPH
+ Tl Credits Nph
+ 0x20
+
+
+ TL_CREDITS_PD
+ Tl Credits Pd
+ 0x198
+
+
+ TL_CREDITS_PH
+ Tl Credits Ph
+ 0x20
+
+
+ TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE
+ Tl Extended Cfg Extend Interface Enable
+ FALSE
+
+
+ TL_LEGACY_MODE_ENABLE
+ Tl Legacy Mode Enable
+ FALSE
+
+
+ TL_PF_ENABLE_REG
+ Tl Pf Enable Reg
+ FALSE
+
+
+ VF0_CAPABILITY_POINTER
+ Vf0 Capability Pointer
+ 0x80
+
+
+ VF0_MSIX_CAP_PBA_BIR
+ Vf0 Msix Cap Pba Bir
+ 0
+
+
+ VF0_MSIX_CAP_PBA_OFFSET
+ Vf0 Msix Cap Pba Offset
+ 0x00000000
+
+
+ VF0_MSIX_CAP_TABLE_BIR
+ Vf0 Msix Cap Table Bir
+ 0
+
+
+ VF0_MSIX_CAP_TABLE_OFFSET
+ Vf0 Msix Cap Table Offset
+ 0x00000000
+
+
+ VF0_MSIX_CAP_TABLE_SIZE
+ Vf0 Msix Cap Table Size
+ 0x000
+
+
+ VF0_MSI_CAP_MULTIMSGCAP
+ Vf0 Msi Cap Multimsgcap
+ 0
+
+
+ VF0_PM_CAP_NEXTPTR
+ Vf0 Pm Cap Nextptr
+ "00000000"
+
+
+ VF1_MSIX_CAP_PBA_BIR
+ Vf1 Msix Cap Pba Bir
+ 0
+
+
+ VF1_MSIX_CAP_PBA_OFFSET
+ Vf1 Msix Cap Pba Offset
+ 0x00000000
+
+
+ VF1_MSIX_CAP_TABLE_BIR
+ Vf1 Msix Cap Table Bir
+ 0
+
+
+ VF1_MSIX_CAP_TABLE_OFFSET
+ Vf1 Msix Cap Table Offset
+ 0x00000000
+
+
+ VF1_MSIX_CAP_TABLE_SIZE
+ Vf1 Msix Cap Table Size
+ 0x000
+
+
+ VF1_MSI_CAP_MULTIMSGCAP
+ Vf1 Msi Cap Multimsgcap
+ 0
+
+
+ VF1_PM_CAP_NEXTPTR
+ Vf1 Pm Cap Nextptr
+ "00000000"
+
+
+ VF2_MSIX_CAP_PBA_BIR
+ Vf2 Msix Cap Pba Bir
+ 0
+
+
+ VF2_MSIX_CAP_PBA_OFFSET
+ Vf2 Msix Cap Pba Offset
+ 0x00000000
+
+
+ VF2_MSIX_CAP_TABLE_BIR
+ Vf2 Msix Cap Table Bir
+ 0
+
+
+ VF2_MSIX_CAP_TABLE_OFFSET
+ Vf2 Msix Cap Table Offset
+ 0x00000000
+
+
+ VF2_MSIX_CAP_TABLE_SIZE
+ Vf2 Msix Cap Table Size
+ 0x000
+
+
+ VF2_MSI_CAP_MULTIMSGCAP
+ Vf2 Msi Cap Multimsgcap
+ 0
+
+
+ VF2_PM_CAP_NEXTPTR
+ Vf2 Pm Cap Nextptr
+ "00000000"
+
+
+ VF3_MSIX_CAP_PBA_BIR
+ Vf3 Msix Cap Pba Bir
+ 0
+
+
+ VF3_MSIX_CAP_PBA_OFFSET
+ Vf3 Msix Cap Pba Offset
+ 0x00000000
+
+
+ VF3_MSIX_CAP_TABLE_BIR
+ Vf3 Msix Cap Table Bir
+ 0
+
+
+ VF3_MSIX_CAP_TABLE_OFFSET
+ Vf3 Msix Cap Table Offset
+ 0x00000000
+
+
+ VF3_MSIX_CAP_TABLE_SIZE
+ Vf3 Msix Cap Table Size
+ 0x000
+
+
+ VF3_MSI_CAP_MULTIMSGCAP
+ Vf3 Msi Cap Multimsgcap
+ 0
+
+
+ VF3_PM_CAP_NEXTPTR
+ Vf3 Pm Cap Nextptr
+ "00000000"
+
+
+ VF4_MSIX_CAP_PBA_BIR
+ Vf4 Msix Cap Pba Bir
+ 0
+
+
+ VF4_MSIX_CAP_PBA_OFFSET
+ Vf4 Msix Cap Pba Offset
+ 0x00000000
+
+
+ VF4_MSIX_CAP_TABLE_BIR
+ Vf4 Msix Cap Table Bir
+ 0
+
+
+ VF4_MSIX_CAP_TABLE_OFFSET
+ Vf4 Msix Cap Table Offset
+ 0x00000000
+
+
+ VF4_MSIX_CAP_TABLE_SIZE
+ Vf4 Msix Cap Table Size
+ 0x000
+
+
+ VF4_MSI_CAP_MULTIMSGCAP
+ Vf4 Msi Cap Multimsgcap
+ 0
+
+
+ VF4_PM_CAP_NEXTPTR
+ Vf4 Pm Cap Nextptr
+ "00000000"
+
+
+ VF5_MSIX_CAP_PBA_BIR
+ Vf5 Msix Cap Pba Bir
+ 0
+
+
+ VF5_MSIX_CAP_PBA_OFFSET
+ Vf5 Msix Cap Pba Offset
+ 0x00000000
+
+
+ VF5_MSIX_CAP_TABLE_BIR
+ Vf5 Msix Cap Table Bir
+ 0
+
+
+ VF5_MSIX_CAP_TABLE_OFFSET
+ Vf5 Msix Cap Table Offset
+ 0x00000000
+
+
+ VF5_MSIX_CAP_TABLE_SIZE
+ Vf5 Msix Cap Table Size
+ 0x000
+
+
+ VF5_MSI_CAP_MULTIMSGCAP
+ Vf5 Msi Cap Multimsgcap
+ 0
+
+
+ VF5_PM_CAP_NEXTPTR
+ Vf5 Pm Cap Nextptr
+ "00000000"
+
+
+ COMPLETION_SPACE
+ Completion Space
+ 16KB
+
+
+ gen_x0y0_ucf
+ Generate X0Y0 UCF
+ 0
+
+
+ gen_x0y3_ucf
+ Generate X0Y3 UCF
+ 0
+
+
+ gen_x0y2_ucf
+ Generate X0Y2 UCF
+ 1
+
+
+ gen_x0y1_ucf
+ Generate X0Y1 UCF
+ 0
+
+
+ silicon_revision
+ Silicon Revision
+ Production
+
+
+ xlnx_ref_board
+ Xlnx Ref Board
+ 0
+
+
+ pcie_blk_locn
+ Pcie Blk Locn
+ 2
+
+
+ SHARED_LOGIC_IN_CORE
+ FALSE
+
+
+ PIPE_SIM
+ FALSE
+
+
+ MSI_EN
+ TRUE
+
+
+ MSIX_EN
+ FALSE
+
+
+ PCIE_EXT_CLK
+ FALSE
+
+
+ PCIE_EXT_GT_COMMON
+ FALSE
+
+
+ EXT_CH_GT_DRP
+ FALSE
+
+
+ CFG_STATUS_IF
+ TRUE
+
+
+ TX_FC_IF
+ FALSE
+
+
+ CFG_EXT_IF
+ FALSE
+
+
+ CFG_FC_IF
+ TRUE
+
+
+ PER_FUNC_STATUS_IF
+ FALSE
+
+
+ CFG_MGMT_IF
+ FALSE
+
+
+ RCV_MSG_IF
+ FALSE
+
+
+ CFG_TX_MSG_IF
+ FALSE
+
+
+ CFG_CTL_IF
+ FALSE
+
+
+ PCIE_DRP
+ FALSE
+
+
+ TRANSCEIVER_CTRL_STATUS_PORTS
+ FALSE
+
+
+ AXISTEN_IF_ENABLE_CLIENT_TAG
+ TRUE
+
+
+ PCIE_USE_MODE
+ PCIE USE MODE
+ 2.1
+
+
+ PCIE_FAST_CONFIG
+ PCIE FAST CONFIG
+ NONE
+
+
+ EXT_STARTUP_PRIMITIVE
+ EXT STARTUP PRIMITIVE
+ FALSE
+
+
+ EXT_PIPE_INTERFACE
+ EXT PIPE INTERFACE
+ FALSE
+
+
+ AXISTEN_IF_ENABLE_MSG_ROUTE
+ 0x00000
+
+
+ AXISTEN_IF_ENABLE_RX_MSG_INTFC
+ FALSE
+
+
+ POWER_DOWN
+ FALSE
+
+
+
+
+
+ choices_0
+ PCI_Express_Endpoint_device
+ Legacy_PCI_Express_Endpoint_device
+ Root_Port_of_PCI_Express_Root_Complex
+
+
+ choices_1
+ None
+ VC709
+
+
+ choices_2
+ 2.5_GT/s
+ 5.0_GT/s
+ 8.0_GT/s
+
+
+ choices_3
+ X1
+ X2
+ X4
+ X8
+
+
+ choices_4
+ 100_MHz
+ 125_MHz
+ 250_MHz
+
+
+ choices_5
+ true
+ false
+
+
+ choices_6
+ true
+ false
+
+
+ choices_7
+ true
+ false
+
+
+ choices_8
+ true
+ false
+
+
+ choices_9
+ true
+ false
+
+
+ choices_10
+ true
+ false
+
+
+ choices_11
+ true
+ false
+
+
+ choices_12
+ 00_Not_Supported
+ 01_MSI_only
+
+
+ choices_13
+ true
+ false
+
+
+ choices_14
+ true
+ false
+
+
+ choices_15
+ NONE
+ INTA
+ INTB
+ INTC
+ INTD
+
+
+ choices_16
+ true
+ false
+
+
+ choices_17
+ BAR_0
+
+
+ choices_18
+ BAR_0
+ 0
+ BAR_1
+ 1
+ BAR_2
+ 2
+ BAR_3
+ 3
+ BAR_4
+ 4
+ BAR_5
+
+
+ choices_19
+ 1_vector
+ 2_vectors
+ 4_vectors
+ 8_vectors
+ 16_vectors
+ 32_vectors
+
+
+ choices_20
+ true
+ false
+
+
+ choices_21
+ true
+ false
+
+
+ choices_22
+ true
+ false
+
+
+ choices_23
+ 0
+ 1
+ 2
+ 3
+ 4
+ 5
+ 6
+
+
+ choices_24
+ true
+ false
+
+
+ choices_25
+ true
+ false
+
+
+ choices_26
+ NONE
+ INTA
+ INTB
+ INTC
+ INTD
+
+
+ choices_27
+ BAR_0
+
+
+ choices_28
+ BAR_0
+ 0
+ BAR_1
+ 1
+ BAR_2
+ 2
+ BAR_3
+ 3
+ BAR_4
+ 4
+ BAR_5
+
+
+ choices_29
+ 1_vector
+ 2_vectors
+ 4_vectors
+ 8_vectors
+ 16_vectors
+ 32_vectors
+
+
+ choices_30
+ 0
+
+
+ choices_31
+ true
+ false
+
+
+ choices_32
+ true
+ false
+
+
+ choices_33
+ true
+ false
+
+
+ choices_34
+ BAR_0
+ 0
+ BAR_1
+ 1
+ BAR_2
+ 2
+ BAR_3
+ 3
+ BAR_4
+ 4
+ BAR_5
+
+
+ choices_35
+ BAR_0
+ 0
+ BAR_1
+ 1
+ BAR_2
+ 2
+ BAR_3
+ 3
+ BAR_4
+ 4
+ BAR_5
+
+
+ choices_36
+ 1_vector
+ 2_vectors
+ 4_vectors
+ 8_vectors
+ 16_vectors
+ 32_vectors
+
+
+ choices_37
+ BAR_0
+ 0
+ BAR_1
+ 1
+ BAR_2
+ 2
+ BAR_3
+ 3
+ BAR_4
+ 4
+ BAR_5
+
+
+ choices_38
+ BAR_0
+ 0
+ BAR_1
+ 1
+ BAR_2
+ 2
+ BAR_3
+ 3
+ BAR_4
+ 4
+ BAR_5
+
+
+ choices_39
+ 1_vector
+ 2_vectors
+ 4_vectors
+ 8_vectors
+ 16_vectors
+ 32_vectors
+
+
+ choices_40
+ BAR_0
+ 0
+ BAR_1
+ 1
+ BAR_2
+ 2
+ BAR_3
+ 3
+ BAR_4
+ 4
+ BAR_5
+
+
+ choices_41
+ BAR_0
+ 0
+ BAR_1
+ 1
+ BAR_2
+ 2
+ BAR_3
+ 3
+ BAR_4
+ 4
+ BAR_5
+
+
+ choices_42
+ 1_vector
+ 2_vectors
+ 4_vectors
+ 8_vectors
+ 16_vectors
+ 32_vectors
+
+
+ choices_43
+ BAR_0
+ 0
+ BAR_1
+ 1
+ BAR_2
+ 2
+ BAR_3
+ 3
+ BAR_4
+ 4
+ BAR_5
+
+
+ choices_44
+ BAR_0
+ 0
+ BAR_1
+ 1
+ BAR_2
+ 2
+ BAR_3
+ 3
+ BAR_4
+ 4
+ BAR_5
+
+
+ choices_45
+ 1_vector
+ 2_vectors
+ 4_vectors
+ 8_vectors
+ 16_vectors
+ 32_vectors
+
+
+ choices_46
+ BAR_0
+ 0
+ BAR_1
+ 1
+ BAR_2
+ 2
+ BAR_3
+ 3
+ BAR_4
+ 4
+ BAR_5
+
+
+ choices_47
+ BAR_0
+ 0
+ BAR_1
+ 1
+ BAR_2
+ 2
+ BAR_3
+ 3
+ BAR_4
+ 4
+ BAR_5
+
+
+ choices_48
+ 1_vector
+ 2_vectors
+ 4_vectors
+ 8_vectors
+ 16_vectors
+ 32_vectors
+
+
+ choices_49
+ BAR_0
+ 0
+ BAR_1
+ 1
+ BAR_2
+ 2
+ BAR_3
+ 3
+ BAR_4
+ 4
+ BAR_5
+
+
+ choices_50
+ BAR_0
+ 0
+ BAR_1
+ 1
+ BAR_2
+ 2
+ BAR_3
+ 3
+ BAR_4
+ 4
+ BAR_5
+
+
+ choices_51
+ 1_vector
+ 2_vectors
+ 4_vectors
+ 8_vectors
+ 16_vectors
+ 32_vectors
+
+
+ choices_52
+ true
+ false
+
+
+ choices_53
+ true
+ false
+
+
+ choices_54
+ true
+ false
+
+
+ choices_55
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_56
+ N/A
+
+
+ choices_57
+ true
+ false
+
+
+ choices_58
+ N/A
+
+
+ choices_59
+ true
+ false
+
+
+ choices_60
+ true
+ false
+
+
+ choices_61
+ X0Y1
+ X0Y2
+
+
+ choices_62
+ true
+ false
+
+
+ choices_63
+ true
+ false
+
+
+ choices_64
+ true
+ false
+
+
+ choices_65
+ true
+ false
+
+
+ choices_66
+ N/A
+
+
+ choices_67
+ true
+ false
+
+
+ choices_68
+ N/A
+
+
+ choices_69
+ true
+ false
+
+
+ choices_70
+ true
+ false
+
+
+ choices_71
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_72
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_73
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_74
+ N/A
+
+
+ choices_75
+ Wireless_controller
+ Satellite_communication_controllers
+ Data_acquisition_and_signal_processing_controllers
+ Intelligent_I/O_controllers
+ Docking_stations
+ Device_was_built_before_Class_Code_definitions_were_finalized
+ Memory_controller
+ Simple_communication_controllers
+ Serial_bus_controllers
+ Encryption/Decryption_controllers
+ Display_controller
+ Multimedia_device
+ Input_devices
+ Mass_storage_controller
+ Processors
+ Device_does_not_fit_in_any_defined_classes
+ Bridge_device
+ Network_controller
+ Base_system_peripherals
+
+
+ choices_76
+ Generic_XT_compatible_serial_controller
+ 16450_compatible_serial_controller
+ Parallel_port
+ IEEE_1284_controller
+ Multiport_serial_controller
+ 16650_compatible_serial_controller
+ IEEE_1284_target_device
+ Hayes_compatible_modem_with_16550_compatible_interface
+ ECP_1.X_compliant_parallel_port
+ 16850_compatible_serial_controller
+ Hayes_compatible_modem_with_16750_compatible_interface
+ Smard_Card
+ Bi_directional_parallel_port
+ Other_communications_device
+ GPIB(IEEE_488.1/2)_controller
+ 16550_compatible_serial_controller
+ Hayes_compatible_modem_with_16450_compatible_interface
+ 16750_compatible_serial_controller
+ Hayes_compatible_modem_with_16650_compatible_interface
+ Generic_modem
+ 16950_compatible_serial_controller
+
+
+ choices_77
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_78
+ true
+ false
+
+
+ choices_79
+ true
+ false
+
+
+ choices_80
+ true
+ false
+
+
+ choices_81
+ N/A
+
+
+ choices_82
+ true
+ false
+
+
+ choices_83
+ true
+ false
+
+
+ choices_84
+ true
+ false
+
+
+ choices_85
+ true
+ false
+
+
+ choices_86
+ true
+ false
+
+
+ choices_87
+ true
+ false
+
+
+ choices_88
+ true
+ false
+
+
+ choices_89
+ true
+ false
+
+
+ choices_90
+ true
+ false
+
+
+ choices_91
+ true
+ false
+
+
+ choices_92
+ true
+ false
+
+
+ choices_93
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_94
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_95
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_96
+ true
+ false
+
+
+ choices_97
+ DWORD_Aligned
+ Address_Aligned
+
+
+ choices_98
+ true
+ false
+
+
+ choices_99
+ Production
+
+
+ choices_100
+ true
+ false
+
+
+ choices_101
+ true
+ false
+
+
+ choices_102
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_103
+ true
+ false
+
+
+ choices_104
+ true
+ false
+
+
+ choices_105
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_106
+ true
+ false
+
+
+ choices_107
+ Memory
+
+
+ choices_108
+ true
+ false
+
+
+ choices_109
+ true
+ false
+
+
+ choices_110
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_111
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_112
+ true
+ false
+
+
+ choices_113
+ N/A
+
+
+ choices_114
+ true
+ false
+
+
+ choices_115
+ true
+ false
+
+
+ choices_116
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_117
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_118
+ true
+ false
+
+
+ choices_119
+ N/A
+
+
+ choices_120
+ true
+ false
+
+
+ choices_121
+ true
+ false
+
+
+ choices_122
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_123
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_124
+ true
+ false
+
+
+ choices_125
+ N/A
+
+
+ choices_126
+ true
+ false
+
+
+ choices_127
+ true
+ false
+
+
+ choices_128
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_129
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_130
+ true
+ false
+
+
+ choices_131
+ N/A
+
+
+ choices_132
+ true
+ false
+
+
+ choices_133
+ true
+ false
+
+
+ choices_134
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_135
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_136
+ true
+ false
+
+
+ choices_137
+ N/A
+
+
+ choices_138
+ true
+ false
+
+
+ choices_139
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_140
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_141
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_142
+ true
+ false
+
+
+ choices_143
+ true
+ false
+
+
+ choices_144
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_145
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_146
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_147
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_148
+ true
+ false
+
+
+ choices_149
+ 128_bytes
+ 256_bytes
+ 512_bytes
+ 1024_bytes
+
+
+ choices_150
+ true
+ false
+
+
+ choices_151
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_152
+ true
+ false
+
+
+ choices_153
+ true
+ false
+
+
+ choices_154
+ true
+ false
+
+
+ choices_155
+ Bytes
+ Kilobytes
+ Megabytes
+
+
+ choices_156
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_157
+ true
+ false
+
+
+ choices_158
+ true
+ false
+
+
+ choices_159
+ true
+ false
+
+
+ choices_160
+ true
+ false
+
+
+ choices_161
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_162
+ true
+ false
+
+
+ choices_163
+ true
+ false
+
+
+ choices_164
+ true
+ false
+
+
+ choices_165
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_166
+ Wireless_controller
+ Satellite_communication_controllers
+ Data_acquisition_and_signal_processing_controllers
+ Intelligent_I/O_controllers
+ Docking_stations
+ Device_was_built_before_Class_Code_definitions_were_finalized
+ Memory_controller
+ Simple_communication_controllers
+ Serial_bus_controllers
+ Encryption/Decryption_controllers
+ Display_controller
+ Multimedia_device
+ Input_devices
+ Mass_storage_controller
+ Processors
+ Device_does_not_fit_in_any_defined_classes
+ Bridge_device
+ Network_controller
+ Base_system_peripherals
+
+
+ choices_167
+ Generic_XT_compatible_serial_controller
+ 16450_compatible_serial_controller
+ Parallel_port
+ IEEE_1284_controller
+ Multiport_serial_controller
+ 16650_compatible_serial_controller
+ IEEE_1284_target_device
+ Hayes_compatible_modem_with_16550_compatible_interface
+ ECP_1.X_compliant_parallel_port
+ 16850_compatible_serial_controller
+ Hayes_compatible_modem_with_16750_compatible_interface
+ Smard_Card
+ Bi_directional_parallel_port
+ Other_communications_device
+ GPIB(IEEE_488.1/2)_controller
+ 16550_compatible_serial_controller
+ Hayes_compatible_modem_with_16450_compatible_interface
+ 16750_compatible_serial_controller
+ Hayes_compatible_modem_with_16650_compatible_interface
+ Generic_modem
+ 16950_compatible_serial_controller
+
+
+ choices_168
+ Memory
+
+
+ choices_169
+ true
+ false
+
+
+ choices_170
+ true
+ false
+
+
+ choices_171
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_172
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_173
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_174
+ true
+ false
+
+
+ choices_175
+ N/A
+
+
+ choices_176
+ true
+ false
+
+
+ choices_177
+ Bytes
+ Kilobytes
+ Megabytes
+
+
+ choices_178
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_179
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_180
+ true
+ false
+
+
+ choices_181
+ true
+ false
+
+
+ choices_182
+ true
+ false
+
+
+ choices_183
+ N/A
+
+
+ choices_184
+ true
+ false
+
+
+ choices_185
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_186
+ N/A
+
+
+ choices_187
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_188
+ true
+ false
+
+
+ choices_189
+ N/A
+
+
+ choices_190
+ true
+ false
+
+
+ choices_191
+ true
+ false
+
+
+ choices_192
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_193
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_194
+ true
+ false
+
+
+ choices_195
+ N/A
+
+
+ choices_196
+ true
+ false
+
+
+ choices_197
+ true
+ false
+
+
+ choices_198
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_199
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_200
+ true
+ false
+
+
+ choices_201
+ true
+ false
+
+
+ choices_202
+ true
+ false
+
+
+ choices_203
+ N/A
+
+
+ choices_204
+ true
+ false
+
+
+ choices_205
+ true
+ false
+
+
+ choices_206
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_207
+ true
+ false
+
+
+ choices_208
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_209
+ true
+ false
+
+
+ choices_210
+ N/A
+
+
+ choices_211
+ true
+ false
+
+
+ choices_212
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_213
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_214
+ true
+ false
+
+
+ choices_215
+ Good
+ Extreme
+
+
+ choices_216
+ 128_bit
+ 256_bit
+
+
+ choices_217
+ true
+ false
+
+
+ choices_218
+ Memory
+
+
+ choices_219
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_220
+ true
+ false
+
+
+ choices_221
+ true
+ false
+
+
+ choices_222
+ true
+ false
+
+
+ choices_223
+ N/A
+
+
+ choices_224
+ true
+ false
+
+
+ choices_225
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_226
+ true
+ false
+
+
+ choices_227
+ true
+ false
+
+
+ choices_228
+ true
+ false
+
+
+ choices_229
+ N/A
+
+
+ choices_230
+ true
+ false
+
+
+ choices_231
+ 1
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choices_232
+ true
+ false
+
+
+ choices_233
+ Bytes
+ Kilobytes
+ Megabytes
+ Gigabytes
+
+
+ choices_234
+ 128_bytes
+ 256_bytes
+ 512_bytes
+ 1024_bytes
+
+
+ choices_235
+ true
+ false
+
+
+ choices_236
+ N/A
+
+
+ choices_237
+ true
+ false
+
+
+ choices_238
+ Basic
+ Advanced
+
+
+ choices_239
+ None
+ Tandem_PROM (Refer PG023)
+ Tandem_PCIe (Refer PG023)
+
+
+ choices_240
+ 250
+
+
+ choices_241
+ No_ASPM
+
+
+ choices_242
+ Custom
+
+
+ choices_243
+ true
+ false
+
+
+ choices_244
+ true
+ false
+
+
+ choices_245
+ None
+ Enable_Pipe_Simulation
+ Enable_External_PIPE_Interface
+
+
+
+
+ xilinx_elaboratesubcores_view_fileset
+
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+
+ source/PCIeGen3x4If128_qpll_wrapper.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_rxeq_scan.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_gt_wrapper.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_gt_top.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_gt_common.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_gtx_cpllpd_ovrd.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128-PCIE_X0Y2.xdc
+ xdc
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ synth/PCIeGen3x4If128_ooc.xdc
+ xdc
+ USED_IN_out_of_context
+ USED_IN_synthesis
+ USED_IN_implementation
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_3_0_7vx.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+
+ xilinx_verilogsynthesiswrapper_view_fileset
+
+ synth/PCIeGen3x4If128.v
+ verilogSource
+ xil_defaultlib
+
+
+
+ xilinx_verilogbehavioralsimulation_view_fileset
+
+ source/PCIeGen3x4If128_pcie_7vx.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_bram_7vx.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_bram_7vx_8k.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_bram_7vx_16k.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_bram_7vx_cpl.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_bram_7vx_rep.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_bram_7vx_rep_8k.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_bram_7vx_req.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_init_ctrl_7vx.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_pipe_lane.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_pipe_misc.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_pipe_pipeline.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_top.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_force_adapt.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pipe_clock.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pipe_drp.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pipe_eq.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pipe_rate.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pipe_reset.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pipe_sync.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pipe_user.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pipe_wrapper.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_qpll_drp.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_qpll_reset.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_qpll_wrapper.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_rxeq_scan.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_gt_wrapper.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_gt_top.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_gt_common.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_gtx_cpllpd_ovrd.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_tlp_tph_tbl_7vx.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+ source/PCIeGen3x4If128_pcie_3_0_7vx.v
+ verilogSource
+ PCIeGen3x4If128_pcie_3_0_7vx
+
+
+
+ xilinx_verilogsimulationwrapper_view_fileset
+
+ sim/PCIeGen3x4If128.v
+ verilogSource
+ xil_defaultlib
+
+
+
+ xilinx_versioninformation_view_fileset
+
+ doc/pcie3_7x_v3_0_changelog.txt
+ text
+
+
+
+ xilinx_externalfiles_view_fileset
+
+ PCIeGen3x4If128.dcp
+ dcp
+ USED_IN_synthesis
+ USED_IN_implementation
+ xil_defaultlib
+
+
+ PCIeGen3x4If128_stub.v
+ verilogSource
+ USED_IN_synth_blackbox_stub
+ xil_defaultlib
+
+
+ PCIeGen3x4If128_stub.vhdl
+ vhdlSource
+ USED_IN_synth_blackbox_stub
+ xil_defaultlib
+
+
+ PCIeGen3x4If128_funcsim.v
+ verilogSource
+ USED_IN_simulation
+ USED_IN_single_language
+ xil_defaultlib
+
+
+ PCIeGen3x4If128_funcsim.vhdl
+ vhdlSource
+ USED_IN_simulation
+ USED_IN_single_language
+ xil_defaultlib
+
+
+
+ The Xilinx 7 Series Gen3 Integrated Block for PCI Express (1-lane, 2-lane, 4-lane, and 8-lane) in conjunction with flexible 7-Series architectural features such as integrated GTs (Gigabit Transceivers) and BRAM (Block RAMs) are used to implement a PCI Express Base Specification v3.0 compliant PCI Express Endpoint.
+
+
+ device_port_type
+ Device Port Type
+ PCI_Express_Endpoint_device
+
+
+ xlnx_ref_board
+ Xlnx Ref Board
+ None
+
+
+
+ false
+
+
+
+
+
+ PL_LINK_CAP_MAX_LINK_SPEED
+ Pl Link Cap Max Link Speed
+ 8.0_GT/s
+
+
+ PL_LINK_CAP_MAX_LINK_WIDTH
+ Pl Link Cap Max Link Width
+ The Xilinx 7 Series Gen3 Integrated Block for PCI Expressification v3.0 compliant PCI Express Endpoint.
+ X4
+
+
+ REF_CLK_FREQ
+ Ref Clk Freq
+ 100_MHz
+
+
+ AXISTEN_IF_RC_STRADDLE
+ Axisten If Rc Straddle
+ false
+
+
+ axisten_if_enable_client_tag
+ Disable Client Tag
+ false
+
+
+ PF0_AER_CAP_ECRC_CHECK_CAPABLE
+ Pf0 Aer Cap Ecrc Check Capable
+ false
+
+
+ PF0_AER_CAP_ECRC_GEN_CAPABLE
+ Pf0 Aer Cap Ecrc Gen Capable
+ false
+
+
+ PF0_CLASS_CODE
+ Pf0 Class Code
+ 058000
+
+
+ PF0_DEVICE_ID
+ Pf0 Device Id
+ 7034
+
+
+ PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT
+ Pf0 Dev Cap2 128b Cas Atomic Completer Support
+ false
+
+
+ PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT
+ Pf0 Dev Cap2 32b Atomic Completer Support
+ false
+
+
+ PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT
+ Pf0 Dev Cap2 64b Atomic Completer Support
+ false
+
+
+ PF0_DEV_CAP2_OBFF_SUPPORT
+ Pf0 Dev Cap2 Obff Support
+ 00_Not_Supported
+
+
+ PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT
+ Pf0 Dev Cap2 Tph Completer Support
+ false
+
+
+ PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE
+ Pf0 Dev Cap Function Level Reset Capable
+ false
+
+
+ PF0_INTERRUPT_PIN
+ Pf0 Interrupt Pin
+ NONE
+
+
+ PF0_LINK_STATUS_SLOT_CLOCK_CONFIG
+ Pf0 Link Status Slot Clock Config
+ false
+
+
+ PF0_MSIX_CAP_PBA_BIR
+ Pf0 Msix Cap Pba Bir
+ BAR_0
+
+
+ PF0_MSIX_CAP_PBA_OFFSET
+ Pf0 Msix Cap Pba Offset
+ 00000000
+
+
+ PF0_MSIX_CAP_TABLE_BIR
+ Pf0 Msix Cap Table Bir
+ BAR_0
+
+
+ PF0_MSIX_CAP_TABLE_OFFSET
+ Pf0 Msix Cap Table Offset
+ 00000000
+
+
+ PF0_MSIX_CAP_TABLE_SIZE
+ Pf0 Msix Cap Table Size
+ 000
+
+
+ PF0_MSI_CAP_MULTIMSGCAP
+ Pf0 Msi Cap Multimsgcap
+ 1_vector
+
+
+ PF0_PM_CAP_PMESUPPORT_D1
+ Pf0 Pm Cap Pmesupport D1
+ false
+
+
+ PF0_PM_CAP_PMESUPPORT_D3HOT
+ Pf0 Pm Cap Pmesupport D3hot
+ false
+
+
+ PF0_PM_CAP_SUPP_D1_STATE
+ Pf0 Pm Cap Supp D1 State
+ false
+
+
+ PF0_REVISION_ID
+ Pf0 Revision Id
+ 00
+
+
+ PF0_SRIOV_CAP_INITIAL_VF
+ Pf0 Sriov Cap Initial Vf
+ 0
+
+
+ PF0_SRIOV_FIRST_VF_OFFSET
+ Pf0 Sriov First Vf Offset
+ N/A
+
+
+ PF0_SRIOV_FUNC_DEP_LINK
+ Pf0 Sriov Func Dep Link
+ 0000
+
+
+ PF0_SRIOV_SUPPORTED_PAGE_SIZE
+ Pf0 Sriov Supported Page Size
+ 00000553
+
+
+ PF0_SRIOV_VF_DEVICE_ID
+ Pf0 Sriov Vf Device Id
+ 0000
+
+
+ PF0_SUBSYSTEM_ID
+ Pf0 Subsystem Id
+ 0007
+
+
+ PF1_AER_CAP_ECRC_CHECK_CAPABLE
+ Pf1 Aer Cap Ecrc Check Capable
+ false
+
+
+ PF1_AER_CAP_ECRC_GEN_CAPABLE
+ Pf1 Aer Cap Ecrc Gen Capable
+ false
+
+
+ PF1_CLASS_CODE
+ Pf1 Class Code
+ 058000
+
+
+ PF1_DEVICE_ID
+ Pf1 Device Id
+ 7011
+
+
+ PF1_INTERRUPT_PIN
+ Pf1 Interrupt Pin
+ NONE
+
+
+ PF1_MSIX_CAP_PBA_BIR
+ Pf1 Msix Cap Pba Bir
+ BAR_0
+
+
+ PF1_MSIX_CAP_TABLE_BIR
+ Pf1 Msix Cap Table Bir
+ BAR_0
+
+
+ PF1_MSIX_CAP_TABLE_SIZE
+ Pf1 Msix Cap Table Size
+ 000
+
+
+ PF1_MSIX_CAP_TABLE_OFFSET
+ Pf1 Msix Cap Table Offset
+ 00000000
+
+
+ PF1_MSIX_CAP_PBA_OFFSET
+ Pf1 Msix Cap Pba Offset
+ 00000000
+
+
+ PF1_MSI_CAP_MULTIMSGCAP
+ Pf1 Msi Cap Multimsgcap
+ 1_vector
+
+
+ PF1_REVISION_ID
+ Pf1 Revision Id
+ 00
+
+
+ PF1_SRIOV_CAP_INITIAL_VF
+ Pf1 Sriov Cap Initial Vf
+ 0
+
+
+ PF1_SRIOV_CAP_VER
+ Pf1 Sriov Cap Ver
+ 0
+
+
+ PF1_SRIOV_FIRST_VF_OFFSET
+ Pf1 Sriov First Vf Offset
+ N/A
+
+
+ PF1_SRIOV_FUNC_DEP_LINK
+ Pf1 Sriov Func Dep Link
+ 0001
+
+
+ PF1_SRIOV_SUPPORTED_PAGE_SIZE
+ Pf1 Sriov Supported Page Size
+ 00000553
+
+
+ PF1_SRIOV_VF_DEVICE_ID
+ Pf1 Sriov Vf Device Id
+ 0000
+
+
+ PF1_SUBSYSTEM_ID
+ Pf1 Subsystem Id
+ 0007
+
+
+ tl_pf0_enable_reg
+ Tl Pf0 Enable Reg
+ true
+
+
+ TL_PF_ENABLE_REG
+ Tl Pf Enable Reg
+ false
+
+
+ SRIOV_CAP_ENABLE
+ Sriov Cap Enable
+ false
+
+
+ VF0_MSIX_CAP_PBA_BIR
+ Vf0 Msix Cap Pba Bir
+ BAR_0
+
+
+ VF0_MSIX_CAP_PBA_OFFSET
+ Vf0 Msix Cap Pba Offset
+ 00000000
+
+
+ VF0_MSIX_CAP_TABLE_BIR
+ Vf0 Msix Cap Table Bir
+ BAR_0
+
+
+ VF0_MSIX_CAP_TABLE_OFFSET
+ Vf0 Msix Cap Table Offset
+ 00000000
+
+
+ VF0_MSIX_CAP_TABLE_SIZE
+ Vf0 Msix Cap Table Size
+ 000
+
+
+ VF0_MSI_CAP_MULTIMSGCAP
+ Vf0 Msi Cap Multimsgcap
+ 1_vector
+
+
+ VF1_MSIX_CAP_PBA_BIR
+ Vf1 Msix Cap Pba Bir
+ BAR_0
+
+
+ VF1_MSIX_CAP_PBA_OFFSET
+ Vf1 Msix Cap Pba Offset
+ 00000000
+
+
+ VF1_MSIX_CAP_TABLE_BIR
+ Vf1 Msix Cap Table Bir
+ BAR_0
+
+
+ VF1_MSIX_CAP_TABLE_OFFSET
+ Vf1 Msix Cap Table Offset
+ 00000000
+
+
+ VF1_MSIX_CAP_TABLE_SIZE
+ Vf1 Msix Cap Table Size
+ 000
+
+
+ VF1_MSI_CAP_MULTIMSGCAP
+ Vf1 Msi Cap Multimsgcap
+ 1_vector
+
+
+ VF2_MSIX_CAP_PBA_BIR
+ Vf2 Msix Cap Pba Bir
+ BAR_0
+
+
+ VF2_MSIX_CAP_PBA_OFFSET
+ Vf2 Msix Cap Pba Offset
+ 00000000
+
+
+ VF2_MSIX_CAP_TABLE_BIR
+ Vf2 Msix Cap Table Bir
+ BAR_0
+
+
+ VF2_MSIX_CAP_TABLE_OFFSET
+ Vf2 Msix Cap Table Offset
+ 00000000
+
+
+ VF2_MSIX_CAP_TABLE_SIZE
+ Vf2 Msix Cap Table Size
+ 000
+
+
+ VF2_MSI_CAP_MULTIMSGCAP
+ Vf2 Msi Cap Multimsgcap
+ 1_vector
+
+
+ VF3_MSIX_CAP_PBA_BIR
+ Vf3 Msix Cap Pba Bir
+ BAR_0
+
+
+ VF3_MSIX_CAP_PBA_OFFSET
+ Vf3 Msix Cap Pba Offset
+ 00000000
+
+
+ VF3_MSIX_CAP_TABLE_BIR
+ Vf3 Msix Cap Table Bir
+ BAR_0
+
+
+ VF3_MSIX_CAP_TABLE_OFFSET
+ Vf3 Msix Cap Table Offset
+ 00000000
+
+
+ VF3_MSIX_CAP_TABLE_SIZE
+ Vf3 Msix Cap Table Size
+ 000
+
+
+ VF3_MSI_CAP_MULTIMSGCAP
+ Vf3 Msi Cap Multimsgcap
+ 1_vector
+
+
+ VF4_MSIX_CAP_PBA_BIR
+ Vf4 Msix Cap Pba Bir
+ BAR_0
+
+
+ VF4_MSIX_CAP_PBA_OFFSET
+ Vf4 Msix Cap Pba Offset
+ 00000000
+
+
+ VF4_MSIX_CAP_TABLE_BIR
+ Vf4 Msix Cap Table Bir
+ BAR_0
+
+
+ VF4_MSIX_CAP_TABLE_OFFSET
+ Vf4 Msix Cap Table Offset
+ 00000000
+
+
+ VF4_MSIX_CAP_TABLE_SIZE
+ Vf4 Msix Cap Table Size
+ 000
+
+
+ VF4_MSI_CAP_MULTIMSGCAP
+ Vf4 Msi Cap Multimsgcap
+ 1_vector
+
+
+ VF5_MSIX_CAP_PBA_BIR
+ Vf5 Msix Cap Pba Bir
+ BAR_0
+
+
+ VF5_MSIX_CAP_PBA_OFFSET
+ Vf5 Msix Cap Pba Offset
+ 00000000
+
+
+ VF5_MSIX_CAP_TABLE_BIR
+ Vf5 Msix Cap Table Bir
+ BAR_0
+
+
+ VF5_MSIX_CAP_TABLE_OFFSET
+ Vf5 Msix Cap Table Offset
+ 00000000
+
+
+ VF5_MSIX_CAP_TABLE_SIZE
+ Vf5 Msix Cap Table Size
+ 000
+
+
+ VF5_MSI_CAP_MULTIMSGCAP
+ Vf5 Msi Cap Multimsgcap
+ 1_vector
+
+
+ Component_Name
+ PCIeGen3x4If128
+
+
+ PF0_Use_Class_Code_Lookup_Assistant
+ false
+
+
+ PF1_Use_Class_Code_Lookup_Assistant
+ false
+
+
+ PF0_PM_CAP_PMESUPPORT_D0
+ Pf0 Pm Cap Pmesupport D0
+ false
+
+
+ PF0_SUBSYSTEM_VENDOR_ID
+ Pf0 Subsystem Vendor Id
+ 10EE
+
+
+ pf1_sriov_bar5_scale
+ Pf1 Sriov Bar5 Scale
+ Kilobytes
+
+
+ pf0_class_code_sub
+ Pf0 Class Code Sub
+ 80
+
+
+ pf1_sriov_bar4_type
+ Pf1 Sriov Bar4 Type
+ N/A
+
+
+ pf0_vc_cap_enabled
+ Pf0 Vc Cap Enabled
+ false
+
+
+ pf1_sriov_bar5_type
+ Pf1 Sriov Bar5 Type
+ N/A
+
+
+ pf1_sriov_bar0_enabled
+ Pf1 Sriov Bar0 Enabled
+ true
+
+
+ pf0_sriov_bar5_enabled
+ Pf0 Sriov Bar5 Enabled
+ false
+
+
+ pcie_blk_locn
+ Pcie Blk Locn
+ X0Y2
+
+
+ pf0_sriov_bar1_64bit
+ Pf0 Sriov Bar1 64bit
+ false
+
+
+ pf1_class_code_base
+ Pf1 Class Code Base
+ 05
+
+
+ pf1_sriov_bar3_prefetchable
+ Pf1 Sriov Bar3 Prefetchable
+ false
+
+
+ pf0_pb_enabled
+ Pf0 Pb Enabled
+ false
+
+
+ pf1_sriov_bar0_64bit
+ Pf1 Sriov Bar0 64bit
+ false
+
+
+ pf1_bar3_type
+ Pf1 Bar3 Type
+ N/A
+
+
+ pf1_bar2_enabled
+ Pf1 Bar2 Enabled
+ false
+
+
+ pf1_bar2_type
+ Pf1 Bar2 Type
+ N/A
+
+
+ pf1_bar2_64bit
+ Pf1 Bar2 64bit
+ false
+
+
+ pf1_bar2_prefetchable
+ Pf1 Bar2 Prefetchable
+ false
+
+
+ pf1_bar2_scale
+ Pf1 Bar2 Scale
+ Kilobytes
+
+
+ pf1_bar2_size
+ Pf1 Bar2 Size
+ 2
+
+
+ pf0_class_code_interface
+ Pf0 Class Code Interface
+ 00
+
+
+ pf0_sriov_bar1_scale
+ Pf0 Sriov Bar1 Scale
+ Kilobytes
+
+
+ pf1_bar4_type
+ Pf1 Bar4 Type
+ N/A
+
+
+ pf0_base_class_menu
+ Pf0 Base Class Menu
+ Simple_communication_controllers
+
+
+ pf0_sub_class_interface_menu
+ Pf0 Sub Class Interface Menu
+ Generic_XT_compatible_serial_controller
+
+
+ pf1_sriov_bar0_scale
+ Pf1 Sriov Bar0 Scale
+ Kilobytes
+
+
+ pf1_expansion_rom_enabled
+ Pf1 Expansion Rom Enabled
+ false
+
+
+ pf0_sriov_bar0_enabled
+ Pf0 Sriov Bar0 Enabled
+ true
+
+
+ pf1_sriov_bar0_prefetchable
+ Pf1 Sriov Bar0 Prefetchable
+ false
+
+
+ pf1_bar5_type
+ Pf1 Bar5 Type
+ N/A
+
+
+ pf0_sriov_bar5_prefetchable
+ Pf0 Sriov Bar5 Prefetchable
+ false
+
+
+ pf1_sriov_bar1_enabled
+ Pf1 Sriov Bar1 Enabled
+ false
+
+
+ pf1_class_code_interface
+ Pf1 Class Code Interface
+ 00
+
+
+ pf0_sriov_bar2_64bit
+ Pf0 Sriov Bar2 64bit
+ false
+
+
+ pf1_msix_enabled
+ Pf1 Msix Enabled
+ false
+
+
+ pf1_bar5_prefetchable
+ Pf1 Bar5 Prefetchable
+ false
+
+
+ pf0_rbar_enabled
+ Pf0 Rbar Enabled
+ false
+
+
+ pf1_pb_enabled
+ Pf1 Pb Enabled
+ false
+
+
+ pf1_sriov_bar1_64bit
+ Pf1 Sriov Bar1 64bit
+ false
+
+
+ pf1_bar3_64bit
+ Pf1 Bar3 64bit
+ false
+
+
+ pf0_sriov_bar2_prefetchable
+ Pf0 Sriov Bar2 Prefetchable
+ false
+
+
+ pf1_bar3_enabled
+ Pf1 Bar3 Enabled
+ false
+
+
+ pf0_sriov_bar2_scale
+ Pf0 Sriov Bar2 Scale
+ Kilobytes
+
+
+ pf1_sriov_bar1_scale
+ Pf1 Sriov Bar1 Scale
+ Kilobytes
+
+
+ pf1_bar3_scale
+ Pf1 Bar3 Scale
+ Kilobytes
+
+
+ pf0_sriov_bar1_enabled
+ Pf0 Sriov Bar1 Enabled
+ false
+
+
+ alignment_mode
+ Alignment Mode
+ DWORD_Aligned
+
+
+ pf1_sriov_bar4_prefetchable
+ Pf1 Sriov Bar4 Prefetchable
+ false
+
+
+ silicon_rev
+ Silicon Rev
+ Production
+
+
+ pf1_sriov_bar2_enabled
+ Pf1 Sriov Bar2 Enabled
+ false
+
+
+ pf0_sriov_bar3_64bit
+ Pf0 Sriov Bar3 64bit
+ false
+
+
+ pf0_sriov_bar0_size
+ Pf0 Sriov Bar0 Size
+ 2
+
+
+ pf1_sriov_bar2_64bit
+ Pf1 Sriov Bar2 64bit
+ false
+
+
+ pf1_bar4_64bit
+ Pf1 Bar4 64bit
+ false
+
+
+ pf0_sriov_bar1_size
+ Pf0 Sriov Bar1 Size
+ 2
+
+
+ pf0_bar0_enabled
+ Pf0 Bar0 Enabled
+ true
+
+
+ pf0_bar0_type
+ Pf0 Bar0 Type
+ Memory
+
+
+ pf0_bar0_64bit
+ Pf0 Bar0 64bit
+ false
+
+
+ pf0_bar0_prefetchable
+ Pf0 Bar0 Prefetchable
+ false
+
+
+ pf0_bar0_scale
+ Pf0 Bar0 Scale
+ Kilobytes
+
+
+ pf0_bar0_size
+ Pf0 Bar0 Size
+ 1
+
+
+ pf0_bar1_enabled
+ Pf0 Bar1 Enabled
+ false
+
+
+ pf0_bar1_type
+ Pf0 Bar1 Type
+ N/A
+
+
+ pf0_bar1_64bit
+ Pf0 Bar1 64bit
+ false
+
+
+ pf0_bar1_prefetchable
+ Pf0 Bar1 Prefetchable
+ false
+
+
+ pf0_bar1_scale
+ Pf0 Bar1 Scale
+ Kilobytes
+
+
+ pf0_bar1_size
+ Pf0 Bar1 Size
+ 2
+
+
+ pf0_bar2_enabled
+ Pf0 Bar2 Enabled
+ false
+
+
+ pf0_bar2_type
+ Pf0 Bar2 Type
+ N/A
+
+
+ pf0_bar2_64bit
+ Pf0 Bar2 64bit
+ false
+
+
+ pf0_bar2_prefetchable
+ Pf0 Bar2 Prefetchable
+ false
+
+
+ pf0_bar2_scale
+ Pf0 Bar2 Scale
+ Kilobytes
+
+
+ pf0_bar2_size
+ Pf0 Bar2 Size
+ 2
+
+
+ pf0_bar3_enabled
+ Pf0 Bar3 Enabled
+ false
+
+
+ pf0_bar3_type
+ Pf0 Bar3 Type
+ N/A
+
+
+ pf0_bar3_64bit
+ Pf0 Bar3 64bit
+ false
+
+
+ pf0_bar3_prefetchable
+ Pf0 Bar3 Prefetchable
+ false
+
+
+ pf0_bar3_scale
+ Pf0 Bar3 Scale
+ Kilobytes
+
+
+ pf0_bar3_size
+ Pf0 Bar3 Size
+ 2
+
+
+ pf0_bar4_enabled
+ Pf0 Bar4 Enabled
+ false
+
+
+ pf0_bar4_type
+ Pf0 Bar4 Type
+ N/A
+
+
+ pf0_bar4_64bit
+ Pf0 Bar4 64bit
+ false
+
+
+ pf0_bar4_prefetchable
+ Pf0 Bar4 Prefetchable
+ false
+
+
+ pf0_bar4_scale
+ Pf0 Bar4 Scale
+ Kilobytes
+
+
+ pf0_bar4_size
+ Pf0 Bar4 Size
+ 2
+
+
+ pf0_bar5_enabled
+ Pf0 Bar5 Enabled
+ false
+
+
+ pf0_bar5_type
+ Pf0 Bar5 Type
+ N/A
+
+
+ pf0_bar5_prefetchable
+ Pf0 Bar5 Prefetchable
+ false
+
+
+ pf0_bar5_scale
+ Pf0 Bar5 Scale
+ Kilobytes
+
+
+ pf0_bar5_size
+ Pf0 Bar5 Size
+ 2
+
+
+ pf0_sriov_bar3_scale
+ Pf0 Sriov Bar3 Scale
+ Kilobytes
+
+
+ pf1_bar4_enabled
+ Pf1 Bar4 Enabled
+ false
+
+
+ pf1_sriov_bar1_prefetchable
+ Pf1 Sriov Bar1 Prefetchable
+ false
+
+
+ pf0_sriov_bar2_size
+ Pf0 Sriov Bar2 Size
+ 2
+
+
+ pf1_sriov_bar2_scale
+ Pf1 Sriov Bar2 Scale
+ Kilobytes
+
+
+ pf1_bar4_scale
+ Pf1 Bar4 Scale
+ Kilobytes
+
+
+ pf0_sriov_bar3_size
+ Pf0 Sriov Bar3 Size
+ 2
+
+
+ pf0_sriov_bar2_enabled
+ Pf0 Sriov Bar2 Enabled
+ false
+
+
+ pf0_dev_cap_max_payload
+ Pf0 Dev Cap Max Payload
+ 512_bytes
+
+
+ gen_x0y0
+ Gen X0y0
+ false
+
+
+ pf0_sriov_bar4_size
+ Pf0 Sriov Bar4 Size
+ 2
+
+
+ gen_x0y1
+ Gen X0y1
+ false
+
+
+ gen_x0y2
+ Gen X0y2
+ true
+
+
+ gen_x0y3
+ Gen X0y3
+ false
+
+
+ pf1_expansion_rom_scale
+ Pf1 Expansion Rom Scale
+ Kilobytes
+
+
+ pf1_expansion_rom_size
+ Pf1 Expansion Rom Size
+ 2
+
+
+ pf1_rbar_enabled
+ Pf1 Rbar Enabled
+ false
+
+
+ pf1_tphr_enable
+ Pf1 Tphr Enable
+ false
+
+
+ pf1_sriov_bar3_enabled
+ Pf1 Sriov Bar3 Enabled
+ false
+
+
+ pf0_sriov_bar4_64bit
+ Pf0 Sriov Bar4 64bit
+ false
+
+
+ pf0_sriov_bar5_size
+ Pf0 Sriov Bar5 Size
+ 2
+
+
+ pf0_sriov_bar3_prefetchable
+ Pf0 Sriov Bar3 Prefetchable
+ false
+
+
+ pf1_sriov_bar3_64bit
+ Pf1 Sriov Bar3 64bit
+ false
+
+
+ pf0_expansion_rom_enabled
+ Pf0 Expansion Rom Enabled
+ false
+
+
+ pf0_sriov_bar4_scale
+ Pf0 Sriov Bar4 Scale
+ Kilobytes
+
+
+ pf1_base_class_menu
+ Pf1 Base Class Menu
+ Simple_communication_controllers
+
+
+ pf1_sub_class_interface_menu
+ Pf1 Sub Class Interface Menu
+ Generic_XT_compatible_serial_controller
+
+
+ pf0_sriov_bar0_type
+ Pf0 Sriov Bar0 Type
+ Memory
+
+
+ pf1_bar5_enabled
+ Pf1 Bar5 Enabled
+ false
+
+
+ pf1_bar3_prefetchable
+ Pf1 Bar3 Prefetchable
+ false
+
+
+ pf1_sriov_bar0_size
+ Pf1 Sriov Bar0 Size
+ 2
+
+
+ pf1_sriov_bar3_scale
+ Pf1 Sriov Bar3 Scale
+ Kilobytes
+
+
+ pf1_bar5_scale
+ Pf1 Bar5 Scale
+ Kilobytes
+
+
+ pf1_class_code_sub
+ Pf1 Class Code Sub
+ 80
+
+
+ extended_tag_field
+ Extended Tag Field
+ false
+
+
+ pf0_sriov_bar1_type
+ Pf0 Sriov Bar1 Type
+ N/A
+
+
+ pf0_sriov_bar0_prefetchable
+ Pf0 Sriov Bar0 Prefetchable
+ false
+
+
+ pf0_expansion_rom_scale
+ Pf0 Expansion Rom Scale
+ Kilobytes
+
+
+ pf0_expansion_rom_size
+ Pf0 Expansion Rom Size
+ 2
+
+
+ pf1_sriov_bar1_size
+ Pf1 Sriov Bar1 Size
+ 2
+
+
+ pf1_ari_enabled
+ Pf1 Ari Enabled
+ false
+
+
+ pf0_sriov_bar3_enabled
+ Pf0 Sriov Bar3 Enabled
+ false
+
+
+ pf1_sriov_bar5_prefetchable
+ Pf1 Sriov Bar5 Prefetchable
+ false
+
+
+ pf0_sriov_bar2_type
+ Pf0 Sriov Bar2 Type
+ N/A
+
+
+ vendor_id
+ Vendor Id
+ 10EE
+
+
+ pf0_tphr_enable
+ Pf0 Tphr Enable
+ false
+
+
+ pf1_sriov_bar2_size
+ Pf1 Sriov Bar2 Size
+ 2
+
+
+ pf0_sriov_bar3_type
+ Pf0 Sriov Bar3 Type
+ N/A
+
+
+ pf1_sriov_bar3_size
+ Pf1 Sriov Bar3 Size
+ 2
+
+
+ pf1_bar0_enabled
+ Pf1 Bar0 Enabled
+ false
+
+
+ pf1_bar0_type
+ Pf1 Bar0 Type
+ N/A
+
+
+ pf1_bar0_64bit
+ Pf1 Bar0 64bit
+ false
+
+
+ pf1_bar0_prefetchable
+ Pf1 Bar0 Prefetchable
+ false
+
+
+ pf1_bar0_scale
+ Pf1 Bar0 Scale
+ Kilobytes
+
+
+ pf1_bar0_size
+ Pf1 Bar0 Size
+ 2
+
+
+ pf1_bar1_enabled
+ Pf1 Bar1 Enabled
+ false
+
+
+ pf1_bar1_type
+ Pf1 Bar1 Type
+ N/A
+
+
+ pf1_bar1_64bit
+ Pf1 Bar1 64bit
+ false
+
+
+ pf1_bar1_prefetchable
+ Pf1 Bar1 Prefetchable
+ false
+
+
+ pf1_bar1_scale
+ Pf1 Bar1 Scale
+ Kilobytes
+
+
+ pf1_bar1_size
+ Pf1 Bar1 Size
+ 2
+
+
+ pf1_sriov_bar4_enabled
+ Pf1 Sriov Bar4 Enabled
+ false
+
+
+ pf1_aer_enabled
+ Pf1 Aer Enabled
+ true
+
+
+ pf1_dsn_enabled
+ Pf1 Dsn Enabled
+ false
+
+
+ pf0_sriov_bar4_type
+ Pf0 Sriov Bar4 Type
+ N/A
+
+
+ pf1_sriov_bar4_64bit
+ Pf1 Sriov Bar4 64bit
+ false
+
+
+ pf1_sriov_bar2_prefetchable
+ Pf1 Sriov Bar2 Prefetchable
+ false
+
+
+ pf0_sriov_cap_ver
+ Pf0 Sriov Cap Ver
+ 0
+
+
+ pf1_sriov_bar4_size
+ Pf1 Sriov Bar4 Size
+ 2
+
+
+ pf1_msi_enabled
+ Pf1 Msi Enabled
+ true
+
+
+ pf0_sriov_bar5_scale
+ Pf0 Sriov Bar5 Scale
+ Kilobytes
+
+
+ pf1_dpa_enabled
+ Pf1 Dpa Enabled
+ false
+
+
+ pf0_sriov_bar5_type
+ Pf0 Sriov Bar5 Type
+ N/A
+
+
+ ext_pcie_cfg_space_enabled
+ Ext Pcie Cfg Space Enabled
+ false
+
+
+ pf1_sriov_bar4_scale
+ Pf1 Sriov Bar4 Scale
+ Kilobytes
+
+
+ pf1_sriov_bar5_size
+ Pf1 Sriov Bar5 Size
+ 2
+
+
+ pf0_ari_enabled
+ Pf0 Ari Enabled
+ false
+
+
+ perf_level
+ Perf Level
+ Extreme
+
+
+ pf0_class_code_base
+ Pf0 Class Code Base
+ 05
+
+
+ axisten_if_width
+ Axisten If Width
+ 128_bit
+
+
+ pf0_sriov_bar4_enabled
+ Pf0 Sriov Bar4 Enabled
+ false
+
+
+ pf1_sriov_bar0_type
+ Pf1 Sriov Bar0 Type
+ Memory
+
+
+ pf1_bar3_size
+ Pf1 Bar3 Size
+ 2
+
+
+ pf0_sriov_bar4_prefetchable
+ Pf0 Sriov Bar4 Prefetchable
+ false
+
+
+ pf0_aer_enabled
+ Pf0 Aer Enabled
+ true
+
+
+ pf0_dsn_enabled
+ Pf0 Dsn Enabled
+ false
+
+
+ pf1_sriov_bar1_type
+ Pf1 Sriov Bar1 Type
+ N/A
+
+
+ pf0_sriov_bar0_64bit
+ Pf0 Sriov Bar0 64bit
+ false
+
+
+ pf1_bar4_size
+ Pf1 Bar4 Size
+ 2
+
+
+ pf0_msi_enabled
+ Pf0 Msi Enabled
+ true
+
+
+ pf1_sriov_bar5_enabled
+ Pf1 Sriov Bar5 Enabled
+ false
+
+
+ pf0_dpa_enabled
+ Pf0 Dpa Enabled
+ false
+
+
+ pf1_sriov_bar2_type
+ Pf1 Sriov Bar2 Type
+ N/A
+
+
+ pf0_msix_enabled
+ Pf0 Msix Enabled
+ false
+
+
+ pf1_bar5_size
+ Pf1 Bar5 Size
+ 2
+
+
+ pf1_bar4_prefetchable
+ Pf1 Bar4 Prefetchable
+ false
+
+
+ pf0_sriov_bar0_scale
+ Pf0 Sriov Bar0 Scale
+ Kilobytes
+
+
+ pf1_dev_cap_max_payload
+ Pf1 Dev Cap Max Payload
+ 512_bytes
+
+
+ pf0_sriov_bar1_prefetchable
+ Pf0 Sriov Bar1 Prefetchable
+ false
+
+
+ pf1_sriov_bar3_type
+ Pf1 Sriov Bar3 Type
+ N/A
+
+
+ pf0_ltr_enabled
+ Pf0 Ltr Enabled
+ false
+
+
+ mode_selection
+ Mode
+ Advanced
+
+
+ pipe_sim
+ false
+
+
+ shared_logic_in_core
+ false
+
+
+ en_ext_clk
+ false
+
+
+ en_ext_gt_common
+ false
+
+
+ en_ext_ch_gt_drp
+ false
+
+
+ en_transceiver_status_ports
+ false
+
+
+ tx_fc_if
+ false
+
+
+ cfg_fc_if
+ true
+
+
+ cfg_ext_if
+ false
+
+
+ cfg_status_if
+ true
+
+
+ per_func_status_if
+ false
+
+
+ cfg_mgmt_if
+ false
+
+
+ rcv_msg_if
+ false
+
+
+ cfg_tx_msg_if
+ false
+
+
+ cfg_ctl_if
+ false
+
+
+ en_pcie_drp
+ false
+
+
+ en_ext_pipe_interface
+ false
+
+
+ en_msi_per_vec_masking
+ false
+
+
+ en_ext_startup
+ false
+
+
+ tandem_mode
+ Tandem Mode
+ None
+
+
+ axisten_freq
+ AXISTEN IF FREQ
+ 250
+
+
+ aspm_support
+ ASPM Support
+ No_ASPM
+
+
+ USE_BOARD_FLOW
+ Generate Board based IO Constraints
+ false
+
+
+ RESET_BOARD_INTERFACE
+ Custom
+
+
+ SRIOV_CAP_ENABLE_EXT
+ SRIOV Cap Enable
+ false
+
+
+ axisten_if_enable_msg_route
+ 2FFFF
+
+
+ axisten_if_enable_rx_msg_intfc
+ false
+
+
+ pipe_mode_sim
+ None
+
+
+ en_powerdown
+ false
+
+
+
+
+
+ qvirtex7{xq7vx(330|690|980)(.*)}
+ virtex7{xc7vh(580|870)th(.*)}
+ virtex7{xc7vx(330|415|550|690|980|1140)(.*)}
+
+
+ /Standard_Bus_Interfaces/PCI_Express
+
+ Virtex-7 FPGA Gen3 Integrated Block for PCI Express
+ http://www.xilinx.com
+ 4
+
+ xilinx.com:ip:pcie3_7x:1.3
+ xilinx.com:ip:pcie3_7x:1.4
+ xilinx.com:ip:pcie3_7x:2.0
+ xilinx.com:ip:pcie3_7x:2.1
+ xilinx.com:ip:pcie3_7x:2.2
+
+ 2014-11-18T08:00:57Z
+
+
+ 2014.4
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/prj/7V3_Gen3x4If128.xpr b/fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/prj/7V3_Gen3x4If128.xpr
new file mode 100644
index 0000000..881cf70
--- /dev/null
+++ b/fpga/xilinx/adm-pcie-7v3/7V3_Gen3x4If128/prj/7V3_Gen3x4If128.xpr
@@ -0,0 +1,790 @@
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+
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+
+
+
+
+
+
+
+
+ Vivado Synthesis Defaults
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Vivado Implementation Defaults
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/fpga/xilinx/adm-pcie-7v3/riffa_wrapper_7V3.v b/fpga/xilinx/adm-pcie-7v3/riffa_wrapper_7V3.v
index 0be3237..88e47e7 100644
--- a/fpga/xilinx/adm-pcie-7v3/riffa_wrapper_7V3.v
+++ b/fpga/xilinx/adm-pcie-7v3/riffa_wrapper_7V3.v
@@ -148,7 +148,7 @@ module riffa_wrapper_7V3
localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
localparam C_PIPELINE_OUTPUT = 1;
localparam C_PIPELINE_INPUT = 1;
- localparam C_DEPTH_PACKETS = 10;
+ localparam C_DEPTH_PACKETS = 4;
wire clk;
wire rst_in;