FPGA/riffa
1
0
Fork 0
mirror of https://github.com/KastnerRG/riffa.git synced 2024-12-24 22:58:54 +08:00
Code Issues Projects Releases Wiki Activity

Fixing/updating makefiles for new xilinx clock test projects

Browse Source
This commit is contained in:
Dustin Richmond 2016-08-11 13:54:54 -07:00
parent e97054d191
commit eb1a3934c4
4 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
fpga/xilinx/vc709/Makefile
View File

@ -40,7 +40,7 @@
# Author: Dustin Richmond (@darichmond) # Author: Dustin Richmond (@darichmond)
#----------------------------------------------------------------------- #-----------------------------------------------------------------------
BOARD:=vc709 BOARD:=vc709
BOARD_PROJECTS:=VC709_Gen1x8If64 VC709_Gen2x8If128 VC709_Gen3x4If128 BOARD_PROJECTS:=VC709_Gen1x8If64 VC709_Gen2x8If128 VC709_Gen3x4If128 VC709_Gen1x8If64_CLK VC709_Gen2x8If128_CLK
BOARD_TYPE:=ultrascale BOARD_TYPE:=ultrascale
VENDOR:=xilinx VENDOR:=xilinx
include ../vendor.mk include ../vendor.mk

2
fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/Makefile
View File

@ -59,4 +59,4 @@ endif
include $(RIFFA_HDL_PATH)/riffa.mk include $(RIFFA_HDL_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk include $(BOARD_PATH)/board.mk
PROJECT_IP+=ip/PCIeGen1x8If64.xci PROJECT_IP+=ip/PCIeGen1x8If64.xci ip/clk_250MIn_2/clk_250MIn_2.xci ip/clk_250MIn_1/clk_250MIn_1.xci

2
fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/Makefile
View File

@ -59,4 +59,4 @@ endif
include $(RIFFA_HDL_PATH)/riffa.mk include $(RIFFA_HDL_PATH)/riffa.mk
include $(BOARD_PATH)/board.mk include $(BOARD_PATH)/board.mk
PROJECT_IP+=ip/PCIeGen2x8If128.xci PROJECT_IP+=ip/PCIeGen2x8If128.xci ip/clk_250MIn_2/clk_250MIn_2.xci ip/clk_250MIn_1/clk_250MIn_1.xci

2
fpga/xilinx/vc709/board.mk
View File

@ -78,7 +78,7 @@ all $(TYPE) $(VENDOR) $(BOARD):$(PROJECT)
clean: clean:
echo "reset_run impl_1; reset_run synth_1;" | vivado -mode tcl prj/$(PROJECT).xpr echo "reset_run impl_1; reset_run synth_1;" | vivado -mode tcl prj/$(PROJECT).xpr
rm -rf *.log *.jou *~ .Xil rm -rf *.log *.jou *~ .Xil
rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~ rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~ ip/*.txt ip/clk_250MIn_2 ip/clk_250MIn_1
rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~ rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~
clobber: clobber: