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Adding a few changes the the ML605 project.

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Forgot to specify development board in the ip block, also commented out a ucf
file line.
This commit is contained in:
Dustin Richmond 2015-08-11 15:34:35 -07:00
parent 47530ee0cf
commit f836029e8d
3 changed files with 16 additions and 19 deletions
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2
fpga/xilinx/ml605/ML605Gen2x4If128/constr/ML605_Top.ucf
View File

@ -101,8 +101,6 @@ PIN "PCIeGen*/trn_reset_n_int_i.CLR" TIG ;
PIN "PCIeGen*/trn_reset_n_i.CLR" TIG ;
PIN "PCIeGen*/pcie_clocking_i/mmcm_adv_i.RST" TIG ;
#TIMESPEC "TS_RESETN" = FROM FFS(*) TO FFS(user_reset) 8 ns;
###############################################################################
# Physical Constraints
###############################################################################

6
fpga/xilinx/ml605/ML605Gen2x4If128/ip/PCIeGen2x4If128.xco
View File

@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Fri Feb 27 23:45:45 2015
# Date: Mon Aug 3 23:07:31 2015
#
##############################################################
#
@ -199,10 +199,10 @@ CSET vc_cap_enabled=false
CSET vc_cap_reject_snoop=false
CSET vendor_id=10EE
CSET vsec_enabled=false
CSET xlnx_ref_board=None
CSET xlnx_ref_board=ML_605
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-10-13T18:30:52Z
# END Extra information
GENERATE
# CRC: 1fea7c10
# CRC: 96c65ca9

27
fpga/xilinx/ml605/ML605Gen2x4If128/prj/ML605Gen2x4If128/ML605Gen2x4If128.xise
View File

@ -472,7 +472,7 @@
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
@ -527,8 +527,8 @@
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Timing Performance" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Performance with IOB Packing;/home/drichmond/Xilinx/14.7/ISE_DS/ISE/virtex6/data/virtex6_performance_with_iobpacking.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
@ -546,8 +546,8 @@
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
@ -568,16 +568,16 @@
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="riffa_wrapper_ml605" xil_pn:valueState="non-default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Package" xil_pn:value="ff1156" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="riffa_wrapper_ml605_map.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="riffa_wrapper_ml605_timesim.v" xil_pn:valueState="non-default"/>
@ -598,7 +598,7 @@
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
@ -681,7 +681,7 @@
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/home/drichmond/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
@ -731,7 +731,6 @@
<file xil_pn:name="../../../../../riffa_hdl/types.vh" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../../../../riffa_hdl/ultrascale.vh" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../../../../riffa_hdl/tlp.vh" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../../../../riffa_hdl/altera.vh" xil_pn:type=""/>
<file xil_pn:name="../../../../../riffa_hdl/xilinx.vh" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../../../../riffa_hdl/schedules.vh" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>