Updating 7V3 board for bug fixes, and adding preliminary support for new boards.

Added and tested the 7V3 and NetFPGA board projects. Added the KC705 board (Gen1
and Gen2, but haven't tested them)

fpga/xilinx/NetFPGA/NetFPGA_Gen1x8If64/constr/NetFPGA_Top.xdc

@@ -0,0 +1,212 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+#
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            NetFPGA_Top.xdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Xilinx Design Constraints for the NetFPGA board.
+# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin
+#
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+#
+#########################################################################################################################
+# User Constraints
+#########################################################################################################################
+
+###############################################################################
+# User Time Names / User Time Groups / Time Specs
+###############################################################################
+
+###############################################################################
+# User Physical Constraints
+###############################################################################
+
+set_property PACKAGE_PIN AR22 [get_ports {LED[0]}]
+set_property PACKAGE_PIN AR23 [get_ports {LED[1]}]
+
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[1]}]
+
+set_false_path -to [get_ports -filter NAME=~LED*]
+
+#########################################################################################################################
+# End User Constraints
+#########################################################################################################################
+#
+#
+#
+#########################################################################################################################
+# PCIE Core Constraints
+#########################################################################################################################
+
+# SYS reset (input) signal.  The sys_reset_n signal should be
+# obtained from the PCI Express interface if possible.  For
+# slot based form factors, a system reset signal is usually
+# present on the connector.  For cable based form factors, a
+# system reset signal may not be available.  In this case, the
+# system reset signal must be generated locally by some form of
+# supervisory circuit.  You may change the IOSTANDARD and LOC
+# to suit your requirements and VCCO voltage banking rules.
+# Some 7 series devices do not have 3.3 V I/Os available.
+# Therefore the appropriate level shift is required to operate
+# with these devices that contain only 1.8 V banks.
+
+set_property PACKAGE_PIN AY35 [get_ports PCIE_RESET_N]
+set_property IOSTANDARD LVCMOS15 [get_ports PCIE_RESET_N]
+set_property PULLUP true [get_ports PCIE_RESET_N]
+
+# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
+# signals are the PCI Express reference clock. Virtex-7 GT
+# Transceiver architecture requires the use of a dedicated clock
+# resources (FPGA input pins) associated with each GT Transceiver.
+# To use these pins an IBUFDS primitive (refclk_ibuf) is
+# instantiated in user's design.
+# Please refer to the Virtex-7 GT Transceiver User Guide
+# (UG) for guidelines regarding clock resource selection.
+set_property LOC IBUFDS_GTE2_X1Y11 [get_cells refclk_ibuf]
+
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O]
+
+###############################################################################
+# Physical Constraints
+###############################################################################
+
+set_false_path -from [get_ports PCIE_RESET_N]
+###############################################################################
+# End
+###############################################################################
+
+
+
+#set_property MARK_DEBUG true [get_nets {pcie3_7x_0_i/inst/cfg_interrupt_msi_int[0]}]
+#set_property MARK_DEBUG true [get_nets {pcie3_7x_0_i/inst/cfg_interrupt_msi_pending_status[0]}]
+#set_property MARK_DEBUG true [get_nets pcie3_7x_0_i/inst/cfg_interrupt_msi_fail]
+#set_property MARK_DEBUG true [get_nets pcie3_7x_0_i/inst/cfg_interrupt_msi_sent]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlRxDoneReady]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlRxLenValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlRxOfflastValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgRxAddrHiValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgRxAddrLoValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgRxLenValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgTxAddrHiValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgTxAddrLoValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgTxLenValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlTxDoneReady]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlTxLenReady]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wTransDoneRst]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/intr/cfg_interrupt_msi_fail]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/intr/cfg_interrupt_msi_sent]
+#set_property MARK_DEBUG true [get_nets {riffa/riffa_inst/intr/wIntrVectorReady[0]}]
+#set_property MARK_DEBUG true [get_nets {riffa/riffa_inst/intr/wIntrVectorReady[1]}]
+#set_property MARK_DEBUG true [get_nets riffa/txr_sent]
+#create_debug_core u_ila_0_0 ila
+#set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0_0]
+#set_property ALL_PROBE_SAME_MU_CNT 2 [get_debug_cores u_ila_0_0]
+#set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0_0]
+#set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0_0]
+#set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0_0]
+#set_property C_INPUT_PIPE_STAGES 2 [get_debug_cores u_ila_0_0]
+#set_property C_TRIGIN_EN false [get_debug_cores u_ila_0_0]
+#set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0_0]
+#set_property port_width 1 [get_debug_ports u_ila_0_0/clk]
+#connect_debug_port u_ila_0_0/clk [get_nets [list user_clk]]
+#set_property port_width 2 [get_debug_ports u_ila_0_0/probe0]
+#connect_debug_port u_ila_0_0/probe0 [get_nets [list {riffa/riffa_inst/intr/wIntrVectorReady[0]} {riffa/riffa_inst/intr/wIntrVectorReady[1]}]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe1]
+#connect_debug_port u_ila_0_0/probe1 [get_nets [list {pcie3_7x_0_i/inst/cfg_interrupt_msi_pending_status[0]}]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe2]
+#connect_debug_port u_ila_0_0/probe2 [get_nets [list {pcie3_7x_0_i/inst/cfg_interrupt_msi_int[0]}]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe3]
+#connect_debug_port u_ila_0_0/probe3 [get_nets [list riffa/riffa_inst/intr/cfg_interrupt_msi_fail]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe4]
+#connect_debug_port u_ila_0_0/probe4 [get_nets [list pcie3_7x_0_i/inst/cfg_interrupt_msi_fail]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe5]
+#connect_debug_port u_ila_0_0/probe5 [get_nets [list pcie3_7x_0_i/inst/cfg_interrupt_msi_sent]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe6]
+#connect_debug_port u_ila_0_0/probe6 [get_nets [list riffa/riffa_inst/intr/cfg_interrupt_msi_sent]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe7]
+#connect_debug_port u_ila_0_0/probe7 [get_nets [list riffa/txr_sent]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe8]
+#connect_debug_port u_ila_0_0/probe8 [get_nets [list riffa/riffa_inst/reg_inst/wChnlRxDoneReady]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe9]
+#connect_debug_port u_ila_0_0/probe9 [get_nets [list riffa/riffa_inst/reg_inst/wChnlRxLenValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe10]
+#connect_debug_port u_ila_0_0/probe10 [get_nets [list riffa/riffa_inst/reg_inst/wChnlRxOfflastValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe11]
+#connect_debug_port u_ila_0_0/probe11 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgRxAddrHiValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe12]
+#connect_debug_port u_ila_0_0/probe12 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgRxAddrLoValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe13]
+#connect_debug_port u_ila_0_0/probe13 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgRxLenValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe14]
+#connect_debug_port u_ila_0_0/probe14 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgTxAddrHiValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe15]
+#connect_debug_port u_ila_0_0/probe15 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgTxAddrLoValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe16]
+#connect_debug_port u_ila_0_0/probe16 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgTxLenValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe17]
+#connect_debug_port u_ila_0_0/probe17 [get_nets [list riffa/riffa_inst/reg_inst/wChnlTxDoneReady]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe18]
+#connect_debug_port u_ila_0_0/probe18 [get_nets [list riffa/riffa_inst/reg_inst/wChnlTxLenReady]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe19]
+#connect_debug_port u_ila_0_0/probe19 [get_nets [list riffa/riffa_inst/reg_inst/wTransDoneRst]]
+#set_property MARK_DEBUG true [get_nets riffa/engine_layer_inst/rx_engine_ultrascale_inst/RXR_DATA_VALID]
+#set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+#connect_debug_port dbg_hub/clk [get_nets user_clk]

fpga/xilinx/NetFPGA/NetFPGA_Gen1x8If64/hdl/NetFPGAGen1x8If64.v

@@ -0,0 +1,450 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            NetFPGAGen1x8If64.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Xilinx NetFPGA Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "ultrascale.vh"
+`timescale 1ps / 1ps
+module NetFPGAGen1x8If64
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 64,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 6) 
+    (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
+     output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXP,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXN,
+
+     output [1:0]                   LED,
+     input                          PCIE_REFCLK_P,
+     input                          PCIE_REFCLK_N,
+     input                          PCIE_RESET_N);
+
+    // Clocks, etc
+    wire                            user_lnk_up;
+    wire                            user_clk;
+    wire                            user_reset;
+    wire                            pcie_refclk;
+    wire                            pcie_reset_n;
+
+    // Interface: RQ (TXC)
+    wire                            s_axis_rq_tlast;
+    wire [C_PCI_DATA_WIDTH-1:0]     s_axis_rq_tdata;
+    wire [`SIG_RQ_TUSER_W-1:0]      s_axis_rq_tuser;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
+    wire                             s_axis_rq_tready;
+    wire                             s_axis_rq_tvalid;
+    // Interface: RC (RXC)
+    wire [C_PCI_DATA_WIDTH-1:0]      m_axis_rc_tdata;
+    wire [`SIG_RC_TUSER_W-1:0]       m_axis_rc_tuser;
+    wire                             m_axis_rc_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
+    wire                             m_axis_rc_tvalid;
+    wire                             m_axis_rc_tready;
+    // Interface: CQ (RXR)
+    wire [C_PCI_DATA_WIDTH-1:0]      m_axis_cq_tdata;
+    wire [`SIG_CQ_TUSER_W-1:0]       m_axis_cq_tuser;
+    wire                             m_axis_cq_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
+    wire                             m_axis_cq_tvalid;
+    wire                             m_axis_cq_tready;
+    // Interface: CC (TXC)
+    wire [C_PCI_DATA_WIDTH-1:0]      s_axis_cc_tdata;
+    wire [`SIG_CC_TUSER_W-1:0]       s_axis_cc_tuser;
+    wire                             s_axis_cc_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
+    wire                             s_axis_cc_tvalid;
+    wire                             s_axis_cc_tready;
+
+    // Configuration (CFG) Interface                                           
+    wire [3:0]                       pcie_rq_seq_num;
+    wire                             pcie_rq_seq_num_vld;
+    wire [5:0]                       pcie_rq_tag;
+    wire                             pcie_rq_tag_vld;
+    wire                             pcie_cq_np_req;
+    wire [5:0]                       pcie_cq_np_req_count;
+
+    wire                             cfg_phy_link_down;
+    wire [3:0]                       cfg_negotiated_width; // CONFIG_LINK_WIDTH
+    wire [2:0]                       cfg_current_speed; // CONFIG_LINK_RATE
+    wire [2:0]                       cfg_max_payload; // CONFIG_MAX_PAYLOAD
+    wire [2:0]                       cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
+    wire [7:0]                       cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
+    wire [5:0]                       cfg_function_power_state; // Ignorable but not removable
+    wire [11:0]                      cfg_vf_status; // Ignorable but not removable
+    wire [17:0]                      cfg_vf_power_state; // Ignorable but not removable
+    wire [1:0]                       cfg_link_power_state; // Ignorable but not removable
+
+    // Error Reporting Interface
+    wire                             cfg_err_cor_out;
+    wire                             cfg_err_nonfatal_out;
+    wire                             cfg_err_fatal_out;
+
+    wire                             cfg_ltr_enable;
+    wire [5:0]                       cfg_ltssm_state;
+    wire [1:0]                       cfg_rcb_status;
+    wire [1:0]                       cfg_dpa_substate_change;
+    wire [1:0]                       cfg_obff_enable;
+    wire                             cfg_pl_status_change;
+
+    wire [1:0]                       cfg_tph_requester_enable;
+    wire [5:0]                       cfg_tph_st_mode;
+    wire [5:0]                       cfg_vf_tph_requester_enable;
+    wire [17:0]                      cfg_vf_tph_st_mode;
+    wire [7:0]                       cfg_fc_ph;
+    wire [11:0]                      cfg_fc_pd;
+    wire [7:0]                       cfg_fc_nph;
+    wire [11:0]                      cfg_fc_npd;
+    wire [7:0]                       cfg_fc_cplh;
+    wire [11:0]                      cfg_fc_cpld;
+    wire [2:0]                       cfg_fc_sel;
+
+    // Interrupt Interface Signals
+    wire [3:0]                       cfg_interrupt_int;
+    wire [1:0]                       cfg_interrupt_pending;
+    wire                             cfg_interrupt_sent;
+    wire [1:0]                       cfg_interrupt_msi_enable;
+    wire [5:0]                       cfg_interrupt_msi_vf_enable;
+    wire [5:0]                       cfg_interrupt_msi_mmenable;
+    wire                             cfg_interrupt_msi_mask_update;
+    wire [31:0]                      cfg_interrupt_msi_data;
+    wire [3:0]                       cfg_interrupt_msi_select;
+    wire [31:0]                      cfg_interrupt_msi_int;
+    wire [63:0]                      cfg_interrupt_msi_pending_status;
+    wire                             cfg_interrupt_msi_sent;
+    wire                             cfg_interrupt_msi_fail;
+    wire [2:0]                       cfg_interrupt_msi_attr;
+    wire                             cfg_interrupt_msi_tph_present;
+    wire [1:0]                       cfg_interrupt_msi_tph_type;
+    wire [8:0]                       cfg_interrupt_msi_tph_st_tag;
+    wire [2:0]                       cfg_interrupt_msi_function_number;
+
+    wire                             rst_out;
+    wire [C_NUM_CHNL-1:0]            chnl_rx_clk; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx_ack; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_rx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_ren;
+
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_clk; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_tx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_ren;
+
+    genvar                                     chnl;
+
+    IBUF 
+        #()  
+    pci_reset_n_ibuf 
+        (.O(pcie_reset_n), 
+         .I(PCIE_RESET_N));
+
+    IBUFDS_GTE2 
+        #()
+    refclk_ibuf 
+        (.O(pcie_refclk), 
+         .ODIV2(), 
+         .I(PCIE_REFCLK_P), 
+         .CEB(1'b0), 
+         .IB(PCIE_REFCLK_N));
+
+    OBUF 
+        #() 
+    led_0_obuf 
+        (.O(LED[0]),
+         .I(cfg_ltssm_state[0]));
+    OBUF 
+        #() 
+    led_1_obuf 
+        (.O(LED[1]),
+         .I(cfg_ltssm_state[1]));
+
+    // Core Top Level Wrapper
+    PCIeGen1x8If64  
+        #()
+    pcie3_7x_0_i 
+        (//---------------------------------------------------------------------
+         //  PCI Express (pci_exp) Interface                                    
+         //---------------------------------------------------------------------
+         .pci_exp_txn                                    ( PCI_EXP_TXN ),
+         .pci_exp_txp                                    ( PCI_EXP_TXP ),
+         .pci_exp_rxn                                    ( PCI_EXP_RXN ),
+         .pci_exp_rxp                                    ( PCI_EXP_RXP ),
+
+         //---------------------------------------------------------------------
+         //  AXI Interface                                                      
+         //---------------------------------------------------------------------
+         .user_clk                                       ( user_clk ),
+         .user_reset                                     ( user_reset ),
+         .user_lnk_up                                    ( user_lnk_up ),
+         .user_app_rdy                                   ( ),
+
+         .s_axis_rq_tlast                                ( s_axis_rq_tlast ),
+         .s_axis_rq_tdata                                ( s_axis_rq_tdata ),
+         .s_axis_rq_tuser                                ( s_axis_rq_tuser ),
+         .s_axis_rq_tkeep                                ( s_axis_rq_tkeep ),
+         .s_axis_rq_tready                               ( s_axis_rq_tready ),
+         .s_axis_rq_tvalid                               ( s_axis_rq_tvalid ),
+
+         .m_axis_rc_tdata                                ( m_axis_rc_tdata ),
+         .m_axis_rc_tuser                                ( m_axis_rc_tuser ),
+         .m_axis_rc_tlast                                ( m_axis_rc_tlast ),
+         .m_axis_rc_tkeep                                ( m_axis_rc_tkeep ),
+         .m_axis_rc_tvalid                               ( m_axis_rc_tvalid ),
+         .m_axis_rc_tready                               ( {22{m_axis_rc_tready}} ),
+
+         .m_axis_cq_tdata                                ( m_axis_cq_tdata ),
+         .m_axis_cq_tuser                                ( m_axis_cq_tuser ),
+         .m_axis_cq_tlast                                ( m_axis_cq_tlast ),
+         .m_axis_cq_tkeep                                ( m_axis_cq_tkeep ),
+         .m_axis_cq_tvalid                               ( m_axis_cq_tvalid ),
+         .m_axis_cq_tready                               ( {22{m_axis_cq_tready}} ),
+
+         .s_axis_cc_tdata                                ( s_axis_cc_tdata ),
+         .s_axis_cc_tuser                                ( s_axis_cc_tuser ),
+         .s_axis_cc_tlast                                ( s_axis_cc_tlast ),
+         .s_axis_cc_tkeep                                ( s_axis_cc_tkeep ),
+         .s_axis_cc_tvalid                               ( s_axis_cc_tvalid ),
+         .s_axis_cc_tready                               ( s_axis_cc_tready ),
+
+         //---------------------------------------------------------------------
+         //  Configuration (CFG) Interface                                      
+         //---------------------------------------------------------------------
+         .pcie_rq_seq_num                                ( pcie_rq_seq_num ),
+         .pcie_rq_seq_num_vld                            ( pcie_rq_seq_num_vld ),
+         .pcie_rq_tag                                    ( pcie_rq_tag ),
+         .pcie_rq_tag_vld                                ( pcie_rq_tag_vld ),
+         .pcie_cq_np_req                                 ( pcie_cq_np_req ),
+         .pcie_cq_np_req_count                           ( pcie_cq_np_req_count ),
+         .cfg_phy_link_down                              ( cfg_phy_link_down ),
+         .cfg_phy_link_status                            ( cfg_phy_link_status),
+         .cfg_negotiated_width                           ( cfg_negotiated_width ),
+         .cfg_current_speed                              ( cfg_current_speed ),
+         .cfg_max_payload                                ( cfg_max_payload ),
+         .cfg_max_read_req                               ( cfg_max_read_req ),
+         .cfg_function_status                            ( cfg_function_status ),
+         .cfg_function_power_state                       ( cfg_function_power_state ),
+         .cfg_vf_status                                  ( cfg_vf_status ),
+         .cfg_vf_power_state                             ( cfg_vf_power_state ),
+         .cfg_link_power_state                           ( cfg_link_power_state ),
+         // Error Reporting Interface
+         .cfg_err_cor_out                                ( cfg_err_cor_out ),
+         .cfg_err_nonfatal_out                           ( cfg_err_nonfatal_out ),
+         .cfg_err_fatal_out                              ( cfg_err_fatal_out ),
+         .cfg_ltr_enable                                 ( cfg_ltr_enable ),
+         .cfg_ltssm_state                                ( cfg_ltssm_state ),
+         .cfg_rcb_status                                 ( cfg_rcb_status ),
+         .cfg_dpa_substate_change                        ( cfg_dpa_substate_change ),
+         .cfg_obff_enable                                ( cfg_obff_enable ),
+         .cfg_pl_status_change                           ( cfg_pl_status_change ),
+         .cfg_tph_requester_enable                       ( cfg_tph_requester_enable ),
+         .cfg_tph_st_mode                                ( cfg_tph_st_mode ),
+         .cfg_vf_tph_requester_enable                    ( cfg_vf_tph_requester_enable ),
+         .cfg_vf_tph_st_mode                             ( cfg_vf_tph_st_mode ),
+         .cfg_fc_ph                                      ( cfg_fc_ph ),
+         .cfg_fc_pd                                      ( cfg_fc_pd ),
+         .cfg_fc_nph                                     ( cfg_fc_nph ),
+         .cfg_fc_npd                                     ( cfg_fc_npd ),
+         .cfg_fc_cplh                                    ( cfg_fc_cplh ),
+         .cfg_fc_cpld                                    ( cfg_fc_cpld ),
+         .cfg_fc_sel                                     ( cfg_fc_sel ),
+         //---------------------------------------------------------------------
+         // EP Only                                                             
+         //---------------------------------------------------------------------
+         // Interrupt Interface Signals
+         .cfg_interrupt_int                              ( cfg_interrupt_int ),
+         .cfg_interrupt_pending                          ( cfg_interrupt_pending ),
+         .cfg_interrupt_sent                             ( cfg_interrupt_sent ),
+         .cfg_interrupt_msi_enable                       ( cfg_interrupt_msi_enable ),
+         .cfg_interrupt_msi_vf_enable                    ( cfg_interrupt_msi_vf_enable ),
+         .cfg_interrupt_msi_mmenable                     ( cfg_interrupt_msi_mmenable ),
+         .cfg_interrupt_msi_mask_update                  ( cfg_interrupt_msi_mask_update ),
+         .cfg_interrupt_msi_data                         ( cfg_interrupt_msi_data ),
+         .cfg_interrupt_msi_select                       ( cfg_interrupt_msi_select ),
+         .cfg_interrupt_msi_int                          ( cfg_interrupt_msi_int ),
+         .cfg_interrupt_msi_pending_status               ( cfg_interrupt_msi_pending_status ),
+         .cfg_interrupt_msi_sent                         ( cfg_interrupt_msi_sent ),
+         .cfg_interrupt_msi_fail                         ( cfg_interrupt_msi_fail ),
+         .cfg_interrupt_msi_attr                         ( cfg_interrupt_msi_attr ),
+         .cfg_interrupt_msi_tph_present                  ( cfg_interrupt_msi_tph_present ),
+         .cfg_interrupt_msi_tph_type                     ( cfg_interrupt_msi_tph_type ),
+         .cfg_interrupt_msi_tph_st_tag                   ( cfg_interrupt_msi_tph_st_tag ),
+         .cfg_interrupt_msi_function_number              ( cfg_interrupt_msi_function_number ),
+
+         //---------------------------------------------------------------------
+         //  System(SYS) Interface                                              
+         //---------------------------------------------------------------------
+         .sys_clk                                        (pcie_refclk),
+         .sys_reset                                      (~pcie_reset_n));
+
+    riffa_wrapper_NetFPGA
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (// Outputs
+         .M_AXIS_CQ_TREADY              (m_axis_cq_tready),
+         .M_AXIS_RC_TREADY              (m_axis_rc_tready),
+         .S_AXIS_CC_TVALID              (s_axis_cc_tvalid),
+         .S_AXIS_CC_TLAST               (s_axis_cc_tlast),
+         .S_AXIS_CC_TDATA               (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (s_axis_rq_tvalid),
+         .S_AXIS_RQ_TLAST               (s_axis_rq_tlast),
+         .S_AXIS_RQ_TDATA               (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
+         .USER_CLK                      (user_clk),
+         .USER_RESET                    (user_reset),
+         .CFG_INTERRUPT_INT             (cfg_interrupt_int[3:0]),
+         .CFG_INTERRUPT_PENDING         (cfg_interrupt_pending[1:0]),
+         .CFG_INTERRUPT_MSI_SELECT      (cfg_interrupt_msi_select[3:0]),
+         .CFG_INTERRUPT_MSI_INT         (cfg_interrupt_msi_int[31:0]),
+         .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
+         .CFG_INTERRUPT_MSI_ATTR        (cfg_interrupt_msi_attr[2:0]),
+         .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
+         .CFG_INTERRUPT_MSI_TPH_TYPE    (cfg_interrupt_msi_tph_type[1:0]),
+         .CFG_INTERRUPT_MSI_TPH_ST_TAG  (cfg_interrupt_msi_tph_st_tag[8:0]),
+         .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
+         .CFG_FC_SEL                    (cfg_fc_sel[2:0]),
+         .PCIE_CQ_NP_REQ                (pcie_cq_np_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (m_axis_cq_tvalid),
+         .M_AXIS_CQ_TLAST               (m_axis_cq_tlast),
+         .M_AXIS_CQ_TDATA               (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (m_axis_rc_tvalid),
+         .M_AXIS_RC_TLAST               (m_axis_rc_tlast),
+         .M_AXIS_RC_TDATA               (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (s_axis_cc_tready),
+         .S_AXIS_RQ_TREADY              (s_axis_rq_tready),
+         .CFG_INTERRUPT_MSI_ENABLE      (cfg_interrupt_msi_enable[1:0]),
+         .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
+         .CFG_INTERRUPT_MSI_DATA        (cfg_interrupt_msi_data[31:0]),
+         .CFG_INTERRUPT_MSI_SENT        (cfg_interrupt_msi_sent),
+         .CFG_INTERRUPT_MSI_FAIL        (cfg_interrupt_msi_fail),
+         .CFG_FC_CPLH                   (cfg_fc_cplh[7:0]),
+         .CFG_FC_CPLD                   (cfg_fc_cpld[11:0]),
+         .CFG_NEGOTIATED_WIDTH          (cfg_negotiated_width[3:0]),
+         .CFG_CURRENT_SPEED             (cfg_current_speed[2:0]),
+         .CFG_MAX_PAYLOAD               (cfg_max_payload[2:0]),
+         .CFG_MAX_READ_REQ              (cfg_max_read_req[2:0]),
+         .CFG_FUNCTION_STATUS           (cfg_function_status[7:0]),
+         .CFG_RCB_STATUS                (cfg_rcb_status[1:0]),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0])
+         /*AUTOINST*/);
+
+    generate
+        for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
+            chnl_tester 
+                    #(/*AUTOINSTPARAM*/
+                      // Parameters
+                      .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH)) 
+            module1 
+                    (.CLK(user_clk),
+                     .RST(rst_out),    // riffa_reset includes riffa_endpoint resets
+                     // Rx interface
+                     .CHNL_RX_CLK(chnl_rx_clk[chnl]), 
+                     .CHNL_RX(chnl_rx[chnl]), 
+                     .CHNL_RX_ACK(chnl_rx_ack[chnl]), 
+                     .CHNL_RX_LAST(chnl_rx_last[chnl]), 
+                     .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), 
+                     .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), 
+                     .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), 
+                     .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
+                     // Tx interface
+                     .CHNL_TX_CLK(chnl_tx_clk[chnl]), 
+                     .CHNL_TX(chnl_tx[chnl]), 
+                     .CHNL_TX_ACK(chnl_tx_ack[chnl]), 
+                     .CHNL_TX_LAST(chnl_tx_last[chnl]), 
+                     .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), 
+                     .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), 
+                     .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), 
+                     .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
+                     /*AUTOINST*/);    
+        end
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("../../../../riffa_hdl/" "../../")
+// End:
+

fpga/xilinx/NetFPGA/NetFPGA_Gen1x8If64/ip/PCIeGen1x8If64.xci

@@ -0,0 +1,677 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>PCIeGen1x8If64</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie3_7x" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.device_port_type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xlnx_ref_board">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xlnx_ref_board">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">2.5_GT/s</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">X8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXISTEN_IF_RC_STRADDLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_client_tag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_CLASS_CODE">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEVICE_ID">7018</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_OBFF_SUPPORT">00_Not_Supported</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_REVISION_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_CLASS_CODE">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_DEVICE_ID">7011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_REVISION_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_VER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK">0001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_pf0_enable_reg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TL_PF_ENABLE_REG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">PCIeGen1x8If128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_vc_cap_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_blk_locn">X0Y1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_pb_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pb_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.alignment_mode">DWORD_Aligned</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_rev">Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dev_cap_max_payload">512_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_tphr_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sub_class_interface_menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.extended_tag_field">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_ari_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vendor_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_tphr_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_aer_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dsn_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_cap_ver">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msi_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dpa_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_pcie_cfg_space_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ari_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.perf_level">Extreme</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_width">64_bit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_aer_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dsn_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msi_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dpa_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dev_cap_max_payload">512_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ltr_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Advanced</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.shared_logic_in_core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_gt_common">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tx_fc_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_fc_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ext_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_status_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.per_func_status_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_mgmt_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rcv_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_tx_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ctl_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pcie_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_pipe_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_msi_per_vec_masking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_startup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tandem_mode">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_freq">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.aspm_support">No_ASPM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE_EXT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_msg_route">2FFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_rx_msg_intfc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_mode_sim">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_powerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USER_CLK2_FREQ">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_CAP_ASPM_SUPPORT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.REF_CLK_FREQ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_LINK_SPEED">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ARI_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXT_FUNC">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CQ_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_STRADDLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RQ_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_CHECK_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_GEN_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR0_APERTURE_SIZE">0b00011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR0_CONTROL">0b100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR1_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR1_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR2_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR2_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR3_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR3_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR4_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR4_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR5_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR5_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_CLASS_CODE">0x058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_VENDOR_ID">0x10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEVICE_ID">0x7018</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_LTR_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_OBFF_SUPPORT">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_EXT_TAG_SUPPORTED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_MAX_PAYLOAD_SIZE">0b010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DSN_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_INTERRUPT_PIN">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LTR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSI_CAP_NEXTPTR">0xC0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PB_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_NEXTPTR">0x90</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE0">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE1">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE2">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE0">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE1">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE2">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_REVISION_ID">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR0_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR0_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR1_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR1_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR2_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR2_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR3_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR3_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR4_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR4_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR5_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR5_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_TOTAL_VF">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_VER">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">0x00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID">0x10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SUBSYSTEM_ID">0x0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_VC_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SPARE_WORD1">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_ECRC_CHECK_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_ECRC_GEN_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR0_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR1_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR1_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR2_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR2_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR3_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR3_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR4_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR4_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR5_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR5_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DSN_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_INTERRUPT_PIN">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PB_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_REVISION_ID">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR0_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR0_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR1_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR2_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR2_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR3_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR3_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR4_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR4_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR5_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR5_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_TOTAL_VF">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_VER">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK">0x0001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE">0x00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SUBSYSTEM_ID">0x0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_UPSTREAM_FACING">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SRIOV_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_CD">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_CH">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_NPD">0x028</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_NPH">0x20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_PD">0x198</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_PH">0x20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_LEGACY_MODE_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_PF_ENABLE_REG">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_PM_CAP_NEXTPTR">&quot;00000000&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_PM_CAP_NEXTPTR">&quot;00000000&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_PM_CAP_NEXTPTR">&quot;00000000&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_PM_CAP_NEXTPTR">&quot;00000000&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_PM_CAP_NEXTPTR">&quot;00000000&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_PM_CAP_NEXTPTR">&quot;00000000&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.COMPLETION_SPACE">16KB</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y0_ucf">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y3_ucf">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y2_ucf">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y1_ucf">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_revision">Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.xlnx_ref_board">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_blk_locn">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SHARED_LOGIC_IN_CORE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PIPE_SIM">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MSI_EN">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MSIX_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_EXT_CLK">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_EXT_GT_COMMON">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_CH_GT_DRP">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_STATUS_IF">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TX_FC_IF">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_EXT_IF">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_FC_IF">TRUE</spirit:configurableElementValue>
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+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxr_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxr_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxc_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxc_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue_output.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue_input.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/interrupt_controller.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/demux.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel_64.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel_32.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel_128.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxc_engine_128.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxr_engine_128.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_multiplexer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rx_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rx_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/riffa.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/registers.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/recv_credit_flow_ctrl.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/interrupt.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/riffa.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/engine_layer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/chnl_tester.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../riffa_wrapper_NetFPGA.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../hdl/NetFPGAGen1x8If64.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../hdl/NetFPGAGen1x8If128.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/xilinx.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/altera.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="NetFPGAGen1x8If64"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../constr/NetFPGA_Top.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/NetFPGA_Top.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="NetFPGAGen1x8If64"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="PCIeGen1x8If64" Type="BlockSrcs" RelSrcDir="$PSRCDIR/PCIeGen1x8If64">
+      <File Path="$PPRDIR/../ip/PCIeGen1x8If64.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="PCIeGen1x8If64"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="9">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx690tffg1761-3" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen1x8If64_synth_1" Type="Ft3:Synth" SrcSet="PCIeGen1x8If64" Part="xc7vx690tffg1761-3" ConstrsSet="PCIeGen1x8If64" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/PCIeGen1x8If64_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1761-3" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen1x8If64_impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1761-3" ConstrsSet="PCIeGen1x8If64" Description="Vivado Implementation Defaults" SynthRun="PCIeGen1x8If64_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
+          <Desc>Vivado Implementation Defaults</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+  </Runs>
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</Project>

fpga/xilinx/NetFPGA/NetFPGA_Gen2x8If128/constr/NetFPGA_Top.xdc

@@ -0,0 +1,212 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+#
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            NetFPGA_Top.xdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Xilinx Design Constraints for the NetFPGA board.
+# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin
+#
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+#
+#########################################################################################################################
+# User Constraints
+#########################################################################################################################
+
+###############################################################################
+# User Time Names / User Time Groups / Time Specs
+###############################################################################
+
+###############################################################################
+# User Physical Constraints
+###############################################################################
+
+set_property PACKAGE_PIN AR22 [get_ports {LED[0]}]
+set_property PACKAGE_PIN AR23 [get_ports {LED[1]}]
+
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[1]}]
+
+set_false_path -to [get_ports -filter NAME=~LED*]
+
+#########################################################################################################################
+# End User Constraints
+#########################################################################################################################
+#
+#
+#
+#########################################################################################################################
+# PCIE Core Constraints
+#########################################################################################################################
+
+# SYS reset (input) signal.  The sys_reset_n signal should be
+# obtained from the PCI Express interface if possible.  For
+# slot based form factors, a system reset signal is usually
+# present on the connector.  For cable based form factors, a
+# system reset signal may not be available.  In this case, the
+# system reset signal must be generated locally by some form of
+# supervisory circuit.  You may change the IOSTANDARD and LOC
+# to suit your requirements and VCCO voltage banking rules.
+# Some 7 series devices do not have 3.3 V I/Os available.
+# Therefore the appropriate level shift is required to operate
+# with these devices that contain only 1.8 V banks.
+
+set_property PACKAGE_PIN AY35 [get_ports PCIE_RESET_N]
+set_property IOSTANDARD LVCMOS15 [get_ports PCIE_RESET_N]
+set_property PULLUP true [get_ports PCIE_RESET_N]
+
+# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
+# signals are the PCI Express reference clock. Virtex-7 GT
+# Transceiver architecture requires the use of a dedicated clock
+# resources (FPGA input pins) associated with each GT Transceiver.
+# To use these pins an IBUFDS primitive (refclk_ibuf) is
+# instantiated in user's design.
+# Please refer to the Virtex-7 GT Transceiver User Guide
+# (UG) for guidelines regarding clock resource selection.
+set_property LOC IBUFDS_GTE2_X1Y11 [get_cells refclk_ibuf]
+
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O]
+
+###############################################################################
+# Physical Constraints
+###############################################################################
+
+set_false_path -from [get_ports PCIE_RESET_N]
+###############################################################################
+# End
+###############################################################################
+
+
+
+#set_property MARK_DEBUG true [get_nets {pcie3_7x_0_i/inst/cfg_interrupt_msi_int[0]}]
+#set_property MARK_DEBUG true [get_nets {pcie3_7x_0_i/inst/cfg_interrupt_msi_pending_status[0]}]
+#set_property MARK_DEBUG true [get_nets pcie3_7x_0_i/inst/cfg_interrupt_msi_fail]
+#set_property MARK_DEBUG true [get_nets pcie3_7x_0_i/inst/cfg_interrupt_msi_sent]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlRxDoneReady]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlRxLenValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlRxOfflastValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgRxAddrHiValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgRxAddrLoValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgRxLenValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgTxAddrHiValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgTxAddrLoValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgTxLenValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlTxDoneReady]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlTxLenReady]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wTransDoneRst]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/intr/cfg_interrupt_msi_fail]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/intr/cfg_interrupt_msi_sent]
+#set_property MARK_DEBUG true [get_nets {riffa/riffa_inst/intr/wIntrVectorReady[0]}]
+#set_property MARK_DEBUG true [get_nets {riffa/riffa_inst/intr/wIntrVectorReady[1]}]
+#set_property MARK_DEBUG true [get_nets riffa/txr_sent]
+#create_debug_core u_ila_0_0 ila
+#set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0_0]
+#set_property ALL_PROBE_SAME_MU_CNT 2 [get_debug_cores u_ila_0_0]
+#set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0_0]
+#set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0_0]
+#set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0_0]
+#set_property C_INPUT_PIPE_STAGES 2 [get_debug_cores u_ila_0_0]
+#set_property C_TRIGIN_EN false [get_debug_cores u_ila_0_0]
+#set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0_0]
+#set_property port_width 1 [get_debug_ports u_ila_0_0/clk]
+#connect_debug_port u_ila_0_0/clk [get_nets [list user_clk]]
+#set_property port_width 2 [get_debug_ports u_ila_0_0/probe0]
+#connect_debug_port u_ila_0_0/probe0 [get_nets [list {riffa/riffa_inst/intr/wIntrVectorReady[0]} {riffa/riffa_inst/intr/wIntrVectorReady[1]}]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe1]
+#connect_debug_port u_ila_0_0/probe1 [get_nets [list {pcie3_7x_0_i/inst/cfg_interrupt_msi_pending_status[0]}]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe2]
+#connect_debug_port u_ila_0_0/probe2 [get_nets [list {pcie3_7x_0_i/inst/cfg_interrupt_msi_int[0]}]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe3]
+#connect_debug_port u_ila_0_0/probe3 [get_nets [list riffa/riffa_inst/intr/cfg_interrupt_msi_fail]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe4]
+#connect_debug_port u_ila_0_0/probe4 [get_nets [list pcie3_7x_0_i/inst/cfg_interrupt_msi_fail]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe5]
+#connect_debug_port u_ila_0_0/probe5 [get_nets [list pcie3_7x_0_i/inst/cfg_interrupt_msi_sent]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe6]
+#connect_debug_port u_ila_0_0/probe6 [get_nets [list riffa/riffa_inst/intr/cfg_interrupt_msi_sent]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe7]
+#connect_debug_port u_ila_0_0/probe7 [get_nets [list riffa/txr_sent]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe8]
+#connect_debug_port u_ila_0_0/probe8 [get_nets [list riffa/riffa_inst/reg_inst/wChnlRxDoneReady]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe9]
+#connect_debug_port u_ila_0_0/probe9 [get_nets [list riffa/riffa_inst/reg_inst/wChnlRxLenValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe10]
+#connect_debug_port u_ila_0_0/probe10 [get_nets [list riffa/riffa_inst/reg_inst/wChnlRxOfflastValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe11]
+#connect_debug_port u_ila_0_0/probe11 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgRxAddrHiValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe12]
+#connect_debug_port u_ila_0_0/probe12 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgRxAddrLoValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe13]
+#connect_debug_port u_ila_0_0/probe13 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgRxLenValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe14]
+#connect_debug_port u_ila_0_0/probe14 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgTxAddrHiValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe15]
+#connect_debug_port u_ila_0_0/probe15 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgTxAddrLoValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe16]
+#connect_debug_port u_ila_0_0/probe16 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgTxLenValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe17]
+#connect_debug_port u_ila_0_0/probe17 [get_nets [list riffa/riffa_inst/reg_inst/wChnlTxDoneReady]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe18]
+#connect_debug_port u_ila_0_0/probe18 [get_nets [list riffa/riffa_inst/reg_inst/wChnlTxLenReady]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe19]
+#connect_debug_port u_ila_0_0/probe19 [get_nets [list riffa/riffa_inst/reg_inst/wTransDoneRst]]
+#set_property MARK_DEBUG true [get_nets riffa/engine_layer_inst/rx_engine_ultrascale_inst/RXR_DATA_VALID]
+#set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+#connect_debug_port dbg_hub/clk [get_nets user_clk]

fpga/xilinx/NetFPGA/NetFPGA_Gen2x8If128/hdl/NetFPGAGen2x8If128.v

@@ -0,0 +1,450 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            NetFPGAGen2x8If128.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Xilinx NetFPGA Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "ultrascale.vh"
+`timescale 1ps / 1ps
+module NetFPGAGen2x8If128
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 6) 
+    (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
+     output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXP,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXN,
+
+     output [1:0]                   LED,
+     input                          PCIE_REFCLK_P,
+     input                          PCIE_REFCLK_N,
+     input                          PCIE_RESET_N);
+
+    // Clocks, etc
+    wire                            user_lnk_up;
+    wire                            user_clk;
+    wire                            user_reset;
+    wire                            pcie_refclk;
+    wire                            pcie_reset_n;
+
+    // Interface: RQ (TXC)
+    wire                            s_axis_rq_tlast;
+    wire [C_PCI_DATA_WIDTH-1:0]     s_axis_rq_tdata;
+    wire [`SIG_RQ_TUSER_W-1:0]      s_axis_rq_tuser;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
+    wire                             s_axis_rq_tready;
+    wire                             s_axis_rq_tvalid;
+    // Interface: RC (RXC)
+    wire [C_PCI_DATA_WIDTH-1:0]      m_axis_rc_tdata;
+    wire [`SIG_RC_TUSER_W-1:0]       m_axis_rc_tuser;
+    wire                             m_axis_rc_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
+    wire                             m_axis_rc_tvalid;
+    wire                             m_axis_rc_tready;
+    // Interface: CQ (RXR)
+    wire [C_PCI_DATA_WIDTH-1:0]      m_axis_cq_tdata;
+    wire [`SIG_CQ_TUSER_W-1:0]       m_axis_cq_tuser;
+    wire                             m_axis_cq_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
+    wire                             m_axis_cq_tvalid;
+    wire                             m_axis_cq_tready;
+    // Interface: CC (TXC)
+    wire [C_PCI_DATA_WIDTH-1:0]      s_axis_cc_tdata;
+    wire [`SIG_CC_TUSER_W-1:0]       s_axis_cc_tuser;
+    wire                             s_axis_cc_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
+    wire                             s_axis_cc_tvalid;
+    wire                             s_axis_cc_tready;
+
+    // Configuration (CFG) Interface                                           
+    wire [3:0]                       pcie_rq_seq_num;
+    wire                             pcie_rq_seq_num_vld;
+    wire [5:0]                       pcie_rq_tag;
+    wire                             pcie_rq_tag_vld;
+    wire                             pcie_cq_np_req;
+    wire [5:0]                       pcie_cq_np_req_count;
+
+    wire                             cfg_phy_link_down;
+    wire [3:0]                       cfg_negotiated_width; // CONFIG_LINK_WIDTH
+    wire [2:0]                       cfg_current_speed; // CONFIG_LINK_RATE
+    wire [2:0]                       cfg_max_payload; // CONFIG_MAX_PAYLOAD
+    wire [2:0]                       cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
+    wire [7:0]                       cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
+    wire [5:0]                       cfg_function_power_state; // Ignorable but not removable
+    wire [11:0]                      cfg_vf_status; // Ignorable but not removable
+    wire [17:0]                      cfg_vf_power_state; // Ignorable but not removable
+    wire [1:0]                       cfg_link_power_state; // Ignorable but not removable
+
+    // Error Reporting Interface
+    wire                             cfg_err_cor_out;
+    wire                             cfg_err_nonfatal_out;
+    wire                             cfg_err_fatal_out;
+
+    wire                             cfg_ltr_enable;
+    wire [5:0]                       cfg_ltssm_state;
+    wire [1:0]                       cfg_rcb_status;
+    wire [1:0]                       cfg_dpa_substate_change;
+    wire [1:0]                       cfg_obff_enable;
+    wire                             cfg_pl_status_change;
+
+    wire [1:0]                       cfg_tph_requester_enable;
+    wire [5:0]                       cfg_tph_st_mode;
+    wire [5:0]                       cfg_vf_tph_requester_enable;
+    wire [17:0]                      cfg_vf_tph_st_mode;
+    wire [7:0]                       cfg_fc_ph;
+    wire [11:0]                      cfg_fc_pd;
+    wire [7:0]                       cfg_fc_nph;
+    wire [11:0]                      cfg_fc_npd;
+    wire [7:0]                       cfg_fc_cplh;
+    wire [11:0]                      cfg_fc_cpld;
+    wire [2:0]                       cfg_fc_sel;
+
+    // Interrupt Interface Signals
+    wire [3:0]                       cfg_interrupt_int;
+    wire [1:0]                       cfg_interrupt_pending;
+    wire                             cfg_interrupt_sent;
+    wire [1:0]                       cfg_interrupt_msi_enable;
+    wire [5:0]                       cfg_interrupt_msi_vf_enable;
+    wire [5:0]                       cfg_interrupt_msi_mmenable;
+    wire                             cfg_interrupt_msi_mask_update;
+    wire [31:0]                      cfg_interrupt_msi_data;
+    wire [3:0]                       cfg_interrupt_msi_select;
+    wire [31:0]                      cfg_interrupt_msi_int;
+    wire [63:0]                      cfg_interrupt_msi_pending_status;
+    wire                             cfg_interrupt_msi_sent;
+    wire                             cfg_interrupt_msi_fail;
+    wire [2:0]                       cfg_interrupt_msi_attr;
+    wire                             cfg_interrupt_msi_tph_present;
+    wire [1:0]                       cfg_interrupt_msi_tph_type;
+    wire [8:0]                       cfg_interrupt_msi_tph_st_tag;
+    wire [2:0]                       cfg_interrupt_msi_function_number;
+
+    wire                             rst_out;
+    wire [C_NUM_CHNL-1:0]            chnl_rx_clk; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx_ack; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_rx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_ren;
+
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_clk; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_tx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_ren;
+
+    genvar                                     chnl;
+
+    IBUF 
+        #()  
+    pci_reset_n_ibuf 
+        (.O(pcie_reset_n), 
+         .I(PCIE_RESET_N));
+
+    IBUFDS_GTE2 
+        #()
+    refclk_ibuf 
+        (.O(pcie_refclk), 
+         .ODIV2(), 
+         .I(PCIE_REFCLK_P), 
+         .CEB(1'b0), 
+         .IB(PCIE_REFCLK_N));
+
+    OBUF 
+        #() 
+    led_0_obuf 
+        (.O(LED[0]),
+         .I(cfg_ltssm_state[0]));
+    OBUF 
+        #() 
+    led_1_obuf 
+        (.O(LED[1]),
+         .I(cfg_ltssm_state[1]));
+
+    // Core Top Level Wrapper
+    PCIeGen2x8If128  
+        #()
+    pcie3_7x_0_i 
+        (//---------------------------------------------------------------------
+         //  PCI Express (pci_exp) Interface                                    
+         //---------------------------------------------------------------------
+         .pci_exp_txn                                    ( PCI_EXP_TXN ),
+         .pci_exp_txp                                    ( PCI_EXP_TXP ),
+         .pci_exp_rxn                                    ( PCI_EXP_RXN ),
+         .pci_exp_rxp                                    ( PCI_EXP_RXP ),
+
+         //---------------------------------------------------------------------
+         //  AXI Interface                                                      
+         //---------------------------------------------------------------------
+         .user_clk                                       ( user_clk ),
+         .user_reset                                     ( user_reset ),
+         .user_lnk_up                                    ( user_lnk_up ),
+         .user_app_rdy                                   ( ),
+
+         .s_axis_rq_tlast                                ( s_axis_rq_tlast ),
+         .s_axis_rq_tdata                                ( s_axis_rq_tdata ),
+         .s_axis_rq_tuser                                ( s_axis_rq_tuser ),
+         .s_axis_rq_tkeep                                ( s_axis_rq_tkeep ),
+         .s_axis_rq_tready                               ( s_axis_rq_tready ),
+         .s_axis_rq_tvalid                               ( s_axis_rq_tvalid ),
+
+         .m_axis_rc_tdata                                ( m_axis_rc_tdata ),
+         .m_axis_rc_tuser                                ( m_axis_rc_tuser ),
+         .m_axis_rc_tlast                                ( m_axis_rc_tlast ),
+         .m_axis_rc_tkeep                                ( m_axis_rc_tkeep ),
+         .m_axis_rc_tvalid                               ( m_axis_rc_tvalid ),
+         .m_axis_rc_tready                               ( {22{m_axis_rc_tready}} ),
+
+         .m_axis_cq_tdata                                ( m_axis_cq_tdata ),
+         .m_axis_cq_tuser                                ( m_axis_cq_tuser ),
+         .m_axis_cq_tlast                                ( m_axis_cq_tlast ),
+         .m_axis_cq_tkeep                                ( m_axis_cq_tkeep ),
+         .m_axis_cq_tvalid                               ( m_axis_cq_tvalid ),
+         .m_axis_cq_tready                               ( {22{m_axis_cq_tready}} ),
+
+         .s_axis_cc_tdata                                ( s_axis_cc_tdata ),
+         .s_axis_cc_tuser                                ( s_axis_cc_tuser ),
+         .s_axis_cc_tlast                                ( s_axis_cc_tlast ),
+         .s_axis_cc_tkeep                                ( s_axis_cc_tkeep ),
+         .s_axis_cc_tvalid                               ( s_axis_cc_tvalid ),
+         .s_axis_cc_tready                               ( s_axis_cc_tready ),
+
+         //---------------------------------------------------------------------
+         //  Configuration (CFG) Interface                                      
+         //---------------------------------------------------------------------
+         .pcie_rq_seq_num                                ( pcie_rq_seq_num ),
+         .pcie_rq_seq_num_vld                            ( pcie_rq_seq_num_vld ),
+         .pcie_rq_tag                                    ( pcie_rq_tag ),
+         .pcie_rq_tag_vld                                ( pcie_rq_tag_vld ),
+         .pcie_cq_np_req                                 ( pcie_cq_np_req ),
+         .pcie_cq_np_req_count                           ( pcie_cq_np_req_count ),
+         .cfg_phy_link_down                              ( cfg_phy_link_down ),
+         .cfg_phy_link_status                            ( cfg_phy_link_status),
+         .cfg_negotiated_width                           ( cfg_negotiated_width ),
+         .cfg_current_speed                              ( cfg_current_speed ),
+         .cfg_max_payload                                ( cfg_max_payload ),
+         .cfg_max_read_req                               ( cfg_max_read_req ),
+         .cfg_function_status                            ( cfg_function_status ),
+         .cfg_function_power_state                       ( cfg_function_power_state ),
+         .cfg_vf_status                                  ( cfg_vf_status ),
+         .cfg_vf_power_state                             ( cfg_vf_power_state ),
+         .cfg_link_power_state                           ( cfg_link_power_state ),
+         // Error Reporting Interface
+         .cfg_err_cor_out                                ( cfg_err_cor_out ),
+         .cfg_err_nonfatal_out                           ( cfg_err_nonfatal_out ),
+         .cfg_err_fatal_out                              ( cfg_err_fatal_out ),
+         .cfg_ltr_enable                                 ( cfg_ltr_enable ),
+         .cfg_ltssm_state                                ( cfg_ltssm_state ),
+         .cfg_rcb_status                                 ( cfg_rcb_status ),
+         .cfg_dpa_substate_change                        ( cfg_dpa_substate_change ),
+         .cfg_obff_enable                                ( cfg_obff_enable ),
+         .cfg_pl_status_change                           ( cfg_pl_status_change ),
+         .cfg_tph_requester_enable                       ( cfg_tph_requester_enable ),
+         .cfg_tph_st_mode                                ( cfg_tph_st_mode ),
+         .cfg_vf_tph_requester_enable                    ( cfg_vf_tph_requester_enable ),
+         .cfg_vf_tph_st_mode                             ( cfg_vf_tph_st_mode ),
+         .cfg_fc_ph                                      ( cfg_fc_ph ),
+         .cfg_fc_pd                                      ( cfg_fc_pd ),
+         .cfg_fc_nph                                     ( cfg_fc_nph ),
+         .cfg_fc_npd                                     ( cfg_fc_npd ),
+         .cfg_fc_cplh                                    ( cfg_fc_cplh ),
+         .cfg_fc_cpld                                    ( cfg_fc_cpld ),
+         .cfg_fc_sel                                     ( cfg_fc_sel ),
+         //---------------------------------------------------------------------
+         // EP Only                                                             
+         //---------------------------------------------------------------------
+         // Interrupt Interface Signals
+         .cfg_interrupt_int                              ( cfg_interrupt_int ),
+         .cfg_interrupt_pending                          ( cfg_interrupt_pending ),
+         .cfg_interrupt_sent                             ( cfg_interrupt_sent ),
+         .cfg_interrupt_msi_enable                       ( cfg_interrupt_msi_enable ),
+         .cfg_interrupt_msi_vf_enable                    ( cfg_interrupt_msi_vf_enable ),
+         .cfg_interrupt_msi_mmenable                     ( cfg_interrupt_msi_mmenable ),
+         .cfg_interrupt_msi_mask_update                  ( cfg_interrupt_msi_mask_update ),
+         .cfg_interrupt_msi_data                         ( cfg_interrupt_msi_data ),
+         .cfg_interrupt_msi_select                       ( cfg_interrupt_msi_select ),
+         .cfg_interrupt_msi_int                          ( cfg_interrupt_msi_int ),
+         .cfg_interrupt_msi_pending_status               ( cfg_interrupt_msi_pending_status ),
+         .cfg_interrupt_msi_sent                         ( cfg_interrupt_msi_sent ),
+         .cfg_interrupt_msi_fail                         ( cfg_interrupt_msi_fail ),
+         .cfg_interrupt_msi_attr                         ( cfg_interrupt_msi_attr ),
+         .cfg_interrupt_msi_tph_present                  ( cfg_interrupt_msi_tph_present ),
+         .cfg_interrupt_msi_tph_type                     ( cfg_interrupt_msi_tph_type ),
+         .cfg_interrupt_msi_tph_st_tag                   ( cfg_interrupt_msi_tph_st_tag ),
+         .cfg_interrupt_msi_function_number              ( cfg_interrupt_msi_function_number ),
+
+         //---------------------------------------------------------------------
+         //  System(SYS) Interface                                              
+         //---------------------------------------------------------------------
+         .sys_clk                                        (pcie_refclk),
+         .sys_reset                                      (~pcie_reset_n));
+
+    riffa_wrapper_NetFPGA
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (// Outputs
+         .M_AXIS_CQ_TREADY              (m_axis_cq_tready),
+         .M_AXIS_RC_TREADY              (m_axis_rc_tready),
+         .S_AXIS_CC_TVALID              (s_axis_cc_tvalid),
+         .S_AXIS_CC_TLAST               (s_axis_cc_tlast),
+         .S_AXIS_CC_TDATA               (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (s_axis_rq_tvalid),
+         .S_AXIS_RQ_TLAST               (s_axis_rq_tlast),
+         .S_AXIS_RQ_TDATA               (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
+         .USER_CLK                      (user_clk),
+         .USER_RESET                    (user_reset),
+         .CFG_INTERRUPT_INT             (cfg_interrupt_int[3:0]),
+         .CFG_INTERRUPT_PENDING         (cfg_interrupt_pending[1:0]),
+         .CFG_INTERRUPT_MSI_SELECT      (cfg_interrupt_msi_select[3:0]),
+         .CFG_INTERRUPT_MSI_INT         (cfg_interrupt_msi_int[31:0]),
+         .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
+         .CFG_INTERRUPT_MSI_ATTR        (cfg_interrupt_msi_attr[2:0]),
+         .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
+         .CFG_INTERRUPT_MSI_TPH_TYPE    (cfg_interrupt_msi_tph_type[1:0]),
+         .CFG_INTERRUPT_MSI_TPH_ST_TAG  (cfg_interrupt_msi_tph_st_tag[8:0]),
+         .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
+         .CFG_FC_SEL                    (cfg_fc_sel[2:0]),
+         .PCIE_CQ_NP_REQ                (pcie_cq_np_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (m_axis_cq_tvalid),
+         .M_AXIS_CQ_TLAST               (m_axis_cq_tlast),
+         .M_AXIS_CQ_TDATA               (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (m_axis_rc_tvalid),
+         .M_AXIS_RC_TLAST               (m_axis_rc_tlast),
+         .M_AXIS_RC_TDATA               (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (s_axis_cc_tready),
+         .S_AXIS_RQ_TREADY              (s_axis_rq_tready),
+         .CFG_INTERRUPT_MSI_ENABLE      (cfg_interrupt_msi_enable[1:0]),
+         .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
+         .CFG_INTERRUPT_MSI_DATA        (cfg_interrupt_msi_data[31:0]),
+         .CFG_INTERRUPT_MSI_SENT        (cfg_interrupt_msi_sent),
+         .CFG_INTERRUPT_MSI_FAIL        (cfg_interrupt_msi_fail),
+         .CFG_FC_CPLH                   (cfg_fc_cplh[7:0]),
+         .CFG_FC_CPLD                   (cfg_fc_cpld[11:0]),
+         .CFG_NEGOTIATED_WIDTH          (cfg_negotiated_width[3:0]),
+         .CFG_CURRENT_SPEED             (cfg_current_speed[2:0]),
+         .CFG_MAX_PAYLOAD               (cfg_max_payload[2:0]),
+         .CFG_MAX_READ_REQ              (cfg_max_read_req[2:0]),
+         .CFG_FUNCTION_STATUS           (cfg_function_status[7:0]),
+         .CFG_RCB_STATUS                (cfg_rcb_status[1:0]),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0])
+         /*AUTOINST*/);
+
+    generate
+        for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
+            chnl_tester 
+                    #(/*AUTOINSTPARAM*/
+                      // Parameters
+                      .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH)) 
+            module1 
+                    (.CLK(user_clk),
+                     .RST(rst_out),    // riffa_reset includes riffa_endpoint resets
+                     // Rx interface
+                     .CHNL_RX_CLK(chnl_rx_clk[chnl]), 
+                     .CHNL_RX(chnl_rx[chnl]), 
+                     .CHNL_RX_ACK(chnl_rx_ack[chnl]), 
+                     .CHNL_RX_LAST(chnl_rx_last[chnl]), 
+                     .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), 
+                     .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), 
+                     .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), 
+                     .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
+                     // Tx interface
+                     .CHNL_TX_CLK(chnl_tx_clk[chnl]), 
+                     .CHNL_TX(chnl_tx[chnl]), 
+                     .CHNL_TX_ACK(chnl_tx_ack[chnl]), 
+                     .CHNL_TX_LAST(chnl_tx_last[chnl]), 
+                     .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), 
+                     .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), 
+                     .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), 
+                     .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
+                     /*AUTOINST*/);    
+        end
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("../../../../riffa_hdl/" "../../")
+// End:
+

fpga/xilinx/NetFPGA/NetFPGA_Gen2x8If128/ip/PCIeGen2x8If128.xci

@@ -0,0 +1,677 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>PCIeGen2x8If128</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie3_7x" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.device_port_type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xlnx_ref_board">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xlnx_ref_board">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">5.0_GT/s</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">X8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXISTEN_IF_RC_STRADDLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_client_tag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_CLASS_CODE">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEVICE_ID">7028</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_OBFF_SUPPORT">00_Not_Supported</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_REVISION_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_CLASS_CODE">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_DEVICE_ID">7011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_REVISION_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_VER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK">0001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_pf0_enable_reg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TL_PF_ENABLE_REG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">PCIeGen2x8If128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_vc_cap_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_blk_locn">X0Y1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_pb_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pb_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.alignment_mode">DWORD_Aligned</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_rev">Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dev_cap_max_payload">512_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_tphr_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sub_class_interface_menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.extended_tag_field">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_ari_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vendor_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_tphr_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_aer_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dsn_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_cap_ver">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msi_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dpa_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_pcie_cfg_space_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ari_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.perf_level">Extreme</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_width">128_bit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_aer_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dsn_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msi_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dpa_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dev_cap_max_payload">512_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ltr_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Advanced</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.shared_logic_in_core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_gt_common">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tx_fc_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_fc_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ext_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_status_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.per_func_status_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_mgmt_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rcv_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_tx_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ctl_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pcie_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_pipe_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_msi_per_vec_masking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_startup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tandem_mode">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_freq">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.aspm_support">No_ASPM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE_EXT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_msg_route">2FFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_rx_msg_intfc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_mode_sim">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_powerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USER_CLK2_FREQ">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_CAP_ASPM_SUPPORT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_WIDTH">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.REF_CLK_FREQ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_LINK_SPEED">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ARI_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXT_FUNC">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CQ_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_STRADDLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RQ_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_CHECK_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_GEN_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
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fpga/xilinx/NetFPGA/NetFPGA_Gen2x8If128/prj/NetFPGA_Gen2x8If128.xpr

@@ -0,0 +1,799 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2014.4 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="2" Path="/home/drichmond/Research/repositories/git/riffa/fpga/xilinx/NetFPGA/NetFPGA_Gen2x8If128/prj/NetFPGA_Gen2x8If128.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="771e255770ec4edc86ac461b1b604342"/>
+    <Option Name="Part" Val="xc7vx690tffg1761-3"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../../../../riffa_hdl/shiftreg.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/functions.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/scsdpram.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/fifo.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/ff.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/syncff.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rotate.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/ram_2clk_1w_1r.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/ram_1clk_1w_1r.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/pipeline.v">
+        <FileInfo>
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+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/one_hot_mux.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/offset_to_mask.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/types.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/trellis.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/widths.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/offset_flag_to_one_hot.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
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+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_data_shift.v">
+        <FileInfo>
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+      <File Path="$PPRDIR/../constr/NetFPGA_Top.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/NetFPGA_Top.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="NetFPGAGen2x8If128"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="PCIeGen2x8If128" Type="BlockSrcs" RelSrcDir="$PSRCDIR/PCIeGen2x8If128">
+      <File Path="$PPRDIR/../ip/PCIeGen2x8If128.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="PCIeGen2x8If128"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="9">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx690tffg1761-3" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen2x8If128_synth_1" Type="Ft3:Synth" SrcSet="PCIeGen2x8If128" Part="xc7vx690tffg1761-3" ConstrsSet="PCIeGen2x8If128" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/PCIeGen2x8If128_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1761-3" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen2x8If128_impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1761-3" ConstrsSet="PCIeGen2x8If128" Description="Vivado Implementation Defaults" SynthRun="PCIeGen2x8If128_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+  </Runs>
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</Project>

fpga/xilinx/NetFPGA/NetFPGA_Gen3x4If128/constr/NetFPGA_Top.xdc

@@ -0,0 +1,212 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+#
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            NetFPGA_Top.xdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Xilinx Design Constraints for the NetFPGA board.
+# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin
+#
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------
+#
+#########################################################################################################################
+# User Constraints
+#########################################################################################################################
+
+###############################################################################
+# User Time Names / User Time Groups / Time Specs
+###############################################################################
+
+###############################################################################
+# User Physical Constraints
+###############################################################################
+
+set_property PACKAGE_PIN AR22 [get_ports {LED[0]}]
+set_property PACKAGE_PIN AR23 [get_ports {LED[1]}]
+
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[1]}]
+
+set_false_path -to [get_ports -filter NAME=~LED*]
+
+#########################################################################################################################
+# End User Constraints
+#########################################################################################################################
+#
+#
+#
+#########################################################################################################################
+# PCIE Core Constraints
+#########################################################################################################################
+
+# SYS reset (input) signal.  The sys_reset_n signal should be
+# obtained from the PCI Express interface if possible.  For
+# slot based form factors, a system reset signal is usually
+# present on the connector.  For cable based form factors, a
+# system reset signal may not be available.  In this case, the
+# system reset signal must be generated locally by some form of
+# supervisory circuit.  You may change the IOSTANDARD and LOC
+# to suit your requirements and VCCO voltage banking rules.
+# Some 7 series devices do not have 3.3 V I/Os available.
+# Therefore the appropriate level shift is required to operate
+# with these devices that contain only 1.8 V banks.
+
+set_property PACKAGE_PIN AY35 [get_ports PCIE_RESET_N]
+set_property IOSTANDARD LVCMOS15 [get_ports PCIE_RESET_N]
+set_property PULLUP true [get_ports PCIE_RESET_N]
+
+# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
+# signals are the PCI Express reference clock. Virtex-7 GT
+# Transceiver architecture requires the use of a dedicated clock
+# resources (FPGA input pins) associated with each GT Transceiver.
+# To use these pins an IBUFDS primitive (refclk_ibuf) is
+# instantiated in user's design.
+# Please refer to the Virtex-7 GT Transceiver User Guide
+# (UG) for guidelines regarding clock resource selection.
+set_property LOC IBUFDS_GTE2_X1Y11 [get_cells refclk_ibuf]
+
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O]
+
+###############################################################################
+# Physical Constraints
+###############################################################################
+
+set_false_path -from [get_ports PCIE_RESET_N]
+###############################################################################
+# End
+###############################################################################
+
+
+
+#set_property MARK_DEBUG true [get_nets {pcie3_7x_0_i/inst/cfg_interrupt_msi_int[0]}]
+#set_property MARK_DEBUG true [get_nets {pcie3_7x_0_i/inst/cfg_interrupt_msi_pending_status[0]}]
+#set_property MARK_DEBUG true [get_nets pcie3_7x_0_i/inst/cfg_interrupt_msi_fail]
+#set_property MARK_DEBUG true [get_nets pcie3_7x_0_i/inst/cfg_interrupt_msi_sent]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlRxDoneReady]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlRxLenValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlRxOfflastValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgRxAddrHiValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgRxAddrLoValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgRxLenValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgTxAddrHiValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgTxAddrLoValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlSgTxLenValid]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlTxDoneReady]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wChnlTxLenReady]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/reg_inst/wTransDoneRst]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/intr/cfg_interrupt_msi_fail]
+#set_property MARK_DEBUG true [get_nets riffa/riffa_inst/intr/cfg_interrupt_msi_sent]
+#set_property MARK_DEBUG true [get_nets {riffa/riffa_inst/intr/wIntrVectorReady[0]}]
+#set_property MARK_DEBUG true [get_nets {riffa/riffa_inst/intr/wIntrVectorReady[1]}]
+#set_property MARK_DEBUG true [get_nets riffa/txr_sent]
+#create_debug_core u_ila_0_0 ila
+#set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0_0]
+#set_property ALL_PROBE_SAME_MU_CNT 2 [get_debug_cores u_ila_0_0]
+#set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0_0]
+#set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0_0]
+#set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0_0]
+#set_property C_INPUT_PIPE_STAGES 2 [get_debug_cores u_ila_0_0]
+#set_property C_TRIGIN_EN false [get_debug_cores u_ila_0_0]
+#set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0_0]
+#set_property port_width 1 [get_debug_ports u_ila_0_0/clk]
+#connect_debug_port u_ila_0_0/clk [get_nets [list user_clk]]
+#set_property port_width 2 [get_debug_ports u_ila_0_0/probe0]
+#connect_debug_port u_ila_0_0/probe0 [get_nets [list {riffa/riffa_inst/intr/wIntrVectorReady[0]} {riffa/riffa_inst/intr/wIntrVectorReady[1]}]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe1]
+#connect_debug_port u_ila_0_0/probe1 [get_nets [list {pcie3_7x_0_i/inst/cfg_interrupt_msi_pending_status[0]}]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe2]
+#connect_debug_port u_ila_0_0/probe2 [get_nets [list {pcie3_7x_0_i/inst/cfg_interrupt_msi_int[0]}]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe3]
+#connect_debug_port u_ila_0_0/probe3 [get_nets [list riffa/riffa_inst/intr/cfg_interrupt_msi_fail]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe4]
+#connect_debug_port u_ila_0_0/probe4 [get_nets [list pcie3_7x_0_i/inst/cfg_interrupt_msi_fail]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe5]
+#connect_debug_port u_ila_0_0/probe5 [get_nets [list pcie3_7x_0_i/inst/cfg_interrupt_msi_sent]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe6]
+#connect_debug_port u_ila_0_0/probe6 [get_nets [list riffa/riffa_inst/intr/cfg_interrupt_msi_sent]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe7]
+#connect_debug_port u_ila_0_0/probe7 [get_nets [list riffa/txr_sent]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe8]
+#connect_debug_port u_ila_0_0/probe8 [get_nets [list riffa/riffa_inst/reg_inst/wChnlRxDoneReady]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe9]
+#connect_debug_port u_ila_0_0/probe9 [get_nets [list riffa/riffa_inst/reg_inst/wChnlRxLenValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe10]
+#connect_debug_port u_ila_0_0/probe10 [get_nets [list riffa/riffa_inst/reg_inst/wChnlRxOfflastValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe11]
+#connect_debug_port u_ila_0_0/probe11 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgRxAddrHiValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe12]
+#connect_debug_port u_ila_0_0/probe12 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgRxAddrLoValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe13]
+#connect_debug_port u_ila_0_0/probe13 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgRxLenValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe14]
+#connect_debug_port u_ila_0_0/probe14 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgTxAddrHiValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe15]
+#connect_debug_port u_ila_0_0/probe15 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgTxAddrLoValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe16]
+#connect_debug_port u_ila_0_0/probe16 [get_nets [list riffa/riffa_inst/reg_inst/wChnlSgTxLenValid]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe17]
+#connect_debug_port u_ila_0_0/probe17 [get_nets [list riffa/riffa_inst/reg_inst/wChnlTxDoneReady]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe18]
+#connect_debug_port u_ila_0_0/probe18 [get_nets [list riffa/riffa_inst/reg_inst/wChnlTxLenReady]]
+#create_debug_port u_ila_0_0 probe
+#set_property port_width 1 [get_debug_ports u_ila_0_0/probe19]
+#connect_debug_port u_ila_0_0/probe19 [get_nets [list riffa/riffa_inst/reg_inst/wTransDoneRst]]
+#set_property MARK_DEBUG true [get_nets riffa/engine_layer_inst/rx_engine_ultrascale_inst/RXR_DATA_VALID]
+#set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+#connect_debug_port dbg_hub/clk [get_nets user_clk]

fpga/xilinx/NetFPGA/NetFPGA_Gen3x4If128/hdl/NetFPGAGen3x4If128.v

@@ -0,0 +1,450 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            NetFPGAGen3x4If128.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Xilinx NetFPGA Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "functions.vh"
+`include "riffa.vh"
+`include "ultrascale.vh"
+`timescale 1ps / 1ps
+module NetFPGAGen3x4If128
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  4,
+      // Settings from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 6) 
+    (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
+     output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXP,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXN,
+
+     output [1:0]                   LED,
+     input                          PCIE_REFCLK_P,
+     input                          PCIE_REFCLK_N,
+     input                          PCIE_RESET_N);
+
+    // Clocks, etc
+    wire                            user_lnk_up;
+    wire                            user_clk;
+    wire                            user_reset;
+    wire                            pcie_refclk;
+    wire                            pcie_reset_n;
+
+    // Interface: RQ (TXC)
+    wire                            s_axis_rq_tlast;
+    wire [C_PCI_DATA_WIDTH-1:0]     s_axis_rq_tdata;
+    wire [`SIG_RQ_TUSER_W-1:0]      s_axis_rq_tuser;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
+    wire                             s_axis_rq_tready;
+    wire                             s_axis_rq_tvalid;
+    // Interface: RC (RXC)
+    wire [C_PCI_DATA_WIDTH-1:0]      m_axis_rc_tdata;
+    wire [`SIG_RC_TUSER_W-1:0]       m_axis_rc_tuser;
+    wire                             m_axis_rc_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
+    wire                             m_axis_rc_tvalid;
+    wire                             m_axis_rc_tready;
+    // Interface: CQ (RXR)
+    wire [C_PCI_DATA_WIDTH-1:0]      m_axis_cq_tdata;
+    wire [`SIG_CQ_TUSER_W-1:0]       m_axis_cq_tuser;
+    wire                             m_axis_cq_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
+    wire                             m_axis_cq_tvalid;
+    wire                             m_axis_cq_tready;
+    // Interface: CC (TXC)
+    wire [C_PCI_DATA_WIDTH-1:0]      s_axis_cc_tdata;
+    wire [`SIG_CC_TUSER_W-1:0]       s_axis_cc_tuser;
+    wire                             s_axis_cc_tlast;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
+    wire                             s_axis_cc_tvalid;
+    wire                             s_axis_cc_tready;
+
+    // Configuration (CFG) Interface                                           
+    wire [3:0]                       pcie_rq_seq_num;
+    wire                             pcie_rq_seq_num_vld;
+    wire [5:0]                       pcie_rq_tag;
+    wire                             pcie_rq_tag_vld;
+    wire                             pcie_cq_np_req;
+    wire [5:0]                       pcie_cq_np_req_count;
+
+    wire                             cfg_phy_link_down;
+    wire [3:0]                       cfg_negotiated_width; // CONFIG_LINK_WIDTH
+    wire [2:0]                       cfg_current_speed; // CONFIG_LINK_RATE
+    wire [2:0]                       cfg_max_payload; // CONFIG_MAX_PAYLOAD
+    wire [2:0]                       cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
+    wire [7:0]                       cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
+    wire [5:0]                       cfg_function_power_state; // Ignorable but not removable
+    wire [11:0]                      cfg_vf_status; // Ignorable but not removable
+    wire [17:0]                      cfg_vf_power_state; // Ignorable but not removable
+    wire [1:0]                       cfg_link_power_state; // Ignorable but not removable
+
+    // Error Reporting Interface
+    wire                             cfg_err_cor_out;
+    wire                             cfg_err_nonfatal_out;
+    wire                             cfg_err_fatal_out;
+
+    wire                             cfg_ltr_enable;
+    wire [5:0]                       cfg_ltssm_state;
+    wire [1:0]                       cfg_rcb_status;
+    wire [1:0]                       cfg_dpa_substate_change;
+    wire [1:0]                       cfg_obff_enable;
+    wire                             cfg_pl_status_change;
+
+    wire [1:0]                       cfg_tph_requester_enable;
+    wire [5:0]                       cfg_tph_st_mode;
+    wire [5:0]                       cfg_vf_tph_requester_enable;
+    wire [17:0]                      cfg_vf_tph_st_mode;
+    wire [7:0]                       cfg_fc_ph;
+    wire [11:0]                      cfg_fc_pd;
+    wire [7:0]                       cfg_fc_nph;
+    wire [11:0]                      cfg_fc_npd;
+    wire [7:0]                       cfg_fc_cplh;
+    wire [11:0]                      cfg_fc_cpld;
+    wire [2:0]                       cfg_fc_sel;
+
+    // Interrupt Interface Signals
+    wire [3:0]                       cfg_interrupt_int;
+    wire [1:0]                       cfg_interrupt_pending;
+    wire                             cfg_interrupt_sent;
+    wire [1:0]                       cfg_interrupt_msi_enable;
+    wire [5:0]                       cfg_interrupt_msi_vf_enable;
+    wire [5:0]                       cfg_interrupt_msi_mmenable;
+    wire                             cfg_interrupt_msi_mask_update;
+    wire [31:0]                      cfg_interrupt_msi_data;
+    wire [3:0]                       cfg_interrupt_msi_select;
+    wire [31:0]                      cfg_interrupt_msi_int;
+    wire [63:0]                      cfg_interrupt_msi_pending_status;
+    wire                             cfg_interrupt_msi_sent;
+    wire                             cfg_interrupt_msi_fail;
+    wire [2:0]                       cfg_interrupt_msi_attr;
+    wire                             cfg_interrupt_msi_tph_present;
+    wire [1:0]                       cfg_interrupt_msi_tph_type;
+    wire [8:0]                       cfg_interrupt_msi_tph_st_tag;
+    wire [2:0]                       cfg_interrupt_msi_function_number;
+
+    wire                             rst_out;
+    wire [C_NUM_CHNL-1:0]            chnl_rx_clk; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx_ack; 
+    wire [C_NUM_CHNL-1:0]            chnl_rx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_rx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_ren;
+
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_clk; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_tx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_ren;
+
+    genvar                                     chnl;
+
+    IBUF 
+        #()  
+    pci_reset_n_ibuf 
+        (.O(pcie_reset_n), 
+         .I(PCIE_RESET_N));
+
+    IBUFDS_GTE2 
+        #()
+    refclk_ibuf 
+        (.O(pcie_refclk), 
+         .ODIV2(), 
+         .I(PCIE_REFCLK_P), 
+         .CEB(1'b0), 
+         .IB(PCIE_REFCLK_N));
+
+    OBUF 
+        #() 
+    led_0_obuf 
+        (.O(LED[0]),
+         .I(cfg_ltssm_state[0]));
+    OBUF 
+        #() 
+    led_1_obuf 
+        (.O(LED[1]),
+         .I(cfg_ltssm_state[1]));
+
+    // Core Top Level Wrapper
+    PCIeGen3x4If128  
+        #()
+    pcie3_7x_0_i 
+        (//---------------------------------------------------------------------
+         //  PCI Express (pci_exp) Interface                                    
+         //---------------------------------------------------------------------
+         .pci_exp_txn                                    ( PCI_EXP_TXN ),
+         .pci_exp_txp                                    ( PCI_EXP_TXP ),
+         .pci_exp_rxn                                    ( PCI_EXP_RXN ),
+         .pci_exp_rxp                                    ( PCI_EXP_RXP ),
+
+         //---------------------------------------------------------------------
+         //  AXI Interface                                                      
+         //---------------------------------------------------------------------
+         .user_clk                                       ( user_clk ),
+         .user_reset                                     ( user_reset ),
+         .user_lnk_up                                    ( user_lnk_up ),
+         .user_app_rdy                                   ( ),
+
+         .s_axis_rq_tlast                                ( s_axis_rq_tlast ),
+         .s_axis_rq_tdata                                ( s_axis_rq_tdata ),
+         .s_axis_rq_tuser                                ( s_axis_rq_tuser ),
+         .s_axis_rq_tkeep                                ( s_axis_rq_tkeep ),
+         .s_axis_rq_tready                               ( s_axis_rq_tready ),
+         .s_axis_rq_tvalid                               ( s_axis_rq_tvalid ),
+
+         .m_axis_rc_tdata                                ( m_axis_rc_tdata ),
+         .m_axis_rc_tuser                                ( m_axis_rc_tuser ),
+         .m_axis_rc_tlast                                ( m_axis_rc_tlast ),
+         .m_axis_rc_tkeep                                ( m_axis_rc_tkeep ),
+         .m_axis_rc_tvalid                               ( m_axis_rc_tvalid ),
+         .m_axis_rc_tready                               ( {22{m_axis_rc_tready}} ),
+
+         .m_axis_cq_tdata                                ( m_axis_cq_tdata ),
+         .m_axis_cq_tuser                                ( m_axis_cq_tuser ),
+         .m_axis_cq_tlast                                ( m_axis_cq_tlast ),
+         .m_axis_cq_tkeep                                ( m_axis_cq_tkeep ),
+         .m_axis_cq_tvalid                               ( m_axis_cq_tvalid ),
+         .m_axis_cq_tready                               ( {22{m_axis_cq_tready}} ),
+
+         .s_axis_cc_tdata                                ( s_axis_cc_tdata ),
+         .s_axis_cc_tuser                                ( s_axis_cc_tuser ),
+         .s_axis_cc_tlast                                ( s_axis_cc_tlast ),
+         .s_axis_cc_tkeep                                ( s_axis_cc_tkeep ),
+         .s_axis_cc_tvalid                               ( s_axis_cc_tvalid ),
+         .s_axis_cc_tready                               ( s_axis_cc_tready ),
+
+         //---------------------------------------------------------------------
+         //  Configuration (CFG) Interface                                      
+         //---------------------------------------------------------------------
+         .pcie_rq_seq_num                                ( pcie_rq_seq_num ),
+         .pcie_rq_seq_num_vld                            ( pcie_rq_seq_num_vld ),
+         .pcie_rq_tag                                    ( pcie_rq_tag ),
+         .pcie_rq_tag_vld                                ( pcie_rq_tag_vld ),
+         .pcie_cq_np_req                                 ( pcie_cq_np_req ),
+         .pcie_cq_np_req_count                           ( pcie_cq_np_req_count ),
+         .cfg_phy_link_down                              ( cfg_phy_link_down ),
+         .cfg_phy_link_status                            ( cfg_phy_link_status),
+         .cfg_negotiated_width                           ( cfg_negotiated_width ),
+         .cfg_current_speed                              ( cfg_current_speed ),
+         .cfg_max_payload                                ( cfg_max_payload ),
+         .cfg_max_read_req                               ( cfg_max_read_req ),
+         .cfg_function_status                            ( cfg_function_status ),
+         .cfg_function_power_state                       ( cfg_function_power_state ),
+         .cfg_vf_status                                  ( cfg_vf_status ),
+         .cfg_vf_power_state                             ( cfg_vf_power_state ),
+         .cfg_link_power_state                           ( cfg_link_power_state ),
+         // Error Reporting Interface
+         .cfg_err_cor_out                                ( cfg_err_cor_out ),
+         .cfg_err_nonfatal_out                           ( cfg_err_nonfatal_out ),
+         .cfg_err_fatal_out                              ( cfg_err_fatal_out ),
+         .cfg_ltr_enable                                 ( cfg_ltr_enable ),
+         .cfg_ltssm_state                                ( cfg_ltssm_state ),
+         .cfg_rcb_status                                 ( cfg_rcb_status ),
+         .cfg_dpa_substate_change                        ( cfg_dpa_substate_change ),
+         .cfg_obff_enable                                ( cfg_obff_enable ),
+         .cfg_pl_status_change                           ( cfg_pl_status_change ),
+         .cfg_tph_requester_enable                       ( cfg_tph_requester_enable ),
+         .cfg_tph_st_mode                                ( cfg_tph_st_mode ),
+         .cfg_vf_tph_requester_enable                    ( cfg_vf_tph_requester_enable ),
+         .cfg_vf_tph_st_mode                             ( cfg_vf_tph_st_mode ),
+         .cfg_fc_ph                                      ( cfg_fc_ph ),
+         .cfg_fc_pd                                      ( cfg_fc_pd ),
+         .cfg_fc_nph                                     ( cfg_fc_nph ),
+         .cfg_fc_npd                                     ( cfg_fc_npd ),
+         .cfg_fc_cplh                                    ( cfg_fc_cplh ),
+         .cfg_fc_cpld                                    ( cfg_fc_cpld ),
+         .cfg_fc_sel                                     ( cfg_fc_sel ),
+         //---------------------------------------------------------------------
+         // EP Only                                                             
+         //---------------------------------------------------------------------
+         // Interrupt Interface Signals
+         .cfg_interrupt_int                              ( cfg_interrupt_int ),
+         .cfg_interrupt_pending                          ( cfg_interrupt_pending ),
+         .cfg_interrupt_sent                             ( cfg_interrupt_sent ),
+         .cfg_interrupt_msi_enable                       ( cfg_interrupt_msi_enable ),
+         .cfg_interrupt_msi_vf_enable                    ( cfg_interrupt_msi_vf_enable ),
+         .cfg_interrupt_msi_mmenable                     ( cfg_interrupt_msi_mmenable ),
+         .cfg_interrupt_msi_mask_update                  ( cfg_interrupt_msi_mask_update ),
+         .cfg_interrupt_msi_data                         ( cfg_interrupt_msi_data ),
+         .cfg_interrupt_msi_select                       ( cfg_interrupt_msi_select ),
+         .cfg_interrupt_msi_int                          ( cfg_interrupt_msi_int ),
+         .cfg_interrupt_msi_pending_status               ( cfg_interrupt_msi_pending_status ),
+         .cfg_interrupt_msi_sent                         ( cfg_interrupt_msi_sent ),
+         .cfg_interrupt_msi_fail                         ( cfg_interrupt_msi_fail ),
+         .cfg_interrupt_msi_attr                         ( cfg_interrupt_msi_attr ),
+         .cfg_interrupt_msi_tph_present                  ( cfg_interrupt_msi_tph_present ),
+         .cfg_interrupt_msi_tph_type                     ( cfg_interrupt_msi_tph_type ),
+         .cfg_interrupt_msi_tph_st_tag                   ( cfg_interrupt_msi_tph_st_tag ),
+         .cfg_interrupt_msi_function_number              ( cfg_interrupt_msi_function_number ),
+
+         //---------------------------------------------------------------------
+         //  System(SYS) Interface                                              
+         //---------------------------------------------------------------------
+         .sys_clk                                        (pcie_refclk),
+         .sys_reset                                      (~pcie_reset_n));
+
+    riffa_wrapper_NetFPGA
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (// Outputs
+         .M_AXIS_CQ_TREADY              (m_axis_cq_tready),
+         .M_AXIS_RC_TREADY              (m_axis_rc_tready),
+         .S_AXIS_CC_TVALID              (s_axis_cc_tvalid),
+         .S_AXIS_CC_TLAST               (s_axis_cc_tlast),
+         .S_AXIS_CC_TDATA               (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (s_axis_rq_tvalid),
+         .S_AXIS_RQ_TLAST               (s_axis_rq_tlast),
+         .S_AXIS_RQ_TDATA               (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
+         .USER_CLK                      (user_clk),
+         .USER_RESET                    (user_reset),
+         .CFG_INTERRUPT_INT             (cfg_interrupt_int[3:0]),
+         .CFG_INTERRUPT_PENDING         (cfg_interrupt_pending[1:0]),
+         .CFG_INTERRUPT_MSI_SELECT      (cfg_interrupt_msi_select[3:0]),
+         .CFG_INTERRUPT_MSI_INT         (cfg_interrupt_msi_int[31:0]),
+         .CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
+         .CFG_INTERRUPT_MSI_ATTR        (cfg_interrupt_msi_attr[2:0]),
+         .CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
+         .CFG_INTERRUPT_MSI_TPH_TYPE    (cfg_interrupt_msi_tph_type[1:0]),
+         .CFG_INTERRUPT_MSI_TPH_ST_TAG  (cfg_interrupt_msi_tph_st_tag[8:0]),
+         .CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
+         .CFG_FC_SEL                    (cfg_fc_sel[2:0]),
+         .PCIE_CQ_NP_REQ                (pcie_cq_np_req),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (m_axis_cq_tvalid),
+         .M_AXIS_CQ_TLAST               (m_axis_cq_tlast),
+         .M_AXIS_CQ_TDATA               (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (m_axis_rc_tvalid),
+         .M_AXIS_RC_TLAST               (m_axis_rc_tlast),
+         .M_AXIS_RC_TDATA               (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (s_axis_cc_tready),
+         .S_AXIS_RQ_TREADY              (s_axis_rq_tready),
+         .CFG_INTERRUPT_MSI_ENABLE      (cfg_interrupt_msi_enable[1:0]),
+         .CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
+         .CFG_INTERRUPT_MSI_DATA        (cfg_interrupt_msi_data[31:0]),
+         .CFG_INTERRUPT_MSI_SENT        (cfg_interrupt_msi_sent),
+         .CFG_INTERRUPT_MSI_FAIL        (cfg_interrupt_msi_fail),
+         .CFG_FC_CPLH                   (cfg_fc_cplh[7:0]),
+         .CFG_FC_CPLD                   (cfg_fc_cpld[11:0]),
+         .CFG_NEGOTIATED_WIDTH          (cfg_negotiated_width[3:0]),
+         .CFG_CURRENT_SPEED             (cfg_current_speed[2:0]),
+         .CFG_MAX_PAYLOAD               (cfg_max_payload[2:0]),
+         .CFG_MAX_READ_REQ              (cfg_max_read_req[2:0]),
+         .CFG_FUNCTION_STATUS           (cfg_function_status[7:0]),
+         .CFG_RCB_STATUS                (cfg_rcb_status[1:0]),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0])
+         /*AUTOINST*/);
+
+    generate
+        for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
+            chnl_tester 
+                    #(/*AUTOINSTPARAM*/
+                      // Parameters
+                      .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH)) 
+            module1 
+                    (.CLK(user_clk),
+                     .RST(rst_out),    // riffa_reset includes riffa_endpoint resets
+                     // Rx interface
+                     .CHNL_RX_CLK(chnl_rx_clk[chnl]), 
+                     .CHNL_RX(chnl_rx[chnl]), 
+                     .CHNL_RX_ACK(chnl_rx_ack[chnl]), 
+                     .CHNL_RX_LAST(chnl_rx_last[chnl]), 
+                     .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), 
+                     .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), 
+                     .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), 
+                     .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
+                     // Tx interface
+                     .CHNL_TX_CLK(chnl_tx_clk[chnl]), 
+                     .CHNL_TX(chnl_tx[chnl]), 
+                     .CHNL_TX_ACK(chnl_tx_ack[chnl]), 
+                     .CHNL_TX_LAST(chnl_tx_last[chnl]), 
+                     .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), 
+                     .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), 
+                     .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), 
+                     .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
+                     /*AUTOINST*/);    
+        end
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("../../../../riffa_hdl/" "../../")
+// End:
+

fpga/xilinx/NetFPGA/NetFPGA_Gen3x4If128/ip/PCIeGen3x4If128.xci

@@ -0,0 +1,677 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>PCIeGen3x4If128</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie3_7x" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.device_port_type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xlnx_ref_board">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xlnx_ref_board">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">8.0_GT/s</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">X4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXISTEN_IF_RC_STRADDLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_client_tag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_CLASS_CODE">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEVICE_ID">7034</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_OBFF_SUPPORT">00_Not_Supported</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_REVISION_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_CLASS_CODE">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_DEVICE_ID">7011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_REVISION_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_VER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK">0001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_pf0_enable_reg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TL_PF_ENABLE_REG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">PCIeGen3x4If128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_vc_cap_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_blk_locn">X0Y1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_pb_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pb_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.alignment_mode">DWORD_Aligned</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_rev">Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dev_cap_max_payload">512_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_tphr_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sub_class_interface_menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.extended_tag_field">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_ari_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vendor_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_tphr_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_aer_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dsn_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_cap_ver">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msi_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dpa_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_pcie_cfg_space_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ari_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.perf_level">Extreme</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_width">128_bit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_aer_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dsn_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msi_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dpa_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dev_cap_max_payload">512_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ltr_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Advanced</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.shared_logic_in_core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_gt_common">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tx_fc_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_fc_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ext_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_status_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.per_func_status_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_mgmt_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rcv_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_tx_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ctl_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pcie_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_pipe_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_msi_per_vec_masking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_startup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tandem_mode">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_freq">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.aspm_support">No_ASPM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE_EXT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_msg_route">2FFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_rx_msg_intfc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_mode_sim">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_powerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USER_CLK2_FREQ">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_CAP_ASPM_SUPPORT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_WIDTH">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.REF_CLK_FREQ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_LINK_SPEED">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ARI_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXT_FUNC">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CQ_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_STRADDLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RQ_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_CHECK_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_GEN_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR0_APERTURE_SIZE">0b00011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR0_CONTROL">0b100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR1_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR1_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR2_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR2_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR3_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR3_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR4_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR4_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR5_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR5_CONTROL">0b000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_CLASS_CODE">0x058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_VENDOR_ID">0x10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEVICE_ID">0x7034</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_LTR_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_OBFF_SUPPORT">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_EXT_TAG_SUPPORTED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_MAX_PAYLOAD_SIZE">0b010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DSN_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_APERTURE_SIZE">0b00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_INTERRUPT_PIN">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LTR_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSI_CAP_NEXTPTR">0xC0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PB_CAP_NEXTPTR">0x274</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_NEXTPTR">0x90</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE0">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE1">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE2">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE0">0x00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE1">0x00000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_ECRC_GEN_CAPABLE">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_LEGACY_MODE_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_PF_ENABLE_REG">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
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+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
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+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
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+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_engine_selector.v">
+        <FileInfo>
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+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
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+        <FileInfo>
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+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
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+        <FileInfo>
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+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
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+        <FileInfo>
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+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
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+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/register.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reset_controller.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_multiplexer_64.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
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+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_multiplexer_32.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
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+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
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+      <File Path="$PPRDIR/../../../../riffa_hdl/ultrascale.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/txr_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tlp.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/txr_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/txc_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/txc_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxr_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxr_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxc_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxc_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue_output.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue_input.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/interrupt_controller.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/demux.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel_64.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel_32.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel_128.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxc_engine_128.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rxr_engine_128.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_multiplexer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/tx_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rx_engine_ultrascale.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/rx_engine_classic.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/reorder_queue.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/riffa.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/registers.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/recv_credit_flow_ctrl.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/interrupt.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/riffa.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/engine_layer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/chnl_tester.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../riffa_wrapper_NetFPGA.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../hdl/NetFPGAGen3x4If128.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/xilinx.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/altera.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="NetFPGAGen3x4If128"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../constr/NetFPGA_Top.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/NetFPGA_Top.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="NetFPGAGen3x4If128"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="PCIeGen3x4If128" Type="BlockSrcs" RelSrcDir="$PSRCDIR/PCIeGen3x4If128">
+      <File Path="$PPRDIR/../ip/PCIeGen3x4If128.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="PCIeGen3x4If128"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="9">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx690tffg1761-3" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen3x4If128_synth_1" Type="Ft3:Synth" SrcSet="PCIeGen3x4If128" Part="xc7vx690tffg1761-3" ConstrsSet="PCIeGen3x4If128" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/PCIeGen3x4If128_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1761-3" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen3x4If128_impl_1" Type="Ft2:EntireDesign" Part="xc7vx690tffg1761-3" ConstrsSet="PCIeGen3x4If128" Description="Vivado Implementation Defaults" SynthRun="PCIeGen3x4If128_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
+          <Desc>Vivado Implementation Defaults</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+  </Runs>
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</Project>

fpga/xilinx/NetFPGA/riffa_wrapper_NetFPGA.v

@@ -0,0 +1,598 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            riffa_wrapper_NetFPGA.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         RIFFA wrapper for the NetFPGA SUME Development board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "ultrascale.vh"
+`include "functions.vh"
+`timescale 1ps / 1ps
+module riffa_wrapper_NetFPGA
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Bit-Width from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      // 4-Byte Name for this FPGA
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5, 
+      parameter C_FPGA_ID = "7V30") 
+    (//Interface: CQ Ultrascale (RXR)
+     input                                        M_AXIS_CQ_TVALID,
+     input                                        M_AXIS_CQ_TLAST,
+     input [C_PCI_DATA_WIDTH-1:0]                 M_AXIS_CQ_TDATA,
+     input [(C_PCI_DATA_WIDTH/32)-1:0]            M_AXIS_CQ_TKEEP,
+     input [`SIG_CQ_TUSER_W-1:0]                  M_AXIS_CQ_TUSER,
+     output                                       M_AXIS_CQ_TREADY,
+
+     //Interface: RC Ultrascale (RXC)
+     input                                        M_AXIS_RC_TVALID,
+     input                                        M_AXIS_RC_TLAST,
+     input [C_PCI_DATA_WIDTH-1:0]                 M_AXIS_RC_TDATA,
+     input [(C_PCI_DATA_WIDTH/32)-1:0]            M_AXIS_RC_TKEEP,
+     input [`SIG_RC_TUSER_W-1:0]                  M_AXIS_RC_TUSER,
+     output                                       M_AXIS_RC_TREADY,
+
+     //Interface: CC Ultrascale (TXC)
+     input                                        S_AXIS_CC_TREADY,
+     output                                       S_AXIS_CC_TVALID,
+     output                                       S_AXIS_CC_TLAST,
+     output [C_PCI_DATA_WIDTH-1:0]                S_AXIS_CC_TDATA,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]           S_AXIS_CC_TKEEP,
+     output [`SIG_CC_TUSER_W-1:0]                 S_AXIS_CC_TUSER,
+    
+     //Interface: RQ Ultrascale (TXR) 
+     input                                        S_AXIS_RQ_TREADY,
+     output                                       S_AXIS_RQ_TVALID,
+     output                                       S_AXIS_RQ_TLAST,
+     output [C_PCI_DATA_WIDTH-1:0]                S_AXIS_RQ_TDATA,
+     output [(C_PCI_DATA_WIDTH/32)-1:0]           S_AXIS_RQ_TKEEP,
+     output [`SIG_RQ_TUSER_W-1:0]                 S_AXIS_RQ_TUSER,
+
+     input                                        USER_CLK,
+     input                                        USER_RESET,
+
+     output [3:0]                                 CFG_INTERRUPT_INT,
+     output [1:0]                                 CFG_INTERRUPT_PENDING,
+     input [1:0]                                  CFG_INTERRUPT_MSI_ENABLE,
+     input                                        CFG_INTERRUPT_MSI_MASK_UPDATE,
+     input [31:0]                                 CFG_INTERRUPT_MSI_DATA,
+     output [3:0]                                 CFG_INTERRUPT_MSI_SELECT,
+     output [31:0]                                CFG_INTERRUPT_MSI_INT,
+     output [63:0]                                CFG_INTERRUPT_MSI_PENDING_STATUS,
+     input                                        CFG_INTERRUPT_MSI_SENT,
+     input                                        CFG_INTERRUPT_MSI_FAIL,
+     output [2:0]                                 CFG_INTERRUPT_MSI_ATTR,
+     output                                       CFG_INTERRUPT_MSI_TPH_PRESENT,
+     output [1:0]                                 CFG_INTERRUPT_MSI_TPH_TYPE,
+     output [8:0]                                 CFG_INTERRUPT_MSI_TPH_ST_TAG,
+     output [2:0]                                 CFG_INTERRUPT_MSI_FUNCTION_NUMBER,
+
+     input [7:0]                                  CFG_FC_CPLH,
+     input [11:0]                                 CFG_FC_CPLD,
+     output [2:0]                                 CFG_FC_SEL,
+
+     input [3:0]                                  CFG_NEGOTIATED_WIDTH, // CONFIG_LINK_WIDTH
+     input [2:0]                                  CFG_CURRENT_SPEED, // CONFIG_LINK_RATE
+     input [2:0]                                  CFG_MAX_PAYLOAD, // CONFIG_MAX_PAYLOAD
+     input [2:0]                                  CFG_MAX_READ_REQ, // CONFIG_MAX_READ_REQUEST
+     input [7:0]                                  CFG_FUNCTION_STATUS, // [2] = CONFIG_BUS_MASTER_ENABLE
+     input [1:0]                                  CFG_RCB_STATUS,
+    
+     output                                       PCIE_CQ_NP_REQ,
+
+     // RIFFA Interface Signals
+     output                                       RST_OUT,
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_CLK, // Channel read clock
+     output [C_NUM_CHNL-1:0]                      CHNL_RX, // Channel read receive signal
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_ACK, // Channel read received signal
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_LAST, // Channel last read
+     output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
+     output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
+     output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   CHNL_RX_DATA, // Channel read data
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_DATA_VALID, // Channel read data valid
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_DATA_REN, // Channel read data has been recieved
+
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_CLK, // Channel write clock
+     input [C_NUM_CHNL-1:0]                       CHNL_TX, // Channel write receive signal
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_ACK, // Channel write acknowledgement signal
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_LAST, // Channel last write
+     input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]  CHNL_TX_LEN, // Channel write length (in 32 bit words)
+     input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]  CHNL_TX_OFF, // Channel write offset
+     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]    CHNL_TX_DATA, // Channel write data
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_DATA_VALID, // Channel write data valid
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_DATA_REN); // Channel write data has been recieved
+     
+    localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
+    localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
+    // ALTERA, XILINX or ULTRASCALE
+    localparam C_VENDOR = "ULTRASCALE";
+
+    localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
+    localparam C_PIPELINE_OUTPUT = 1;
+    localparam C_PIPELINE_INPUT = 1;
+    localparam C_DEPTH_PACKETS = 4;
+    
+    wire                                          clk;
+    wire                                          rst_in;
+    wire                                          done_txc_rst;
+    wire                                          done_txr_rst;
+    wire                                          done_rxr_rst;
+    wire                                          done_rxc_rst;
+    // Interface: RXC Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxc_data;
+    wire                                          rxc_data_valid;
+    wire                                          rxc_data_start_flag;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxc_data_word_enable;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxc_meta_fdwbe;
+    wire                                          rxc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxc_meta_ldwbe;
+    wire [`SIG_TAG_W-1:0]                         rxc_meta_tag;
+    wire [`SIG_LOWADDR_W-1:0]                     rxc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        rxc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         rxc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     rxc_meta_bytes_remaining;
+    wire [`SIG_CPLID_W-1:0]                       rxc_meta_completer_id;
+    wire                                          rxc_meta_ep;
+
+    // Interface: RXR Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxr_data;
+    wire                                          rxr_data_valid;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxr_data_word_enable;
+    wire                                          rxr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxr_meta_fdwbe;
+    wire                                          rxr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxr_meta_ldwbe;
+    wire [`SIG_TC_W-1:0]                          rxr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        rxr_meta_attr;
+    wire [`SIG_TAG_W-1:0]                         rxr_meta_tag;
+    wire [`SIG_TYPE_W-1:0]                        rxr_meta_type;
+    wire [`SIG_ADDR_W-1:0]                        rxr_meta_addr;
+    wire [`SIG_BARDECODE_W-1:0]                   rxr_meta_bar_decoded;
+    wire [`SIG_REQID_W-1:0]                       rxr_meta_requester_id;
+    wire [`SIG_LEN_W-1:0]                         rxr_meta_length;
+    wire                                          rxr_meta_ep;
+    
+    // interface: TXC Engine
+    wire                                          txc_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txc_data;
+    wire                                          txc_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_start_offset;
+    wire                                          txc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_end_offset;
+    wire                                          txc_data_ready;
+
+    wire                                          txc_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txc_meta_fdwbe;
+    wire [`SIG_LBE_W-1:0]                         txc_meta_ldwbe;
+    wire [`SIG_LOWADDR_W-1:0]                     txc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        txc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         txc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     txc_meta_byte_count;
+    wire [`SIG_TAG_W-1:0]                         txc_meta_tag;
+    wire [`SIG_REQID_W-1:0]                       txc_meta_requester_id;
+    wire [`SIG_TC_W-1:0]                          txc_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txc_meta_attr;
+    wire                                          txc_meta_ep;
+    wire                                          txc_meta_ready;
+    wire                                          txc_sent;
+
+    // Interface: TXR Engine
+    wire                                          txr_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txr_data;
+    wire                                          txr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_start_offset;
+    wire                                          txr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_end_offset;
+    wire                                          txr_data_ready;
+
+    wire                                          txr_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txr_meta_fdwbe; 
+    wire [`SIG_LBE_W-1:0]                         txr_meta_ldwbe;
+    wire [`SIG_ADDR_W-1:0]                        txr_meta_addr;
+    wire [`SIG_LEN_W-1:0]                         txr_meta_length;
+    wire [`SIG_TAG_W-1:0]                         txr_meta_tag;
+    wire [`SIG_TC_W-1:0]                          txr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txr_meta_attr;
+    wire [`SIG_TYPE_W-1:0]                        txr_meta_type;
+    wire                                          txr_meta_ep;
+    wire                                          txr_meta_ready;
+    wire                                          txr_sent;
+
+    // Unconnected Wires (Used in classic interface)
+    wire                                          wRxTlpReady_nc;
+    wire [C_PCI_DATA_WIDTH-1:0]                   wRxTlp_nc = 0;
+    wire                                          wRxTlpEndFlag_nc = 0;
+    wire [`SIG_OFFSET_W-1:0]                      wRxTlpEndOffset_nc = 0;
+    wire                                          wRxTlpStartFlag_nc = 0;
+    wire [`SIG_OFFSET_W-1:0]                      wRxTlpStartOffset_nc = 0;
+    wire                                          wRxTlpValid_nc = 0;
+    wire [`SIG_BARDECODE_W-1:0]                   wRxTlpBarDecode_nc = 0;
+    
+    wire                                          wTxTlpReady_nc = 0;
+    wire [C_PCI_DATA_WIDTH-1:0]                   wTxTlp_nc;
+    wire                                          wTxTlpEndFlag_nc;
+    wire [`SIG_OFFSET_W-1:0]                      wTxTlpEndOffset_nc;
+    wire                                          wTxTlpStartFlag_nc;
+    wire [`SIG_OFFSET_W-1:0]                      wTxTlpStartOffset_nc;
+    wire                                          wTxTlpValid_nc;
+
+    //--------------------------------------------------------------------------
+
+    // Interface: Configuration
+    wire                                          config_bus_master_enable;
+    wire [`SIG_CPLID_W-1:0]                       config_completer_id;
+    wire                                          config_cpl_boundary_sel;
+    wire                                          config_interrupt_msienable;
+    wire [`SIG_LINKRATE_W-1:0]                    config_link_rate;
+    wire [`SIG_LINKWIDTH_W-1:0]                   config_link_width;
+    wire [`SIG_MAXPAYLOAD_W-1:0]                  config_max_payload_size;
+    wire [`SIG_MAXREAD_W-1:0]                     config_max_read_request_size;
+    wire [`SIG_FC_CPLD_W-1:0]                     config_max_cpl_data;
+    wire [`SIG_FC_CPLH_W-1:0]                     config_max_cpl_hdr;
+
+    wire                                          intr_msi_request;
+    wire                                          intr_msi_rdy;
+
+    genvar                                        chnl;
+
+    assign clk = USER_CLK;
+    assign rst_in = USER_RESET;
+
+    assign config_completer_id = 0; // Not used in ULTRASCALE implementation
+    assign config_bus_master_enable = CFG_FUNCTION_STATUS[2];
+    assign config_link_width = {2'b00,CFG_NEGOTIATED_WIDTH}; // CONFIG_LINK_WIDTH
+    assign config_link_rate = CFG_CURRENT_SPEED[2]? 2'b11 : CFG_CURRENT_SPEED[2] ? 2'b10 : 2'b01;
+    assign config_max_payload_size = CFG_MAX_PAYLOAD; // CONFIG_MAX_PAYLOAD
+    assign config_max_read_request_size = CFG_MAX_READ_REQ; // CONFIG_MAX_READ_REQUEST
+    assign config_cpl_boundary_sel =  CFG_RCB_STATUS[0];
+    assign config_interrupt_msienable = CFG_INTERRUPT_MSI_ENABLE[0];
+    assign config_max_cpl_data = CFG_FC_CPLD;    
+    assign config_max_cpl_hdr = CFG_FC_CPLH;    
+
+    assign CFG_FC_SEL = 3'b001; // Always display credit maximum for the signals below
+    assign CFG_INTERRUPT_MSI_INT = {31'b0,intr_msi_request};
+    assign CFG_INTERRUPT_MSI_SELECT = 0;
+    assign CFG_INTERRUPT_INT = 0;
+    assign CFG_INTERRUPT_PENDING = 0;
+    assign CFG_INTERRUPT_MSI_SELECT = 0;
+    assign CFG_INTERRUPT_MSI_PENDING_STATUS = {63'b0,intr_msi_request};
+    assign CFG_INTERRUPT_MSI_ATTR = 0;
+    assign CFG_INTERRUPT_MSI_TPH_PRESENT = 0;
+    assign CFG_INTERRUPT_MSI_TPH_ST_TAG = 0;
+    assign CFG_INTERRUPT_MSI_TPH_TYPE = 0;
+    assign CFG_INTERRUPT_MSI_FUNCTION_NUMBER = 0;
+    
+    assign intr_msi_rdy = CFG_INTERRUPT_MSI_SENT & ~CFG_INTERRUPT_MSI_FAIL;
+
+    assign PCIE_CQ_NP_REQ = 1;
+    
+    engine_layer
+        #(// Parameters
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_BYTES/4),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_VENDOR                     (C_VENDOR))
+    engine_layer_inst
+        (// Outputs
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+
+         .RST_LOGIC                     (RST_OUT),
+         // Unconnected Outputs
+         .TX_TLP                        (wTxTlp_nc),
+         .TX_TLP_VALID                  (wTxTlpValid_nc),
+         .TX_TLP_START_FLAG             (wTxTlpStartFlag_nc),
+         .TX_TLP_START_OFFSET           (wTxTlpStartOffset_nc),
+         .TX_TLP_END_FLAG               (wTxTlpEndFlag_nc),
+         .TX_TLP_END_OFFSET             (wTxTlpEndOffset_nc),
+
+         .RX_TLP_READY                  (wRxTlpReady_nc),
+         // Inputs
+         .CLK_BUS                       (clk),
+         .RST_BUS                       (rst_in),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+         // Unconnected Inputs
+         .RX_TLP                        (wRxTlp_nc),
+         .RX_TLP_VALID                  (wRxTlpValid_nc),
+         .RX_TLP_START_FLAG             (wRxTlpStartFlag_nc),
+         .RX_TLP_START_OFFSET           (wRxTlpStartOffset_nc),
+         .RX_TLP_END_FLAG               (wRxTlpEndFlag_nc),
+         .RX_TLP_END_OFFSET             (wRxTlpEndOffset_nc),
+         .RX_TLP_BAR_DECODE             (wRxTlpBarDecode_nc),
+
+         .TX_TLP_READY                  (wTxTlpReady_nc),
+         .DONE_TXC_RST                  (done_txc_rst),
+         .DONE_TXR_RST                  (done_txr_rst),
+         .DONE_RXR_RST                  (done_rxc_rst),
+         .DONE_RXC_RST                  (done_rxr_rstsudo),
+         /*AUTOINST*/
+         // Outputs
+         .M_AXIS_CQ_TREADY              (M_AXIS_CQ_TREADY),
+         .M_AXIS_RC_TREADY              (M_AXIS_RC_TREADY),
+         .S_AXIS_CC_TVALID              (S_AXIS_CC_TVALID),
+         .S_AXIS_CC_TLAST               (S_AXIS_CC_TLAST),
+         .S_AXIS_CC_TDATA               (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (S_AXIS_RQ_TVALID),
+         .S_AXIS_RQ_TLAST               (S_AXIS_RQ_TLAST),
+         .S_AXIS_RQ_TDATA               (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (M_AXIS_CQ_TVALID),
+         .M_AXIS_CQ_TLAST               (M_AXIS_CQ_TLAST),
+         .M_AXIS_CQ_TDATA               (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (M_AXIS_CQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (M_AXIS_CQ_TUSER[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (M_AXIS_RC_TVALID),
+         .M_AXIS_RC_TLAST               (M_AXIS_RC_TLAST),
+         .M_AXIS_RC_TDATA               (M_AXIS_RC_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (M_AXIS_RC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (M_AXIS_RC_TUSER[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (S_AXIS_CC_TREADY),
+         .S_AXIS_RQ_TREADY              (S_AXIS_RQ_TREADY));
+
+    riffa
+        #(.C_TAG_WIDTH                  (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_MAX_READ_REQ_BYTES         (C_MAX_READ_REQ_BYTES),
+          .C_VENDOR                     (C_VENDOR),
+          .C_FPGA_NAME                  (C_FPGA_NAME),
+          .C_FPGA_ID                    (C_FPGA_ID),
+          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS))
+    riffa_inst
+        (// Outputs
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+
+         .INTR_MSI_REQUEST              (intr_msi_request),
+         // Inputs
+         .CLK                           (clk),
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),         
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE      (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH             (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE              (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE  (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE       (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE    (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL       (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA           (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR            (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+        
+         .INTR_MSI_RDY                  (intr_msi_rdy),
+
+         .DONE_TXC_RST                  (done_txc_rst),
+         .DONE_TXR_RST                  (done_txr_rst),
+         .RST_BUS                       (rst_in),
+         /*AUTOINST*/
+         // Outputs
+         .RST_OUT                       (RST_OUT),
+         .CHNL_RX                       (CHNL_RX[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_RX_OFF                   (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_RX_DATA                  (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
+         // Inputs
+         .CHNL_RX_CLK                   (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (CHNL_TX[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_TX_OFF                   (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_TX_DATA                  (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("../../riffa_hdl/")
+// End:
+

fpga/xilinx/adm-pcie-7v3/7V3_Gen1x8If64/ip/PCIeGen1x8If64.xci

@@ -232,7 +232,7 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_scale">Kilobytes</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_sub">80</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.extended_tag_field">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.extended_tag_field">true</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_type">N/A</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
@@ -375,7 +375,7 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_LTR_SUPPORT">FALSE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_OBFF_SUPPORT">00</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_EXT_TAG_SUPPORTED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_EXT_TAG_SUPPORTED">TRUE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">FALSE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_MAX_PAYLOAD_SIZE">0b010</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_NEXTPTR">0x000</spirit:configurableElementValue>

fpga/xilinx/adm-pcie-7v3/7V3_Gen2x8If128/hdl/ADM_PCIe_7V3Gen2x8If128.v

@@ -48,7 +48,7 @@ module ADM_PCIe_7V3Gen2x8If128
     #(// Number of RIFFA Channels
       parameter C_NUM_CHNL = 1,
       // Number of PCIe Lanes
-      parameter C_NUM_LANES =  4,
+      parameter C_NUM_LANES =  8,
       // Settings from Vivado IP Generator
       parameter C_PCI_DATA_WIDTH = 128,
       parameter C_MAX_PAYLOAD_BYTES = 256,

fpga/xilinx/kc705/KC705_Gen1x8If64/constr/KC705_Top.xdc

@@ -0,0 +1,117 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            KC705_Top.xdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Xilinx Design Constraints for the KC705 (REVC) board.
+# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin
+#
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------#
+#
+###############################################################################
+# User Time Names / User Time Groups / Time Specs
+###############################################################################
+
+###############################################################################
+# User Physical Constraints
+###############################################################################
+
+
+###############################################################################
+# Timing Constraints
+###############################################################################
+
+
+create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O]
+
+###############################################################################
+# Pinout and Related I/O Constraints
+###############################################################################
+
+#
+# SYS reset (input) signal.  The sys_reset_n signal should be
+# obtained from the PCI Express interface if possible.  For
+# slot based form factors, a system reset signal is usually
+# present on the connector.  For cable based form factors, a
+# system reset signal may not be available.  In this case, the
+# system reset signal must be generated locally by some form of
+# supervisory circuit.  You may change the IOSTANDARD and LOC
+# to suit your requirements and VCCO voltage banking rules.
+# Some 7 series devices do not have 3.3 V I/Os available.
+# Therefore the appropriate level shift is required to operate
+# with these devices that contain only 1.8 V banks.
+#
+
+set_property IOSTANDARD LVCMOS25 [get_ports PCIE_RESET_N]
+set_property PULLUP true [get_ports PCIE_RESET_N]
+set_property LOC G25 [get_ports PCIE_RESET_N]
+
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[1]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[2]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[3]}]
+
+set_property LOC AB8 [get_ports {LED[0]}]
+set_property LOC AA8 [get_ports {LED[1]}]
+set_property LOC AC9 [get_ports {LED[2]}]
+set_property LOC AB9 [get_ports {LED[3]}]
+
+set_false_path -to [get_ports -filter {NAME=~LED*}]
+
+
+###############################################################################
+# Physical Constraints
+###############################################################################
+#
+# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
+# signals are the PCI Express reference clock. Virtex-7 GT
+# Transceiver architecture requires the use of a dedicated clock
+# resources (FPGA input pins) associated with each GT Transceiver.
+# To use these pins an IBUFDS primitive (refclk_ibuf) is
+# instantiated in user's design.
+# Please refer to the Virtex-7 GT Transceiver User Guide
+# (UG) for guidelines regarding clock resource selection.
+#
+
+set_property LOC IBUFDS_GTE2_X0Y1 [get_cells refclk_ibuf]
+
+set_false_path -from [get_ports PCIE_RESET_N]
+
+
+###############################################################################
+# End
+###############################################################################

fpga/xilinx/kc705/KC705_Gen1x8If64/hdl/KC705Gen1x8If64.v

@@ -0,0 +1,402 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            KC705Gen1x8If64.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Xilinx KC705 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "tlp.vh"
+`include "xilinx.vh"
+`timescale 1ps / 1ps
+module KC705Gen1x8If64
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 64,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
+     output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXP,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXN,
+
+     output [3:0]                   LED,
+     input                          PCIE_REFCLK_P,
+     input                          PCIE_REFCLK_N,
+     input                          PCIE_RESET_N
+     );
+
+    wire                            pcie_refclk;
+    wire                            pcie_reset_n;
+
+    wire                            user_clk;
+    wire                            user_reset;
+    wire                            user_lnk_up;
+    wire                            user_app_rdy;
+    
+    wire                            s_axis_tx_tready;
+    wire [C_PCI_DATA_WIDTH-1 : 0]   s_axis_tx_tdata;
+    wire [(C_PCI_DATA_WIDTH/8)-1 : 0] s_axis_tx_tkeep;
+    wire                              s_axis_tx_tlast;
+    wire                              s_axis_tx_tvalid;
+    wire [`SIG_XIL_TX_TUSER_W : 0]    s_axis_tx_tuser;
+    
+    wire [C_PCI_DATA_WIDTH-1 : 0]     m_axis_rx_tdata;
+    wire [(C_PCI_DATA_WIDTH/8)-1 : 0] m_axis_rx_tkeep;
+    wire                              m_axis_rx_tlast;
+    wire                              m_axis_rx_tvalid;
+    wire                              m_axis_rx_tready;
+    wire [`SIG_XIL_RX_TUSER_W - 1 : 0] m_axis_rx_tuser;
+
+    wire                               tx_cfg_gnt;
+    wire                               rx_np_ok;
+    wire                               rx_np_req;
+    wire                               cfg_turnoff_ok;
+    wire                               cfg_trn_pending;
+    wire                               cfg_pm_halt_aspm_l0s;
+    wire                               cfg_pm_halt_aspm_l1;
+    wire                               cfg_pm_force_state_en;
+    wire [1:0]                         cfg_pm_force_state;
+    wire                               cfg_pm_wake;
+    wire [63:0]                        cfg_dsn;
+
+    wire [11 : 0]                      fc_cpld;
+    wire [7 : 0]                       fc_cplh;
+    wire [11 : 0]                      fc_npd;
+    wire [7 : 0]                       fc_nph;
+    wire [11 : 0]                      fc_pd;
+    wire [7 : 0]                       fc_ph;
+    wire [2 : 0]                       fc_sel;
+    
+    wire [15 : 0]                      cfg_status;
+    wire [15 : 0]                      cfg_command;
+    wire [15 : 0]                      cfg_dstatus;
+    wire [15 : 0]                      cfg_dcommand;
+    wire [15 : 0]                      cfg_lstatus;
+    wire [15 : 0]                      cfg_lcommand;
+    wire [15 : 0]                      cfg_dcommand2;
+    
+    wire [2 : 0]                       cfg_pcie_link_state;
+    wire                               cfg_pmcsr_pme_en;
+    wire [1 : 0]                       cfg_pmcsr_powerstate;
+    wire                               cfg_pmcsr_pme_status;
+    wire                               cfg_received_func_lvl_rst;
+    wire [4 : 0]                       cfg_pciecap_interrupt_msgnum;
+    wire                               cfg_to_turnoff;
+    wire [7 : 0]                       cfg_bus_number;
+    wire [4 : 0]                       cfg_device_number;
+    wire [2 : 0]                       cfg_function_number;
+
+    wire                               cfg_interrupt;
+    wire                               cfg_interrupt_rdy;
+    wire                               cfg_interrupt_assert;
+    wire [7 : 0]                       cfg_interrupt_di;
+    wire [7 : 0]                       cfg_interrupt_do;
+    wire [2 : 0]                       cfg_interrupt_mmenable;
+    wire                               cfg_interrupt_msienable;
+    wire                               cfg_interrupt_msixenable;
+    wire                               cfg_interrupt_msixfm;
+    wire                               cfg_interrupt_stat;
+    
+
+
+    wire                               rst_out;
+    wire [C_NUM_CHNL-1:0]              chnl_rx_clk; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx_ack; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_rx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_ren;
+
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_clk; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_tx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_ren;
+
+    genvar                                     chnl;
+
+    assign cfg_turnoff_ok = 0;
+    assign cfg_trn_pending = 0;
+    assign cfg_pm_halt_aspm_l0s = 0;
+    assign cfg_pm_halt_aspm_l1 = 0;
+    assign cfg_pm_force_state_en = 0;
+    assign cfg_pm_force_state = 0;
+    assign cfg_dsn = 0;
+    assign cfg_interrupt_assert = 0;
+    assign cfg_interrupt_di = 0;
+    assign cfg_interrupt_stat = 0;
+    assign cfg_pciecap_interrupt_msgnum = 0;
+    assign cfg_turnoff_ok = 0;
+    assign cfg_pm_wake = 0;
+
+    IBUF 
+        #()  
+    pci_reset_n_ibuf 
+        (.O(pcie_reset_n), 
+         .I(PCIE_RESET_N));
+
+    IBUFDS_GTE2 
+        #()
+    refclk_ibuf 
+        (.O(pcie_refclk), 
+         .ODIV2(), 
+         .I(PCIE_REFCLK_P), 
+         .CEB(1'b0), 
+         .IB(PCIE_REFCLK_N));
+
+    // Core Top Level Wrapper
+
+    PCIeGen1x8If64 PCIeGen1x8If64_i
+        (//---------------------------------------------------------------------
+         // PCI Express (pci_exp) Interface                                     
+         //---------------------------------------------------------------------
+         // Tx
+         .pci_exp_txn                               ( PCI_EXP_TXN ),
+         .pci_exp_txp                               ( PCI_EXP_TXP ),
+        
+         // Rx
+         .pci_exp_rxn                               ( PCI_EXP_RXN ),
+         .pci_exp_rxp                               ( PCI_EXP_RXP ),
+        
+         //---------------------------------------------------------------------
+         // AXI-S Interface                                                     
+         //---------------------------------------------------------------------
+         // Common
+         .user_clk_out                              ( user_clk ),
+         .user_reset_out                            ( user_reset ),
+         .user_lnk_up                               ( user_lnk_up ),
+         .user_app_rdy                              ( user_app_rdy ),
+        
+         // TX
+         .s_axis_tx_tready                          ( s_axis_tx_tready ),
+         .s_axis_tx_tdata                           ( s_axis_tx_tdata ),
+         .s_axis_tx_tkeep                           ( s_axis_tx_tkeep ),
+         .s_axis_tx_tuser                           ( s_axis_tx_tuser ),
+         .s_axis_tx_tlast                           ( s_axis_tx_tlast ),
+         .s_axis_tx_tvalid                          ( s_axis_tx_tvalid ),
+        
+         // Rx
+         .m_axis_rx_tdata                           ( m_axis_rx_tdata ),
+         .m_axis_rx_tkeep                           ( m_axis_rx_tkeep ),
+         .m_axis_rx_tlast                           ( m_axis_rx_tlast ),
+         .m_axis_rx_tvalid                          ( m_axis_rx_tvalid ),
+         .m_axis_rx_tready                          ( m_axis_rx_tready ),
+         .m_axis_rx_tuser                           ( m_axis_rx_tuser ),
+
+         .tx_cfg_gnt                                ( tx_cfg_gnt ),
+         .rx_np_ok                                  ( rx_np_ok ),
+         .rx_np_req                                 ( rx_np_req ),
+         .cfg_trn_pending                           ( cfg_trn_pending ),
+         .cfg_pm_halt_aspm_l0s                      ( cfg_pm_halt_aspm_l0s ),
+         .cfg_pm_halt_aspm_l1                       ( cfg_pm_halt_aspm_l1 ),
+         .cfg_pm_force_state_en                     ( cfg_pm_force_state_en ),
+         .cfg_pm_force_state                        ( cfg_pm_force_state ),
+         .cfg_dsn                                   ( cfg_dsn ),
+         .cfg_turnoff_ok                            ( cfg_turnoff_ok ),
+         .cfg_pm_wake                               ( cfg_pm_wake ),
+         .cfg_pm_send_pme_to                        ( 1'b0 ),
+         .cfg_ds_bus_number                         ( 8'b0 ),
+         .cfg_ds_device_number                      ( 5'b0 ),
+         .cfg_ds_function_number                    ( 3'b0 ),
+
+         //---------------------------------------------------------------------
+         // Flow Control Interface                                              
+         //---------------------------------------------------------------------
+         .fc_cpld                                   ( fc_cpld ),
+         .fc_cplh                                   ( fc_cplh ),
+         .fc_npd                                    ( fc_npd ),
+         .fc_nph                                    ( fc_nph ),
+         .fc_pd                                     ( fc_pd ),
+         .fc_ph                                     ( fc_ph ),
+         .fc_sel                                    ( fc_sel ),
+         
+         //---------------------------------------------------------------------
+         // Configuration (CFG) Interface                                       
+         //---------------------------------------------------------------------
+         .cfg_device_number                         ( cfg_device_number ),
+         .cfg_dcommand2                             ( cfg_dcommand2 ),
+         .cfg_pmcsr_pme_status                      ( cfg_pmcsr_pme_status ),
+         .cfg_status                                ( cfg_status ),
+         .cfg_to_turnoff                            ( cfg_to_turnoff ),
+         .cfg_received_func_lvl_rst                 ( cfg_received_func_lvl_rst ),
+         .cfg_dcommand                              ( cfg_dcommand ),
+         .cfg_bus_number                            ( cfg_bus_number ),
+         .cfg_function_number                       ( cfg_function_number ),
+         .cfg_command                               ( cfg_command ),
+         .cfg_dstatus                               ( cfg_dstatus ),
+         .cfg_lstatus                               ( cfg_lstatus ),
+         .cfg_pcie_link_state                       ( cfg_pcie_link_state ),
+         .cfg_lcommand                              ( cfg_lcommand ),
+         .cfg_pmcsr_pme_en                          ( cfg_pmcsr_pme_en ),
+         .cfg_pmcsr_powerstate                      ( cfg_pmcsr_powerstate ),
+         
+         //------------------------------------------------//
+         // EP Only                                        //
+         //------------------------------------------------//
+         .cfg_interrupt                             ( cfg_interrupt ),
+         .cfg_interrupt_rdy                         ( cfg_interrupt_rdy ),
+         .cfg_interrupt_assert                      ( cfg_interrupt_assert ),
+         .cfg_interrupt_di                          ( cfg_interrupt_di ),
+         .cfg_interrupt_do                          ( cfg_interrupt_do ),
+         .cfg_interrupt_mmenable                    ( cfg_interrupt_mmenable ),
+         .cfg_interrupt_msienable                   ( cfg_interrupt_msienable ),
+         .cfg_interrupt_msixenable                  ( cfg_interrupt_msixenable ),
+         .cfg_interrupt_msixfm                      ( cfg_interrupt_msixfm ),
+         .cfg_interrupt_stat                        ( cfg_interrupt_stat ),
+         .cfg_pciecap_interrupt_msgnum              ( cfg_pciecap_interrupt_msgnum ),
+         //---------------------------------------------------------------------
+         // System  (SYS) Interface                                             
+         //---------------------------------------------------------------------
+         .sys_clk                                    ( pcie_refclk ),
+         .sys_rst_n                                  ( pcie_reset_n )
+         
+         );
+
+
+    riffa_wrapper_kc705
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .CFG_INTERRUPT                 (cfg_interrupt),
+         .M_AXIS_RX_TREADY              (m_axis_rx_tready),
+         .S_AXIS_TX_TDATA               (s_axis_tx_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_TX_TKEEP               (s_axis_tx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .S_AXIS_TX_TLAST               (s_axis_tx_tlast),
+         .S_AXIS_TX_TVALID              (s_axis_tx_tvalid),
+         .S_AXIS_TX_TUSER               (s_axis_tx_tuser[`SIG_XIL_TX_TUSER_W-1:0]),
+         .FC_SEL                        (fc_sel[`SIG_FC_SEL_W-1:0]),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .M_AXIS_RX_TDATA               (m_axis_rx_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RX_TKEEP               (m_axis_rx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .M_AXIS_RX_TLAST               (m_axis_rx_tlast),
+         .M_AXIS_RX_TVALID              (m_axis_rx_tvalid),
+         .M_AXIS_RX_TUSER               (m_axis_rx_tuser[`SIG_XIL_RX_TUSER_W-1:0]),
+         .S_AXIS_TX_TREADY              (s_axis_tx_tready),
+         .CFG_BUS_NUMBER                (cfg_bus_number[`SIG_BUSID_W-1:0]),
+         .CFG_DEVICE_NUMBER             (cfg_device_number[`SIG_DEVID_W-1:0]),
+         .CFG_FUNCTION_NUMBER           (cfg_function_number[`SIG_FNID_W-1:0]),
+         .CFG_COMMAND                   (cfg_command[`SIG_CFGREG_W-1:0]),
+         .CFG_DCOMMAND                  (cfg_dcommand[`SIG_CFGREG_W-1:0]),
+         .CFG_LSTATUS                   (cfg_lstatus[`SIG_CFGREG_W-1:0]),
+         .CFG_LCOMMAND                  (cfg_lcommand[`SIG_CFGREG_W-1:0]),
+         .FC_CPLD                       (fc_cpld[`SIG_FC_CPLD_W-1:0]),
+         .FC_CPLH                       (fc_cplh[`SIG_FC_CPLH_W-1:0]),
+         .CFG_INTERRUPT_MSIEN           (cfg_interrupt_msienable),// TODO: Rename
+         .CFG_INTERRUPT_RDY             (cfg_interrupt_rdy),
+         .USER_CLK                      (user_clk),
+         .USER_RESET                    (user_reset),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]),
+         .RX_NP_OK                      (rx_np_ok),
+         .TX_CFG_GNT                    (tx_cfg_gnt),
+         .RX_NP_REQ                     (rx_np_req)
+         /*AUTOINST*/);
+
+    generate
+        for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
+            chnl_tester 
+                    #(
+                      .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                      ) 
+            module1 
+                    (.CLK(user_clk),
+                     .RST(rst_out),    // riffa_reset includes riffa_endpoint resets
+                     // Rx interface
+                     .CHNL_RX_CLK(chnl_rx_clk[chnl]), 
+                     .CHNL_RX(chnl_rx[chnl]), 
+                     .CHNL_RX_ACK(chnl_rx_ack[chnl]), 
+                     .CHNL_RX_LAST(chnl_rx_last[chnl]), 
+                     .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), 
+                     .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), 
+                     .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), 
+                     .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
+                     // Tx interface
+                     .CHNL_TX_CLK(chnl_tx_clk[chnl]), 
+                     .CHNL_TX(chnl_tx[chnl]), 
+                     .CHNL_TX_ACK(chnl_tx_ack[chnl]), 
+                     .CHNL_TX_LAST(chnl_tx_last[chnl]), 
+                     .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), 
+                     .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), 
+                     .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), 
+                     .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
+                     );    
+        end
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/" "../..")
+// End:
+

fpga/xilinx/kc705/KC705_Gen1x8If64/ip/PCIeGen1x8If64.xci

@@ -0,0 +1,479 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>PCIeGen1x8If64</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie_7x" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Advanced</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">PCIeGen1x8If64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_Port_Type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Maximum_Link_Width">X8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Link_Speed">2.5_GT/s</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Width">64_bit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.User_Clk_Freq">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Enabled">true</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Size">2</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Type">N/A</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Scale">Kilobytes</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Enabled">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IO_Base_Limit_Registers">Disabled</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Vendor_ID">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_ID">7018</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Revision_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Subsystem_Vendor_ID">10EE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RCB">64_byte</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Trgt_Link_Speed">4&apos;h1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Hw_Auton_Spd_Disable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.De_emph">-3.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Slot_Clock_Cfg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Root_Cap_CRS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Attn_Butn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Ctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_MRL">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Attn_Ind">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Ind">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_HotPlug_Surprise">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_HotPlug_Cap">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Elec_Interlock">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_No_Cmd_Comp_Sup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Limit_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Limit_Scale">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Physical_Slot_Num">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IntX_Generation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Legacy_Interrupt">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_64b">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Multiple_Message_Capable">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_Vec_Mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_Size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_Offset">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_PBA_Offset">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_Specific_Initialization">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3hot_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3cold_PME_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Soft_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DSN_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VC_Cap_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VC_Cap_Reject_Snoop">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VSEC_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCI_CFG_Space">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCI_CFG_Space_Addr">3F</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXT_PCI_CFG_Space">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXT_PCI_CFG_Space_Addr">3FF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Xlnx_Ref_Board">KC705_REVC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Blk_Locn">X0Y0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Trans_Buf_Pipeline">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_unlock">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pme_to">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_cor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_nfl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_ftl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_inta">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pm_pme">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pme_to_ack">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Receive_NP_Request">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ACK_NAK_Timer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACK_NAK_Timeout_Func">Absolute</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACK_NAK_Timeout_Value">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Replay_Timer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Replay_Timeout_Func">Add</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Replay_Timeout_Value">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Lane_Reversal">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Upconfigure_Capable">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Force_No_Scrambling">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Tx_ASPM_L0s">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Downstream_Link_Num">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_INV_REQ">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_PRS_RESPONSE">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Silicon_Rev">GES_and_Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pcie_fast_config">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Debug_Ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Ref_Clk_Freq">100_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cost_Table">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_Atomic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ATOMICOP32_Completer_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ATOMICOP64_Completer_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CAS128_Completer_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TPH_Completer_Supported">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARI_Forwarding_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AtomicOp_Routing_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASPM_Optionality">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Check_Capable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Gen_Capable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Multiheader">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Permit_Root_Error_Update">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Correctable_Internal_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Header_Log_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Receiver_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Surprise_Down">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Flow_Control_Protocol_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Completion_Timeout">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Completer_Abort">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Receiver_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ACS_Violation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Uncorrectable_Internal_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_MC_Blocked_TLP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_AtomicOp_Egress_Blocked">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_TLP_Prefix_Blocked">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optional_Error_Support">000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Num">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR0_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR1_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR2_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR3_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR4_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR5_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECRC_Check">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECRC_Check_Trim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Rx_Poisoned_Resp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_gt_common">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.shared_logic_in_core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pl_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_mgmt_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ctl_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_status_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rcv_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_fc_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.err_reporting_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_pipe_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_startup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_mode_sim">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">PCIeGen1x8If64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dev_port_type">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_dev_port_type">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_header_type">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_upstream_facing">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.max_lnk_wdt">001000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.max_lnk_spd">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gen1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pci_exp_int_freq">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_pcie_fast_config">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_0">FFFFFC00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_5">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.xrom_bar">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.cost_table">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ven_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dev_id">7018</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.rev_id">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.subsys_ven_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.subsys_id">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.class_code">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.cardbus_cis_ptr">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.cap_ver">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_pcie_cap_slot_implemented">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.mps">010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.cmps">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ext_tag_fld_sup">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_dev_control_ext_tag_default">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.phantm_func_sup">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_phantom_functions">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ep_l0s_accpt_lat">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_ep_l0s_accpt_lat">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ep_l1_accpt_lat">111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_ep_l1_accpt_lat">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_cpl_timeout_disable_sup">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_cpl_timeout_range">0010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_cpl_timeout_ranges_sup">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_buf_opt_bma">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_perf_level_high">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_tx_last_tlp">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rx_ram_limit">7FF</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_fc_nph">4</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_fc_cpld">850</spirit:configurableElementValue>
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fpga/xilinx/kc705/KC705_Gen1x8If64/prj/KC705_Gen1x8If64.xpr

@@ -0,0 +1,806 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2014.4 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="2" Path="/home/drichmond/Research/repositories/git/riffa/fpga/xilinx/kc705/KC705_Gen1x8If64/prj/KC705_Gen1x8If64.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="91b0f64634d74c568297d2f88f9aee86"/>
+    <Option Name="Part" Val="xc7k325tffg900-2"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="BoardPart" Val="xilinx.com:kc705:part0:1.1"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../../../../riffa_hdl/shiftreg.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/functions.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/scsdpram.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/fifo.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/ff.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/syncff.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
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+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/interrupt.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/channel.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/xilinx.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/translation_xilinx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/riffa.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/engine_layer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../riffa_wrapper_kc705.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/chnl_tester.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../hdl/KC705Gen1x8If64.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../riffa_hdl/altera.vh">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="KC705Gen1x8If64"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../constr/KC705_Top.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/../constr/KC705_Top.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="KC705Gen1x8If64"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="PCIeGen1x8If64" Type="BlockSrcs" RelSrcDir="$PSRCDIR/PCIeGen1x8If64">
+      <File Path="$PPRDIR/../ip/PCIeGen1x8If64.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="PCIeGen1x8If64"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="9">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k325tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen1x8If64_synth_1" Type="Ft3:Synth" SrcSet="PCIeGen1x8If64" Part="xc7k325tffg900-2" ConstrsSet="PCIeGen1x8If64" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/PCIeGen1x8If64_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen1x8If64_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="PCIeGen1x8If64" Description="Vivado Implementation Defaults" SynthRun="PCIeGen1x8If64_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+  </Runs>
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</Project>

fpga/xilinx/kc705/KC705_Gen2x8If128/constr/KC705_Top.xdc

@@ -0,0 +1,117 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# Filename:            KC705_Top.xdc
+# Version:             1.00.a
+# Verilog Standard:    Verilog-2001
+# Description:         Xilinx Design Constraints for the KC705 (REVC) board.
+# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin
+#
+# Author:              Dustin Richmond (@darichmond)
+#-----------------------------------------------------------------------------#
+#
+###############################################################################
+# User Time Names / User Time Groups / Time Specs
+###############################################################################
+
+###############################################################################
+# User Physical Constraints
+###############################################################################
+
+
+###############################################################################
+# Timing Constraints
+###############################################################################
+
+
+create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O]
+
+###############################################################################
+# Pinout and Related I/O Constraints
+###############################################################################
+
+#
+# SYS reset (input) signal.  The sys_reset_n signal should be
+# obtained from the PCI Express interface if possible.  For
+# slot based form factors, a system reset signal is usually
+# present on the connector.  For cable based form factors, a
+# system reset signal may not be available.  In this case, the
+# system reset signal must be generated locally by some form of
+# supervisory circuit.  You may change the IOSTANDARD and LOC
+# to suit your requirements and VCCO voltage banking rules.
+# Some 7 series devices do not have 3.3 V I/Os available.
+# Therefore the appropriate level shift is required to operate
+# with these devices that contain only 1.8 V banks.
+#
+
+set_property IOSTANDARD LVCMOS25 [get_ports PCIE_RESET_N]
+set_property PULLUP true [get_ports PCIE_RESET_N]
+set_property LOC G25 [get_ports PCIE_RESET_N]
+
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[1]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[2]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {LED[3]}]
+
+set_property LOC AB8 [get_ports {LED[0]}]
+set_property LOC AA8 [get_ports {LED[1]}]
+set_property LOC AC9 [get_ports {LED[2]}]
+set_property LOC AB9 [get_ports {LED[3]}]
+
+set_false_path -to [get_ports -filter {NAME=~LED*}]
+
+
+###############################################################################
+# Physical Constraints
+###############################################################################
+#
+# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
+# signals are the PCI Express reference clock. Virtex-7 GT
+# Transceiver architecture requires the use of a dedicated clock
+# resources (FPGA input pins) associated with each GT Transceiver.
+# To use these pins an IBUFDS primitive (refclk_ibuf) is
+# instantiated in user's design.
+# Please refer to the Virtex-7 GT Transceiver User Guide
+# (UG) for guidelines regarding clock resource selection.
+#
+
+set_property LOC IBUFDS_GTE2_X0Y1 [get_cells refclk_ibuf]
+
+set_false_path -from [get_ports PCIE_RESET_N]
+
+
+###############################################################################
+# End
+###############################################################################

fpga/xilinx/kc705/KC705_Gen2x8If128/hdl/KC705Gen2x8If128.v

@@ -0,0 +1,402 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            KC705Gen2x8If128.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         Top level module for RIFFA 2.2 reference design for the
+//                      the Xilinx KC705 Development Board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "tlp.vh"
+`include "xilinx.vh"
+`timescale 1ps / 1ps
+module KC705Gen2x8If128
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Number of PCIe Lanes
+      parameter C_NUM_LANES =  8,
+      // Settings from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 64,
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5
+      ) 
+    (output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
+     output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXP,
+     input [(C_NUM_LANES - 1) : 0]  PCI_EXP_RXN,
+
+     output [3:0]                   LED,
+     input                          PCIE_REFCLK_P,
+     input                          PCIE_REFCLK_N,
+     input                          PCIE_RESET_N
+     );
+
+    wire                            pcie_refclk;
+    wire                            pcie_reset_n;
+
+    wire                            user_clk;
+    wire                            user_reset;
+    wire                            user_lnk_up;
+    wire                            user_app_rdy;
+    
+    wire                            s_axis_tx_tready;
+    wire [C_PCI_DATA_WIDTH-1 : 0]   s_axis_tx_tdata;
+    wire [(C_PCI_DATA_WIDTH/8)-1 : 0] s_axis_tx_tkeep;
+    wire                              s_axis_tx_tlast;
+    wire                              s_axis_tx_tvalid;
+    wire [`SIG_XIL_TX_TUSER_W : 0]    s_axis_tx_tuser;
+    
+    wire [C_PCI_DATA_WIDTH-1 : 0]     m_axis_rx_tdata;
+    wire [(C_PCI_DATA_WIDTH/8)-1 : 0] m_axis_rx_tkeep;
+    wire                              m_axis_rx_tlast;
+    wire                              m_axis_rx_tvalid;
+    wire                              m_axis_rx_tready;
+    wire [`SIG_XIL_RX_TUSER_W - 1 : 0] m_axis_rx_tuser;
+
+    wire                               tx_cfg_gnt;
+    wire                               rx_np_ok;
+    wire                               rx_np_req;
+    wire                               cfg_turnoff_ok;
+    wire                               cfg_trn_pending;
+    wire                               cfg_pm_halt_aspm_l0s;
+    wire                               cfg_pm_halt_aspm_l1;
+    wire                               cfg_pm_force_state_en;
+    wire [1:0]                         cfg_pm_force_state;
+    wire                               cfg_pm_wake;
+    wire [63:0]                        cfg_dsn;
+
+    wire [11 : 0]                      fc_cpld;
+    wire [7 : 0]                       fc_cplh;
+    wire [11 : 0]                      fc_npd;
+    wire [7 : 0]                       fc_nph;
+    wire [11 : 0]                      fc_pd;
+    wire [7 : 0]                       fc_ph;
+    wire [2 : 0]                       fc_sel;
+    
+    wire [15 : 0]                      cfg_status;
+    wire [15 : 0]                      cfg_command;
+    wire [15 : 0]                      cfg_dstatus;
+    wire [15 : 0]                      cfg_dcommand;
+    wire [15 : 0]                      cfg_lstatus;
+    wire [15 : 0]                      cfg_lcommand;
+    wire [15 : 0]                      cfg_dcommand2;
+    
+    wire [2 : 0]                       cfg_pcie_link_state;
+    wire                               cfg_pmcsr_pme_en;
+    wire [1 : 0]                       cfg_pmcsr_powerstate;
+    wire                               cfg_pmcsr_pme_status;
+    wire                               cfg_received_func_lvl_rst;
+    wire [4 : 0]                       cfg_pciecap_interrupt_msgnum;
+    wire                               cfg_to_turnoff;
+    wire [7 : 0]                       cfg_bus_number;
+    wire [4 : 0]                       cfg_device_number;
+    wire [2 : 0]                       cfg_function_number;
+
+    wire                               cfg_interrupt;
+    wire                               cfg_interrupt_rdy;
+    wire                               cfg_interrupt_assert;
+    wire [7 : 0]                       cfg_interrupt_di;
+    wire [7 : 0]                       cfg_interrupt_do;
+    wire [2 : 0]                       cfg_interrupt_mmenable;
+    wire                               cfg_interrupt_msienable;
+    wire                               cfg_interrupt_msixenable;
+    wire                               cfg_interrupt_msixfm;
+    wire                               cfg_interrupt_stat;
+    
+
+
+    wire                               rst_out;
+    wire [C_NUM_CHNL-1:0]              chnl_rx_clk; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx_ack; 
+    wire [C_NUM_CHNL-1:0]              chnl_rx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_rx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_rx_data_ren;
+
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_clk; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_ack;
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_last; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len; 
+    wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off; 
+    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_tx_data; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_valid; 
+    wire [C_NUM_CHNL-1:0]                      chnl_tx_data_ren;
+
+    genvar                                     chnl;
+
+    assign cfg_turnoff_ok = 0;
+    assign cfg_trn_pending = 0;
+    assign cfg_pm_halt_aspm_l0s = 0;
+    assign cfg_pm_halt_aspm_l1 = 0;
+    assign cfg_pm_force_state_en = 0;
+    assign cfg_pm_force_state = 0;
+    assign cfg_dsn = 0;
+    assign cfg_interrupt_assert = 0;
+    assign cfg_interrupt_di = 0;
+    assign cfg_interrupt_stat = 0;
+    assign cfg_pciecap_interrupt_msgnum = 0;
+    assign cfg_turnoff_ok = 0;
+    assign cfg_pm_wake = 0;
+
+    IBUF 
+        #()  
+    pci_reset_n_ibuf 
+        (.O(pcie_reset_n), 
+         .I(PCIE_RESET_N));
+
+    IBUFDS_GTE2 
+        #()
+    refclk_ibuf 
+        (.O(pcie_refclk), 
+         .ODIV2(), 
+         .I(PCIE_REFCLK_P), 
+         .CEB(1'b0), 
+         .IB(PCIE_REFCLK_N));
+
+    // Core Top Level Wrapper
+
+    PCIeGen2x8If128 PCIeGen1x8If64_i
+        (//---------------------------------------------------------------------
+         // PCI Express (pci_exp) Interface                                     
+         //---------------------------------------------------------------------
+         // Tx
+         .pci_exp_txn                               ( PCI_EXP_TXN ),
+         .pci_exp_txp                               ( PCI_EXP_TXP ),
+        
+         // Rx
+         .pci_exp_rxn                               ( PCI_EXP_RXN ),
+         .pci_exp_rxp                               ( PCI_EXP_RXP ),
+        
+         //---------------------------------------------------------------------
+         // AXI-S Interface                                                     
+         //---------------------------------------------------------------------
+         // Common
+         .user_clk_out                              ( user_clk ),
+         .user_reset_out                            ( user_reset ),
+         .user_lnk_up                               ( user_lnk_up ),
+         .user_app_rdy                              ( user_app_rdy ),
+        
+         // TX
+         .s_axis_tx_tready                          ( s_axis_tx_tready ),
+         .s_axis_tx_tdata                           ( s_axis_tx_tdata ),
+         .s_axis_tx_tkeep                           ( s_axis_tx_tkeep ),
+         .s_axis_tx_tuser                           ( s_axis_tx_tuser ),
+         .s_axis_tx_tlast                           ( s_axis_tx_tlast ),
+         .s_axis_tx_tvalid                          ( s_axis_tx_tvalid ),
+        
+         // Rx
+         .m_axis_rx_tdata                           ( m_axis_rx_tdata ),
+         .m_axis_rx_tkeep                           ( m_axis_rx_tkeep ),
+         .m_axis_rx_tlast                           ( m_axis_rx_tlast ),
+         .m_axis_rx_tvalid                          ( m_axis_rx_tvalid ),
+         .m_axis_rx_tready                          ( m_axis_rx_tready ),
+         .m_axis_rx_tuser                           ( m_axis_rx_tuser ),
+
+         .tx_cfg_gnt                                ( tx_cfg_gnt ),
+         .rx_np_ok                                  ( rx_np_ok ),
+         .rx_np_req                                 ( rx_np_req ),
+         .cfg_trn_pending                           ( cfg_trn_pending ),
+         .cfg_pm_halt_aspm_l0s                      ( cfg_pm_halt_aspm_l0s ),
+         .cfg_pm_halt_aspm_l1                       ( cfg_pm_halt_aspm_l1 ),
+         .cfg_pm_force_state_en                     ( cfg_pm_force_state_en ),
+         .cfg_pm_force_state                        ( cfg_pm_force_state ),
+         .cfg_dsn                                   ( cfg_dsn ),
+         .cfg_turnoff_ok                            ( cfg_turnoff_ok ),
+         .cfg_pm_wake                               ( cfg_pm_wake ),
+         .cfg_pm_send_pme_to                        ( 1'b0 ),
+         .cfg_ds_bus_number                         ( 8'b0 ),
+         .cfg_ds_device_number                      ( 5'b0 ),
+         .cfg_ds_function_number                    ( 3'b0 ),
+
+         //---------------------------------------------------------------------
+         // Flow Control Interface                                              
+         //---------------------------------------------------------------------
+         .fc_cpld                                   ( fc_cpld ),
+         .fc_cplh                                   ( fc_cplh ),
+         .fc_npd                                    ( fc_npd ),
+         .fc_nph                                    ( fc_nph ),
+         .fc_pd                                     ( fc_pd ),
+         .fc_ph                                     ( fc_ph ),
+         .fc_sel                                    ( fc_sel ),
+         
+         //---------------------------------------------------------------------
+         // Configuration (CFG) Interface                                       
+         //---------------------------------------------------------------------
+         .cfg_device_number                         ( cfg_device_number ),
+         .cfg_dcommand2                             ( cfg_dcommand2 ),
+         .cfg_pmcsr_pme_status                      ( cfg_pmcsr_pme_status ),
+         .cfg_status                                ( cfg_status ),
+         .cfg_to_turnoff                            ( cfg_to_turnoff ),
+         .cfg_received_func_lvl_rst                 ( cfg_received_func_lvl_rst ),
+         .cfg_dcommand                              ( cfg_dcommand ),
+         .cfg_bus_number                            ( cfg_bus_number ),
+         .cfg_function_number                       ( cfg_function_number ),
+         .cfg_command                               ( cfg_command ),
+         .cfg_dstatus                               ( cfg_dstatus ),
+         .cfg_lstatus                               ( cfg_lstatus ),
+         .cfg_pcie_link_state                       ( cfg_pcie_link_state ),
+         .cfg_lcommand                              ( cfg_lcommand ),
+         .cfg_pmcsr_pme_en                          ( cfg_pmcsr_pme_en ),
+         .cfg_pmcsr_powerstate                      ( cfg_pmcsr_powerstate ),
+         
+         //------------------------------------------------//
+         // EP Only                                        //
+         //------------------------------------------------//
+         .cfg_interrupt                             ( cfg_interrupt ),
+         .cfg_interrupt_rdy                         ( cfg_interrupt_rdy ),
+         .cfg_interrupt_assert                      ( cfg_interrupt_assert ),
+         .cfg_interrupt_di                          ( cfg_interrupt_di ),
+         .cfg_interrupt_do                          ( cfg_interrupt_do ),
+         .cfg_interrupt_mmenable                    ( cfg_interrupt_mmenable ),
+         .cfg_interrupt_msienable                   ( cfg_interrupt_msienable ),
+         .cfg_interrupt_msixenable                  ( cfg_interrupt_msixenable ),
+         .cfg_interrupt_msixfm                      ( cfg_interrupt_msixfm ),
+         .cfg_interrupt_stat                        ( cfg_interrupt_stat ),
+         .cfg_pciecap_interrupt_msgnum              ( cfg_pciecap_interrupt_msgnum ),
+         //---------------------------------------------------------------------
+         // System  (SYS) Interface                                             
+         //---------------------------------------------------------------------
+         .sys_clk                                    ( pcie_refclk ),
+         .sys_rst_n                                  ( pcie_reset_n )
+         
+         );
+
+
+    riffa_wrapper_kc705
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES))
+    riffa
+        (
+         // Outputs
+         .CFG_INTERRUPT                 (cfg_interrupt),
+         .M_AXIS_RX_TREADY              (m_axis_rx_tready),
+         .S_AXIS_TX_TDATA               (s_axis_tx_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_TX_TKEEP               (s_axis_tx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .S_AXIS_TX_TLAST               (s_axis_tx_tlast),
+         .S_AXIS_TX_TVALID              (s_axis_tx_tvalid),
+         .S_AXIS_TX_TUSER               (s_axis_tx_tuser[`SIG_XIL_TX_TUSER_W-1:0]),
+         .FC_SEL                        (fc_sel[`SIG_FC_SEL_W-1:0]),
+         .RST_OUT                       (rst_out),
+         .CHNL_RX                       (chnl_rx[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (chnl_rx_last[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_RX_OFF                   (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_RX_DATA                  (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (chnl_tx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
+         // Inputs
+         .M_AXIS_RX_TDATA               (m_axis_rx_tdata[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RX_TKEEP               (m_axis_rx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .M_AXIS_RX_TLAST               (m_axis_rx_tlast),
+         .M_AXIS_RX_TVALID              (m_axis_rx_tvalid),
+         .M_AXIS_RX_TUSER               (m_axis_rx_tuser[`SIG_XIL_RX_TUSER_W-1:0]),
+         .S_AXIS_TX_TREADY              (s_axis_tx_tready),
+         .CFG_BUS_NUMBER                (cfg_bus_number[`SIG_BUSID_W-1:0]),
+         .CFG_DEVICE_NUMBER             (cfg_device_number[`SIG_DEVID_W-1:0]),
+         .CFG_FUNCTION_NUMBER           (cfg_function_number[`SIG_FNID_W-1:0]),
+         .CFG_COMMAND                   (cfg_command[`SIG_CFGREG_W-1:0]),
+         .CFG_DCOMMAND                  (cfg_dcommand[`SIG_CFGREG_W-1:0]),
+         .CFG_LSTATUS                   (cfg_lstatus[`SIG_CFGREG_W-1:0]),
+         .CFG_LCOMMAND                  (cfg_lcommand[`SIG_CFGREG_W-1:0]),
+         .FC_CPLD                       (fc_cpld[`SIG_FC_CPLD_W-1:0]),
+         .FC_CPLH                       (fc_cplh[`SIG_FC_CPLH_W-1:0]),
+         .CFG_INTERRUPT_MSIEN           (cfg_interrupt_msienable),// TODO: Rename
+         .CFG_INTERRUPT_RDY             (cfg_interrupt_rdy),
+         .USER_CLK                      (user_clk),
+         .USER_RESET                    (user_reset),
+         .CHNL_RX_CLK                   (chnl_rx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (chnl_rx_ack[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (chnl_tx_clk[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (chnl_tx[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (chnl_tx_last[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
+         .CHNL_TX_OFF                   (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
+         .CHNL_TX_DATA                  (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (chnl_tx_data_valid[C_NUM_CHNL-1:0]),
+         .RX_NP_OK                      (rx_np_ok),
+         .TX_CFG_GNT                    (tx_cfg_gnt),
+         .RX_NP_REQ                     (rx_np_req)
+         /*AUTOINST*/);
+
+    generate
+        for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
+            chnl_tester 
+                    #(
+                      .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
+                      ) 
+            module1 
+                    (.CLK(user_clk),
+                     .RST(rst_out),    // riffa_reset includes riffa_endpoint resets
+                     // Rx interface
+                     .CHNL_RX_CLK(chnl_rx_clk[chnl]), 
+                     .CHNL_RX(chnl_rx[chnl]), 
+                     .CHNL_RX_ACK(chnl_rx_ack[chnl]), 
+                     .CHNL_RX_LAST(chnl_rx_last[chnl]), 
+                     .CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]), 
+                     .CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]), 
+                     .CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]), 
+                     .CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
+                     // Tx interface
+                     .CHNL_TX_CLK(chnl_tx_clk[chnl]), 
+                     .CHNL_TX(chnl_tx[chnl]), 
+                     .CHNL_TX_ACK(chnl_tx_ack[chnl]), 
+                     .CHNL_TX_LAST(chnl_tx_last[chnl]), 
+                     .CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]), 
+                     .CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]), 
+                     .CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]), 
+                     .CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]), 
+                     .CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
+                     );    
+        end
+    endgenerate
+endmodule
+// Local Variables:
+// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/" "../..")
+// End:
+

fpga/xilinx/kc705/KC705_Gen2x8If128/ip/PCIeGen2x8If128.xci

@@ -0,0 +1,479 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>PCIeGen2x8If128</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie_7x" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Advanced</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">PCIeGen2x8If128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_Port_Type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Maximum_Link_Width">X8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Link_Speed">5.0_GT/s</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Width">128_bit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.User_Clk_Freq">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar0_Size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar1_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar2_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar3_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar4_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Bar5_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Expansion_Rom_Size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IO_Base_Limit_Registers">Disabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Prefetchable_Memory_Base_Limit_Registers">Disabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Vendor_ID">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_ID">7018</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Revision_ID">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Subsystem_Vendor_ID">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Subsystem_ID">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Class_Code_Base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Class_Code_Sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Class_Code_Interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Base_Class_Menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Sub_Class_Interface_Menu">Generic_XT_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cardbus_CIS_Pointer">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Cap_Slot_Implemented">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Max_Payload_Size">256_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Extended_Tag_Field">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Extended_Tag_Default">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phantom_Functions">No_function_number_bits_used</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Acceptable_L0s_Latency">Maximum_of_64_ns</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Acceptable_L1_Latency">No_limit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cpl_Finite">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cpl_Timeout_Disable_Sup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cpl_Timeout_Range">Range_B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Buf_Opt_BMA">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Perf_Level">High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dll_Link_Active_Cap">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RCB">64_byte</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Trgt_Link_Speed">4&apos;h1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Hw_Auton_Spd_Disable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.De_emph">-3.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Slot_Clock_Cfg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Root_Cap_CRS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Attn_Butn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Ctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_MRL">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Attn_Ind">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Ind">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_HotPlug_Surprise">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_HotPlug_Cap">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Elec_Interlock">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_No_Cmd_Comp_Sup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Limit_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Pwr_Limit_Scale">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slot_Cap_Physical_Slot_Num">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IntX_Generation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Legacy_Interrupt">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_64b">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Multiple_Message_Capable">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_Vec_Mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Enabled">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_Offset">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_Table_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_PBA_Offset">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSIx_PBA_BIR">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Device_Specific_Initialization">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3hot_PME_Support">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3cold_PME_Support">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Soft_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Consumed">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Consumed_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D0_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D1_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D2_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Dissipated">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.D3_Power_Dissipated_Factor">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DSN_Enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VC_Cap_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VC_Cap_Reject_Snoop">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VSEC_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCI_CFG_Space">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCI_CFG_Space_Addr">3F</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXT_PCI_CFG_Space">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Xlnx_Ref_Board">KC705_REVC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Blk_Locn">X0Y0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Trans_Buf_Pipeline">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_unlock">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pme_to">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_cor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_nfl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_err_ftl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_inta">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_intd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pm_pme">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.En_route_pme_to_ack">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Receive_NP_Request">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ACK_NAK_Timer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACK_NAK_Timeout_Func">Absolute</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACK_NAK_Timeout_Value">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Replay_Timer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Replay_Timeout_Func">Add</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Replay_Timeout_Value">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Lane_Reversal">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Upconfigure_Capable">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Force_No_Scrambling">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Tx_ASPM_L0s">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Downstream_Link_Num">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_INV_REQ">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UR_PRS_RESPONSE">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Silicon_Rev">GES_and_Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pcie_fast_config">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIe_Debug_Ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Ref_Clk_Freq">100_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Cost_Table">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARI_Forwarding_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AtomicOp_Routing_Supported">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASPM_Optionality">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Check_Capable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Gen_Capable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Multiheader">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Permit_Root_Error_Update">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Correctable_Internal_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Header_Log_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Receiver_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Surprise_Down">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Flow_Control_Protocol_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Completion_Timeout">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Completer_Abort">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Receiver_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ECRC_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_ACS_Violation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_Uncorrectable_Internal_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_MC_Blocked_TLP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_AtomicOp_Egress_Blocked">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AER_TLP_Prefix_Blocked">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optional_Error_Support">000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Enabled">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value0">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR1_Size_Vector">1M</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR2_Size_Vector">1M</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR3_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR4_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR_Index_Value5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BAR5_Size_Vector">1M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RBAR_Initial_Value5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECRC_Check">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECRC_Check_Trim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Rx_Poisoned_Resp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_gt_common">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.shared_logic_in_core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pl_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_mgmt_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ctl_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_status_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rcv_msg_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_fc_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.err_reporting_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_pipe_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_startup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_mode_sim">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">PCIeGen2x8If128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dev_port_type">0000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.max_lnk_spd">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gen1">true</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_pcie_fast_config">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_0">FFFFFC00</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.bar_5">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.xrom_bar">00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ven_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dev_id">7018</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.subsys_ven_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.subsys_id">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.class_code">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.cardbus_cis_ptr">00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ext_tag_fld_sup">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_dev_control_ext_tag_default">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_cpl_timeout_disable_sup">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_cpl_timeout_ranges_sup">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_buf_opt_bma">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_perf_level_high">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_tx_last_tlp">28</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rx_ram_limit">3FF</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_dll_lnk_actv_cap">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_hw_auton_spd_disable">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_de_emph">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.slot_clk">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_root_cap_crs">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_slot_cap_attn_butn">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_slot_cap_attn_ind">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_slot_cap_pwr_ind">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_slot_cap_hotplug_surprise">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_slot_cap_hotplug_cap">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_slot_cap_elec_interlock">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_slot_cap_no_cmd_comp_sup">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.intx">FALSE</spirit:configurableElementValue>
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fpga/xilinx/kc705/KC705_Gen2x8If128/prj/KC705_Gen2x8If128.xpr

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+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2014.4 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.   -->
+
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+    </Run>
+    <Run Id="PCIeGen2x8If128_synth_1" Type="Ft3:Synth" SrcSet="PCIeGen2x8If128" Part="xc7k325tffg900-2" ConstrsSet="PCIeGen2x8If128" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/PCIeGen2x8If128_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="PCIeGen2x8If128_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="PCIeGen2x8If128" Description="Vivado Implementation Defaults" SynthRun="PCIeGen2x8If128_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
+          <Desc>Vivado Implementation Defaults</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+  </Runs>
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</Project>

fpga/xilinx/kc705/riffa_wrapper_kc705.v

@@ -0,0 +1,649 @@
+// ----------------------------------------------------------------------
+// Copyright (c) 2015, The Regents of the University of California All
+// rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// 
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+// 
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+// 
+//     * Neither the name of The Regents of the University of California
+//       nor the names of its contributors may be used to endorse or
+//       promote products derived from this software without specific
+//       prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+// DAMAGE.
+// ----------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Filename:            riffa_wrapper_kc705.v
+// Version:             1.00.a
+// Verilog Standard:    Verilog-2001
+// Description:         RIFFA wrapper for the KC705 (REV C) Development board.
+// Author:              Dustin Richmond (@darichmond)
+//-----------------------------------------------------------------------------
+`include "trellis.vh"
+`include "riffa.vh"
+`include "xilinx.vh"
+`include "ultrascale.vh"
+`include "functions.vh"
+`timescale 1ps / 1ps
+module riffa_wrapper_kc705
+    #(// Number of RIFFA Channels
+      parameter C_NUM_CHNL = 1,
+      // Bit-Width from Vivado IP Generator
+      parameter C_PCI_DATA_WIDTH = 128,
+      // 4-Byte Name for this FPGA
+      parameter C_MAX_PAYLOAD_BYTES = 256,
+      parameter C_LOG_NUM_TAGS = 5,
+      parameter C_FPGA_ID = "KC105") 
+    (// Interface: Xilinx RX 
+     input [C_PCI_DATA_WIDTH-1:0]                 M_AXIS_RX_TDATA,
+     input [(C_PCI_DATA_WIDTH/8)-1:0]             M_AXIS_RX_TKEEP,
+     input                                        M_AXIS_RX_TLAST,
+     input                                        M_AXIS_RX_TVALID,
+     output                                       M_AXIS_RX_TREADY,
+     input [`SIG_XIL_RX_TUSER_W-1:0]              M_AXIS_RX_TUSER,
+     output                                       RX_NP_OK,
+     output                                       RX_NP_REQ,
+
+     // Interface: Xilinx TX
+     output [C_PCI_DATA_WIDTH-1:0]                S_AXIS_TX_TDATA,
+     output [(C_PCI_DATA_WIDTH/8)-1:0]            S_AXIS_TX_TKEEP,
+     output                                       S_AXIS_TX_TLAST,
+     output                                       S_AXIS_TX_TVALID,
+     input                                        S_AXIS_TX_TREADY,
+     output [`SIG_XIL_TX_TUSER_W-1:0]             S_AXIS_TX_TUSER,
+     output                                       TX_CFG_GNT,
+
+     // Interface: Xilinx Configuration 
+     input [`SIG_BUSID_W-1:0]                     CFG_BUS_NUMBER,
+     input [`SIG_DEVID_W-1:0]                     CFG_DEVICE_NUMBER,
+     input [`SIG_FNID_W-1:0]                      CFG_FUNCTION_NUMBER,
+     input [`SIG_CFGREG_W-1:0]                    CFG_COMMAND,
+     input [`SIG_CFGREG_W-1:0]                    CFG_DCOMMAND,
+     input [`SIG_CFGREG_W-1:0]                    CFG_LSTATUS,
+     input [`SIG_CFGREG_W-1:0]                    CFG_LCOMMAND,
+
+     // Interface: Xilinx Flow Control
+     input [`SIG_FC_CPLD_W-1:0]                   FC_CPLD,
+     input [`SIG_FC_CPLH_W-1:0]                   FC_CPLH,
+     output [`SIG_FC_SEL_W-1:0]                   FC_SEL,
+    
+     // Interface: Xilinx Interrupt
+     input                                        CFG_INTERRUPT_MSIEN,
+     input                                        CFG_INTERRUPT_RDY,
+     output                                       CFG_INTERRUPT,
+
+     input                                        USER_CLK,
+     input                                        USER_RESET,
+    
+     // RIFFA Interface Signals
+     output                                       RST_OUT,
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_CLK, // Channel read clock
+     output [C_NUM_CHNL-1:0]                      CHNL_RX, // Channel read receive signal
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_ACK, // Channel read received signal
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_LAST, // Channel last read
+     output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
+     output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
+     output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   CHNL_RX_DATA, // Channel read data
+     output [C_NUM_CHNL-1:0]                      CHNL_RX_DATA_VALID, // Channel read data valid
+     input [C_NUM_CHNL-1:0]                       CHNL_RX_DATA_REN, // Channel read data has been recieved
+
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_CLK, // Channel write clock
+     input [C_NUM_CHNL-1:0]                       CHNL_TX, // Channel write receive signal
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_ACK, // Channel write acknowledgement signal
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_LAST, // Channel last write
+     input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]  CHNL_TX_LEN, // Channel write length (in 32 bit words)
+     input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]  CHNL_TX_OFF, // Channel write offset
+     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]    CHNL_TX_DATA, // Channel write data
+     input [C_NUM_CHNL-1:0]                       CHNL_TX_DATA_VALID, // Channel write data valid
+     output [C_NUM_CHNL-1:0]                      CHNL_TX_DATA_REN); // Channel write data has been recieved
+     
+    localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
+    localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
+    // ALTERA, XILINX or ULTRASCALE
+    localparam C_VENDOR = "XILINX";
+
+    localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
+    localparam C_PIPELINE_OUTPUT = 1;
+    localparam C_PIPELINE_INPUT = 1;
+    localparam C_DEPTH_PACKETS = 4;
+    
+    wire                                          clk;
+    wire                                          rst_in;
+    wire                                          done_txc_rst;
+    wire                                          done_txr_rst;
+    wire                                          done_rxr_rst;
+    wire                                          done_rxc_rst;
+    // Interface: RXC Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxc_data;
+    wire                                          rxc_data_valid;
+    wire                                          rxc_data_start_flag;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxc_data_word_enable;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxc_meta_fdwbe;
+    wire                                          rxc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxc_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxc_meta_ldwbe;
+    wire [`SIG_TAG_W-1:0]                         rxc_meta_tag;
+    wire [`SIG_LOWADDR_W-1:0]                     rxc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        rxc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         rxc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     rxc_meta_bytes_remaining;
+    wire [`SIG_CPLID_W-1:0]                       rxc_meta_completer_id;
+    wire                                          rxc_meta_ep;
+
+    // Interface: RXR Engine
+    wire [C_PCI_DATA_WIDTH-1:0]                   rxr_data;
+    wire                                          rxr_data_valid;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              rxr_data_word_enable;
+    wire                                          rxr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_start_offset;
+    wire [`SIG_FBE_W-1:0]                         rxr_meta_fdwbe;
+    wire                                          rxr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        rxr_data_end_offset;
+    wire [`SIG_LBE_W-1:0]                         rxr_meta_ldwbe;
+    wire [`SIG_TC_W-1:0]                          rxr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        rxr_meta_attr;
+    wire [`SIG_TAG_W-1:0]                         rxr_meta_tag;
+    wire [`SIG_TYPE_W-1:0]                        rxr_meta_type;
+    wire [`SIG_ADDR_W-1:0]                        rxr_meta_addr;
+    wire [`SIG_BARDECODE_W-1:0]                   rxr_meta_bar_decoded;
+    wire [`SIG_REQID_W-1:0]                       rxr_meta_requester_id;
+    wire [`SIG_LEN_W-1:0]                         rxr_meta_length;
+    wire                                          rxr_meta_ep;
+    
+    // interface: TXC Engine
+    wire                                          txc_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txc_data;
+    wire                                          txc_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_start_offset;
+    wire                                          txc_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txc_data_end_offset;
+    wire                                          txc_data_ready;
+
+    wire                                          txc_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txc_meta_fdwbe;
+    wire [`SIG_LBE_W-1:0]                         txc_meta_ldwbe;
+    wire [`SIG_LOWADDR_W-1:0]                     txc_meta_addr;
+    wire [`SIG_TYPE_W-1:0]                        txc_meta_type;
+    wire [`SIG_LEN_W-1:0]                         txc_meta_length;
+    wire [`SIG_BYTECNT_W-1:0]                     txc_meta_byte_count;
+    wire [`SIG_TAG_W-1:0]                         txc_meta_tag;
+    wire [`SIG_REQID_W-1:0]                       txc_meta_requester_id;
+    wire [`SIG_TC_W-1:0]                          txc_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txc_meta_attr;
+    wire                                          txc_meta_ep;
+    wire                                          txc_meta_ready;
+    wire                                          txc_sent;
+
+    // Interface: TXR Engine
+    wire                                          txr_data_valid;
+    wire [C_PCI_DATA_WIDTH-1:0]                   txr_data;
+    wire                                          txr_data_start_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_start_offset;
+    wire                                          txr_data_end_flag;
+    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]        txr_data_end_offset;
+    wire                                          txr_data_ready;
+
+    wire                                          txr_meta_valid;
+    wire [`SIG_FBE_W-1:0]                         txr_meta_fdwbe; 
+    wire [`SIG_LBE_W-1:0]                         txr_meta_ldwbe;
+    wire [`SIG_ADDR_W-1:0]                        txr_meta_addr;
+    wire [`SIG_LEN_W-1:0]                         txr_meta_length;
+    wire [`SIG_TAG_W-1:0]                         txr_meta_tag;
+    wire [`SIG_TC_W-1:0]                          txr_meta_tc;
+    wire [`SIG_ATTR_W-1:0]                        txr_meta_attr;
+    wire [`SIG_TYPE_W-1:0]                        txr_meta_type;
+    wire                                          txr_meta_ep;
+    wire                                          txr_meta_ready;
+    wire                                          txr_sent;
+
+    // Classic Interface Wires
+    wire                                          rx_tlp_ready;
+    wire [C_PCI_DATA_WIDTH-1:0]                   rx_tlp;
+    wire                                          rx_tlp_end_flag;
+    wire [`SIG_OFFSET_W-1:0]                      rx_tlp_end_offset;
+    wire                                          rx_tlp_start_flag;
+    wire [`SIG_OFFSET_W-1:0]                      rx_tlp_start_offset;
+    wire                                          rx_tlp_valid;
+    wire [`SIG_BARDECODE_W-1:0]                   rx_tlp_bar_decode;
+    
+    wire                                          tx_tlp_ready;
+    wire [C_PCI_DATA_WIDTH-1:0]                   tx_tlp;
+    wire                                          tx_tlp_end_flag;
+    wire [`SIG_OFFSET_W-1:0]                      tx_tlp_end_offset;
+    wire                                          tx_tlp_start_flag;
+    wire [`SIG_OFFSET_W-1:0]                      tx_tlp_start_offset;
+    wire                                          tx_tlp_valid;
+    
+    // Unconnected Wires (Used in ultrascale interface)
+    // Interface: RQ (TXC)
+    wire                                          s_axis_rq_tlast_nc;
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_rq_tdata_nc;
+    wire [`SIG_RQ_TUSER_W-1:0]                    s_axis_rq_tuser_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_rq_tkeep_nc;
+    wire                                          s_axis_rq_tready_nc = 0;
+    wire                                          s_axis_rq_tvalid_nc;
+    // Interface: RC (RXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_rc_tdata_nc = 0;
+    wire [`SIG_RC_TUSER_W-1:0]                    m_axis_rc_tuser_nc = 0;
+    wire                                          m_axis_rc_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_rc_tkeep_nc = 0;
+    wire                                          m_axis_rc_tvalid_nc = 0;
+    wire                                          m_axis_rc_tready_nc;
+    // Interface: CQ (RXR)
+    wire [C_PCI_DATA_WIDTH-1:0]                   m_axis_cq_tdata_nc = 0;
+    wire [`SIG_CQ_TUSER_W-1:0]                    m_axis_cq_tuser_nc = 0;
+    wire                                          m_axis_cq_tlast_nc = 0;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              m_axis_cq_tkeep_nc = 0;
+    wire                                          m_axis_cq_tvalid_nc = 0;
+    wire                                          m_axis_cq_tready_nc = 0;
+    // Interface: CC (TXC)
+    wire [C_PCI_DATA_WIDTH-1:0]                   s_axis_cc_tdata_nc;
+    wire [`SIG_CC_TUSER_W-1:0]                    s_axis_cc_tuser_nc;
+    wire                                          s_axis_cc_tlast_nc;
+    wire [(C_PCI_DATA_WIDTH/32)-1:0]              s_axis_cc_tkeep_nc;
+    wire                                          s_axis_cc_tvalid_nc;
+    wire                                          s_axis_cc_tready_nc = 0;
+
+    // Interface: Configuration
+    wire                                          config_bus_master_enable;
+    wire [`SIG_CPLID_W-1:0]                       config_completer_id;
+    wire                                          config_cpl_boundary_sel;
+    wire                                          config_interrupt_msienable;
+    wire [`SIG_LINKRATE_W-1:0]                    config_link_rate;
+    wire [`SIG_LINKWIDTH_W-1:0]                   config_link_width;
+    wire [`SIG_MAXPAYLOAD_W-1:0]                  config_max_payload_size;
+    wire [`SIG_MAXREAD_W-1:0]                     config_max_read_request_size;
+    wire [`SIG_FC_CPLD_W-1:0]                     config_max_cpl_data;
+    wire [`SIG_FC_CPLH_W-1:0]                     config_max_cpl_hdr;
+
+    wire                                          intr_msi_request;
+    wire                                          intr_msi_rdy;
+
+    genvar                                        chnl;
+
+    reg                                           rRxTlpValid;
+    reg                                           rRxTlpEndFlag;
+
+    assign clk = USER_CLK;
+    assign rst_in = USER_RESET;
+
+    translation_xilinx
+        #(/*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH))
+    trans
+        (
+         // Outputs
+         .RX_TLP                        (rx_tlp[C_PCI_DATA_WIDTH-1:0]),
+         .RX_TLP_VALID                  (rx_tlp_valid),
+         .RX_TLP_START_FLAG             (rx_tlp_start_flag),
+         .RX_TLP_START_OFFSET           (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RX_TLP_END_FLAG               (rx_tlp_end_flag),
+         .RX_TLP_END_OFFSET             (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RX_TLP_BAR_DECODE             (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]),
+         .TX_TLP_READY                  (tx_tlp_ready),
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE      (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH             (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE              (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE  (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE       (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE    (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL       (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA           (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR            (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+         .INTR_MSI_RDY                  (intr_msi_rdy),
+         // Inputs
+         .CLK                           (clk),
+         .RST_IN                        (rst_in),
+         .RX_TLP_READY                  (rx_tlp_ready),
+         .TX_TLP                        (tx_tlp[C_PCI_DATA_WIDTH-1:0]),
+         .TX_TLP_VALID                  (tx_tlp_valid),
+         .TX_TLP_START_FLAG             (tx_tlp_start_flag),
+         .TX_TLP_START_OFFSET           (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TX_TLP_END_FLAG               (tx_tlp_end_flag),
+         .TX_TLP_END_OFFSET             (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .INTR_MSI_REQUEST              (intr_msi_request),
+         /*AUTOINST*/
+         // Outputs
+         .M_AXIS_RX_TREADY              (M_AXIS_RX_TREADY),
+         .RX_NP_OK                      (RX_NP_OK),
+         .RX_NP_REQ                     (RX_NP_REQ),
+         .S_AXIS_TX_TDATA               (S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_TX_TKEEP               (S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .S_AXIS_TX_TLAST               (S_AXIS_TX_TLAST),
+         .S_AXIS_TX_TVALID              (S_AXIS_TX_TVALID),
+         .S_AXIS_TX_TUSER               (S_AXIS_TX_TUSER[`SIG_XIL_TX_TUSER_W-1:0]),
+         .TX_CFG_GNT                    (TX_CFG_GNT),
+         .FC_SEL                        (FC_SEL[`SIG_FC_SEL_W-1:0]),
+         .CFG_INTERRUPT                 (CFG_INTERRUPT),
+         // Inputs
+         .M_AXIS_RX_TDATA               (M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RX_TKEEP               (M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
+         .M_AXIS_RX_TLAST               (M_AXIS_RX_TLAST),
+         .M_AXIS_RX_TVALID              (M_AXIS_RX_TVALID),
+         .M_AXIS_RX_TUSER               (M_AXIS_RX_TUSER[`SIG_XIL_RX_TUSER_W-1:0]),
+         .S_AXIS_TX_TREADY              (S_AXIS_TX_TREADY),
+         .CFG_BUS_NUMBER                (CFG_BUS_NUMBER[`SIG_BUSID_W-1:0]),
+         .CFG_DEVICE_NUMBER             (CFG_DEVICE_NUMBER[`SIG_DEVID_W-1:0]),
+         .CFG_FUNCTION_NUMBER           (CFG_FUNCTION_NUMBER[`SIG_FNID_W-1:0]),
+         .CFG_COMMAND                   (CFG_COMMAND[`SIG_CFGREG_W-1:0]),
+         .CFG_DCOMMAND                  (CFG_DCOMMAND[`SIG_CFGREG_W-1:0]),
+         .CFG_LSTATUS                   (CFG_LSTATUS[`SIG_CFGREG_W-1:0]),
+         .CFG_LCOMMAND                  (CFG_LCOMMAND[`SIG_CFGREG_W-1:0]),
+         .FC_CPLD                       (FC_CPLD[`SIG_FC_CPLD_W-1:0]),
+         .FC_CPLH                       (FC_CPLH[`SIG_FC_CPLH_W-1:0]),
+         .CFG_INTERRUPT_MSIEN           (CFG_INTERRUPT_MSIEN),
+         .CFG_INTERRUPT_RDY             (CFG_INTERRUPT_RDY));
+
+    engine_layer
+        #(// Parameters
+          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_BYTES/4),
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
+          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
+          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
+          .C_VENDOR                     (C_VENDOR))
+    engine_layer_inst
+        (// Outputs
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+
+         .RST_LOGIC                     (RST_OUT),
+         // Unconnected Outputs
+         .TX_TLP                        (tx_tlp),
+         .TX_TLP_VALID                  (tx_tlp_valid),
+         .TX_TLP_START_FLAG             (tx_tlp_start_flag),
+         .TX_TLP_START_OFFSET           (tx_tlp_start_offset),
+         .TX_TLP_END_FLAG               (tx_tlp_end_flag),
+         .TX_TLP_END_OFFSET             (tx_tlp_end_offset),
+
+         .RX_TLP_READY                  (rx_tlp_ready),
+         // Inputs
+         .CLK_BUS                       (clk),
+         .RST_BUS                       (rst_in),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+         // Unconnected Inputs
+         .RX_TLP                        (rx_tlp),
+         .RX_TLP_VALID                  (rx_tlp_valid),
+         .RX_TLP_START_FLAG             (rx_tlp_start_flag),
+         .RX_TLP_START_OFFSET           (rx_tlp_start_offset),
+         .RX_TLP_END_FLAG               (rx_tlp_end_flag),
+         .RX_TLP_END_OFFSET             (rx_tlp_end_offset),
+         .RX_TLP_BAR_DECODE             (rx_tlp_bar_decode),
+
+         .TX_TLP_READY                  (wTxTlpReady),
+         .DONE_TXC_RST                  (done_txc_rst),
+         .DONE_TXR_RST                  (done_txr_rst),
+         .DONE_RXR_RST                  (done_rxc_rst),
+         .DONE_RXC_RST                  (done_rxr_rstsudo),
+         /*AUTOINST*/
+         // Outputs
+         .M_AXIS_CQ_TREADY              (m_axis_cq_tready_nc),
+         .M_AXIS_RC_TREADY              (m_axis_rc_tready_nc),
+         .S_AXIS_CC_TVALID              (s_axis_cc_tvalid_nc),
+         .S_AXIS_CC_TLAST               (s_axis_cc_tlast_nc),
+         .S_AXIS_CC_TDATA               (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_CC_TKEEP               (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_CC_TUSER               (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
+         .S_AXIS_RQ_TVALID              (s_axis_rq_tvalid_nc),
+         .S_AXIS_RQ_TLAST               (s_axis_rq_tlast_nc),
+         .S_AXIS_RQ_TDATA               (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .S_AXIS_RQ_TKEEP               (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .S_AXIS_RQ_TUSER               (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
+         // Inputs
+         .M_AXIS_CQ_TVALID              (m_axis_cq_tvalid_nc),
+         .M_AXIS_CQ_TLAST               (m_axis_cq_tlast_nc),
+         .M_AXIS_CQ_TDATA               (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_CQ_TKEEP               (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_CQ_TUSER               (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
+         .M_AXIS_RC_TVALID              (m_axis_rc_tvalid_nc),
+         .M_AXIS_RC_TLAST               (m_axis_rc_tlast_nc),
+         .M_AXIS_RC_TDATA               (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
+         .M_AXIS_RC_TKEEP               (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .M_AXIS_RC_TUSER               (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
+         .S_AXIS_CC_TREADY              (s_axis_cc_tready_nc),
+         .S_AXIS_RQ_TREADY              (s_axis_rq_tready_nc)
+         /*AUTOINST*/);
+
+    riffa
+        #(.C_TAG_WIDTH                  (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
+          /*AUTOINSTPARAM*/
+          // Parameters
+          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
+          .C_NUM_CHNL                   (C_NUM_CHNL),
+          .C_MAX_READ_REQ_BYTES         (C_MAX_READ_REQ_BYTES),
+          .C_VENDOR                     (C_VENDOR),
+          .C_FPGA_NAME                  (C_FPGA_NAME),
+          .C_FPGA_ID                    (C_FPGA_ID),
+          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS))
+    riffa_inst
+        (// Outputs
+         .TXC_DATA                      (txc_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXC_DATA_VALID                (txc_data_valid),
+         .TXC_DATA_START_FLAG           (txc_data_start_flag),
+         .TXC_DATA_START_OFFSET         (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_DATA_END_FLAG             (txc_data_end_flag),
+         .TXC_DATA_END_OFFSET           (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXC_META_VALID                (txc_meta_valid),
+         .TXC_META_FDWBE                (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXC_META_LDWBE                (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXC_META_ADDR                 (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .TXC_META_TYPE                 (txc_meta_type[`SIG_TYPE_W-1:0]),
+         .TXC_META_LENGTH               (txc_meta_length[`SIG_LEN_W-1:0]),
+         .TXC_META_BYTE_COUNT           (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
+         .TXC_META_TAG                  (txc_meta_tag[`SIG_TAG_W-1:0]),
+         .TXC_META_REQUESTER_ID         (txc_meta_requester_id[`SIG_REQID_W-1:0]),
+         .TXC_META_TC                   (txc_meta_tc[`SIG_TC_W-1:0]),
+         .TXC_META_ATTR                 (txc_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXC_META_EP                   (txc_meta_ep),
+
+         .TXR_DATA_VALID                (txr_data_valid),
+         .TXR_DATA                      (txr_data[C_PCI_DATA_WIDTH-1:0]),
+         .TXR_DATA_START_FLAG           (txr_data_start_flag),
+         .TXR_DATA_START_OFFSET         (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_DATA_END_FLAG             (txr_data_end_flag),
+         .TXR_DATA_END_OFFSET           (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .TXR_META_VALID                (txr_meta_valid),
+         .TXR_META_FDWBE                (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .TXR_META_LDWBE                (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .TXR_META_ADDR                 (txr_meta_addr[`SIG_ADDR_W-1:0]),
+         .TXR_META_LENGTH               (txr_meta_length[`SIG_LEN_W-1:0]),
+         .TXR_META_TAG                  (txr_meta_tag[`SIG_TAG_W-1:0]),
+         .TXR_META_TC                   (txr_meta_tc[`SIG_TC_W-1:0]),
+         .TXR_META_ATTR                 (txr_meta_attr[`SIG_ATTR_W-1:0]),
+         .TXR_META_TYPE                 (txr_meta_type[`SIG_TYPE_W-1:0]),
+         .TXR_META_EP                   (txr_meta_ep),
+
+         .INTR_MSI_REQUEST              (intr_msi_request),
+         // Inputs
+         .CLK                           (clk),
+         .RXR_DATA                      (rxr_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXR_DATA_VALID                (rxr_data_valid),
+         .RXR_DATA_START_FLAG           (rxr_data_start_flag),
+         .RXR_DATA_START_OFFSET         (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_WORD_ENABLE          (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_DATA_END_FLAG             (rxr_data_end_flag),
+         .RXR_DATA_END_OFFSET           (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXR_META_FDWBE                (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXR_META_LDWBE                (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXR_META_TC                   (rxr_meta_tc[`SIG_TC_W-1:0]),
+         .RXR_META_ATTR                 (rxr_meta_attr[`SIG_ATTR_W-1:0]),
+         .RXR_META_TAG                  (rxr_meta_tag[`SIG_TAG_W-1:0]),
+         .RXR_META_TYPE                 (rxr_meta_type[`SIG_TYPE_W-1:0]),
+         .RXR_META_ADDR                 (rxr_meta_addr[`SIG_ADDR_W-1:0]),
+         .RXR_META_BAR_DECODED          (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
+         .RXR_META_REQUESTER_ID         (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
+         .RXR_META_LENGTH               (rxr_meta_length[`SIG_LEN_W-1:0]),
+         .RXR_META_EP                   (rxr_meta_ep),
+
+         .RXC_DATA_VALID                (rxc_data_valid),
+         .RXC_DATA                      (rxc_data[C_PCI_DATA_WIDTH-1:0]),
+         .RXC_DATA_START_FLAG           (rxc_data_start_flag),
+         .RXC_DATA_START_OFFSET         (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_WORD_ENABLE          (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_DATA_END_FLAG             (rxc_data_end_flag),
+         .RXC_DATA_END_OFFSET           (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
+         .RXC_META_FDWBE                (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
+         .RXC_META_LDWBE                (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
+         .RXC_META_TAG                  (rxc_meta_tag[`SIG_TAG_W-1:0]),
+         .RXC_META_ADDR                 (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
+         .RXC_META_TYPE                 (rxc_meta_type[`SIG_TYPE_W-1:0]),
+         .RXC_META_LENGTH               (rxc_meta_length[`SIG_LEN_W-1:0]),
+         .RXC_META_BYTES_REMAINING      (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
+         .RXC_META_COMPLETER_ID         (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
+         .RXC_META_EP                   (rxc_meta_ep),
+
+         .TXC_DATA_READY                (txc_data_ready),
+         .TXC_META_READY                (txc_meta_ready),
+         .TXC_SENT                      (txc_sent),         
+
+         .TXR_DATA_READY                (txr_data_ready),
+         .TXR_META_READY                (txr_meta_ready),
+         .TXR_SENT                      (txr_sent),
+
+         .CONFIG_COMPLETER_ID           (config_completer_id[`SIG_CPLID_W-1:0]),
+         .CONFIG_BUS_MASTER_ENABLE      (config_bus_master_enable),
+         .CONFIG_LINK_WIDTH             (config_link_width[`SIG_LINKWIDTH_W-1:0]),
+         .CONFIG_LINK_RATE              (config_link_rate[`SIG_LINKRATE_W-1:0]),
+         .CONFIG_MAX_READ_REQUEST_SIZE  (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
+         .CONFIG_MAX_PAYLOAD_SIZE       (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
+         .CONFIG_INTERRUPT_MSIENABLE    (config_interrupt_msienable),
+         .CONFIG_CPL_BOUNDARY_SEL       (config_cpl_boundary_sel),
+         .CONFIG_MAX_CPL_DATA           (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
+         .CONFIG_MAX_CPL_HDR            (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
+        
+         .INTR_MSI_RDY                  (intr_msi_rdy),
+
+         .DONE_TXC_RST                  (done_txc_rst),
+         .DONE_TXR_RST                  (done_txr_rst),
+         .RST_BUS                       (rst_in),
+         /*AUTOINST*/
+         // Outputs
+         .RST_OUT                       (RST_OUT),
+         .CHNL_RX                       (CHNL_RX[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LAST                  (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_RX_LEN                   (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_RX_OFF                   (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_RX_DATA                  (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_RX_DATA_VALID            (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
+         .CHNL_TX_ACK                   (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_TX_DATA_REN              (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
+         // Inputs
+         .CHNL_RX_CLK                   (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_ACK                   (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
+         .CHNL_RX_DATA_REN              (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
+         .CHNL_TX_CLK                   (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
+         .CHNL_TX                       (CHNL_TX[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LAST                  (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
+         .CHNL_TX_LEN                   (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
+         .CHNL_TX_OFF                   (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
+         .CHNL_TX_DATA                  (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
+         .CHNL_TX_DATA_VALID            (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
+
+endmodule
+// Local Variables:
+// verilog-library-directories:("../../riffa_hdl/")
+// End:
+