Dustin Richmond
4e9d3c8d81
Final RIFFA 2.2.2 commit
2016-09-07 15:06:54 -07:00
Dustin Richmond
f7b5c8b153
Changing PLL parameters for two of the clock test projects
2016-08-11 16:28:43 -07:00
Dustin Richmond
0c2c734256
Removing non-qsys DE5 bit files to reduce confusion. Adding a README in each directory to alleviate confusion.
2016-08-11 16:09:17 -07:00
Dustin Richmond
0805b4c864
Adding back altera boards, removing make file for a release/merge
2016-08-11 16:04:51 -07:00
Dustin Richmond
8384618b36
Removing signal tap declaration from DE4 project
2016-08-11 14:18:13 -07:00
Dustin Richmond
b8398e09cf
Fixing a bug in the VC709 board specific make file
2016-08-11 14:08:24 -07:00
Dustin Richmond
e9c1b329b8
Adding an additional file to remove in board-specific make file
2016-08-11 13:55:40 -07:00
Dustin Richmond
eb1a3934c4
Fixing/updating makefiles for new xilinx clock test projects
2016-08-11 13:54:54 -07:00
Dustin Richmond
e97054d191
Renaming altera clock test projects
2016-08-11 13:53:38 -07:00
Dustin Richmond
22d6da6537
Renaming Xilinx projects
2016-08-11 13:28:37 -07:00
Dustin Richmond
2499f4ff10
Commiting fix for 40-mhz missing-dword bug.
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In rare cases, when using a slow clock frequency the first C_PCI_DATA_WIDTH/32 dwords would be dropped during a TX transaction (FPGA to host). This was caused by an earlier bug fix, also addressing slow clock frequencies.
In this case, the fix caused RD_EN to stay high for too long, which subsequently caused the first dwords to be dropped.
Also adding: New testing projects which instantiate 12 channels, each with a different clock frequency, and a test script (asyncutil.sh) to test these projects.
2016-08-11 13:07:00 -07:00
Dustin Richmond
778c42e74b
First attempt (and maybe only) at fixing a bug in the CHNL_TX interface.
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In the interface, CHNL_TX_DATA_REN was remaining asserted for two cycles after CHNL_TX was deasserted. This has been fixed, and CHNL_TX_DATA_REN now deasserts one cycle after CHNL_TX is deasserted.
2016-07-18 16:28:11 -07:00
Dustin Richmond
2849235361
Committing RIFFA 2.2.1 into master
2016-03-14 08:20:08 -07:00
Dustin Richmond
17bdf731e6
Updating bitfiles for latest bug fix
2016-02-22 14:26:35 -08:00
Dustin Richmond
62137cabad
Fixed a bug in the TX Multiplexer, write notification logic. The write
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notification buffer was too small.
2016-02-22 13:32:59 -08:00
Dustin Richmond
255fb848cb
Another bit file update
2016-02-18 12:35:46 -08:00
Dustin Richmond
4f78805fd5
Adding a new feature to the makefiles, where typing make release in the top
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directory will package (most of) a new release
2016-02-18 11:14:09 -08:00
Dustin Richmond
4d0bc24319
Fixed a bug (uncovered by the clock ratio issue) where the tx_multiplexer would
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confuse the tx_port_monitor by returning too few or too many write-packet
acknowledgements, resulting in a hang (but correct data!).
2016-02-16 16:04:10 -08:00
Dustin Richmond
753ffffd93
Fixed a bug where a clock ratio of less than 1:2 between the user-provided clock
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and the PCIe core clock would cause some transfers to return 0 words (but not
hang).
2016-02-16 16:02:42 -08:00
Dustin Richmond
6ff69de5c6
Updating copyright statements for 2016
2016-02-09 15:23:37 -08:00
Dustin Richmond
02c144fbfb
Adding corrected bit-file for DE4 Gen1 64-bit interface
2016-02-09 13:03:01 -08:00
Dustin Richmond
d27b265b90
Updating bitfiles with bugfixes from past commits
2016-02-04 14:58:36 -08:00
Dustin Richmond
bc8999eba4
Fixed a bug where the tx_multiplexer kept LBE field high on packets of 1 DW in length.
2016-02-04 11:03:06 -08:00
Dustin Richmond
2a832ffe4e
Fixed a bug in the TX Alignment Pipeline where two EOFs in a cycle from the Data
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Fifo would cause corruption in subsequent transfers.
2016-02-02 17:14:29 -08:00
Dustin Richmond
ce83bdefe1
Adding updated bit files and project files
2016-01-27 10:39:17 -08:00
Dustin Richmond
ceb60c92f9
Adding source search path in C4 Development board example design
2016-01-27 10:16:50 -08:00
Dustin Richmond
0fb6908dd3
Updating copyright statements with correct file names
2016-01-27 10:12:17 -08:00
Dustin Richmond
e60f64efe2
Adding additional commands to base Makefile
2016-01-26 11:31:06 -08:00
Dustin Richmond
fee2c60a6b
updating project files, upgrading IP, and removing project errors
2016-01-26 11:30:02 -08:00
Dustin Richmond
ad101929f2
Updating board.mk makefiles to clean and reset xilinx projects
2016-01-26 11:15:21 -08:00
Dustin Richmond
83ebefe37e
Removing unnecessary file from riffa.mk
2016-01-26 11:14:34 -08:00
Dustin Richmond
025d2a424c
Correcting all C_NUM_CHNL parameters to 1 (for testing)
2016-01-25 16:51:19 -08:00
Dustin Richmond
cd204136c6
Further updates to hierarchical makefiles.
2016-01-25 16:37:33 -08:00
Dustin Richmond
680260b3f7
Adding copyright statments
2016-01-20 18:13:06 -08:00
Dustin Richmond
ad496b4c94
Mega-commit (which I usually like to avoid, but this one didn't really come cleanly)
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The majority of this work can be summarized as: Makefiles have been added to
generate all of the boards, boards for each vendor, board, and projects for each
board.
To make things cleaner I renamed a few of the Xilinx projects, and may rename
the latera projects for consistency.
I removed the de5_qsys directory, and moved all projects into the de5 directory,
but those projects have a Q between DE5 and the PCIe specifications, ie
DE5QGen... (haven't updated the documentation)
Added c4dev board (untested)
Apologies to those of you who recently switched onto the DEVEL branch.
2016-01-20 17:46:39 -08:00
Dustin Richmond
c209dac5d3
Fixing a small bug in the tx_port_buffer related to xilinx synthesis in Xilinx
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2015 versions.
2016-01-15 15:34:33 -08:00
Dustin Richmond
7b1d9b2dfd
Merge branch 'master' into devel/RIFFA/2.2.1
2015-09-14 09:53:57 -07:00
Dustin Richmond
9e4c9241a1
Updating ultrascale projects, and riffa documentation
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The riffa documentation said that the 7-series core lacked Gen2x8 support. This
is incorrect.
2015-09-01 08:55:00 -07:00
Dustin Richmond
c9a68ddd7a
Updating ML605 files
2015-09-01 08:48:41 -07:00
Dustin Richmond
3d3f866649
Fixing a bug in the RXR engines/RXC Engines that seems to only affect DE4 Gen2
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devices.
On IP Compiler devices, it is apparently possible to have valid drop
mid-packet. This condition is now checked, and has been tested (though new bit
files have not be uploaded)
2015-08-26 16:14:40 -07:00
Dustin Richmond
d6c5115c10
Cleaning up more reset logic (no real changes)
2015-08-26 16:11:33 -07:00
Dustin Richmond
918665aff2
Adding BSD 3-Clause licenses to files that were missing it.
2015-08-26 07:33:40 -07:00
Dustin Richmond
d2cb526218
Adding updated AC701 bit files
2015-08-13 08:37:35 -07:00
Dustin Richmond
bfa63eb3ad
Fixed a naming issue in the AC701 wrapper file.
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tx_tlp_ready was named wTxTlpReady
2015-08-13 08:03:27 -07:00
Dustin Richmond
2f13ce9adc
Adding missing ac701 riffa wrapper file.
2015-08-13 08:01:01 -07:00
Dustin Richmond
c420b76c16
Finishing reset logic and testing/implementing across a wide swath of boards.
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Changes are mostly in the RX logic, where RST_IN was still used, though some new
logic (reset_extender) was added to riffa.v. Updated projects for: VC709, VC707,
ZC706 (partial), NetFPGA, ADM-7V3, ML605 (Still not working), AC701 (Untested)
and KC705 (Untested)
2015-08-12 16:16:27 -07:00
Dustin Richmond
9d7543a5ff
Adding DE2 project files (only slightly tested)
2015-08-11 16:47:13 -07:00
Dustin Richmond
f836029e8d
Adding a few changes the the ML605 project.
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Forgot to specify development board in the ip block, also commented out a ucf
file line.
2015-08-11 15:34:35 -07:00
Dustin Richmond
47530ee0cf
Adding AC701 projects for RIFFA 2.2.1.
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Also fixed a small bug in the KC705 riffa wrapper, and KC705 boards
2015-08-11 15:33:49 -07:00
Dustin Richmond
e13b825fa1
Adding VERY PRELIMINARY ML605 development board files.
2015-07-31 15:29:00 -07:00
