Dustin Richmond
744953c2ad
Adding resetter.v, a new module that controls the reset logic in riffa.v.
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This logic will allow us to reset the TX pipeline safely, and still transmit the
status completion. This is a feature requested by the NetFPGA team.
2015-07-15 17:27:17 -07:00
Dustin Richmond
d5f3ba7309
Added a parameter C_VALUE to shiftreg.v and changed all declarations.
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The C_VALUE parameter sets the reset value of each bit in the shift
register. All bits will get the same value, individual setting of reset values
is not implemented.
2015-07-15 17:26:00 -07:00
Dustin Richmond
84ebc073f1
Fixed a small bit-width related issue in counter.v.
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Fixed to satisfy linter. No change in functionality.
2015-07-15 16:44:50 -07:00
Dustin Richmond
98b09aa12a
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
