4 Commits

Author	SHA1	Message	Date
Dustin Richmond	ff9d11d2c1	Fixed two bugs, one in riffa.v, one in tx_data_fifo.v ... In riffa.v, the interrupt module was getting data from the TXC_DATA, which didn't match the assertion of the ready signal from the registers module. Changed to _wTxcData. In tx_data_fifo.v, changed the DATA_READY signal to connect to the fifo instead of the packet counter. In the tx_engine, removed the curious case of the +1 in the data fifo packet depth	2015-07-30 13:35:48 -07:00
Dustin Richmond	dc93333b9c	Fixing a bug in the tx_data_fifo where the data fifo was not large enough. ... The error occured when calculating the actual header fifo depth, C_ACTUAL_FIFO_DEPTH. This was initially clog2(C_FIFO_DEPTH), but should have been 1<<clog2(C_FIFO_DEPTH).	2015-07-29 08:33:11 -07:00
Dustin Richmond	31b82c1777	Adding graceful reset logic to the Ultrascale TX Engines ... The graceful reset logic splits the RST_IN port into the RST_BUS and RST_LOGIC ports. The RST_BUS port is for when the entire PCIe (or whatever) bus is undergoing reset and the RIFFA logic should not worry about corrupting any state by terminating a packet early (causing a malformed packet). RST_LOGIC is for logic resets, where PCIe state is not affected and may be corrupted by a malformed packet.	2015-07-22 17:29:35 -07:00
Dustin Richmond	98b09aa12a	Initial commit of RIFFA development repository (RIFFA 2.2)	2015-05-04 14:50:57 -07:00