Dustin Richmond
6ff69de5c6
Updating copyright statements for 2016
2016-02-09 15:23:37 -08:00
Dustin Richmond
d27b265b90
Updating bitfiles with bugfixes from past commits
2016-02-04 14:58:36 -08:00
Dustin Richmond
ce83bdefe1
Adding updated bit files and project files
2016-01-27 10:39:17 -08:00
Dustin Richmond
0fb6908dd3
Updating copyright statements with correct file names
2016-01-27 10:12:17 -08:00
Dustin Richmond
fee2c60a6b
updating project files, upgrading IP, and removing project errors
2016-01-26 11:30:02 -08:00
Dustin Richmond
ad101929f2
Updating board.mk makefiles to clean and reset xilinx projects
2016-01-26 11:15:21 -08:00
Dustin Richmond
025d2a424c
Correcting all C_NUM_CHNL parameters to 1 (for testing)
2016-01-25 16:51:19 -08:00
Dustin Richmond
cd204136c6
Further updates to hierarchical makefiles.
2016-01-25 16:37:33 -08:00
Dustin Richmond
680260b3f7
Adding copyright statments
2016-01-20 18:13:06 -08:00
Dustin Richmond
ad496b4c94
Mega-commit (which I usually like to avoid, but this one didn't really come cleanly)
...
The majority of this work can be summarized as: Makefiles have been added to
generate all of the boards, boards for each vendor, board, and projects for each
board.
To make things cleaner I renamed a few of the Xilinx projects, and may rename
the latera projects for consistency.
I removed the de5_qsys directory, and moved all projects into the de5 directory,
but those projects have a Q between DE5 and the PCIe specifications, ie
DE5QGen... (haven't updated the documentation)
Added c4dev board (untested)
Apologies to those of you who recently switched onto the DEVEL branch.
2016-01-20 17:46:39 -08:00
Dustin Richmond
9e4c9241a1
Updating ultrascale projects, and riffa documentation
...
The riffa documentation said that the 7-series core lacked Gen2x8 support. This
is incorrect.
2015-09-01 08:55:00 -07:00
Dustin Richmond
c9a68ddd7a
Updating ML605 files
2015-09-01 08:48:41 -07:00
Dustin Richmond
d2cb526218
Adding updated AC701 bit files
2015-08-13 08:37:35 -07:00
Dustin Richmond
bfa63eb3ad
Fixed a naming issue in the AC701 wrapper file.
...
tx_tlp_ready was named wTxTlpReady
2015-08-13 08:03:27 -07:00
Dustin Richmond
2f13ce9adc
Adding missing ac701 riffa wrapper file.
2015-08-13 08:01:01 -07:00
Dustin Richmond
c420b76c16
Finishing reset logic and testing/implementing across a wide swath of boards.
...
Changes are mostly in the RX logic, where RST_IN was still used, though some new
logic (reset_extender) was added to riffa.v. Updated projects for: VC709, VC707,
ZC706 (partial), NetFPGA, ADM-7V3, ML605 (Still not working), AC701 (Untested)
and KC705 (Untested)
2015-08-12 16:16:27 -07:00
Dustin Richmond
f836029e8d
Adding a few changes the the ML605 project.
...
Forgot to specify development board in the ip block, also commented out a ucf
file line.
2015-08-11 15:34:35 -07:00
Dustin Richmond
47530ee0cf
Adding AC701 projects for RIFFA 2.2.1.
...
Also fixed a small bug in the KC705 riffa wrapper, and KC705 boards
2015-08-11 15:33:49 -07:00
Dustin Richmond
e13b825fa1
Adding VERY PRELIMINARY ML605 development board files.
2015-07-31 15:29:00 -07:00
Dustin Richmond
f0efc47981
Adding preliminary VCU108 and KCU105 projects.
...
Also fixed a warning in the riffa.v file where a /* was in a comment
2015-07-31 15:19:52 -07:00
Dustin Richmond
f96391061e
Updating 7V3 board for bug fixes, and adding preliminary support for new boards.
...
Added and tested the 7V3 and NetFPGA board projects. Added the KC705 board (Gen1
and Gen2, but haven't tested them)
2015-07-30 15:45:13 -07:00
Dustin Richmond
d0e4df9737
Adding the Gen2 and Gen3 projects for the ADM 7V3 board
2015-07-29 08:32:44 -07:00
Dustin Richmond
e11eb70853
Adding AlphaData 7V3 project for user.
...
Does not meet timing, may have potential bug in TX Engine Logic
2015-07-27 11:20:38 -07:00
Dustin Richmond
98b09aa12a
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
