5 Commits

Author	SHA1	Message	Date
Dustin Richmond	5ee3747243	Replaced RST_IN with RST_BUS and RST_LOGIC and addded DONE_RST in top level engine layer files. ... Still need to propagate the changes and hook the resets up in the formatters, multiplexers, etc. RST_BUS will be the equivalent of a PCIe PERST Pin reset, a general inelegant reset where formatting is disregarded. RST_LOGIC is a reset caused by application or higher level logic, where formatting needs to be considered so that the bus does not lock up. DONE_RST will signal that the engine layer has finished resetting, and is ready to transmit data.	2015-07-16 12:07:04 -07:00
Dustin Richmond	744953c2ad	Adding resetter.v, a new module that controls the reset logic in riffa.v. ... This logic will allow us to reset the TX pipeline safely, and still transmit the status completion. This is a feature requested by the NetFPGA team.	2015-07-15 17:27:17 -07:00
Dustin Richmond	d5f3ba7309	Added a parameter C_VALUE to shiftreg.v and changed all declarations. ... The C_VALUE parameter sets the reset value of each bit in the shift register. All bits will get the same value, individual setting of reset values is not implemented.	2015-07-15 17:26:00 -07:00
Dustin Richmond	84ebc073f1	Fixed a small bit-width related issue in counter.v. ... Fixed to satisfy linter. No change in functionality.	2015-07-15 16:44:50 -07:00
Dustin Richmond	98b09aa12a	Initial commit of RIFFA development repository (RIFFA 2.2)	2015-05-04 14:50:57 -07:00