Changes are mostly in the RX logic, where RST_IN was still used, though some new
logic (reset_extender) was added to riffa.v. Updated projects for: VC709, VC707,
ZC706 (partial), NetFPGA, ADM-7V3, ML605 (Still not working), AC701 (Untested)
and KC705 (Untested)
In riffa.v, the interrupt module was getting data from the TXC_DATA, which didn't match the assertion of the ready signal from the registers module. Changed to _wTxcData.
In tx_data_fifo.v, changed the DATA_READY signal to connect to the fifo instead of the packet counter.
In the tx_engine, removed the curious case of the +1 in the data fifo packet depth
