In riffa.v, the interrupt module was getting data from the TXC_DATA, which didn't match the assertion of the ready signal from the registers module. Changed to _wTxcData.
In tx_data_fifo.v, changed the DATA_READY signal to connect to the fifo instead of the packet counter.
In the tx_engine, removed the curious case of the +1 in the data fifo packet depth
The error occured when calculating the actual header fifo depth,
C_ACTUAL_FIFO_DEPTH. This was initially clog2(C_FIFO_DEPTH), but should have
been 1<<clog2(C_FIFO_DEPTH).
The graceful reset logic splits the RST_IN port into the RST_BUS and RST_LOGIC
ports. The RST_BUS port is for when the entire PCIe (or whatever) bus is
undergoing reset and the RIFFA logic should not worry about corrupting any state
by terminating a packet early (causing a malformed packet). RST_LOGIC is for logic resets, where PCIe state is not affected and may be corrupted by a malformed packet.
