Dustin Richmond
744953c2ad
Adding resetter.v, a new module that controls the reset logic in riffa.v.
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This logic will allow us to reset the TX pipeline safely, and still transmit the
status completion. This is a feature requested by the NetFPGA team.
2015-07-15 17:27:17 -07:00
Dustin Richmond
d5f3ba7309
Added a parameter C_VALUE to shiftreg.v and changed all declarations.
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The C_VALUE parameter sets the reset value of each bit in the shift
register. All bits will get the same value, individual setting of reset values
is not implemented.
2015-07-15 17:26:00 -07:00
Dustin Richmond
84ebc073f1
Fixed a small bit-width related issue in counter.v.
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Fixed to satisfy linter. No change in functionality.
2015-07-15 16:44:50 -07:00
Dustin Richmond
28fdcedfba
Updating license headers for a few files that snuck through.
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These files contained copies of our older license (Modified BSD), which has been
replaced by the new license (BSD 3-Clause)
2015-07-15 15:55:09 -07:00
Dustin Richmond
66bf96b098
Fixing a two small typos in the documentation.
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These typos only affected Expert Altera users
2015-07-15 10:26:04 -07:00
Dustin Richmond
81be51cb50
Adding RIFFA documentation files.
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Most of this documentation is identical to what you can find in the RIFFA 2.2
distribution. I have added Chapter 6 describing the architecture of RIFFA and
should help those who wish to help develop or modify RIFFA in the future.
2015-07-14 09:43:51 -07:00
Dustin Richmond
8836ab92eb
Adding fix for windows driver issue where consecutive small transfers can get corrupted
2015-06-22 08:42:25 -07:00
Dustin Richmond
8fc60c9f63
Changing name of the repository to riffa, from riffa-devel
2015-05-04 15:11:26 -07:00
Dustin Richmond
6c320e7574
Updating README.md file
2015-05-04 14:53:51 -07:00
Dustin Richmond
98b09aa12a
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
drichmond
98c75e7f31
Initial commit
2015-05-04 14:24:17 -07:00
