Dustin Richmond
778c42e74b
First attempt (and maybe only) at fixing a bug in the CHNL_TX interface.
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In the interface, CHNL_TX_DATA_REN was remaining asserted for two cycles after CHNL_TX was deasserted. This has been fixed, and CHNL_TX_DATA_REN now deasserts one cycle after CHNL_TX is deasserted.
2016-07-18 16:28:11 -07:00
Dustin Richmond
1d228c190d
Fixing more backwards compatibility issues
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Had to remove some method calls
2016-06-29 16:39:16 -07:00
Dustin Richmond
64cd40f0b6
Fixing the missing registers for real (I misread the problem)
2016-06-29 15:59:23 -07:00
Dustin Richmond
35b2730aa5
Merge branch 'devel/RIFFA/2.2.2' of github.com:drichmond/riffa into devel/RIFFA/2.2.2
2016-06-29 15:43:25 -07:00
Dustin Richmond
57e389ef81
Fixing some capability problems in the linux driver.
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Fixing register define #ifdef macros, because I thought they looked ugly
Implementing method bodies instead of empty methods, because I really would like
that functionality, even if it is for the purpose of debate.
2016-06-29 15:42:05 -07:00
Dustin Richmond
cd494e1ea5
Adding linux/slab.h to riffa_driver.c, which fixes a driver compilation problem on some ARM platforms.
2016-06-29 14:53:47 -07:00
Dustin Richmond
4e898fcf35
Fixing unsigned windows driver issue
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Issue was invalid path in makefile.inc that allowed the build script to
"pass" but fail to sign the RIFFA catalog file and driver (!). This
issue has been fixed, and more comments have been added to the README to
avoid this issue in the future.
2016-06-29 14:43:38 -07:00
Dustin Richmond
af7c5928f2
Merge pull request #6 from jrobrien/py3k-x64
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Add support for 64 bit pointers and Python 3
2016-05-09 16:27:23 -07:00
Jonathan O'Brien
718d167823
Manually fixed up copyright date.
2016-03-28 11:09:18 -07:00
Jonathan O'Brien
58fd605f35
Add support for 64 bit arch and python 3
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Added signature to pass *data as pointer instead of int (default) which
was causing problems on 64 bit systems. Use truncating division
operator to support python 3.
2016-03-28 10:50:08 -07:00
Dustin Richmond
2849235361
Committing RIFFA 2.2.1 into master
2016-03-14 08:20:08 -07:00
Dustin Richmond
17bdf731e6
Updating bitfiles for latest bug fix
2016-02-22 14:26:35 -08:00
Dustin Richmond
62137cabad
Fixed a bug in the TX Multiplexer, write notification logic. The write
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notification buffer was too small.
2016-02-22 13:32:59 -08:00
Dustin Richmond
255fb848cb
Another bit file update
2016-02-18 12:35:46 -08:00
Dustin Richmond
4f78805fd5
Adding a new feature to the makefiles, where typing make release in the top
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directory will package (most of) a new release
2016-02-18 11:14:09 -08:00
Dustin Richmond
4d0bc24319
Fixed a bug (uncovered by the clock ratio issue) where the tx_multiplexer would
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confuse the tx_port_monitor by returning too few or too many write-packet
acknowledgements, resulting in a hang (but correct data!).
2016-02-16 16:04:10 -08:00
Dustin Richmond
753ffffd93
Fixed a bug where a clock ratio of less than 1:2 between the user-provided clock
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and the PCIe core clock would cause some transfers to return 0 words (but not
hang).
2016-02-16 16:02:42 -08:00
Dustin Richmond
eb75cd688e
Fixing results path
2016-02-09 15:55:32 -08:00
Dustin Richmond
79ab9253a1
Adding copyright statements to example and test applications
2016-02-09 15:49:01 -08:00
Dustin Richmond
6ff69de5c6
Updating copyright statements for 2016
2016-02-09 15:23:37 -08:00
Dustin Richmond
02c144fbfb
Adding corrected bit-file for DE4 Gen1 64-bit interface
2016-02-09 13:03:01 -08:00
Dustin Richmond
5118d0eeb2
Adding the applications we use to test before release
2016-02-09 10:06:31 -08:00
Dustin Richmond
d27b265b90
Updating bitfiles with bugfixes from past commits
2016-02-04 14:58:36 -08:00
Dustin Richmond
2e5f37f633
Merge branch 'marzoul-linux-safelock' into devel/RIFFA/2.2.1
2016-02-04 11:05:44 -08:00
Dustin Richmond
bc8999eba4
Fixed a bug where the tx_multiplexer kept LBE field high on packets of 1 DW in length.
2016-02-04 11:03:06 -08:00
Dustin Richmond
2a832ffe4e
Fixed a bug in the TX Alignment Pipeline where two EOFs in a cycle from the Data
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Fifo would cause corruption in subsequent transfers.
2016-02-02 17:14:29 -08:00
Dustin Richmond
4da00b7d84
Merge branch 'linux-safelock' of git://github.com/marzoul/riffa into marzoul-linux-safelock
2016-01-28 09:46:29 -08:00
Dustin Richmond
ce83bdefe1
Adding updated bit files and project files
2016-01-27 10:39:17 -08:00
Dustin Richmond
ceb60c92f9
Adding source search path in C4 Development board example design
2016-01-27 10:16:50 -08:00
Dustin Richmond
0fb6908dd3
Updating copyright statements with correct file names
2016-01-27 10:12:17 -08:00
Dustin Richmond
e60f64efe2
Adding additional commands to base Makefile
2016-01-26 11:31:06 -08:00
Dustin Richmond
fee2c60a6b
updating project files, upgrading IP, and removing project errors
2016-01-26 11:30:02 -08:00
Dustin Richmond
ad101929f2
Updating board.mk makefiles to clean and reset xilinx projects
2016-01-26 11:15:21 -08:00
Dustin Richmond
83ebefe37e
Removing unnecessary file from riffa.mk
2016-01-26 11:14:34 -08:00
Dustin Richmond
025d2a424c
Correcting all C_NUM_CHNL parameters to 1 (for testing)
2016-01-25 16:51:19 -08:00
Dustin Richmond
cd204136c6
Further updates to hierarchical makefiles.
2016-01-25 16:37:33 -08:00
Dustin Richmond
680260b3f7
Adding copyright statments
2016-01-20 18:13:06 -08:00
Dustin Richmond
ad496b4c94
Mega-commit (which I usually like to avoid, but this one didn't really come cleanly)
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The majority of this work can be summarized as: Makefiles have been added to
generate all of the boards, boards for each vendor, board, and projects for each
board.
To make things cleaner I renamed a few of the Xilinx projects, and may rename
the latera projects for consistency.
I removed the de5_qsys directory, and moved all projects into the de5 directory,
but those projects have a Q between DE5 and the PCIe specifications, ie
DE5QGen... (haven't updated the documentation)
Added c4dev board (untested)
Apologies to those of you who recently switched onto the DEVEL branch.
2016-01-20 17:46:39 -08:00
Dustin Richmond
c209dac5d3
Fixing a small bug in the tx_port_buffer related to xilinx synthesis in Xilinx
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2015 versions.
2016-01-15 15:34:33 -08:00
Adrien Prost-Boucle
9f791acfea
Linux driver: Protect recv and send with atomic test and set instead of lock to enable clear at reset
2016-01-06 17:34:41 +01:00
Adrien Prost-Boucle
3775133808
Use appropriate ioctl return codes
2015-12-14 15:16:29 +01:00
Adrien Prost-Boucle
4369d5b6ef
Linux driver: Protect recv and send from conflicting simultaneous access
2015-10-23 14:34:00 +02:00
Dustin Richmond
7b1d9b2dfd
Merge branch 'master' into devel/RIFFA/2.2.1
2015-09-14 09:53:57 -07:00
Dustin Richmond
9e4c9241a1
Updating ultrascale projects, and riffa documentation
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The riffa documentation said that the 7-series core lacked Gen2x8 support. This
is incorrect.
2015-09-01 08:55:00 -07:00
Dustin Richmond
c9a68ddd7a
Updating ML605 files
2015-09-01 08:48:41 -07:00
Dustin Richmond
78a7130dec
Fixed the Virtex-7 documentation.
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Stated that Gen2 x8 was not available. That is incorrect
2015-08-28 09:44:56 -07:00
Dustin Richmond
3d3f866649
Fixing a bug in the RXR engines/RXC Engines that seems to only affect DE4 Gen2
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devices.
On IP Compiler devices, it is apparently possible to have valid drop
mid-packet. This condition is now checked, and has been tested (though new bit
files have not be uploaded)
2015-08-26 16:14:40 -07:00
Dustin Richmond
d6c5115c10
Cleaning up more reset logic (no real changes)
2015-08-26 16:11:33 -07:00
Dustin Richmond
ad83ed811c
To reduce confusion, renaming riffa.tex and riffa.pdf
2015-08-26 07:37:39 -07:00
Dustin Richmond
918665aff2
Adding BSD 3-Clause licenses to files that were missing it.
2015-08-26 07:33:40 -07:00
