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mirror of https://github.com/KastnerRG/riffa.git synced 2025-01-30 23:02:54 +08:00

2 Commits

Author SHA1 Message Date
Dustin Richmond
744953c2ad Adding resetter.v, a new module that controls the reset logic in riffa.v.
This logic will allow us to reset the TX pipeline safely, and still transmit the
status completion. This is a feature requested by the NetFPGA team.
2015-07-15 17:27:17 -07:00
Dustin Richmond
98b09aa12a Initial commit of RIFFA development repository (RIFFA 2.2) 2015-05-04 14:50:57 -07:00