5 Commits

Author	SHA1	Message	Date
Dustin Richmond	f0efc47981	Adding preliminary VCU108 and KCU105 projects. ... Also fixed a warning in the riffa.v file where a /* was in a comment	2015-07-31 15:19:52 -07:00
Dustin Richmond	ff9d11d2c1	Fixed two bugs, one in riffa.v, one in tx_data_fifo.v ... In riffa.v, the interrupt module was getting data from the TXC_DATA, which didn't match the assertion of the ready signal from the registers module. Changed to _wTxcData. In tx_data_fifo.v, changed the DATA_READY signal to connect to the fifo instead of the packet counter. In the tx_engine, removed the curious case of the +1 in the data fifo packet depth	2015-07-30 13:35:48 -07:00
Dustin Richmond	1254f44441	Adding graceful reset logic to the RIFFA core.	2015-07-27 10:31:16 -07:00
Dustin Richmond	744953c2ad	Adding resetter.v, a new module that controls the reset logic in riffa.v. ... This logic will allow us to reset the TX pipeline safely, and still transmit the status completion. This is a feature requested by the NetFPGA team.	2015-07-15 17:27:17 -07:00
Dustin Richmond	98b09aa12a	Initial commit of RIFFA development repository (RIFFA 2.2)	2015-05-04 14:50:57 -07:00