The majority of this work can be summarized as: Makefiles have been added to
generate all of the boards, boards for each vendor, board, and projects for each
board.
To make things cleaner I renamed a few of the Xilinx projects, and may rename
the latera projects for consistency.
I removed the de5_qsys directory, and moved all projects into the de5 directory,
but those projects have a Q between DE5 and the PCIe specifications, ie
DE5QGen... (haven't updated the documentation)
Added c4dev board (untested)
Apologies to those of you who recently switched onto the DEVEL branch.
devices.
On IP Compiler devices, it is apparently possible to have valid drop
mid-packet. This condition is now checked, and has been tested (though new bit
files have not be uploaded)
Changes are mostly in the RX logic, where RST_IN was still used, though some new
logic (reset_extender) was added to riffa.v. Updated projects for: VC709, VC707,
ZC706 (partial), NetFPGA, ADM-7V3, ML605 (Still not working), AC701 (Untested)
and KC705 (Untested)
In riffa.v, the interrupt module was getting data from the TXC_DATA, which didn't match the assertion of the ready signal from the registers module. Changed to _wTxcData.
In tx_data_fifo.v, changed the DATA_READY signal to connect to the fifo instead of the packet counter.
In the tx_engine, removed the curious case of the +1 in the data fifo packet depth
The error occured when calculating the actual header fifo depth,
C_ACTUAL_FIFO_DEPTH. This was initially clog2(C_FIFO_DEPTH), but should have
been 1<<clog2(C_FIFO_DEPTH).
This does not fix the user bug, which occurs in the 64-bit interface. I suspect
this is a data under-read/over-read error in the data fifo but I have yet to
confirm it.
The graceful reset logic splits the RST_IN port into the RST_BUS and RST_LOGIC
ports. The RST_BUS port is for when the entire PCIe (or whatever) bus is
undergoing reset and the RIFFA logic should not worry about corrupting any state
by terminating a packet early (causing a malformed packet). RST_LOGIC is for logic resets, where PCIe state is not affected and may be corrupted by a malformed packet.
The reset_controller module will safely reset a single stage pipeline without
using an asychronous reset (bleh). It is intended for use in the TX engines,
where it will control the output stage of the engine, and provide a gracefull
end-of-packet reset.
Bug caused received 128-bit Request Headers without payload to signal data word valid one cycle early. May not be a final fix. Unlikely to affect current users.
