The error occured when calculating the actual header fifo depth,
C_ACTUAL_FIFO_DEPTH. This was initially clog2(C_FIFO_DEPTH), but should have
been 1<<clog2(C_FIFO_DEPTH).
The graceful reset logic splits the RST_IN port into the RST_BUS and RST_LOGIC
ports. The RST_BUS port is for when the entire PCIe (or whatever) bus is
undergoing reset and the RIFFA logic should not worry about corrupting any state
by terminating a packet early (causing a malformed packet). RST_LOGIC is for logic resets, where PCIe state is not affected and may be corrupted by a malformed packet.
Expanded DONE_RST into four signals, for each of the four engine interfaces. In
the ultrascale engines, wired up all of the RST and DONE_RST signals. Quickly tested the logic in a power-on-reset like situation, no guarantees on graceful in-transmission resets. Classic engines will have to wait.
