riffa

FPGA/riffa

Fork 0

mirror of https://github.com/KastnerRG/riffa.git synced 2025-01-30 23:02:54 +08:00

Commit Graph

Author	SHA1	Message	Date
Dustin Richmond	eb1a3934c4	Fixing/updating makefiles for new xilinx clock test projects	2016-08-11 13:54:54 -07:00
Dustin Richmond	22d6da6537	Renaming Xilinx projects	2016-08-11 13:28:37 -07:00
Dustin Richmond	2499f4ff10	Commiting fix for 40-mhz missing-dword bug. In rare cases, when using a slow clock frequency the first C_PCI_DATA_WIDTH/32 dwords would be dropped during a TX transaction (FPGA to host). This was caused by an earlier bug fix, also addressing slow clock frequencies. In this case, the fix caused RD_EN to stay high for too long, which subsequently caused the first dwords to be dropped. Also adding: New testing projects which instantiate 12 channels, each with a different clock frequency, and a test script (asyncutil.sh) to test these projects.	2016-08-11 13:07:00 -07:00

Author

SHA1

Message

Date

Dustin Richmond

eb1a3934c4

Fixing/updating makefiles for new xilinx clock test projects

2016-08-11 13:54:54 -07:00

Dustin Richmond

22d6da6537

Renaming Xilinx projects

2016-08-11 13:28:37 -07:00

Dustin Richmond

2499f4ff10

Commiting fix for 40-mhz missing-dword bug.

In rare cases, when using a slow clock frequency the first C_PCI_DATA_WIDTH/32 dwords would be dropped during a TX transaction (FPGA to host). This was caused by an earlier bug fix, also addressing slow clock frequencies.

In this case, the fix caused RD_EN to stay high for too long, which subsequently caused the first dwords to be dropped.

Also adding: New testing projects which instantiate 12 channels, each with a different clock frequency, and a test script (asyncutil.sh) to test these projects.

2016-08-11 13:07:00 -07:00

3 Commits