riffa

FPGA/riffa

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Commit Graph

Author	SHA1	Message	Date
Dustin Richmond	31b82c1777	Adding graceful reset logic to the Ultrascale TX Engines The graceful reset logic splits the RST_IN port into the RST_BUS and RST_LOGIC ports. The RST_BUS port is for when the entire PCIe (or whatever) bus is undergoing reset and the RIFFA logic should not worry about corrupting any state by terminating a packet early (causing a malformed packet). RST_LOGIC is for logic resets, where PCIe state is not affected and may be corrupted by a malformed packet.	2015-07-22 17:29:35 -07:00
Dustin Richmond	505c72d16f	Adding new reset_controller.v file. The reset_controller module will safely reset a single stage pipeline without using an asychronous reset (bleh). It is intended for use in the TX engines, where it will control the output stage of the engine, and provide a gracefull end-of-packet reset.	2015-07-22 17:25:09 -07:00

Author

SHA1

Message

Date

Dustin Richmond

31b82c1777

Adding graceful reset logic to the Ultrascale TX Engines

The graceful reset logic splits the RST_IN port into the RST_BUS and RST_LOGIC
ports. The RST_BUS port is for when the entire PCIe (or whatever) bus is
undergoing reset and the RIFFA logic should not worry about corrupting any state
by terminating a packet early (causing a malformed packet). RST_LOGIC is for logic resets, where PCIe state is not affected and may be corrupted by a malformed packet.

2015-07-22 17:29:35 -07:00

Dustin Richmond

505c72d16f

Adding new reset_controller.v file.

The reset_controller module will safely reset a single stage pipeline without
using an asychronous reset (bleh). It is intended for use in the TX engines,
where it will control the output stage of the engine, and provide a gracefull
end-of-packet reset.

2015-07-22 17:25:09 -07:00

2 Commits