riffa

FPGA/riffa

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Commit Graph

Author	SHA1	Message	Date
Dustin Richmond	5058a758fc	Adding timing improvements to tx_alignment pipeline. This does not fix the user bug, which occurs in the 64-bit interface. I suspect this is a data under-read/over-read error in the data fifo but I have yet to confirm it.	2015-07-27 19:26:55 -07:00
Dustin Richmond	31b82c1777	Adding graceful reset logic to the Ultrascale TX Engines The graceful reset logic splits the RST_IN port into the RST_BUS and RST_LOGIC ports. The RST_BUS port is for when the entire PCIe (or whatever) bus is undergoing reset and the RIFFA logic should not worry about corrupting any state by terminating a packet early (causing a malformed packet). RST_LOGIC is for logic resets, where PCIe state is not affected and may be corrupted by a malformed packet.	2015-07-22 17:29:35 -07:00
Dustin Richmond	98b09aa12a	Initial commit of RIFFA development repository (RIFFA 2.2)	2015-05-04 14:50:57 -07:00

Author

SHA1

Message

Date

Dustin Richmond

5058a758fc

Adding timing improvements to tx_alignment pipeline.

This does not fix the user bug, which occurs in the 64-bit interface. I suspect
this is a data under-read/over-read error in the data fifo but I have yet to
confirm it.

2015-07-27 19:26:55 -07:00

Dustin Richmond

31b82c1777

Adding graceful reset logic to the Ultrascale TX Engines

The graceful reset logic splits the RST_IN port into the RST_BUS and RST_LOGIC
ports. The RST_BUS port is for when the entire PCIe (or whatever) bus is
undergoing reset and the RIFFA logic should not worry about corrupting any state
by terminating a packet early (causing a malformed packet). RST_LOGIC is for logic resets, where PCIe state is not affected and may be corrupted by a malformed packet.

2015-07-22 17:29:35 -07:00

Dustin Richmond

98b09aa12a

Initial commit of RIFFA development repository (RIFFA 2.2)

2015-05-04 14:50:57 -07:00

3 Commits