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Code Issues Projects Releases Wiki Activity

Commit Graph

  • 025d2a424c Correcting all C_NUM_CHNL parameters to 1 (for testing) Dustin Richmond 2016-01-25 16:51:19 -08:00
  • cd204136c6 Further updates to hierarchical makefiles. Dustin Richmond 2016-01-25 16:37:33 -08:00
  • 680260b3f7 Adding copyright statments Dustin Richmond 2016-01-20 18:13:06 -08:00
  • ad496b4c94 Mega-commit (which I usually like to avoid, but this one didn't really come cleanly) Dustin Richmond 2016-01-20 17:46:39 -08:00
  • c209dac5d3 Fixing a small bug in the tx_port_buffer related to xilinx synthesis in Xilinx 2015 versions. Dustin Richmond 2016-01-15 15:34:33 -08:00
  • 9dd20c0bd2 Merge 9f791acfea31def8b248e53b255d01b9d19914c3 into 78a7130decce6102642672fabdb9095297b1f89d marzoul 2016-01-07 20:35:07 +00:00
  • 9f791acfea Linux driver: Protect recv and send with atomic test and set instead of lock to enable clear at reset Adrien Prost-Boucle 2016-01-06 17:34:41 +01:00
  • 3775133808 Use appropriate ioctl return codes Adrien Prost-Boucle 2015-12-14 15:16:29 +01:00
  • 4369d5b6ef Linux driver: Protect recv and send from conflicting simultaneous access Adrien Prost-Boucle 2015-10-23 14:34:00 +02:00
  • 7b1d9b2dfd Merge branch 'master' into devel/RIFFA/2.2.1 Dustin Richmond 2015-09-14 09:53:57 -07:00
  • 9e4c9241a1 Updating ultrascale projects, and riffa documentation Dustin Richmond 2015-09-01 08:55:00 -07:00
  • c9a68ddd7a Updating ML605 files Dustin Richmond 2015-09-01 08:48:41 -07:00
  • 78a7130dec Fixed the Virtex-7 documentation. Dustin Richmond 2015-08-28 09:44:56 -07:00
  • 3d3f866649 Fixing a bug in the RXR engines/RXC Engines that seems to only affect DE4 Gen2 devices. Dustin Richmond 2015-08-26 16:14:40 -07:00
  • d6c5115c10 Cleaning up more reset logic (no real changes) Dustin Richmond 2015-08-26 16:11:33 -07:00
  • ad83ed811c To reduce confusion, renaming riffa.tex and riffa.pdf Dustin Richmond 2015-08-26 07:37:39 -07:00
  • 918665aff2 Adding BSD 3-Clause licenses to files that were missing it. Dustin Richmond 2015-08-26 07:33:40 -07:00
  • d2cb526218 Adding updated AC701 bit files Dustin Richmond 2015-08-13 08:37:35 -07:00
  • bfa63eb3ad Fixed a naming issue in the AC701 wrapper file. Dustin Richmond 2015-08-13 08:03:27 -07:00
  • 2f13ce9adc Adding missing ac701 riffa wrapper file. Dustin Richmond 2015-08-13 08:01:01 -07:00
  • c420b76c16 Finishing reset logic and testing/implementing across a wide swath of boards. Dustin Richmond 2015-08-12 16:16:27 -07:00
  • 9d7543a5ff Adding DE2 project files (only slightly tested) Dustin Richmond 2015-08-11 16:47:13 -07:00
  • f836029e8d Adding a few changes the the ML605 project. Dustin Richmond 2015-08-11 15:34:35 -07:00
  • 47530ee0cf Adding AC701 projects for RIFFA 2.2.1. Dustin Richmond 2015-08-11 15:33:49 -07:00
  • e13b825fa1 Adding VERY PRELIMINARY ML605 development board files. Dustin Richmond 2015-07-31 15:29:00 -07:00
  • f0efc47981 Adding preliminary VCU108 and KCU105 projects. Dustin Richmond 2015-07-31 15:19:52 -07:00
  • f96391061e Updating 7V3 board for bug fixes, and adding preliminary support for new boards. Dustin Richmond 2015-07-30 15:45:13 -07:00
  • ff9d11d2c1 Fixed two bugs, one in riffa.v, one in tx_data_fifo.v Dustin Richmond 2015-07-30 13:35:48 -07:00
  • dc93333b9c Fixing a bug in the tx_data_fifo where the data fifo was not large enough. Dustin Richmond 2015-07-29 08:33:11 -07:00
  • d0e4df9737 Adding the Gen2 and Gen3 projects for the ADM 7V3 board Dustin Richmond 2015-07-29 08:32:44 -07:00
  • 5058a758fc Adding timing improvements to tx_alignment pipeline. Dustin Richmond 2015-07-27 19:26:55 -07:00
  • e11eb70853 Adding AlphaData 7V3 project for user. Dustin Richmond 2015-07-27 11:20:38 -07:00
  • 1254f44441 Adding graceful reset logic to the RIFFA core. Dustin Richmond 2015-07-27 10:31:16 -07:00
  • 924d52e6ab Finalized reset logic in the classic engines (see previous commit) Dustin Richmond 2015-07-23 09:56:44 -07:00
  • 31b82c1777 Adding graceful reset logic to the Ultrascale TX Engines Dustin Richmond 2015-07-22 17:29:35 -07:00
  • 505c72d16f Adding new reset_controller.v file. Dustin Richmond 2015-07-22 17:25:09 -07:00
  • e2f3abe01b Fixed a bug in RIFFA 2.2 for the Classic Xilinx 128-bit interface. Dustin Richmond 2015-07-21 15:46:36 -07:00
  • 5be7627910 Added a S_AXIS_**_TREADY Check on the reset logic in the ultrascale engines. Dustin Richmond 2015-07-17 16:54:06 -07:00
  • ad90d61584 Finished wiring reset logic in the Engine Layer (untested) Dustin Richmond 2015-07-16 16:26:05 -07:00
  • 5ee3747243 Replaced RST_IN with RST_BUS and RST_LOGIC and addded DONE_RST in top level engine layer files. Dustin Richmond 2015-07-16 12:07:04 -07:00
  • 744953c2ad Adding resetter.v, a new module that controls the reset logic in riffa.v. Dustin Richmond 2015-07-15 17:27:17 -07:00
  • d5f3ba7309 Added a parameter C_VALUE to shiftreg.v and changed all declarations. Dustin Richmond 2015-07-15 17:26:00 -07:00
  • 84ebc073f1 Fixed a small bit-width related issue in counter.v. Dustin Richmond 2015-07-15 16:44:50 -07:00
  • 28fdcedfba Updating license headers for a few files that snuck through. Dustin Richmond 2015-07-15 15:53:19 -07:00
  • 66bf96b098 Fixing a two small typos in the documentation. Dustin Richmond 2015-07-15 10:26:04 -07:00
  • 81be51cb50 Adding RIFFA documentation files. Dustin Richmond 2015-07-14 09:43:51 -07:00
  • 8836ab92eb Adding fix for windows driver issue where consecutive small transfers can get corrupted Dustin Richmond 2015-06-22 08:42:25 -07:00
  • 8fc60c9f63 Changing name of the repository to riffa, from riffa-devel Dustin Richmond 2015-05-04 15:11:26 -07:00
  • 6c320e7574 Updating README.md file Dustin Richmond 2015-05-04 14:53:51 -07:00
  • 98b09aa12a Initial commit of RIFFA development repository (RIFFA 2.2) Dustin Richmond 2015-05-04 14:50:57 -07:00
  • 98c75e7f31 Initial commit drichmond 2015-05-04 14:24:17 -07:00