Engine Layer PCIe Core (Xilinx Gen1,2) PCIe Core (Altera Gen 1,2,3) Config Interface Interrupt Interface TX Interface RX Interface Config Interface Interrupt Interface TX Interface RX Interface SG DMA Layer BAR Memory Space RX Scatter Gather List Reader TX Scatter Gather List Reader Data Abstraction / DMA Layer (RIFFA) DMA Data Read Engine DMA Data Write Engine Channel Interface (RIFFA) User Application Completion Merge/Reorder Buffer Data Packer Write Buffer RX Channel TX Channel Rx Completion (RxC) Interface RX Request (RxR) Interface Tx Request Interface Tx Completion Interface Interrupt Engine Config Interface TXR Formatter RX Engine RXR Engine RXC Engine TX Engine Mux Fifo Fifo Arbiter TX Engine TXC Formatting Pipeline TXR Formatting Pipeline Rate Limiter TX Rate Limiter RX Request (RxR) Interface Tx Completion (TxC) Tx Request (TxR) Mux Rx Completion (RxC) Config Interface Interrupt Interface Ultrascale Translation Layer Xilinx Ultrascale Core Classic Translation Layer M_AXIS_RX_TDATA[C_PCI_DWIDTH-1:0] M_AXIS_RX_TKEEP[(C_PCI_DWIDTH/8)-1:0] M_AXIS_RX_TLAST M_AXIS_RX_TVALID M_AXIS_RX_TREADY S_AXIS_SRC_DSC S_AXIS_TX_TDATA[C_PCI_DWIDTH-1:0] S_AXIS_TX_TKEEP[(C_PCI_DWIDTH/8)-1:0] S_AXIS_TX_TVALID S_AXIS_TX_TREADY S_AXIS_TX_TLAST CFG_INTERRUPT_ASSERT INTR_LEGACY_CLR CFG_LINK_WIDTH CFG_LINK_RATE CFG_BUS_MSTR_ENABLE COMPLETER_ID MAX_READ_REQUEST_SIZE MAX_PAYLOAD_SIZE IS_EOF[3;0] (128 Only) RX_ST_SOP[1:0] RX_ST_VALID RX_ST_EOP[1:0] RX_ST_READY APP_INT_STS APP_MSI_REQ CURRENTSPEED[1:0] TL_CFG_CTL[21:0] TL_CFG_ADD[4:0] TL_CFG_STS[52:0] TX_ST_READY TX_ST_EOP TX_ST_VALID TX_ST_DATA[C_PCI_DWIDTH-1:0] APP_MSI_ACK APP_INT_ACK CFG_INTERRUPT_MSIENABLE RX_ST_EMPTY[1:0] RERR_FWD IS_SOF[3:0] (128 only) CFG_INTERRUPT CFG_INTERRUPT_RDY RX_ST_DATA[C_PCI_DWIDTH-1:0] TX_ST_EMPTY[1:0] TX_ST_SOP RX_TLP[C_PCI_DWIDTH-1:0] RX_TLP_VALID RX_TLP_READY RX_TLP_END_OFFSET[3:0] RX_TLP_START_OFFSET[3:0] RX_TLP_START_FLAG RX_TLP_END_FLAG INTR_LEGACY_READY INTR_MSI_READY INTR_LEGACY_REQUEST INTR_MSI_REQUEST INTR_MSI_NUM[4:0] CFG_MSI_NUM[4;0] CONFIG_COMPLETER_ID CONFIG_BUS_MASTER_ENABLE CONFIG_LINK_WIDTH CONFIG_LINK_RATE CONFIG_MAX_PAYLOAD CONFIG_MAX_READ_REQUEST CONFIG_MSI_ENABLE TX_TLP_READY TX_TLP_VALID TX_TLP_END_OFFSET[3:0] TX_TLP_END_FLAG TX_TLP_START_FLAG TX_TLP_START_OFFSET[3:0] TX_TLP[C_PCI_DWIDTH-1:0] RX_TLP_BAR_DECODE[7:0] RXR_BAR_DECODED[8:0] RXR_ADDR[63:0] RXR_REQUESTER_ID[15:0] RXR_LENGTH[10:0] RXR_TAG[7:0] RXR_REQUEST_TYPE[3:0] RXR_DATA_START_FLAG RXR_DATA_VALID RXR_ATTR[2:0] RXR_TC[2:0] RXR_DATA_END_OFFSET[3:0] RXR_DATA[C_PCI_DWIDTH-1:0] RXR_DATA_END_FLAG RXR_DATA_START_OFFSET[3:0] RXR_DATA_READY RXC_META_ADDR[7:0] RXC_META_TAG[7:0] RXC_META_LENGTH[9:0] RXC_DATA_FDWBE[3:0] RXC_DATA_LDWBE[3:0] RXC_DATA[C_PCI_DWIDTH-1:0] RXC_META_BYTES_REMAINING[12:0] RXC_META_COMPLETER_ID[15:0] RXC_DATA_READY RXC_DATA_VALID RXC_DATA_START_FLAG RXC_DATA_END_FLAG RXC_DATA_END_OFFSET[3:0] RXC_DATA_START_OFFSET[3:0] INTR_MSI_REQUEST INTR_MSI_NUMBER[4:0] INTR_MSI_ACK CONFIG_COMPLETER_ID CONFIG_BUS_MASTER_ENABLE CONFIG_LINK_WIDTH CONFIG_LINK_RATE CONFIG_MAX_READ_REQUEST CONFIG_MAX_PAYLOAD CONFIG_MSIENABLE TXC_DATA[C_PCI_DWIDTH-1:0] TXC_META_ADDR[7:0] TXC_META_LENGTH[8:0] TXC_META_ATTR[2:0] TXC_META_TC[2:0] TXC_META_TAG[8:0] TXC_META_REQUESTER_ID[15:0] TXC_META_EP TXC_DATA_START_FLAG TXC_DATA_END_FLAG TXC_DATA_VALID TXC_META_BYTE_COUNT[12:0] TXC_DATA_READY TXC_DATA_FDWBE[3:0] TXC_DATA_LDWBE[3:0] TXC_DATA_END_OFFSET[3:0] TXC_DATA_START_OFFSET[3:0] TXR_DATA_READY TXR_META_ADDR[63:0] TXR_DATA[C_PCI_DWIDTH-1:0] TXR_META_TYPE[3:0] TXR_META_ATTR[2:0] TXR_META_TAG[2:0] (Virtualized) TXR_META_LENGTH[9:0] TXR_META_EP TXR_DATA_VALID TXR_META_TC[2:0] TXR_DATA_LDWBE[3:0] TXR_DATA_FDWBE[3:0] TXR_DATA_START_FLAG TXR_DATA_END_FLAG TXR_DATA_END_OFFSET[3:0] TXR_DATA_START_OFFSET[3:0] RXR_DATA_FDWBE[3:0] RXR_DATA_LDWBE[3;0] RC CQ RQ CC