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//----------------------------------------------------------------------------
// Filename:			ff.v
// Version:				1.00.a
// Verilog Standard:	Verilog-2001
// Description:			A D/Q flip flop.
// Author:				Matt Jacobsen
// History:				@mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module ff
    (
     input      CLK,
     input      D,
     output reg Q
     );
    always @ (posedge CLK) begin 
	    Q <= #1 D; 
    end
endmodule